1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
50 static const u16 e1000_igp_2_cable_length_table[] =
51 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 ARRAY_SIZE(e1000_igp_2_cable_length_table)
62 #define BM_PHY_REG_PAGE(offset) \
63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
64 #define BM_PHY_REG_NUM(offset) \
65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
67 ~MAX_PHY_REG_ADDRESS)))
69 #define HV_INTC_FC_PAGE_START 768
70 #define I82578_ADDR_REG 29
71 #define I82577_ADDR_REG 16
72 #define I82577_CFG_REG 22
73 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
74 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
75 #define I82577_CTRL_REG 23
77 /* 82577 specific PHY registers */
78 #define I82577_PHY_CTRL_2 18
79 #define I82577_PHY_STATUS_2 26
80 #define I82577_PHY_DIAG_STATUS 31
82 /* I82577 PHY Status 2 */
83 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
84 #define I82577_PHY_STATUS2_MDIX 0x0800
85 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
86 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
88 /* I82577 PHY Control 2 */
89 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
90 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
92 /* I82577 PHY Diagnostics Status */
93 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
94 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
96 /* BM PHY Copper Specific Control 1 */
97 #define BM_CS_CTRL1 16
99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
100 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
101 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
105 * @hw: pointer to the HW structure
107 * Read the PHY management control register and check whether a PHY reset
108 * is blocked. If a reset is not blocked return 0, otherwise
109 * return E1000_BLK_PHY_RESET (12).
111 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
118 E1000_BLK_PHY_RESET : 0;
122 * e1000e_get_phy_id - Retrieve the PHY ID and revision
123 * @hw: pointer to the HW structure
125 * Reads the PHY registers and stores the PHY ID and possibly the PHY
126 * revision in the hardware structure.
128 s32 e1000e_get_phy_id(struct e1000_hw *hw)
130 struct e1000_phy_info *phy = &hw->phy;
135 if (!(phy->ops.read_reg))
138 while (retry_count < 2) {
139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
143 phy->id = (u32)(phy_id << 16);
145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
156 * If the PHY ID is still unknown, we may have an 82577
157 * without link. We will try again after setting Slow MDIC
158 * mode. No harm in trying again in this case since the PHY
159 * ID is unknown at this point anyway.
161 ret_val = phy->ops.acquire(hw);
164 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
167 phy->ops.release(hw);
172 /* Revert to MDIO fast mode, if applicable */
174 ret_val = phy->ops.acquire(hw);
177 ret_val = e1000_set_mdio_slow_mode_hv(hw, false);
178 phy->ops.release(hw);
185 * e1000e_phy_reset_dsp - Reset PHY DSP
186 * @hw: pointer to the HW structure
188 * Reset the digital signal processor.
190 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
194 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
198 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
202 * e1000e_read_phy_reg_mdic - Read MDI control register
203 * @hw: pointer to the HW structure
204 * @offset: register offset to be read
205 * @data: pointer to the read data
207 * Reads the MDI control register in the PHY at offset and stores the
208 * information read to data.
210 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
212 struct e1000_phy_info *phy = &hw->phy;
215 if (offset > MAX_PHY_REG_ADDRESS) {
216 e_dbg("PHY Address %d is out of range\n", offset);
217 return -E1000_ERR_PARAM;
221 * Set up Op-code, Phy Address, and register offset in the MDI
222 * Control register. The MAC will take care of interfacing with the
223 * PHY to retrieve the desired data.
225 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
226 (phy->addr << E1000_MDIC_PHY_SHIFT) |
227 (E1000_MDIC_OP_READ));
232 * Poll the ready bit to see if the MDI read completed
233 * Increasing the time out as testing showed failures with
236 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
239 if (mdic & E1000_MDIC_READY)
242 if (!(mdic & E1000_MDIC_READY)) {
243 e_dbg("MDI Read did not complete\n");
244 return -E1000_ERR_PHY;
246 if (mdic & E1000_MDIC_ERROR) {
247 e_dbg("MDI Error\n");
248 return -E1000_ERR_PHY;
256 * e1000e_write_phy_reg_mdic - Write MDI control register
257 * @hw: pointer to the HW structure
258 * @offset: register offset to write to
259 * @data: data to write to register at offset
261 * Writes data to MDI control register in the PHY at offset.
263 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
265 struct e1000_phy_info *phy = &hw->phy;
268 if (offset > MAX_PHY_REG_ADDRESS) {
269 e_dbg("PHY Address %d is out of range\n", offset);
270 return -E1000_ERR_PARAM;
274 * Set up Op-code, Phy Address, and register offset in the MDI
275 * Control register. The MAC will take care of interfacing with the
276 * PHY to retrieve the desired data.
278 mdic = (((u32)data) |
279 (offset << E1000_MDIC_REG_SHIFT) |
280 (phy->addr << E1000_MDIC_PHY_SHIFT) |
281 (E1000_MDIC_OP_WRITE));
286 * Poll the ready bit to see if the MDI read completed
287 * Increasing the time out as testing showed failures with
290 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
293 if (mdic & E1000_MDIC_READY)
296 if (!(mdic & E1000_MDIC_READY)) {
297 e_dbg("MDI Write did not complete\n");
298 return -E1000_ERR_PHY;
300 if (mdic & E1000_MDIC_ERROR) {
301 e_dbg("MDI Error\n");
302 return -E1000_ERR_PHY;
309 * e1000e_read_phy_reg_m88 - Read m88 PHY register
310 * @hw: pointer to the HW structure
311 * @offset: register offset to be read
312 * @data: pointer to the read data
314 * Acquires semaphore, if necessary, then reads the PHY register at offset
315 * and storing the retrieved information in data. Release any acquired
316 * semaphores before exiting.
318 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
322 ret_val = hw->phy.ops.acquire(hw);
326 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
329 hw->phy.ops.release(hw);
335 * e1000e_write_phy_reg_m88 - Write m88 PHY register
336 * @hw: pointer to the HW structure
337 * @offset: register offset to write to
338 * @data: data to write at register offset
340 * Acquires semaphore, if necessary, then writes the data to PHY register
341 * at the offset. Release any acquired semaphores before exiting.
343 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
347 ret_val = hw->phy.ops.acquire(hw);
351 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
354 hw->phy.ops.release(hw);
360 * __e1000e_read_phy_reg_igp - Read igp PHY register
361 * @hw: pointer to the HW structure
362 * @offset: register offset to be read
363 * @data: pointer to the read data
364 * @locked: semaphore has already been acquired or not
366 * Acquires semaphore, if necessary, then reads the PHY register at offset
367 * and stores the retrieved information in data. Release any acquired
368 * semaphores before exiting.
370 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
376 if (!(hw->phy.ops.acquire))
379 ret_val = hw->phy.ops.acquire(hw);
384 if (offset > MAX_PHY_MULTI_PAGE_REG) {
385 ret_val = e1000e_write_phy_reg_mdic(hw,
386 IGP01E1000_PHY_PAGE_SELECT,
392 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
397 hw->phy.ops.release(hw);
403 * e1000e_read_phy_reg_igp - Read igp PHY register
404 * @hw: pointer to the HW structure
405 * @offset: register offset to be read
406 * @data: pointer to the read data
408 * Acquires semaphore then reads the PHY register at offset and stores the
409 * retrieved information in data.
410 * Release the acquired semaphore before exiting.
412 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
414 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
418 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
419 * @hw: pointer to the HW structure
420 * @offset: register offset to be read
421 * @data: pointer to the read data
423 * Reads the PHY register at offset and stores the retrieved information
424 * in data. Assumes semaphore already acquired.
426 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
428 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
432 * e1000e_write_phy_reg_igp - Write igp PHY register
433 * @hw: pointer to the HW structure
434 * @offset: register offset to write to
435 * @data: data to write at register offset
436 * @locked: semaphore has already been acquired or not
438 * Acquires semaphore, if necessary, then writes the data to PHY register
439 * at the offset. Release any acquired semaphores before exiting.
441 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
447 if (!(hw->phy.ops.acquire))
450 ret_val = hw->phy.ops.acquire(hw);
455 if (offset > MAX_PHY_MULTI_PAGE_REG) {
456 ret_val = e1000e_write_phy_reg_mdic(hw,
457 IGP01E1000_PHY_PAGE_SELECT,
463 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
468 hw->phy.ops.release(hw);
475 * e1000e_write_phy_reg_igp - Write igp PHY register
476 * @hw: pointer to the HW structure
477 * @offset: register offset to write to
478 * @data: data to write at register offset
480 * Acquires semaphore then writes the data to PHY register
481 * at the offset. Release any acquired semaphores before exiting.
483 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
485 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
489 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
490 * @hw: pointer to the HW structure
491 * @offset: register offset to write to
492 * @data: data to write at register offset
494 * Writes the data to PHY register at the offset.
495 * Assumes semaphore already acquired.
497 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
499 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
503 * __e1000_read_kmrn_reg - Read kumeran register
504 * @hw: pointer to the HW structure
505 * @offset: register offset to be read
506 * @data: pointer to the read data
507 * @locked: semaphore has already been acquired or not
509 * Acquires semaphore, if necessary. Then reads the PHY register at offset
510 * using the kumeran interface. The information retrieved is stored in data.
511 * Release any acquired semaphores before exiting.
513 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
520 if (!(hw->phy.ops.acquire))
523 ret_val = hw->phy.ops.acquire(hw);
528 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
529 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
530 ew32(KMRNCTRLSTA, kmrnctrlsta);
534 kmrnctrlsta = er32(KMRNCTRLSTA);
535 *data = (u16)kmrnctrlsta;
538 hw->phy.ops.release(hw);
545 * e1000e_read_kmrn_reg - Read kumeran register
546 * @hw: pointer to the HW structure
547 * @offset: register offset to be read
548 * @data: pointer to the read data
550 * Acquires semaphore then reads the PHY register at offset using the
551 * kumeran interface. The information retrieved is stored in data.
552 * Release the acquired semaphore before exiting.
554 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
556 return __e1000_read_kmrn_reg(hw, offset, data, false);
560 * e1000e_read_kmrn_reg_locked - Read kumeran register
561 * @hw: pointer to the HW structure
562 * @offset: register offset to be read
563 * @data: pointer to the read data
565 * Reads the PHY register at offset using the kumeran interface. The
566 * information retrieved is stored in data.
567 * Assumes semaphore already acquired.
569 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
571 return __e1000_read_kmrn_reg(hw, offset, data, true);
575 * __e1000_write_kmrn_reg - Write kumeran register
576 * @hw: pointer to the HW structure
577 * @offset: register offset to write to
578 * @data: data to write at register offset
579 * @locked: semaphore has already been acquired or not
581 * Acquires semaphore, if necessary. Then write the data to PHY register
582 * at the offset using the kumeran interface. Release any acquired semaphores
585 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
592 if (!(hw->phy.ops.acquire))
595 ret_val = hw->phy.ops.acquire(hw);
600 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
601 E1000_KMRNCTRLSTA_OFFSET) | data;
602 ew32(KMRNCTRLSTA, kmrnctrlsta);
607 hw->phy.ops.release(hw);
614 * e1000e_write_kmrn_reg - Write kumeran register
615 * @hw: pointer to the HW structure
616 * @offset: register offset to write to
617 * @data: data to write at register offset
619 * Acquires semaphore then writes the data to the PHY register at the offset
620 * using the kumeran interface. Release the acquired semaphore before exiting.
622 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
624 return __e1000_write_kmrn_reg(hw, offset, data, false);
628 * e1000e_write_kmrn_reg_locked - Write kumeran register
629 * @hw: pointer to the HW structure
630 * @offset: register offset to write to
631 * @data: data to write at register offset
633 * Write the data to PHY register at the offset using the kumeran interface.
634 * Assumes semaphore already acquired.
636 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
638 return __e1000_write_kmrn_reg(hw, offset, data, true);
642 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
643 * @hw: pointer to the HW structure
645 * Sets up Carrier-sense on Transmit and downshift values.
647 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
649 struct e1000_phy_info *phy = &hw->phy;
653 /* Enable CRS on TX. This must be set for half-duplex operation. */
654 ret_val = phy->ops.read_reg(hw, I82577_CFG_REG, &phy_data);
658 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
660 /* Enable downshift */
661 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
663 ret_val = phy->ops.write_reg(hw, I82577_CFG_REG, phy_data);
670 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
671 * @hw: pointer to the HW structure
673 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
674 * and downshift values are set also.
676 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
678 struct e1000_phy_info *phy = &hw->phy;
682 /* Enable CRS on Tx. This must be set for half-duplex operation. */
683 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
687 /* For BM PHY this bit is downshift enable */
688 if (phy->type != e1000_phy_bm)
689 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
693 * MDI/MDI-X = 0 (default)
694 * 0 - Auto for all speeds
697 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
699 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
703 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
706 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
709 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
713 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
719 * disable_polarity_correction = 0 (default)
720 * Automatic Correction for Reversed Cable Polarity
724 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
725 if (phy->disable_polarity_correction == 1)
726 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
728 /* Enable downshift on BM (disabled by default) */
729 if (phy->type == e1000_phy_bm)
730 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
732 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
736 if ((phy->type == e1000_phy_m88) &&
737 (phy->revision < E1000_REVISION_4) &&
738 (phy->id != BME1000_E_PHY_ID_R2)) {
740 * Force TX_CLK in the Extended PHY Specific Control Register
743 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
747 phy_data |= M88E1000_EPSCR_TX_CLK_25;
749 if ((phy->revision == 2) &&
750 (phy->id == M88E1111_I_PHY_ID)) {
751 /* 82573L PHY - set the downshift counter to 5x. */
752 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
753 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
755 /* Configure Master and Slave downshift values */
756 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
757 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
758 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
759 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
761 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
766 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
767 /* Set PHY page 0, register 29 to 0x0003 */
768 ret_val = e1e_wphy(hw, 29, 0x0003);
772 /* Set PHY page 0, register 30 to 0x0000 */
773 ret_val = e1e_wphy(hw, 30, 0x0000);
778 /* Commit the changes. */
779 ret_val = e1000e_commit_phy(hw);
781 e_dbg("Error committing the PHY changes\n");
785 if (phy->type == e1000_phy_82578) {
786 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
791 /* 82578 PHY - set the downshift count to 1x. */
792 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
793 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
794 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
804 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
805 * @hw: pointer to the HW structure
807 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
810 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
812 struct e1000_phy_info *phy = &hw->phy;
816 ret_val = e1000_phy_hw_reset(hw);
818 e_dbg("Error resetting the PHY.\n");
823 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
824 * timeout issues when LFS is enabled.
828 /* disable lplu d0 during driver init */
829 ret_val = e1000_set_d0_lplu_state(hw, false);
831 e_dbg("Error Disabling LPLU D0\n");
834 /* Configure mdi-mdix settings */
835 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
839 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
843 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
846 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
850 data |= IGP01E1000_PSCR_AUTO_MDIX;
853 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
857 /* set auto-master slave resolution settings */
858 if (hw->mac.autoneg) {
860 * when autonegotiation advertisement is only 1000Mbps then we
861 * should disable SmartSpeed and enable Auto MasterSlave
862 * resolution as hardware default.
864 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
865 /* Disable SmartSpeed */
866 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
871 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
872 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
877 /* Set auto Master/Slave resolution process */
878 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
882 data &= ~CR_1000T_MS_ENABLE;
883 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
888 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
892 /* load defaults for future use */
893 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
894 ((data & CR_1000T_MS_VALUE) ?
895 e1000_ms_force_master :
896 e1000_ms_force_slave) :
899 switch (phy->ms_type) {
900 case e1000_ms_force_master:
901 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
903 case e1000_ms_force_slave:
904 data |= CR_1000T_MS_ENABLE;
905 data &= ~(CR_1000T_MS_VALUE);
908 data &= ~CR_1000T_MS_ENABLE;
912 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
919 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
920 * @hw: pointer to the HW structure
922 * Reads the MII auto-neg advertisement register and/or the 1000T control
923 * register and if the PHY is already setup for auto-negotiation, then
924 * return successful. Otherwise, setup advertisement and flow control to
925 * the appropriate values for the wanted auto-negotiation.
927 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
929 struct e1000_phy_info *phy = &hw->phy;
931 u16 mii_autoneg_adv_reg;
932 u16 mii_1000t_ctrl_reg = 0;
934 phy->autoneg_advertised &= phy->autoneg_mask;
936 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
937 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
941 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
942 /* Read the MII 1000Base-T Control Register (Address 9). */
943 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
949 * Need to parse both autoneg_advertised and fc and set up
950 * the appropriate PHY registers. First we will parse for
951 * autoneg_advertised software override. Since we can advertise
952 * a plethora of combinations, we need to check each bit
957 * First we clear all the 10/100 mb speed bits in the Auto-Neg
958 * Advertisement Register (Address 4) and the 1000 mb speed bits in
959 * the 1000Base-T Control Register (Address 9).
961 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
962 NWAY_AR_100TX_HD_CAPS |
963 NWAY_AR_10T_FD_CAPS |
964 NWAY_AR_10T_HD_CAPS);
965 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
967 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
969 /* Do we want to advertise 10 Mb Half Duplex? */
970 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
971 e_dbg("Advertise 10mb Half duplex\n");
972 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
975 /* Do we want to advertise 10 Mb Full Duplex? */
976 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
977 e_dbg("Advertise 10mb Full duplex\n");
978 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
981 /* Do we want to advertise 100 Mb Half Duplex? */
982 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
983 e_dbg("Advertise 100mb Half duplex\n");
984 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
987 /* Do we want to advertise 100 Mb Full Duplex? */
988 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
989 e_dbg("Advertise 100mb Full duplex\n");
990 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
993 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
994 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
995 e_dbg("Advertise 1000mb Half duplex request denied!\n");
997 /* Do we want to advertise 1000 Mb Full Duplex? */
998 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
999 e_dbg("Advertise 1000mb Full duplex\n");
1000 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1004 * Check for a software override of the flow control settings, and
1005 * setup the PHY advertisement registers accordingly. If
1006 * auto-negotiation is enabled, then software will have to set the
1007 * "PAUSE" bits to the correct value in the Auto-Negotiation
1008 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1011 * The possible values of the "fc" parameter are:
1012 * 0: Flow control is completely disabled
1013 * 1: Rx flow control is enabled (we can receive pause frames
1014 * but not send pause frames).
1015 * 2: Tx flow control is enabled (we can send pause frames
1016 * but we do not support receiving pause frames).
1017 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1018 * other: No software override. The flow control configuration
1019 * in the EEPROM is used.
1021 switch (hw->fc.current_mode) {
1024 * Flow control (Rx & Tx) is completely disabled by a
1025 * software over-ride.
1027 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1029 case e1000_fc_rx_pause:
1031 * Rx Flow control is enabled, and Tx Flow control is
1032 * disabled, by a software over-ride.
1034 * Since there really isn't a way to advertise that we are
1035 * capable of Rx Pause ONLY, we will advertise that we
1036 * support both symmetric and asymmetric Rx PAUSE. Later
1037 * (in e1000e_config_fc_after_link_up) we will disable the
1038 * hw's ability to send PAUSE frames.
1040 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1042 case e1000_fc_tx_pause:
1044 * Tx Flow control is enabled, and Rx Flow control is
1045 * disabled, by a software over-ride.
1047 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1048 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1052 * Flow control (both Rx and Tx) is enabled by a software
1055 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1058 e_dbg("Flow control param set incorrectly\n");
1059 ret_val = -E1000_ERR_CONFIG;
1063 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1067 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1069 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1070 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1077 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1078 * @hw: pointer to the HW structure
1080 * Performs initial bounds checking on autoneg advertisement parameter, then
1081 * configure to advertise the full capability. Setup the PHY to autoneg
1082 * and restart the negotiation process between the link partner. If
1083 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1085 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1087 struct e1000_phy_info *phy = &hw->phy;
1092 * Perform some bounds checking on the autoneg advertisement
1095 phy->autoneg_advertised &= phy->autoneg_mask;
1098 * If autoneg_advertised is zero, we assume it was not defaulted
1099 * by the calling code so we set to advertise full capability.
1101 if (phy->autoneg_advertised == 0)
1102 phy->autoneg_advertised = phy->autoneg_mask;
1104 e_dbg("Reconfiguring auto-neg advertisement params\n");
1105 ret_val = e1000_phy_setup_autoneg(hw);
1107 e_dbg("Error Setting up Auto-Negotiation\n");
1110 e_dbg("Restarting Auto-Neg\n");
1113 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1114 * the Auto Neg Restart bit in the PHY control register.
1116 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1120 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1121 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1126 * Does the user want to wait for Auto-Neg to complete here, or
1127 * check at a later time (for example, callback routine).
1129 if (phy->autoneg_wait_to_complete) {
1130 ret_val = e1000_wait_autoneg(hw);
1132 e_dbg("Error while waiting for "
1133 "autoneg to complete\n");
1138 hw->mac.get_link_status = 1;
1144 * e1000e_setup_copper_link - Configure copper link settings
1145 * @hw: pointer to the HW structure
1147 * Calls the appropriate function to configure the link for auto-neg or forced
1148 * speed and duplex. Then we check for link, once link is established calls
1149 * to configure collision distance and flow control are called. If link is
1150 * not established, we return -E1000_ERR_PHY (-2).
1152 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1157 if (hw->mac.autoneg) {
1159 * Setup autoneg and flow control advertisement and perform
1162 ret_val = e1000_copper_link_autoneg(hw);
1167 * PHY will be set to 10H, 10F, 100H or 100F
1168 * depending on user settings.
1170 e_dbg("Forcing Speed and Duplex\n");
1171 ret_val = e1000_phy_force_speed_duplex(hw);
1173 e_dbg("Error Forcing Speed and Duplex\n");
1179 * Check link status. Wait up to 100 microseconds for link to become
1182 ret_val = e1000e_phy_has_link_generic(hw,
1183 COPPER_LINK_UP_LIMIT,
1190 e_dbg("Valid link established!!!\n");
1191 e1000e_config_collision_dist(hw);
1192 ret_val = e1000e_config_fc_after_link_up(hw);
1194 e_dbg("Unable to establish link!!!\n");
1201 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1202 * @hw: pointer to the HW structure
1204 * Calls the PHY setup function to force speed and duplex. Clears the
1205 * auto-crossover to force MDI manually. Waits for link and returns
1206 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1208 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1210 struct e1000_phy_info *phy = &hw->phy;
1215 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1219 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1221 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1226 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1227 * forced whenever speed and duplex are forced.
1229 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1233 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1234 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1236 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1240 e_dbg("IGP PSCR: %X\n", phy_data);
1244 if (phy->autoneg_wait_to_complete) {
1245 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1247 ret_val = e1000e_phy_has_link_generic(hw,
1255 e_dbg("Link taking longer than expected.\n");
1258 ret_val = e1000e_phy_has_link_generic(hw,
1270 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1271 * @hw: pointer to the HW structure
1273 * Calls the PHY setup function to force speed and duplex. Clears the
1274 * auto-crossover to force MDI manually. Resets the PHY to commit the
1275 * changes. If time expires while waiting for link up, we reset the DSP.
1276 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1277 * successful completion, else return corresponding error code.
1279 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1281 struct e1000_phy_info *phy = &hw->phy;
1287 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1288 * forced whenever speed and duplex are forced.
1290 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1294 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1295 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1299 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1301 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1305 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1307 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1311 /* Reset the phy to commit changes. */
1312 ret_val = e1000e_commit_phy(hw);
1316 if (phy->autoneg_wait_to_complete) {
1317 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1319 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1325 if (hw->phy.type != e1000_phy_m88) {
1326 e_dbg("Link taking longer than expected.\n");
1329 * We didn't get link.
1330 * Reset the DSP and cross our fingers.
1332 ret_val = e1e_wphy(hw,
1333 M88E1000_PHY_PAGE_SELECT,
1337 ret_val = e1000e_phy_reset_dsp(hw);
1344 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1350 if (hw->phy.type != e1000_phy_m88)
1353 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1358 * Resetting the phy means we need to re-force TX_CLK in the
1359 * Extended PHY Specific Control Register to 25MHz clock from
1360 * the reset value of 2.5MHz.
1362 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1363 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1368 * In addition, we must re-enable CRS on Tx for both half and full
1371 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1375 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1376 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1382 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1383 * @hw: pointer to the HW structure
1385 * Forces the speed and duplex settings of the PHY.
1386 * This is a function pointer entry point only called by
1387 * PHY setup routines.
1389 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1391 struct e1000_phy_info *phy = &hw->phy;
1396 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1400 e1000e_phy_force_speed_duplex_setup(hw, &data);
1402 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1406 /* Disable MDI-X support for 10/100 */
1407 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1411 data &= ~IFE_PMC_AUTO_MDIX;
1412 data &= ~IFE_PMC_FORCE_MDIX;
1414 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1418 e_dbg("IFE PMC: %X\n", data);
1422 if (phy->autoneg_wait_to_complete) {
1423 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1425 ret_val = e1000e_phy_has_link_generic(hw,
1433 e_dbg("Link taking longer than expected.\n");
1436 ret_val = e1000e_phy_has_link_generic(hw,
1449 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1450 * @hw: pointer to the HW structure
1451 * @phy_ctrl: pointer to current value of PHY_CONTROL
1453 * Forces speed and duplex on the PHY by doing the following: disable flow
1454 * control, force speed/duplex on the MAC, disable auto speed detection,
1455 * disable auto-negotiation, configure duplex, configure speed, configure
1456 * the collision distance, write configuration to CTRL register. The
1457 * caller must write to the PHY_CONTROL register for these settings to
1460 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1462 struct e1000_mac_info *mac = &hw->mac;
1465 /* Turn off flow control when forcing speed/duplex */
1466 hw->fc.current_mode = e1000_fc_none;
1468 /* Force speed/duplex on the mac */
1470 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1471 ctrl &= ~E1000_CTRL_SPD_SEL;
1473 /* Disable Auto Speed Detection */
1474 ctrl &= ~E1000_CTRL_ASDE;
1476 /* Disable autoneg on the phy */
1477 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1479 /* Forcing Full or Half Duplex? */
1480 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1481 ctrl &= ~E1000_CTRL_FD;
1482 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1483 e_dbg("Half Duplex\n");
1485 ctrl |= E1000_CTRL_FD;
1486 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1487 e_dbg("Full Duplex\n");
1490 /* Forcing 10mb or 100mb? */
1491 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1492 ctrl |= E1000_CTRL_SPD_100;
1493 *phy_ctrl |= MII_CR_SPEED_100;
1494 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1495 e_dbg("Forcing 100mb\n");
1497 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1498 *phy_ctrl |= MII_CR_SPEED_10;
1499 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1500 e_dbg("Forcing 10mb\n");
1503 e1000e_config_collision_dist(hw);
1509 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1510 * @hw: pointer to the HW structure
1511 * @active: boolean used to enable/disable lplu
1513 * Success returns 0, Failure returns 1
1515 * The low power link up (lplu) state is set to the power management level D3
1516 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1517 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1518 * is used during Dx states where the power conservation is most important.
1519 * During driver activity, SmartSpeed should be enabled so performance is
1522 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1524 struct e1000_phy_info *phy = &hw->phy;
1528 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1533 data &= ~IGP02E1000_PM_D3_LPLU;
1534 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1538 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1539 * during Dx states where the power conservation is most
1540 * important. During driver activity we should enable
1541 * SmartSpeed, so performance is maintained.
1543 if (phy->smart_speed == e1000_smart_speed_on) {
1544 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1549 data |= IGP01E1000_PSCFR_SMART_SPEED;
1550 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1554 } else if (phy->smart_speed == e1000_smart_speed_off) {
1555 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1560 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1561 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1566 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1567 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1568 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1569 data |= IGP02E1000_PM_D3_LPLU;
1570 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1574 /* When LPLU is enabled, we should disable SmartSpeed */
1575 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1579 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1580 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1587 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1588 * @hw: pointer to the HW structure
1590 * Success returns 0, Failure returns 1
1592 * A downshift is detected by querying the PHY link health.
1594 s32 e1000e_check_downshift(struct e1000_hw *hw)
1596 struct e1000_phy_info *phy = &hw->phy;
1598 u16 phy_data, offset, mask;
1600 switch (phy->type) {
1602 case e1000_phy_gg82563:
1604 case e1000_phy_82578:
1605 offset = M88E1000_PHY_SPEC_STATUS;
1606 mask = M88E1000_PSSR_DOWNSHIFT;
1608 case e1000_phy_igp_2:
1609 case e1000_phy_igp_3:
1610 offset = IGP01E1000_PHY_LINK_HEALTH;
1611 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1614 /* speed downshift not supported */
1615 phy->speed_downgraded = false;
1619 ret_val = e1e_rphy(hw, offset, &phy_data);
1622 phy->speed_downgraded = (phy_data & mask);
1628 * e1000_check_polarity_m88 - Checks the polarity.
1629 * @hw: pointer to the HW structure
1631 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1633 * Polarity is determined based on the PHY specific status register.
1635 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1637 struct e1000_phy_info *phy = &hw->phy;
1641 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1644 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1645 ? e1000_rev_polarity_reversed
1646 : e1000_rev_polarity_normal;
1652 * e1000_check_polarity_igp - Checks the polarity.
1653 * @hw: pointer to the HW structure
1655 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1657 * Polarity is determined based on the PHY port status register, and the
1658 * current speed (since there is no polarity at 100Mbps).
1660 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1662 struct e1000_phy_info *phy = &hw->phy;
1664 u16 data, offset, mask;
1667 * Polarity is determined based on the speed of
1670 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1674 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1675 IGP01E1000_PSSR_SPEED_1000MBPS) {
1676 offset = IGP01E1000_PHY_PCS_INIT_REG;
1677 mask = IGP01E1000_PHY_POLARITY_MASK;
1680 * This really only applies to 10Mbps since
1681 * there is no polarity for 100Mbps (always 0).
1683 offset = IGP01E1000_PHY_PORT_STATUS;
1684 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1687 ret_val = e1e_rphy(hw, offset, &data);
1690 phy->cable_polarity = (data & mask)
1691 ? e1000_rev_polarity_reversed
1692 : e1000_rev_polarity_normal;
1698 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1699 * @hw: pointer to the HW structure
1701 * Polarity is determined on the polarity reversal feature being enabled.
1703 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1705 struct e1000_phy_info *phy = &hw->phy;
1707 u16 phy_data, offset, mask;
1710 * Polarity is determined based on the reversal feature being enabled.
1712 if (phy->polarity_correction) {
1713 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1714 mask = IFE_PESC_POLARITY_REVERSED;
1716 offset = IFE_PHY_SPECIAL_CONTROL;
1717 mask = IFE_PSC_FORCE_POLARITY;
1720 ret_val = e1e_rphy(hw, offset, &phy_data);
1723 phy->cable_polarity = (phy_data & mask)
1724 ? e1000_rev_polarity_reversed
1725 : e1000_rev_polarity_normal;
1731 * e1000_wait_autoneg - Wait for auto-neg completion
1732 * @hw: pointer to the HW structure
1734 * Waits for auto-negotiation to complete or for the auto-negotiation time
1735 * limit to expire, which ever happens first.
1737 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1742 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1743 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1744 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1747 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1750 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1756 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1763 * e1000e_phy_has_link_generic - Polls PHY for link
1764 * @hw: pointer to the HW structure
1765 * @iterations: number of times to poll for link
1766 * @usec_interval: delay between polling attempts
1767 * @success: pointer to whether polling was successful or not
1769 * Polls the PHY status register for link, 'iterations' number of times.
1771 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1772 u32 usec_interval, bool *success)
1777 for (i = 0; i < iterations; i++) {
1779 * Some PHYs require the PHY_STATUS register to be read
1780 * twice due to the link bit being sticky. No harm doing
1781 * it across the board.
1783 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1786 * If the first read fails, another entity may have
1787 * ownership of the resources, wait and try again to
1788 * see if they have relinquished the resources yet.
1790 udelay(usec_interval);
1791 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1794 if (phy_status & MII_SR_LINK_STATUS)
1796 if (usec_interval >= 1000)
1797 mdelay(usec_interval/1000);
1799 udelay(usec_interval);
1802 *success = (i < iterations);
1808 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1809 * @hw: pointer to the HW structure
1811 * Reads the PHY specific status register to retrieve the cable length
1812 * information. The cable length is determined by averaging the minimum and
1813 * maximum values to get the "average" cable length. The m88 PHY has four
1814 * possible cable length values, which are:
1815 * Register Value Cable Length
1819 * 3 110 - 140 meters
1822 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1824 struct e1000_phy_info *phy = &hw->phy;
1826 u16 phy_data, index;
1828 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1832 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1833 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1834 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1835 ret_val = -E1000_ERR_PHY;
1839 phy->min_cable_length = e1000_m88_cable_length_table[index];
1840 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1842 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1849 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1850 * @hw: pointer to the HW structure
1852 * The automatic gain control (agc) normalizes the amplitude of the
1853 * received signal, adjusting for the attenuation produced by the
1854 * cable. By reading the AGC registers, which represent the
1855 * combination of coarse and fine gain value, the value can be put
1856 * into a lookup table to obtain the approximate cable length
1859 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1861 struct e1000_phy_info *phy = &hw->phy;
1863 u16 phy_data, i, agc_value = 0;
1864 u16 cur_agc_index, max_agc_index = 0;
1865 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1866 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1867 {IGP02E1000_PHY_AGC_A,
1868 IGP02E1000_PHY_AGC_B,
1869 IGP02E1000_PHY_AGC_C,
1870 IGP02E1000_PHY_AGC_D};
1872 /* Read the AGC registers for all channels */
1873 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1874 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1879 * Getting bits 15:9, which represent the combination of
1880 * coarse and fine gain values. The result is a number
1881 * that can be put into the lookup table to obtain the
1882 * approximate cable length.
1884 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1885 IGP02E1000_AGC_LENGTH_MASK;
1887 /* Array index bound check. */
1888 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1889 (cur_agc_index == 0))
1890 return -E1000_ERR_PHY;
1892 /* Remove min & max AGC values from calculation. */
1893 if (e1000_igp_2_cable_length_table[min_agc_index] >
1894 e1000_igp_2_cable_length_table[cur_agc_index])
1895 min_agc_index = cur_agc_index;
1896 if (e1000_igp_2_cable_length_table[max_agc_index] <
1897 e1000_igp_2_cable_length_table[cur_agc_index])
1898 max_agc_index = cur_agc_index;
1900 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1903 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1904 e1000_igp_2_cable_length_table[max_agc_index]);
1905 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1907 /* Calculate cable length with the error range of +/- 10 meters. */
1908 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1909 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1910 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1912 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1918 * e1000e_get_phy_info_m88 - Retrieve PHY information
1919 * @hw: pointer to the HW structure
1921 * Valid for only copper links. Read the PHY status register (sticky read)
1922 * to verify that link is up. Read the PHY special control register to
1923 * determine the polarity and 10base-T extended distance. Read the PHY
1924 * special status register to determine MDI/MDIx and current speed. If
1925 * speed is 1000, then determine cable length, local and remote receiver.
1927 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1929 struct e1000_phy_info *phy = &hw->phy;
1934 if (phy->media_type != e1000_media_type_copper) {
1935 e_dbg("Phy info is only valid for copper media\n");
1936 return -E1000_ERR_CONFIG;
1939 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1944 e_dbg("Phy info is only valid if link is up\n");
1945 return -E1000_ERR_CONFIG;
1948 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1952 phy->polarity_correction = (phy_data &
1953 M88E1000_PSCR_POLARITY_REVERSAL);
1955 ret_val = e1000_check_polarity_m88(hw);
1959 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1963 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1965 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1966 ret_val = e1000_get_cable_length(hw);
1970 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1974 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1975 ? e1000_1000t_rx_status_ok
1976 : e1000_1000t_rx_status_not_ok;
1978 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1979 ? e1000_1000t_rx_status_ok
1980 : e1000_1000t_rx_status_not_ok;
1982 /* Set values to "undefined" */
1983 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1984 phy->local_rx = e1000_1000t_rx_status_undefined;
1985 phy->remote_rx = e1000_1000t_rx_status_undefined;
1992 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1993 * @hw: pointer to the HW structure
1995 * Read PHY status to determine if link is up. If link is up, then
1996 * set/determine 10base-T extended distance and polarity correction. Read
1997 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1998 * determine on the cable length, local and remote receiver.
2000 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2002 struct e1000_phy_info *phy = &hw->phy;
2007 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2012 e_dbg("Phy info is only valid if link is up\n");
2013 return -E1000_ERR_CONFIG;
2016 phy->polarity_correction = true;
2018 ret_val = e1000_check_polarity_igp(hw);
2022 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2026 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
2028 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2029 IGP01E1000_PSSR_SPEED_1000MBPS) {
2030 ret_val = e1000_get_cable_length(hw);
2034 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2038 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2039 ? e1000_1000t_rx_status_ok
2040 : e1000_1000t_rx_status_not_ok;
2042 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2043 ? e1000_1000t_rx_status_ok
2044 : e1000_1000t_rx_status_not_ok;
2046 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2047 phy->local_rx = e1000_1000t_rx_status_undefined;
2048 phy->remote_rx = e1000_1000t_rx_status_undefined;
2055 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2056 * @hw: pointer to the HW structure
2058 * Populates "phy" structure with various feature states.
2060 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2062 struct e1000_phy_info *phy = &hw->phy;
2067 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2072 e_dbg("Phy info is only valid if link is up\n");
2073 ret_val = -E1000_ERR_CONFIG;
2077 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2080 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2083 if (phy->polarity_correction) {
2084 ret_val = e1000_check_polarity_ife(hw);
2088 /* Polarity is forced */
2089 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2090 ? e1000_rev_polarity_reversed
2091 : e1000_rev_polarity_normal;
2094 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2098 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2100 /* The following parameters are undefined for 10/100 operation. */
2101 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2102 phy->local_rx = e1000_1000t_rx_status_undefined;
2103 phy->remote_rx = e1000_1000t_rx_status_undefined;
2110 * e1000e_phy_sw_reset - PHY software reset
2111 * @hw: pointer to the HW structure
2113 * Does a software reset of the PHY by reading the PHY control register and
2114 * setting/write the control register reset bit to the PHY.
2116 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2121 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2125 phy_ctrl |= MII_CR_RESET;
2126 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2136 * e1000e_phy_hw_reset_generic - PHY hardware reset
2137 * @hw: pointer to the HW structure
2139 * Verify the reset block is not blocking us from resetting. Acquire
2140 * semaphore (if necessary) and read/set/write the device control reset
2141 * bit in the PHY. Wait the appropriate delay time for the device to
2142 * reset and release the semaphore (if necessary).
2144 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2146 struct e1000_phy_info *phy = &hw->phy;
2150 ret_val = e1000_check_reset_block(hw);
2154 ret_val = phy->ops.acquire(hw);
2159 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2162 udelay(phy->reset_delay_us);
2169 phy->ops.release(hw);
2171 return e1000_get_phy_cfg_done(hw);
2175 * e1000e_get_cfg_done - Generic configuration done
2176 * @hw: pointer to the HW structure
2178 * Generic function to wait 10 milli-seconds for configuration to complete
2179 * and return success.
2181 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2188 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2189 * @hw: pointer to the HW structure
2191 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2193 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2195 e_dbg("Running IGP 3 PHY init script\n");
2197 /* PHY init IGP 3 */
2198 /* Enable rise/fall, 10-mode work in class-A */
2199 e1e_wphy(hw, 0x2F5B, 0x9018);
2200 /* Remove all caps from Replica path filter */
2201 e1e_wphy(hw, 0x2F52, 0x0000);
2202 /* Bias trimming for ADC, AFE and Driver (Default) */
2203 e1e_wphy(hw, 0x2FB1, 0x8B24);
2204 /* Increase Hybrid poly bias */
2205 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2206 /* Add 4% to Tx amplitude in Gig mode */
2207 e1e_wphy(hw, 0x2010, 0x10B0);
2208 /* Disable trimming (TTT) */
2209 e1e_wphy(hw, 0x2011, 0x0000);
2210 /* Poly DC correction to 94.6% + 2% for all channels */
2211 e1e_wphy(hw, 0x20DD, 0x249A);
2212 /* ABS DC correction to 95.9% */
2213 e1e_wphy(hw, 0x20DE, 0x00D3);
2214 /* BG temp curve trim */
2215 e1e_wphy(hw, 0x28B4, 0x04CE);
2216 /* Increasing ADC OPAMP stage 1 currents to max */
2217 e1e_wphy(hw, 0x2F70, 0x29E4);
2218 /* Force 1000 ( required for enabling PHY regs configuration) */
2219 e1e_wphy(hw, 0x0000, 0x0140);
2220 /* Set upd_freq to 6 */
2221 e1e_wphy(hw, 0x1F30, 0x1606);
2223 e1e_wphy(hw, 0x1F31, 0xB814);
2224 /* Disable adaptive fixed FFE (Default) */
2225 e1e_wphy(hw, 0x1F35, 0x002A);
2226 /* Enable FFE hysteresis */
2227 e1e_wphy(hw, 0x1F3E, 0x0067);
2228 /* Fixed FFE for short cable lengths */
2229 e1e_wphy(hw, 0x1F54, 0x0065);
2230 /* Fixed FFE for medium cable lengths */
2231 e1e_wphy(hw, 0x1F55, 0x002A);
2232 /* Fixed FFE for long cable lengths */
2233 e1e_wphy(hw, 0x1F56, 0x002A);
2234 /* Enable Adaptive Clip Threshold */
2235 e1e_wphy(hw, 0x1F72, 0x3FB0);
2236 /* AHT reset limit to 1 */
2237 e1e_wphy(hw, 0x1F76, 0xC0FF);
2238 /* Set AHT master delay to 127 msec */
2239 e1e_wphy(hw, 0x1F77, 0x1DEC);
2240 /* Set scan bits for AHT */
2241 e1e_wphy(hw, 0x1F78, 0xF9EF);
2242 /* Set AHT Preset bits */
2243 e1e_wphy(hw, 0x1F79, 0x0210);
2244 /* Change integ_factor of channel A to 3 */
2245 e1e_wphy(hw, 0x1895, 0x0003);
2246 /* Change prop_factor of channels BCD to 8 */
2247 e1e_wphy(hw, 0x1796, 0x0008);
2248 /* Change cg_icount + enable integbp for channels BCD */
2249 e1e_wphy(hw, 0x1798, 0xD008);
2251 * Change cg_icount + enable integbp + change prop_factor_master
2252 * to 8 for channel A
2254 e1e_wphy(hw, 0x1898, 0xD918);
2255 /* Disable AHT in Slave mode on channel A */
2256 e1e_wphy(hw, 0x187A, 0x0800);
2258 * Enable LPLU and disable AN to 1000 in non-D0a states,
2261 e1e_wphy(hw, 0x0019, 0x008D);
2262 /* Enable restart AN on an1000_dis change */
2263 e1e_wphy(hw, 0x001B, 0x2080);
2264 /* Enable wh_fifo read clock in 10/100 modes */
2265 e1e_wphy(hw, 0x0014, 0x0045);
2266 /* Restart AN, Speed selection is 1000 */
2267 e1e_wphy(hw, 0x0000, 0x1340);
2272 /* Internal function pointers */
2275 * e1000_get_phy_cfg_done - Generic PHY configuration done
2276 * @hw: pointer to the HW structure
2278 * Return success if silicon family did not implement a family specific
2279 * get_cfg_done function.
2281 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2283 if (hw->phy.ops.get_cfg_done)
2284 return hw->phy.ops.get_cfg_done(hw);
2290 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2291 * @hw: pointer to the HW structure
2293 * When the silicon family has not implemented a forced speed/duplex
2294 * function for the PHY, simply return 0.
2296 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2298 if (hw->phy.ops.force_speed_duplex)
2299 return hw->phy.ops.force_speed_duplex(hw);
2305 * e1000e_get_phy_type_from_id - Get PHY type from id
2306 * @phy_id: phy_id read from the phy
2308 * Returns the phy type from the id.
2310 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2312 enum e1000_phy_type phy_type = e1000_phy_unknown;
2315 case M88E1000_I_PHY_ID:
2316 case M88E1000_E_PHY_ID:
2317 case M88E1111_I_PHY_ID:
2318 case M88E1011_I_PHY_ID:
2319 phy_type = e1000_phy_m88;
2321 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2322 phy_type = e1000_phy_igp_2;
2324 case GG82563_E_PHY_ID:
2325 phy_type = e1000_phy_gg82563;
2327 case IGP03E1000_E_PHY_ID:
2328 phy_type = e1000_phy_igp_3;
2331 case IFE_PLUS_E_PHY_ID:
2332 case IFE_C_E_PHY_ID:
2333 phy_type = e1000_phy_ife;
2335 case BME1000_E_PHY_ID:
2336 case BME1000_E_PHY_ID_R2:
2337 phy_type = e1000_phy_bm;
2339 case I82578_E_PHY_ID:
2340 phy_type = e1000_phy_82578;
2342 case I82577_E_PHY_ID:
2343 phy_type = e1000_phy_82577;
2346 phy_type = e1000_phy_unknown;
2353 * e1000e_determine_phy_address - Determines PHY address.
2354 * @hw: pointer to the HW structure
2356 * This uses a trial and error method to loop through possible PHY
2357 * addresses. It tests each by reading the PHY ID registers and
2358 * checking for a match.
2360 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2362 s32 ret_val = -E1000_ERR_PHY_TYPE;
2365 enum e1000_phy_type phy_type = e1000_phy_unknown;
2367 hw->phy.id = phy_type;
2369 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2370 hw->phy.addr = phy_addr;
2374 e1000e_get_phy_id(hw);
2375 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2378 * If phy_type is valid, break - we found our
2381 if (phy_type != e1000_phy_unknown) {
2395 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2396 * @page: page to access
2398 * Returns the phy address for the page requested.
2400 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2404 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2411 * e1000e_write_phy_reg_bm - Write BM PHY register
2412 * @hw: pointer to the HW structure
2413 * @offset: register offset to write to
2414 * @data: data to write at register offset
2416 * Acquires semaphore, if necessary, then writes the data to PHY register
2417 * at the offset. Release any acquired semaphores before exiting.
2419 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2422 u32 page_select = 0;
2423 u32 page = offset >> IGP_PAGE_SHIFT;
2426 ret_val = hw->phy.ops.acquire(hw);
2430 /* Page 800 works differently than the rest so it has its own func */
2431 if (page == BM_WUC_PAGE) {
2432 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2437 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2439 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2441 * Page select is register 31 for phy address 1 and 22 for
2442 * phy address 2 and 3. Page select is shifted only for
2445 if (hw->phy.addr == 1) {
2446 page_shift = IGP_PAGE_SHIFT;
2447 page_select = IGP01E1000_PHY_PAGE_SELECT;
2450 page_select = BM_PHY_PAGE_SELECT;
2453 /* Page is shifted left, PHY expects (page x 32) */
2454 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2455 (page << page_shift));
2460 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2464 hw->phy.ops.release(hw);
2469 * e1000e_read_phy_reg_bm - Read BM PHY register
2470 * @hw: pointer to the HW structure
2471 * @offset: register offset to be read
2472 * @data: pointer to the read data
2474 * Acquires semaphore, if necessary, then reads the PHY register at offset
2475 * and storing the retrieved information in data. Release any acquired
2476 * semaphores before exiting.
2478 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2481 u32 page_select = 0;
2482 u32 page = offset >> IGP_PAGE_SHIFT;
2485 ret_val = hw->phy.ops.acquire(hw);
2489 /* Page 800 works differently than the rest so it has its own func */
2490 if (page == BM_WUC_PAGE) {
2491 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2496 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2498 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2500 * Page select is register 31 for phy address 1 and 22 for
2501 * phy address 2 and 3. Page select is shifted only for
2504 if (hw->phy.addr == 1) {
2505 page_shift = IGP_PAGE_SHIFT;
2506 page_select = IGP01E1000_PHY_PAGE_SELECT;
2509 page_select = BM_PHY_PAGE_SELECT;
2512 /* Page is shifted left, PHY expects (page x 32) */
2513 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2514 (page << page_shift));
2519 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2522 hw->phy.ops.release(hw);
2527 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2528 * @hw: pointer to the HW structure
2529 * @offset: register offset to be read
2530 * @data: pointer to the read data
2532 * Acquires semaphore, if necessary, then reads the PHY register at offset
2533 * and storing the retrieved information in data. Release any acquired
2534 * semaphores before exiting.
2536 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2539 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2541 ret_val = hw->phy.ops.acquire(hw);
2545 /* Page 800 works differently than the rest so it has its own func */
2546 if (page == BM_WUC_PAGE) {
2547 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2554 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2556 /* Page is shifted left, PHY expects (page x 32) */
2557 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2564 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2567 hw->phy.ops.release(hw);
2572 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2573 * @hw: pointer to the HW structure
2574 * @offset: register offset to write to
2575 * @data: data to write at register offset
2577 * Acquires semaphore, if necessary, then writes the data to PHY register
2578 * at the offset. Release any acquired semaphores before exiting.
2580 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2583 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2585 ret_val = hw->phy.ops.acquire(hw);
2589 /* Page 800 works differently than the rest so it has its own func */
2590 if (page == BM_WUC_PAGE) {
2591 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2598 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2599 /* Page is shifted left, PHY expects (page x 32) */
2600 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2607 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2611 hw->phy.ops.release(hw);
2616 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2617 * @hw: pointer to the HW structure
2618 * @offset: register offset to be read or written
2619 * @data: pointer to the data to read or write
2620 * @read: determines if operation is read or write
2622 * Acquires semaphore, if necessary, then reads the PHY register at offset
2623 * and storing the retrieved information in data. Release any acquired
2624 * semaphores before exiting. Note that procedure to read the wakeup
2625 * registers are different. It works as such:
2626 * 1) Set page 769, register 17, bit 2 = 1
2627 * 2) Set page to 800 for host (801 if we were manageability)
2628 * 3) Write the address using the address opcode (0x11)
2629 * 4) Read or write the data using the data opcode (0x12)
2630 * 5) Restore 769_17.2 to its original value
2632 * Assumes semaphore already acquired.
2634 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2635 u16 *data, bool read)
2638 u16 reg = BM_PHY_REG_NUM(offset);
2641 /* Gig must be disabled for MDIO accesses to page 800 */
2642 if ((hw->mac.type == e1000_pchlan) &&
2643 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2644 e_dbg("Attempting to access page 800 while gig enabled.\n");
2646 /* All operations in this function are phy address 1 */
2650 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2651 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2653 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, &phy_reg);
2655 e_dbg("Could not read PHY page 769\n");
2659 /* First clear bit 4 to avoid a power state change */
2660 phy_reg &= ~(BM_WUC_HOST_WU_BIT);
2661 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2663 e_dbg("Could not clear PHY page 769 bit 4\n");
2667 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2668 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG,
2669 phy_reg | BM_WUC_ENABLE_BIT);
2671 e_dbg("Could not write PHY page 769 bit 2\n");
2675 /* Select page 800 */
2676 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2677 (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2679 /* Write the page 800 offset value using opcode 0x11 */
2680 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2682 e_dbg("Could not write address opcode to page 800\n");
2687 /* Read the page 800 value using opcode 0x12 */
2688 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2691 /* Write the page 800 value using opcode 0x12 */
2692 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2697 e_dbg("Could not access data value from page 800\n");
2702 * Restore 769_17.2 to its original value
2705 e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2706 (BM_WUC_ENABLE_PAGE << IGP_PAGE_SHIFT));
2708 /* Clear 769_17.2 */
2709 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2711 e_dbg("Could not clear PHY page 769 bit 2\n");
2720 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2721 * @hw: pointer to the HW structure
2723 * In the case of a PHY power down to save power, or to turn off link during a
2724 * driver unload, or wake on lan is not enabled, restore the link to previous
2727 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2731 /* The PHY will retain its settings across a power down/up cycle */
2732 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2733 mii_reg &= ~MII_CR_POWER_DOWN;
2734 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2738 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2739 * @hw: pointer to the HW structure
2741 * In the case of a PHY power down to save power, or to turn off link during a
2742 * driver unload, or wake on lan is not enabled, restore the link to previous
2745 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2749 /* The PHY will retain its settings across a power down/up cycle */
2750 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2751 mii_reg |= MII_CR_POWER_DOWN;
2752 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2757 * e1000e_commit_phy - Soft PHY reset
2758 * @hw: pointer to the HW structure
2760 * Performs a soft PHY reset on those that apply. This is a function pointer
2761 * entry point called by drivers.
2763 s32 e1000e_commit_phy(struct e1000_hw *hw)
2765 if (hw->phy.ops.commit)
2766 return hw->phy.ops.commit(hw);
2772 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2773 * @hw: pointer to the HW structure
2774 * @active: boolean used to enable/disable lplu
2776 * Success returns 0, Failure returns 1
2778 * The low power link up (lplu) state is set to the power management level D0
2779 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2780 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2781 * is used during Dx states where the power conservation is most important.
2782 * During driver activity, SmartSpeed should be enabled so performance is
2783 * maintained. This is a function pointer entry point called by drivers.
2785 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2787 if (hw->phy.ops.set_d0_lplu_state)
2788 return hw->phy.ops.set_d0_lplu_state(hw, active);
2794 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2795 * @hw: pointer to the HW structure
2796 * @slow: true for slow mode, false for normal mode
2798 * Assumes semaphore already acquired.
2800 s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow)
2805 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
2807 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
2808 (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2812 ret_val = e1000e_write_phy_reg_mdic(hw, BM_CS_CTRL1,
2813 (0x2180 | (slow << 10)));
2817 /* dummy read when reverting to fast mode - throw away result */
2819 ret_val = e1000e_read_phy_reg_mdic(hw, BM_CS_CTRL1, &data);
2826 * __e1000_read_phy_reg_hv - Read HV PHY register
2827 * @hw: pointer to the HW structure
2828 * @offset: register offset to be read
2829 * @data: pointer to the read data
2830 * @locked: semaphore has already been acquired or not
2832 * Acquires semaphore, if necessary, then reads the PHY register at offset
2833 * and stores the retrieved information in data. Release any acquired
2834 * semaphore before exiting.
2836 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2840 u16 page = BM_PHY_REG_PAGE(offset);
2841 u16 reg = BM_PHY_REG_NUM(offset);
2842 bool in_slow_mode = false;
2845 ret_val = hw->phy.ops.acquire(hw);
2850 /* Workaround failure in MDIO access while cable is disconnected */
2851 if ((hw->phy.type == e1000_phy_82577) &&
2852 !(er32(STATUS) & E1000_STATUS_LU)) {
2853 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
2857 in_slow_mode = true;
2860 /* Page 800 works differently than the rest so it has its own func */
2861 if (page == BM_WUC_PAGE) {
2862 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2867 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2868 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2873 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2875 if (page == HV_INTC_FC_PAGE_START)
2878 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2879 u32 phy_addr = hw->phy.addr;
2883 /* Page is shifted left, PHY expects (page x 32) */
2884 ret_val = e1000e_write_phy_reg_mdic(hw,
2885 IGP01E1000_PHY_PAGE_SELECT,
2886 (page << IGP_PAGE_SHIFT));
2887 hw->phy.addr = phy_addr;
2893 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2896 /* Revert to MDIO fast mode, if applicable */
2897 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
2898 ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
2901 hw->phy.ops.release(hw);
2907 * e1000_read_phy_reg_hv - Read HV PHY register
2908 * @hw: pointer to the HW structure
2909 * @offset: register offset to be read
2910 * @data: pointer to the read data
2912 * Acquires semaphore then reads the PHY register at offset and stores
2913 * the retrieved information in data. Release the acquired semaphore
2916 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2918 return __e1000_read_phy_reg_hv(hw, offset, data, false);
2922 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2923 * @hw: pointer to the HW structure
2924 * @offset: register offset to be read
2925 * @data: pointer to the read data
2927 * Reads the PHY register at offset and stores the retrieved information
2928 * in data. Assumes semaphore already acquired.
2930 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2932 return __e1000_read_phy_reg_hv(hw, offset, data, true);
2936 * __e1000_write_phy_reg_hv - Write HV PHY register
2937 * @hw: pointer to the HW structure
2938 * @offset: register offset to write to
2939 * @data: data to write at register offset
2940 * @locked: semaphore has already been acquired or not
2942 * Acquires semaphore, if necessary, then writes the data to PHY register
2943 * at the offset. Release any acquired semaphores before exiting.
2945 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2949 u16 page = BM_PHY_REG_PAGE(offset);
2950 u16 reg = BM_PHY_REG_NUM(offset);
2951 bool in_slow_mode = false;
2954 ret_val = hw->phy.ops.acquire(hw);
2959 /* Workaround failure in MDIO access while cable is disconnected */
2960 if ((hw->phy.type == e1000_phy_82577) &&
2961 !(er32(STATUS) & E1000_STATUS_LU)) {
2962 ret_val = e1000_set_mdio_slow_mode_hv(hw, true);
2966 in_slow_mode = true;
2969 /* Page 800 works differently than the rest so it has its own func */
2970 if (page == BM_WUC_PAGE) {
2971 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset,
2976 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2977 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2982 hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2984 if (page == HV_INTC_FC_PAGE_START)
2988 * Workaround MDIO accesses being disabled after entering IEEE Power
2989 * Down (whenever bit 11 of the PHY Control register is set)
2991 if ((hw->phy.type == e1000_phy_82578) &&
2992 (hw->phy.revision >= 1) &&
2993 (hw->phy.addr == 2) &&
2994 ((MAX_PHY_REG_ADDRESS & reg) == 0) &&
2995 (data & (1 << 11))) {
2997 ret_val = e1000_access_phy_debug_regs_hv(hw, (1 << 6) | 0x3,
3003 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3004 u32 phy_addr = hw->phy.addr;
3008 /* Page is shifted left, PHY expects (page x 32) */
3009 ret_val = e1000e_write_phy_reg_mdic(hw,
3010 IGP01E1000_PHY_PAGE_SELECT,
3011 (page << IGP_PAGE_SHIFT));
3012 hw->phy.addr = phy_addr;
3018 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3022 /* Revert to MDIO fast mode, if applicable */
3023 if ((hw->phy.type == e1000_phy_82577) && in_slow_mode)
3024 ret_val |= e1000_set_mdio_slow_mode_hv(hw, false);
3027 hw->phy.ops.release(hw);
3033 * e1000_write_phy_reg_hv - Write HV PHY register
3034 * @hw: pointer to the HW structure
3035 * @offset: register offset to write to
3036 * @data: data to write at register offset
3038 * Acquires semaphore then writes the data to PHY register at the offset.
3039 * Release the acquired semaphores before exiting.
3041 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3043 return __e1000_write_phy_reg_hv(hw, offset, data, false);
3047 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3048 * @hw: pointer to the HW structure
3049 * @offset: register offset to write to
3050 * @data: data to write at register offset
3052 * Writes the data to PHY register at the offset. Assumes semaphore
3055 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3057 return __e1000_write_phy_reg_hv(hw, offset, data, true);
3061 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
3062 * @page: page to be accessed
3064 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3068 if (page >= HV_INTC_FC_PAGE_START)
3075 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3076 * @hw: pointer to the HW structure
3077 * @offset: register offset to be read or written
3078 * @data: pointer to the data to be read or written
3079 * @read: determines if operation is read or written
3081 * Reads the PHY register at offset and stores the retreived information
3082 * in data. Assumes semaphore already acquired. Note that the procedure
3083 * to read these regs uses the address port and data port to read/write.
3085 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3086 u16 *data, bool read)
3092 /* This takes care of the difference with desktop vs mobile phy */
3093 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3094 I82578_ADDR_REG : I82577_ADDR_REG;
3095 data_reg = addr_reg + 1;
3097 /* All operations in this function are phy address 2 */
3100 /* masking with 0x3F to remove the page from offset */
3101 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3103 e_dbg("Could not write PHY the HV address register\n");
3107 /* Read or write the data value next */
3109 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3111 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3114 e_dbg("Could not read data value from HV data register\n");
3123 * e1000_link_stall_workaround_hv - Si workaround
3124 * @hw: pointer to the HW structure
3126 * This function works around a Si bug where the link partner can get
3127 * a link up indication before the PHY does. If small packets are sent
3128 * by the link partner they can be placed in the packet buffer without
3129 * being properly accounted for by the PHY and will stall preventing
3130 * further packets from being received. The workaround is to clear the
3131 * packet buffer after the PHY detects link up.
3133 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3138 if (hw->phy.type != e1000_phy_82578)
3141 /* Do not apply workaround if in PHY loopback bit 14 set */
3142 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3143 if (data & PHY_CONTROL_LB)
3146 /* check if link is up and at 1Gbps */
3147 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3151 data &= BM_CS_STATUS_LINK_UP |
3152 BM_CS_STATUS_RESOLVED |
3153 BM_CS_STATUS_SPEED_MASK;
3155 if (data != (BM_CS_STATUS_LINK_UP |
3156 BM_CS_STATUS_RESOLVED |
3157 BM_CS_STATUS_SPEED_1000))
3162 /* flush the packets in the fifo buffer */
3163 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3164 HV_MUX_DATA_CTRL_GEN_TO_MAC |
3165 HV_MUX_DATA_CTRL_FORCE_SPEED);
3169 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3170 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3177 * e1000_check_polarity_82577 - Checks the polarity.
3178 * @hw: pointer to the HW structure
3180 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3182 * Polarity is determined based on the PHY specific status register.
3184 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3186 struct e1000_phy_info *phy = &hw->phy;
3190 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3193 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3194 ? e1000_rev_polarity_reversed
3195 : e1000_rev_polarity_normal;
3201 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3202 * @hw: pointer to the HW structure
3204 * Calls the PHY setup function to force speed and duplex. Clears the
3205 * auto-crossover to force MDI manually. Waits for link and returns
3206 * successful if link up is successful, else -E1000_ERR_PHY (-2).
3208 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3210 struct e1000_phy_info *phy = &hw->phy;
3215 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3219 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3221 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3226 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
3227 * forced whenever speed and duplex are forced.
3229 ret_val = phy->ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
3233 phy_data &= ~I82577_PHY_CTRL2_AUTO_MDIX;
3234 phy_data &= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX;
3236 ret_val = phy->ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
3240 e_dbg("I82577_PHY_CTRL_2: %X\n", phy_data);
3244 if (phy->autoneg_wait_to_complete) {
3245 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3247 ret_val = e1000e_phy_has_link_generic(hw,
3255 e_dbg("Link taking longer than expected.\n");
3258 ret_val = e1000e_phy_has_link_generic(hw,
3271 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3272 * @hw: pointer to the HW structure
3274 * Read PHY status to determine if link is up. If link is up, then
3275 * set/determine 10base-T extended distance and polarity correction. Read
3276 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3277 * determine on the cable length, local and remote receiver.
3279 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3281 struct e1000_phy_info *phy = &hw->phy;
3286 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3291 e_dbg("Phy info is only valid if link is up\n");
3292 ret_val = -E1000_ERR_CONFIG;
3296 phy->polarity_correction = true;
3298 ret_val = e1000_check_polarity_82577(hw);
3302 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3306 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
3308 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3309 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3310 ret_val = hw->phy.ops.get_cable_length(hw);
3314 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
3318 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3319 ? e1000_1000t_rx_status_ok
3320 : e1000_1000t_rx_status_not_ok;
3322 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3323 ? e1000_1000t_rx_status_ok
3324 : e1000_1000t_rx_status_not_ok;
3326 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3327 phy->local_rx = e1000_1000t_rx_status_undefined;
3328 phy->remote_rx = e1000_1000t_rx_status_undefined;
3336 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3337 * @hw: pointer to the HW structure
3339 * Reads the diagnostic status register and verifies result is valid before
3340 * placing it in the phy_cable_length field.
3342 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3344 struct e1000_phy_info *phy = &hw->phy;
3346 u16 phy_data, length;
3348 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3352 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3353 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3355 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3356 ret_val = -E1000_ERR_PHY;
3358 phy->cable_length = length;