drivers/net/e1000e/es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include "e1000.h"
  35
  36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
  40
  41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  44
  45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
  48
  49 #define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
  50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
  51
  52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  54
  55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  57
  58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  60 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  61 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  64
  65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  66 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  67                                                 /* 1=Reverse Auto-Negotiation */
  68
  69 /* MAC Specific Control Register (Page 2, Register 21) */
  70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  71 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  73 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  74 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  75
  76 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  77
  78 /* DSP Distance Register (Page 5, Register 26) */
  79 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  80                                                            1 = 50-80M
  81                                                            2 = 80-110M
  82                                                            3 = 110-140M
  83                                                            4 = >140M */
  84
  85 /* Kumeran Mode Control Register (Page 193, Register 16) */
  86 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  87
  88 /* Max number of times Kumeran read/write should be validated */
  89 #define GG82563_MAX_KMRN_RETRY  0x5
  90
  91 /* Power Management Control Register (Page 193, Register 20) */
  92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  93                                            /* 1=Enable SERDES Electrical Idle */
  94
  95 /* In-Band Control Register (Page 194, Register 18) */
  96 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  97
  98 /*
  99  * A table for the GG82563 cable length where the range is defined
 100  * with a lower bound at "index" and the upper bound at
 101  * "index + 5".
 102  */
 103 static const u16 e1000_gg82563_cable_length_table[] =
 104          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
 106                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
 107
 108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 116 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 117                                             u16 *data);
 118 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 119                                              u16 data);
 120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
 121
 122 /**
 123  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 124  *  @hw: pointer to the HW structure
 125  **/
 126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 127 {
 128         struct e1000_phy_info *phy = &hw->phy;
 129         s32 ret_val;
 130
 131         if (hw->phy.media_type != e1000_media_type_copper) {
 132                 phy->type       = e1000_phy_none;
 133                 return 0;
 134         } else {
 135                 phy->ops.power_up = e1000_power_up_phy_copper;
 136                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 137         }
 138
 139         phy->addr               = 1;
 140         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 141         phy->reset_delay_us      = 100;
 142         phy->type               = e1000_phy_gg82563;
 143
 144         /* This can only be done after all function pointers are setup. */
 145         ret_val = e1000e_get_phy_id(hw);
 146
 147         /* Verify phy id */
 148         if (phy->id != GG82563_E_PHY_ID)
 149                 return -E1000_ERR_PHY;
 150
 151         return ret_val;
 152 }
 153
 154 /**
 155  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 156  *  @hw: pointer to the HW structure
 157  **/
 158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 159 {
 160         struct e1000_nvm_info *nvm = &hw->nvm;
 161         u32 eecd = er32(EECD);
 162         u16 size;
 163
 164         nvm->opcode_bits        = 8;
 165         nvm->delay_usec  = 1;
 166         switch (nvm->override) {
 167         case e1000_nvm_override_spi_large:
 168                 nvm->page_size    = 32;
 169                 nvm->address_bits = 16;
 170                 break;
 171         case e1000_nvm_override_spi_small:
 172                 nvm->page_size    = 8;
 173                 nvm->address_bits = 8;
 174                 break;
 175         default:
 176                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 177                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 178                 break;
 179         }
 180
 181         nvm->type = e1000_nvm_eeprom_spi;
 182
 183         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 184                           E1000_EECD_SIZE_EX_SHIFT);
 185
 186         /*
 187          * Added to a constant, "size" becomes the left-shift value
 188          * for setting word_size.
 189          */
 190         size += NVM_WORD_SIZE_BASE_SHIFT;
 191
 192         /* EEPROM access above 16k is unsupported */
 193         if (size > 14)
 194                 size = 14;
 195         nvm->word_size  = 1 << size;
 196
 197         return 0;
 198 }
 199
 200 /**
 201  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 202  *  @hw: pointer to the HW structure
 203  **/
 204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
 205 {
 206         struct e1000_hw *hw = &adapter->hw;
 207         struct e1000_mac_info *mac = &hw->mac;
 208         struct e1000_mac_operations *func = &mac->ops;
 209
 210         /* Set media type */
 211         switch (adapter->pdev->device) {
 212         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 213                 hw->phy.media_type = e1000_media_type_internal_serdes;
 214                 break;
 215         default:
 216                 hw->phy.media_type = e1000_media_type_copper;
 217                 break;
 218         }
 219
 220         /* Set mta register count */
 221         mac->mta_reg_count = 128;
 222         /* Set rar entry count */
 223         mac->rar_entry_count = E1000_RAR_ENTRIES;
 224         /* Set if manageability features are enabled. */
 225         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
 226                         ? true : false;
 227         /* Adaptive IFS not supported */
 228         mac->adaptive_ifs = false;
 229
 230         /* check for link */
 231         switch (hw->phy.media_type) {
 232         case e1000_media_type_copper:
 233                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
 234                 func->check_for_link = e1000e_check_for_copper_link;
 235                 break;
 236         case e1000_media_type_fiber:
 237                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 238                 func->check_for_link = e1000e_check_for_fiber_link;
 239                 break;
 240         case e1000_media_type_internal_serdes:
 241                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 242                 func->check_for_link = e1000e_check_for_serdes_link;
 243                 break;
 244         default:
 245                 return -E1000_ERR_CONFIG;
 246                 break;
 247         }
 248
 249         /* set lan id for port to determine which phy lock to use */
 250         hw->mac.ops.set_lan_id(hw);
 251
 252         return 0;
 253 }
 254
 255 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 256 {
 257         struct e1000_hw *hw = &adapter->hw;
 258         s32 rc;
 259
 260         rc = e1000_init_mac_params_80003es2lan(adapter);
 261         if (rc)
 262                 return rc;
 263
 264         rc = e1000_init_nvm_params_80003es2lan(hw);
 265         if (rc)
 266                 return rc;
 267
 268         rc = e1000_init_phy_params_80003es2lan(hw);
 269         if (rc)
 270                 return rc;
 271
 272         return 0;
 273 }
 274
 275 /**
 276  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 277  *  @hw: pointer to the HW structure
 278  *
 279  *  A wrapper to acquire access rights to the correct PHY.
 280  **/
 281 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 282 {
 283         u16 mask;
 284
 285         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 286         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 287 }
 288
 289 /**
 290  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 291  *  @hw: pointer to the HW structure
 292  *
 293  *  A wrapper to release access rights to the correct PHY.
 294  **/
 295 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 296 {
 297         u16 mask;
 298
 299         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 300         e1000_release_swfw_sync_80003es2lan(hw, mask);
 301 }
 302
 303 /**
 304  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 305  *  @hw: pointer to the HW structure
 306  *
 307  *  Acquire the semaphore to access the Kumeran interface.
 308  *
 309  **/
 310 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 311 {
 312         u16 mask;
 313
 314         mask = E1000_SWFW_CSR_SM;
 315
 316         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 317 }
 318
 319 /**
 320  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 321  *  @hw: pointer to the HW structure
 322  *
 323  *  Release the semaphore used to access the Kumeran interface
 324  **/
 325 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 326 {
 327         u16 mask;
 328
 329         mask = E1000_SWFW_CSR_SM;
 330
 331         e1000_release_swfw_sync_80003es2lan(hw, mask);
 332 }
 333
 334 /**
 335  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 336  *  @hw: pointer to the HW structure
 337  *
 338  *  Acquire the semaphore to access the EEPROM.
 339  **/
 340 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 341 {
 342         s32 ret_val;
 343
 344         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 345         if (ret_val)
 346                 return ret_val;
 347
 348         ret_val = e1000e_acquire_nvm(hw);
 349
 350         if (ret_val)
 351                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 352
 353         return ret_val;
 354 }
 355
 356 /**
 357  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 358  *  @hw: pointer to the HW structure
 359  *
 360  *  Release the semaphore used to access the EEPROM.
 361  **/
 362 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 363 {
 364         e1000e_release_nvm(hw);
 365         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 366 }
 367
 368 /**
 369  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 370  *  @hw: pointer to the HW structure
 371  *  @mask: specifies which semaphore to acquire
 372  *
 373  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 374  *  will also specify which port we're acquiring the lock for.
 375  **/
 376 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 377 {
 378         u32 swfw_sync;
 379         u32 swmask = mask;
 380         u32 fwmask = mask << 16;
 381         s32 i = 0;
 382         s32 timeout = 50;
 383
 384         while (i < timeout) {
 385                 if (e1000e_get_hw_semaphore(hw))
 386                         return -E1000_ERR_SWFW_SYNC;
 387
 388                 swfw_sync = er32(SW_FW_SYNC);
 389                 if (!(swfw_sync & (fwmask | swmask)))
 390                         break;
 391
 392                 /*
 393                  * Firmware currently using resource (fwmask)
 394                  * or other software thread using resource (swmask)
 395                  */
 396                 e1000e_put_hw_semaphore(hw);
 397                 mdelay(5);
 398                 i++;
 399         }
 400
 401         if (i == timeout) {
 402                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 403                 return -E1000_ERR_SWFW_SYNC;
 404         }
 405
 406         swfw_sync |= swmask;
 407         ew32(SW_FW_SYNC, swfw_sync);
 408
 409         e1000e_put_hw_semaphore(hw);
 410
 411         return 0;
 412 }
 413
 414 /**
 415  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 416  *  @hw: pointer to the HW structure
 417  *  @mask: specifies which semaphore to acquire
 418  *
 419  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 420  *  will also specify which port we're releasing the lock for.
 421  **/
 422 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 423 {
 424         u32 swfw_sync;
 425
 426         while (e1000e_get_hw_semaphore(hw) != 0);
 427         /* Empty */
 428
 429         swfw_sync = er32(SW_FW_SYNC);
 430         swfw_sync &= ~mask;
 431         ew32(SW_FW_SYNC, swfw_sync);
 432
 433         e1000e_put_hw_semaphore(hw);
 434 }
 435
 436 /**
 437  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 438  *  @hw: pointer to the HW structure
 439  *  @offset: offset of the register to read
 440  *  @data: pointer to the data returned from the operation
 441  *
 442  *  Read the GG82563 PHY register.
 443  **/
 444 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 445                                                   u32 offset, u16 *data)
 446 {
 447         s32 ret_val;
 448         u32 page_select;
 449         u16 temp;
 450
 451         ret_val = e1000_acquire_phy_80003es2lan(hw);
 452         if (ret_val)
 453                 return ret_val;
 454
 455         /* Select Configuration Page */
 456         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 457                 page_select = GG82563_PHY_PAGE_SELECT;
 458         } else {
 459                 /*
 460                  * Use Alternative Page Select register to access
 461                  * registers 30 and 31
 462                  */
 463                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 464         }
 465
 466         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 467         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 468         if (ret_val) {
 469                 e1000_release_phy_80003es2lan(hw);
 470                 return ret_val;
 471         }
 472
 473         if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
 474                 /*
 475                  * The "ready" bit in the MDIC register may be incorrectly set
 476                  * before the device has completed the "Page Select" MDI
 477                  * transaction.  So we wait 200us after each MDI command...
 478                  */
 479                 udelay(200);
 480
 481                 /* ...and verify the command was successful. */
 482                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 483
 484                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 485                         ret_val = -E1000_ERR_PHY;
 486                         e1000_release_phy_80003es2lan(hw);
 487                         return ret_val;
 488                 }
 489
 490                 udelay(200);
 491
 492                 ret_val = e1000e_read_phy_reg_mdic(hw,
 493                                                   MAX_PHY_REG_ADDRESS & offset,
 494                                                   data);
 495
 496                 udelay(200);
 497         } else {
 498                 ret_val = e1000e_read_phy_reg_mdic(hw,
 499                                                   MAX_PHY_REG_ADDRESS & offset,
 500                                                   data);
 501         }
 502
 503         e1000_release_phy_80003es2lan(hw);
 504
 505         return ret_val;
 506 }
 507
 508 /**
 509  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 510  *  @hw: pointer to the HW structure
 511  *  @offset: offset of the register to read
 512  *  @data: value to write to the register
 513  *
 514  *  Write to the GG82563 PHY register.
 515  **/
 516 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 517                                                    u32 offset, u16 data)
 518 {
 519         s32 ret_val;
 520         u32 page_select;
 521         u16 temp;
 522
 523         ret_val = e1000_acquire_phy_80003es2lan(hw);
 524         if (ret_val)
 525                 return ret_val;
 526
 527         /* Select Configuration Page */
 528         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 529                 page_select = GG82563_PHY_PAGE_SELECT;
 530         } else {
 531                 /*
 532                  * Use Alternative Page Select register to access
 533                  * registers 30 and 31
 534                  */
 535                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 536         }
 537
 538         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 539         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 540         if (ret_val) {
 541                 e1000_release_phy_80003es2lan(hw);
 542                 return ret_val;
 543         }
 544
 545         if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
 546                 /*
 547                  * The "ready" bit in the MDIC register may be incorrectly set
 548                  * before the device has completed the "Page Select" MDI
 549                  * transaction.  So we wait 200us after each MDI command...
 550                  */
 551                 udelay(200);
 552
 553                 /* ...and verify the command was successful. */
 554                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 555
 556                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 557                         e1000_release_phy_80003es2lan(hw);
 558                         return -E1000_ERR_PHY;
 559                 }
 560
 561                 udelay(200);
 562
 563                 ret_val = e1000e_write_phy_reg_mdic(hw,
 564                                                   MAX_PHY_REG_ADDRESS & offset,
 565                                                   data);
 566
 567                 udelay(200);
 568         } else {
 569                 ret_val = e1000e_write_phy_reg_mdic(hw,
 570                                                   MAX_PHY_REG_ADDRESS & offset,
 571                                                   data);
 572         }
 573
 574         e1000_release_phy_80003es2lan(hw);
 575
 576         return ret_val;
 577 }
 578
 579 /**
 580  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 581  *  @hw: pointer to the HW structure
 582  *  @offset: offset of the register to read
 583  *  @words: number of words to write
 584  *  @data: buffer of data to write to the NVM
 585  *
 586  *  Write "words" of data to the ESB2 NVM.
 587  **/
 588 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 589                                        u16 words, u16 *data)
 590 {
 591         return e1000e_write_nvm_spi(hw, offset, words, data);
 592 }
 593
 594 /**
 595  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 596  *  @hw: pointer to the HW structure
 597  *
 598  *  Wait a specific amount of time for manageability processes to complete.
 599  *  This is a function pointer entry point called by the phy module.
 600  **/
 601 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 602 {
 603         s32 timeout = PHY_CFG_TIMEOUT;
 604         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 605
 606         if (hw->bus.func == 1)
 607                 mask = E1000_NVM_CFG_DONE_PORT_1;
 608
 609         while (timeout) {
 610                 if (er32(EEMNGCTL) & mask)
 611                         break;
 612                 msleep(1);
 613                 timeout--;
 614         }
 615         if (!timeout) {
 616                 e_dbg("MNG configuration cycle has not completed.\n");
 617                 return -E1000_ERR_RESET;
 618         }
 619
 620         return 0;
 621 }
 622
 623 /**
 624  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 625  *  @hw: pointer to the HW structure
 626  *
 627  *  Force the speed and duplex settings onto the PHY.  This is a
 628  *  function pointer entry point called by the phy module.
 629  **/
 630 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 631 {
 632         s32 ret_val;
 633         u16 phy_data;
 634         bool link;
 635
 636         /*
 637          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 638          * forced whenever speed and duplex are forced.
 639          */
 640         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 641         if (ret_val)
 642                 return ret_val;
 643
 644         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 645         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 646         if (ret_val)
 647                 return ret_val;
 648
 649         e_dbg("GG82563 PSCR: %X\n", phy_data);
 650
 651         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 652         if (ret_val)
 653                 return ret_val;
 654
 655         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 656
 657         /* Reset the phy to commit changes. */
 658         phy_data |= MII_CR_RESET;
 659
 660         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 661         if (ret_val)
 662                 return ret_val;
 663
 664         udelay(1);
 665
 666         if (hw->phy.autoneg_wait_to_complete) {
 667                 e_dbg("Waiting for forced speed/duplex link "
 668                          "on GG82563 phy.\n");
 669
 670                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 671                                                      100000, &link);
 672                 if (ret_val)
 673                         return ret_val;
 674
 675                 if (!link) {
 676                         /*
 677                          * We didn't get link.
 678                          * Reset the DSP and cross our fingers.
 679                          */
 680                         ret_val = e1000e_phy_reset_dsp(hw);
 681                         if (ret_val)
 682                                 return ret_val;
 683                 }
 684
 685                 /* Try once more */
 686                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 687                                                      100000, &link);
 688                 if (ret_val)
 689                         return ret_val;
 690         }
 691
 692         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 693         if (ret_val)
 694                 return ret_val;
 695
 696         /*
 697          * Resetting the phy means we need to verify the TX_CLK corresponds
 698          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 699          */
 700         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 701         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 702                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 703         else
 704                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 705
 706         /*
 707          * In addition, we must re-enable CRS on Tx for both half and full
 708          * duplex.
 709          */
 710         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 711         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 712
 713         return ret_val;
 714 }
 715
 716 /**
 717  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 718  *  @hw: pointer to the HW structure
 719  *
 720  *  Find the approximate cable length as measured by the GG82563 PHY.
 721  *  This is a function pointer entry point called by the phy module.
 722  **/
 723 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 724 {
 725         struct e1000_phy_info *phy = &hw->phy;
 726         s32 ret_val = 0;
 727         u16 phy_data, index;
 728
 729         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 730         if (ret_val)
 731                 goto out;
 732
 733         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 734
 735         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
 736                 ret_val = -E1000_ERR_PHY;
 737                 goto out;
 738         }
 739
 740         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 741         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 742
 743         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 744
 745 out:
 746         return ret_val;
 747 }
 748
 749 /**
 750  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 751  *  @hw: pointer to the HW structure
 752  *  @speed: pointer to speed buffer
 753  *  @duplex: pointer to duplex buffer
 754  *
 755  *  Retrieve the current speed and duplex configuration.
 756  **/
 757 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 758                                               u16 *duplex)
 759 {
 760         s32 ret_val;
 761
 762         if (hw->phy.media_type == e1000_media_type_copper) {
 763                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 764                                                                     speed,
 765                                                                     duplex);
 766                 hw->phy.ops.cfg_on_link_up(hw);
 767         } else {
 768                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 769                                                                   speed,
 770                                                                   duplex);
 771         }
 772
 773         return ret_val;
 774 }
 775
 776 /**
 777  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 778  *  @hw: pointer to the HW structure
 779  *
 780  *  Perform a global reset to the ESB2 controller.
 781  **/
 782 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 783 {
 784         u32 ctrl, icr;
 785         s32 ret_val;
 786
 787         /*
 788          * Prevent the PCI-E bus from sticking if there is no TLP connection
 789          * on the last TLP read/write transaction when MAC is reset.
 790          */
 791         ret_val = e1000e_disable_pcie_master(hw);
 792         if (ret_val)
 793                 e_dbg("PCI-E Master disable polling has failed.\n");
 794
 795         e_dbg("Masking off all interrupts\n");
 796         ew32(IMC, 0xffffffff);
 797
 798         ew32(RCTL, 0);
 799         ew32(TCTL, E1000_TCTL_PSP);
 800         e1e_flush();
 801
 802         msleep(10);
 803
 804         ctrl = er32(CTRL);
 805
 806         ret_val = e1000_acquire_phy_80003es2lan(hw);
 807         e_dbg("Issuing a global reset to MAC\n");
 808         ew32(CTRL, ctrl | E1000_CTRL_RST);
 809         e1000_release_phy_80003es2lan(hw);
 810
 811         ret_val = e1000e_get_auto_rd_done(hw);
 812         if (ret_val)
 813                 /* We don't want to continue accessing MAC registers. */
 814                 return ret_val;
 815
 816         /* Clear any pending interrupt events. */
 817         ew32(IMC, 0xffffffff);
 818         icr = er32(ICR);
 819
 820         ret_val = e1000_check_alt_mac_addr_generic(hw);
 821
 822         return ret_val;
 823 }
 824
 825 /**
 826  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 827  *  @hw: pointer to the HW structure
 828  *
 829  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 830  **/
 831 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 832 {
 833         struct e1000_mac_info *mac = &hw->mac;
 834         u32 reg_data;
 835         s32 ret_val;
 836         u16 i;
 837
 838         e1000_initialize_hw_bits_80003es2lan(hw);
 839
 840         /* Initialize identification LED */
 841         ret_val = e1000e_id_led_init(hw);
 842         if (ret_val)
 843                 e_dbg("Error initializing identification LED\n");
 844                 /* This is not fatal and we should not stop init due to this */
 845
 846         /* Disabling VLAN filtering */
 847         e_dbg("Initializing the IEEE VLAN\n");
 848         mac->ops.clear_vfta(hw);
 849
 850         /* Setup the receive address. */
 851         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 852
 853         /* Zero out the Multicast HASH table */
 854         e_dbg("Zeroing the MTA\n");
 855         for (i = 0; i < mac->mta_reg_count; i++)
 856                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 857
 858         /* Setup link and flow control */
 859         ret_val = e1000e_setup_link(hw);
 860
 861         /* Set the transmit descriptor write-back policy */
 862         reg_data = er32(TXDCTL(0));
 863         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 864                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 865         ew32(TXDCTL(0), reg_data);
 866
 867         /* ...for both queues. */
 868         reg_data = er32(TXDCTL(1));
 869         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 870                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 871         ew32(TXDCTL(1), reg_data);
 872
 873         /* Enable retransmit on late collisions */
 874         reg_data = er32(TCTL);
 875         reg_data |= E1000_TCTL_RTLC;
 876         ew32(TCTL, reg_data);
 877
 878         /* Configure Gigabit Carry Extend Padding */
 879         reg_data = er32(TCTL_EXT);
 880         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 881         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 882         ew32(TCTL_EXT, reg_data);
 883
 884         /* Configure Transmit Inter-Packet Gap */
 885         reg_data = er32(TIPG);
 886         reg_data &= ~E1000_TIPG_IPGT_MASK;
 887         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 888         ew32(TIPG, reg_data);
 889
 890         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 891         reg_data &= ~0x00100000;
 892         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 893
 894         /* default to true to enable the MDIC W/A */
 895         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 896
 897         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
 898                                       E1000_KMRNCTRLSTA_OFFSET >>
 899                                       E1000_KMRNCTRLSTA_OFFSET_SHIFT,
 900                                       &i);
 901         if (!ret_val) {
 902                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 903                      E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 904                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 905         }
 906
 907         /*
 908          * Clear all of the statistics registers (clear on read).  It is
 909          * important that we do this after we have tried to establish link
 910          * because the symbol error count will increment wildly if there
 911          * is no link.
 912          */
 913         e1000_clear_hw_cntrs_80003es2lan(hw);
 914
 915         return ret_val;
 916 }
 917
 918 /**
 919  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 920  *  @hw: pointer to the HW structure
 921  *
 922  *  Initializes required hardware-dependent bits needed for normal operation.
 923  **/
 924 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 925 {
 926         u32 reg;
 927
 928         /* Transmit Descriptor Control 0 */
 929         reg = er32(TXDCTL(0));
 930         reg |= (1 << 22);
 931         ew32(TXDCTL(0), reg);
 932
 933         /* Transmit Descriptor Control 1 */
 934         reg = er32(TXDCTL(1));
 935         reg |= (1 << 22);
 936         ew32(TXDCTL(1), reg);
 937
 938         /* Transmit Arbitration Control 0 */
 939         reg = er32(TARC(0));
 940         reg &= ~(0xF << 27); /* 30:27 */
 941         if (hw->phy.media_type != e1000_media_type_copper)
 942                 reg &= ~(1 << 20);
 943         ew32(TARC(0), reg);
 944
 945         /* Transmit Arbitration Control 1 */
 946         reg = er32(TARC(1));
 947         if (er32(TCTL) & E1000_TCTL_MULR)
 948                 reg &= ~(1 << 28);
 949         else
 950                 reg |= (1 << 28);
 951         ew32(TARC(1), reg);
 952 }
 953
 954 /**
 955  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 956  *  @hw: pointer to the HW structure
 957  *
 958  *  Setup some GG82563 PHY registers for obtaining link
 959  **/
 960 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 961 {
 962         struct e1000_phy_info *phy = &hw->phy;
 963         s32 ret_val;
 964         u32 ctrl_ext;
 965         u16 data;
 966
 967         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 968         if (ret_val)
 969                 return ret_val;
 970
 971         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 972         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 973         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 974
 975         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 976         if (ret_val)
 977                 return ret_val;
 978
 979         /*
 980          * Options:
 981          *   MDI/MDI-X = 0 (default)
 982          *   0 - Auto for all speeds
 983          *   1 - MDI mode
 984          *   2 - MDI-X mode
 985          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 986          */
 987         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 988         if (ret_val)
 989                 return ret_val;
 990
 991         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 992
 993         switch (phy->mdix) {
 994         case 1:
 995                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 996                 break;
 997         case 2:
 998                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 999                 break;
1000         case 0:
1001         default:
1002                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1003                 break;
1004         }
1005
1006         /*
1007          * Options:
1008          *   disable_polarity_correction = 0 (default)
1009          *       Automatic Correction for Reversed Cable Polarity
1010          *   0 - Disabled
1011          *   1 - Enabled
1012          */
1013         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1014         if (phy->disable_polarity_correction)
1015                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1016
1017         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1018         if (ret_val)
1019                 return ret_val;
1020
1021         /* SW Reset the PHY so all changes take effect */
1022         ret_val = e1000e_commit_phy(hw);
1023         if (ret_val) {
1024                 e_dbg("Error Resetting the PHY\n");
1025                 return ret_val;
1026         }
1027
1028         /* Bypass Rx and Tx FIFO's */
1029         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1030                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1031                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1032                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1033         if (ret_val)
1034                 return ret_val;
1035
1036         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1037                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1038                                        &data);
1039         if (ret_val)
1040                 return ret_val;
1041         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1042         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1043                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1044                                         data);
1045         if (ret_val)
1046                 return ret_val;
1047
1048         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1049         if (ret_val)
1050                 return ret_val;
1051
1052         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1053         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1054         if (ret_val)
1055                 return ret_val;
1056
1057         ctrl_ext = er32(CTRL_EXT);
1058         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1059         ew32(CTRL_EXT, ctrl_ext);
1060
1061         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1062         if (ret_val)
1063                 return ret_val;
1064
1065         /*
1066          * Do not init these registers when the HW is in IAMT mode, since the
1067          * firmware will have already initialized them.  We only initialize
1068          * them if the HW is not in IAMT mode.
1069          */
1070         if (!e1000e_check_mng_mode(hw)) {
1071                 /* Enable Electrical Idle on the PHY */
1072                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1073                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1074                 if (ret_val)
1075                         return ret_val;
1076
1077                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1078                 if (ret_val)
1079                         return ret_val;
1080
1081                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1082                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1083                 if (ret_val)
1084                         return ret_val;
1085         }
1086
1087         /*
1088          * Workaround: Disable padding in Kumeran interface in the MAC
1089          * and in the PHY to avoid CRC errors.
1090          */
1091         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1092         if (ret_val)
1093                 return ret_val;
1094
1095         data |= GG82563_ICR_DIS_PADDING;
1096         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1097         if (ret_val)
1098                 return ret_val;
1099
1100         return 0;
1101 }
1102
1103 /**
1104  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1105  *  @hw: pointer to the HW structure
1106  *
1107  *  Essentially a wrapper for setting up all things "copper" related.
1108  *  This is a function pointer entry point called by the mac module.
1109  **/
1110 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1111 {
1112         u32 ctrl;
1113         s32 ret_val;
1114         u16 reg_data;
1115
1116         ctrl = er32(CTRL);
1117         ctrl |= E1000_CTRL_SLU;
1118         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1119         ew32(CTRL, ctrl);
1120
1121         /*
1122          * Set the mac to wait the maximum time between each
1123          * iteration and increase the max iterations when
1124          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1125          */
1126         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1127                                                    0xFFFF);
1128         if (ret_val)
1129                 return ret_val;
1130         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1131                                                   &reg_data);
1132         if (ret_val)
1133                 return ret_val;
1134         reg_data |= 0x3F;
1135         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1136                                                    reg_data);
1137         if (ret_val)
1138                 return ret_val;
1139         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1140                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1141                                       &reg_data);
1142         if (ret_val)
1143                 return ret_val;
1144         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1145         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1146                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1147                                         reg_data);
1148         if (ret_val)
1149                 return ret_val;
1150
1151         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1152         if (ret_val)
1153                 return ret_val;
1154
1155         ret_val = e1000e_setup_copper_link(hw);
1156
1157         return 0;
1158 }
1159
1160 /**
1161  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1162  *  @hw: pointer to the HW structure
1163  *  @duplex: current duplex setting
1164  *
1165  *  Configure the KMRN interface by applying last minute quirks for
1166  *  10/100 operation.
1167  **/
1168 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1169 {
1170         s32 ret_val = 0;
1171         u16 speed;
1172         u16 duplex;
1173
1174         if (hw->phy.media_type == e1000_media_type_copper) {
1175                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1176                                                              &duplex);
1177                 if (ret_val)
1178                         return ret_val;
1179
1180                 if (speed == SPEED_1000)
1181                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1182                 else
1183                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1184         }
1185
1186         return ret_val;
1187 }
1188
1189 /**
1190  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1191  *  @hw: pointer to the HW structure
1192  *  @duplex: current duplex setting
1193  *
1194  *  Configure the KMRN interface by applying last minute quirks for
1195  *  10/100 operation.
1196  **/
1197 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1198 {
1199         s32 ret_val;
1200         u32 tipg;
1201         u32 i = 0;
1202         u16 reg_data, reg_data2;
1203
1204         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1205         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1206                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1207                                        reg_data);
1208         if (ret_val)
1209                 return ret_val;
1210
1211         /* Configure Transmit Inter-Packet Gap */
1212         tipg = er32(TIPG);
1213         tipg &= ~E1000_TIPG_IPGT_MASK;
1214         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1215         ew32(TIPG, tipg);
1216
1217         do {
1218                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1219                 if (ret_val)
1220                         return ret_val;
1221
1222                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1223                 if (ret_val)
1224                         return ret_val;
1225                 i++;
1226         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1227
1228         if (duplex == HALF_DUPLEX)
1229                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1230         else
1231                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1232
1233         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1234
1235         return 0;
1236 }
1237
1238 /**
1239  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1240  *  @hw: pointer to the HW structure
1241  *
1242  *  Configure the KMRN interface by applying last minute quirks for
1243  *  gigabit operation.
1244  **/
1245 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1246 {
1247         s32 ret_val;
1248         u16 reg_data, reg_data2;
1249         u32 tipg;
1250         u32 i = 0;
1251
1252         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1253         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1254                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1255                                        reg_data);
1256         if (ret_val)
1257                 return ret_val;
1258
1259         /* Configure Transmit Inter-Packet Gap */
1260         tipg = er32(TIPG);
1261         tipg &= ~E1000_TIPG_IPGT_MASK;
1262         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1263         ew32(TIPG, tipg);
1264
1265         do {
1266                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1267                 if (ret_val)
1268                         return ret_val;
1269
1270                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1271                 if (ret_val)
1272                         return ret_val;
1273                 i++;
1274         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1275
1276         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1277         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1278
1279         return ret_val;
1280 }
1281
1282 /**
1283  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1284  *  @hw: pointer to the HW structure
1285  *  @offset: register offset to be read
1286  *  @data: pointer to the read data
1287  *
1288  *  Acquire semaphore, then read the PHY register at offset
1289  *  using the kumeran interface.  The information retrieved is stored in data.
1290  *  Release the semaphore before exiting.
1291  **/
1292 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1293                                            u16 *data)
1294 {
1295         u32 kmrnctrlsta;
1296         s32 ret_val = 0;
1297
1298         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1299         if (ret_val)
1300                 return ret_val;
1301
1302         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1303                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1304         ew32(KMRNCTRLSTA, kmrnctrlsta);
1305
1306         udelay(2);
1307
1308         kmrnctrlsta = er32(KMRNCTRLSTA);
1309         *data = (u16)kmrnctrlsta;
1310
1311         e1000_release_mac_csr_80003es2lan(hw);
1312
1313         return ret_val;
1314 }
1315
1316 /**
1317  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1318  *  @hw: pointer to the HW structure
1319  *  @offset: register offset to write to
1320  *  @data: data to write at register offset
1321  *
1322  *  Acquire semaphore, then write the data to PHY register
1323  *  at the offset using the kumeran interface.  Release semaphore
1324  *  before exiting.
1325  **/
1326 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1327                                             u16 data)
1328 {
1329         u32 kmrnctrlsta;
1330         s32 ret_val = 0;
1331
1332         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1333         if (ret_val)
1334                 return ret_val;
1335
1336         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1337                        E1000_KMRNCTRLSTA_OFFSET) | data;
1338         ew32(KMRNCTRLSTA, kmrnctrlsta);
1339
1340         udelay(2);
1341
1342         e1000_release_mac_csr_80003es2lan(hw);
1343
1344         return ret_val;
1345 }
1346
1347 /**
1348  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1349  *  @hw: pointer to the HW structure
1350  **/
1351 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1352 {
1353         s32 ret_val = 0;
1354
1355         /*
1356          * If there's an alternate MAC address place it in RAR0
1357          * so that it will override the Si installed default perm
1358          * address.
1359          */
1360         ret_val = e1000_check_alt_mac_addr_generic(hw);
1361         if (ret_val)
1362                 goto out;
1363
1364         ret_val = e1000_read_mac_addr_generic(hw);
1365
1366 out:
1367         return ret_val;
1368 }
1369
1370 /**
1371  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1372  * @hw: pointer to the HW structure
1373  *
1374  * In the case of a PHY power down to save power, or to turn off link during a
1375  * driver unload, or wake on lan is not enabled, remove the link.
1376  **/
1377 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1378 {
1379         /* If the management interface is not enabled, then power down */
1380         if (!(hw->mac.ops.check_mng_mode(hw) ||
1381               hw->phy.ops.check_reset_block(hw)))
1382                 e1000_power_down_phy_copper(hw);
1383
1384         return;
1385 }
1386
1387 /**
1388  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1389  *  @hw: pointer to the HW structure
1390  *
1391  *  Clears the hardware counters by reading the counter registers.
1392  **/
1393 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1394 {
1395         e1000e_clear_hw_cntrs_base(hw);
1396
1397         er32(PRC64);
1398         er32(PRC127);
1399         er32(PRC255);
1400         er32(PRC511);
1401         er32(PRC1023);
1402         er32(PRC1522);
1403         er32(PTC64);
1404         er32(PTC127);
1405         er32(PTC255);
1406         er32(PTC511);
1407         er32(PTC1023);
1408         er32(PTC1522);
1409
1410         er32(ALGNERRC);
1411         er32(RXERRC);
1412         er32(TNCRS);
1413         er32(CEXTERR);
1414         er32(TSCTC);
1415         er32(TSCTFC);
1416
1417         er32(MGTPRC);
1418         er32(MGTPDC);
1419         er32(MGTPTC);
1420
1421         er32(IAC);
1422         er32(ICRXOC);
1423
1424         er32(ICRXPTC);
1425         er32(ICRXATC);
1426         er32(ICTXPTC);
1427         er32(ICTXATC);
1428         er32(ICTXQEC);
1429         er32(ICTXQMTC);
1430         er32(ICRXDMTC);
1431 }
1432
1433 static struct e1000_mac_operations es2_mac_ops = {
1434         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1435         .id_led_init            = e1000e_id_led_init,
1436         .check_mng_mode         = e1000e_check_mng_mode_generic,
1437         /* check_for_link dependent on media type */
1438         .cleanup_led            = e1000e_cleanup_led_generic,
1439         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1440         .get_bus_info           = e1000e_get_bus_info_pcie,
1441         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1442         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1443         .led_on                 = e1000e_led_on_generic,
1444         .led_off                = e1000e_led_off_generic,
1445         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1446         .write_vfta             = e1000_write_vfta_generic,
1447         .clear_vfta             = e1000_clear_vfta_generic,
1448         .reset_hw               = e1000_reset_hw_80003es2lan,
1449         .init_hw                = e1000_init_hw_80003es2lan,
1450         .setup_link             = e1000e_setup_link,
1451         /* setup_physical_interface dependent on media type */
1452         .setup_led              = e1000e_setup_led_generic,
1453 };
1454
1455 static struct e1000_phy_operations es2_phy_ops = {
1456         .acquire                = e1000_acquire_phy_80003es2lan,
1457         .check_polarity         = e1000_check_polarity_m88,
1458         .check_reset_block      = e1000e_check_reset_block_generic,
1459         .commit                 = e1000e_phy_sw_reset,
1460         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1461         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1462         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1463         .get_info               = e1000e_get_phy_info_m88,
1464         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1465         .release                = e1000_release_phy_80003es2lan,
1466         .reset                  = e1000e_phy_hw_reset_generic,
1467         .set_d0_lplu_state      = NULL,
1468         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1469         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1470         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1471 };
1472
1473 static struct e1000_nvm_operations es2_nvm_ops = {
1474         .acquire                = e1000_acquire_nvm_80003es2lan,
1475         .read                   = e1000e_read_nvm_eerd,
1476         .release                = e1000_release_nvm_80003es2lan,
1477         .update                 = e1000e_update_nvm_checksum_generic,
1478         .valid_led_default      = e1000e_valid_led_default,
1479         .validate               = e1000e_validate_nvm_checksum_generic,
1480         .write                  = e1000_write_nvm_80003es2lan,
1481 };
1482
1483 struct e1000_info e1000_es2_info = {
1484         .mac                    = e1000_80003es2lan,
1485         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1486                                   | FLAG_HAS_JUMBO_FRAMES
1487                                   | FLAG_HAS_WOL
1488                                   | FLAG_APME_IN_CTRL3
1489                                   | FLAG_RX_CSUM_ENABLED
1490                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1491                                   | FLAG_RX_NEEDS_RESTART /* errata */
1492                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1493                                   | FLAG_APME_CHECK_PORT_B
1494                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1495                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1496         .pba                    = 38,
1497         .max_hw_frame_size      = DEFAULT_JUMBO,
1498         .get_variants           = e1000_get_variants_80003es2lan,
1499         .mac_ops                = &es2_mac_ops,
1500         .phy_ops                = &es2_phy_ops,
1501         .nvm_ops                = &es2_nvm_ops,
1502 };
1503