1 /* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/string.h>
19 #include <linux/timer.h>
20 #include <linux/errno.h>
21 #include <linux/ioport.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/init.h>
29 #include <linux/crc32.h>
30 #include <linux/ethtool.h>
31 #include <linux/bitops.h>
32 #include <asm/processor.h> /* Processor type for cache alignment. */
34 #include <asm/uaccess.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/time.h>
38 #define TX_RING_SIZE 256
39 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used.*/
40 #define RX_RING_SIZE 256
41 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
42 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
44 /* This driver was written to use PCI memory space, however x86-oriented
45 hardware often uses I/O space accesses. */
61 /* Offsets to the device registers.
62 Unlike software-only systems, device drivers interact with complex hardware.
63 It's not useful to define symbolic names for every register bit in the
64 device. The name can only partially document the semantics and make
65 the driver longer and more difficult to read.
66 In general, only the important configuration values or bits changed
67 multiple times should be defined symbolically.
70 /* I/O register offsets */
75 TxDMABurstThresh = 0x18,
76 TxDMAUrgentThresh = 0x19,
77 TxDMAPollPeriod = 0x1a,
80 RxDMABurstThresh = 0x24,
81 RxDMAUrgentThresh = 0x25,
82 RxDMAPollPeriod = 0x26,
114 RxJumboFrames = 0xbc,
115 TCPCheckSumErrors = 0xc0,
116 IPCheckSumErrors = 0xc2,
117 UDPCheckSumErrors = 0xc4,
118 TxJumboFrames = 0xf4,
119 /* Ethernet MIB statistic register offsets */
121 McstOctetRcvOk = 0xac,
122 BcstOctetRcvOk = 0xb0,
124 McstFramesRcvdOk = 0xb8,
125 BcstFramesRcvdOk = 0xbe,
126 MacControlFramesRcvd = 0xc6,
127 FrameTooLongErrors = 0xc8,
128 InRangeLengthErrors = 0xca,
129 FramesCheckSeqErrors = 0xcc,
130 FramesLostRxErrors = 0xce,
132 McstOctetXmtOk = 0xd4,
133 BcstOctetXmtOk = 0xd8,
135 McstFramesXmtdOk = 0xe0,
136 FramesWDeferredXmt = 0xe4,
137 LateCollisions = 0xe8,
138 MultiColFrames = 0xec,
139 SingleColFrames = 0xf0,
140 BcstFramesXmtdOk = 0xf6,
141 CarrierSenseErrors = 0xf8,
142 MacControlFramesXmtd = 0xfa,
143 FramesAbortXSColls = 0xfc,
144 FramesWEXDeferal = 0xfe,
145 /* RMON statistic register offsets */
146 EtherStatsCollisions = 0x100,
147 EtherStatsOctetsTransmit = 0x104,
148 EtherStatsPktsTransmit = 0x108,
149 EtherStatsPkts64OctetTransmit = 0x10c,
150 EtherStats65to127OctetsTransmit = 0x110,
151 EtherStatsPkts128to255OctetsTransmit = 0x114,
152 EtherStatsPkts256to511OctetsTransmit = 0x118,
153 EtherStatsPkts512to1023OctetsTransmit = 0x11c,
154 EtherStatsPkts1024to1518OctetsTransmit = 0x120,
155 EtherStatsCRCAlignErrors = 0x124,
156 EtherStatsUndersizePkts = 0x128,
157 EtherStatsFragments = 0x12c,
158 EtherStatsJabbers = 0x130,
159 EtherStatsOctets = 0x134,
160 EtherStatsPkts = 0x138,
161 EtherStats64Octets = 0x13c,
162 EtherStatsPkts65to127Octets = 0x140,
163 EtherStatsPkts128to255Octets = 0x144,
164 EtherStatsPkts256to511Octets = 0x148,
165 EtherStatsPkts512to1023Octets = 0x14c,
166 EtherStatsPkts1024to1518Octets = 0x150,
169 /* Bits in the interrupt status/mask registers. */
170 enum IntStatus_bits {
171 InterruptStatus = 0x0001,
173 MACCtrlFrame = 0x0008,
177 IntRequested = 0x0040,
178 UpdateStats = 0x0080,
180 TxDMAComplete = 0x0200,
181 RxDMAComplete = 0x0400,
183 RxDMAPriority = 0x1000,
186 /* Bits in the ReceiveMode register. */
187 enum ReceiveMode_bits {
188 ReceiveUnicast = 0x0001,
189 ReceiveMulticast = 0x0002,
190 ReceiveBroadcast = 0x0004,
191 ReceiveAllFrames = 0x0008,
192 ReceiveMulticastHash = 0x0010,
193 ReceiveIPMulticast = 0x0020,
194 ReceiveVLANMatch = 0x0100,
195 ReceiveVLANHash = 0x0200,
197 /* Bits in MACCtrl. */
200 TxFlowControlEnable = 0x80,
201 RxFlowControlEnable = 0x0100,
203 AutoVLANtagging = 0x1000,
204 AutoVLANuntagging = 0x2000,
205 StatsEnable = 0x00200000,
206 StatsDisable = 0x00400000,
207 StatsEnabled = 0x00800000,
208 TxEnable = 0x01000000,
209 TxDisable = 0x02000000,
210 TxEnabled = 0x04000000,
211 RxEnable = 0x08000000,
212 RxDisable = 0x10000000,
213 RxEnabled = 0x20000000,
216 enum ASICCtrl_LoWord_bits {
220 enum ASICCtrl_HiWord_bits {
221 GlobalReset = 0x0001,
226 NetworkReset = 0x0020,
231 /* Transmit Frame Control bits */
233 DwordAlign = 0x00000000,
234 WordAlignDisable = 0x00030000,
235 WordAlign = 0x00020000,
236 TCPChecksumEnable = 0x00040000,
237 UDPChecksumEnable = 0x00080000,
238 IPChecksumEnable = 0x00100000,
239 FCSAppendDisable = 0x00200000,
240 TxIndicate = 0x00400000,
241 TxDMAIndicate = 0x00800000,
243 VLANTagInsert = 0x0000000010000000,
244 TFDDone = 0x80000000,
246 UsePriorityShift = 48,
249 /* Receive Frames Status bits */
251 RxFIFOOverrun = 0x00010000,
252 RxRuntFrame = 0x00020000,
253 RxAlignmentError = 0x00040000,
254 RxFCSError = 0x00080000,
255 RxOverSizedFrame = 0x00100000,
256 RxLengthError = 0x00200000,
257 VLANDetected = 0x00400000,
258 TCPDetected = 0x00800000,
259 TCPError = 0x01000000,
260 UDPDetected = 0x02000000,
261 UDPError = 0x04000000,
262 IPDetected = 0x08000000,
263 IPError = 0x10000000,
264 FrameStart = 0x20000000,
265 FrameEnd = 0x40000000,
266 RFDDone = 0x80000000,
268 RFS_Errors = 0x003f0000,
271 #define MII_RESET_TIME_OUT 10000
300 /* Basic Mode Control Register */
302 MII_BMCR_RESET = 0x8000,
303 MII_BMCR_LOOP_BACK = 0x4000,
304 MII_BMCR_SPEED_LSB = 0x2000,
305 MII_BMCR_AN_ENABLE = 0x1000,
306 MII_BMCR_POWER_DOWN = 0x0800,
307 MII_BMCR_ISOLATE = 0x0400,
308 MII_BMCR_RESTART_AN = 0x0200,
309 MII_BMCR_DUPLEX_MODE = 0x0100,
310 MII_BMCR_COL_TEST = 0x0080,
311 MII_BMCR_SPEED_MSB = 0x0040,
312 MII_BMCR_SPEED_RESERVED = 0x003f,
313 MII_BMCR_SPEED_10 = 0,
314 MII_BMCR_SPEED_100 = MII_BMCR_SPEED_LSB,
315 MII_BMCR_SPEED_1000 = MII_BMCR_SPEED_MSB,
318 /* Basic Mode Status Register */
320 MII_BMSR_100BT4 = 0x8000,
321 MII_BMSR_100BX_FD = 0x4000,
322 MII_BMSR_100BX_HD = 0x2000,
323 MII_BMSR_10BT_FD = 0x1000,
324 MII_BMSR_10BT_HD = 0x0800,
325 MII_BMSR_100BT2_FD = 0x0400,
326 MII_BMSR_100BT2_HD = 0x0200,
327 MII_BMSR_EXT_STATUS = 0x0100,
328 MII_BMSR_PREAMBLE_SUPP = 0x0040,
329 MII_BMSR_AN_COMPLETE = 0x0020,
330 MII_BMSR_REMOTE_FAULT = 0x0010,
331 MII_BMSR_AN_ABILITY = 0x0008,
332 MII_BMSR_LINK_STATUS = 0x0004,
333 MII_BMSR_JABBER_DETECT = 0x0002,
334 MII_BMSR_EXT_CAP = 0x0001,
339 MII_ANAR_NEXT_PAGE = 0x8000,
340 MII_ANAR_REMOTE_FAULT = 0x4000,
341 MII_ANAR_ASYMMETRIC = 0x0800,
342 MII_ANAR_PAUSE = 0x0400,
343 MII_ANAR_100BT4 = 0x0200,
344 MII_ANAR_100BX_FD = 0x0100,
345 MII_ANAR_100BX_HD = 0x0080,
346 MII_ANAR_10BT_FD = 0x0020,
347 MII_ANAR_10BT_HD = 0x0010,
348 MII_ANAR_SELECTOR = 0x001f,
349 MII_IEEE8023_CSMACD = 0x0001,
354 MII_ANLPAR_NEXT_PAGE = MII_ANAR_NEXT_PAGE,
355 MII_ANLPAR_REMOTE_FAULT = MII_ANAR_REMOTE_FAULT,
356 MII_ANLPAR_ASYMMETRIC = MII_ANAR_ASYMMETRIC,
357 MII_ANLPAR_PAUSE = MII_ANAR_PAUSE,
358 MII_ANLPAR_100BT4 = MII_ANAR_100BT4,
359 MII_ANLPAR_100BX_FD = MII_ANAR_100BX_FD,
360 MII_ANLPAR_100BX_HD = MII_ANAR_100BX_HD,
361 MII_ANLPAR_10BT_FD = MII_ANAR_10BT_FD,
362 MII_ANLPAR_10BT_HD = MII_ANAR_10BT_HD,
363 MII_ANLPAR_SELECTOR = MII_ANAR_SELECTOR,
366 /* Auto-Negotiation Expansion Register */
367 typedef union t_MII_ANER {
370 u16 lp_negotiable:1; // bit 0
371 u16 page_received:1; // bit 1
372 u16 nextpagable:1; // bit 2
373 u16 lp_nextpagable:1; // bit 3
374 u16 pdetect_fault:1; // bit 4
375 u16 _bit15_5:11; // bit 15:5
380 MII_ANER_PAR_DETECT_FAULT = 0x0010,
381 MII_ANER_LP_NEXTPAGABLE = 0x0008,
382 MII_ANER_NETXTPAGABLE = 0x0004,
383 MII_ANER_PAGE_RECEIVED = 0x0002,
384 MII_ANER_LP_NEGOTIABLE = 0x0001,
387 /* MASTER-SLAVE Control Register */
388 typedef union t_MII_MSCR {
391 u16 _bit_7_0:8; // bit 7:0
392 u16 media_1000BT_HD:1; // bit 8
393 u16 media_1000BT_FD:1; // bit 9
394 u16 port_type:1; // bit 10
395 u16 cfg_value:1; // bit 11
396 u16 cfg_enable:1; // bit 12
397 u16 test_mode:3; // bit 15:13
402 MII_MSCR_TEST_MODE = 0xe000,
403 MII_MSCR_CFG_ENABLE = 0x1000,
404 MII_MSCR_CFG_VALUE = 0x0800,
405 MII_MSCR_PORT_VALUE = 0x0400,
406 MII_MSCR_1000BT_FD = 0x0200,
407 MII_MSCR_1000BT_HD = 0X0100,
410 /* MASTER-SLAVE Status Register */
411 typedef union t_MII_MSSR {
414 u16 idle_err_count:8; // bit 7:0
415 u16 _bit_9_8:2; // bit 9:8
416 u16 lp_1000BT_HD:1; // bit 10
417 u16 lp_1000BT_FD:1; // bit 11
418 u16 remote_rcv_status:1; // bit 12
419 u16 local_rcv_status:1; // bit 13
420 u16 cfg_resolution:1; // bit 14
421 u16 cfg_fault:1; // bit 15
426 MII_MSSR_CFG_FAULT = 0x8000,
427 MII_MSSR_CFG_RES = 0x4000,
428 MII_MSSR_LOCAL_RCV_STATUS = 0x2000,
429 MII_MSSR_REMOTE_RCVR = 0x1000,
430 MII_MSSR_LP_1000BT_HD = 0x0800,
431 MII_MSSR_LP_1000BT_FD = 0x0400,
432 MII_MSSR_IDLE_ERR_COUNT = 0x00ff,
435 /* IEEE Extened Status Register */
436 typedef union t_MII_ESR {
439 u16 _bit_11_0:12; // bit 11:0
440 u16 media_1000BT_HD:2; // bit 12
441 u16 media_1000BT_FD:1; // bit 13
442 u16 media_1000BX_HD:1; // bit 14
443 u16 media_1000BX_FD:1; // bit 15
448 MII_ESR_1000BX_FD = 0x8000,
449 MII_ESR_1000BX_HD = 0x4000,
450 MII_ESR_1000BT_FD = 0x2000,
451 MII_ESR_1000BT_HD = 0x1000,
453 /* PHY Specific Control Register */
454 typedef union t_MII_PHY_SCR {
457 u16 disable_jabber:1; // bit 0
458 u16 polarity_reversal:1; // bit 1
459 u16 SEQ_test:1; // bit 2
460 u16 _bit_3:1; // bit 3
461 u16 disable_CLK125:1; // bit 4
462 u16 mdi_crossover_mode:2; // bit 6:5
463 u16 enable_ext_dist:1; // bit 7
464 u16 _bit_8_9:2; // bit 9:8
465 u16 force_link:1; // bit 10
466 u16 assert_CRS:1; // bit 11
467 u16 rcv_fifo_depth:2; // bit 13:12
468 u16 xmit_fifo_depth:2; // bit 15:14
470 } PHY_SCR_t, *PPHY_SCR_t;
472 typedef enum t_MII_ADMIN_STATUS {
478 } MII_ADMIN_t, *PMII_ADMIN_t;
480 /* Physical Coding Sublayer Management (PCS) */
481 /* PCS control and status registers bitmap as the same as MII */
482 /* PCS Extended Status register bitmap as the same as MII */
485 PCS_ANAR_NEXT_PAGE = 0x8000,
486 PCS_ANAR_REMOTE_FAULT = 0x3000,
487 PCS_ANAR_ASYMMETRIC = 0x0100,
488 PCS_ANAR_PAUSE = 0x0080,
489 PCS_ANAR_HALF_DUPLEX = 0x0040,
490 PCS_ANAR_FULL_DUPLEX = 0x0020,
494 PCS_ANLPAR_NEXT_PAGE = PCS_ANAR_NEXT_PAGE,
495 PCS_ANLPAR_REMOTE_FAULT = PCS_ANAR_REMOTE_FAULT,
496 PCS_ANLPAR_ASYMMETRIC = PCS_ANAR_ASYMMETRIC,
497 PCS_ANLPAR_PAUSE = PCS_ANAR_PAUSE,
498 PCS_ANLPAR_HALF_DUPLEX = PCS_ANAR_HALF_DUPLEX,
499 PCS_ANLPAR_FULL_DUPLEX = PCS_ANAR_FULL_DUPLEX,
502 typedef struct t_SROM {
503 u16 config_param; /* 0x00 */
504 u16 asic_ctrl; /* 0x02 */
505 u16 sub_vendor_id; /* 0x04 */
506 u16 sub_system_id; /* 0x06 */
507 u16 reserved1[12]; /* 0x08-0x1f */
508 u8 mac_addr[6]; /* 0x20-0x25 */
509 u8 reserved2[10]; /* 0x26-0x2f */
510 u8 sib[204]; /* 0x30-0xfb */
511 u32 crc; /* 0xfc-0xff */
514 /* Ioctl custom data */
529 /* The Rx and Tx buffer descriptors. */
536 #define PRIV_ALIGN 15 /* Required alignment mask */
537 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
538 within the structure. */
539 struct netdev_private {
540 /* Descriptor rings first for alignment. */
541 struct netdev_desc *rx_ring;
542 struct netdev_desc *tx_ring;
543 struct sk_buff *rx_skbuff[RX_RING_SIZE];
544 struct sk_buff *tx_skbuff[TX_RING_SIZE];
545 dma_addr_t tx_ring_dma;
546 dma_addr_t rx_ring_dma;
547 struct pci_dev *pdev;
550 struct net_device_stats stats;
551 unsigned int rx_buf_sz; /* Based on MTU+slack. */
552 unsigned int speed; /* Operating speed */
553 unsigned int vlan; /* VLAN Id */
554 unsigned int chip_id; /* PCI table chip id */
555 unsigned int rx_coalesce; /* Maximum frames each RxDMAComplete intr */
556 unsigned int rx_timeout; /* Wait time between RxDMAComplete intr */
557 unsigned int tx_coalesce; /* Maximum frames each tx interrupt */
558 unsigned int full_duplex:1; /* Full-duplex operation requested. */
559 unsigned int an_enable:2; /* Auto-Negotiated Enable */
560 unsigned int jumbo:1; /* Jumbo frame enable */
561 unsigned int coalesce:1; /* Rx coalescing enable */
562 unsigned int tx_flow:1; /* Tx flow control enable */
563 unsigned int rx_flow:1; /* Rx flow control enable */
564 unsigned int phy_media:1; /* 1: fiber, 0: copper */
565 unsigned int link_status:1; /* Current link status */
566 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
567 unsigned long cur_rx, old_rx; /* Producer/consumer ring indices */
568 unsigned long cur_tx, old_tx;
569 struct timer_list timer;
571 char name[256]; /* net device description */
574 u16 advertising; /* NWay media advertisement */
575 u16 negotiate; /* Negotiated media */
576 int phy_addr; /* PHY addresses. */
579 /* The station address location in the EEPROM. */
580 /* The struct pci_device_id consist of:
581 vendor, device Vendor and device ID to match (or PCI_ANY_ID)
582 subvendor, subdevice Subsystem vendor and device ID to match (or PCI_ANY_ID)
583 class Device class to match. The class_mask tells which bits
584 class_mask of the class are honored during the comparison.
585 driver_data Data private to the driver.
588 static const struct pci_device_id rio_pci_tbl[] = {
589 {0x1186, 0x4000, PCI_ANY_ID, PCI_ANY_ID, },
590 {0x13f0, 0x1021, PCI_ANY_ID, PCI_ANY_ID, },
593 MODULE_DEVICE_TABLE (pci, rio_pci_tbl);
594 #define TX_TIMEOUT (4*HZ)
595 #define PACKET_SIZE 1536
596 #define MAX_JUMBO 8000
597 #define RIO_IO_SIZE 340
598 #define DEFAULT_RXC 5
599 #define DEFAULT_RXT 750
600 #define DEFAULT_TXC 1
602 #endif /* __DL2K_H__ */