drivers/net/defxx.c

   1 /*
   2  * File Name:
   3  *   defxx.c
   4  *
   5  * Copyright Information:
   6  *   Copyright Digital Equipment Corporation 1996.
   7  *
   8  *   This software may be used and distributed according to the terms of
   9  *   the GNU General Public License, incorporated herein by reference.
  10  *
  11  * Abstract:
  12  *   A Linux device driver supporting the Digital Equipment Corporation
  13  *   FDDI TURBOchannel, EISA and PCI controller families.  Supported
  14  *   adapters include:
  15  *
  16  *              DEC FDDIcontroller/TURBOchannel (DEFTA)
  17  *              DEC FDDIcontroller/EISA         (DEFEA)
  18  *              DEC FDDIcontroller/PCI          (DEFPA)
  19  *
  20  * The original author:
  21  *   LVS        Lawrence V. Stefani <lstefani@yahoo.com>
  22  *
  23  * Maintainers:
  24  *   macro      Maciej W. Rozycki <macro@linux-mips.org>
  25  *
  26  * Credits:
  27  *   I'd like to thank Patricia Cross for helping me get started with
  28  *   Linux, David Davies for a lot of help upgrading and configuring
  29  *   my development system and for answering many OS and driver
  30  *   development questions, and Alan Cox for recommendations and
  31  *   integration help on getting FDDI support into Linux.  LVS
  32  *
  33  * Driver Architecture:
  34  *   The driver architecture is largely based on previous driver work
  35  *   for other operating systems.  The upper edge interface and
  36  *   functions were largely taken from existing Linux device drivers
  37  *   such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
  38  *   driver.
  39  *
  40  *   Adapter Probe -
  41  *              The driver scans for supported EISA adapters by reading the
  42  *              SLOT ID register for each EISA slot and making a match
  43  *              against the expected value.
  44  *
  45  *   Bus-Specific Initialization -
  46  *              This driver currently supports both EISA and PCI controller
  47  *              families.  While the custom DMA chip and FDDI logic is similar
  48  *              or identical, the bus logic is very different.  After
  49  *              initialization, the     only bus-specific differences is in how the
  50  *              driver enables and disables interrupts.  Other than that, the
  51  *              run-time critical code behaves the same on both families.
  52  *              It's important to note that both adapter families are configured
  53  *              to I/O map, rather than memory map, the adapter registers.
  54  *
  55  *   Driver Open/Close -
  56  *              In the driver open routine, the driver ISR (interrupt service
  57  *              routine) is registered and the adapter is brought to an
  58  *              operational state.  In the driver close routine, the opposite
  59  *              occurs; the driver ISR is deregistered and the adapter is
  60  *              brought to a safe, but closed state.  Users may use consecutive
  61  *              commands to bring the adapter up and down as in the following
  62  *              example:
  63  *                                      ifconfig fddi0 up
  64  *                                      ifconfig fddi0 down
  65  *                                      ifconfig fddi0 up
  66  *
  67  *   Driver Shutdown -
  68  *              Apparently, there is no shutdown or halt routine support under
  69  *              Linux.  This routine would be called during "reboot" or
  70  *              "shutdown" to allow the driver to place the adapter in a safe
  71  *              state before a warm reboot occurs.  To be really safe, the user
  72  *              should close the adapter before shutdown (eg. ifconfig fddi0 down)
  73  *              to ensure that the adapter DMA engine is taken off-line.  However,
  74  *              the current driver code anticipates this problem and always issues
  75  *              a soft reset of the adapter     at the beginning of driver initialization.
  76  *              A future driver enhancement in this area may occur in 2.1.X where
  77  *              Alan indicated that a shutdown handler may be implemented.
  78  *
  79  *   Interrupt Service Routine -
  80  *              The driver supports shared interrupts, so the ISR is registered for
  81  *              each board with the appropriate flag and the pointer to that board's
  82  *              device structure.  This provides the context during interrupt
  83  *              processing to support shared interrupts and multiple boards.
  84  *
  85  *              Interrupt enabling/disabling can occur at many levels.  At the host
  86  *              end, you can disable system interrupts, or disable interrupts at the
  87  *              PIC (on Intel systems).  Across the bus, both EISA and PCI adapters
  88  *              have a bus-logic chip interrupt enable/disable as well as a DMA
  89  *              controller interrupt enable/disable.
  90  *
  91  *              The driver currently enables and disables adapter interrupts at the
  92  *              bus-logic chip and assumes that Linux will take care of clearing or
  93  *              acknowledging any host-based interrupt chips.
  94  *
  95  *   Control Functions -
  96  *              Control functions are those used to support functions such as adding
  97  *              or deleting multicast addresses, enabling or disabling packet
  98  *              reception filters, or other custom/proprietary commands.  Presently,
  99  *              the driver supports the "get statistics", "set multicast list", and
 100  *              "set mac address" functions defined by Linux.  A list of possible
 101  *              enhancements include:
 102  *
 103  *                              - Custom ioctl interface for executing port interface commands
 104  *                              - Custom ioctl interface for adding unicast addresses to
 105  *                                adapter CAM (to support bridge functions).
 106  *                              - Custom ioctl interface for supporting firmware upgrades.
 107  *
 108  *   Hardware (port interface) Support Routines -
 109  *              The driver function names that start with "dfx_hw_" represent
 110  *              low-level port interface routines that are called frequently.  They
 111  *              include issuing a DMA or port control command to the adapter,
 112  *              resetting the adapter, or reading the adapter state.  Since the
 113  *              driver initialization and run-time code must make calls into the
 114  *              port interface, these routines were written to be as generic and
 115  *              usable as possible.
 116  *
 117  *   Receive Path -
 118  *              The adapter DMA engine supports a 256 entry receive descriptor block
 119  *              of which up to 255 entries can be used at any given time.  The
 120  *              architecture is a standard producer, consumer, completion model in
 121  *              which the driver "produces" receive buffers to the adapter, the
 122  *              adapter "consumes" the receive buffers by DMAing incoming packet data,
 123  *              and the driver "completes" the receive buffers by servicing the
 124  *              incoming packet, then "produces" a new buffer and starts the cycle
 125  *              again.  Receive buffers can be fragmented in up to 16 fragments
 126  *              (descriptor     entries).  For simplicity, this driver posts
 127  *              single-fragment receive buffers of 4608 bytes, then allocates a
 128  *              sk_buff, copies the data, then reposts the buffer.  To reduce CPU
 129  *              utilization, a better approach would be to pass up the receive
 130  *              buffer (no extra copy) then allocate and post a replacement buffer.
 131  *              This is a performance enhancement that should be looked into at
 132  *              some point.
 133  *
 134  *   Transmit Path -
 135  *              Like the receive path, the adapter DMA engine supports a 256 entry
 136  *              transmit descriptor block of which up to 255 entries can be used at
 137  *              any     given time.  Transmit buffers can be fragmented in up to 255
 138  *              fragments (descriptor entries).  This driver always posts one
 139  *              fragment per transmit packet request.
 140  *
 141  *              The fragment contains the entire packet from FC to end of data.
 142  *              Before posting the buffer to the adapter, the driver sets a three-byte
 143  *              packet request header (PRH) which is required by the Motorola MAC chip
 144  *              used on the adapters.  The PRH tells the MAC the type of token to
 145  *              receive/send, whether or not to generate and append the CRC, whether
 146  *              synchronous or asynchronous framing is used, etc.  Since the PRH
 147  *              definition is not necessarily consistent across all FDDI chipsets,
 148  *              the driver, rather than the common FDDI packet handler routines,
 149  *              sets these bytes.
 150  *
 151  *              To reduce the amount of descriptor fetches needed per transmit request,
 152  *              the driver takes advantage of the fact that there are at least three
 153  *              bytes available before the skb->data field on the outgoing transmit
 154  *              request.  This is guaranteed by having fddi_setup() in net_init.c set
 155  *              dev->hard_header_len to 24 bytes.  21 bytes accounts for the largest
 156  *              header in an 802.2 SNAP frame.  The other 3 bytes are the extra "pad"
 157  *              bytes which we'll use to store the PRH.
 158  *
 159  *              There's a subtle advantage to adding these pad bytes to the
 160  *              hard_header_len, it ensures that the data portion of the packet for
 161  *              an 802.2 SNAP frame is longword aligned.  Other FDDI driver
 162  *              implementations may not need the extra padding and can start copying
 163  *              or DMAing directly from the FC byte which starts at skb->data.  Should
 164  *              another driver implementation need ADDITIONAL padding, the net_init.c
 165  *              module should be updated and dev->hard_header_len should be increased.
 166  *              NOTE: To maintain the alignment on the data portion of the packet,
 167  *              dev->hard_header_len should always be evenly divisible by 4 and at
 168  *              least 24 bytes in size.
 169  *
 170  * Modification History:
 171  *              Date            Name    Description
 172  *              16-Aug-96       LVS             Created.
 173  *              20-Aug-96       LVS             Updated dfx_probe so that version information
 174  *                                                      string is only displayed if 1 or more cards are
 175  *                                                      found.  Changed dfx_rcv_queue_process to copy
 176  *                                                      3 NULL bytes before FC to ensure that data is
 177  *                                                      longword aligned in receive buffer.
 178  *              09-Sep-96       LVS             Updated dfx_ctl_set_multicast_list to enable
 179  *                                                      LLC group promiscuous mode if multicast list
 180  *                                                      is too large.  LLC individual/group promiscuous
 181  *                                                      mode is now disabled if IFF_PROMISC flag not set.
 182  *                                                      dfx_xmt_queue_pkt no longer checks for NULL skb
 183  *                                                      on Alan Cox recommendation.  Added node address
 184  *                                                      override support.
 185  *              12-Sep-96       LVS             Reset current address to factory address during
 186  *                                                      device open.  Updated transmit path to post a
 187  *                                                      single fragment which includes PRH->end of data.
 188  *              Mar 2000        AC              Did various cleanups for 2.3.x
 189  *              Jun 2000        jgarzik         PCI and resource alloc cleanups
 190  *              Jul 2000        tjeerd          Much cleanup and some bug fixes
 191  *              Sep 2000        tjeerd          Fix leak on unload, cosmetic code cleanup
 192  *              Feb 2001                        Skb allocation fixes
 193  *              Feb 2001        davej           PCI enable cleanups.
 194  *              04 Aug 2003     macro           Converted to the DMA API.
 195  *              14 Aug 2004     macro           Fix device names reported.
 196  *              14 Jun 2005     macro           Use irqreturn_t.
 197  *              23 Oct 2006     macro           Big-endian host support.
 198  *              14 Dec 2006     macro           TURBOchannel support.
 199  */
 200
 201 /* Include files */
 202 #include <linux/bitops.h>
 203 #include <linux/compiler.h>
 204 #include <linux/delay.h>
 205 #include <linux/dma-mapping.h>
 206 #include <linux/eisa.h>
 207 #include <linux/errno.h>
 208 #include <linux/fddidevice.h>
 209 #include <linux/init.h>
 210 #include <linux/interrupt.h>
 211 #include <linux/ioport.h>
 212 #include <linux/kernel.h>
 213 #include <linux/module.h>
 214 #include <linux/netdevice.h>
 215 #include <linux/pci.h>
 216 #include <linux/skbuff.h>
 217 #include <linux/slab.h>
 218 #include <linux/string.h>
 219 #include <linux/tc.h>
 220
 221 #include <asm/byteorder.h>
 222 #include <asm/io.h>
 223
 224 #include "defxx.h"
 225
 226 /* Version information string should be updated prior to each new release!  */
 227 #define DRV_NAME "defxx"
 228 #define DRV_VERSION "v1.10"
 229 #define DRV_RELDATE "2006/12/14"
 230
 231 static char version[] __devinitdata =
 232         DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
 233         "  Lawrence V. Stefani and others\n";
 234
 235 #define DYNAMIC_BUFFERS 1
 236
 237 #define SKBUFF_RX_COPYBREAK 200
 238 /*
 239  * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
 240  * alignment for compatibility with old EISA boards.
 241  */
 242 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
 243
 244 #ifdef CONFIG_PCI
 245 #define DFX_BUS_PCI(dev) (dev->bus == &pci_bus_type)
 246 #else
 247 #define DFX_BUS_PCI(dev) 0
 248 #endif
 249
 250 #ifdef CONFIG_EISA
 251 #define DFX_BUS_EISA(dev) (dev->bus == &eisa_bus_type)
 252 #else
 253 #define DFX_BUS_EISA(dev) 0
 254 #endif
 255
 256 #ifdef CONFIG_TC
 257 #define DFX_BUS_TC(dev) (dev->bus == &tc_bus_type)
 258 #else
 259 #define DFX_BUS_TC(dev) 0
 260 #endif
 261
 262 #ifdef CONFIG_DEFXX_MMIO
 263 #define DFX_MMIO 1
 264 #else
 265 #define DFX_MMIO 0
 266 #endif
 267
 268 /* Define module-wide (static) routines */
 269
 270 static void             dfx_bus_init(struct net_device *dev);
 271 static void             dfx_bus_uninit(struct net_device *dev);
 272 static void             dfx_bus_config_check(DFX_board_t *bp);
 273
 274 static int              dfx_driver_init(struct net_device *dev,
 275                                         const char *print_name,
 276                                         resource_size_t bar_start);
 277 static int              dfx_adap_init(DFX_board_t *bp, int get_buffers);
 278
 279 static int              dfx_open(struct net_device *dev);
 280 static int              dfx_close(struct net_device *dev);
 281
 282 static void             dfx_int_pr_halt_id(DFX_board_t *bp);
 283 static void             dfx_int_type_0_process(DFX_board_t *bp);
 284 static void             dfx_int_common(struct net_device *dev);
 285 static irqreturn_t      dfx_interrupt(int irq, void *dev_id);
 286
 287 static struct           net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
 288 static void             dfx_ctl_set_multicast_list(struct net_device *dev);
 289 static int              dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
 290 static int              dfx_ctl_update_cam(DFX_board_t *bp);
 291 static int              dfx_ctl_update_filters(DFX_board_t *bp);
 292
 293 static int              dfx_hw_dma_cmd_req(DFX_board_t *bp);
 294 static int              dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
 295 static void             dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
 296 static int              dfx_hw_adap_state_rd(DFX_board_t *bp);
 297 static int              dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
 298
 299 static int              dfx_rcv_init(DFX_board_t *bp, int get_buffers);
 300 static void             dfx_rcv_queue_process(DFX_board_t *bp);
 301 static void             dfx_rcv_flush(DFX_board_t *bp);
 302
 303 static int              dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev);
 304 static int              dfx_xmt_done(DFX_board_t *bp);
 305 static void             dfx_xmt_flush(DFX_board_t *bp);
 306
 307 /* Define module-wide (static) variables */
 308
 309 static struct pci_driver dfx_pci_driver;
 310 static struct eisa_driver dfx_eisa_driver;
 311 static struct tc_driver dfx_tc_driver;
 312
 313
 314 /*
 315  * =======================
 316  * = dfx_port_write_long =
 317  * = dfx_port_read_long  =
 318  * =======================
 319  *
 320  * Overview:
 321  *   Routines for reading and writing values from/to adapter
 322  *
 323  * Returns:
 324  *   None
 325  *
 326  * Arguments:
 327  *   bp         - pointer to board information
 328  *   offset     - register offset from base I/O address
 329  *   data       - for dfx_port_write_long, this is a value to write;
 330  *                for dfx_port_read_long, this is a pointer to store
 331  *                the read value
 332  *
 333  * Functional Description:
 334  *   These routines perform the correct operation to read or write
 335  *   the adapter register.
 336  *
 337  *   EISA port block base addresses are based on the slot number in which the
 338  *   controller is installed.  For example, if the EISA controller is installed
 339  *   in slot 4, the port block base address is 0x4000.  If the controller is
 340  *   installed in slot 2, the port block base address is 0x2000, and so on.
 341  *   This port block can be used to access PDQ, ESIC, and DEFEA on-board
 342  *   registers using the register offsets defined in DEFXX.H.
 343  *
 344  *   PCI port block base addresses are assigned by the PCI BIOS or system
 345  *   firmware.  There is one 128 byte port block which can be accessed.  It
 346  *   allows for I/O mapping of both PDQ and PFI registers using the register
 347  *   offsets defined in DEFXX.H.
 348  *
 349  * Return Codes:
 350  *   None
 351  *
 352  * Assumptions:
 353  *   bp->base is a valid base I/O address for this adapter.
 354  *   offset is a valid register offset for this adapter.
 355  *
 356  * Side Effects:
 357  *   Rather than produce macros for these functions, these routines
 358  *   are defined using "inline" to ensure that the compiler will
 359  *   generate inline code and not waste a procedure call and return.
 360  *   This provides all the benefits of macros, but with the
 361  *   advantage of strict data type checking.
 362  */
 363
 364 static inline void dfx_writel(DFX_board_t *bp, int offset, u32 data)
 365 {
 366         writel(data, bp->base.mem + offset);
 367         mb();
 368 }
 369
 370 static inline void dfx_outl(DFX_board_t *bp, int offset, u32 data)
 371 {
 372         outl(data, bp->base.port + offset);
 373 }
 374
 375 static void dfx_port_write_long(DFX_board_t *bp, int offset, u32 data)
 376 {
 377         struct device __maybe_unused *bdev = bp->bus_dev;
 378         int dfx_bus_tc = DFX_BUS_TC(bdev);
 379         int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
 380
 381         if (dfx_use_mmio)
 382                 dfx_writel(bp, offset, data);
 383         else
 384                 dfx_outl(bp, offset, data);
 385 }
 386
 387
 388 static inline void dfx_readl(DFX_board_t *bp, int offset, u32 *data)
 389 {
 390         mb();
 391         *data = readl(bp->base.mem + offset);
 392 }
 393
 394 static inline void dfx_inl(DFX_board_t *bp, int offset, u32 *data)
 395 {
 396         *data = inl(bp->base.port + offset);
 397 }
 398
 399 static void dfx_port_read_long(DFX_board_t *bp, int offset, u32 *data)
 400 {
 401         struct device __maybe_unused *bdev = bp->bus_dev;
 402         int dfx_bus_tc = DFX_BUS_TC(bdev);
 403         int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
 404
 405         if (dfx_use_mmio)
 406                 dfx_readl(bp, offset, data);
 407         else
 408                 dfx_inl(bp, offset, data);
 409 }
 410
 411
 412 /*
 413  * ================
 414  * = dfx_get_bars =
 415  * ================
 416  *
 417  * Overview:
 418  *   Retrieves the address range used to access control and status
 419  *   registers.
 420  *
 421  * Returns:
 422  *   None
 423  *
 424  * Arguments:
 425  *   bdev       - pointer to device information
 426  *   bar_start  - pointer to store the start address
 427  *   bar_len    - pointer to store the length of the area
 428  *
 429  * Assumptions:
 430  *   I am sure there are some.
 431  *
 432  * Side Effects:
 433  *   None
 434  */
 435 static void dfx_get_bars(struct device *bdev,
 436                          resource_size_t *bar_start, resource_size_t *bar_len)
 437 {
 438         int dfx_bus_pci = DFX_BUS_PCI(bdev);
 439         int dfx_bus_eisa = DFX_BUS_EISA(bdev);
 440         int dfx_bus_tc = DFX_BUS_TC(bdev);
 441         int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
 442
 443         if (dfx_bus_pci) {
 444                 int num = dfx_use_mmio ? 0 : 1;
 445
 446                 *bar_start = pci_resource_start(to_pci_dev(bdev), num);
 447                 *bar_len = pci_resource_len(to_pci_dev(bdev), num);
 448         }
 449         if (dfx_bus_eisa) {
 450                 unsigned long base_addr = to_eisa_device(bdev)->base_addr;
 451                 resource_size_t bar;
 452
 453                 if (dfx_use_mmio) {
 454                         bar = inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_2);
 455                         bar <<= 8;
 456                         bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_1);
 457                         bar <<= 8;
 458                         bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_CMP_0);
 459                         bar <<= 16;
 460                         *bar_start = bar;
 461                         bar = inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_2);
 462                         bar <<= 8;
 463                         bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_1);
 464                         bar <<= 8;
 465                         bar |= inb(base_addr + PI_ESIC_K_MEM_ADD_MASK_0);
 466                         bar <<= 16;
 467                         *bar_len = (bar | PI_MEM_ADD_MASK_M) + 1;
 468                 } else {
 469                         *bar_start = base_addr;
 470                         *bar_len = PI_ESIC_K_CSR_IO_LEN;
 471                 }
 472         }
 473         if (dfx_bus_tc) {
 474                 *bar_start = to_tc_dev(bdev)->resource.start +
 475                              PI_TC_K_CSR_OFFSET;
 476                 *bar_len = PI_TC_K_CSR_LEN;
 477         }
 478 }
 479
 480 static const struct net_device_ops dfx_netdev_ops = {
 481         .ndo_open               = dfx_open,
 482         .ndo_stop               = dfx_close,
 483         .ndo_start_xmit         = dfx_xmt_queue_pkt,
 484         .ndo_get_stats          = dfx_ctl_get_stats,
 485         .ndo_set_multicast_list = dfx_ctl_set_multicast_list,
 486         .ndo_set_mac_address    = dfx_ctl_set_mac_address,
 487 };
 488
 489 /*
 490  * ================
 491  * = dfx_register =
 492  * ================
 493  *
 494  * Overview:
 495  *   Initializes a supported FDDI controller
 496  *
 497  * Returns:
 498  *   Condition code
 499  *
 500  * Arguments:
 501  *   bdev - pointer to device information
 502  *
 503  * Functional Description:
 504  *
 505  * Return Codes:
 506  *   0           - This device (fddi0, fddi1, etc) configured successfully
 507  *   -EBUSY      - Failed to get resources, or dfx_driver_init failed.
 508  *
 509  * Assumptions:
 510  *   It compiles so it should work :-( (PCI cards do :-)
 511  *
 512  * Side Effects:
 513  *   Device structures for FDDI adapters (fddi0, fddi1, etc) are
 514  *   initialized and the board resources are read and stored in
 515  *   the device structure.
 516  */
 517 static int __devinit dfx_register(struct device *bdev)
 518 {
 519         static int version_disp;
 520         int dfx_bus_pci = DFX_BUS_PCI(bdev);
 521         int dfx_bus_tc = DFX_BUS_TC(bdev);
 522         int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
 523         const char *print_name = dev_name(bdev);
 524         struct net_device *dev;
 525         DFX_board_t       *bp;                  /* board pointer */
 526         resource_size_t bar_start = 0;          /* pointer to port */
 527         resource_size_t bar_len = 0;            /* resource length */
 528         int alloc_size;                         /* total buffer size used */
 529         struct resource *region;
 530         int err = 0;
 531
 532         if (!version_disp) {    /* display version info if adapter is found */
 533                 version_disp = 1;       /* set display flag to TRUE so that */
 534                 printk(version);        /* we only display this string ONCE */
 535         }
 536
 537         dev = alloc_fddidev(sizeof(*bp));
 538         if (!dev) {
 539                 printk(KERN_ERR "%s: Unable to allocate fddidev, aborting\n",
 540                        print_name);
 541                 return -ENOMEM;
 542         }
 543
 544         /* Enable PCI device. */
 545         if (dfx_bus_pci && pci_enable_device(to_pci_dev(bdev))) {
 546                 printk(KERN_ERR "%s: Cannot enable PCI device, aborting\n",
 547                        print_name);
 548                 goto err_out;
 549         }
 550
 551         SET_NETDEV_DEV(dev, bdev);
 552
 553         bp = netdev_priv(dev);
 554         bp->bus_dev = bdev;
 555         dev_set_drvdata(bdev, dev);
 556
 557         dfx_get_bars(bdev, &bar_start, &bar_len);
 558
 559         if (dfx_use_mmio)
 560                 region = request_mem_region(bar_start, bar_len, print_name);
 561         else
 562                 region = request_region(bar_start, bar_len, print_name);
 563         if (!region) {
 564                 printk(KERN_ERR "%s: Cannot reserve I/O resource "
 565                        "0x%lx @ 0x%lx, aborting\n",
 566                        print_name, (long)bar_len, (long)bar_start);
 567                 err = -EBUSY;
 568                 goto err_out_disable;
 569         }
 570
 571         /* Set up I/O base address. */
 572         if (dfx_use_mmio) {
 573                 bp->base.mem = ioremap_nocache(bar_start, bar_len);
 574                 if (!bp->base.mem) {
 575                         printk(KERN_ERR "%s: Cannot map MMIO\n", print_name);
 576                         err = -ENOMEM;
 577                         goto err_out_region;
 578                 }
 579         } else {
 580                 bp->base.port = bar_start;
 581                 dev->base_addr = bar_start;
 582         }
 583
 584         /* Initialize new device structure */
 585         dev->netdev_ops                 = &dfx_netdev_ops;
 586
 587         if (dfx_bus_pci)
 588                 pci_set_master(to_pci_dev(bdev));
 589
 590         if (dfx_driver_init(dev, print_name, bar_start) != DFX_K_SUCCESS) {
 591                 err = -ENODEV;
 592                 goto err_out_unmap;
 593         }
 594
 595         err = register_netdev(dev);
 596         if (err)
 597                 goto err_out_kfree;
 598
 599         printk("%s: registered as %s\n", print_name, dev->name);
 600         return 0;
 601
 602 err_out_kfree:
 603         alloc_size = sizeof(PI_DESCR_BLOCK) +
 604                      PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
 605 #ifndef DYNAMIC_BUFFERS
 606                      (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
 607 #endif
 608                      sizeof(PI_CONSUMER_BLOCK) +
 609                      (PI_ALIGN_K_DESC_BLK - 1);
 610         if (bp->kmalloced)
 611                 dma_free_coherent(bdev, alloc_size,
 612                                   bp->kmalloced, bp->kmalloced_dma);
 613
 614 err_out_unmap:
 615         if (dfx_use_mmio)
 616                 iounmap(bp->base.mem);
 617
 618 err_out_region:
 619         if (dfx_use_mmio)
 620                 release_mem_region(bar_start, bar_len);
 621         else
 622                 release_region(bar_start, bar_len);
 623
 624 err_out_disable:
 625         if (dfx_bus_pci)
 626                 pci_disable_device(to_pci_dev(bdev));
 627
 628 err_out:
 629         free_netdev(dev);
 630         return err;
 631 }
 632
 633
 634 /*
 635  * ================
 636  * = dfx_bus_init =
 637  * ================
 638  *
 639  * Overview:
 640  *   Initializes the bus-specific controller logic.
 641  *
 642  * Returns:
 643  *   None
 644  *
 645  * Arguments:
 646  *   dev - pointer to device information
 647  *
 648  * Functional Description:
 649  *   Determine and save adapter IRQ in device table,
 650  *   then perform bus-specific logic initialization.
 651  *
 652  * Return Codes:
 653  *   None
 654  *
 655  * Assumptions:
 656  *   bp->base has already been set with the proper
 657  *       base I/O address for this device.
 658  *
 659  * Side Effects:
 660  *   Interrupts are enabled at the adapter bus-specific logic.
 661  *   Note:  Interrupts at the DMA engine (PDQ chip) are not
 662  *   enabled yet.
 663  */
 664
 665 static void __devinit dfx_bus_init(struct net_device *dev)
 666 {
 667         DFX_board_t *bp = netdev_priv(dev);
 668         struct device *bdev = bp->bus_dev;
 669         int dfx_bus_pci = DFX_BUS_PCI(bdev);
 670         int dfx_bus_eisa = DFX_BUS_EISA(bdev);
 671         int dfx_bus_tc = DFX_BUS_TC(bdev);
 672         int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
 673         u8 val;
 674
 675         DBG_printk("In dfx_bus_init...\n");
 676
 677         /* Initialize a pointer back to the net_device struct */
 678         bp->dev = dev;
 679
 680         /* Initialize adapter based on bus type */
 681
 682         if (dfx_bus_tc)
 683                 dev->irq = to_tc_dev(bdev)->interrupt;
 684         if (dfx_bus_eisa) {
 685                 unsigned long base_addr = to_eisa_device(bdev)->base_addr;
 686
 687                 /* Get the interrupt level from the ESIC chip.  */
 688                 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
 689                 val &= PI_CONFIG_STAT_0_M_IRQ;
 690                 val >>= PI_CONFIG_STAT_0_V_IRQ;
 691
 692                 switch (val) {
 693                 case PI_CONFIG_STAT_0_IRQ_K_9:
 694                         dev->irq = 9;
 695                         break;
 696
 697                 case PI_CONFIG_STAT_0_IRQ_K_10:
 698                         dev->irq = 10;
 699                         break;
 700
 701                 case PI_CONFIG_STAT_0_IRQ_K_11:
 702                         dev->irq = 11;
 703                         break;
 704
 705                 case PI_CONFIG_STAT_0_IRQ_K_15:
 706                         dev->irq = 15;
 707                         break;
 708                 }
 709
 710                 /*
 711                  * Enable memory decoding (MEMCS0) and/or port decoding
 712                  * (IOCS1/IOCS0) as appropriate in Function Control
 713                  * Register.  One of the port chip selects seems to be
 714                  * used for the Burst Holdoff register, but this bit of
 715                  * documentation is missing and as yet it has not been
 716                  * determined which of the two.  This is also the reason
 717                  * the size of the decoded port range is twice as large
 718                  * as one required by the PDQ.
 719                  */
 720
 721                 /* Set the decode range of the board.  */
 722                 val = ((bp->base.port >> 12) << PI_IO_CMP_V_SLOT);
 723                 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_1, val);
 724                 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_0_0, 0);
 725                 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_1, val);
 726                 outb(base_addr + PI_ESIC_K_IO_ADD_CMP_1_0, 0);
 727                 val = PI_ESIC_K_CSR_IO_LEN - 1;
 728                 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_1, (val >> 8) & 0xff);
 729                 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_0_0, val & 0xff);
 730                 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_1, (val >> 8) & 0xff);
 731                 outb(base_addr + PI_ESIC_K_IO_ADD_MASK_1_0, val & 0xff);
 732
 733                 /* Enable the decoders.  */
 734                 val = PI_FUNCTION_CNTRL_M_IOCS1 | PI_FUNCTION_CNTRL_M_IOCS0;
 735                 if (dfx_use_mmio)
 736                         val |= PI_FUNCTION_CNTRL_M_MEMCS0;
 737                 outb(base_addr + PI_ESIC_K_FUNCTION_CNTRL, val);
 738
 739                 /*
 740                  * Enable access to the rest of the module
 741                  * (including PDQ and packet memory).
 742                  */
 743                 val = PI_SLOT_CNTRL_M_ENB;
 744                 outb(base_addr + PI_ESIC_K_SLOT_CNTRL, val);
 745
 746                 /*
 747                  * Map PDQ registers into memory or port space.  This is
 748                  * done with a bit in the Burst Holdoff register.
 749                  */
 750                 val = inb(base_addr + PI_DEFEA_K_BURST_HOLDOFF);
 751                 if (dfx_use_mmio)
 752                         val |= PI_BURST_HOLDOFF_V_MEM_MAP;
 753                 else
 754                         val &= ~PI_BURST_HOLDOFF_V_MEM_MAP;
 755                 outb(base_addr + PI_DEFEA_K_BURST_HOLDOFF, val);
 756
 757                 /* Enable interrupts at EISA bus interface chip (ESIC) */
 758                 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
 759                 val |= PI_CONFIG_STAT_0_M_INT_ENB;
 760                 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val);
 761         }
 762         if (dfx_bus_pci) {
 763                 struct pci_dev *pdev = to_pci_dev(bdev);
 764
 765                 /* Get the interrupt level from the PCI Configuration Table */
 766
 767                 dev->irq = pdev->irq;
 768
 769                 /* Check Latency Timer and set if less than minimal */
 770
 771                 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
 772                 if (val < PFI_K_LAT_TIMER_MIN) {
 773                         val = PFI_K_LAT_TIMER_DEF;
 774                         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
 775                 }
 776
 777                 /* Enable interrupts at PCI bus interface chip (PFI) */
 778                 val = PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB;
 779                 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, val);
 780         }
 781 }
 782
 783 /*
 784  * ==================
 785  * = dfx_bus_uninit =
 786  * ==================
 787  *
 788  * Overview:
 789  *   Uninitializes the bus-specific controller logic.
 790  *
 791  * Returns:
 792  *   None
 793  *
 794  * Arguments:
 795  *   dev - pointer to device information
 796  *
 797  * Functional Description:
 798  *   Perform bus-specific logic uninitialization.
 799  *
 800  * Return Codes:
 801  *   None
 802  *
 803  * Assumptions:
 804  *   bp->base has already been set with the proper
 805  *       base I/O address for this device.
 806  *
 807  * Side Effects:
 808  *   Interrupts are disabled at the adapter bus-specific logic.
 809  */
 810
 811 static void __devexit dfx_bus_uninit(struct net_device *dev)
 812 {
 813         DFX_board_t *bp = netdev_priv(dev);
 814         struct device *bdev = bp->bus_dev;
 815         int dfx_bus_pci = DFX_BUS_PCI(bdev);
 816         int dfx_bus_eisa = DFX_BUS_EISA(bdev);
 817         u8 val;
 818
 819         DBG_printk("In dfx_bus_uninit...\n");
 820
 821         /* Uninitialize adapter based on bus type */
 822
 823         if (dfx_bus_eisa) {
 824                 unsigned long base_addr = to_eisa_device(bdev)->base_addr;
 825
 826                 /* Disable interrupts at EISA bus interface chip (ESIC) */
 827                 val = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
 828                 val &= ~PI_CONFIG_STAT_0_M_INT_ENB;
 829                 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, val);
 830         }
 831         if (dfx_bus_pci) {
 832                 /* Disable interrupts at PCI bus interface chip (PFI) */
 833                 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, 0);
 834         }
 835 }
 836
 837
 838 /*
 839  * ========================
 840  * = dfx_bus_config_check =
 841  * ========================
 842  *
 843  * Overview:
 844  *   Checks the configuration (burst size, full-duplex, etc.)  If any parameters
 845  *   are illegal, then this routine will set new defaults.
 846  *
 847  * Returns:
 848  *   None
 849  *
 850  * Arguments:
 851  *   bp - pointer to board information
 852  *
 853  * Functional Description:
 854  *   For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
 855  *   PDQ, and all FDDI PCI controllers, all values are legal.
 856  *
 857  * Return Codes:
 858  *   None
 859  *
 860  * Assumptions:
 861  *   dfx_adap_init has NOT been called yet so burst size and other items have
 862  *   not been set.
 863  *
 864  * Side Effects:
 865  *   None
 866  */
 867
 868 static void __devinit dfx_bus_config_check(DFX_board_t *bp)
 869 {
 870         struct device __maybe_unused *bdev = bp->bus_dev;
 871         int dfx_bus_eisa = DFX_BUS_EISA(bdev);
 872         int     status;                         /* return code from adapter port control call */
 873         u32     host_data;                      /* LW data returned from port control call */
 874
 875         DBG_printk("In dfx_bus_config_check...\n");
 876
 877         /* Configuration check only valid for EISA adapter */
 878
 879         if (dfx_bus_eisa) {
 880                 /*
 881                  * First check if revision 2 EISA controller.  Rev. 1 cards used
 882                  * PDQ revision B, so no workaround needed in this case.  Rev. 3
 883                  * cards used PDQ revision E, so no workaround needed in this
 884                  * case, either.  Only Rev. 2 cards used either Rev. D or E
 885                  * chips, so we must verify the chip revision on Rev. 2 cards.
 886                  */
 887                 if (to_eisa_device(bdev)->id.driver_data == DEFEA_PROD_ID_2) {
 888                         /*
 889                          * Revision 2 FDDI EISA controller found,
 890                          * so let's check PDQ revision of adapter.
 891                          */
 892                         status = dfx_hw_port_ctrl_req(bp,
 893                                                                                         PI_PCTRL_M_SUB_CMD,
 894                                                                                         PI_SUB_CMD_K_PDQ_REV_GET,
 895                                                                                         0,
 896                                                                                         &host_data);
 897                         if ((status != DFX_K_SUCCESS) || (host_data == 2))
 898                                 {
 899                                 /*
 900                                  * Either we couldn't determine the PDQ revision, or
 901                                  * we determined that it is at revision D.  In either case,
 902                                  * we need to implement the workaround.
 903                                  */
 904
 905                                 /* Ensure that the burst size is set to 8 longwords or less */
 906
 907                                 switch (bp->burst_size)
 908                                         {
 909                                         case PI_PDATA_B_DMA_BURST_SIZE_32:
 910                                         case PI_PDATA_B_DMA_BURST_SIZE_16:
 911                                                 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
 912                                                 break;
 913
 914                                         default:
 915                                                 break;
 916                                         }
 917
 918                                 /* Ensure that full-duplex mode is not enabled */
 919
 920                                 bp->full_duplex_enb = PI_SNMP_K_FALSE;
 921                                 }
 922                         }
 923                 }
 924         }
 925
 926
 927 /*
 928  * ===================
 929  * = dfx_driver_init =
 930  * ===================
 931  *
 932  * Overview:
 933  *   Initializes remaining adapter board structure information
 934  *   and makes sure adapter is in a safe state prior to dfx_open().
 935  *
 936  * Returns:
 937  *   Condition code
 938  *
 939  * Arguments:
 940  *   dev - pointer to device information
 941  *   print_name - printable device name
 942  *
 943  * Functional Description:
 944  *   This function allocates additional resources such as the host memory
 945  *   blocks needed by the adapter (eg. descriptor and consumer blocks).
 946  *       Remaining bus initialization steps are also completed.  The adapter
 947  *   is also reset so that it is in the DMA_UNAVAILABLE state.  The OS
 948  *   must call dfx_open() to open the adapter and bring it on-line.
 949  *
 950  * Return Codes:
 951  *   DFX_K_SUCCESS      - initialization succeeded
 952  *   DFX_K_FAILURE      - initialization failed - could not allocate memory
 953  *                                              or read adapter MAC address
 954  *
 955  * Assumptions:
 956  *   Memory allocated from pci_alloc_consistent() call is physically
 957  *   contiguous, locked memory.
 958  *
 959  * Side Effects:
 960  *   Adapter is reset and should be in DMA_UNAVAILABLE state before
 961  *   returning from this routine.
 962  */
 963
 964 static int __devinit dfx_driver_init(struct net_device *dev,
 965                                      const char *print_name,
 966                                      resource_size_t bar_start)
 967 {
 968         DFX_board_t *bp = netdev_priv(dev);
 969         struct device *bdev = bp->bus_dev;
 970         int dfx_bus_pci = DFX_BUS_PCI(bdev);
 971         int dfx_bus_eisa = DFX_BUS_EISA(bdev);
 972         int dfx_bus_tc = DFX_BUS_TC(bdev);
 973         int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
 974         int alloc_size;                 /* total buffer size needed */
 975         char *top_v, *curr_v;           /* virtual addrs into memory block */
 976         dma_addr_t top_p, curr_p;       /* physical addrs into memory block */
 977         u32 data;                       /* host data register value */
 978         __le32 le32;
 979         char *board_name = NULL;
 980
 981         DBG_printk("In dfx_driver_init...\n");
 982
 983         /* Initialize bus-specific hardware registers */
 984
 985         dfx_bus_init(dev);
 986
 987         /*
 988          * Initialize default values for configurable parameters
 989          *
 990          * Note: All of these parameters are ones that a user may
 991          *       want to customize.  It'd be nice to break these
 992          *               out into Space.c or someplace else that's more
 993          *               accessible/understandable than this file.
 994          */
 995
 996         bp->full_duplex_enb             = PI_SNMP_K_FALSE;
 997         bp->req_ttrt                    = 8 * 12500;            /* 8ms in 80 nanosec units */
 998         bp->burst_size                  = PI_PDATA_B_DMA_BURST_SIZE_DEF;
 999         bp->rcv_bufs_to_post    = RCV_BUFS_DEF;
1000
1001         /*
1002          * Ensure that HW configuration is OK
1003          *
1004          * Note: Depending on the hardware revision, we may need to modify
1005          *       some of the configurable parameters to workaround hardware
1006          *       limitations.  We'll perform this configuration check AFTER
1007          *       setting the parameters to their default values.
1008          */
1009
1010         dfx_bus_config_check(bp);
1011
1012         /* Disable PDQ interrupts first */
1013
1014         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1015
1016         /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1017
1018         (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1019
1020         /*  Read the factory MAC address from the adapter then save it */
1021
1022         if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0,
1023                                  &data) != DFX_K_SUCCESS) {
1024                 printk("%s: Could not read adapter factory MAC address!\n",
1025                        print_name);
1026                 return(DFX_K_FAILURE);
1027         }
1028         le32 = cpu_to_le32(data);
1029         memcpy(&bp->factory_mac_addr[0], &le32, sizeof(u32));
1030
1031         if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
1032                                  &data) != DFX_K_SUCCESS) {
1033                 printk("%s: Could not read adapter factory MAC address!\n",
1034                        print_name);
1035                 return(DFX_K_FAILURE);
1036         }
1037         le32 = cpu_to_le32(data);
1038         memcpy(&bp->factory_mac_addr[4], &le32, sizeof(u16));
1039
1040         /*
1041          * Set current address to factory address
1042          *
1043          * Note: Node address override support is handled through
1044          *       dfx_ctl_set_mac_address.
1045          */
1046
1047         memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1048         if (dfx_bus_tc)
1049                 board_name = "DEFTA";
1050         if (dfx_bus_eisa)
1051                 board_name = "DEFEA";
1052         if (dfx_bus_pci)
1053                 board_name = "DEFPA";
1054         pr_info("%s: %s at %saddr = 0x%llx, IRQ = %d, "
1055                 "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
1056                 print_name, board_name, dfx_use_mmio ? "" : "I/O ",
1057                 (long long)bar_start, dev->irq,
1058                 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1059                 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1060
1061         /*
1062          * Get memory for descriptor block, consumer block, and other buffers
1063          * that need to be DMA read or written to by the adapter.
1064          */
1065
1066         alloc_size = sizeof(PI_DESCR_BLOCK) +
1067                                         PI_CMD_REQ_K_SIZE_MAX +
1068                                         PI_CMD_RSP_K_SIZE_MAX +
1069 #ifndef DYNAMIC_BUFFERS
1070                                         (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
1071 #endif
1072                                         sizeof(PI_CONSUMER_BLOCK) +
1073                                         (PI_ALIGN_K_DESC_BLK - 1);
1074         bp->kmalloced = top_v = dma_alloc_coherent(bp->bus_dev, alloc_size,
1075                                                    &bp->kmalloced_dma,
1076                                                    GFP_ATOMIC);
1077         if (top_v == NULL) {
1078                 printk("%s: Could not allocate memory for host buffers "
1079                        "and structures!\n", print_name);
1080                 return(DFX_K_FAILURE);
1081         }
1082         memset(top_v, 0, alloc_size);   /* zero out memory before continuing */
1083         top_p = bp->kmalloced_dma;      /* get physical address of buffer */
1084
1085         /*
1086          *  To guarantee the 8K alignment required for the descriptor block, 8K - 1
1087          *  plus the amount of memory needed was allocated.  The physical address
1088          *      is now 8K aligned.  By carving up the memory in a specific order,
1089          *  we'll guarantee the alignment requirements for all other structures.
1090          *
1091          *  Note: If the assumptions change regarding the non-paged, non-cached,
1092          *                physically contiguous nature of the memory block or the address
1093          *                alignments, then we'll need to implement a different algorithm
1094          *                for allocating the needed memory.
1095          */
1096
1097         curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK);
1098         curr_v = top_v + (curr_p - top_p);
1099
1100         /* Reserve space for descriptor block */
1101
1102         bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
1103         bp->descr_block_phys = curr_p;
1104         curr_v += sizeof(PI_DESCR_BLOCK);
1105         curr_p += sizeof(PI_DESCR_BLOCK);
1106
1107         /* Reserve space for command request buffer */
1108
1109         bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
1110         bp->cmd_req_phys = curr_p;
1111         curr_v += PI_CMD_REQ_K_SIZE_MAX;
1112         curr_p += PI_CMD_REQ_K_SIZE_MAX;
1113
1114         /* Reserve space for command response buffer */
1115
1116         bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
1117         bp->cmd_rsp_phys = curr_p;
1118         curr_v += PI_CMD_RSP_K_SIZE_MAX;
1119         curr_p += PI_CMD_RSP_K_SIZE_MAX;
1120
1121         /* Reserve space for the LLC host receive queue buffers */
1122
1123         bp->rcv_block_virt = curr_v;
1124         bp->rcv_block_phys = curr_p;
1125
1126 #ifndef DYNAMIC_BUFFERS
1127         curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
1128         curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
1129 #endif
1130
1131         /* Reserve space for the consumer block */
1132
1133         bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
1134         bp->cons_block_phys = curr_p;
1135
1136         /* Display virtual and physical addresses if debug driver */
1137
1138         DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n",
1139                    print_name,
1140                    (long)bp->descr_block_virt, bp->descr_block_phys);
1141         DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n",
1142                    print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
1143         DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n",
1144                    print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
1145         DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n",
1146                    print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
1147         DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n",
1148                    print_name, (long)bp->cons_block_virt, bp->cons_block_phys);
1149
1150         return(DFX_K_SUCCESS);
1151 }
1152
1153
1154 /*
1155  * =================
1156  * = dfx_adap_init =
1157  * =================
1158  *
1159  * Overview:
1160  *   Brings the adapter to the link avail/link unavailable state.
1161  *
1162  * Returns:
1163  *   Condition code
1164  *
1165  * Arguments:
1166  *   bp - pointer to board information
1167  *   get_buffers - non-zero if buffers to be allocated
1168  *
1169  * Functional Description:
1170  *   Issues the low-level firmware/hardware calls necessary to bring
1171  *   the adapter up, or to properly reset and restore adapter during
1172  *   run-time.
1173  *
1174  * Return Codes:
1175  *   DFX_K_SUCCESS - Adapter brought up successfully
1176  *   DFX_K_FAILURE - Adapter initialization failed
1177  *
1178  * Assumptions:
1179  *   bp->reset_type should be set to a valid reset type value before
1180  *   calling this routine.
1181  *
1182  * Side Effects:
1183  *   Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1184  *   upon a successful return of this routine.
1185  */
1186
1187 static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
1188         {
1189         DBG_printk("In dfx_adap_init...\n");
1190
1191         /* Disable PDQ interrupts first */
1192
1193         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1194
1195         /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1196
1197         if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
1198                 {
1199                 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
1200                 return(DFX_K_FAILURE);
1201                 }
1202
1203         /*
1204          * When the PDQ is reset, some false Type 0 interrupts may be pending,
1205          * so we'll acknowledge all Type 0 interrupts now before continuing.
1206          */
1207
1208         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
1209
1210         /*
1211          * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1212          *
1213          * Note: We only need to clear host copies of these registers.  The PDQ reset
1214          *       takes care of the on-board register values.
1215          */
1216
1217         bp->cmd_req_reg.lword   = 0;
1218         bp->cmd_rsp_reg.lword   = 0;
1219         bp->rcv_xmt_reg.lword   = 0;
1220
1221         /* Clear consumer block before going to DMA_AVAILABLE state */
1222
1223         memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1224
1225         /* Initialize the DMA Burst Size */
1226
1227         if (dfx_hw_port_ctrl_req(bp,
1228                                                         PI_PCTRL_M_SUB_CMD,
1229                                                         PI_SUB_CMD_K_BURST_SIZE_SET,
1230                                                         bp->burst_size,
1231                                                         NULL) != DFX_K_SUCCESS)
1232                 {
1233                 printk("%s: Could not set adapter burst size!\n", bp->dev->name);
1234                 return(DFX_K_FAILURE);
1235                 }
1236
1237         /*
1238          * Set base address of Consumer Block
1239          *
1240          * Assumption: 32-bit physical address of consumer block is 64 byte
1241          *                         aligned.  That is, bits 0-5 of the address must be zero.
1242          */
1243
1244         if (dfx_hw_port_ctrl_req(bp,
1245                                                         PI_PCTRL_M_CONS_BLOCK,
1246                                                         bp->cons_block_phys,
1247                                                         0,
1248                                                         NULL) != DFX_K_SUCCESS)
1249                 {
1250                 printk("%s: Could not set consumer block address!\n", bp->dev->name);
1251                 return(DFX_K_FAILURE);
1252                 }
1253
1254         /*
1255          * Set the base address of Descriptor Block and bring adapter
1256          * to DMA_AVAILABLE state.
1257          *
1258          * Note: We also set the literal and data swapping requirements
1259          *       in this command.
1260          *
1261          * Assumption: 32-bit physical address of descriptor block
1262          *       is 8Kbyte aligned.
1263          */
1264         if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
1265                                  (u32)(bp->descr_block_phys |
1266                                        PI_PDATA_A_INIT_M_BSWAP_INIT),
1267                                  0, NULL) != DFX_K_SUCCESS) {
1268                 printk("%s: Could not set descriptor block address!\n",
1269                        bp->dev->name);
1270                 return DFX_K_FAILURE;
1271         }
1272
1273         /* Set transmit flush timeout value */
1274
1275         bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
1276         bp->cmd_req_virt->char_set.item[0].item_code    = PI_ITEM_K_FLUSH_TIME;
1277         bp->cmd_req_virt->char_set.item[0].value                = 3;    /* 3 seconds */
1278         bp->cmd_req_virt->char_set.item[0].item_index   = 0;
1279         bp->cmd_req_virt->char_set.item[1].item_code    = PI_ITEM_K_EOL;
1280         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1281                 {
1282                 printk("%s: DMA command request failed!\n", bp->dev->name);
1283                 return(DFX_K_FAILURE);
1284                 }
1285
1286         /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1287
1288         bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
1289         bp->cmd_req_virt->snmp_set.item[0].item_code    = PI_ITEM_K_FDX_ENB_DIS;
1290         bp->cmd_req_virt->snmp_set.item[0].value                = bp->full_duplex_enb;
1291         bp->cmd_req_virt->snmp_set.item[0].item_index   = 0;
1292         bp->cmd_req_virt->snmp_set.item[1].item_code    = PI_ITEM_K_MAC_T_REQ;
1293         bp->cmd_req_virt->snmp_set.item[1].value                = bp->req_ttrt;
1294         bp->cmd_req_virt->snmp_set.item[1].item_index   = 0;
1295         bp->cmd_req_virt->snmp_set.item[2].item_code    = PI_ITEM_K_EOL;
1296         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1297                 {
1298                 printk("%s: DMA command request failed!\n", bp->dev->name);
1299                 return(DFX_K_FAILURE);
1300                 }
1301
1302         /* Initialize adapter CAM */
1303
1304         if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
1305                 {
1306                 printk("%s: Adapter CAM update failed!\n", bp->dev->name);
1307                 return(DFX_K_FAILURE);
1308                 }
1309
1310         /* Initialize adapter filters */
1311
1312         if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
1313                 {
1314                 printk("%s: Adapter filters update failed!\n", bp->dev->name);
1315                 return(DFX_K_FAILURE);
1316                 }
1317
1318         /*
1319          * Remove any existing dynamic buffers (i.e. if the adapter is being
1320          * reinitialized)
1321          */
1322
1323         if (get_buffers)
1324                 dfx_rcv_flush(bp);
1325
1326         /* Initialize receive descriptor block and produce buffers */
1327
1328         if (dfx_rcv_init(bp, get_buffers))
1329                 {
1330                 printk("%s: Receive buffer allocation failed\n", bp->dev->name);
1331                 if (get_buffers)
1332                         dfx_rcv_flush(bp);
1333                 return(DFX_K_FAILURE);
1334                 }
1335
1336         /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1337
1338         bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
1339         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1340                 {
1341                 printk("%s: Start command failed\n", bp->dev->name);
1342                 if (get_buffers)
1343                         dfx_rcv_flush(bp);
1344                 return(DFX_K_FAILURE);
1345                 }
1346
1347         /* Initialization succeeded, reenable PDQ interrupts */
1348
1349         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
1350         return(DFX_K_SUCCESS);
1351         }
1352
1353
1354 /*
1355  * ============
1356  * = dfx_open =
1357  * ============
1358  *
1359  * Overview:
1360  *   Opens the adapter
1361  *
1362  * Returns:
1363  *   Condition code
1364  *
1365  * Arguments:
1366  *   dev - pointer to device information
1367  *
1368  * Functional Description:
1369  *   This function brings the adapter to an operational state.
1370  *
1371  * Return Codes:
1372  *   0           - Adapter was successfully opened
1373  *   -EAGAIN - Could not register IRQ or adapter initialization failed
1374  *
1375  * Assumptions:
1376  *   This routine should only be called for a device that was
1377  *   initialized successfully.
1378  *
1379  * Side Effects:
1380  *   Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1381  *   if the open is successful.
1382  */
1383
1384 static int dfx_open(struct net_device *dev)
1385 {
1386         DFX_board_t *bp = netdev_priv(dev);
1387         int ret;
1388
1389         DBG_printk("In dfx_open...\n");
1390
1391         /* Register IRQ - support shared interrupts by passing device ptr */
1392
1393         ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name,
1394                           dev);
1395         if (ret) {
1396                 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
1397                 return ret;
1398         }
1399
1400         /*
1401          * Set current address to factory MAC address
1402          *
1403          * Note: We've already done this step in dfx_driver_init.
1404          *       However, it's possible that a user has set a node
1405          *               address override, then closed and reopened the
1406          *               adapter.  Unless we reset the device address field
1407          *               now, we'll continue to use the existing modified
1408          *               address.
1409          */
1410
1411         memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1412
1413         /* Clear local unicast/multicast address tables and counts */
1414
1415         memset(bp->uc_table, 0, sizeof(bp->uc_table));
1416         memset(bp->mc_table, 0, sizeof(bp->mc_table));
1417         bp->uc_count = 0;
1418         bp->mc_count = 0;
1419
1420         /* Disable promiscuous filter settings */
1421
1422         bp->ind_group_prom      = PI_FSTATE_K_BLOCK;
1423         bp->group_prom          = PI_FSTATE_K_BLOCK;
1424
1425         spin_lock_init(&bp->lock);
1426
1427         /* Reset and initialize adapter */
1428
1429         bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST;    /* skip self-test */
1430         if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
1431         {
1432                 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
1433                 free_irq(dev->irq, dev);
1434                 return -EAGAIN;
1435         }
1436
1437         /* Set device structure info */
1438         netif_start_queue(dev);
1439         return(0);
1440 }
1441
1442
1443 /*
1444  * =============
1445  * = dfx_close =
1446  * =============
1447  *
1448  * Overview:
1449  *   Closes the device/module.
1450  *
1451  * Returns:
1452  *   Condition code
1453  *
1454  * Arguments:
1455  *   dev - pointer to device information
1456  *
1457  * Functional Description:
1458  *   This routine closes the adapter and brings it to a safe state.
1459  *   The interrupt service routine is deregistered with the OS.
1460  *   The adapter can be opened again with another call to dfx_open().
1461  *
1462  * Return Codes:
1463  *   Always return 0.
1464  *
1465  * Assumptions:
1466  *   No further requests for this adapter are made after this routine is
1467  *   called.  dfx_open() can be called to reset and reinitialize the
1468  *   adapter.
1469  *
1470  * Side Effects:
1471  *   Adapter should be in DMA_UNAVAILABLE state upon completion of this
1472  *   routine.
1473  */
1474
1475 static int dfx_close(struct net_device *dev)
1476 {
1477         DFX_board_t *bp = netdev_priv(dev);
1478
1479         DBG_printk("In dfx_close...\n");
1480
1481         /* Disable PDQ interrupts first */
1482
1483         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1484
1485         /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1486
1487         (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1488
1489         /*
1490          * Flush any pending transmit buffers
1491          *
1492          * Note: It's important that we flush the transmit buffers
1493          *               BEFORE we clear our copy of the Type 2 register.
1494          *               Otherwise, we'll have no idea how many buffers
1495          *               we need to free.
1496          */
1497
1498         dfx_xmt_flush(bp);
1499
1500         /*
1501          * Clear Type 1 and Type 2 registers after adapter reset
1502          *
1503          * Note: Even though we're closing the adapter, it's
1504          *       possible that an interrupt will occur after
1505          *               dfx_close is called.  Without some assurance to
1506          *               the contrary we want to make sure that we don't
1507          *               process receive and transmit LLC frames and update
1508          *               the Type 2 register with bad information.
1509          */
1510
1511         bp->cmd_req_reg.lword   = 0;
1512         bp->cmd_rsp_reg.lword   = 0;
1513         bp->rcv_xmt_reg.lword   = 0;
1514
1515         /* Clear consumer block for the same reason given above */
1516
1517         memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1518
1519         /* Release all dynamically allocate skb in the receive ring. */
1520
1521         dfx_rcv_flush(bp);
1522
1523         /* Clear device structure flags */
1524
1525         netif_stop_queue(dev);
1526
1527         /* Deregister (free) IRQ */
1528
1529         free_irq(dev->irq, dev);
1530
1531         return(0);
1532 }
1533
1534
1535 /*
1536  * ======================
1537  * = dfx_int_pr_halt_id =
1538  * ======================
1539  *
1540  * Overview:
1541  *   Displays halt id's in string form.
1542  *
1543  * Returns:
1544  *   None
1545  *
1546  * Arguments:
1547  *   bp - pointer to board information
1548  *
1549  * Functional Description:
1550  *   Determine current halt id and display appropriate string.
1551  *
1552  * Return Codes:
1553  *   None
1554  *
1555  * Assumptions:
1556  *   None
1557  *
1558  * Side Effects:
1559  *   None
1560  */
1561
1562 static void dfx_int_pr_halt_id(DFX_board_t      *bp)
1563         {
1564         PI_UINT32       port_status;                    /* PDQ port status register value */
1565         PI_UINT32       halt_id;                                /* PDQ port status halt ID */
1566
1567         /* Read the latest port status */
1568
1569         dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1570
1571         /* Display halt state transition information */
1572
1573         halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
1574         switch (halt_id)
1575                 {
1576                 case PI_HALT_ID_K_SELFTEST_TIMEOUT:
1577                         printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
1578                         break;
1579
1580                 case PI_HALT_ID_K_PARITY_ERROR:
1581                         printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
1582                         break;
1583
1584                 case PI_HALT_ID_K_HOST_DIR_HALT:
1585                         printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
1586                         break;
1587
1588                 case PI_HALT_ID_K_SW_FAULT:
1589                         printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
1590                         break;
1591
1592                 case PI_HALT_ID_K_HW_FAULT:
1593                         printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
1594                         break;
1595
1596                 case PI_HALT_ID_K_PC_TRACE:
1597                         printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
1598                         break;
1599
1600                 case PI_HALT_ID_K_DMA_ERROR:
1601                         printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
1602                         break;
1603
1604                 case PI_HALT_ID_K_IMAGE_CRC_ERROR:
1605                         printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
1606                         break;
1607
1608                 case PI_HALT_ID_K_BUS_EXCEPTION:
1609                         printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
1610                         break;
1611
1612                 default:
1613                         printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
1614                         break;
1615                 }
1616         }
1617
1618
1619 /*
1620  * ==========================
1621  * = dfx_int_type_0_process =
1622  * ==========================
1623  *
1624  * Overview:
1625  *   Processes Type 0 interrupts.
1626  *
1627  * Returns:
1628  *   None
1629  *
1630  * Arguments:
1631  *   bp - pointer to board information
1632  *
1633  * Functional Description:
1634  *   Processes all enabled Type 0 interrupts.  If the reason for the interrupt
1635  *   is a serious fault on the adapter, then an error message is displayed
1636  *   and the adapter is reset.
1637  *
1638  *   One tricky potential timing window is the rapid succession of "link avail"
1639  *   "link unavail" state change interrupts.  The acknowledgement of the Type 0
1640  *   interrupt must be done before reading the state from the Port Status
1641  *   register.  This is true because a state change could occur after reading
1642  *   the data, but before acknowledging the interrupt.  If this state change
1643  *   does happen, it would be lost because the driver is using the old state,
1644  *   and it will never know about the new state because it subsequently
1645  *   acknowledges the state change interrupt.
1646  *
1647  *          INCORRECT                                      CORRECT
1648  *      read type 0 int reasons                   read type 0 int reasons
1649  *      read adapter state                        ack type 0 interrupts
1650  *      ack type 0 interrupts                     read adapter state
1651  *      ... process interrupt ...                 ... process interrupt ...
1652  *
1653  * Return Codes:
1654  *   None
1655  *
1656  * Assumptions:
1657  *   None
1658  *
1659  * Side Effects:
1660  *   An adapter reset may occur if the adapter has any Type 0 error interrupts
1661  *   or if the port status indicates that the adapter is halted.  The driver
1662  *   is responsible for reinitializing the adapter with the current CAM
1663  *   contents and adapter filter settings.
1664  */
1665
1666 static void dfx_int_type_0_process(DFX_board_t  *bp)
1667
1668         {
1669         PI_UINT32       type_0_status;          /* Host Interrupt Type 0 register */
1670         PI_UINT32       state;                          /* current adap state (from port status) */
1671
1672         /*
1673          * Read host interrupt Type 0 register to determine which Type 0
1674          * interrupts are pending.  Immediately write it back out to clear
1675          * those interrupts.
1676          */
1677
1678         dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
1679         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
1680
1681         /* Check for Type 0 error interrupts */
1682
1683         if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
1684                                                         PI_TYPE_0_STAT_M_PM_PAR_ERR |
1685                                                         PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1686                 {
1687                 /* Check for Non-Existent Memory error */
1688
1689                 if (type_0_status & PI_TYPE_0_STAT_M_NXM)
1690                         printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
1691
1692                 /* Check for Packet Memory Parity error */
1693
1694                 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
1695                         printk("%s: Packet Memory Parity Error\n", bp->dev->name);
1696
1697                 /* Check for Host Bus Parity error */
1698
1699                 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
1700                         printk("%s: Host Bus Parity Error\n", bp->dev->name);
1701
1702                 /* Reset adapter and bring it back on-line */
1703
1704                 bp->link_available = PI_K_FALSE;        /* link is no longer available */
1705                 bp->reset_type = 0;                                     /* rerun on-board diagnostics */
1706                 printk("%s: Resetting adapter...\n", bp->dev->name);
1707                 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1708                         {
1709                         printk("%s: Adapter reset failed!  Disabling adapter interrupts.\n", bp->dev->name);
1710                         dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1711                         return;
1712                         }
1713                 printk("%s: Adapter reset successful!\n", bp->dev->name);
1714                 return;
1715                 }
1716
1717         /* Check for transmit flush interrupt */
1718
1719         if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
1720                 {
1721                 /* Flush any pending xmt's and acknowledge the flush interrupt */
1722
1723                 bp->link_available = PI_K_FALSE;                /* link is no longer available */
1724                 dfx_xmt_flush(bp);                                              /* flush any outstanding packets */
1725                 (void) dfx_hw_port_ctrl_req(bp,
1726                                                                         PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1727                                                                         0,
1728                                                                         0,
1729                                                                         NULL);
1730                 }
1731
1732         /* Check for adapter state change */
1733
1734         if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
1735                 {
1736                 /* Get latest adapter state */
1737
1738                 state = dfx_hw_adap_state_rd(bp);       /* get adapter state */
1739                 if (state == PI_STATE_K_HALTED)
1740                         {
1741                         /*
1742                          * Adapter has transitioned to HALTED state, try to reset
1743                          * adapter to bring it back on-line.  If reset fails,
1744                          * leave the adapter in the broken state.
1745                          */
1746
1747                         printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
1748                         dfx_int_pr_halt_id(bp);                 /* display halt id as string */
1749
1750                         /* Reset adapter and bring it back on-line */
1751
1752                         bp->link_available = PI_K_FALSE;        /* link is no longer available */
1753                         bp->reset_type = 0;                                     /* rerun on-board diagnostics */
1754                         printk("%s: Resetting adapter...\n", bp->dev->name);
1755                         if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1756                                 {
1757                                 printk("%s: Adapter reset failed!  Disabling adapter interrupts.\n", bp->dev->name);
1758                                 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1759                                 return;
1760                                 }
1761                         printk("%s: Adapter reset successful!\n", bp->dev->name);
1762                         }
1763                 else if (state == PI_STATE_K_LINK_AVAIL)
1764                         {
1765                         bp->link_available = PI_K_TRUE;         /* set link available flag */
1766                         }
1767                 }
1768         }
1769
1770
1771 /*
1772  * ==================
1773  * = dfx_int_common =
1774  * ==================
1775  *
1776  * Overview:
1777  *   Interrupt service routine (ISR)
1778  *
1779  * Returns:
1780  *   None
1781  *
1782  * Arguments:
1783  *   bp - pointer to board information
1784  *
1785  * Functional Description:
1786  *   This is the ISR which processes incoming adapter interrupts.
1787  *
1788  * Return Codes:
1789  *   None
1790  *
1791  * Assumptions:
1792  *   This routine assumes PDQ interrupts have not been disabled.
1793  *   When interrupts are disabled at the PDQ, the Port Status register
1794  *   is automatically cleared.  This routine uses the Port Status
1795  *   register value to determine whether a Type 0 interrupt occurred,
1796  *   so it's important that adapter interrupts are not normally
1797  *   enabled/disabled at the PDQ.
1798  *
1799  *   It's vital that this routine is NOT reentered for the
1800  *   same board and that the OS is not in another section of
1801  *   code (eg. dfx_xmt_queue_pkt) for the same board on a
1802  *   different thread.
1803  *
1804  * Side Effects:
1805  *   Pending interrupts are serviced.  Depending on the type of
1806  *   interrupt, acknowledging and clearing the interrupt at the
1807  *   PDQ involves writing a register to clear the interrupt bit
1808  *   or updating completion indices.
1809  */
1810
1811 static void dfx_int_common(struct net_device *dev)
1812 {
1813         DFX_board_t *bp = netdev_priv(dev);
1814         PI_UINT32       port_status;            /* Port Status register */
1815
1816         /* Process xmt interrupts - frequent case, so always call this routine */
1817
1818         if(dfx_xmt_done(bp))                            /* free consumed xmt packets */
1819                 netif_wake_queue(dev);
1820
1821         /* Process rcv interrupts - frequent case, so always call this routine */
1822
1823         dfx_rcv_queue_process(bp);              /* service received LLC frames */
1824
1825         /*
1826          * Transmit and receive producer and completion indices are updated on the
1827          * adapter by writing to the Type 2 Producer register.  Since the frequent
1828          * case is that we'll be processing either LLC transmit or receive buffers,
1829          * we'll optimize I/O writes by doing a single register write here.
1830          */
1831
1832         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
1833
1834         /* Read PDQ Port Status register to find out which interrupts need processing */
1835
1836         dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1837
1838         /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1839
1840         if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
1841                 dfx_int_type_0_process(bp);     /* process Type 0 interrupts */
1842         }
1843
1844
1845 /*
1846  * =================
1847  * = dfx_interrupt =
1848  * =================
1849  *
1850  * Overview:
1851  *   Interrupt processing routine
1852  *
1853  * Returns:
1854  *   Whether a valid interrupt was seen.
1855  *
1856  * Arguments:
1857  *   irq        - interrupt vector
1858  *   dev_id     - pointer to device information
1859  *
1860  * Functional Description:
1861  *   This routine calls the interrupt processing routine for this adapter.  It
1862  *   disables and reenables adapter interrupts, as appropriate.  We can support
1863  *   shared interrupts since the incoming dev_id pointer provides our device
1864  *   structure context.
1865  *
1866  * Return Codes:
1867  *   IRQ_HANDLED - an IRQ was handled.
1868  *   IRQ_NONE    - no IRQ was handled.
1869  *
1870  * Assumptions:
1871  *   The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1872  *   on Intel-based systems) is done by the operating system outside this
1873  *   routine.
1874  *
1875  *       System interrupts are enabled through this call.
1876  *
1877  * Side Effects:
1878  *   Interrupts are disabled, then reenabled at the adapter.
1879  */
1880
1881 static irqreturn_t dfx_interrupt(int irq, void *dev_id)
1882 {
1883         struct net_device *dev = dev_id;
1884         DFX_board_t *bp = netdev_priv(dev);
1885         struct device *bdev = bp->bus_dev;
1886         int dfx_bus_pci = DFX_BUS_PCI(bdev);
1887         int dfx_bus_eisa = DFX_BUS_EISA(bdev);
1888         int dfx_bus_tc = DFX_BUS_TC(bdev);
1889
1890         /* Service adapter interrupts */
1891
1892         if (dfx_bus_pci) {
1893                 u32 status;
1894
1895                 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status);
1896                 if (!(status & PFI_STATUS_M_PDQ_INT))
1897                         return IRQ_NONE;
1898
1899                 spin_lock(&bp->lock);
1900
1901                 /* Disable PDQ-PFI interrupts at PFI */
1902                 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1903                                     PFI_MODE_M_DMA_ENB);
1904
1905                 /* Call interrupt service routine for this adapter */
1906                 dfx_int_common(dev);
1907
1908                 /* Clear PDQ interrupt status bit and reenable interrupts */
1909                 dfx_port_write_long(bp, PFI_K_REG_STATUS,
1910                                     PFI_STATUS_M_PDQ_INT);
1911                 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1912                                     (PFI_MODE_M_PDQ_INT_ENB |
1913                                      PFI_MODE_M_DMA_ENB));
1914
1915                 spin_unlock(&bp->lock);
1916         }
1917         if (dfx_bus_eisa) {
1918                 unsigned long base_addr = to_eisa_device(bdev)->base_addr;
1919                 u8 status;
1920
1921                 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
1922                 if (!(status & PI_CONFIG_STAT_0_M_PEND))
1923                         return IRQ_NONE;
1924
1925                 spin_lock(&bp->lock);
1926
1927                 /* Disable interrupts at the ESIC */
1928                 status &= ~PI_CONFIG_STAT_0_M_INT_ENB;
1929                 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status);
1930
1931                 /* Call interrupt service routine for this adapter */
1932                 dfx_int_common(dev);
1933
1934                 /* Reenable interrupts at the ESIC */
1935                 status = inb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0);
1936                 status |= PI_CONFIG_STAT_0_M_INT_ENB;
1937                 outb(base_addr + PI_ESIC_K_IO_CONFIG_STAT_0, status);
1938
1939                 spin_unlock(&bp->lock);
1940         }
1941         if (dfx_bus_tc) {
1942                 u32 status;
1943
1944                 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &status);
1945                 if (!(status & (PI_PSTATUS_M_RCV_DATA_PENDING |
1946                                 PI_PSTATUS_M_XMT_DATA_PENDING |
1947                                 PI_PSTATUS_M_SMT_HOST_PENDING |
1948                                 PI_PSTATUS_M_UNSOL_PENDING |
1949                                 PI_PSTATUS_M_CMD_RSP_PENDING |
1950                                 PI_PSTATUS_M_CMD_REQ_PENDING |
1951                                 PI_PSTATUS_M_TYPE_0_PENDING)))
1952                         return IRQ_NONE;
1953
1954                 spin_lock(&bp->lock);
1955
1956                 /* Call interrupt service routine for this adapter */
1957                 dfx_int_common(dev);
1958
1959                 spin_unlock(&bp->lock);
1960         }
1961
1962         return IRQ_HANDLED;
1963 }
1964
1965
1966 /*
1967  * =====================
1968  * = dfx_ctl_get_stats =
1969  * =====================
1970  *
1971  * Overview:
1972  *   Get statistics for FDDI adapter
1973  *
1974  * Returns:
1975  *   Pointer to FDDI statistics structure
1976  *
1977  * Arguments:
1978  *   dev - pointer to device information
1979  *
1980  * Functional Description:
1981  *   Gets current MIB objects from adapter, then
1982  *   returns FDDI statistics structure as defined
1983  *   in if_fddi.h.
1984  *
1985  *   Note: Since the FDDI statistics structure is
1986  *   still new and the device structure doesn't
1987  *   have an FDDI-specific get statistics handler,
1988  *   we'll return the FDDI statistics structure as
1989  *   a pointer to an Ethernet statistics structure.
1990  *   That way, at least the first part of the statistics
1991  *   structure can be decoded properly, and it allows
1992  *   "smart" applications to perform a second cast to
1993  *   decode the FDDI-specific statistics.
1994  *
1995  *   We'll have to pay attention to this routine as the
1996  *   device structure becomes more mature and LAN media
1997  *   independent.
1998  *
1999  * Return Codes:
2000  *   None
2001  *
2002  * Assumptions:
2003  *   None
2004  *
2005  * Side Effects:
2006  *   None
2007  */
2008
2009 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
2010         {
2011         DFX_board_t *bp = netdev_priv(dev);
2012
2013         /* Fill the bp->stats structure with driver-maintained counters */
2014
2015         bp->stats.gen.rx_packets = bp->rcv_total_frames;
2016         bp->stats.gen.tx_packets = bp->xmt_total_frames;
2017         bp->stats.gen.rx_bytes   = bp->rcv_total_bytes;
2018         bp->stats.gen.tx_bytes   = bp->xmt_total_bytes;
2019         bp->stats.gen.rx_errors  = bp->rcv_crc_errors +
2020                                    bp->rcv_frame_status_errors +
2021                                    bp->rcv_length_errors;
2022         bp->stats.gen.tx_errors  = bp->xmt_length_errors;
2023         bp->stats.gen.rx_dropped = bp->rcv_discards;
2024         bp->stats.gen.tx_dropped = bp->xmt_discards;
2025         bp->stats.gen.multicast  = bp->rcv_multicast_frames;
2026         bp->stats.gen.collisions = 0;           /* always zero (0) for FDDI */
2027
2028         /* Get FDDI SMT MIB objects */
2029
2030         bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
2031         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2032                 return((struct net_device_stats *) &bp->stats);
2033
2034         /* Fill the bp->stats structure with the SMT MIB object values */
2035
2036         memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
2037         bp->stats.smt_op_version_id                                     = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
2038         bp->stats.smt_hi_version_id                                     = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
2039         bp->stats.smt_lo_version_id                                     = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
2040         memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
2041         bp->stats.smt_mib_version_id                            = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
2042         bp->stats.smt_mac_cts                                           = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
2043         bp->stats.smt_non_master_cts                            = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
2044         bp->stats.smt_master_cts                                        = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
2045         bp->stats.smt_available_paths                           = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
2046         bp->stats.smt_config_capabilities                       = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
2047         bp->stats.smt_config_policy                                     = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
2048         bp->stats.smt_connection_policy                         = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
2049         bp->stats.smt_t_notify                                          = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
2050         bp->stats.smt_stat_rpt_policy                           = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
2051         bp->stats.smt_trace_max_expiration                      = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
2052         bp->stats.smt_bypass_present                            = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
2053         bp->stats.smt_ecm_state                                         = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
2054         bp->stats.smt_cf_state                                          = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
2055         bp->stats.smt_remote_disconnect_flag            = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
2056         bp->stats.smt_station_status                            = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
2057         bp->stats.smt_peer_wrap_flag                            = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
2058         bp->stats.smt_time_stamp                                        = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
2059         bp->stats.smt_transition_time_stamp                     = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
2060         bp->stats.mac_frame_status_functions            = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
2061         bp->stats.mac_t_max_capability                          = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
2062         bp->stats.mac_tvx_capability                            = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
2063         bp->stats.mac_available_paths                           = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
2064         bp->stats.mac_current_path                                      = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
2065         memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
2066         memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
2067         memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
2068         memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
2069         bp->stats.mac_dup_address_test                          = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
2070         bp->stats.mac_requested_paths                           = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
2071         bp->stats.mac_downstream_port_type                      = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
2072         memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
2073         bp->stats.mac_t_req                                                     = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
2074         bp->stats.mac_t_neg                                                     = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
2075         bp->stats.mac_t_max                                                     = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
2076         bp->stats.mac_tvx_value                                         = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
2077         bp->stats.mac_frame_error_threshold                     = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
2078         bp->stats.mac_frame_error_ratio                         = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
2079         bp->stats.mac_rmt_state                                         = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
2080         bp->stats.mac_da_flag                                           = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
2081         bp->stats.mac_una_da_flag                                       = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
2082         bp->stats.mac_frame_error_flag                          = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
2083         bp->stats.mac_ma_unitdata_available                     = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
2084         bp->stats.mac_hardware_present                          = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
2085         bp->stats.mac_ma_unitdata_enable                        = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
2086         bp->stats.path_tvx_lower_bound                          = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
2087         bp->stats.path_t_max_lower_bound                        = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
2088         bp->stats.path_max_t_req                                        = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
2089         memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
2090         bp->stats.port_my_type[0]                                       = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
2091         bp->stats.port_my_type[1]                                       = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
2092         bp->stats.port_neighbor_type[0]                         = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
2093         bp->stats.port_neighbor_type[1]                         = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
2094         bp->stats.port_connection_policies[0]           = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
2095         bp->stats.port_connection_policies[1]           = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
2096         bp->stats.port_mac_indicated[0]                         = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
2097         bp->stats.port_mac_indicated[1]                         = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
2098         bp->stats.port_current_path[0]                          = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
2099         bp->stats.port_current_path[1]                          = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
2100         memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
2101         memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
2102         bp->stats.port_mac_placement[0]                         = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
2103         bp->stats.port_mac_placement[1]                         = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
2104         bp->stats.port_available_paths[0]                       = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
2105         bp->stats.port_available_paths[1]                       = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
2106         bp->stats.port_pmd_class[0]                                     = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
2107         bp->stats.port_pmd_class[1]                                     = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
2108         bp->stats.port_connection_capabilities[0]       = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
2109         bp->stats.port_connection_capabilities[1]       = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
2110         bp->stats.port_bs_flag[0]                                       = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
2111         bp->stats.port_bs_flag[1]                                       = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
2112         bp->stats.port_ler_estimate[0]                          = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
2113         bp->stats.port_ler_estimate[1]                          = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
2114         bp->stats.port_ler_cutoff[0]                            = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
2115         bp->stats.port_ler_cutoff[1]                            = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
2116         bp->stats.port_ler_alarm[0]                                     = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
2117         bp->stats.port_ler_alarm[1]                                     = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
2118         bp->stats.port_connect_state[0]                         = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
2119         bp->stats.port_connect_state[1]                         = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
2120         bp->stats.port_pcm_state[0]                                     = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
2121         bp->stats.port_pcm_state[1]                                     = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
2122         bp->stats.port_pc_withhold[0]                           = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
2123         bp->stats.port_pc_withhold[1]                           = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
2124         bp->stats.port_ler_flag[0]                                      = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
2125         bp->stats.port_ler_flag[1]                                      = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
2126         bp->stats.port_hardware_present[0]                      = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
2127         bp->stats.port_hardware_present[1]                      = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
2128
2129         /* Get FDDI counters */
2130
2131         bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
2132         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2133                 return((struct net_device_stats *) &bp->stats);
2134
2135         /* Fill the bp->stats structure with the FDDI counter values */
2136
2137         bp->stats.mac_frame_cts                         = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
2138         bp->stats.mac_copied_cts                        = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
2139         bp->stats.mac_transmit_cts                      = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
2140         bp->stats.mac_error_cts                         = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
2141         bp->stats.mac_lost_cts                          = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
2142         bp->stats.port_lct_fail_cts[0]          = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
2143         bp->stats.port_lct_fail_cts[1]          = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
2144         bp->stats.port_lem_reject_cts[0]        = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
2145         bp->stats.port_lem_reject_cts[1]        = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
2146         bp->stats.port_lem_cts[0]                       = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
2147         bp->stats.port_lem_cts[1]                       = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
2148
2149         return((struct net_device_stats *) &bp->stats);
2150         }
2151
2152
2153 /*
2154  * ==============================
2155  * = dfx_ctl_set_multicast_list =
2156  * ==============================
2157  *
2158  * Overview:
2159  *   Enable/Disable LLC frame promiscuous mode reception
2160  *   on the adapter and/or update multicast address table.
2161  *
2162  * Returns:
2163  *   None
2164  *
2165  * Arguments:
2166  *   dev - pointer to device information
2167  *
2168  * Functional Description:
2169  *   This routine follows a fairly simple algorithm for setting the
2170  *   adapter filters and CAM:
2171  *
2172  *              if IFF_PROMISC flag is set
2173  *                      enable LLC individual/group promiscuous mode
2174  *              else
2175  *                      disable LLC individual/group promiscuous mode
2176  *                      if number of incoming multicast addresses >
2177  *                                      (CAM max size - number of unicast addresses in CAM)
2178  *                              enable LLC group promiscuous mode
2179  *                              set driver-maintained multicast address count to zero
2180  *                      else
2181  *                              disable LLC group promiscuous mode
2182  *                              set driver-maintained multicast address count to incoming count
2183  *                      update adapter CAM
2184  *              update adapter filters
2185  *
2186  * Return Codes:
2187  *   None
2188  *
2189  * Assumptions:
2190  *   Multicast addresses are presented in canonical (LSB) format.
2191  *
2192  * Side Effects:
2193  *   On-board adapter CAM and filters are updated.
2194  */
2195
2196 static void dfx_ctl_set_multicast_list(struct net_device *dev)
2197 {
2198         DFX_board_t *bp = netdev_priv(dev);
2199         int                                     i;                      /* used as index in for loop */
2200         struct dev_mc_list      *dmi;           /* ptr to multicast addr entry */
2201
2202         /* Enable LLC frame promiscuous mode, if necessary */
2203
2204         if (dev->flags & IFF_PROMISC)
2205                 bp->ind_group_prom = PI_FSTATE_K_PASS;          /* Enable LLC ind/group prom mode */
2206
2207         /* Else, update multicast address table */
2208
2209         else
2210                 {
2211                 bp->ind_group_prom = PI_FSTATE_K_BLOCK;         /* Disable LLC ind/group prom mode */
2212                 /*
2213                  * Check whether incoming multicast address count exceeds table size
2214                  *
2215                  * Note: The adapters utilize an on-board 64 entry CAM for
2216                  *       supporting perfect filtering of multicast packets
2217                  *               and bridge functions when adding unicast addresses.
2218                  *               There is no hash function available.  To support
2219                  *               additional multicast addresses, the all multicast
2220                  *               filter (LLC group promiscuous mode) must be enabled.
2221                  *
2222                  *               The firmware reserves two CAM entries for SMT-related
2223                  *               multicast addresses, which leaves 62 entries available.
2224                  *               The following code ensures that we're not being asked
2225                  *               to add more than 62 addresses to the CAM.  If we are,
2226                  *               the driver will enable the all multicast filter.
2227                  *               Should the number of multicast addresses drop below
2228                  *               the high water mark, the filter will be disabled and
2229                  *               perfect filtering will be used.
2230                  */
2231
2232                 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
2233                         {
2234                         bp->group_prom  = PI_FSTATE_K_PASS;             /* Enable LLC group prom mode */
2235                         bp->mc_count    = 0;                                    /* Don't add mc addrs to CAM */
2236                         }
2237                 else
2238                         {
2239                         bp->group_prom  = PI_FSTATE_K_BLOCK;    /* Disable LLC group prom mode */
2240                         bp->mc_count    = dev->mc_count;                /* Add mc addrs to CAM */
2241                         }
2242
2243                 /* Copy addresses to multicast address table, then update adapter CAM */
2244
2245                 dmi = dev->mc_list;                             /* point to first multicast addr */
2246                 for (i=0; i < bp->mc_count; i++)
2247                         {
2248                         memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN);
2249                         dmi = dmi->next;                        /* point to next multicast addr */
2250                         }
2251                 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2252                         {
2253                         DBG_printk("%s: Could not update multicast address table!\n", dev->name);
2254                         }
2255                 else
2256                         {
2257                         DBG_printk("%s: Multicast address table updated!  Added %d addresses.\n", dev->name, bp->mc_count);
2258                         }
2259                 }
2260
2261         /* Update adapter filters */
2262
2263         if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2264                 {
2265                 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2266                 }
2267         else
2268                 {
2269                 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2270                 }
2271         }
2272
2273
2274 /*
2275  * ===========================
2276  * = dfx_ctl_set_mac_address =
2277  * ===========================
2278  *
2279  * Overview:
2280  *   Add node address override (unicast address) to adapter
2281  *   CAM and update dev_addr field in device table.
2282  *
2283  * Returns:
2284  *   None
2285  *
2286  * Arguments:
2287  *   dev  - pointer to device information
2288  *   addr - pointer to sockaddr structure containing unicast address to add
2289  *
2290  * Functional Description:
2291  *   The adapter supports node address overrides by adding one or more
2292  *   unicast addresses to the adapter CAM.  This is similar to adding
2293  *   multicast addresses.  In this routine we'll update the driver and
2294  *   device structures with the new address, then update the adapter CAM
2295  *   to ensure that the adapter will copy and strip frames destined and
2296  *   sourced by that address.
2297  *
2298  * Return Codes:
2299  *   Always returns zero.
2300  *
2301  * Assumptions:
2302  *   The address pointed to by addr->sa_data is a valid unicast
2303  *   address and is presented in canonical (LSB) format.
2304  *
2305  * Side Effects:
2306  *   On-board adapter CAM is updated.  On-board adapter filters
2307  *   may be updated.
2308  */
2309
2310 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
2311         {
2312         struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
2313         DFX_board_t *bp = netdev_priv(dev);
2314
2315         /* Copy unicast address to driver-maintained structs and update count */
2316
2317         memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN);        /* update device struct */
2318         memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN);     /* update driver struct */
2319         bp->uc_count = 1;
2320
2321         /*
2322          * Verify we're not exceeding the CAM size by adding unicast address
2323          *
2324          * Note: It's possible that before entering this routine we've
2325          *       already filled the CAM with 62 multicast addresses.
2326          *               Since we need to place the node address override into
2327          *               the CAM, we have to check to see that we're not
2328          *               exceeding the CAM size.  If we are, we have to enable
2329          *               the LLC group (multicast) promiscuous mode filter as
2330          *               in dfx_ctl_set_multicast_list.
2331          */
2332
2333         if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
2334                 {
2335                 bp->group_prom  = PI_FSTATE_K_PASS;             /* Enable LLC group prom mode */
2336                 bp->mc_count    = 0;                                    /* Don't add mc addrs to CAM */
2337
2338                 /* Update adapter filters */
2339
2340                 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2341                         {
2342                         DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2343                         }
2344                 else
2345                         {
2346                         DBG_printk("%s: Adapter filters updated!\n", dev->name);
2347                         }
2348                 }
2349
2350         /* Update adapter CAM with new unicast address */
2351
2352         if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2353                 {
2354                 DBG_printk("%s: Could not set new MAC address!\n", dev->name);
2355                 }
2356         else
2357                 {
2358                 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
2359                 }
2360         return(0);                      /* always return zero */
2361         }
2362
2363
2364 /*
2365  * ======================
2366  * = dfx_ctl_update_cam =
2367  * ======================
2368  *
2369  * Overview:
2370  *   Procedure to update adapter CAM (Content Addressable Memory)
2371  *   with desired unicast and multicast address entries.
2372  *
2373  * Returns:
2374  *   Condition code
2375  *
2376  * Arguments:
2377  *   bp - pointer to board information
2378  *
2379  * Functional Description:
2380  *   Updates adapter CAM with current contents of board structure
2381  *   unicast and multicast address tables.  Since there are only 62
2382  *   free entries in CAM, this routine ensures that the command
2383  *   request buffer is not overrun.
2384  *
2385  * Return Codes:
2386  *   DFX_K_SUCCESS - Request succeeded
2387  *   DFX_K_FAILURE - Request failed
2388  *
2389  * Assumptions:
2390  *   All addresses being added (unicast and multicast) are in canonical
2391  *   order.
2392  *
2393  * Side Effects:
2394  *   On-board adapter CAM is updated.
2395  */
2396
2397 static int dfx_ctl_update_cam(DFX_board_t *bp)
2398         {
2399         int                     i;                              /* used as index */
2400         PI_LAN_ADDR     *p_addr;                /* pointer to CAM entry */
2401
2402         /*
2403          * Fill in command request information
2404          *
2405          * Note: Even though both the unicast and multicast address
2406          *       table entries are stored as contiguous 6 byte entries,
2407          *               the firmware address filter set command expects each
2408          *               entry to be two longwords (8 bytes total).  We must be
2409          *               careful to only copy the six bytes of each unicast and
2410          *               multicast table entry into each command entry.  This
2411          *               is also why we must first clear the entire command
2412          *               request buffer.
2413          */
2414
2415         memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX);     /* first clear buffer */
2416         bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
2417         p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
2418
2419         /* Now add unicast addresses to command request buffer, if any */
2420
2421         for (i=0; i < (int)bp->uc_count; i++)
2422                 {
2423                 if (i < PI_CMD_ADDR_FILTER_K_SIZE)
2424                         {
2425                         memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2426                         p_addr++;                       /* point to next command entry */
2427                         }
2428                 }
2429
2430         /* Now add multicast addresses to command request buffer, if any */
2431
2432         for (i=0; i < (int)bp->mc_count; i++)
2433                 {
2434                 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
2435                         {
2436                         memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2437                         p_addr++;                       /* point to next command entry */
2438                         }
2439                 }
2440
2441         /* Issue command to update adapter CAM, then return */
2442
2443         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2444                 return(DFX_K_FAILURE);
2445         return(DFX_K_SUCCESS);
2446         }
2447
2448
2449 /*
2450  * ==========================
2451  * = dfx_ctl_update_filters =
2452  * ==========================
2453  *
2454  * Overview:
2455  *   Procedure to update adapter filters with desired
2456  *   filter settings.
2457  *
2458  * Returns:
2459  *   Condition code
2460  *
2461  * Arguments:
2462  *   bp - pointer to board information
2463  *
2464  * Functional Description:
2465  *   Enables or disables filter using current filter settings.
2466  *
2467  * Return Codes:
2468  *   DFX_K_SUCCESS - Request succeeded.
2469  *   DFX_K_FAILURE - Request failed.
2470  *
2471  * Assumptions:
2472  *   We must always pass up packets destined to the broadcast
2473  *   address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2474  *   broadcast filter enabled.
2475  *
2476  * Side Effects:
2477  *   On-board adapter filters are updated.
2478  */
2479
2480 static int dfx_ctl_update_filters(DFX_board_t *bp)
2481         {
2482         int     i = 0;                                  /* used as index */
2483
2484         /* Fill in command request information */
2485
2486         bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
2487
2488         /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2489
2490         bp->cmd_req_virt->filter_set.item[i].item_code  = PI_ITEM_K_BROADCAST;
2491         bp->cmd_req_virt->filter_set.item[i++].value    = PI_FSTATE_K_PASS;
2492
2493         /* Initialize LLC Individual/Group Promiscuous filter */
2494
2495         bp->cmd_req_virt->filter_set.item[i].item_code  = PI_ITEM_K_IND_GROUP_PROM;
2496         bp->cmd_req_virt->filter_set.item[i++].value    = bp->ind_group_prom;
2497
2498         /* Initialize LLC Group Promiscuous filter */
2499
2500         bp->cmd_req_virt->filter_set.item[i].item_code  = PI_ITEM_K_GROUP_PROM;
2501         bp->cmd_req_virt->filter_set.item[i++].value    = bp->group_prom;
2502
2503         /* Terminate the item code list */
2504
2505         bp->cmd_req_virt->filter_set.item[i].item_code  = PI_ITEM_K_EOL;
2506
2507         /* Issue command to update adapter filters, then return */
2508
2509         if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2510                 return(DFX_K_FAILURE);
2511         return(DFX_K_SUCCESS);
2512         }
2513
2514
2515 /*
2516  * ======================
2517  * = dfx_hw_dma_cmd_req =
2518  * ======================
2519  *
2520  * Overview:
2521  *   Sends PDQ DMA command to adapter firmware
2522  *
2523  * Returns:
2524  *   Condition code
2525  *
2526  * Arguments:
2527  *   bp - pointer to board information
2528  *
2529  * Functional Description:
2530  *   The command request and response buffers are posted to the adapter in the manner
2531  *   described in the PDQ Port Specification:
2532  *
2533  *              1. Command Response Buffer is posted to adapter.
2534  *              2. Command Request Buffer is posted to adapter.
2535  *              3. Command Request consumer index is polled until it indicates that request
2536  *         buffer has been DMA'd to adapter.
2537  *              4. Command Response consumer index is polled until it indicates that response
2538  *         buffer has been DMA'd from adapter.
2539  *
2540  *   This ordering ensures that a response buffer is already available for the firmware
2541  *   to use once it's done processing the request buffer.
2542  *
2543  * Return Codes:
2544  *   DFX_K_SUCCESS        - DMA command succeeded
2545  *       DFX_K_OUTSTATE   - Adapter is NOT in proper state
2546  *   DFX_K_HW_TIMEOUT - DMA command timed out
2547  *
2548  * Assumptions:
2549  *   Command request buffer has already been filled with desired DMA command.
2550  *
2551  * Side Effects:
2552  *   None
2553  */
2554
2555 static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
2556         {
2557         int status;                     /* adapter status */
2558         int timeout_cnt;        /* used in for loops */
2559
2560         /* Make sure the adapter is in a state that we can issue the DMA command in */
2561
2562         status = dfx_hw_adap_state_rd(bp);
2563         if ((status == PI_STATE_K_RESET)                ||
2564                 (status == PI_STATE_K_HALTED)           ||
2565                 (status == PI_STATE_K_DMA_UNAVAIL)      ||
2566                 (status == PI_STATE_K_UPGRADE))
2567                 return(DFX_K_OUTSTATE);
2568
2569         /* Put response buffer on the command response queue */
2570
2571         bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2572                         ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2573         bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
2574
2575         /* Bump (and wrap) the producer index and write out to register */
2576
2577         bp->cmd_rsp_reg.index.prod += 1;
2578         bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2579         dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2580
2581         /* Put request buffer on the command request queue */
2582
2583         bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
2584                         PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
2585         bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
2586
2587         /* Bump (and wrap) the producer index and write out to register */
2588
2589         bp->cmd_req_reg.index.prod += 1;
2590         bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2591         dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2592
2593         /*
2594          * Here we wait for the command request consumer index to be equal
2595          * to the producer, indicating that the adapter has DMAed the request.
2596          */
2597
2598         for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2599                 {
2600                 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
2601                         break;
2602                 udelay(100);                    /* wait for 100 microseconds */
2603                 }
2604         if (timeout_cnt == 0)
2605                 return(DFX_K_HW_TIMEOUT);
2606
2607         /* Bump (and wrap) the completion index and write out to register */
2608
2609         bp->cmd_req_reg.index.comp += 1;
2610         bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2611         dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2612
2613         /*
2614          * Here we wait for the command response consumer index to be equal
2615          * to the producer, indicating that the adapter has DMAed the response.
2616          */
2617
2618         for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2619                 {
2620                 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
2621                         break;
2622                 udelay(100);                    /* wait for 100 microseconds */
2623                 }
2624         if (timeout_cnt == 0)
2625                 return(DFX_K_HW_TIMEOUT);
2626
2627         /* Bump (and wrap) the completion index and write out to register */
2628
2629         bp->cmd_rsp_reg.index.comp += 1;
2630         bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2631         dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2632         return(DFX_K_SUCCESS);
2633         }
2634
2635
2636 /*
2637  * ========================
2638  * = dfx_hw_port_ctrl_req =
2639  * ========================
2640  *
2641  * Overview:
2642  *   Sends PDQ port control command to adapter firmware
2643  *
2644  * Returns:
2645  *   Host data register value in host_data if ptr is not NULL
2646  *
2647  * Arguments:
2648  *   bp                 - pointer to board information
2649  *       command        - port control command
2650  *       data_a         - port data A register value
2651  *       data_b         - port data B register value
2652  *       host_data      - ptr to host data register value
2653  *
2654  * Functional Description:
2655  *   Send generic port control command to adapter by writing
2656  *   to various PDQ port registers, then polling for completion.
2657  *
2658  * Return Codes:
2659  *   DFX_K_SUCCESS        - port control command succeeded
2660  *   DFX_K_HW_TIMEOUT - port control command timed out
2661  *
2662  * Assumptions:
2663  *   None
2664  *
2665  * Side Effects:
2666  *   None
2667  */
2668
2669 static int dfx_hw_port_ctrl_req(
2670         DFX_board_t     *bp,
2671         PI_UINT32       command,
2672         PI_UINT32       data_a,
2673         PI_UINT32       data_b,
2674         PI_UINT32       *host_data
2675         )
2676
2677         {
2678         PI_UINT32       port_cmd;               /* Port Control command register value */
2679         int                     timeout_cnt;    /* used in for loops */
2680
2681         /* Set Command Error bit in command longword */
2682
2683         port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
2684
2685         /* Issue port command to the adapter */
2686
2687         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
2688         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
2689         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
2690
2691         /* Now wait for command to complete */
2692
2693         if (command == PI_PCTRL_M_BLAST_FLASH)
2694                 timeout_cnt = 600000;   /* set command timeout count to 60 seconds */
2695         else
2696                 timeout_cnt = 20000;    /* set command timeout count to 2 seconds */
2697
2698         for (; timeout_cnt > 0; timeout_cnt--)
2699                 {
2700                 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
2701                 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
2702                         break;
2703                 udelay(100);                    /* wait for 100 microseconds */
2704                 }
2705         if (timeout_cnt == 0)
2706                 return(DFX_K_HW_TIMEOUT);
2707
2708         /*
2709          * If the address of host_data is non-zero, assume caller has supplied a
2710          * non NULL pointer, and return the contents of the HOST_DATA register in
2711          * it.
2712          */
2713
2714         if (host_data != NULL)
2715                 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
2716         return(DFX_K_SUCCESS);
2717         }
2718
2719
2720 /*
2721  * =====================
2722  * = dfx_hw_adap_reset =
2723  * =====================
2724  *
2725  * Overview:
2726  *   Resets adapter
2727  *
2728  * Returns:
2729  *   None
2730  *
2731  * Arguments:
2732  *   bp   - pointer to board information
2733  *   type - type of reset to perform
2734  *
2735  * Functional Description:
2736  *   Issue soft reset to adapter by writing to PDQ Port Reset
2737  *   register.  Use incoming reset type to tell adapter what
2738  *   kind of reset operation to perform.
2739  *
2740  * Return Codes:
2741  *   None
2742  *
2743  * Assumptions:
2744  *   This routine merely issues a soft reset to the adapter.
2745  *   It is expected that after this routine returns, the caller
2746  *   will appropriately poll the Port Status register for the
2747  *   adapter to enter the proper state.
2748  *
2749  * Side Effects:
2750  *   Internal adapter registers are cleared.
2751  */
2752
2753 static void dfx_hw_adap_reset(
2754         DFX_board_t     *bp,
2755         PI_UINT32       type
2756         )
2757
2758         {
2759         /* Set Reset type and assert reset */
2760
2761         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type);        /* tell adapter type of reset */
2762         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
2763
2764         /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2765
2766         udelay(20);
2767
2768         /* Deassert reset */
2769
2770         dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
2771         }
2772
2773
2774 /*
2775  * ========================
2776  * = dfx_hw_adap_state_rd =
2777  * ========================
2778  *
2779  * Overview:
2780  *   Returns current adapter state
2781  *
2782  * Returns:
2783  *   Adapter state per PDQ Port Specification
2784  *
2785  * Arguments:
2786  *   bp - pointer to board information
2787  *
2788  * Functional Description:
2789  *   Reads PDQ Port Status register and returns adapter state.
2790  *
2791  * Return Codes:
2792  *   None
2793  *
2794  * Assumptions:
2795  *   None
2796  *
2797  * Side Effects:
2798  *   None
2799  */
2800
2801 static int dfx_hw_adap_state_rd(DFX_board_t *bp)
2802         {
2803         PI_UINT32 port_status;          /* Port Status register value */
2804
2805         dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
2806         return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE);
2807         }
2808
2809
2810 /*
2811  * =====================
2812  * = dfx_hw_dma_uninit =
2813  * =====================
2814  *
2815  * Overview:
2816  *   Brings adapter to DMA_UNAVAILABLE state
2817  *
2818  * Returns:
2819  *   Condition code
2820  *
2821  * Arguments:
2822  *   bp   - pointer to board information
2823  *   type - type of reset to perform
2824  *
2825  * Functional Description:
2826  *   Bring adapter to DMA_UNAVAILABLE state by performing the following:
2827  *              1. Set reset type bit in Port Data A Register then reset adapter.
2828  *              2. Check that adapter is in DMA_UNAVAILABLE state.
2829  *
2830  * Return Codes:
2831  *   DFX_K_SUCCESS        - adapter is in DMA_UNAVAILABLE state
2832  *   DFX_K_HW_TIMEOUT - adapter did not reset properly
2833  *
2834  * Assumptions:
2835  *   None
2836  *
2837  * Side Effects:
2838  *   Internal adapter registers are cleared.
2839  */
2840
2841 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
2842         {
2843         int timeout_cnt;        /* used in for loops */
2844
2845         /* Set reset type bit and reset adapter */
2846
2847         dfx_hw_adap_reset(bp, type);
2848
2849         /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2850
2851         for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
2852                 {
2853                 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
2854                         break;
2855                 udelay(100);                                    /* wait for 100 microseconds */
2856                 }
2857         if (timeout_cnt == 0)
2858                 return(DFX_K_HW_TIMEOUT);
2859         return(DFX_K_SUCCESS);
2860         }
2861
2862 /*
2863  *      Align an sk_buff to a boundary power of 2
2864  *
2865  */
2866
2867 static void my_skb_align(struct sk_buff *skb, int n)
2868 {
2869         unsigned long x = (unsigned long)skb->data;
2870         unsigned long v;
2871
2872         v = ALIGN(x, n);        /* Where we want to be */
2873
2874         skb_reserve(skb, v - x);
2875 }
2876
2877
2878 /*
2879  * ================
2880  * = dfx_rcv_init =
2881  * ================
2882  *
2883  * Overview:
2884  *   Produces buffers to adapter LLC Host receive descriptor block
2885  *
2886  * Returns:
2887  *   None
2888  *
2889  * Arguments:
2890  *   bp - pointer to board information
2891  *   get_buffers - non-zero if buffers to be allocated
2892  *
2893  * Functional Description:
2894  *   This routine can be called during dfx_adap_init() or during an adapter
2895  *       reset.  It initializes the descriptor block and produces all allocated
2896  *   LLC Host queue receive buffers.
2897  *
2898  * Return Codes:
2899  *   Return 0 on success or -ENOMEM if buffer allocation failed (when using
2900  *   dynamic buffer allocation). If the buffer allocation failed, the
2901  *   already allocated buffers will not be released and the caller should do
2902  *   this.
2903  *
2904  * Assumptions:
2905  *   The PDQ has been reset and the adapter and driver maintained Type 2
2906  *   register indices are cleared.
2907  *
2908  * Side Effects:
2909  *   Receive buffers are posted to the adapter LLC queue and the adapter
2910  *   is notified.
2911  */
2912
2913 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
2914         {
2915         int     i, j;                                   /* used in for loop */
2916
2917         /*
2918          *  Since each receive buffer is a single fragment of same length, initialize
2919          *  first longword in each receive descriptor for entire LLC Host descriptor
2920          *  block.  Also initialize second longword in each receive descriptor with
2921          *  physical address of receive buffer.  We'll always allocate receive
2922          *  buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2923          *  block and produce new receive buffers by simply updating the receive
2924          *  producer index.
2925          *
2926          *      Assumptions:
2927          *              To support all shipping versions of PDQ, the receive buffer size
2928          *              must be mod 128 in length and the physical address must be 128 byte
2929          *              aligned.  In other words, bits 0-6 of the length and address must
2930          *              be zero for the following descriptor field entries to be correct on
2931          *              all PDQ-based boards.  We guaranteed both requirements during
2932          *              driver initialization when we allocated memory for the receive buffers.
2933          */
2934
2935         if (get_buffers) {
2936 #ifdef DYNAMIC_BUFFERS
2937         for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
2938                 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2939                 {
2940                         struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO);
2941                         if (!newskb)
2942                                 return -ENOMEM;
2943                         bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2944                                 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2945                         /*
2946                          * align to 128 bytes for compatibility with
2947                          * the old EISA boards.
2948                          */
2949
2950                         my_skb_align(newskb, 128);
2951                         bp->descr_block_virt->rcv_data[i + j].long_1 =
2952                                 (u32)dma_map_single(bp->bus_dev, newskb->data,
2953                                                     NEW_SKB_SIZE,
2954                                                     DMA_FROM_DEVICE);
2955                         /*
2956                          * p_rcv_buff_va is only used inside the
2957                          * kernel so we put the skb pointer here.
2958                          */
2959                         bp->p_rcv_buff_va[i+j] = (char *) newskb;
2960                 }
2961 #else
2962         for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
2963                 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2964                         {
2965                         bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2966                                 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2967                         bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2968                         bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
2969                         }
2970 #endif
2971         }
2972
2973         /* Update receive producer and Type 2 register */
2974
2975         bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
2976         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
2977         return 0;
2978         }
2979
2980
2981 /*
2982  * =========================
2983  * = dfx_rcv_queue_process =
2984  * =========================
2985  *
2986  * Overview:
2987  *   Process received LLC frames.
2988  *
2989  * Returns:
2990  *   None
2991  *
2992  * Arguments:
2993  *   bp - pointer to board information
2994  *
2995  * Functional Description:
2996  *   Received LLC frames are processed until there are no more consumed frames.
2997  *   Once all frames are processed, the receive buffers are returned to the
2998  *   adapter.  Note that this algorithm fixes the length of time that can be spent
2999  *   in this routine, because there are a fixed number of receive buffers to
3000  *   process and buffers are not produced until this routine exits and returns
3001  *   to the ISR.
3002  *
3003  * Return Codes:
3004  *   None
3005  *
3006  * Assumptions:
3007  *   None
3008  *
3009  * Side Effects:
3010  *   None
3011  */
3012
3013 static void dfx_rcv_queue_process(
3014         DFX_board_t *bp
3015         )
3016
3017         {
3018         PI_TYPE_2_CONSUMER      *p_type_2_cons;         /* ptr to rcv/xmt consumer block register */
3019         char                            *p_buff;                        /* ptr to start of packet receive buffer (FMC descriptor) */
3020         u32                                     descr, pkt_len;         /* FMC descriptor field and packet length */
3021         struct sk_buff          *skb;                           /* pointer to a sk_buff to hold incoming packet data */
3022
3023         /* Service all consumed LLC receive frames */
3024
3025         p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3026         while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
3027                 {
3028                 /* Process any errors */
3029
3030                 int entry;
3031
3032                 entry = bp->rcv_xmt_reg.index.rcv_comp;
3033 #ifdef DYNAMIC_BUFFERS
3034                 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
3035 #else
3036                 p_buff = (char *) bp->p_rcv_buff_va[entry];
3037 #endif
3038                 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
3039
3040                 if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
3041                         {
3042                         if (descr & PI_FMC_DESCR_M_RCC_CRC)
3043                                 bp->rcv_crc_errors++;
3044                         else
3045                                 bp->rcv_frame_status_errors++;
3046                         }
3047                 else
3048                 {
3049                         int rx_in_place = 0;
3050
3051                         /* The frame was received without errors - verify packet length */
3052
3053                         pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
3054                         pkt_len -= 4;                           /* subtract 4 byte CRC */
3055                         if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3056                                 bp->rcv_length_errors++;
3057                         else{
3058 #ifdef DYNAMIC_BUFFERS
3059                                 if (pkt_len > SKBUFF_RX_COPYBREAK) {
3060                                         struct sk_buff *newskb;
3061
3062                                         newskb = dev_alloc_skb(NEW_SKB_SIZE);
3063                                         if (newskb){
3064                                                 rx_in_place = 1;
3065
3066                                                 my_skb_align(newskb, 128);
3067                                                 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
3068                                                 dma_unmap_single(bp->bus_dev,
3069                                                         bp->descr_block_virt->rcv_data[entry].long_1,
3070                                                         NEW_SKB_SIZE,
3071                                                         DMA_FROM_DEVICE);
3072                                                 skb_reserve(skb, RCV_BUFF_K_PADDING);
3073                                                 bp->p_rcv_buff_va[entry] = (char *)newskb;
3074                                                 bp->descr_block_virt->rcv_data[entry].long_1 =
3075                                                         (u32)dma_map_single(bp->bus_dev,
3076                                                                 newskb->data,
3077                                                                 NEW_SKB_SIZE,
3078                                                                 DMA_FROM_DEVICE);
3079                                         } else
3080                                                 skb = NULL;
3081                                 } else
3082 #endif
3083                                         skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */
3084                                 if (skb == NULL)
3085                                         {
3086                                         printk("%s: Could not allocate receive buffer.  Dropping packet.\n", bp->dev->name);
3087                                         bp->rcv_discards++;
3088                                         break;
3089                                         }
3090                                 else {
3091 #ifndef DYNAMIC_BUFFERS
3092                                         if (! rx_in_place)
3093 #endif
3094                                         {
3095                                                 /* Receive buffer allocated, pass receive packet up */
3096
3097                                                 skb_copy_to_linear_data(skb,
3098                                                                p_buff + RCV_BUFF_K_PADDING,
3099                                                                pkt_len + 3);
3100                                         }
3101
3102                                         skb_reserve(skb,3);             /* adjust data field so that it points to FC byte */
3103                                         skb_put(skb, pkt_len);          /* pass up packet length, NOT including CRC */
3104                                         skb->protocol = fddi_type_trans(skb, bp->dev);
3105                                         bp->rcv_total_bytes += skb->len;
3106                                         netif_rx(skb);
3107
3108                                         /* Update the rcv counters */
3109                                         bp->rcv_total_frames++;
3110                                         if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
3111                                                 bp->rcv_multicast_frames++;
3112                                 }
3113                         }
3114                         }
3115
3116                 /*
3117                  * Advance the producer (for recycling) and advance the completion
3118                  * (for servicing received frames).  Note that it is okay to
3119                  * advance the producer without checking that it passes the
3120                  * completion index because they are both advanced at the same
3121                  * rate.
3122                  */
3123
3124                 bp->rcv_xmt_reg.index.rcv_prod += 1;
3125                 bp->rcv_xmt_reg.index.rcv_comp += 1;
3126                 }
3127         }
3128
3129
3130 /*
3131  * =====================
3132  * = dfx_xmt_queue_pkt =
3133  * =====================
3134  *
3135  * Overview:
3136  *   Queues packets for transmission
3137  *
3138  * Returns:
3139  *   Condition code
3140  *
3141  * Arguments:
3142  *   skb - pointer to sk_buff to queue for transmission
3143  *   dev - pointer to device information
3144  *
3145  * Functional Description:
3146  *   Here we assume that an incoming skb transmit request
3147  *   is contained in a single physically contiguous buffer
3148  *   in which the virtual address of the start of packet
3149  *   (skb->data) can be converted to a physical address
3150  *   by using pci_map_single().
3151  *
3152  *   Since the adapter architecture requires a three byte
3153  *   packet request header to prepend the start of packet,
3154  *   we'll write the three byte field immediately prior to
3155  *   the FC byte.  This assumption is valid because we've
3156  *   ensured that dev->hard_header_len includes three pad
3157  *   bytes.  By posting a single fragment to the adapter,
3158  *   we'll reduce the number of descriptor fetches and
3159  *   bus traffic needed to send the request.
3160  *
3161  *   Also, we can't free the skb until after it's been DMA'd
3162  *   out by the adapter, so we'll queue it in the driver and
3163  *   return it in dfx_xmt_done.
3164  *
3165  * Return Codes:
3166  *   0 - driver queued packet, link is unavailable, or skbuff was bad
3167  *       1 - caller should requeue the sk_buff for later transmission
3168  *
3169  * Assumptions:
3170  *       First and foremost, we assume the incoming skb pointer
3171  *   is NOT NULL and is pointing to a valid sk_buff structure.
3172  *
3173  *   The outgoing packet is complete, starting with the
3174  *   frame control byte including the last byte of data,
3175  *   but NOT including the 4 byte CRC.  We'll let the
3176  *   adapter hardware generate and append the CRC.
3177  *
3178  *   The entire packet is stored in one physically
3179  *   contiguous buffer which is not cached and whose
3180  *   32-bit physical address can be determined.
3181  *
3182  *   It's vital that this routine is NOT reentered for the
3183  *   same board and that the OS is not in another section of
3184  *   code (eg. dfx_int_common) for the same board on a
3185  *   different thread.
3186  *
3187  * Side Effects:
3188  *   None
3189  */
3190
3191 static int dfx_xmt_queue_pkt(
3192         struct sk_buff  *skb,
3193         struct net_device       *dev
3194         )
3195
3196         {
3197         DFX_board_t             *bp = netdev_priv(dev);
3198         u8                      prod;                           /* local transmit producer index */
3199         PI_XMT_DESCR            *p_xmt_descr;           /* ptr to transmit descriptor block entry */
3200         XMT_DRIVER_DESCR        *p_xmt_drv_descr;       /* ptr to transmit driver descriptor */
3201         unsigned long           flags;
3202
3203         netif_stop_queue(dev);
3204
3205         /*
3206          * Verify that incoming transmit request is OK
3207          *
3208          * Note: The packet size check is consistent with other
3209          *               Linux device drivers, although the correct packet
3210          *               size should be verified before calling the
3211          *               transmit routine.
3212          */
3213
3214         if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3215         {
3216                 printk("%s: Invalid packet length - %u bytes\n",
3217                         dev->name, skb->len);
3218                 bp->xmt_length_errors++;                /* bump error counter */
3219                 netif_wake_queue(dev);
3220                 dev_kfree_skb(skb);
3221                 return(0);                              /* return "success" */
3222         }
3223         /*
3224          * See if adapter link is available, if not, free buffer
3225          *
3226          * Note: If the link isn't available, free buffer and return 0
3227          *               rather than tell the upper layer to requeue the packet.
3228          *               The methodology here is that by the time the link
3229          *               becomes available, the packet to be sent will be
3230          *               fairly stale.  By simply dropping the packet, the
3231          *               higher layer protocols will eventually time out
3232          *               waiting for response packets which it won't receive.
3233          */
3234
3235         if (bp->link_available == PI_K_FALSE)
3236                 {
3237                 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL)  /* is link really available? */
3238                         bp->link_available = PI_K_TRUE;         /* if so, set flag and continue */
3239                 else
3240                         {
3241                         bp->xmt_discards++;                                     /* bump error counter */
3242                         dev_kfree_skb(skb);             /* free sk_buff now */
3243                         netif_wake_queue(dev);
3244                         return(0);                                                      /* return "success" */
3245                         }
3246                 }
3247
3248         spin_lock_irqsave(&bp->lock, flags);
3249
3250         /* Get the current producer and the next free xmt data descriptor */
3251
3252         prod            = bp->rcv_xmt_reg.index.xmt_prod;
3253         p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
3254
3255         /*
3256          * Get pointer to auxiliary queue entry to contain information
3257          * for this packet.
3258          *
3259          * Note: The current xmt producer index will become the
3260          *       current xmt completion index when we complete this
3261          *       packet later on.  So, we'll get the pointer to the
3262          *       next auxiliary queue entry now before we bump the
3263          *       producer index.
3264          */
3265
3266         p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]);     /* also bump producer index */
3267
3268         /* Write the three PRH bytes immediately before the FC byte */
3269
3270         skb_push(skb,3);
3271         skb->data[0] = DFX_PRH0_BYTE;   /* these byte values are defined */
3272         skb->data[1] = DFX_PRH1_BYTE;   /* in the Motorola FDDI MAC chip */
3273         skb->data[2] = DFX_PRH2_BYTE;   /* specification */
3274
3275         /*
3276          * Write the descriptor with buffer info and bump producer
3277          *
3278          * Note: Since we need to start DMA from the packet request
3279          *               header, we'll add 3 bytes to the DMA buffer length,
3280          *               and we'll determine the physical address of the
3281          *               buffer from the PRH, not skb->data.
3282          *
3283          * Assumptions:
3284          *               1. Packet starts with the frame control (FC) byte
3285          *                  at skb->data.
3286          *               2. The 4-byte CRC is not appended to the buffer or
3287          *                      included in the length.
3288          *               3. Packet length (skb->len) is from FC to end of
3289          *                      data, inclusive.
3290          *               4. The packet length does not exceed the maximum
3291          *                      FDDI LLC frame length of 4491 bytes.
3292          *               5. The entire packet is contained in a physically
3293          *                      contiguous, non-cached, locked memory space
3294          *                      comprised of a single buffer pointed to by
3295          *                      skb->data.
3296          *               6. The physical address of the start of packet
3297          *                      can be determined from the virtual address
3298          *                      by using pci_map_single() and is only 32-bits
3299          *                      wide.
3300          */
3301
3302         p_xmt_descr->long_0     = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3303         p_xmt_descr->long_1 = (u32)dma_map_single(bp->bus_dev, skb->data,
3304                                                   skb->len, DMA_TO_DEVICE);
3305
3306         /*
3307          * Verify that descriptor is actually available
3308          *
3309          * Note: If descriptor isn't available, return 1 which tells
3310          *       the upper layer to requeue the packet for later
3311          *       transmission.
3312          *
3313          *       We need to ensure that the producer never reaches the
3314          *       completion, except to indicate that the queue is empty.
3315          */
3316
3317         if (prod == bp->rcv_xmt_reg.index.xmt_comp)
3318         {
3319                 skb_pull(skb,3);
3320                 spin_unlock_irqrestore(&bp->lock, flags);
3321                 return(1);                      /* requeue packet for later */
3322         }
3323
3324         /*
3325          * Save info for this packet for xmt done indication routine
3326          *
3327          * Normally, we'd save the producer index in the p_xmt_drv_descr
3328          * structure so that we'd have it handy when we complete this
3329          * packet later (in dfx_xmt_done).  However, since the current
3330          * transmit architecture guarantees a single fragment for the
3331          * entire packet, we can simply bump the completion index by
3332          * one (1) for each completed packet.
3333          *
3334          * Note: If this assumption changes and we're presented with
3335          *       an inconsistent number of transmit fragments for packet
3336          *       data, we'll need to modify this code to save the current
3337          *       transmit producer index.
3338          */
3339
3340         p_xmt_drv_descr->p_skb = skb;
3341
3342         /* Update Type 2 register */
3343
3344         bp->rcv_xmt_reg.index.xmt_prod = prod;
3345         dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
3346         spin_unlock_irqrestore(&bp->lock, flags);
3347         netif_wake_queue(dev);
3348         return(0);                                                      /* packet queued to adapter */
3349         }
3350
3351
3352 /*
3353  * ================
3354  * = dfx_xmt_done =
3355  * ================
3356  *
3357  * Overview:
3358  *   Processes all frames that have been transmitted.
3359  *
3360  * Returns:
3361  *   None
3362  *
3363  * Arguments:
3364  *   bp - pointer to board information
3365  *
3366  * Functional Description:
3367  *   For all consumed transmit descriptors that have not
3368  *   yet been completed, we'll free the skb we were holding
3369  *   onto using dev_kfree_skb and bump the appropriate
3370  *   counters.
3371  *
3372  * Return Codes:
3373  *   None
3374  *
3375  * Assumptions:
3376  *   The Type 2 register is not updated in this routine.  It is
3377  *   assumed that it will be updated in the ISR when dfx_xmt_done
3378  *   returns.
3379  *
3380  * Side Effects:
3381  *   None
3382  */
3383
3384 static int dfx_xmt_done(DFX_board_t *bp)
3385         {
3386         XMT_DRIVER_DESCR        *p_xmt_drv_descr;       /* ptr to transmit driver descriptor */
3387         PI_TYPE_2_CONSUMER      *p_type_2_cons;         /* ptr to rcv/xmt consumer block register */
3388         u8                      comp;                   /* local transmit completion index */
3389         int                     freed = 0;              /* buffers freed */
3390
3391         /* Service all consumed transmit frames */
3392
3393         p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3394         while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
3395                 {
3396                 /* Get pointer to the transmit driver descriptor block information */
3397
3398                 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3399
3400                 /* Increment transmit counters */
3401
3402                 bp->xmt_total_frames++;
3403                 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
3404
3405                 /* Return skb to operating system */
3406                 comp = bp->rcv_xmt_reg.index.xmt_comp;
3407                 dma_unmap_single(bp->bus_dev,
3408                                  bp->descr_block_virt->xmt_data[comp].long_1,
3409                                  p_xmt_drv_descr->p_skb->len,
3410                                  DMA_TO_DEVICE);
3411                 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb);
3412
3413                 /*
3414                  * Move to start of next packet by updating completion index
3415                  *
3416                  * Here we assume that a transmit packet request is always
3417                  * serviced by posting one fragment.  We can therefore
3418                  * simplify the completion code by incrementing the
3419                  * completion index by one.  This code will need to be
3420                  * modified if this assumption changes.  See comments
3421                  * in dfx_xmt_queue_pkt for more details.
3422                  */
3423
3424                 bp->rcv_xmt_reg.index.xmt_comp += 1;
3425                 freed++;
3426                 }
3427         return freed;
3428         }
3429
3430
3431 /*
3432  * =================
3433  * = dfx_rcv_flush =
3434  * =================
3435  *
3436  * Overview:
3437  *   Remove all skb's in the receive ring.
3438  *
3439  * Returns:
3440  *   None
3441  *
3442  * Arguments:
3443  *   bp - pointer to board information
3444  *
3445  * Functional Description:
3446  *   Free's all the dynamically allocated skb's that are
3447  *   currently attached to the device receive ring. This
3448  *   function is typically only used when the device is
3449  *   initialized or reinitialized.
3450  *
3451  * Return Codes:
3452  *   None
3453  *
3454  * Side Effects:
3455  *   None
3456  */
3457 #ifdef DYNAMIC_BUFFERS
3458 static void dfx_rcv_flush( DFX_board_t *bp )
3459         {
3460         int i, j;
3461
3462         for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
3463                 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
3464                 {
3465                         struct sk_buff *skb;
3466                         skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
3467                         if (skb)
3468                                 dev_kfree_skb(skb);
3469                         bp->p_rcv_buff_va[i+j] = NULL;
3470                 }
3471
3472         }
3473 #else
3474 static inline void dfx_rcv_flush( DFX_board_t *bp )
3475 {
3476 }
3477 #endif /* DYNAMIC_BUFFERS */
3478
3479 /*
3480  * =================
3481  * = dfx_xmt_flush =
3482  * =================
3483  *
3484  * Overview:
3485  *   Processes all frames whether they've been transmitted
3486  *   or not.
3487  *
3488  * Returns:
3489  *   None
3490  *
3491  * Arguments:
3492  *   bp - pointer to board information
3493  *
3494  * Functional Description:
3495  *   For all produced transmit descriptors that have not
3496  *   yet been completed, we'll free the skb we were holding
3497  *   onto using dev_kfree_skb and bump the appropriate
3498  *   counters.  Of course, it's possible that some of
3499  *   these transmit requests actually did go out, but we
3500  *   won't make that distinction here.  Finally, we'll
3501  *   update the consumer index to match the producer.
3502  *
3503  * Return Codes:
3504  *   None
3505  *
3506  * Assumptions:
3507  *   This routine does NOT update the Type 2 register.  It
3508  *   is assumed that this routine is being called during a
3509  *   transmit flush interrupt, or a shutdown or close routine.
3510  *
3511  * Side Effects:
3512  *   None
3513  */
3514
3515 static void dfx_xmt_flush( DFX_board_t *bp )
3516         {
3517         u32                     prod_cons;              /* rcv/xmt consumer block longword */
3518         XMT_DRIVER_DESCR        *p_xmt_drv_descr;       /* ptr to transmit driver descriptor */
3519         u8                      comp;                   /* local transmit completion index */
3520
3521         /* Flush all outstanding transmit frames */
3522
3523         while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
3524                 {
3525                 /* Get pointer to the transmit driver descriptor block information */
3526
3527                 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3528
3529                 /* Return skb to operating system */
3530                 comp = bp->rcv_xmt_reg.index.xmt_comp;
3531                 dma_unmap_single(bp->bus_dev,
3532                                  bp->descr_block_virt->xmt_data[comp].long_1,
3533                                  p_xmt_drv_descr->p_skb->len,
3534                                  DMA_TO_DEVICE);
3535                 dev_kfree_skb(p_xmt_drv_descr->p_skb);
3536
3537                 /* Increment transmit error counter */
3538
3539                 bp->xmt_discards++;
3540
3541                 /*
3542                  * Move to start of next packet by updating completion index
3543                  *
3544                  * Here we assume that a transmit packet request is always
3545                  * serviced by posting one fragment.  We can therefore
3546                  * simplify the completion code by incrementing the
3547                  * completion index by one.  This code will need to be
3548                  * modified if this assumption changes.  See comments
3549                  * in dfx_xmt_queue_pkt for more details.
3550                  */
3551
3552                 bp->rcv_xmt_reg.index.xmt_comp += 1;
3553                 }
3554
3555         /* Update the transmit consumer index in the consumer block */
3556
3557         prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
3558         prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
3559         bp->cons_block_virt->xmt_rcv_data = prod_cons;
3560         }
3561
3562 /*
3563  * ==================
3564  * = dfx_unregister =
3565  * ==================
3566  *
3567  * Overview:
3568  *   Shuts down an FDDI controller
3569  *
3570  * Returns:
3571  *   Condition code
3572  *
3573  * Arguments:
3574  *   bdev - pointer to device information
3575  *
3576  * Functional Description:
3577  *
3578  * Return Codes:
3579  *   None
3580  *
3581  * Assumptions:
3582  *   It compiles so it should work :-( (PCI cards do :-)
3583  *
3584  * Side Effects:
3585  *   Device structures for FDDI adapters (fddi0, fddi1, etc) are
3586  *   freed.
3587  */
3588 static void __devexit dfx_unregister(struct device *bdev)
3589 {
3590         struct net_device *dev = dev_get_drvdata(bdev);
3591         DFX_board_t *bp = netdev_priv(dev);
3592         int dfx_bus_pci = DFX_BUS_PCI(bdev);
3593         int dfx_bus_tc = DFX_BUS_TC(bdev);
3594         int dfx_use_mmio = DFX_MMIO || dfx_bus_tc;
3595         resource_size_t bar_start = 0;          /* pointer to port */
3596         resource_size_t bar_len = 0;            /* resource length */
3597         int             alloc_size;             /* total buffer size used */
3598
3599         unregister_netdev(dev);
3600
3601         alloc_size = sizeof(PI_DESCR_BLOCK) +
3602                      PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
3603 #ifndef DYNAMIC_BUFFERS
3604                      (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
3605 #endif
3606                      sizeof(PI_CONSUMER_BLOCK) +
3607                      (PI_ALIGN_K_DESC_BLK - 1);
3608         if (bp->kmalloced)
3609                 dma_free_coherent(bdev, alloc_size,
3610                                   bp->kmalloced, bp->kmalloced_dma);
3611
3612         dfx_bus_uninit(dev);
3613
3614         dfx_get_bars(bdev, &bar_start, &bar_len);
3615         if (dfx_use_mmio) {
3616                 iounmap(bp->base.mem);
3617                 release_mem_region(bar_start, bar_len);
3618         } else
3619                 release_region(bar_start, bar_len);
3620
3621         if (dfx_bus_pci)
3622                 pci_disable_device(to_pci_dev(bdev));
3623
3624         free_netdev(dev);
3625 }
3626
3627
3628 static int __devinit __maybe_unused dfx_dev_register(struct device *);
3629 static int __devexit __maybe_unused dfx_dev_unregister(struct device *);
3630
3631 #ifdef CONFIG_PCI
3632 static int __devinit dfx_pci_register(struct pci_dev *,
3633                                       const struct pci_device_id *);
3634 static void __devexit dfx_pci_unregister(struct pci_dev *);
3635
3636 static struct pci_device_id dfx_pci_table[] = {
3637         { PCI_DEVICE(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI) },
3638         { }
3639 };
3640 MODULE_DEVICE_TABLE(pci, dfx_pci_table);
3641
3642 static struct pci_driver dfx_pci_driver = {
3643         .name           = "defxx",
3644         .id_table       = dfx_pci_table,
3645         .probe          = dfx_pci_register,
3646         .remove         = __devexit_p(dfx_pci_unregister),
3647 };
3648
3649 static __devinit int dfx_pci_register(struct pci_dev *pdev,
3650                                       const struct pci_device_id *ent)
3651 {
3652         return dfx_register(&pdev->dev);
3653 }
3654
3655 static void __devexit dfx_pci_unregister(struct pci_dev *pdev)
3656 {
3657         dfx_unregister(&pdev->dev);
3658 }
3659 #endif /* CONFIG_PCI */
3660
3661 #ifdef CONFIG_EISA
3662 static struct eisa_device_id dfx_eisa_table[] = {
3663         { "DEC3001", DEFEA_PROD_ID_1 },
3664         { "DEC3002", DEFEA_PROD_ID_2 },
3665         { "DEC3003", DEFEA_PROD_ID_3 },
3666         { "DEC3004", DEFEA_PROD_ID_4 },
3667         { }
3668 };
3669 MODULE_DEVICE_TABLE(eisa, dfx_eisa_table);
3670
3671 static struct eisa_driver dfx_eisa_driver = {
3672         .id_table       = dfx_eisa_table,
3673         .driver         = {
3674                 .name   = "defxx",
3675                 .bus    = &eisa_bus_type,
3676                 .probe  = dfx_dev_register,
3677                 .remove = __devexit_p(dfx_dev_unregister),
3678         },
3679 };
3680 #endif /* CONFIG_EISA */
3681
3682 #ifdef CONFIG_TC
3683 static struct tc_device_id const dfx_tc_table[] = {
3684         { "DEC     ", "PMAF-FA " },
3685         { "DEC     ", "PMAF-FD " },
3686         { "DEC     ", "PMAF-FS " },
3687         { "DEC     ", "PMAF-FU " },
3688         { }
3689 };
3690 MODULE_DEVICE_TABLE(tc, dfx_tc_table);
3691
3692 static struct tc_driver dfx_tc_driver = {
3693         .id_table       = dfx_tc_table,
3694         .driver         = {
3695                 .name   = "defxx",
3696                 .bus    = &tc_bus_type,
3697                 .probe  = dfx_dev_register,
3698                 .remove = __devexit_p(dfx_dev_unregister),
3699         },
3700 };
3701 #endif /* CONFIG_TC */
3702
3703 static int __devinit __maybe_unused dfx_dev_register(struct device *dev)
3704 {
3705         int status;
3706
3707         status = dfx_register(dev);
3708         if (!status)
3709                 get_device(dev);
3710         return status;
3711 }
3712
3713 static int __devexit __maybe_unused dfx_dev_unregister(struct device *dev)
3714 {
3715         put_device(dev);
3716         dfx_unregister(dev);
3717         return 0;
3718 }
3719
3720
3721 static int __devinit dfx_init(void)
3722 {
3723         int status;
3724
3725         status = pci_register_driver(&dfx_pci_driver);
3726         if (!status)
3727                 status = eisa_driver_register(&dfx_eisa_driver);
3728         if (!status)
3729                 status = tc_register_driver(&dfx_tc_driver);
3730         return status;
3731 }
3732
3733 static void __devexit dfx_cleanup(void)
3734 {
3735         tc_unregister_driver(&dfx_tc_driver);
3736         eisa_driver_unregister(&dfx_eisa_driver);
3737         pci_unregister_driver(&dfx_pci_driver);
3738 }
3739
3740 module_init(dfx_init);
3741 module_exit(dfx_cleanup);
3742 MODULE_AUTHOR("Lawrence V. Stefani");
3743 MODULE_DESCRIPTION("DEC FDDIcontroller TC/EISA/PCI (DEFTA/DEFEA/DEFPA) driver "
3744                    DRV_VERSION " " DRV_RELDATE);
3745 MODULE_LICENSE("GPL");