5 * Copyright Information:
6 * Copyright Digital Equipment Corporation 1996.
8 * This software may be used and distributed according to the terms of
9 * the GNU General Public License, incorporated herein by reference.
12 * A Linux device driver supporting the Digital Equipment Corporation
13 * FDDI EISA and PCI controller families. Supported adapters include:
15 * DEC FDDIcontroller/EISA (DEFEA)
16 * DEC FDDIcontroller/PCI (DEFPA)
18 * The original author:
19 * LVS Lawrence V. Stefani <lstefani@yahoo.com>
22 * macro Maciej W. Rozycki <macro@linux-mips.org>
25 * I'd like to thank Patricia Cross for helping me get started with
26 * Linux, David Davies for a lot of help upgrading and configuring
27 * my development system and for answering many OS and driver
28 * development questions, and Alan Cox for recommendations and
29 * integration help on getting FDDI support into Linux. LVS
31 * Driver Architecture:
32 * The driver architecture is largely based on previous driver work
33 * for other operating systems. The upper edge interface and
34 * functions were largely taken from existing Linux device drivers
35 * such as David Davies' DE4X5.C driver and Donald Becker's TULIP.C
39 * The driver scans for supported EISA adapters by reading the
40 * SLOT ID register for each EISA slot and making a match
41 * against the expected value.
43 * Bus-Specific Initialization -
44 * This driver currently supports both EISA and PCI controller
45 * families. While the custom DMA chip and FDDI logic is similar
46 * or identical, the bus logic is very different. After
47 * initialization, the only bus-specific differences is in how the
48 * driver enables and disables interrupts. Other than that, the
49 * run-time critical code behaves the same on both families.
50 * It's important to note that both adapter families are configured
51 * to I/O map, rather than memory map, the adapter registers.
54 * In the driver open routine, the driver ISR (interrupt service
55 * routine) is registered and the adapter is brought to an
56 * operational state. In the driver close routine, the opposite
57 * occurs; the driver ISR is deregistered and the adapter is
58 * brought to a safe, but closed state. Users may use consecutive
59 * commands to bring the adapter up and down as in the following
66 * Apparently, there is no shutdown or halt routine support under
67 * Linux. This routine would be called during "reboot" or
68 * "shutdown" to allow the driver to place the adapter in a safe
69 * state before a warm reboot occurs. To be really safe, the user
70 * should close the adapter before shutdown (eg. ifconfig fddi0 down)
71 * to ensure that the adapter DMA engine is taken off-line. However,
72 * the current driver code anticipates this problem and always issues
73 * a soft reset of the adapter at the beginning of driver initialization.
74 * A future driver enhancement in this area may occur in 2.1.X where
75 * Alan indicated that a shutdown handler may be implemented.
77 * Interrupt Service Routine -
78 * The driver supports shared interrupts, so the ISR is registered for
79 * each board with the appropriate flag and the pointer to that board's
80 * device structure. This provides the context during interrupt
81 * processing to support shared interrupts and multiple boards.
83 * Interrupt enabling/disabling can occur at many levels. At the host
84 * end, you can disable system interrupts, or disable interrupts at the
85 * PIC (on Intel systems). Across the bus, both EISA and PCI adapters
86 * have a bus-logic chip interrupt enable/disable as well as a DMA
87 * controller interrupt enable/disable.
89 * The driver currently enables and disables adapter interrupts at the
90 * bus-logic chip and assumes that Linux will take care of clearing or
91 * acknowledging any host-based interrupt chips.
94 * Control functions are those used to support functions such as adding
95 * or deleting multicast addresses, enabling or disabling packet
96 * reception filters, or other custom/proprietary commands. Presently,
97 * the driver supports the "get statistics", "set multicast list", and
98 * "set mac address" functions defined by Linux. A list of possible
99 * enhancements include:
101 * - Custom ioctl interface for executing port interface commands
102 * - Custom ioctl interface for adding unicast addresses to
103 * adapter CAM (to support bridge functions).
104 * - Custom ioctl interface for supporting firmware upgrades.
106 * Hardware (port interface) Support Routines -
107 * The driver function names that start with "dfx_hw_" represent
108 * low-level port interface routines that are called frequently. They
109 * include issuing a DMA or port control command to the adapter,
110 * resetting the adapter, or reading the adapter state. Since the
111 * driver initialization and run-time code must make calls into the
112 * port interface, these routines were written to be as generic and
113 * usable as possible.
116 * The adapter DMA engine supports a 256 entry receive descriptor block
117 * of which up to 255 entries can be used at any given time. The
118 * architecture is a standard producer, consumer, completion model in
119 * which the driver "produces" receive buffers to the adapter, the
120 * adapter "consumes" the receive buffers by DMAing incoming packet data,
121 * and the driver "completes" the receive buffers by servicing the
122 * incoming packet, then "produces" a new buffer and starts the cycle
123 * again. Receive buffers can be fragmented in up to 16 fragments
124 * (descriptor entries). For simplicity, this driver posts
125 * single-fragment receive buffers of 4608 bytes, then allocates a
126 * sk_buff, copies the data, then reposts the buffer. To reduce CPU
127 * utilization, a better approach would be to pass up the receive
128 * buffer (no extra copy) then allocate and post a replacement buffer.
129 * This is a performance enhancement that should be looked into at
133 * Like the receive path, the adapter DMA engine supports a 256 entry
134 * transmit descriptor block of which up to 255 entries can be used at
135 * any given time. Transmit buffers can be fragmented in up to 255
136 * fragments (descriptor entries). This driver always posts one
137 * fragment per transmit packet request.
139 * The fragment contains the entire packet from FC to end of data.
140 * Before posting the buffer to the adapter, the driver sets a three-byte
141 * packet request header (PRH) which is required by the Motorola MAC chip
142 * used on the adapters. The PRH tells the MAC the type of token to
143 * receive/send, whether or not to generate and append the CRC, whether
144 * synchronous or asynchronous framing is used, etc. Since the PRH
145 * definition is not necessarily consistent across all FDDI chipsets,
146 * the driver, rather than the common FDDI packet handler routines,
149 * To reduce the amount of descriptor fetches needed per transmit request,
150 * the driver takes advantage of the fact that there are at least three
151 * bytes available before the skb->data field on the outgoing transmit
152 * request. This is guaranteed by having fddi_setup() in net_init.c set
153 * dev->hard_header_len to 24 bytes. 21 bytes accounts for the largest
154 * header in an 802.2 SNAP frame. The other 3 bytes are the extra "pad"
155 * bytes which we'll use to store the PRH.
157 * There's a subtle advantage to adding these pad bytes to the
158 * hard_header_len, it ensures that the data portion of the packet for
159 * an 802.2 SNAP frame is longword aligned. Other FDDI driver
160 * implementations may not need the extra padding and can start copying
161 * or DMAing directly from the FC byte which starts at skb->data. Should
162 * another driver implementation need ADDITIONAL padding, the net_init.c
163 * module should be updated and dev->hard_header_len should be increased.
164 * NOTE: To maintain the alignment on the data portion of the packet,
165 * dev->hard_header_len should always be evenly divisible by 4 and at
166 * least 24 bytes in size.
168 * Modification History:
169 * Date Name Description
170 * 16-Aug-96 LVS Created.
171 * 20-Aug-96 LVS Updated dfx_probe so that version information
172 * string is only displayed if 1 or more cards are
173 * found. Changed dfx_rcv_queue_process to copy
174 * 3 NULL bytes before FC to ensure that data is
175 * longword aligned in receive buffer.
176 * 09-Sep-96 LVS Updated dfx_ctl_set_multicast_list to enable
177 * LLC group promiscuous mode if multicast list
178 * is too large. LLC individual/group promiscuous
179 * mode is now disabled if IFF_PROMISC flag not set.
180 * dfx_xmt_queue_pkt no longer checks for NULL skb
181 * on Alan Cox recommendation. Added node address
183 * 12-Sep-96 LVS Reset current address to factory address during
184 * device open. Updated transmit path to post a
185 * single fragment which includes PRH->end of data.
186 * Mar 2000 AC Did various cleanups for 2.3.x
187 * Jun 2000 jgarzik PCI and resource alloc cleanups
188 * Jul 2000 tjeerd Much cleanup and some bug fixes
189 * Sep 2000 tjeerd Fix leak on unload, cosmetic code cleanup
190 * Feb 2001 Skb allocation fixes
191 * Feb 2001 davej PCI enable cleanups.
192 * 04 Aug 2003 macro Converted to the DMA API.
193 * 14 Aug 2004 macro Fix device names reported.
194 * 14 Jun 2005 macro Use irqreturn_t.
195 * 23 Oct 2006 macro Big-endian host support.
200 #include <linux/module.h>
201 #include <linux/kernel.h>
202 #include <linux/string.h>
203 #include <linux/errno.h>
204 #include <linux/ioport.h>
205 #include <linux/slab.h>
206 #include <linux/interrupt.h>
207 #include <linux/pci.h>
208 #include <linux/delay.h>
209 #include <linux/init.h>
210 #include <linux/netdevice.h>
211 #include <linux/fddidevice.h>
212 #include <linux/skbuff.h>
213 #include <linux/bitops.h>
215 #include <asm/byteorder.h>
220 /* Version information string should be updated prior to each new release! */
221 #define DRV_NAME "defxx"
222 #define DRV_VERSION "v1.09"
223 #define DRV_RELDATE "2006/10/23"
225 static char version[] __devinitdata =
226 DRV_NAME ": " DRV_VERSION " " DRV_RELDATE
227 " Lawrence V. Stefani and others\n";
229 #define DYNAMIC_BUFFERS 1
231 #define SKBUFF_RX_COPYBREAK 200
233 * NEW_SKB_SIZE = PI_RCV_DATA_K_SIZE_MAX+128 to allow 128 byte
234 * alignment for compatibility with old EISA boards.
236 #define NEW_SKB_SIZE (PI_RCV_DATA_K_SIZE_MAX+128)
238 /* Define module-wide (static) routines */
240 static void dfx_bus_init(struct net_device *dev);
241 static void dfx_bus_config_check(DFX_board_t *bp);
243 static int dfx_driver_init(struct net_device *dev, const char *print_name);
244 static int dfx_adap_init(DFX_board_t *bp, int get_buffers);
246 static int dfx_open(struct net_device *dev);
247 static int dfx_close(struct net_device *dev);
249 static void dfx_int_pr_halt_id(DFX_board_t *bp);
250 static void dfx_int_type_0_process(DFX_board_t *bp);
251 static void dfx_int_common(struct net_device *dev);
252 static irqreturn_t dfx_interrupt(int irq, void *dev_id);
254 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev);
255 static void dfx_ctl_set_multicast_list(struct net_device *dev);
256 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr);
257 static int dfx_ctl_update_cam(DFX_board_t *bp);
258 static int dfx_ctl_update_filters(DFX_board_t *bp);
260 static int dfx_hw_dma_cmd_req(DFX_board_t *bp);
261 static int dfx_hw_port_ctrl_req(DFX_board_t *bp, PI_UINT32 command, PI_UINT32 data_a, PI_UINT32 data_b, PI_UINT32 *host_data);
262 static void dfx_hw_adap_reset(DFX_board_t *bp, PI_UINT32 type);
263 static int dfx_hw_adap_state_rd(DFX_board_t *bp);
264 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type);
266 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers);
267 static void dfx_rcv_queue_process(DFX_board_t *bp);
268 static void dfx_rcv_flush(DFX_board_t *bp);
270 static int dfx_xmt_queue_pkt(struct sk_buff *skb, struct net_device *dev);
271 static int dfx_xmt_done(DFX_board_t *bp);
272 static void dfx_xmt_flush(DFX_board_t *bp);
274 /* Define module-wide (static) variables */
276 static struct net_device *root_dfx_eisa_dev;
280 * =======================
281 * = dfx_port_write_byte =
282 * = dfx_port_read_byte =
283 * = dfx_port_write_long =
284 * = dfx_port_read_long =
285 * =======================
288 * Routines for reading and writing values from/to adapter
294 * bp - pointer to board information
295 * offset - register offset from base I/O address
296 * data - for dfx_port_write_byte and dfx_port_write_long, this
297 * is a value to write.
298 * for dfx_port_read_byte and dfx_port_read_byte, this
299 * is a pointer to store the read value.
301 * Functional Description:
302 * These routines perform the correct operation to read or write
303 * the adapter register.
305 * EISA port block base addresses are based on the slot number in which the
306 * controller is installed. For example, if the EISA controller is installed
307 * in slot 4, the port block base address is 0x4000. If the controller is
308 * installed in slot 2, the port block base address is 0x2000, and so on.
309 * This port block can be used to access PDQ, ESIC, and DEFEA on-board
310 * registers using the register offsets defined in DEFXX.H.
312 * PCI port block base addresses are assigned by the PCI BIOS or system
313 * firmware. There is one 128 byte port block which can be accessed. It
314 * allows for I/O mapping of both PDQ and PFI registers using the register
315 * offsets defined in DEFXX.H.
321 * bp->base_addr is a valid base I/O address for this adapter.
322 * offset is a valid register offset for this adapter.
325 * Rather than produce macros for these functions, these routines
326 * are defined using "inline" to ensure that the compiler will
327 * generate inline code and not waste a procedure call and return.
328 * This provides all the benefits of macros, but with the
329 * advantage of strict data type checking.
332 static inline void dfx_port_write_byte(
339 u16 port = bp->base_addr + offset;
344 static inline void dfx_port_read_byte(
351 u16 port = bp->base_addr + offset;
356 static inline void dfx_port_write_long(
363 u16 port = bp->base_addr + offset;
368 static inline void dfx_port_read_long(
375 u16 port = bp->base_addr + offset;
383 * = dfx_init_one_pci_or_eisa =
387 * Initializes a supported FDDI EISA or PCI controller
393 * pdev - pointer to pci device information (NULL for EISA)
394 * ioaddr - pointer to port (NULL for PCI)
396 * Functional Description:
399 * 0 - This device (fddi0, fddi1, etc) configured successfully
400 * -EBUSY - Failed to get resources, or dfx_driver_init failed.
403 * It compiles so it should work :-( (PCI cards do :-)
406 * Device structures for FDDI adapters (fddi0, fddi1, etc) are
407 * initialized and the board resources are read and stored in
408 * the device structure.
410 static int __devinit dfx_init_one_pci_or_eisa(struct pci_dev *pdev, long ioaddr)
412 static int version_disp;
413 char *print_name = DRV_NAME;
414 struct net_device *dev;
415 DFX_board_t *bp; /* board pointer */
416 int alloc_size; /* total buffer size used */
419 if (!version_disp) { /* display version info if adapter is found */
420 version_disp = 1; /* set display flag to TRUE so that */
421 printk(version); /* we only display this string ONCE */
425 print_name = pci_name(pdev);
427 dev = alloc_fddidev(sizeof(*bp));
429 printk(KERN_ERR "%s: unable to allocate fddidev, aborting\n",
434 /* Enable PCI device. */
436 err = pci_enable_device (pdev);
437 if (err) goto err_out;
438 ioaddr = pci_resource_start (pdev, 1);
441 SET_MODULE_OWNER(dev);
443 SET_NETDEV_DEV(dev, &pdev->dev);
447 if (!request_region(ioaddr,
448 pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN,
450 printk(KERN_ERR "%s: Cannot reserve I/O resource "
451 "0x%x @ 0x%lx, aborting\n", print_name,
452 pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN, ioaddr);
457 /* Initialize new device structure */
459 dev->base_addr = ioaddr; /* save port (I/O) base address */
461 dev->get_stats = dfx_ctl_get_stats;
462 dev->open = dfx_open;
463 dev->stop = dfx_close;
464 dev->hard_start_xmit = dfx_xmt_queue_pkt;
465 dev->set_multicast_list = dfx_ctl_set_multicast_list;
466 dev->set_mac_address = dfx_ctl_set_mac_address;
470 bp->bus_type = DFX_BUS_TYPE_EISA;
471 bp->next = root_dfx_eisa_dev;
472 root_dfx_eisa_dev = dev;
475 bp->bus_type = DFX_BUS_TYPE_PCI;
477 pci_set_drvdata (pdev, dev);
478 pci_set_master (pdev);
481 if (dfx_driver_init(dev, print_name) != DFX_K_SUCCESS) {
486 err = register_netdev(dev);
490 printk("%s: registered as %s\n", print_name, dev->name);
494 alloc_size = sizeof(PI_DESCR_BLOCK) +
495 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
496 #ifndef DYNAMIC_BUFFERS
497 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
499 sizeof(PI_CONSUMER_BLOCK) +
500 (PI_ALIGN_K_DESC_BLK - 1);
502 pci_free_consistent(pdev, alloc_size,
503 bp->kmalloced, bp->kmalloced_dma);
505 release_region(ioaddr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN);
511 static int __devinit dfx_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
513 return dfx_init_one_pci_or_eisa(pdev, 0);
516 static int __init dfx_eisa_init(void)
519 int i; /* used in for loops */
520 u16 port; /* temporary I/O (port) address */
521 u32 slot_id; /* EISA hardware (slot) ID read from adapter */
523 DBG_printk("In dfx_eisa_init...\n");
525 /* Scan for FDDI EISA controllers */
527 for (i=0; i < DFX_MAX_EISA_SLOTS; i++) /* only scan for up to 16 EISA slots */
529 port = (i << 12) + PI_ESIC_K_SLOT_ID; /* port = I/O address for reading slot ID */
530 slot_id = inl(port); /* read EISA HW (slot) ID */
531 if ((slot_id & 0xF0FFFFFF) == DEFEA_PRODUCT_ID)
533 port = (i << 12); /* recalc base addr */
535 if (dfx_init_one_pci_or_eisa(NULL, port) == 0) rc = 0;
547 * Initializes EISA and PCI controller bus-specific logic.
553 * dev - pointer to device information
555 * Functional Description:
556 * Determine and save adapter IRQ in device table,
557 * then perform bus-specific logic initialization.
563 * dev->base_addr has already been set with the proper
564 * base I/O address for this device.
567 * Interrupts are enabled at the adapter bus-specific logic.
568 * Note: Interrupts at the DMA engine (PDQ chip) are not
572 static void __devinit dfx_bus_init(struct net_device *dev)
574 DFX_board_t *bp = dev->priv;
575 u8 val; /* used for I/O read/writes */
577 DBG_printk("In dfx_bus_init...\n");
580 * Initialize base I/O address field in bp structure
582 * Note: bp->base_addr is the same as dev->base_addr.
583 * It's useful because often we'll need to read
584 * or write registers where we already have the
585 * bp pointer instead of the dev pointer. Having
586 * the base address in the bp structure will
587 * save a pointer dereference.
589 * IMPORTANT!! This field must be defined before
590 * any of the dfx_port_* inline functions are
594 bp->base_addr = dev->base_addr;
596 /* And a pointer back to the net_device struct */
599 /* Initialize adapter based on bus type */
601 if (bp->bus_type == DFX_BUS_TYPE_EISA)
603 /* Get the interrupt level from the ESIC chip */
605 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
606 switch ((val & PI_CONFIG_STAT_0_M_IRQ) >> PI_CONFIG_STAT_0_V_IRQ)
608 case PI_CONFIG_STAT_0_IRQ_K_9:
612 case PI_CONFIG_STAT_0_IRQ_K_10:
616 case PI_CONFIG_STAT_0_IRQ_K_11:
620 case PI_CONFIG_STAT_0_IRQ_K_15:
625 /* Enable access to I/O on the board by writing 0x03 to Function Control Register */
627 dfx_port_write_byte(bp, PI_ESIC_K_FUNCTION_CNTRL, PI_ESIC_K_FUNCTION_CNTRL_IO_ENB);
629 /* Set the I/O decode range of the board */
631 val = ((dev->base_addr >> 12) << PI_IO_CMP_V_SLOT);
632 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_0_1, val);
633 dfx_port_write_byte(bp, PI_ESIC_K_IO_CMP_1_1, val);
635 /* Enable access to rest of module (including PDQ and packet memory) */
637 dfx_port_write_byte(bp, PI_ESIC_K_SLOT_CNTRL, PI_SLOT_CNTRL_M_ENB);
640 * Map PDQ registers into I/O space. This is done by clearing a bit
641 * in Burst Holdoff register.
644 dfx_port_read_byte(bp, PI_ESIC_K_BURST_HOLDOFF, &val);
645 dfx_port_write_byte(bp, PI_ESIC_K_BURST_HOLDOFF, (val & ~PI_BURST_HOLDOFF_M_MEM_MAP));
647 /* Enable interrupts at EISA bus interface chip (ESIC) */
649 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &val);
650 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, (val | PI_CONFIG_STAT_0_M_INT_ENB));
654 struct pci_dev *pdev = bp->pci_dev;
656 /* Get the interrupt level from the PCI Configuration Table */
658 dev->irq = pdev->irq;
660 /* Check Latency Timer and set if less than minimal */
662 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val);
663 if (val < PFI_K_LAT_TIMER_MIN) /* if less than min, override with default */
665 val = PFI_K_LAT_TIMER_DEF;
666 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, val);
669 /* Enable interrupts at PCI bus interface chip (PFI) */
671 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL, (PFI_MODE_M_PDQ_INT_ENB | PFI_MODE_M_DMA_ENB));
677 * ========================
678 * = dfx_bus_config_check =
679 * ========================
682 * Checks the configuration (burst size, full-duplex, etc.) If any parameters
683 * are illegal, then this routine will set new defaults.
689 * bp - pointer to board information
691 * Functional Description:
692 * For Revision 1 FDDI EISA, Revision 2 or later FDDI EISA with rev E or later
693 * PDQ, and all FDDI PCI controllers, all values are legal.
699 * dfx_adap_init has NOT been called yet so burst size and other items have
706 static void __devinit dfx_bus_config_check(DFX_board_t *bp)
708 int status; /* return code from adapter port control call */
709 u32 slot_id; /* EISA-bus hardware id (DEC3001, DEC3002,...) */
710 u32 host_data; /* LW data returned from port control call */
712 DBG_printk("In dfx_bus_config_check...\n");
714 /* Configuration check only valid for EISA adapter */
716 if (bp->bus_type == DFX_BUS_TYPE_EISA)
718 dfx_port_read_long(bp, PI_ESIC_K_SLOT_ID, &slot_id);
721 * First check if revision 2 EISA controller. Rev. 1 cards used
722 * PDQ revision B, so no workaround needed in this case. Rev. 3
723 * cards used PDQ revision E, so no workaround needed in this
724 * case, either. Only Rev. 2 cards used either Rev. D or E
725 * chips, so we must verify the chip revision on Rev. 2 cards.
728 if (slot_id == DEFEA_PROD_ID_2)
731 * Revision 2 FDDI EISA controller found, so let's check PDQ
732 * revision of adapter.
735 status = dfx_hw_port_ctrl_req(bp,
737 PI_SUB_CMD_K_PDQ_REV_GET,
740 if ((status != DFX_K_SUCCESS) || (host_data == 2))
743 * Either we couldn't determine the PDQ revision, or
744 * we determined that it is at revision D. In either case,
745 * we need to implement the workaround.
748 /* Ensure that the burst size is set to 8 longwords or less */
750 switch (bp->burst_size)
752 case PI_PDATA_B_DMA_BURST_SIZE_32:
753 case PI_PDATA_B_DMA_BURST_SIZE_16:
754 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_8;
761 /* Ensure that full-duplex mode is not enabled */
763 bp->full_duplex_enb = PI_SNMP_K_FALSE;
771 * ===================
772 * = dfx_driver_init =
773 * ===================
776 * Initializes remaining adapter board structure information
777 * and makes sure adapter is in a safe state prior to dfx_open().
783 * dev - pointer to device information
784 * print_name - printable device name
786 * Functional Description:
787 * This function allocates additional resources such as the host memory
788 * blocks needed by the adapter (eg. descriptor and consumer blocks).
789 * Remaining bus initialization steps are also completed. The adapter
790 * is also reset so that it is in the DMA_UNAVAILABLE state. The OS
791 * must call dfx_open() to open the adapter and bring it on-line.
794 * DFX_K_SUCCESS - initialization succeeded
795 * DFX_K_FAILURE - initialization failed - could not allocate memory
796 * or read adapter MAC address
799 * Memory allocated from pci_alloc_consistent() call is physically
800 * contiguous, locked memory.
803 * Adapter is reset and should be in DMA_UNAVAILABLE state before
804 * returning from this routine.
807 static int __devinit dfx_driver_init(struct net_device *dev,
808 const char *print_name)
810 DFX_board_t *bp = dev->priv;
811 int alloc_size; /* total buffer size needed */
812 char *top_v, *curr_v; /* virtual addrs into memory block */
813 dma_addr_t top_p, curr_p; /* physical addrs into memory block */
814 u32 data; /* host data register value */
816 DBG_printk("In dfx_driver_init...\n");
818 /* Initialize bus-specific hardware registers */
823 * Initialize default values for configurable parameters
825 * Note: All of these parameters are ones that a user may
826 * want to customize. It'd be nice to break these
827 * out into Space.c or someplace else that's more
828 * accessible/understandable than this file.
831 bp->full_duplex_enb = PI_SNMP_K_FALSE;
832 bp->req_ttrt = 8 * 12500; /* 8ms in 80 nanosec units */
833 bp->burst_size = PI_PDATA_B_DMA_BURST_SIZE_DEF;
834 bp->rcv_bufs_to_post = RCV_BUFS_DEF;
837 * Ensure that HW configuration is OK
839 * Note: Depending on the hardware revision, we may need to modify
840 * some of the configurable parameters to workaround hardware
841 * limitations. We'll perform this configuration check AFTER
842 * setting the parameters to their default values.
845 dfx_bus_config_check(bp);
847 /* Disable PDQ interrupts first */
849 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
851 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
853 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
855 /* Read the factory MAC address from the adapter then save it */
857 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_LO, 0,
858 &data) != DFX_K_SUCCESS) {
859 printk("%s: Could not read adapter factory MAC address!\n",
861 return(DFX_K_FAILURE);
863 data = cpu_to_le32(data);
864 memcpy(&bp->factory_mac_addr[0], &data, sizeof(u32));
866 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_MLA, PI_PDATA_A_MLA_K_HI, 0,
867 &data) != DFX_K_SUCCESS) {
868 printk("%s: Could not read adapter factory MAC address!\n",
870 return(DFX_K_FAILURE);
872 data = cpu_to_le32(data);
873 memcpy(&bp->factory_mac_addr[4], &data, sizeof(u16));
876 * Set current address to factory address
878 * Note: Node address override support is handled through
879 * dfx_ctl_set_mac_address.
882 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
883 if (bp->bus_type == DFX_BUS_TYPE_EISA)
884 printk("%s: DEFEA at I/O addr = 0x%lX, IRQ = %d, "
885 "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
886 print_name, dev->base_addr, dev->irq,
887 dev->dev_addr[0], dev->dev_addr[1],
888 dev->dev_addr[2], dev->dev_addr[3],
889 dev->dev_addr[4], dev->dev_addr[5]);
891 printk("%s: DEFPA at I/O addr = 0x%lX, IRQ = %d, "
892 "Hardware addr = %02X-%02X-%02X-%02X-%02X-%02X\n",
893 print_name, dev->base_addr, dev->irq,
894 dev->dev_addr[0], dev->dev_addr[1],
895 dev->dev_addr[2], dev->dev_addr[3],
896 dev->dev_addr[4], dev->dev_addr[5]);
899 * Get memory for descriptor block, consumer block, and other buffers
900 * that need to be DMA read or written to by the adapter.
903 alloc_size = sizeof(PI_DESCR_BLOCK) +
904 PI_CMD_REQ_K_SIZE_MAX +
905 PI_CMD_RSP_K_SIZE_MAX +
906 #ifndef DYNAMIC_BUFFERS
907 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
909 sizeof(PI_CONSUMER_BLOCK) +
910 (PI_ALIGN_K_DESC_BLK - 1);
911 bp->kmalloced = top_v = pci_alloc_consistent(bp->pci_dev, alloc_size,
914 printk("%s: Could not allocate memory for host buffers "
915 "and structures!\n", print_name);
916 return(DFX_K_FAILURE);
918 memset(top_v, 0, alloc_size); /* zero out memory before continuing */
919 top_p = bp->kmalloced_dma; /* get physical address of buffer */
922 * To guarantee the 8K alignment required for the descriptor block, 8K - 1
923 * plus the amount of memory needed was allocated. The physical address
924 * is now 8K aligned. By carving up the memory in a specific order,
925 * we'll guarantee the alignment requirements for all other structures.
927 * Note: If the assumptions change regarding the non-paged, non-cached,
928 * physically contiguous nature of the memory block or the address
929 * alignments, then we'll need to implement a different algorithm
930 * for allocating the needed memory.
933 curr_p = ALIGN(top_p, PI_ALIGN_K_DESC_BLK);
934 curr_v = top_v + (curr_p - top_p);
936 /* Reserve space for descriptor block */
938 bp->descr_block_virt = (PI_DESCR_BLOCK *) curr_v;
939 bp->descr_block_phys = curr_p;
940 curr_v += sizeof(PI_DESCR_BLOCK);
941 curr_p += sizeof(PI_DESCR_BLOCK);
943 /* Reserve space for command request buffer */
945 bp->cmd_req_virt = (PI_DMA_CMD_REQ *) curr_v;
946 bp->cmd_req_phys = curr_p;
947 curr_v += PI_CMD_REQ_K_SIZE_MAX;
948 curr_p += PI_CMD_REQ_K_SIZE_MAX;
950 /* Reserve space for command response buffer */
952 bp->cmd_rsp_virt = (PI_DMA_CMD_RSP *) curr_v;
953 bp->cmd_rsp_phys = curr_p;
954 curr_v += PI_CMD_RSP_K_SIZE_MAX;
955 curr_p += PI_CMD_RSP_K_SIZE_MAX;
957 /* Reserve space for the LLC host receive queue buffers */
959 bp->rcv_block_virt = curr_v;
960 bp->rcv_block_phys = curr_p;
962 #ifndef DYNAMIC_BUFFERS
963 curr_v += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
964 curr_p += (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX);
967 /* Reserve space for the consumer block */
969 bp->cons_block_virt = (PI_CONSUMER_BLOCK *) curr_v;
970 bp->cons_block_phys = curr_p;
972 /* Display virtual and physical addresses if debug driver */
974 DBG_printk("%s: Descriptor block virt = %0lX, phys = %0X\n",
976 (long)bp->descr_block_virt, bp->descr_block_phys);
977 DBG_printk("%s: Command Request buffer virt = %0lX, phys = %0X\n",
978 print_name, (long)bp->cmd_req_virt, bp->cmd_req_phys);
979 DBG_printk("%s: Command Response buffer virt = %0lX, phys = %0X\n",
980 print_name, (long)bp->cmd_rsp_virt, bp->cmd_rsp_phys);
981 DBG_printk("%s: Receive buffer block virt = %0lX, phys = %0X\n",
982 print_name, (long)bp->rcv_block_virt, bp->rcv_block_phys);
983 DBG_printk("%s: Consumer block virt = %0lX, phys = %0X\n",
984 print_name, (long)bp->cons_block_virt, bp->cons_block_phys);
986 return(DFX_K_SUCCESS);
996 * Brings the adapter to the link avail/link unavailable state.
1002 * bp - pointer to board information
1003 * get_buffers - non-zero if buffers to be allocated
1005 * Functional Description:
1006 * Issues the low-level firmware/hardware calls necessary to bring
1007 * the adapter up, or to properly reset and restore adapter during
1011 * DFX_K_SUCCESS - Adapter brought up successfully
1012 * DFX_K_FAILURE - Adapter initialization failed
1015 * bp->reset_type should be set to a valid reset type value before
1016 * calling this routine.
1019 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1020 * upon a successful return of this routine.
1023 static int dfx_adap_init(DFX_board_t *bp, int get_buffers)
1025 DBG_printk("In dfx_adap_init...\n");
1027 /* Disable PDQ interrupts first */
1029 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1031 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1033 if (dfx_hw_dma_uninit(bp, bp->reset_type) != DFX_K_SUCCESS)
1035 printk("%s: Could not uninitialize/reset adapter!\n", bp->dev->name);
1036 return(DFX_K_FAILURE);
1040 * When the PDQ is reset, some false Type 0 interrupts may be pending,
1041 * so we'll acknowledge all Type 0 interrupts now before continuing.
1044 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, PI_HOST_INT_K_ACK_ALL_TYPE_0);
1047 * Clear Type 1 and Type 2 registers before going to DMA_AVAILABLE state
1049 * Note: We only need to clear host copies of these registers. The PDQ reset
1050 * takes care of the on-board register values.
1053 bp->cmd_req_reg.lword = 0;
1054 bp->cmd_rsp_reg.lword = 0;
1055 bp->rcv_xmt_reg.lword = 0;
1057 /* Clear consumer block before going to DMA_AVAILABLE state */
1059 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1061 /* Initialize the DMA Burst Size */
1063 if (dfx_hw_port_ctrl_req(bp,
1065 PI_SUB_CMD_K_BURST_SIZE_SET,
1067 NULL) != DFX_K_SUCCESS)
1069 printk("%s: Could not set adapter burst size!\n", bp->dev->name);
1070 return(DFX_K_FAILURE);
1074 * Set base address of Consumer Block
1076 * Assumption: 32-bit physical address of consumer block is 64 byte
1077 * aligned. That is, bits 0-5 of the address must be zero.
1080 if (dfx_hw_port_ctrl_req(bp,
1081 PI_PCTRL_M_CONS_BLOCK,
1082 bp->cons_block_phys,
1084 NULL) != DFX_K_SUCCESS)
1086 printk("%s: Could not set consumer block address!\n", bp->dev->name);
1087 return(DFX_K_FAILURE);
1091 * Set the base address of Descriptor Block and bring adapter
1092 * to DMA_AVAILABLE state.
1094 * Note: We also set the literal and data swapping requirements
1097 * Assumption: 32-bit physical address of descriptor block
1098 * is 8Kbyte aligned.
1100 if (dfx_hw_port_ctrl_req(bp, PI_PCTRL_M_INIT,
1101 (u32)(bp->descr_block_phys |
1102 PI_PDATA_A_INIT_M_BSWAP_INIT),
1103 0, NULL) != DFX_K_SUCCESS) {
1104 printk("%s: Could not set descriptor block address!\n",
1106 return DFX_K_FAILURE;
1109 /* Set transmit flush timeout value */
1111 bp->cmd_req_virt->cmd_type = PI_CMD_K_CHARS_SET;
1112 bp->cmd_req_virt->char_set.item[0].item_code = PI_ITEM_K_FLUSH_TIME;
1113 bp->cmd_req_virt->char_set.item[0].value = 3; /* 3 seconds */
1114 bp->cmd_req_virt->char_set.item[0].item_index = 0;
1115 bp->cmd_req_virt->char_set.item[1].item_code = PI_ITEM_K_EOL;
1116 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1118 printk("%s: DMA command request failed!\n", bp->dev->name);
1119 return(DFX_K_FAILURE);
1122 /* Set the initial values for eFDXEnable and MACTReq MIB objects */
1124 bp->cmd_req_virt->cmd_type = PI_CMD_K_SNMP_SET;
1125 bp->cmd_req_virt->snmp_set.item[0].item_code = PI_ITEM_K_FDX_ENB_DIS;
1126 bp->cmd_req_virt->snmp_set.item[0].value = bp->full_duplex_enb;
1127 bp->cmd_req_virt->snmp_set.item[0].item_index = 0;
1128 bp->cmd_req_virt->snmp_set.item[1].item_code = PI_ITEM_K_MAC_T_REQ;
1129 bp->cmd_req_virt->snmp_set.item[1].value = bp->req_ttrt;
1130 bp->cmd_req_virt->snmp_set.item[1].item_index = 0;
1131 bp->cmd_req_virt->snmp_set.item[2].item_code = PI_ITEM_K_EOL;
1132 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1134 printk("%s: DMA command request failed!\n", bp->dev->name);
1135 return(DFX_K_FAILURE);
1138 /* Initialize adapter CAM */
1140 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
1142 printk("%s: Adapter CAM update failed!\n", bp->dev->name);
1143 return(DFX_K_FAILURE);
1146 /* Initialize adapter filters */
1148 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
1150 printk("%s: Adapter filters update failed!\n", bp->dev->name);
1151 return(DFX_K_FAILURE);
1155 * Remove any existing dynamic buffers (i.e. if the adapter is being
1162 /* Initialize receive descriptor block and produce buffers */
1164 if (dfx_rcv_init(bp, get_buffers))
1166 printk("%s: Receive buffer allocation failed\n", bp->dev->name);
1169 return(DFX_K_FAILURE);
1172 /* Issue START command and bring adapter to LINK_(UN)AVAILABLE state */
1174 bp->cmd_req_virt->cmd_type = PI_CMD_K_START;
1175 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1177 printk("%s: Start command failed\n", bp->dev->name);
1180 return(DFX_K_FAILURE);
1183 /* Initialization succeeded, reenable PDQ interrupts */
1185 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_ENABLE_DEF_INTS);
1186 return(DFX_K_SUCCESS);
1202 * dev - pointer to device information
1204 * Functional Description:
1205 * This function brings the adapter to an operational state.
1208 * 0 - Adapter was successfully opened
1209 * -EAGAIN - Could not register IRQ or adapter initialization failed
1212 * This routine should only be called for a device that was
1213 * initialized successfully.
1216 * Adapter should be in LINK_AVAILABLE or LINK_UNAVAILABLE state
1217 * if the open is successful.
1220 static int dfx_open(struct net_device *dev)
1223 DFX_board_t *bp = dev->priv;
1225 DBG_printk("In dfx_open...\n");
1227 /* Register IRQ - support shared interrupts by passing device ptr */
1229 ret = request_irq(dev->irq, dfx_interrupt, IRQF_SHARED, dev->name, dev);
1231 printk(KERN_ERR "%s: Requested IRQ %d is busy\n", dev->name, dev->irq);
1236 * Set current address to factory MAC address
1238 * Note: We've already done this step in dfx_driver_init.
1239 * However, it's possible that a user has set a node
1240 * address override, then closed and reopened the
1241 * adapter. Unless we reset the device address field
1242 * now, we'll continue to use the existing modified
1246 memcpy(dev->dev_addr, bp->factory_mac_addr, FDDI_K_ALEN);
1248 /* Clear local unicast/multicast address tables and counts */
1250 memset(bp->uc_table, 0, sizeof(bp->uc_table));
1251 memset(bp->mc_table, 0, sizeof(bp->mc_table));
1255 /* Disable promiscuous filter settings */
1257 bp->ind_group_prom = PI_FSTATE_K_BLOCK;
1258 bp->group_prom = PI_FSTATE_K_BLOCK;
1260 spin_lock_init(&bp->lock);
1262 /* Reset and initialize adapter */
1264 bp->reset_type = PI_PDATA_A_RESET_M_SKIP_ST; /* skip self-test */
1265 if (dfx_adap_init(bp, 1) != DFX_K_SUCCESS)
1267 printk(KERN_ERR "%s: Adapter open failed!\n", dev->name);
1268 free_irq(dev->irq, dev);
1272 /* Set device structure info */
1273 netif_start_queue(dev);
1284 * Closes the device/module.
1290 * dev - pointer to device information
1292 * Functional Description:
1293 * This routine closes the adapter and brings it to a safe state.
1294 * The interrupt service routine is deregistered with the OS.
1295 * The adapter can be opened again with another call to dfx_open().
1301 * No further requests for this adapter are made after this routine is
1302 * called. dfx_open() can be called to reset and reinitialize the
1306 * Adapter should be in DMA_UNAVAILABLE state upon completion of this
1310 static int dfx_close(struct net_device *dev)
1312 DFX_board_t *bp = dev->priv;
1314 DBG_printk("In dfx_close...\n");
1316 /* Disable PDQ interrupts first */
1318 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1320 /* Place adapter in DMA_UNAVAILABLE state by resetting adapter */
1322 (void) dfx_hw_dma_uninit(bp, PI_PDATA_A_RESET_M_SKIP_ST);
1325 * Flush any pending transmit buffers
1327 * Note: It's important that we flush the transmit buffers
1328 * BEFORE we clear our copy of the Type 2 register.
1329 * Otherwise, we'll have no idea how many buffers
1336 * Clear Type 1 and Type 2 registers after adapter reset
1338 * Note: Even though we're closing the adapter, it's
1339 * possible that an interrupt will occur after
1340 * dfx_close is called. Without some assurance to
1341 * the contrary we want to make sure that we don't
1342 * process receive and transmit LLC frames and update
1343 * the Type 2 register with bad information.
1346 bp->cmd_req_reg.lword = 0;
1347 bp->cmd_rsp_reg.lword = 0;
1348 bp->rcv_xmt_reg.lword = 0;
1350 /* Clear consumer block for the same reason given above */
1352 memset(bp->cons_block_virt, 0, sizeof(PI_CONSUMER_BLOCK));
1354 /* Release all dynamically allocate skb in the receive ring. */
1358 /* Clear device structure flags */
1360 netif_stop_queue(dev);
1362 /* Deregister (free) IRQ */
1364 free_irq(dev->irq, dev);
1371 * ======================
1372 * = dfx_int_pr_halt_id =
1373 * ======================
1376 * Displays halt id's in string form.
1382 * bp - pointer to board information
1384 * Functional Description:
1385 * Determine current halt id and display appropriate string.
1397 static void dfx_int_pr_halt_id(DFX_board_t *bp)
1399 PI_UINT32 port_status; /* PDQ port status register value */
1400 PI_UINT32 halt_id; /* PDQ port status halt ID */
1402 /* Read the latest port status */
1404 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1406 /* Display halt state transition information */
1408 halt_id = (port_status & PI_PSTATUS_M_HALT_ID) >> PI_PSTATUS_V_HALT_ID;
1411 case PI_HALT_ID_K_SELFTEST_TIMEOUT:
1412 printk("%s: Halt ID: Selftest Timeout\n", bp->dev->name);
1415 case PI_HALT_ID_K_PARITY_ERROR:
1416 printk("%s: Halt ID: Host Bus Parity Error\n", bp->dev->name);
1419 case PI_HALT_ID_K_HOST_DIR_HALT:
1420 printk("%s: Halt ID: Host-Directed Halt\n", bp->dev->name);
1423 case PI_HALT_ID_K_SW_FAULT:
1424 printk("%s: Halt ID: Adapter Software Fault\n", bp->dev->name);
1427 case PI_HALT_ID_K_HW_FAULT:
1428 printk("%s: Halt ID: Adapter Hardware Fault\n", bp->dev->name);
1431 case PI_HALT_ID_K_PC_TRACE:
1432 printk("%s: Halt ID: FDDI Network PC Trace Path Test\n", bp->dev->name);
1435 case PI_HALT_ID_K_DMA_ERROR:
1436 printk("%s: Halt ID: Adapter DMA Error\n", bp->dev->name);
1439 case PI_HALT_ID_K_IMAGE_CRC_ERROR:
1440 printk("%s: Halt ID: Firmware Image CRC Error\n", bp->dev->name);
1443 case PI_HALT_ID_K_BUS_EXCEPTION:
1444 printk("%s: Halt ID: 68000 Bus Exception\n", bp->dev->name);
1448 printk("%s: Halt ID: Unknown (code = %X)\n", bp->dev->name, halt_id);
1455 * ==========================
1456 * = dfx_int_type_0_process =
1457 * ==========================
1460 * Processes Type 0 interrupts.
1466 * bp - pointer to board information
1468 * Functional Description:
1469 * Processes all enabled Type 0 interrupts. If the reason for the interrupt
1470 * is a serious fault on the adapter, then an error message is displayed
1471 * and the adapter is reset.
1473 * One tricky potential timing window is the rapid succession of "link avail"
1474 * "link unavail" state change interrupts. The acknowledgement of the Type 0
1475 * interrupt must be done before reading the state from the Port Status
1476 * register. This is true because a state change could occur after reading
1477 * the data, but before acknowledging the interrupt. If this state change
1478 * does happen, it would be lost because the driver is using the old state,
1479 * and it will never know about the new state because it subsequently
1480 * acknowledges the state change interrupt.
1483 * read type 0 int reasons read type 0 int reasons
1484 * read adapter state ack type 0 interrupts
1485 * ack type 0 interrupts read adapter state
1486 * ... process interrupt ... ... process interrupt ...
1495 * An adapter reset may occur if the adapter has any Type 0 error interrupts
1496 * or if the port status indicates that the adapter is halted. The driver
1497 * is responsible for reinitializing the adapter with the current CAM
1498 * contents and adapter filter settings.
1501 static void dfx_int_type_0_process(DFX_board_t *bp)
1504 PI_UINT32 type_0_status; /* Host Interrupt Type 0 register */
1505 PI_UINT32 state; /* current adap state (from port status) */
1508 * Read host interrupt Type 0 register to determine which Type 0
1509 * interrupts are pending. Immediately write it back out to clear
1513 dfx_port_read_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, &type_0_status);
1514 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_0_STATUS, type_0_status);
1516 /* Check for Type 0 error interrupts */
1518 if (type_0_status & (PI_TYPE_0_STAT_M_NXM |
1519 PI_TYPE_0_STAT_M_PM_PAR_ERR |
1520 PI_TYPE_0_STAT_M_BUS_PAR_ERR))
1522 /* Check for Non-Existent Memory error */
1524 if (type_0_status & PI_TYPE_0_STAT_M_NXM)
1525 printk("%s: Non-Existent Memory Access Error\n", bp->dev->name);
1527 /* Check for Packet Memory Parity error */
1529 if (type_0_status & PI_TYPE_0_STAT_M_PM_PAR_ERR)
1530 printk("%s: Packet Memory Parity Error\n", bp->dev->name);
1532 /* Check for Host Bus Parity error */
1534 if (type_0_status & PI_TYPE_0_STAT_M_BUS_PAR_ERR)
1535 printk("%s: Host Bus Parity Error\n", bp->dev->name);
1537 /* Reset adapter and bring it back on-line */
1539 bp->link_available = PI_K_FALSE; /* link is no longer available */
1540 bp->reset_type = 0; /* rerun on-board diagnostics */
1541 printk("%s: Resetting adapter...\n", bp->dev->name);
1542 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1544 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1545 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1548 printk("%s: Adapter reset successful!\n", bp->dev->name);
1552 /* Check for transmit flush interrupt */
1554 if (type_0_status & PI_TYPE_0_STAT_M_XMT_FLUSH)
1556 /* Flush any pending xmt's and acknowledge the flush interrupt */
1558 bp->link_available = PI_K_FALSE; /* link is no longer available */
1559 dfx_xmt_flush(bp); /* flush any outstanding packets */
1560 (void) dfx_hw_port_ctrl_req(bp,
1561 PI_PCTRL_M_XMT_DATA_FLUSH_DONE,
1567 /* Check for adapter state change */
1569 if (type_0_status & PI_TYPE_0_STAT_M_STATE_CHANGE)
1571 /* Get latest adapter state */
1573 state = dfx_hw_adap_state_rd(bp); /* get adapter state */
1574 if (state == PI_STATE_K_HALTED)
1577 * Adapter has transitioned to HALTED state, try to reset
1578 * adapter to bring it back on-line. If reset fails,
1579 * leave the adapter in the broken state.
1582 printk("%s: Controller has transitioned to HALTED state!\n", bp->dev->name);
1583 dfx_int_pr_halt_id(bp); /* display halt id as string */
1585 /* Reset adapter and bring it back on-line */
1587 bp->link_available = PI_K_FALSE; /* link is no longer available */
1588 bp->reset_type = 0; /* rerun on-board diagnostics */
1589 printk("%s: Resetting adapter...\n", bp->dev->name);
1590 if (dfx_adap_init(bp, 0) != DFX_K_SUCCESS)
1592 printk("%s: Adapter reset failed! Disabling adapter interrupts.\n", bp->dev->name);
1593 dfx_port_write_long(bp, PI_PDQ_K_REG_HOST_INT_ENB, PI_HOST_INT_K_DISABLE_ALL_INTS);
1596 printk("%s: Adapter reset successful!\n", bp->dev->name);
1598 else if (state == PI_STATE_K_LINK_AVAIL)
1600 bp->link_available = PI_K_TRUE; /* set link available flag */
1607 * ==================
1608 * = dfx_int_common =
1609 * ==================
1612 * Interrupt service routine (ISR)
1618 * bp - pointer to board information
1620 * Functional Description:
1621 * This is the ISR which processes incoming adapter interrupts.
1627 * This routine assumes PDQ interrupts have not been disabled.
1628 * When interrupts are disabled at the PDQ, the Port Status register
1629 * is automatically cleared. This routine uses the Port Status
1630 * register value to determine whether a Type 0 interrupt occurred,
1631 * so it's important that adapter interrupts are not normally
1632 * enabled/disabled at the PDQ.
1634 * It's vital that this routine is NOT reentered for the
1635 * same board and that the OS is not in another section of
1636 * code (eg. dfx_xmt_queue_pkt) for the same board on a
1640 * Pending interrupts are serviced. Depending on the type of
1641 * interrupt, acknowledging and clearing the interrupt at the
1642 * PDQ involves writing a register to clear the interrupt bit
1643 * or updating completion indices.
1646 static void dfx_int_common(struct net_device *dev)
1648 DFX_board_t *bp = dev->priv;
1649 PI_UINT32 port_status; /* Port Status register */
1651 /* Process xmt interrupts - frequent case, so always call this routine */
1653 if(dfx_xmt_done(bp)) /* free consumed xmt packets */
1654 netif_wake_queue(dev);
1656 /* Process rcv interrupts - frequent case, so always call this routine */
1658 dfx_rcv_queue_process(bp); /* service received LLC frames */
1661 * Transmit and receive producer and completion indices are updated on the
1662 * adapter by writing to the Type 2 Producer register. Since the frequent
1663 * case is that we'll be processing either LLC transmit or receive buffers,
1664 * we'll optimize I/O writes by doing a single register write here.
1667 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
1669 /* Read PDQ Port Status register to find out which interrupts need processing */
1671 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
1673 /* Process Type 0 interrupts (if any) - infrequent, so only call when needed */
1675 if (port_status & PI_PSTATUS_M_TYPE_0_PENDING)
1676 dfx_int_type_0_process(bp); /* process Type 0 interrupts */
1686 * Interrupt processing routine
1689 * Whether a valid interrupt was seen.
1692 * irq - interrupt vector
1693 * dev_id - pointer to device information
1695 * Functional Description:
1696 * This routine calls the interrupt processing routine for this adapter. It
1697 * disables and reenables adapter interrupts, as appropriate. We can support
1698 * shared interrupts since the incoming dev_id pointer provides our device
1699 * structure context.
1702 * IRQ_HANDLED - an IRQ was handled.
1703 * IRQ_NONE - no IRQ was handled.
1706 * The interrupt acknowledgement at the hardware level (eg. ACKing the PIC
1707 * on Intel-based systems) is done by the operating system outside this
1710 * System interrupts are enabled through this call.
1713 * Interrupts are disabled, then reenabled at the adapter.
1716 static irqreturn_t dfx_interrupt(int irq, void *dev_id)
1718 struct net_device *dev = dev_id;
1719 DFX_board_t *bp; /* private board structure pointer */
1721 /* Get board pointer only if device structure is valid */
1725 /* See if we're already servicing an interrupt */
1727 /* Service adapter interrupts */
1729 if (bp->bus_type == DFX_BUS_TYPE_PCI) {
1732 dfx_port_read_long(bp, PFI_K_REG_STATUS, &status);
1733 if (!(status & PFI_STATUS_M_PDQ_INT))
1736 spin_lock(&bp->lock);
1738 /* Disable PDQ-PFI interrupts at PFI */
1739 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1740 PFI_MODE_M_DMA_ENB);
1742 /* Call interrupt service routine for this adapter */
1743 dfx_int_common(dev);
1745 /* Clear PDQ interrupt status bit and reenable interrupts */
1746 dfx_port_write_long(bp, PFI_K_REG_STATUS,
1747 PFI_STATUS_M_PDQ_INT);
1748 dfx_port_write_long(bp, PFI_K_REG_MODE_CTRL,
1749 (PFI_MODE_M_PDQ_INT_ENB |
1750 PFI_MODE_M_DMA_ENB));
1752 spin_unlock(&bp->lock);
1756 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status);
1757 if (!(status & PI_CONFIG_STAT_0_M_PEND))
1760 spin_lock(&bp->lock);
1762 /* Disable interrupts at the ESIC */
1763 status &= ~PI_CONFIG_STAT_0_M_INT_ENB;
1764 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status);
1766 /* Call interrupt service routine for this adapter */
1767 dfx_int_common(dev);
1769 /* Reenable interrupts at the ESIC */
1770 dfx_port_read_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, &status);
1771 status |= PI_CONFIG_STAT_0_M_INT_ENB;
1772 dfx_port_write_byte(bp, PI_ESIC_K_IO_CONFIG_STAT_0, status);
1774 spin_unlock(&bp->lock);
1782 * =====================
1783 * = dfx_ctl_get_stats =
1784 * =====================
1787 * Get statistics for FDDI adapter
1790 * Pointer to FDDI statistics structure
1793 * dev - pointer to device information
1795 * Functional Description:
1796 * Gets current MIB objects from adapter, then
1797 * returns FDDI statistics structure as defined
1800 * Note: Since the FDDI statistics structure is
1801 * still new and the device structure doesn't
1802 * have an FDDI-specific get statistics handler,
1803 * we'll return the FDDI statistics structure as
1804 * a pointer to an Ethernet statistics structure.
1805 * That way, at least the first part of the statistics
1806 * structure can be decoded properly, and it allows
1807 * "smart" applications to perform a second cast to
1808 * decode the FDDI-specific statistics.
1810 * We'll have to pay attention to this routine as the
1811 * device structure becomes more mature and LAN media
1824 static struct net_device_stats *dfx_ctl_get_stats(struct net_device *dev)
1826 DFX_board_t *bp = dev->priv;
1828 /* Fill the bp->stats structure with driver-maintained counters */
1830 bp->stats.gen.rx_packets = bp->rcv_total_frames;
1831 bp->stats.gen.tx_packets = bp->xmt_total_frames;
1832 bp->stats.gen.rx_bytes = bp->rcv_total_bytes;
1833 bp->stats.gen.tx_bytes = bp->xmt_total_bytes;
1834 bp->stats.gen.rx_errors = bp->rcv_crc_errors +
1835 bp->rcv_frame_status_errors +
1836 bp->rcv_length_errors;
1837 bp->stats.gen.tx_errors = bp->xmt_length_errors;
1838 bp->stats.gen.rx_dropped = bp->rcv_discards;
1839 bp->stats.gen.tx_dropped = bp->xmt_discards;
1840 bp->stats.gen.multicast = bp->rcv_multicast_frames;
1841 bp->stats.gen.collisions = 0; /* always zero (0) for FDDI */
1843 /* Get FDDI SMT MIB objects */
1845 bp->cmd_req_virt->cmd_type = PI_CMD_K_SMT_MIB_GET;
1846 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1847 return((struct net_device_stats *) &bp->stats);
1849 /* Fill the bp->stats structure with the SMT MIB object values */
1851 memcpy(bp->stats.smt_station_id, &bp->cmd_rsp_virt->smt_mib_get.smt_station_id, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_station_id));
1852 bp->stats.smt_op_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_op_version_id;
1853 bp->stats.smt_hi_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_hi_version_id;
1854 bp->stats.smt_lo_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_lo_version_id;
1855 memcpy(bp->stats.smt_user_data, &bp->cmd_rsp_virt->smt_mib_get.smt_user_data, sizeof(bp->cmd_rsp_virt->smt_mib_get.smt_user_data));
1856 bp->stats.smt_mib_version_id = bp->cmd_rsp_virt->smt_mib_get.smt_mib_version_id;
1857 bp->stats.smt_mac_cts = bp->cmd_rsp_virt->smt_mib_get.smt_mac_ct;
1858 bp->stats.smt_non_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_non_master_ct;
1859 bp->stats.smt_master_cts = bp->cmd_rsp_virt->smt_mib_get.smt_master_ct;
1860 bp->stats.smt_available_paths = bp->cmd_rsp_virt->smt_mib_get.smt_available_paths;
1861 bp->stats.smt_config_capabilities = bp->cmd_rsp_virt->smt_mib_get.smt_config_capabilities;
1862 bp->stats.smt_config_policy = bp->cmd_rsp_virt->smt_mib_get.smt_config_policy;
1863 bp->stats.smt_connection_policy = bp->cmd_rsp_virt->smt_mib_get.smt_connection_policy;
1864 bp->stats.smt_t_notify = bp->cmd_rsp_virt->smt_mib_get.smt_t_notify;
1865 bp->stats.smt_stat_rpt_policy = bp->cmd_rsp_virt->smt_mib_get.smt_stat_rpt_policy;
1866 bp->stats.smt_trace_max_expiration = bp->cmd_rsp_virt->smt_mib_get.smt_trace_max_expiration;
1867 bp->stats.smt_bypass_present = bp->cmd_rsp_virt->smt_mib_get.smt_bypass_present;
1868 bp->stats.smt_ecm_state = bp->cmd_rsp_virt->smt_mib_get.smt_ecm_state;
1869 bp->stats.smt_cf_state = bp->cmd_rsp_virt->smt_mib_get.smt_cf_state;
1870 bp->stats.smt_remote_disconnect_flag = bp->cmd_rsp_virt->smt_mib_get.smt_remote_disconnect_flag;
1871 bp->stats.smt_station_status = bp->cmd_rsp_virt->smt_mib_get.smt_station_status;
1872 bp->stats.smt_peer_wrap_flag = bp->cmd_rsp_virt->smt_mib_get.smt_peer_wrap_flag;
1873 bp->stats.smt_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_msg_time_stamp.ls;
1874 bp->stats.smt_transition_time_stamp = bp->cmd_rsp_virt->smt_mib_get.smt_transition_time_stamp.ls;
1875 bp->stats.mac_frame_status_functions = bp->cmd_rsp_virt->smt_mib_get.mac_frame_status_functions;
1876 bp->stats.mac_t_max_capability = bp->cmd_rsp_virt->smt_mib_get.mac_t_max_capability;
1877 bp->stats.mac_tvx_capability = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_capability;
1878 bp->stats.mac_available_paths = bp->cmd_rsp_virt->smt_mib_get.mac_available_paths;
1879 bp->stats.mac_current_path = bp->cmd_rsp_virt->smt_mib_get.mac_current_path;
1880 memcpy(bp->stats.mac_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_upstream_nbr, FDDI_K_ALEN);
1881 memcpy(bp->stats.mac_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_downstream_nbr, FDDI_K_ALEN);
1882 memcpy(bp->stats.mac_old_upstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_upstream_nbr, FDDI_K_ALEN);
1883 memcpy(bp->stats.mac_old_downstream_nbr, &bp->cmd_rsp_virt->smt_mib_get.mac_old_downstream_nbr, FDDI_K_ALEN);
1884 bp->stats.mac_dup_address_test = bp->cmd_rsp_virt->smt_mib_get.mac_dup_address_test;
1885 bp->stats.mac_requested_paths = bp->cmd_rsp_virt->smt_mib_get.mac_requested_paths;
1886 bp->stats.mac_downstream_port_type = bp->cmd_rsp_virt->smt_mib_get.mac_downstream_port_type;
1887 memcpy(bp->stats.mac_smt_address, &bp->cmd_rsp_virt->smt_mib_get.mac_smt_address, FDDI_K_ALEN);
1888 bp->stats.mac_t_req = bp->cmd_rsp_virt->smt_mib_get.mac_t_req;
1889 bp->stats.mac_t_neg = bp->cmd_rsp_virt->smt_mib_get.mac_t_neg;
1890 bp->stats.mac_t_max = bp->cmd_rsp_virt->smt_mib_get.mac_t_max;
1891 bp->stats.mac_tvx_value = bp->cmd_rsp_virt->smt_mib_get.mac_tvx_value;
1892 bp->stats.mac_frame_error_threshold = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_threshold;
1893 bp->stats.mac_frame_error_ratio = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_ratio;
1894 bp->stats.mac_rmt_state = bp->cmd_rsp_virt->smt_mib_get.mac_rmt_state;
1895 bp->stats.mac_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_da_flag;
1896 bp->stats.mac_una_da_flag = bp->cmd_rsp_virt->smt_mib_get.mac_unda_flag;
1897 bp->stats.mac_frame_error_flag = bp->cmd_rsp_virt->smt_mib_get.mac_frame_error_flag;
1898 bp->stats.mac_ma_unitdata_available = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_available;
1899 bp->stats.mac_hardware_present = bp->cmd_rsp_virt->smt_mib_get.mac_hardware_present;
1900 bp->stats.mac_ma_unitdata_enable = bp->cmd_rsp_virt->smt_mib_get.mac_ma_unitdata_enable;
1901 bp->stats.path_tvx_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_tvx_lower_bound;
1902 bp->stats.path_t_max_lower_bound = bp->cmd_rsp_virt->smt_mib_get.path_t_max_lower_bound;
1903 bp->stats.path_max_t_req = bp->cmd_rsp_virt->smt_mib_get.path_max_t_req;
1904 memcpy(bp->stats.path_configuration, &bp->cmd_rsp_virt->smt_mib_get.path_configuration, sizeof(bp->cmd_rsp_virt->smt_mib_get.path_configuration));
1905 bp->stats.port_my_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[0];
1906 bp->stats.port_my_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_my_type[1];
1907 bp->stats.port_neighbor_type[0] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[0];
1908 bp->stats.port_neighbor_type[1] = bp->cmd_rsp_virt->smt_mib_get.port_neighbor_type[1];
1909 bp->stats.port_connection_policies[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[0];
1910 bp->stats.port_connection_policies[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_policies[1];
1911 bp->stats.port_mac_indicated[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[0];
1912 bp->stats.port_mac_indicated[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_indicated[1];
1913 bp->stats.port_current_path[0] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[0];
1914 bp->stats.port_current_path[1] = bp->cmd_rsp_virt->smt_mib_get.port_current_path[1];
1915 memcpy(&bp->stats.port_requested_paths[0*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[0], 3);
1916 memcpy(&bp->stats.port_requested_paths[1*3], &bp->cmd_rsp_virt->smt_mib_get.port_requested_paths[1], 3);
1917 bp->stats.port_mac_placement[0] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[0];
1918 bp->stats.port_mac_placement[1] = bp->cmd_rsp_virt->smt_mib_get.port_mac_placement[1];
1919 bp->stats.port_available_paths[0] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[0];
1920 bp->stats.port_available_paths[1] = bp->cmd_rsp_virt->smt_mib_get.port_available_paths[1];
1921 bp->stats.port_pmd_class[0] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[0];
1922 bp->stats.port_pmd_class[1] = bp->cmd_rsp_virt->smt_mib_get.port_pmd_class[1];
1923 bp->stats.port_connection_capabilities[0] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[0];
1924 bp->stats.port_connection_capabilities[1] = bp->cmd_rsp_virt->smt_mib_get.port_connection_capabilities[1];
1925 bp->stats.port_bs_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[0];
1926 bp->stats.port_bs_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_bs_flag[1];
1927 bp->stats.port_ler_estimate[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[0];
1928 bp->stats.port_ler_estimate[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_estimate[1];
1929 bp->stats.port_ler_cutoff[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[0];
1930 bp->stats.port_ler_cutoff[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_cutoff[1];
1931 bp->stats.port_ler_alarm[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[0];
1932 bp->stats.port_ler_alarm[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_alarm[1];
1933 bp->stats.port_connect_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[0];
1934 bp->stats.port_connect_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_connect_state[1];
1935 bp->stats.port_pcm_state[0] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[0];
1936 bp->stats.port_pcm_state[1] = bp->cmd_rsp_virt->smt_mib_get.port_pcm_state[1];
1937 bp->stats.port_pc_withhold[0] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[0];
1938 bp->stats.port_pc_withhold[1] = bp->cmd_rsp_virt->smt_mib_get.port_pc_withhold[1];
1939 bp->stats.port_ler_flag[0] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[0];
1940 bp->stats.port_ler_flag[1] = bp->cmd_rsp_virt->smt_mib_get.port_ler_flag[1];
1941 bp->stats.port_hardware_present[0] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[0];
1942 bp->stats.port_hardware_present[1] = bp->cmd_rsp_virt->smt_mib_get.port_hardware_present[1];
1944 /* Get FDDI counters */
1946 bp->cmd_req_virt->cmd_type = PI_CMD_K_CNTRS_GET;
1947 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
1948 return((struct net_device_stats *) &bp->stats);
1950 /* Fill the bp->stats structure with the FDDI counter values */
1952 bp->stats.mac_frame_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.frame_cnt.ls;
1953 bp->stats.mac_copied_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.copied_cnt.ls;
1954 bp->stats.mac_transmit_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.transmit_cnt.ls;
1955 bp->stats.mac_error_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.error_cnt.ls;
1956 bp->stats.mac_lost_cts = bp->cmd_rsp_virt->cntrs_get.cntrs.lost_cnt.ls;
1957 bp->stats.port_lct_fail_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[0].ls;
1958 bp->stats.port_lct_fail_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lct_rejects[1].ls;
1959 bp->stats.port_lem_reject_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[0].ls;
1960 bp->stats.port_lem_reject_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.lem_rejects[1].ls;
1961 bp->stats.port_lem_cts[0] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[0].ls;
1962 bp->stats.port_lem_cts[1] = bp->cmd_rsp_virt->cntrs_get.cntrs.link_errors[1].ls;
1964 return((struct net_device_stats *) &bp->stats);
1969 * ==============================
1970 * = dfx_ctl_set_multicast_list =
1971 * ==============================
1974 * Enable/Disable LLC frame promiscuous mode reception
1975 * on the adapter and/or update multicast address table.
1981 * dev - pointer to device information
1983 * Functional Description:
1984 * This routine follows a fairly simple algorithm for setting the
1985 * adapter filters and CAM:
1987 * if IFF_PROMISC flag is set
1988 * enable LLC individual/group promiscuous mode
1990 * disable LLC individual/group promiscuous mode
1991 * if number of incoming multicast addresses >
1992 * (CAM max size - number of unicast addresses in CAM)
1993 * enable LLC group promiscuous mode
1994 * set driver-maintained multicast address count to zero
1996 * disable LLC group promiscuous mode
1997 * set driver-maintained multicast address count to incoming count
1998 * update adapter CAM
1999 * update adapter filters
2005 * Multicast addresses are presented in canonical (LSB) format.
2008 * On-board adapter CAM and filters are updated.
2011 static void dfx_ctl_set_multicast_list(struct net_device *dev)
2013 DFX_board_t *bp = dev->priv;
2014 int i; /* used as index in for loop */
2015 struct dev_mc_list *dmi; /* ptr to multicast addr entry */
2017 /* Enable LLC frame promiscuous mode, if necessary */
2019 if (dev->flags & IFF_PROMISC)
2020 bp->ind_group_prom = PI_FSTATE_K_PASS; /* Enable LLC ind/group prom mode */
2022 /* Else, update multicast address table */
2026 bp->ind_group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC ind/group prom mode */
2028 * Check whether incoming multicast address count exceeds table size
2030 * Note: The adapters utilize an on-board 64 entry CAM for
2031 * supporting perfect filtering of multicast packets
2032 * and bridge functions when adding unicast addresses.
2033 * There is no hash function available. To support
2034 * additional multicast addresses, the all multicast
2035 * filter (LLC group promiscuous mode) must be enabled.
2037 * The firmware reserves two CAM entries for SMT-related
2038 * multicast addresses, which leaves 62 entries available.
2039 * The following code ensures that we're not being asked
2040 * to add more than 62 addresses to the CAM. If we are,
2041 * the driver will enable the all multicast filter.
2042 * Should the number of multicast addresses drop below
2043 * the high water mark, the filter will be disabled and
2044 * perfect filtering will be used.
2047 if (dev->mc_count > (PI_CMD_ADDR_FILTER_K_SIZE - bp->uc_count))
2049 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2050 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2054 bp->group_prom = PI_FSTATE_K_BLOCK; /* Disable LLC group prom mode */
2055 bp->mc_count = dev->mc_count; /* Add mc addrs to CAM */
2058 /* Copy addresses to multicast address table, then update adapter CAM */
2060 dmi = dev->mc_list; /* point to first multicast addr */
2061 for (i=0; i < bp->mc_count; i++)
2063 memcpy(&bp->mc_table[i*FDDI_K_ALEN], dmi->dmi_addr, FDDI_K_ALEN);
2064 dmi = dmi->next; /* point to next multicast addr */
2066 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2068 DBG_printk("%s: Could not update multicast address table!\n", dev->name);
2072 DBG_printk("%s: Multicast address table updated! Added %d addresses.\n", dev->name, bp->mc_count);
2076 /* Update adapter filters */
2078 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2080 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2084 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2090 * ===========================
2091 * = dfx_ctl_set_mac_address =
2092 * ===========================
2095 * Add node address override (unicast address) to adapter
2096 * CAM and update dev_addr field in device table.
2102 * dev - pointer to device information
2103 * addr - pointer to sockaddr structure containing unicast address to add
2105 * Functional Description:
2106 * The adapter supports node address overrides by adding one or more
2107 * unicast addresses to the adapter CAM. This is similar to adding
2108 * multicast addresses. In this routine we'll update the driver and
2109 * device structures with the new address, then update the adapter CAM
2110 * to ensure that the adapter will copy and strip frames destined and
2111 * sourced by that address.
2114 * Always returns zero.
2117 * The address pointed to by addr->sa_data is a valid unicast
2118 * address and is presented in canonical (LSB) format.
2121 * On-board adapter CAM is updated. On-board adapter filters
2125 static int dfx_ctl_set_mac_address(struct net_device *dev, void *addr)
2127 DFX_board_t *bp = dev->priv;
2128 struct sockaddr *p_sockaddr = (struct sockaddr *)addr;
2130 /* Copy unicast address to driver-maintained structs and update count */
2132 memcpy(dev->dev_addr, p_sockaddr->sa_data, FDDI_K_ALEN); /* update device struct */
2133 memcpy(&bp->uc_table[0], p_sockaddr->sa_data, FDDI_K_ALEN); /* update driver struct */
2137 * Verify we're not exceeding the CAM size by adding unicast address
2139 * Note: It's possible that before entering this routine we've
2140 * already filled the CAM with 62 multicast addresses.
2141 * Since we need to place the node address override into
2142 * the CAM, we have to check to see that we're not
2143 * exceeding the CAM size. If we are, we have to enable
2144 * the LLC group (multicast) promiscuous mode filter as
2145 * in dfx_ctl_set_multicast_list.
2148 if ((bp->uc_count + bp->mc_count) > PI_CMD_ADDR_FILTER_K_SIZE)
2150 bp->group_prom = PI_FSTATE_K_PASS; /* Enable LLC group prom mode */
2151 bp->mc_count = 0; /* Don't add mc addrs to CAM */
2153 /* Update adapter filters */
2155 if (dfx_ctl_update_filters(bp) != DFX_K_SUCCESS)
2157 DBG_printk("%s: Could not update adapter filters!\n", dev->name);
2161 DBG_printk("%s: Adapter filters updated!\n", dev->name);
2165 /* Update adapter CAM with new unicast address */
2167 if (dfx_ctl_update_cam(bp) != DFX_K_SUCCESS)
2169 DBG_printk("%s: Could not set new MAC address!\n", dev->name);
2173 DBG_printk("%s: Adapter CAM updated with new MAC address\n", dev->name);
2175 return(0); /* always return zero */
2180 * ======================
2181 * = dfx_ctl_update_cam =
2182 * ======================
2185 * Procedure to update adapter CAM (Content Addressable Memory)
2186 * with desired unicast and multicast address entries.
2192 * bp - pointer to board information
2194 * Functional Description:
2195 * Updates adapter CAM with current contents of board structure
2196 * unicast and multicast address tables. Since there are only 62
2197 * free entries in CAM, this routine ensures that the command
2198 * request buffer is not overrun.
2201 * DFX_K_SUCCESS - Request succeeded
2202 * DFX_K_FAILURE - Request failed
2205 * All addresses being added (unicast and multicast) are in canonical
2209 * On-board adapter CAM is updated.
2212 static int dfx_ctl_update_cam(DFX_board_t *bp)
2214 int i; /* used as index */
2215 PI_LAN_ADDR *p_addr; /* pointer to CAM entry */
2218 * Fill in command request information
2220 * Note: Even though both the unicast and multicast address
2221 * table entries are stored as contiguous 6 byte entries,
2222 * the firmware address filter set command expects each
2223 * entry to be two longwords (8 bytes total). We must be
2224 * careful to only copy the six bytes of each unicast and
2225 * multicast table entry into each command entry. This
2226 * is also why we must first clear the entire command
2230 memset(bp->cmd_req_virt, 0, PI_CMD_REQ_K_SIZE_MAX); /* first clear buffer */
2231 bp->cmd_req_virt->cmd_type = PI_CMD_K_ADDR_FILTER_SET;
2232 p_addr = &bp->cmd_req_virt->addr_filter_set.entry[0];
2234 /* Now add unicast addresses to command request buffer, if any */
2236 for (i=0; i < (int)bp->uc_count; i++)
2238 if (i < PI_CMD_ADDR_FILTER_K_SIZE)
2240 memcpy(p_addr, &bp->uc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2241 p_addr++; /* point to next command entry */
2245 /* Now add multicast addresses to command request buffer, if any */
2247 for (i=0; i < (int)bp->mc_count; i++)
2249 if ((i + bp->uc_count) < PI_CMD_ADDR_FILTER_K_SIZE)
2251 memcpy(p_addr, &bp->mc_table[i*FDDI_K_ALEN], FDDI_K_ALEN);
2252 p_addr++; /* point to next command entry */
2256 /* Issue command to update adapter CAM, then return */
2258 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2259 return(DFX_K_FAILURE);
2260 return(DFX_K_SUCCESS);
2265 * ==========================
2266 * = dfx_ctl_update_filters =
2267 * ==========================
2270 * Procedure to update adapter filters with desired
2277 * bp - pointer to board information
2279 * Functional Description:
2280 * Enables or disables filter using current filter settings.
2283 * DFX_K_SUCCESS - Request succeeded.
2284 * DFX_K_FAILURE - Request failed.
2287 * We must always pass up packets destined to the broadcast
2288 * address (FF-FF-FF-FF-FF-FF), so we'll always keep the
2289 * broadcast filter enabled.
2292 * On-board adapter filters are updated.
2295 static int dfx_ctl_update_filters(DFX_board_t *bp)
2297 int i = 0; /* used as index */
2299 /* Fill in command request information */
2301 bp->cmd_req_virt->cmd_type = PI_CMD_K_FILTERS_SET;
2303 /* Initialize Broadcast filter - * ALWAYS ENABLED * */
2305 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_BROADCAST;
2306 bp->cmd_req_virt->filter_set.item[i++].value = PI_FSTATE_K_PASS;
2308 /* Initialize LLC Individual/Group Promiscuous filter */
2310 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_IND_GROUP_PROM;
2311 bp->cmd_req_virt->filter_set.item[i++].value = bp->ind_group_prom;
2313 /* Initialize LLC Group Promiscuous filter */
2315 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_GROUP_PROM;
2316 bp->cmd_req_virt->filter_set.item[i++].value = bp->group_prom;
2318 /* Terminate the item code list */
2320 bp->cmd_req_virt->filter_set.item[i].item_code = PI_ITEM_K_EOL;
2322 /* Issue command to update adapter filters, then return */
2324 if (dfx_hw_dma_cmd_req(bp) != DFX_K_SUCCESS)
2325 return(DFX_K_FAILURE);
2326 return(DFX_K_SUCCESS);
2331 * ======================
2332 * = dfx_hw_dma_cmd_req =
2333 * ======================
2336 * Sends PDQ DMA command to adapter firmware
2342 * bp - pointer to board information
2344 * Functional Description:
2345 * The command request and response buffers are posted to the adapter in the manner
2346 * described in the PDQ Port Specification:
2348 * 1. Command Response Buffer is posted to adapter.
2349 * 2. Command Request Buffer is posted to adapter.
2350 * 3. Command Request consumer index is polled until it indicates that request
2351 * buffer has been DMA'd to adapter.
2352 * 4. Command Response consumer index is polled until it indicates that response
2353 * buffer has been DMA'd from adapter.
2355 * This ordering ensures that a response buffer is already available for the firmware
2356 * to use once it's done processing the request buffer.
2359 * DFX_K_SUCCESS - DMA command succeeded
2360 * DFX_K_OUTSTATE - Adapter is NOT in proper state
2361 * DFX_K_HW_TIMEOUT - DMA command timed out
2364 * Command request buffer has already been filled with desired DMA command.
2370 static int dfx_hw_dma_cmd_req(DFX_board_t *bp)
2372 int status; /* adapter status */
2373 int timeout_cnt; /* used in for loops */
2375 /* Make sure the adapter is in a state that we can issue the DMA command in */
2377 status = dfx_hw_adap_state_rd(bp);
2378 if ((status == PI_STATE_K_RESET) ||
2379 (status == PI_STATE_K_HALTED) ||
2380 (status == PI_STATE_K_DMA_UNAVAIL) ||
2381 (status == PI_STATE_K_UPGRADE))
2382 return(DFX_K_OUTSTATE);
2384 /* Put response buffer on the command response queue */
2386 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2387 ((PI_CMD_RSP_K_SIZE_MAX / PI_ALIGN_K_CMD_RSP_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2388 bp->descr_block_virt->cmd_rsp[bp->cmd_rsp_reg.index.prod].long_1 = bp->cmd_rsp_phys;
2390 /* Bump (and wrap) the producer index and write out to register */
2392 bp->cmd_rsp_reg.index.prod += 1;
2393 bp->cmd_rsp_reg.index.prod &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2394 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2396 /* Put request buffer on the command request queue */
2398 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_0 = (u32) (PI_XMT_DESCR_M_SOP |
2399 PI_XMT_DESCR_M_EOP | (PI_CMD_REQ_K_SIZE_MAX << PI_XMT_DESCR_V_SEG_LEN));
2400 bp->descr_block_virt->cmd_req[bp->cmd_req_reg.index.prod].long_1 = bp->cmd_req_phys;
2402 /* Bump (and wrap) the producer index and write out to register */
2404 bp->cmd_req_reg.index.prod += 1;
2405 bp->cmd_req_reg.index.prod &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2406 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2409 * Here we wait for the command request consumer index to be equal
2410 * to the producer, indicating that the adapter has DMAed the request.
2413 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2415 if (bp->cmd_req_reg.index.prod == (u8)(bp->cons_block_virt->cmd_req))
2417 udelay(100); /* wait for 100 microseconds */
2419 if (timeout_cnt == 0)
2420 return(DFX_K_HW_TIMEOUT);
2422 /* Bump (and wrap) the completion index and write out to register */
2424 bp->cmd_req_reg.index.comp += 1;
2425 bp->cmd_req_reg.index.comp &= PI_CMD_REQ_K_NUM_ENTRIES-1;
2426 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_REQ_PROD, bp->cmd_req_reg.lword);
2429 * Here we wait for the command response consumer index to be equal
2430 * to the producer, indicating that the adapter has DMAed the response.
2433 for (timeout_cnt = 20000; timeout_cnt > 0; timeout_cnt--)
2435 if (bp->cmd_rsp_reg.index.prod == (u8)(bp->cons_block_virt->cmd_rsp))
2437 udelay(100); /* wait for 100 microseconds */
2439 if (timeout_cnt == 0)
2440 return(DFX_K_HW_TIMEOUT);
2442 /* Bump (and wrap) the completion index and write out to register */
2444 bp->cmd_rsp_reg.index.comp += 1;
2445 bp->cmd_rsp_reg.index.comp &= PI_CMD_RSP_K_NUM_ENTRIES-1;
2446 dfx_port_write_long(bp, PI_PDQ_K_REG_CMD_RSP_PROD, bp->cmd_rsp_reg.lword);
2447 return(DFX_K_SUCCESS);
2452 * ========================
2453 * = dfx_hw_port_ctrl_req =
2454 * ========================
2457 * Sends PDQ port control command to adapter firmware
2460 * Host data register value in host_data if ptr is not NULL
2463 * bp - pointer to board information
2464 * command - port control command
2465 * data_a - port data A register value
2466 * data_b - port data B register value
2467 * host_data - ptr to host data register value
2469 * Functional Description:
2470 * Send generic port control command to adapter by writing
2471 * to various PDQ port registers, then polling for completion.
2474 * DFX_K_SUCCESS - port control command succeeded
2475 * DFX_K_HW_TIMEOUT - port control command timed out
2484 static int dfx_hw_port_ctrl_req(
2489 PI_UINT32 *host_data
2493 PI_UINT32 port_cmd; /* Port Control command register value */
2494 int timeout_cnt; /* used in for loops */
2496 /* Set Command Error bit in command longword */
2498 port_cmd = (PI_UINT32) (command | PI_PCTRL_M_CMD_ERROR);
2500 /* Issue port command to the adapter */
2502 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, data_a);
2503 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_B, data_b);
2504 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_CTRL, port_cmd);
2506 /* Now wait for command to complete */
2508 if (command == PI_PCTRL_M_BLAST_FLASH)
2509 timeout_cnt = 600000; /* set command timeout count to 60 seconds */
2511 timeout_cnt = 20000; /* set command timeout count to 2 seconds */
2513 for (; timeout_cnt > 0; timeout_cnt--)
2515 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_CTRL, &port_cmd);
2516 if (!(port_cmd & PI_PCTRL_M_CMD_ERROR))
2518 udelay(100); /* wait for 100 microseconds */
2520 if (timeout_cnt == 0)
2521 return(DFX_K_HW_TIMEOUT);
2524 * If the address of host_data is non-zero, assume caller has supplied a
2525 * non NULL pointer, and return the contents of the HOST_DATA register in
2529 if (host_data != NULL)
2530 dfx_port_read_long(bp, PI_PDQ_K_REG_HOST_DATA, host_data);
2531 return(DFX_K_SUCCESS);
2536 * =====================
2537 * = dfx_hw_adap_reset =
2538 * =====================
2547 * bp - pointer to board information
2548 * type - type of reset to perform
2550 * Functional Description:
2551 * Issue soft reset to adapter by writing to PDQ Port Reset
2552 * register. Use incoming reset type to tell adapter what
2553 * kind of reset operation to perform.
2559 * This routine merely issues a soft reset to the adapter.
2560 * It is expected that after this routine returns, the caller
2561 * will appropriately poll the Port Status register for the
2562 * adapter to enter the proper state.
2565 * Internal adapter registers are cleared.
2568 static void dfx_hw_adap_reset(
2574 /* Set Reset type and assert reset */
2576 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_DATA_A, type); /* tell adapter type of reset */
2577 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, PI_RESET_M_ASSERT_RESET);
2579 /* Wait for at least 1 Microsecond according to the spec. We wait 20 just to be safe */
2583 /* Deassert reset */
2585 dfx_port_write_long(bp, PI_PDQ_K_REG_PORT_RESET, 0);
2590 * ========================
2591 * = dfx_hw_adap_state_rd =
2592 * ========================
2595 * Returns current adapter state
2598 * Adapter state per PDQ Port Specification
2601 * bp - pointer to board information
2603 * Functional Description:
2604 * Reads PDQ Port Status register and returns adapter state.
2616 static int dfx_hw_adap_state_rd(DFX_board_t *bp)
2618 PI_UINT32 port_status; /* Port Status register value */
2620 dfx_port_read_long(bp, PI_PDQ_K_REG_PORT_STATUS, &port_status);
2621 return((port_status & PI_PSTATUS_M_STATE) >> PI_PSTATUS_V_STATE);
2626 * =====================
2627 * = dfx_hw_dma_uninit =
2628 * =====================
2631 * Brings adapter to DMA_UNAVAILABLE state
2637 * bp - pointer to board information
2638 * type - type of reset to perform
2640 * Functional Description:
2641 * Bring adapter to DMA_UNAVAILABLE state by performing the following:
2642 * 1. Set reset type bit in Port Data A Register then reset adapter.
2643 * 2. Check that adapter is in DMA_UNAVAILABLE state.
2646 * DFX_K_SUCCESS - adapter is in DMA_UNAVAILABLE state
2647 * DFX_K_HW_TIMEOUT - adapter did not reset properly
2653 * Internal adapter registers are cleared.
2656 static int dfx_hw_dma_uninit(DFX_board_t *bp, PI_UINT32 type)
2658 int timeout_cnt; /* used in for loops */
2660 /* Set reset type bit and reset adapter */
2662 dfx_hw_adap_reset(bp, type);
2664 /* Now wait for adapter to enter DMA_UNAVAILABLE state */
2666 for (timeout_cnt = 100000; timeout_cnt > 0; timeout_cnt--)
2668 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_DMA_UNAVAIL)
2670 udelay(100); /* wait for 100 microseconds */
2672 if (timeout_cnt == 0)
2673 return(DFX_K_HW_TIMEOUT);
2674 return(DFX_K_SUCCESS);
2678 * Align an sk_buff to a boundary power of 2
2682 static void my_skb_align(struct sk_buff *skb, int n)
2684 unsigned long x = (unsigned long)skb->data;
2687 v = ALIGN(x, n); /* Where we want to be */
2689 skb_reserve(skb, v - x);
2699 * Produces buffers to adapter LLC Host receive descriptor block
2705 * bp - pointer to board information
2706 * get_buffers - non-zero if buffers to be allocated
2708 * Functional Description:
2709 * This routine can be called during dfx_adap_init() or during an adapter
2710 * reset. It initializes the descriptor block and produces all allocated
2711 * LLC Host queue receive buffers.
2714 * Return 0 on success or -ENOMEM if buffer allocation failed (when using
2715 * dynamic buffer allocation). If the buffer allocation failed, the
2716 * already allocated buffers will not be released and the caller should do
2720 * The PDQ has been reset and the adapter and driver maintained Type 2
2721 * register indices are cleared.
2724 * Receive buffers are posted to the adapter LLC queue and the adapter
2728 static int dfx_rcv_init(DFX_board_t *bp, int get_buffers)
2730 int i, j; /* used in for loop */
2733 * Since each receive buffer is a single fragment of same length, initialize
2734 * first longword in each receive descriptor for entire LLC Host descriptor
2735 * block. Also initialize second longword in each receive descriptor with
2736 * physical address of receive buffer. We'll always allocate receive
2737 * buffers in powers of 2 so that we can easily fill the 256 entry descriptor
2738 * block and produce new receive buffers by simply updating the receive
2742 * To support all shipping versions of PDQ, the receive buffer size
2743 * must be mod 128 in length and the physical address must be 128 byte
2744 * aligned. In other words, bits 0-6 of the length and address must
2745 * be zero for the following descriptor field entries to be correct on
2746 * all PDQ-based boards. We guaranteed both requirements during
2747 * driver initialization when we allocated memory for the receive buffers.
2751 #ifdef DYNAMIC_BUFFERS
2752 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
2753 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2755 struct sk_buff *newskb = __dev_alloc_skb(NEW_SKB_SIZE, GFP_NOIO);
2758 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2759 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2761 * align to 128 bytes for compatibility with
2762 * the old EISA boards.
2765 my_skb_align(newskb, 128);
2766 bp->descr_block_virt->rcv_data[i + j].long_1 =
2767 (u32)pci_map_single(bp->pci_dev, newskb->data,
2769 PCI_DMA_FROMDEVICE);
2771 * p_rcv_buff_va is only used inside the
2772 * kernel so we put the skb pointer here.
2774 bp->p_rcv_buff_va[i+j] = (char *) newskb;
2777 for (i=0; i < (int)(bp->rcv_bufs_to_post); i++)
2778 for (j=0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
2780 bp->descr_block_virt->rcv_data[i+j].long_0 = (u32) (PI_RCV_DESCR_M_SOP |
2781 ((PI_RCV_DATA_K_SIZE_MAX / PI_ALIGN_K_RCV_DATA_BUFF) << PI_RCV_DESCR_V_SEG_LEN));
2782 bp->descr_block_virt->rcv_data[i+j].long_1 = (u32) (bp->rcv_block_phys + (i * PI_RCV_DATA_K_SIZE_MAX));
2783 bp->p_rcv_buff_va[i+j] = (char *) (bp->rcv_block_virt + (i * PI_RCV_DATA_K_SIZE_MAX));
2788 /* Update receive producer and Type 2 register */
2790 bp->rcv_xmt_reg.index.rcv_prod = bp->rcv_bufs_to_post;
2791 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
2797 * =========================
2798 * = dfx_rcv_queue_process =
2799 * =========================
2802 * Process received LLC frames.
2808 * bp - pointer to board information
2810 * Functional Description:
2811 * Received LLC frames are processed until there are no more consumed frames.
2812 * Once all frames are processed, the receive buffers are returned to the
2813 * adapter. Note that this algorithm fixes the length of time that can be spent
2814 * in this routine, because there are a fixed number of receive buffers to
2815 * process and buffers are not produced until this routine exits and returns
2828 static void dfx_rcv_queue_process(
2833 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
2834 char *p_buff; /* ptr to start of packet receive buffer (FMC descriptor) */
2835 u32 descr, pkt_len; /* FMC descriptor field and packet length */
2836 struct sk_buff *skb; /* pointer to a sk_buff to hold incoming packet data */
2838 /* Service all consumed LLC receive frames */
2840 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
2841 while (bp->rcv_xmt_reg.index.rcv_comp != p_type_2_cons->index.rcv_cons)
2843 /* Process any errors */
2847 entry = bp->rcv_xmt_reg.index.rcv_comp;
2848 #ifdef DYNAMIC_BUFFERS
2849 p_buff = (char *) (((struct sk_buff *)bp->p_rcv_buff_va[entry])->data);
2851 p_buff = (char *) bp->p_rcv_buff_va[entry];
2853 memcpy(&descr, p_buff + RCV_BUFF_K_DESCR, sizeof(u32));
2855 if (descr & PI_FMC_DESCR_M_RCC_FLUSH)
2857 if (descr & PI_FMC_DESCR_M_RCC_CRC)
2858 bp->rcv_crc_errors++;
2860 bp->rcv_frame_status_errors++;
2864 int rx_in_place = 0;
2866 /* The frame was received without errors - verify packet length */
2868 pkt_len = (u32)((descr & PI_FMC_DESCR_M_LEN) >> PI_FMC_DESCR_V_LEN);
2869 pkt_len -= 4; /* subtract 4 byte CRC */
2870 if (!IN_RANGE(pkt_len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
2871 bp->rcv_length_errors++;
2873 #ifdef DYNAMIC_BUFFERS
2874 if (pkt_len > SKBUFF_RX_COPYBREAK) {
2875 struct sk_buff *newskb;
2877 newskb = dev_alloc_skb(NEW_SKB_SIZE);
2881 my_skb_align(newskb, 128);
2882 skb = (struct sk_buff *)bp->p_rcv_buff_va[entry];
2883 pci_unmap_single(bp->pci_dev,
2884 bp->descr_block_virt->rcv_data[entry].long_1,
2886 PCI_DMA_FROMDEVICE);
2887 skb_reserve(skb, RCV_BUFF_K_PADDING);
2888 bp->p_rcv_buff_va[entry] = (char *)newskb;
2889 bp->descr_block_virt->rcv_data[entry].long_1 =
2890 (u32)pci_map_single(bp->pci_dev,
2893 PCI_DMA_FROMDEVICE);
2898 skb = dev_alloc_skb(pkt_len+3); /* alloc new buffer to pass up, add room for PRH */
2901 printk("%s: Could not allocate receive buffer. Dropping packet.\n", bp->dev->name);
2906 #ifndef DYNAMIC_BUFFERS
2910 /* Receive buffer allocated, pass receive packet up */
2912 memcpy(skb->data, p_buff + RCV_BUFF_K_PADDING, pkt_len+3);
2915 skb_reserve(skb,3); /* adjust data field so that it points to FC byte */
2916 skb_put(skb, pkt_len); /* pass up packet length, NOT including CRC */
2917 skb->dev = bp->dev; /* pass up device pointer */
2919 skb->protocol = fddi_type_trans(skb, bp->dev);
2920 bp->rcv_total_bytes += skb->len;
2923 /* Update the rcv counters */
2924 bp->dev->last_rx = jiffies;
2925 bp->rcv_total_frames++;
2926 if (*(p_buff + RCV_BUFF_K_DA) & 0x01)
2927 bp->rcv_multicast_frames++;
2933 * Advance the producer (for recycling) and advance the completion
2934 * (for servicing received frames). Note that it is okay to
2935 * advance the producer without checking that it passes the
2936 * completion index because they are both advanced at the same
2940 bp->rcv_xmt_reg.index.rcv_prod += 1;
2941 bp->rcv_xmt_reg.index.rcv_comp += 1;
2947 * =====================
2948 * = dfx_xmt_queue_pkt =
2949 * =====================
2952 * Queues packets for transmission
2958 * skb - pointer to sk_buff to queue for transmission
2959 * dev - pointer to device information
2961 * Functional Description:
2962 * Here we assume that an incoming skb transmit request
2963 * is contained in a single physically contiguous buffer
2964 * in which the virtual address of the start of packet
2965 * (skb->data) can be converted to a physical address
2966 * by using pci_map_single().
2968 * Since the adapter architecture requires a three byte
2969 * packet request header to prepend the start of packet,
2970 * we'll write the three byte field immediately prior to
2971 * the FC byte. This assumption is valid because we've
2972 * ensured that dev->hard_header_len includes three pad
2973 * bytes. By posting a single fragment to the adapter,
2974 * we'll reduce the number of descriptor fetches and
2975 * bus traffic needed to send the request.
2977 * Also, we can't free the skb until after it's been DMA'd
2978 * out by the adapter, so we'll queue it in the driver and
2979 * return it in dfx_xmt_done.
2982 * 0 - driver queued packet, link is unavailable, or skbuff was bad
2983 * 1 - caller should requeue the sk_buff for later transmission
2986 * First and foremost, we assume the incoming skb pointer
2987 * is NOT NULL and is pointing to a valid sk_buff structure.
2989 * The outgoing packet is complete, starting with the
2990 * frame control byte including the last byte of data,
2991 * but NOT including the 4 byte CRC. We'll let the
2992 * adapter hardware generate and append the CRC.
2994 * The entire packet is stored in one physically
2995 * contiguous buffer which is not cached and whose
2996 * 32-bit physical address can be determined.
2998 * It's vital that this routine is NOT reentered for the
2999 * same board and that the OS is not in another section of
3000 * code (eg. dfx_int_common) for the same board on a
3007 static int dfx_xmt_queue_pkt(
3008 struct sk_buff *skb,
3009 struct net_device *dev
3013 DFX_board_t *bp = dev->priv;
3014 u8 prod; /* local transmit producer index */
3015 PI_XMT_DESCR *p_xmt_descr; /* ptr to transmit descriptor block entry */
3016 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3017 unsigned long flags;
3019 netif_stop_queue(dev);
3022 * Verify that incoming transmit request is OK
3024 * Note: The packet size check is consistent with other
3025 * Linux device drivers, although the correct packet
3026 * size should be verified before calling the
3030 if (!IN_RANGE(skb->len, FDDI_K_LLC_ZLEN, FDDI_K_LLC_LEN))
3032 printk("%s: Invalid packet length - %u bytes\n",
3033 dev->name, skb->len);
3034 bp->xmt_length_errors++; /* bump error counter */
3035 netif_wake_queue(dev);
3037 return(0); /* return "success" */
3040 * See if adapter link is available, if not, free buffer
3042 * Note: If the link isn't available, free buffer and return 0
3043 * rather than tell the upper layer to requeue the packet.
3044 * The methodology here is that by the time the link
3045 * becomes available, the packet to be sent will be
3046 * fairly stale. By simply dropping the packet, the
3047 * higher layer protocols will eventually time out
3048 * waiting for response packets which it won't receive.
3051 if (bp->link_available == PI_K_FALSE)
3053 if (dfx_hw_adap_state_rd(bp) == PI_STATE_K_LINK_AVAIL) /* is link really available? */
3054 bp->link_available = PI_K_TRUE; /* if so, set flag and continue */
3057 bp->xmt_discards++; /* bump error counter */
3058 dev_kfree_skb(skb); /* free sk_buff now */
3059 netif_wake_queue(dev);
3060 return(0); /* return "success" */
3064 spin_lock_irqsave(&bp->lock, flags);
3066 /* Get the current producer and the next free xmt data descriptor */
3068 prod = bp->rcv_xmt_reg.index.xmt_prod;
3069 p_xmt_descr = &(bp->descr_block_virt->xmt_data[prod]);
3072 * Get pointer to auxiliary queue entry to contain information
3075 * Note: The current xmt producer index will become the
3076 * current xmt completion index when we complete this
3077 * packet later on. So, we'll get the pointer to the
3078 * next auxiliary queue entry now before we bump the
3082 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[prod++]); /* also bump producer index */
3084 /* Write the three PRH bytes immediately before the FC byte */
3087 skb->data[0] = DFX_PRH0_BYTE; /* these byte values are defined */
3088 skb->data[1] = DFX_PRH1_BYTE; /* in the Motorola FDDI MAC chip */
3089 skb->data[2] = DFX_PRH2_BYTE; /* specification */
3092 * Write the descriptor with buffer info and bump producer
3094 * Note: Since we need to start DMA from the packet request
3095 * header, we'll add 3 bytes to the DMA buffer length,
3096 * and we'll determine the physical address of the
3097 * buffer from the PRH, not skb->data.
3100 * 1. Packet starts with the frame control (FC) byte
3102 * 2. The 4-byte CRC is not appended to the buffer or
3103 * included in the length.
3104 * 3. Packet length (skb->len) is from FC to end of
3106 * 4. The packet length does not exceed the maximum
3107 * FDDI LLC frame length of 4491 bytes.
3108 * 5. The entire packet is contained in a physically
3109 * contiguous, non-cached, locked memory space
3110 * comprised of a single buffer pointed to by
3112 * 6. The physical address of the start of packet
3113 * can be determined from the virtual address
3114 * by using pci_map_single() and is only 32-bits
3118 p_xmt_descr->long_0 = (u32) (PI_XMT_DESCR_M_SOP | PI_XMT_DESCR_M_EOP | ((skb->len) << PI_XMT_DESCR_V_SEG_LEN));
3119 p_xmt_descr->long_1 = (u32)pci_map_single(bp->pci_dev, skb->data,
3120 skb->len, PCI_DMA_TODEVICE);
3123 * Verify that descriptor is actually available
3125 * Note: If descriptor isn't available, return 1 which tells
3126 * the upper layer to requeue the packet for later
3129 * We need to ensure that the producer never reaches the
3130 * completion, except to indicate that the queue is empty.
3133 if (prod == bp->rcv_xmt_reg.index.xmt_comp)
3136 spin_unlock_irqrestore(&bp->lock, flags);
3137 return(1); /* requeue packet for later */
3141 * Save info for this packet for xmt done indication routine
3143 * Normally, we'd save the producer index in the p_xmt_drv_descr
3144 * structure so that we'd have it handy when we complete this
3145 * packet later (in dfx_xmt_done). However, since the current
3146 * transmit architecture guarantees a single fragment for the
3147 * entire packet, we can simply bump the completion index by
3148 * one (1) for each completed packet.
3150 * Note: If this assumption changes and we're presented with
3151 * an inconsistent number of transmit fragments for packet
3152 * data, we'll need to modify this code to save the current
3153 * transmit producer index.
3156 p_xmt_drv_descr->p_skb = skb;
3158 /* Update Type 2 register */
3160 bp->rcv_xmt_reg.index.xmt_prod = prod;
3161 dfx_port_write_long(bp, PI_PDQ_K_REG_TYPE_2_PROD, bp->rcv_xmt_reg.lword);
3162 spin_unlock_irqrestore(&bp->lock, flags);
3163 netif_wake_queue(dev);
3164 return(0); /* packet queued to adapter */
3174 * Processes all frames that have been transmitted.
3180 * bp - pointer to board information
3182 * Functional Description:
3183 * For all consumed transmit descriptors that have not
3184 * yet been completed, we'll free the skb we were holding
3185 * onto using dev_kfree_skb and bump the appropriate
3192 * The Type 2 register is not updated in this routine. It is
3193 * assumed that it will be updated in the ISR when dfx_xmt_done
3200 static int dfx_xmt_done(DFX_board_t *bp)
3202 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3203 PI_TYPE_2_CONSUMER *p_type_2_cons; /* ptr to rcv/xmt consumer block register */
3204 u8 comp; /* local transmit completion index */
3205 int freed = 0; /* buffers freed */
3207 /* Service all consumed transmit frames */
3209 p_type_2_cons = (PI_TYPE_2_CONSUMER *)(&bp->cons_block_virt->xmt_rcv_data);
3210 while (bp->rcv_xmt_reg.index.xmt_comp != p_type_2_cons->index.xmt_cons)
3212 /* Get pointer to the transmit driver descriptor block information */
3214 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3216 /* Increment transmit counters */
3218 bp->xmt_total_frames++;
3219 bp->xmt_total_bytes += p_xmt_drv_descr->p_skb->len;
3221 /* Return skb to operating system */
3222 comp = bp->rcv_xmt_reg.index.xmt_comp;
3223 pci_unmap_single(bp->pci_dev,
3224 bp->descr_block_virt->xmt_data[comp].long_1,
3225 p_xmt_drv_descr->p_skb->len,
3227 dev_kfree_skb_irq(p_xmt_drv_descr->p_skb);
3230 * Move to start of next packet by updating completion index
3232 * Here we assume that a transmit packet request is always
3233 * serviced by posting one fragment. We can therefore
3234 * simplify the completion code by incrementing the
3235 * completion index by one. This code will need to be
3236 * modified if this assumption changes. See comments
3237 * in dfx_xmt_queue_pkt for more details.
3240 bp->rcv_xmt_reg.index.xmt_comp += 1;
3253 * Remove all skb's in the receive ring.
3259 * bp - pointer to board information
3261 * Functional Description:
3262 * Free's all the dynamically allocated skb's that are
3263 * currently attached to the device receive ring. This
3264 * function is typically only used when the device is
3265 * initialized or reinitialized.
3273 #ifdef DYNAMIC_BUFFERS
3274 static void dfx_rcv_flush( DFX_board_t *bp )
3278 for (i = 0; i < (int)(bp->rcv_bufs_to_post); i++)
3279 for (j = 0; (i + j) < (int)PI_RCV_DATA_K_NUM_ENTRIES; j += bp->rcv_bufs_to_post)
3281 struct sk_buff *skb;
3282 skb = (struct sk_buff *)bp->p_rcv_buff_va[i+j];
3285 bp->p_rcv_buff_va[i+j] = NULL;
3290 static inline void dfx_rcv_flush( DFX_board_t *bp )
3293 #endif /* DYNAMIC_BUFFERS */
3301 * Processes all frames whether they've been transmitted
3308 * bp - pointer to board information
3310 * Functional Description:
3311 * For all produced transmit descriptors that have not
3312 * yet been completed, we'll free the skb we were holding
3313 * onto using dev_kfree_skb and bump the appropriate
3314 * counters. Of course, it's possible that some of
3315 * these transmit requests actually did go out, but we
3316 * won't make that distinction here. Finally, we'll
3317 * update the consumer index to match the producer.
3323 * This routine does NOT update the Type 2 register. It
3324 * is assumed that this routine is being called during a
3325 * transmit flush interrupt, or a shutdown or close routine.
3331 static void dfx_xmt_flush( DFX_board_t *bp )
3333 u32 prod_cons; /* rcv/xmt consumer block longword */
3334 XMT_DRIVER_DESCR *p_xmt_drv_descr; /* ptr to transmit driver descriptor */
3335 u8 comp; /* local transmit completion index */
3337 /* Flush all outstanding transmit frames */
3339 while (bp->rcv_xmt_reg.index.xmt_comp != bp->rcv_xmt_reg.index.xmt_prod)
3341 /* Get pointer to the transmit driver descriptor block information */
3343 p_xmt_drv_descr = &(bp->xmt_drv_descr_blk[bp->rcv_xmt_reg.index.xmt_comp]);
3345 /* Return skb to operating system */
3346 comp = bp->rcv_xmt_reg.index.xmt_comp;
3347 pci_unmap_single(bp->pci_dev,
3348 bp->descr_block_virt->xmt_data[comp].long_1,
3349 p_xmt_drv_descr->p_skb->len,
3351 dev_kfree_skb(p_xmt_drv_descr->p_skb);
3353 /* Increment transmit error counter */
3358 * Move to start of next packet by updating completion index
3360 * Here we assume that a transmit packet request is always
3361 * serviced by posting one fragment. We can therefore
3362 * simplify the completion code by incrementing the
3363 * completion index by one. This code will need to be
3364 * modified if this assumption changes. See comments
3365 * in dfx_xmt_queue_pkt for more details.
3368 bp->rcv_xmt_reg.index.xmt_comp += 1;
3371 /* Update the transmit consumer index in the consumer block */
3373 prod_cons = (u32)(bp->cons_block_virt->xmt_rcv_data & ~PI_CONS_M_XMT_INDEX);
3374 prod_cons |= (u32)(bp->rcv_xmt_reg.index.xmt_prod << PI_CONS_V_XMT_INDEX);
3375 bp->cons_block_virt->xmt_rcv_data = prod_cons;
3378 static void __devexit dfx_remove_one_pci_or_eisa(struct pci_dev *pdev, struct net_device *dev)
3380 DFX_board_t *bp = dev->priv;
3381 int alloc_size; /* total buffer size used */
3383 unregister_netdev(dev);
3384 release_region(dev->base_addr, pdev ? PFI_K_CSR_IO_LEN : PI_ESIC_K_CSR_IO_LEN );
3386 alloc_size = sizeof(PI_DESCR_BLOCK) +
3387 PI_CMD_REQ_K_SIZE_MAX + PI_CMD_RSP_K_SIZE_MAX +
3388 #ifndef DYNAMIC_BUFFERS
3389 (bp->rcv_bufs_to_post * PI_RCV_DATA_K_SIZE_MAX) +
3391 sizeof(PI_CONSUMER_BLOCK) +
3392 (PI_ALIGN_K_DESC_BLK - 1);
3394 pci_free_consistent(pdev, alloc_size, bp->kmalloced,
3399 static void __devexit dfx_remove_one (struct pci_dev *pdev)
3401 struct net_device *dev = pci_get_drvdata(pdev);
3403 dfx_remove_one_pci_or_eisa(pdev, dev);
3404 pci_set_drvdata(pdev, NULL);
3407 static struct pci_device_id dfx_pci_tbl[] = {
3408 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_FDDI, PCI_ANY_ID, PCI_ANY_ID, },
3411 MODULE_DEVICE_TABLE(pci, dfx_pci_tbl);
3413 static struct pci_driver dfx_driver = {
3415 .probe = dfx_init_one,
3416 .remove = __devexit_p(dfx_remove_one),
3417 .id_table = dfx_pci_tbl,
3420 static int dfx_have_pci;
3421 static int dfx_have_eisa;
3424 static void __exit dfx_eisa_cleanup(void)
3426 struct net_device *dev = root_dfx_eisa_dev;
3430 struct net_device *tmp;
3433 bp = (DFX_board_t*)dev->priv;
3435 dfx_remove_one_pci_or_eisa(NULL, dev);
3440 static int __init dfx_init(void)
3442 int rc_pci, rc_eisa;
3444 rc_pci = pci_register_driver(&dfx_driver);
3445 if (rc_pci >= 0) dfx_have_pci = 1;
3447 rc_eisa = dfx_eisa_init();
3448 if (rc_eisa >= 0) dfx_have_eisa = 1;
3450 return ((rc_eisa < 0) ? 0 : rc_eisa) + ((rc_pci < 0) ? 0 : rc_pci);
3453 static void __exit dfx_cleanup(void)
3456 pci_unregister_driver(&dfx_driver);
3462 module_init(dfx_init);
3463 module_exit(dfx_cleanup);
3464 MODULE_AUTHOR("Lawrence V. Stefani");
3465 MODULE_DESCRIPTION("DEC FDDIcontroller EISA/PCI (DEFEA/DEFPA) driver "
3466 DRV_VERSION " " DRV_RELDATE);
3467 MODULE_LICENSE("GPL");
3472 * kernel-compile-command: "gcc -D__KERNEL__ -I/root/linux/include -Wall -Wstrict-prototypes -O2 -pipe -fomit-frame-pointer -fno-strength-reduce -m486 -malign-loops=2 -malign-jumps=2 -malign-functions=2 -c defxx.c"