2 * CAN bus driver for Bosch C_CAN controller
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
7 * Borrowed heavily from the C_CAN driver originally written by:
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
12 * TX and RX NAPI implementation has been borrowed from at91 CAN driver
15 * (C) 2007 by Hans J. Koch <hjk@hansjkoch.de>
16 * (C) 2008, 2009 by Marc Kleine-Budde <kernel@pengutronix.de>
18 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
19 * Bosch C_CAN user manual can be obtained from:
20 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
21 * users_manual_c_can.pdf
23 * This file is licensed under the terms of the GNU General Public
24 * License version 2. This program is licensed "as is" without any
25 * warranty of any kind, whether express or implied.
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/if_arp.h>
35 #include <linux/if_ether.h>
36 #include <linux/list.h>
37 #include <linux/delay.h>
40 #include <linux/can.h>
41 #include <linux/can/dev.h>
42 #include <linux/can/error.h>
46 /* control register */
47 #define CONTROL_TEST BIT(7)
48 #define CONTROL_CCE BIT(6)
49 #define CONTROL_DISABLE_AR BIT(5)
50 #define CONTROL_ENABLE_AR (0 << 5)
51 #define CONTROL_EIE BIT(3)
52 #define CONTROL_SIE BIT(2)
53 #define CONTROL_IE BIT(1)
54 #define CONTROL_INIT BIT(0)
57 #define TEST_RX BIT(7)
58 #define TEST_TX1 BIT(6)
59 #define TEST_TX2 BIT(5)
60 #define TEST_LBACK BIT(4)
61 #define TEST_SILENT BIT(3)
62 #define TEST_BASIC BIT(2)
65 #define STATUS_BOFF BIT(7)
66 #define STATUS_EWARN BIT(6)
67 #define STATUS_EPASS BIT(5)
68 #define STATUS_RXOK BIT(4)
69 #define STATUS_TXOK BIT(3)
71 /* error counter register */
72 #define ERR_CNT_TEC_MASK 0xff
73 #define ERR_CNT_TEC_SHIFT 0
74 #define ERR_CNT_REC_SHIFT 8
75 #define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT)
76 #define ERR_CNT_RP_SHIFT 15
77 #define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT)
79 /* bit-timing register */
80 #define BTR_BRP_MASK 0x3f
81 #define BTR_BRP_SHIFT 0
82 #define BTR_SJW_SHIFT 6
83 #define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT)
84 #define BTR_TSEG1_SHIFT 8
85 #define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT)
86 #define BTR_TSEG2_SHIFT 12
87 #define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT)
89 /* brp extension register */
90 #define BRP_EXT_BRPE_MASK 0x0f
91 #define BRP_EXT_BRPE_SHIFT 0
93 /* IFx command request */
94 #define IF_COMR_BUSY BIT(15)
96 /* IFx command mask */
97 #define IF_COMM_WR BIT(7)
98 #define IF_COMM_MASK BIT(6)
99 #define IF_COMM_ARB BIT(5)
100 #define IF_COMM_CONTROL BIT(4)
101 #define IF_COMM_CLR_INT_PND BIT(3)
102 #define IF_COMM_TXRQST BIT(2)
103 #define IF_COMM_DATAA BIT(1)
104 #define IF_COMM_DATAB BIT(0)
105 #define IF_COMM_ALL (IF_COMM_MASK | IF_COMM_ARB | \
106 IF_COMM_CONTROL | IF_COMM_TXRQST | \
107 IF_COMM_DATAA | IF_COMM_DATAB)
109 /* IFx arbitration */
110 #define IF_ARB_MSGVAL BIT(15)
111 #define IF_ARB_MSGXTD BIT(14)
112 #define IF_ARB_TRANSMIT BIT(13)
114 /* IFx message control */
115 #define IF_MCONT_NEWDAT BIT(15)
116 #define IF_MCONT_MSGLST BIT(14)
117 #define IF_MCONT_CLR_MSGLST (0 << 14)
118 #define IF_MCONT_INTPND BIT(13)
119 #define IF_MCONT_UMASK BIT(12)
120 #define IF_MCONT_TXIE BIT(11)
121 #define IF_MCONT_RXIE BIT(10)
122 #define IF_MCONT_RMTEN BIT(9)
123 #define IF_MCONT_TXRQST BIT(8)
124 #define IF_MCONT_EOB BIT(7)
125 #define IF_MCONT_DLC_MASK 0xf
128 * IFx register masks:
129 * allow easy operation on 16-bit registers when the
130 * argument is 32-bit instead
132 #define IFX_WRITE_LOW_16BIT(x) ((x) & 0xFFFF)
133 #define IFX_WRITE_HIGH_16BIT(x) (((x) & 0xFFFF0000) >> 16)
135 /* message object split */
136 #define C_CAN_NO_OF_OBJECTS 32
137 #define C_CAN_MSG_OBJ_RX_NUM 16
138 #define C_CAN_MSG_OBJ_TX_NUM 16
140 #define C_CAN_MSG_OBJ_RX_FIRST 1
141 #define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
142 C_CAN_MSG_OBJ_RX_NUM - 1)
144 #define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
145 #define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
146 C_CAN_MSG_OBJ_TX_NUM - 1)
148 #define C_CAN_MSG_OBJ_RX_SPLIT 9
149 #define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
151 #define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
152 #define RECEIVE_OBJECT_BITS 0x0000ffff
154 /* status interrupt */
155 #define STATUS_INTERRUPT 0x8000
157 /* global interrupt masks */
158 #define ENABLE_ALL_INTERRUPTS 1
159 #define DISABLE_ALL_INTERRUPTS 0
161 /* minimum timeout for checking BUSY status */
162 #define MIN_TIMEOUT_VALUE 6
165 #define C_CAN_NAPI_WEIGHT C_CAN_MSG_OBJ_RX_NUM
167 /* c_can lec values */
168 enum c_can_lec_type {
181 * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported
183 enum c_can_bus_error_types {
190 static struct can_bittiming_const c_can_bittiming_const = {
191 .name = KBUILD_MODNAME,
192 .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */
194 .tseg2_min = 1, /* Time segment 2 = phase_seg2 */
198 .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/
202 static inline int get_tx_next_msg_obj(const struct c_can_priv *priv)
204 return (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) +
205 C_CAN_MSG_OBJ_TX_FIRST;
208 static inline int get_tx_echo_msg_obj(const struct c_can_priv *priv)
210 return (priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) +
211 C_CAN_MSG_OBJ_TX_FIRST;
214 static u32 c_can_read_reg32(struct c_can_priv *priv, void *reg)
216 u32 val = priv->read_reg(priv, reg);
217 val |= ((u32) priv->read_reg(priv, reg + 2)) << 16;
221 static void c_can_enable_all_interrupts(struct c_can_priv *priv,
224 unsigned int cntrl_save = priv->read_reg(priv,
225 &priv->regs->control);
228 cntrl_save |= (CONTROL_SIE | CONTROL_EIE | CONTROL_IE);
230 cntrl_save &= ~(CONTROL_EIE | CONTROL_IE | CONTROL_SIE);
232 priv->write_reg(priv, &priv->regs->control, cntrl_save);
235 static inline int c_can_msg_obj_is_busy(struct c_can_priv *priv, int iface)
237 int count = MIN_TIMEOUT_VALUE;
239 while (count && priv->read_reg(priv,
240 &priv->regs->ifregs[iface].com_req) &
252 static inline void c_can_object_get(struct net_device *dev,
253 int iface, int objno, int mask)
255 struct c_can_priv *priv = netdev_priv(dev);
258 * As per specs, after writting the message object number in the
259 * IF command request register the transfer b/w interface
260 * register and message RAM must be complete in 6 CAN-CLK
263 priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask,
264 IFX_WRITE_LOW_16BIT(mask));
265 priv->write_reg(priv, &priv->regs->ifregs[iface].com_req,
266 IFX_WRITE_LOW_16BIT(objno));
268 if (c_can_msg_obj_is_busy(priv, iface))
269 netdev_err(dev, "timed out in object get\n");
272 static inline void c_can_object_put(struct net_device *dev,
273 int iface, int objno, int mask)
275 struct c_can_priv *priv = netdev_priv(dev);
278 * As per specs, after writting the message object number in the
279 * IF command request register the transfer b/w interface
280 * register and message RAM must be complete in 6 CAN-CLK
283 priv->write_reg(priv, &priv->regs->ifregs[iface].com_mask,
284 (IF_COMM_WR | IFX_WRITE_LOW_16BIT(mask)));
285 priv->write_reg(priv, &priv->regs->ifregs[iface].com_req,
286 IFX_WRITE_LOW_16BIT(objno));
288 if (c_can_msg_obj_is_busy(priv, iface))
289 netdev_err(dev, "timed out in object put\n");
292 static void c_can_write_msg_object(struct net_device *dev,
293 int iface, struct can_frame *frame, int objno)
298 struct c_can_priv *priv = netdev_priv(dev);
300 if (!(frame->can_id & CAN_RTR_FLAG))
301 flags |= IF_ARB_TRANSMIT;
303 if (frame->can_id & CAN_EFF_FLAG) {
304 id = frame->can_id & CAN_EFF_MASK;
305 flags |= IF_ARB_MSGXTD;
307 id = ((frame->can_id & CAN_SFF_MASK) << 18);
309 flags |= IF_ARB_MSGVAL;
311 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1,
312 IFX_WRITE_LOW_16BIT(id));
313 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, flags |
314 IFX_WRITE_HIGH_16BIT(id));
316 for (i = 0; i < frame->can_dlc; i += 2) {
317 priv->write_reg(priv, &priv->regs->ifregs[iface].data[i / 2],
318 frame->data[i] | (frame->data[i + 1] << 8));
321 /* enable interrupt for this message object */
322 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
323 IF_MCONT_TXIE | IF_MCONT_TXRQST | IF_MCONT_EOB |
325 c_can_object_put(dev, iface, objno, IF_COMM_ALL);
328 static inline void c_can_mark_rx_msg_obj(struct net_device *dev,
329 int iface, int ctrl_mask,
332 struct c_can_priv *priv = netdev_priv(dev);
334 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
335 ctrl_mask & ~(IF_MCONT_MSGLST | IF_MCONT_INTPND));
336 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
340 static inline void c_can_activate_all_lower_rx_msg_obj(struct net_device *dev,
345 struct c_can_priv *priv = netdev_priv(dev);
347 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_MSG_RX_LOW_LAST; i++) {
348 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
349 ctrl_mask & ~(IF_MCONT_MSGLST |
350 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
351 c_can_object_put(dev, iface, i, IF_COMM_CONTROL);
355 static inline void c_can_activate_rx_msg_obj(struct net_device *dev,
356 int iface, int ctrl_mask,
359 struct c_can_priv *priv = netdev_priv(dev);
361 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
362 ctrl_mask & ~(IF_MCONT_MSGLST |
363 IF_MCONT_INTPND | IF_MCONT_NEWDAT));
364 c_can_object_put(dev, iface, obj, IF_COMM_CONTROL);
367 static void c_can_handle_lost_msg_obj(struct net_device *dev,
368 int iface, int objno)
370 struct c_can_priv *priv = netdev_priv(dev);
371 struct net_device_stats *stats = &dev->stats;
373 struct can_frame *frame;
375 netdev_err(dev, "msg lost in buffer %d\n", objno);
377 c_can_object_get(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
379 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl,
380 IF_MCONT_CLR_MSGLST);
382 c_can_object_put(dev, 0, objno, IF_COMM_CONTROL);
384 /* create an error msg */
385 skb = alloc_can_err_skb(dev, &frame);
389 frame->can_id |= CAN_ERR_CRTL;
390 frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
392 stats->rx_over_errors++;
394 netif_receive_skb(skb);
397 static int c_can_read_msg_object(struct net_device *dev, int iface, int ctrl)
402 struct c_can_priv *priv = netdev_priv(dev);
403 struct net_device_stats *stats = &dev->stats;
405 struct can_frame *frame;
407 skb = alloc_can_skb(dev, &frame);
413 frame->can_dlc = get_can_dlc(ctrl & 0x0F);
415 flags = priv->read_reg(priv, &priv->regs->ifregs[iface].arb2);
416 val = priv->read_reg(priv, &priv->regs->ifregs[iface].arb1) |
419 if (flags & IF_ARB_MSGXTD)
420 frame->can_id = (val & CAN_EFF_MASK) | CAN_EFF_FLAG;
422 frame->can_id = (val >> 18) & CAN_SFF_MASK;
424 if (flags & IF_ARB_TRANSMIT)
425 frame->can_id |= CAN_RTR_FLAG;
427 for (i = 0; i < frame->can_dlc; i += 2) {
428 data = priv->read_reg(priv,
429 &priv->regs->ifregs[iface].data[i / 2]);
430 frame->data[i] = data;
431 frame->data[i + 1] = data >> 8;
435 netif_receive_skb(skb);
438 stats->rx_bytes += frame->can_dlc;
443 static void c_can_setup_receive_object(struct net_device *dev, int iface,
444 int objno, unsigned int mask,
445 unsigned int id, unsigned int mcont)
447 struct c_can_priv *priv = netdev_priv(dev);
449 priv->write_reg(priv, &priv->regs->ifregs[iface].mask1,
450 IFX_WRITE_LOW_16BIT(mask));
451 priv->write_reg(priv, &priv->regs->ifregs[iface].mask2,
452 IFX_WRITE_HIGH_16BIT(mask));
454 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1,
455 IFX_WRITE_LOW_16BIT(id));
456 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2,
457 (IF_ARB_MSGVAL | IFX_WRITE_HIGH_16BIT(id)));
459 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, mcont);
460 c_can_object_put(dev, iface, objno, IF_COMM_ALL & ~IF_COMM_TXRQST);
462 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
463 c_can_read_reg32(priv, &priv->regs->msgval1));
466 static void c_can_inval_msg_object(struct net_device *dev, int iface, int objno)
468 struct c_can_priv *priv = netdev_priv(dev);
470 priv->write_reg(priv, &priv->regs->ifregs[iface].arb1, 0);
471 priv->write_reg(priv, &priv->regs->ifregs[iface].arb2, 0);
472 priv->write_reg(priv, &priv->regs->ifregs[iface].msg_cntrl, 0);
474 c_can_object_put(dev, iface, objno, IF_COMM_ARB | IF_COMM_CONTROL);
476 netdev_dbg(dev, "obj no:%d, msgval:0x%08x\n", objno,
477 c_can_read_reg32(priv, &priv->regs->msgval1));
480 static inline int c_can_is_next_tx_obj_busy(struct c_can_priv *priv, int objno)
482 int val = c_can_read_reg32(priv, &priv->regs->txrqst1);
485 * as transmission request register's bit n-1 corresponds to
486 * message object n, we need to handle the same properly.
488 if (val & (1 << (objno - 1)))
494 static netdev_tx_t c_can_start_xmit(struct sk_buff *skb,
495 struct net_device *dev)
498 struct c_can_priv *priv = netdev_priv(dev);
499 struct can_frame *frame = (struct can_frame *)skb->data;
501 if (can_dropped_invalid_skb(dev, skb))
504 msg_obj_no = get_tx_next_msg_obj(priv);
506 /* prepare message object for transmission */
507 c_can_write_msg_object(dev, 0, frame, msg_obj_no);
508 can_put_echo_skb(skb, dev, msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
511 * we have to stop the queue in case of a wrap around or
512 * if the next TX message object is still in use
515 if (c_can_is_next_tx_obj_busy(priv, get_tx_next_msg_obj(priv)) ||
516 (priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) == 0)
517 netif_stop_queue(dev);
522 static int c_can_set_bittiming(struct net_device *dev)
524 unsigned int reg_btr, reg_brpe, ctrl_save;
525 u8 brp, brpe, sjw, tseg1, tseg2;
527 struct c_can_priv *priv = netdev_priv(dev);
528 const struct can_bittiming *bt = &priv->can.bittiming;
530 /* c_can provides a 6-bit brp and 4-bit brpe fields */
531 ten_bit_brp = bt->brp - 1;
532 brp = ten_bit_brp & BTR_BRP_MASK;
533 brpe = ten_bit_brp >> 6;
536 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
537 tseg2 = bt->phase_seg2 - 1;
538 reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) |
539 (tseg2 << BTR_TSEG2_SHIFT);
540 reg_brpe = brpe & BRP_EXT_BRPE_MASK;
543 "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe);
545 ctrl_save = priv->read_reg(priv, &priv->regs->control);
546 priv->write_reg(priv, &priv->regs->control,
547 ctrl_save | CONTROL_CCE | CONTROL_INIT);
548 priv->write_reg(priv, &priv->regs->btr, reg_btr);
549 priv->write_reg(priv, &priv->regs->brp_ext, reg_brpe);
550 priv->write_reg(priv, &priv->regs->control, ctrl_save);
556 * Configure C_CAN message objects for Tx and Rx purposes:
557 * C_CAN provides a total of 32 message objects that can be configured
558 * either for Tx or Rx purposes. Here the first 16 message objects are used as
559 * a reception FIFO. The end of reception FIFO is signified by the EoB bit
560 * being SET. The remaining 16 message objects are kept aside for Tx purposes.
561 * See user guide document for further details on configuring message
564 static void c_can_configure_msg_objects(struct net_device *dev)
568 /* first invalidate all message objects */
569 for (i = C_CAN_MSG_OBJ_RX_FIRST; i <= C_CAN_NO_OF_OBJECTS; i++)
570 c_can_inval_msg_object(dev, 0, i);
572 /* setup receive message objects */
573 for (i = C_CAN_MSG_OBJ_RX_FIRST; i < C_CAN_MSG_OBJ_RX_LAST; i++)
574 c_can_setup_receive_object(dev, 0, i, 0, 0,
575 (IF_MCONT_RXIE | IF_MCONT_UMASK) & ~IF_MCONT_EOB);
577 c_can_setup_receive_object(dev, 0, C_CAN_MSG_OBJ_RX_LAST, 0, 0,
578 IF_MCONT_EOB | IF_MCONT_RXIE | IF_MCONT_UMASK);
582 * Configure C_CAN chip:
583 * - enable/disable auto-retransmission
584 * - set operating mode
585 * - configure message objects
587 static void c_can_chip_config(struct net_device *dev)
589 struct c_can_priv *priv = netdev_priv(dev);
591 if (priv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT)
592 /* disable automatic retransmission */
593 priv->write_reg(priv, &priv->regs->control,
596 /* enable automatic retransmission */
597 priv->write_reg(priv, &priv->regs->control,
600 if (priv->can.ctrlmode & (CAN_CTRLMODE_LISTENONLY &
601 CAN_CTRLMODE_LOOPBACK)) {
602 /* loopback + silent mode : useful for hot self-test */
603 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
604 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
605 priv->write_reg(priv, &priv->regs->test,
606 TEST_LBACK | TEST_SILENT);
607 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
608 /* loopback mode : useful for self-test function */
609 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
610 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
611 priv->write_reg(priv, &priv->regs->test, TEST_LBACK);
612 } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) {
613 /* silent mode : bus-monitoring mode */
614 priv->write_reg(priv, &priv->regs->control, CONTROL_EIE |
615 CONTROL_SIE | CONTROL_IE | CONTROL_TEST);
616 priv->write_reg(priv, &priv->regs->test, TEST_SILENT);
619 priv->write_reg(priv, &priv->regs->control,
620 CONTROL_EIE | CONTROL_SIE | CONTROL_IE);
622 /* configure message objects */
623 c_can_configure_msg_objects(dev);
625 /* set a `lec` value so that we can check for updates later */
626 priv->write_reg(priv, &priv->regs->status, LEC_UNUSED);
628 /* set bittiming params */
629 c_can_set_bittiming(dev);
632 static void c_can_start(struct net_device *dev)
634 struct c_can_priv *priv = netdev_priv(dev);
636 /* enable status change, error and module interrupts */
637 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
639 /* basic c_can configuration */
640 c_can_chip_config(dev);
642 priv->can.state = CAN_STATE_ERROR_ACTIVE;
644 /* reset tx helper pointers */
645 priv->tx_next = priv->tx_echo = 0;
648 static void c_can_stop(struct net_device *dev)
650 struct c_can_priv *priv = netdev_priv(dev);
652 /* disable all interrupts */
653 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
655 /* set the state as STOPPED */
656 priv->can.state = CAN_STATE_STOPPED;
659 static int c_can_set_mode(struct net_device *dev, enum can_mode mode)
664 netif_wake_queue(dev);
673 static int c_can_get_berr_counter(const struct net_device *dev,
674 struct can_berr_counter *bec)
676 unsigned int reg_err_counter;
677 struct c_can_priv *priv = netdev_priv(dev);
679 reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt);
680 bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >>
682 bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK;
688 * theory of operation:
690 * priv->tx_echo holds the number of the oldest can_frame put for
691 * transmission into the hardware, but not yet ACKed by the CAN tx
694 * We iterate from priv->tx_echo to priv->tx_next and check if the
695 * packet has been transmitted, echo it back to the CAN framework.
696 * If we discover a not yet transmitted package, stop looking for more.
698 static void c_can_do_tx(struct net_device *dev)
702 struct c_can_priv *priv = netdev_priv(dev);
703 struct net_device_stats *stats = &dev->stats;
705 for (/* nix */; (priv->tx_next - priv->tx_echo) > 0; priv->tx_echo++) {
706 msg_obj_no = get_tx_echo_msg_obj(priv);
707 c_can_inval_msg_object(dev, 0, msg_obj_no);
708 val = c_can_read_reg32(priv, &priv->regs->txrqst1);
709 if (!(val & (1 << msg_obj_no))) {
710 can_get_echo_skb(dev,
711 msg_obj_no - C_CAN_MSG_OBJ_TX_FIRST);
712 stats->tx_bytes += priv->read_reg(priv,
713 &priv->regs->ifregs[0].msg_cntrl)
719 /* restart queue if wrap-up or if queue stalled on last pkt */
720 if (((priv->tx_next & C_CAN_NEXT_MSG_OBJ_MASK) != 0) ||
721 ((priv->tx_echo & C_CAN_NEXT_MSG_OBJ_MASK) == 0))
722 netif_wake_queue(dev);
726 * theory of operation:
728 * c_can core saves a received CAN message into the first free message
729 * object it finds free (starting with the lowest). Bits NEWDAT and
730 * INTPND are set for this message object indicating that a new message
731 * has arrived. To work-around this issue, we keep two groups of message
732 * objects whose partitioning is defined by C_CAN_MSG_OBJ_RX_SPLIT.
734 * To ensure in-order frame reception we use the following
735 * approach while re-activating a message object to receive further
737 * - if the current message object number is lower than
738 * C_CAN_MSG_RX_LOW_LAST, do not clear the NEWDAT bit while clearing
740 * - if the current message object number is equal to
741 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of all lower
742 * receive message objects.
743 * - if the current message object number is greater than
744 * C_CAN_MSG_RX_LOW_LAST then clear the NEWDAT bit of
745 * only this message object.
747 static int c_can_do_rx_poll(struct net_device *dev, int quota)
750 unsigned int msg_obj, msg_ctrl_save;
751 struct c_can_priv *priv = netdev_priv(dev);
752 u32 val = c_can_read_reg32(priv, &priv->regs->intpnd1);
754 for (msg_obj = C_CAN_MSG_OBJ_RX_FIRST;
755 msg_obj <= C_CAN_MSG_OBJ_RX_LAST && quota > 0;
756 val = c_can_read_reg32(priv, &priv->regs->intpnd1),
759 * as interrupt pending register's bit n-1 corresponds to
760 * message object n, we need to handle the same properly.
762 if (val & (1 << (msg_obj - 1))) {
763 c_can_object_get(dev, 0, msg_obj, IF_COMM_ALL &
765 msg_ctrl_save = priv->read_reg(priv,
766 &priv->regs->ifregs[0].msg_cntrl);
768 if (msg_ctrl_save & IF_MCONT_EOB)
771 if (msg_ctrl_save & IF_MCONT_MSGLST) {
772 c_can_handle_lost_msg_obj(dev, 0, msg_obj);
778 if (!(msg_ctrl_save & IF_MCONT_NEWDAT))
781 /* read the data from the message object */
782 c_can_read_msg_object(dev, 0, msg_ctrl_save);
784 if (msg_obj < C_CAN_MSG_RX_LOW_LAST)
785 c_can_mark_rx_msg_obj(dev, 0,
786 msg_ctrl_save, msg_obj);
787 else if (msg_obj > C_CAN_MSG_RX_LOW_LAST)
788 /* activate this msg obj */
789 c_can_activate_rx_msg_obj(dev, 0,
790 msg_ctrl_save, msg_obj);
791 else if (msg_obj == C_CAN_MSG_RX_LOW_LAST)
792 /* activate all lower message objects */
793 c_can_activate_all_lower_rx_msg_obj(dev,
804 static inline int c_can_has_and_handle_berr(struct c_can_priv *priv)
806 return (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
807 (priv->current_status & LEC_UNUSED);
810 static int c_can_handle_state_change(struct net_device *dev,
811 enum c_can_bus_error_types error_type)
813 unsigned int reg_err_counter;
814 unsigned int rx_err_passive;
815 struct c_can_priv *priv = netdev_priv(dev);
816 struct net_device_stats *stats = &dev->stats;
817 struct can_frame *cf;
819 struct can_berr_counter bec;
821 /* propogate the error condition to the CAN stack */
822 skb = alloc_can_err_skb(dev, &cf);
826 c_can_get_berr_counter(dev, &bec);
827 reg_err_counter = priv->read_reg(priv, &priv->regs->err_cnt);
828 rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >>
831 switch (error_type) {
832 case C_CAN_ERROR_WARNING:
833 /* error warning state */
834 priv->can.can_stats.error_warning++;
835 priv->can.state = CAN_STATE_ERROR_WARNING;
836 cf->can_id |= CAN_ERR_CRTL;
837 cf->data[1] = (bec.txerr > bec.rxerr) ?
838 CAN_ERR_CRTL_TX_WARNING :
839 CAN_ERR_CRTL_RX_WARNING;
840 cf->data[6] = bec.txerr;
841 cf->data[7] = bec.rxerr;
844 case C_CAN_ERROR_PASSIVE:
845 /* error passive state */
846 priv->can.can_stats.error_passive++;
847 priv->can.state = CAN_STATE_ERROR_PASSIVE;
848 cf->can_id |= CAN_ERR_CRTL;
850 cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
852 cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
854 cf->data[6] = bec.txerr;
855 cf->data[7] = bec.rxerr;
859 priv->can.state = CAN_STATE_BUS_OFF;
860 cf->can_id |= CAN_ERR_BUSOFF;
862 * disable all interrupts in bus-off mode to ensure that
863 * the CPU is not hogged down
865 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
872 netif_receive_skb(skb);
874 stats->rx_bytes += cf->can_dlc;
879 static int c_can_handle_bus_err(struct net_device *dev,
880 enum c_can_lec_type lec_type)
882 struct c_can_priv *priv = netdev_priv(dev);
883 struct net_device_stats *stats = &dev->stats;
884 struct can_frame *cf;
888 * early exit if no lec update or no error.
889 * no lec update means that no CAN bus event has been detected
890 * since CPU wrote 0x7 value to status reg.
892 if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR)
895 /* propogate the error condition to the CAN stack */
896 skb = alloc_can_err_skb(dev, &cf);
901 * check for 'last error code' which tells us the
902 * type of the last error to occur on the CAN bus
905 /* common for all type of bus errors */
906 priv->can.can_stats.bus_error++;
908 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
909 cf->data[2] |= CAN_ERR_PROT_UNSPEC;
912 case LEC_STUFF_ERROR:
913 netdev_dbg(dev, "stuff error\n");
914 cf->data[2] |= CAN_ERR_PROT_STUFF;
917 netdev_dbg(dev, "form error\n");
918 cf->data[2] |= CAN_ERR_PROT_FORM;
921 netdev_dbg(dev, "ack error\n");
922 cf->data[2] |= (CAN_ERR_PROT_LOC_ACK |
923 CAN_ERR_PROT_LOC_ACK_DEL);
926 netdev_dbg(dev, "bit1 error\n");
927 cf->data[2] |= CAN_ERR_PROT_BIT1;
930 netdev_dbg(dev, "bit0 error\n");
931 cf->data[2] |= CAN_ERR_PROT_BIT0;
934 netdev_dbg(dev, "CRC error\n");
935 cf->data[2] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
936 CAN_ERR_PROT_LOC_CRC_DEL);
942 /* set a `lec` value so that we can check for updates later */
943 priv->write_reg(priv, &priv->regs->status, LEC_UNUSED);
945 netif_receive_skb(skb);
947 stats->rx_bytes += cf->can_dlc;
952 static int c_can_poll(struct napi_struct *napi, int quota)
957 struct net_device *dev = napi->dev;
958 struct c_can_priv *priv = netdev_priv(dev);
960 irqstatus = priv->read_reg(priv, &priv->regs->interrupt);
964 /* status events have the highest priority */
965 if (irqstatus == STATUS_INTERRUPT) {
966 priv->current_status = priv->read_reg(priv,
967 &priv->regs->status);
969 /* handle Tx/Rx events */
970 if (priv->current_status & STATUS_TXOK)
971 priv->write_reg(priv, &priv->regs->status,
972 priv->current_status & ~STATUS_TXOK);
974 if (priv->current_status & STATUS_RXOK)
975 priv->write_reg(priv, &priv->regs->status,
976 priv->current_status & ~STATUS_RXOK);
978 /* handle state changes */
979 if ((priv->current_status & STATUS_EWARN) &&
980 (!(priv->last_status & STATUS_EWARN))) {
981 netdev_dbg(dev, "entered error warning state\n");
982 work_done += c_can_handle_state_change(dev,
983 C_CAN_ERROR_WARNING);
985 if ((priv->current_status & STATUS_EPASS) &&
986 (!(priv->last_status & STATUS_EPASS))) {
987 netdev_dbg(dev, "entered error passive state\n");
988 work_done += c_can_handle_state_change(dev,
989 C_CAN_ERROR_PASSIVE);
991 if ((priv->current_status & STATUS_BOFF) &&
992 (!(priv->last_status & STATUS_BOFF))) {
993 netdev_dbg(dev, "entered bus off state\n");
994 work_done += c_can_handle_state_change(dev,
998 /* handle bus recovery events */
999 if ((!(priv->current_status & STATUS_BOFF)) &&
1000 (priv->last_status & STATUS_BOFF)) {
1001 netdev_dbg(dev, "left bus off state\n");
1002 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1004 if ((!(priv->current_status & STATUS_EPASS)) &&
1005 (priv->last_status & STATUS_EPASS)) {
1006 netdev_dbg(dev, "left error passive state\n");
1007 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1010 priv->last_status = priv->current_status;
1012 /* handle lec errors on the bus */
1013 lec_type = c_can_has_and_handle_berr(priv);
1015 work_done += c_can_handle_bus_err(dev, lec_type);
1016 } else if ((irqstatus >= C_CAN_MSG_OBJ_RX_FIRST) &&
1017 (irqstatus <= C_CAN_MSG_OBJ_RX_LAST)) {
1018 /* handle events corresponding to receive message objects */
1019 work_done += c_can_do_rx_poll(dev, (quota - work_done));
1020 } else if ((irqstatus >= C_CAN_MSG_OBJ_TX_FIRST) &&
1021 (irqstatus <= C_CAN_MSG_OBJ_TX_LAST)) {
1022 /* handle events corresponding to transmit message objects */
1027 if (work_done < quota) {
1028 napi_complete(napi);
1029 /* enable all IRQs */
1030 c_can_enable_all_interrupts(priv, ENABLE_ALL_INTERRUPTS);
1036 static irqreturn_t c_can_isr(int irq, void *dev_id)
1039 struct net_device *dev = (struct net_device *)dev_id;
1040 struct c_can_priv *priv = netdev_priv(dev);
1042 irqstatus = priv->read_reg(priv, &priv->regs->interrupt);
1046 /* disable all interrupts and schedule the NAPI */
1047 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1048 napi_schedule(&priv->napi);
1053 static int c_can_open(struct net_device *dev)
1056 struct c_can_priv *priv = netdev_priv(dev);
1058 /* open the can device */
1059 err = open_candev(dev);
1061 netdev_err(dev, "failed to open can device\n");
1065 /* register interrupt handler */
1066 err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name,
1069 netdev_err(dev, "failed to request interrupt\n");
1073 /* start the c_can controller */
1076 napi_enable(&priv->napi);
1077 netif_start_queue(dev);
1086 static int c_can_close(struct net_device *dev)
1088 struct c_can_priv *priv = netdev_priv(dev);
1090 netif_stop_queue(dev);
1091 napi_disable(&priv->napi);
1093 free_irq(dev->irq, dev);
1099 struct net_device *alloc_c_can_dev(void)
1101 struct net_device *dev;
1102 struct c_can_priv *priv;
1104 dev = alloc_candev(sizeof(struct c_can_priv), C_CAN_MSG_OBJ_TX_NUM);
1108 priv = netdev_priv(dev);
1109 netif_napi_add(dev, &priv->napi, c_can_poll, C_CAN_NAPI_WEIGHT);
1112 priv->can.bittiming_const = &c_can_bittiming_const;
1113 priv->can.do_set_mode = c_can_set_mode;
1114 priv->can.do_get_berr_counter = c_can_get_berr_counter;
1115 priv->can.ctrlmode_supported = CAN_CTRLMODE_ONE_SHOT |
1116 CAN_CTRLMODE_LOOPBACK |
1117 CAN_CTRLMODE_LISTENONLY |
1118 CAN_CTRLMODE_BERR_REPORTING;
1122 EXPORT_SYMBOL_GPL(alloc_c_can_dev);
1124 void free_c_can_dev(struct net_device *dev)
1128 EXPORT_SYMBOL_GPL(free_c_can_dev);
1130 static const struct net_device_ops c_can_netdev_ops = {
1131 .ndo_open = c_can_open,
1132 .ndo_stop = c_can_close,
1133 .ndo_start_xmit = c_can_start_xmit,
1136 int register_c_can_dev(struct net_device *dev)
1138 dev->flags |= IFF_ECHO; /* we support local echo */
1139 dev->netdev_ops = &c_can_netdev_ops;
1141 return register_candev(dev);
1143 EXPORT_SYMBOL_GPL(register_c_can_dev);
1145 void unregister_c_can_dev(struct net_device *dev)
1147 struct c_can_priv *priv = netdev_priv(dev);
1149 /* disable all interrupts */
1150 c_can_enable_all_interrupts(priv, DISABLE_ALL_INTERRUPTS);
1152 unregister_candev(dev);
1154 EXPORT_SYMBOL_GPL(unregister_c_can_dev);
1156 MODULE_AUTHOR("Bhupesh Sharma <bhupesh.sharma@st.com>");
1157 MODULE_LICENSE("GPL v2");
1158 MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller");