1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <net/ip6_checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/crc32c.h>
49 #include <linux/prefetch.h>
50 #include <linux/zlib.h>
52 #include <linux/stringify.h>
53 #include <linux/vmalloc.h>
56 #include "bnx2x_init.h"
57 #include "bnx2x_init_ops.h"
58 #include "bnx2x_cmn.h"
59 #include "bnx2x_dcb.h"
62 #include <linux/firmware.h>
63 #include "bnx2x_fw_file_hdr.h"
65 #define FW_FILE_VERSION \
66 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
67 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
68 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
69 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
70 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
71 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
72 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
74 /* Time in jiffies before concluding the transmitter is hung */
75 #define TX_TIMEOUT (5*HZ)
77 static char version[] __devinitdata =
78 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
79 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
81 MODULE_AUTHOR("Eliezer Tamir");
82 MODULE_DESCRIPTION("Broadcom NetXtreme II "
83 "BCM57710/57711/57711E/"
84 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
85 "57840/57840_MF Driver");
86 MODULE_LICENSE("GPL");
87 MODULE_VERSION(DRV_MODULE_VERSION);
88 MODULE_FIRMWARE(FW_FILE_NAME_E1);
89 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
90 MODULE_FIRMWARE(FW_FILE_NAME_E2);
92 static int multi_mode = 1;
93 module_param(multi_mode, int, 0);
94 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
95 "(0 Disable; 1 Enable (default))");
98 module_param(num_queues, int, 0);
99 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
100 " (default is as a number of CPUs)");
102 static int disable_tpa;
103 module_param(disable_tpa, int, 0);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106 #define INT_MODE_INTx 1
107 #define INT_MODE_MSI 2
109 module_param(int_mode, int, 0);
110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
113 static int dropless_fc;
114 module_param(dropless_fc, int, 0);
115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118 module_param(poll, int, 0);
119 MODULE_PARM_DESC(poll, " Use polling (for debug)");
121 static int mrrs = -1;
122 module_param(mrrs, int, 0);
123 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
126 module_param(debug, int, 0);
127 MODULE_PARM_DESC(debug, " Default debug msglevel");
131 struct workqueue_struct *bnx2x_wq;
133 enum bnx2x_board_type {
147 /* indexed by board_type, above */
150 } board_info[] __devinitdata = {
151 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
152 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
155 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
162 "Ethernet Multi Function"}
165 #ifndef PCI_DEVICE_ID_NX2_57710
166 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
168 #ifndef PCI_DEVICE_ID_NX2_57711
169 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
171 #ifndef PCI_DEVICE_ID_NX2_57711E
172 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
174 #ifndef PCI_DEVICE_ID_NX2_57712
175 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
177 #ifndef PCI_DEVICE_ID_NX2_57712_MF
178 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
180 #ifndef PCI_DEVICE_ID_NX2_57800
181 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
183 #ifndef PCI_DEVICE_ID_NX2_57800_MF
184 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
186 #ifndef PCI_DEVICE_ID_NX2_57810
187 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
189 #ifndef PCI_DEVICE_ID_NX2_57810_MF
190 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
192 #ifndef PCI_DEVICE_ID_NX2_57840
193 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
195 #ifndef PCI_DEVICE_ID_NX2_57840_MF
196 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
198 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
199 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
200 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
201 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
202 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
203 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
204 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
205 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
206 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
207 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
208 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840), BCM57840 },
209 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
213 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
215 /****************************************************************************
216 * General service functions
217 ****************************************************************************/
219 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
220 u32 addr, dma_addr_t mapping)
222 REG_WR(bp, addr, U64_LO(mapping));
223 REG_WR(bp, addr + 4, U64_HI(mapping));
226 static inline void storm_memset_spq_addr(struct bnx2x *bp,
227 dma_addr_t mapping, u16 abs_fid)
229 u32 addr = XSEM_REG_FAST_MEMORY +
230 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
232 __storm_memset_dma_mapping(bp, addr, mapping);
235 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
238 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
240 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
242 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
244 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
248 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
251 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
253 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
255 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
257 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
261 static inline void storm_memset_eq_data(struct bnx2x *bp,
262 struct event_ring_data *eq_data,
265 size_t size = sizeof(struct event_ring_data);
267 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
269 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
272 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
275 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
276 REG_WR16(bp, addr, eq_prod);
280 * locking is done by mcp
282 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
284 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
285 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
286 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
287 PCICFG_VENDOR_ID_OFFSET);
290 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
294 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
295 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
296 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
297 PCICFG_VENDOR_ID_OFFSET);
302 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
303 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
304 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
305 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
306 #define DMAE_DP_DST_NONE "dst_addr [none]"
308 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
311 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
313 switch (dmae->opcode & DMAE_COMMAND_DST) {
314 case DMAE_CMD_DST_PCI:
315 if (src_type == DMAE_CMD_SRC_PCI)
316 DP(msglvl, "DMAE: opcode 0x%08x\n"
317 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
318 "comp_addr [%x:%08x], comp_val 0x%08x\n",
319 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
320 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
321 dmae->comp_addr_hi, dmae->comp_addr_lo,
324 DP(msglvl, "DMAE: opcode 0x%08x\n"
325 "src [%08x], len [%d*4], dst [%x:%08x]\n"
326 "comp_addr [%x:%08x], comp_val 0x%08x\n",
327 dmae->opcode, dmae->src_addr_lo >> 2,
328 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
329 dmae->comp_addr_hi, dmae->comp_addr_lo,
332 case DMAE_CMD_DST_GRC:
333 if (src_type == DMAE_CMD_SRC_PCI)
334 DP(msglvl, "DMAE: opcode 0x%08x\n"
335 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
336 "comp_addr [%x:%08x], comp_val 0x%08x\n",
337 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
338 dmae->len, dmae->dst_addr_lo >> 2,
339 dmae->comp_addr_hi, dmae->comp_addr_lo,
342 DP(msglvl, "DMAE: opcode 0x%08x\n"
343 "src [%08x], len [%d*4], dst [%08x]\n"
344 "comp_addr [%x:%08x], comp_val 0x%08x\n",
345 dmae->opcode, dmae->src_addr_lo >> 2,
346 dmae->len, dmae->dst_addr_lo >> 2,
347 dmae->comp_addr_hi, dmae->comp_addr_lo,
351 if (src_type == DMAE_CMD_SRC_PCI)
352 DP(msglvl, "DMAE: opcode 0x%08x\n"
353 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
355 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
356 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
357 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
360 DP(msglvl, "DMAE: opcode 0x%08x\n"
361 DP_LEVEL "src_addr [%08x] len [%d * 4] "
363 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
364 dmae->opcode, dmae->src_addr_lo >> 2,
365 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
372 /* copy command into DMAE command memory and set DMAE command go */
373 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
378 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
379 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
380 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
382 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
383 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
385 REG_WR(bp, dmae_reg_go_c[idx], 1);
388 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
390 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
394 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
396 return opcode & ~DMAE_CMD_SRC_RESET;
399 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
400 bool with_comp, u8 comp_type)
404 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
405 (dst_type << DMAE_COMMAND_DST_SHIFT));
407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
415 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
417 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
420 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
424 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
425 struct dmae_command *dmae,
426 u8 src_type, u8 dst_type)
428 memset(dmae, 0, sizeof(struct dmae_command));
431 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
432 true, DMAE_COMP_PCI);
434 /* fill in the completion parameters */
435 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
436 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
437 dmae->comp_val = DMAE_COMP_VAL;
440 /* issue a dmae command over the init-channel and wailt for completion */
441 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
442 struct dmae_command *dmae)
444 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
445 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
448 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
449 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
450 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
453 * Lock the dmae channel. Disable BHs to prevent a dead-lock
454 * as long as this code is called both from syscall context and
455 * from ndo_set_rx_mode() flow that may be called from BH.
457 spin_lock_bh(&bp->dmae_lock);
459 /* reset completion */
462 /* post the command on the channel used for initializations */
463 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
465 /* wait for completion */
467 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
468 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
471 BNX2X_ERR("DMAE timeout!\n");
478 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
479 BNX2X_ERR("DMAE PCI error!\n");
483 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
484 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
485 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
488 spin_unlock_bh(&bp->dmae_lock);
492 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
495 struct dmae_command dmae;
497 if (!bp->dmae_ready) {
498 u32 *data = bnx2x_sp(bp, wb_data[0]);
500 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
501 " using indirect\n", dst_addr, len32);
502 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
506 /* set opcode and fixed command fields */
507 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
509 /* fill in addresses and len */
510 dmae.src_addr_lo = U64_LO(dma_addr);
511 dmae.src_addr_hi = U64_HI(dma_addr);
512 dmae.dst_addr_lo = dst_addr >> 2;
513 dmae.dst_addr_hi = 0;
516 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
518 /* issue the command and wait for completion */
519 bnx2x_issue_dmae_with_comp(bp, &dmae);
522 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
524 struct dmae_command dmae;
526 if (!bp->dmae_ready) {
527 u32 *data = bnx2x_sp(bp, wb_data[0]);
530 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
531 " using indirect\n", src_addr, len32);
532 for (i = 0; i < len32; i++)
533 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
537 /* set opcode and fixed command fields */
538 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
540 /* fill in addresses and len */
541 dmae.src_addr_lo = src_addr >> 2;
542 dmae.src_addr_hi = 0;
543 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
544 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
547 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
549 /* issue the command and wait for completion */
550 bnx2x_issue_dmae_with_comp(bp, &dmae);
553 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
556 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
559 while (len > dmae_wr_max) {
560 bnx2x_write_dmae(bp, phys_addr + offset,
561 addr + offset, dmae_wr_max);
562 offset += dmae_wr_max * 4;
566 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
569 /* used only for slowpath so not inlined */
570 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
574 wb_write[0] = val_hi;
575 wb_write[1] = val_lo;
576 REG_WR_DMAE(bp, reg, wb_write, 2);
580 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
584 REG_RD_DMAE(bp, reg, wb_data, 2);
586 return HILO_U64(wb_data[0], wb_data[1]);
590 static int bnx2x_mc_assert(struct bnx2x *bp)
594 u32 row0, row1, row2, row3;
597 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
598 XSTORM_ASSERT_LIST_INDEX_OFFSET);
600 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
602 /* print the asserts */
603 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
605 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
606 XSTORM_ASSERT_LIST_OFFSET(i));
607 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
608 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
609 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
610 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
611 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
612 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
614 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
615 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
616 " 0x%08x 0x%08x 0x%08x\n",
617 i, row3, row2, row1, row0);
625 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
626 TSTORM_ASSERT_LIST_INDEX_OFFSET);
628 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
630 /* print the asserts */
631 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
633 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
634 TSTORM_ASSERT_LIST_OFFSET(i));
635 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
636 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
637 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
638 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
639 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
640 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
642 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
643 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
644 " 0x%08x 0x%08x 0x%08x\n",
645 i, row3, row2, row1, row0);
653 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
654 CSTORM_ASSERT_LIST_INDEX_OFFSET);
656 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
658 /* print the asserts */
659 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
661 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
662 CSTORM_ASSERT_LIST_OFFSET(i));
663 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
664 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
665 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
666 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
667 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
668 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
670 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
671 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
672 " 0x%08x 0x%08x 0x%08x\n",
673 i, row3, row2, row1, row0);
681 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
682 USTORM_ASSERT_LIST_INDEX_OFFSET);
684 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
686 /* print the asserts */
687 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
689 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
690 USTORM_ASSERT_LIST_OFFSET(i));
691 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
692 USTORM_ASSERT_LIST_OFFSET(i) + 4);
693 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
694 USTORM_ASSERT_LIST_OFFSET(i) + 8);
695 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
696 USTORM_ASSERT_LIST_OFFSET(i) + 12);
698 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
699 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
700 " 0x%08x 0x%08x 0x%08x\n",
701 i, row3, row2, row1, row0);
711 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
717 u32 trace_shmem_base;
719 BNX2X_ERR("NO MCP - can not dump\n");
722 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
723 (bp->common.bc_ver & 0xff0000) >> 16,
724 (bp->common.bc_ver & 0xff00) >> 8,
725 (bp->common.bc_ver & 0xff));
727 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
728 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
729 printk("%s" "MCP PC at 0x%x\n", lvl, val);
731 if (BP_PATH(bp) == 0)
732 trace_shmem_base = bp->common.shmem_base;
734 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
735 addr = trace_shmem_base - 0x0800 + 4;
736 mark = REG_RD(bp, addr);
737 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
738 + ((mark + 0x3) & ~0x3) - 0x08000000;
739 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
742 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
743 for (word = 0; word < 8; word++)
744 data[word] = htonl(REG_RD(bp, offset + 4*word));
746 pr_cont("%s", (char *)data);
748 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
749 for (word = 0; word < 8; word++)
750 data[word] = htonl(REG_RD(bp, offset + 4*word));
752 pr_cont("%s", (char *)data);
754 printk("%s" "end of fw dump\n", lvl);
757 static inline void bnx2x_fw_dump(struct bnx2x *bp)
759 bnx2x_fw_dump_lvl(bp, KERN_ERR);
762 void bnx2x_panic_dump(struct bnx2x *bp)
766 struct hc_sp_status_block_data sp_sb_data;
767 int func = BP_FUNC(bp);
768 #ifdef BNX2X_STOP_ON_ERROR
769 u16 start = 0, end = 0;
773 bp->stats_state = STATS_STATE_DISABLED;
774 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
776 BNX2X_ERR("begin crash dump -----------------\n");
780 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
781 " spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
782 bp->def_idx, bp->def_att_idx, bp->attn_state,
783 bp->spq_prod_idx, bp->stats_counter);
784 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
785 bp->def_status_blk->atten_status_block.attn_bits,
786 bp->def_status_blk->atten_status_block.attn_bits_ack,
787 bp->def_status_blk->atten_status_block.status_block_id,
788 bp->def_status_blk->atten_status_block.attn_bits_index);
790 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
792 bp->def_status_blk->sp_sb.index_values[i],
793 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
795 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
796 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
797 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
800 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) "
801 "pf_id(0x%x) vnic_id(0x%x) "
802 "vf_id(0x%x) vf_valid (0x%x) "
804 sp_sb_data.igu_sb_id,
805 sp_sb_data.igu_seg_id,
806 sp_sb_data.p_func.pf_id,
807 sp_sb_data.p_func.vnic_id,
808 sp_sb_data.p_func.vf_id,
809 sp_sb_data.p_func.vf_valid,
813 for_each_eth_queue(bp, i) {
814 struct bnx2x_fastpath *fp = &bp->fp[i];
816 struct hc_status_block_data_e2 sb_data_e2;
817 struct hc_status_block_data_e1x sb_data_e1x;
818 struct hc_status_block_sm *hc_sm_p =
820 sb_data_e1x.common.state_machine :
821 sb_data_e2.common.state_machine;
822 struct hc_index_data *hc_index_p =
824 sb_data_e1x.index_data :
825 sb_data_e2.index_data;
828 struct bnx2x_fp_txdata txdata;
831 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
832 " rx_comp_prod(0x%x)"
833 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
834 i, fp->rx_bd_prod, fp->rx_bd_cons,
836 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
837 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
838 " fp_hc_idx(0x%x)\n",
839 fp->rx_sge_prod, fp->last_max_sge,
840 le16_to_cpu(fp->fp_hc_idx));
843 for_each_cos_in_tx_queue(fp, cos)
845 txdata = fp->txdata[cos];
846 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
847 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
848 " *tx_cons_sb(0x%x)\n",
849 i, txdata.tx_pkt_prod,
850 txdata.tx_pkt_cons, txdata.tx_bd_prod,
852 le16_to_cpu(*txdata.tx_cons_sb));
855 loop = CHIP_IS_E1x(bp) ?
856 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
864 BNX2X_ERR(" run indexes (");
865 for (j = 0; j < HC_SB_MAX_SM; j++)
867 fp->sb_running_index[j],
868 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
870 BNX2X_ERR(" indexes (");
871 for (j = 0; j < loop; j++)
873 fp->sb_index_values[j],
874 (j == loop - 1) ? ")" : " ");
876 data_size = CHIP_IS_E1x(bp) ?
877 sizeof(struct hc_status_block_data_e1x) :
878 sizeof(struct hc_status_block_data_e2);
879 data_size /= sizeof(u32);
880 sb_data_p = CHIP_IS_E1x(bp) ?
881 (u32 *)&sb_data_e1x :
883 /* copy sb data in here */
884 for (j = 0; j < data_size; j++)
885 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
886 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
889 if (!CHIP_IS_E1x(bp)) {
890 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
891 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
893 sb_data_e2.common.p_func.pf_id,
894 sb_data_e2.common.p_func.vf_id,
895 sb_data_e2.common.p_func.vf_valid,
896 sb_data_e2.common.p_func.vnic_id,
897 sb_data_e2.common.same_igu_sb_1b,
898 sb_data_e2.common.state);
900 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) "
901 "vnic_id(0x%x) same_igu_sb_1b(0x%x) "
903 sb_data_e1x.common.p_func.pf_id,
904 sb_data_e1x.common.p_func.vf_id,
905 sb_data_e1x.common.p_func.vf_valid,
906 sb_data_e1x.common.p_func.vnic_id,
907 sb_data_e1x.common.same_igu_sb_1b,
908 sb_data_e1x.common.state);
912 for (j = 0; j < HC_SB_MAX_SM; j++) {
913 pr_cont("SM[%d] __flags (0x%x) "
914 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
915 "time_to_expire (0x%x) "
916 "timer_value(0x%x)\n", j,
918 hc_sm_p[j].igu_sb_id,
919 hc_sm_p[j].igu_seg_id,
920 hc_sm_p[j].time_to_expire,
921 hc_sm_p[j].timer_value);
925 for (j = 0; j < loop; j++) {
926 pr_cont("INDEX[%d] flags (0x%x) "
927 "timeout (0x%x)\n", j,
929 hc_index_p[j].timeout);
933 #ifdef BNX2X_STOP_ON_ERROR
936 for_each_rx_queue(bp, i) {
937 struct bnx2x_fastpath *fp = &bp->fp[i];
939 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
940 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
941 for (j = start; j != end; j = RX_BD(j + 1)) {
942 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
943 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
945 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
946 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
949 start = RX_SGE(fp->rx_sge_prod);
950 end = RX_SGE(fp->last_max_sge);
951 for (j = start; j != end; j = RX_SGE(j + 1)) {
952 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
953 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
955 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
956 i, j, rx_sge[1], rx_sge[0], sw_page->page);
959 start = RCQ_BD(fp->rx_comp_cons - 10);
960 end = RCQ_BD(fp->rx_comp_cons + 503);
961 for (j = start; j != end; j = RCQ_BD(j + 1)) {
962 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
964 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
965 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
970 for_each_tx_queue(bp, i) {
971 struct bnx2x_fastpath *fp = &bp->fp[i];
972 for_each_cos_in_tx_queue(fp, cos) {
973 struct bnx2x_fp_txdata *txdata = &fp->txdata[cos];
975 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
976 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
977 for (j = start; j != end; j = TX_BD(j + 1)) {
978 struct sw_tx_bd *sw_bd =
979 &txdata->tx_buf_ring[j];
981 BNX2X_ERR("fp%d: txdata %d, "
982 "packet[%x]=[%p,%x]\n",
983 i, cos, j, sw_bd->skb,
987 start = TX_BD(txdata->tx_bd_cons - 10);
988 end = TX_BD(txdata->tx_bd_cons + 254);
989 for (j = start; j != end; j = TX_BD(j + 1)) {
990 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
992 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]="
994 i, cos, j, tx_bd[0], tx_bd[1],
1001 bnx2x_mc_assert(bp);
1002 BNX2X_ERR("end crash dump -----------------\n");
1006 * FLR Support for E2
1008 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1011 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1012 #define FLR_WAIT_INTERAVAL 50 /* usec */
1013 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERAVAL) /* 200 */
1015 struct pbf_pN_buf_regs {
1022 struct pbf_pN_cmd_regs {
1028 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1029 struct pbf_pN_buf_regs *regs,
1032 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1033 u32 cur_cnt = poll_count;
1035 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1036 crd = crd_start = REG_RD(bp, regs->crd);
1037 init_crd = REG_RD(bp, regs->init_crd);
1039 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1040 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1041 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1043 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1044 (init_crd - crd_start))) {
1046 udelay(FLR_WAIT_INTERAVAL);
1047 crd = REG_RD(bp, regs->crd);
1048 crd_freed = REG_RD(bp, regs->crd_freed);
1050 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1052 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1054 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1055 regs->pN, crd_freed);
1059 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1060 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1063 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1064 struct pbf_pN_cmd_regs *regs,
1067 u32 occup, to_free, freed, freed_start;
1068 u32 cur_cnt = poll_count;
1070 occup = to_free = REG_RD(bp, regs->lines_occup);
1071 freed = freed_start = REG_RD(bp, regs->lines_freed);
1073 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1074 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1076 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1078 udelay(FLR_WAIT_INTERAVAL);
1079 occup = REG_RD(bp, regs->lines_occup);
1080 freed = REG_RD(bp, regs->lines_freed);
1082 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1084 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1086 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1091 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1092 poll_count-cur_cnt, FLR_WAIT_INTERAVAL, regs->pN);
1095 static inline u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1096 u32 expected, u32 poll_count)
1098 u32 cur_cnt = poll_count;
1101 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1102 udelay(FLR_WAIT_INTERAVAL);
1107 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1108 char *msg, u32 poll_cnt)
1110 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1112 BNX2X_ERR("%s usage count=%d\n", msg, val);
1118 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1120 /* adjust polling timeout */
1121 if (CHIP_REV_IS_EMUL(bp))
1122 return FLR_POLL_CNT * 2000;
1124 if (CHIP_REV_IS_FPGA(bp))
1125 return FLR_POLL_CNT * 120;
1127 return FLR_POLL_CNT;
1130 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1132 struct pbf_pN_cmd_regs cmd_regs[] = {
1133 {0, (CHIP_IS_E3B0(bp)) ?
1134 PBF_REG_TQ_OCCUPANCY_Q0 :
1135 PBF_REG_P0_TQ_OCCUPANCY,
1136 (CHIP_IS_E3B0(bp)) ?
1137 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1138 PBF_REG_P0_TQ_LINES_FREED_CNT},
1139 {1, (CHIP_IS_E3B0(bp)) ?
1140 PBF_REG_TQ_OCCUPANCY_Q1 :
1141 PBF_REG_P1_TQ_OCCUPANCY,
1142 (CHIP_IS_E3B0(bp)) ?
1143 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1144 PBF_REG_P1_TQ_LINES_FREED_CNT},
1145 {4, (CHIP_IS_E3B0(bp)) ?
1146 PBF_REG_TQ_OCCUPANCY_LB_Q :
1147 PBF_REG_P4_TQ_OCCUPANCY,
1148 (CHIP_IS_E3B0(bp)) ?
1149 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1150 PBF_REG_P4_TQ_LINES_FREED_CNT}
1153 struct pbf_pN_buf_regs buf_regs[] = {
1154 {0, (CHIP_IS_E3B0(bp)) ?
1155 PBF_REG_INIT_CRD_Q0 :
1156 PBF_REG_P0_INIT_CRD ,
1157 (CHIP_IS_E3B0(bp)) ?
1160 (CHIP_IS_E3B0(bp)) ?
1161 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1162 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1163 {1, (CHIP_IS_E3B0(bp)) ?
1164 PBF_REG_INIT_CRD_Q1 :
1165 PBF_REG_P1_INIT_CRD,
1166 (CHIP_IS_E3B0(bp)) ?
1169 (CHIP_IS_E3B0(bp)) ?
1170 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1171 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1172 {4, (CHIP_IS_E3B0(bp)) ?
1173 PBF_REG_INIT_CRD_LB_Q :
1174 PBF_REG_P4_INIT_CRD,
1175 (CHIP_IS_E3B0(bp)) ?
1176 PBF_REG_CREDIT_LB_Q :
1178 (CHIP_IS_E3B0(bp)) ?
1179 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1180 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1185 /* Verify the command queues are flushed P0, P1, P4 */
1186 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1187 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1190 /* Verify the transmission buffers are flushed P0, P1, P4 */
1191 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1192 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1195 #define OP_GEN_PARAM(param) \
1196 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1198 #define OP_GEN_TYPE(type) \
1199 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1201 #define OP_GEN_AGG_VECT(index) \
1202 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1205 static inline int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1208 struct sdm_op_gen op_gen = {0};
1210 u32 comp_addr = BAR_CSTRORM_INTMEM +
1211 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1214 if (REG_RD(bp, comp_addr)) {
1215 BNX2X_ERR("Cleanup complete is not 0\n");
1219 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1220 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1221 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1222 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1224 DP(BNX2X_MSG_SP, "FW Final cleanup\n");
1225 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1227 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1228 BNX2X_ERR("FW final cleanup did not succeed\n");
1231 /* Zero completion for nxt FLR */
1232 REG_WR(bp, comp_addr, 0);
1237 static inline u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1242 pos = pci_pcie_cap(dev);
1246 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1247 return status & PCI_EXP_DEVSTA_TRPND;
1250 /* PF FLR specific routines
1252 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1255 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1256 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1257 CFC_REG_NUM_LCIDS_INSIDE_PF,
1258 "CFC PF usage counter timed out",
1263 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1265 DORQ_REG_PF_USAGE_CNT,
1266 "DQ PF usage counter timed out",
1270 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1272 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1273 "QM PF usage counter timed out",
1277 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1278 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1279 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1280 "Timers VNIC usage counter timed out",
1283 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1284 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1285 "Timers NUM_SCANS usage counter timed out",
1289 /* Wait DMAE PF usage counter to zero */
1290 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1291 dmae_reg_go_c[INIT_DMAE_C(bp)],
1292 "DMAE dommand register timed out",
1299 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1303 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1304 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1306 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1307 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1309 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1310 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1312 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1313 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1315 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1316 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1318 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1319 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1321 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1322 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1324 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1325 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1329 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1331 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1333 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1335 /* Re-enable PF target read access */
1336 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1338 /* Poll HW usage counters */
1339 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1342 /* Zero the igu 'trailing edge' and 'leading edge' */
1344 /* Send the FW cleanup command */
1345 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1350 /* Verify TX hw is flushed */
1351 bnx2x_tx_hw_flushed(bp, poll_cnt);
1353 /* Wait 100ms (not adjusted according to platform) */
1356 /* Verify no pending pci transactions */
1357 if (bnx2x_is_pcie_pending(bp->pdev))
1358 BNX2X_ERR("PCIE Transactions still pending\n");
1361 bnx2x_hw_enable_status(bp);
1364 * Master enable - Due to WB DMAE writes performed before this
1365 * register is re-initialized as part of the regular function init
1367 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1372 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1374 int port = BP_PORT(bp);
1375 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1376 u32 val = REG_RD(bp, addr);
1377 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1378 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1381 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1382 HC_CONFIG_0_REG_INT_LINE_EN_0);
1383 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1384 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1386 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1387 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1388 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1389 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1391 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1392 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1393 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1394 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1396 if (!CHIP_IS_E1(bp)) {
1397 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1400 REG_WR(bp, addr, val);
1402 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1407 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1409 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1410 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1412 REG_WR(bp, addr, val);
1414 * Ensure that HC_CONFIG is written before leading/trailing edge config
1419 if (!CHIP_IS_E1(bp)) {
1420 /* init leading/trailing edge */
1422 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1424 /* enable nig and gpio3 attention */
1429 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1430 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1433 /* Make sure that interrupts are indeed enabled from here on */
1437 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1440 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1441 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1443 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1446 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1447 IGU_PF_CONF_SINGLE_ISR_EN);
1448 val |= (IGU_PF_CONF_FUNC_EN |
1449 IGU_PF_CONF_MSI_MSIX_EN |
1450 IGU_PF_CONF_ATTN_BIT_EN);
1452 val &= ~IGU_PF_CONF_INT_LINE_EN;
1453 val |= (IGU_PF_CONF_FUNC_EN |
1454 IGU_PF_CONF_MSI_MSIX_EN |
1455 IGU_PF_CONF_ATTN_BIT_EN |
1456 IGU_PF_CONF_SINGLE_ISR_EN);
1458 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1459 val |= (IGU_PF_CONF_FUNC_EN |
1460 IGU_PF_CONF_INT_LINE_EN |
1461 IGU_PF_CONF_ATTN_BIT_EN |
1462 IGU_PF_CONF_SINGLE_ISR_EN);
1465 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1466 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1468 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1472 /* init leading/trailing edge */
1474 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1476 /* enable nig and gpio3 attention */
1481 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1482 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1484 /* Make sure that interrupts are indeed enabled from here on */
1488 void bnx2x_int_enable(struct bnx2x *bp)
1490 if (bp->common.int_block == INT_BLOCK_HC)
1491 bnx2x_hc_int_enable(bp);
1493 bnx2x_igu_int_enable(bp);
1496 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1498 int port = BP_PORT(bp);
1499 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1500 u32 val = REG_RD(bp, addr);
1503 * in E1 we must use only PCI configuration space to disable
1504 * MSI/MSIX capablility
1505 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1507 if (CHIP_IS_E1(bp)) {
1508 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1509 * Use mask register to prevent from HC sending interrupts
1510 * after we exit the function
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1514 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1515 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1516 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1518 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1519 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1520 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1521 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1523 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1526 /* flush all outstanding writes */
1529 REG_WR(bp, addr, val);
1530 if (REG_RD(bp, addr) != val)
1531 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1534 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1536 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1538 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1539 IGU_PF_CONF_INT_LINE_EN |
1540 IGU_PF_CONF_ATTN_BIT_EN);
1542 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1544 /* flush all outstanding writes */
1547 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1548 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1549 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1552 void bnx2x_int_disable(struct bnx2x *bp)
1554 if (bp->common.int_block == INT_BLOCK_HC)
1555 bnx2x_hc_int_disable(bp);
1557 bnx2x_igu_int_disable(bp);
1560 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1562 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1566 /* prevent the HW from sending interrupts */
1567 bnx2x_int_disable(bp);
1569 /* make sure all ISRs are done */
1571 synchronize_irq(bp->msix_table[0].vector);
1576 for_each_eth_queue(bp, i)
1577 synchronize_irq(bp->msix_table[offset++].vector);
1579 synchronize_irq(bp->pdev->irq);
1581 /* make sure sp_task is not running */
1582 cancel_delayed_work(&bp->sp_task);
1583 cancel_delayed_work(&bp->period_task);
1584 flush_workqueue(bnx2x_wq);
1590 * General service functions
1593 /* Return true if succeeded to acquire the lock */
1594 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1597 u32 resource_bit = (1 << resource);
1598 int func = BP_FUNC(bp);
1599 u32 hw_lock_control_reg;
1601 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1603 /* Validating that the resource is within range */
1604 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1606 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1607 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1612 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1614 hw_lock_control_reg =
1615 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1617 /* Try to acquire the lock */
1618 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1619 lock_status = REG_RD(bp, hw_lock_control_reg);
1620 if (lock_status & resource_bit)
1623 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1628 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1630 * @bp: driver handle
1632 * Returns the recovery leader resource id according to the engine this function
1633 * belongs to. Currently only only 2 engines is supported.
1635 static inline int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1638 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1640 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1644 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1646 * @bp: driver handle
1648 * Tries to aquire a leader lock for cuurent engine.
1650 static inline bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1652 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1656 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1659 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1661 struct bnx2x *bp = fp->bp;
1662 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1663 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1664 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1665 struct bnx2x_queue_sp_obj *q_obj = &fp->q_obj;
1668 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1669 fp->index, cid, command, bp->state,
1670 rr_cqe->ramrod_cqe.ramrod_type);
1673 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1674 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1675 drv_cmd = BNX2X_Q_CMD_UPDATE;
1678 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1679 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1680 drv_cmd = BNX2X_Q_CMD_SETUP;
1683 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1684 DP(NETIF_MSG_IFUP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1685 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1688 case (RAMROD_CMD_ID_ETH_HALT):
1689 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1690 drv_cmd = BNX2X_Q_CMD_HALT;
1693 case (RAMROD_CMD_ID_ETH_TERMINATE):
1694 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1695 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1698 case (RAMROD_CMD_ID_ETH_EMPTY):
1699 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1700 drv_cmd = BNX2X_Q_CMD_EMPTY;
1704 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1705 command, fp->index);
1709 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1710 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1711 /* q_obj->complete_cmd() failure means that this was
1712 * an unexpected completion.
1714 * In this case we don't want to increase the bp->spq_left
1715 * because apparently we haven't sent this command the first
1718 #ifdef BNX2X_STOP_ON_ERROR
1724 smp_mb__before_atomic_inc();
1725 atomic_inc(&bp->cq_spq_left);
1726 /* push the change in bp->spq_left and towards the memory */
1727 smp_mb__after_atomic_inc();
1729 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1734 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1735 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1737 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1739 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1743 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1745 struct bnx2x *bp = netdev_priv(dev_instance);
1746 u16 status = bnx2x_ack_int(bp);
1751 /* Return here if interrupt is shared and it's not for us */
1752 if (unlikely(status == 0)) {
1753 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1756 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1758 #ifdef BNX2X_STOP_ON_ERROR
1759 if (unlikely(bp->panic))
1763 for_each_eth_queue(bp, i) {
1764 struct bnx2x_fastpath *fp = &bp->fp[i];
1766 mask = 0x2 << (fp->index + CNIC_PRESENT);
1767 if (status & mask) {
1768 /* Handle Rx or Tx according to SB id */
1769 prefetch(fp->rx_cons_sb);
1770 for_each_cos_in_tx_queue(fp, cos)
1771 prefetch(fp->txdata[cos].tx_cons_sb);
1772 prefetch(&fp->sb_running_index[SM_RX_ID]);
1773 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1780 if (status & (mask | 0x1)) {
1781 struct cnic_ops *c_ops = NULL;
1783 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1785 c_ops = rcu_dereference(bp->cnic_ops);
1787 c_ops->cnic_handler(bp->cnic_data, NULL);
1795 if (unlikely(status & 0x1)) {
1796 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1803 if (unlikely(status))
1804 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1813 * General service functions
1816 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1819 u32 resource_bit = (1 << resource);
1820 int func = BP_FUNC(bp);
1821 u32 hw_lock_control_reg;
1824 /* Validating that the resource is within range */
1825 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1827 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1828 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1833 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1835 hw_lock_control_reg =
1836 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1839 /* Validating that the resource is not already taken */
1840 lock_status = REG_RD(bp, hw_lock_control_reg);
1841 if (lock_status & resource_bit) {
1842 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1843 lock_status, resource_bit);
1847 /* Try for 5 second every 5ms */
1848 for (cnt = 0; cnt < 1000; cnt++) {
1849 /* Try to acquire the lock */
1850 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1851 lock_status = REG_RD(bp, hw_lock_control_reg);
1852 if (lock_status & resource_bit)
1857 DP(NETIF_MSG_HW, "Timeout\n");
1861 int bnx2x_release_leader_lock(struct bnx2x *bp)
1863 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1866 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1869 u32 resource_bit = (1 << resource);
1870 int func = BP_FUNC(bp);
1871 u32 hw_lock_control_reg;
1873 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1875 /* Validating that the resource is within range */
1876 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1878 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1879 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1884 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1886 hw_lock_control_reg =
1887 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1890 /* Validating that the resource is currently taken */
1891 lock_status = REG_RD(bp, hw_lock_control_reg);
1892 if (!(lock_status & resource_bit)) {
1893 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1894 lock_status, resource_bit);
1898 REG_WR(bp, hw_lock_control_reg, resource_bit);
1903 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1905 /* The GPIO should be swapped if swap register is set and active */
1906 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1907 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1908 int gpio_shift = gpio_num +
1909 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1910 u32 gpio_mask = (1 << gpio_shift);
1914 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1915 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1919 /* read GPIO value */
1920 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1922 /* get the requested pin value */
1923 if ((gpio_reg & gpio_mask) == gpio_mask)
1928 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1933 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1935 /* The GPIO should be swapped if swap register is set and active */
1936 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1937 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1938 int gpio_shift = gpio_num +
1939 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1940 u32 gpio_mask = (1 << gpio_shift);
1943 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1944 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1948 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1949 /* read GPIO and mask except the float bits */
1950 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1953 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1954 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1955 gpio_num, gpio_shift);
1956 /* clear FLOAT and set CLR */
1957 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1961 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1962 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1963 gpio_num, gpio_shift);
1964 /* clear FLOAT and set SET */
1965 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1966 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1969 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1970 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1971 gpio_num, gpio_shift);
1973 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1980 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1981 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1986 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1991 /* Any port swapping should be handled by caller. */
1993 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1994 /* read GPIO and mask except the float bits */
1995 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1996 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1997 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1998 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2001 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2002 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2004 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2007 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2008 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2010 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2013 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2014 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2016 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2020 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2026 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2028 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2033 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2035 /* The GPIO should be swapped if swap register is set and active */
2036 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2037 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2038 int gpio_shift = gpio_num +
2039 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2040 u32 gpio_mask = (1 << gpio_shift);
2043 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2044 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2048 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2050 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2053 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2054 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
2055 "output low\n", gpio_num, gpio_shift);
2056 /* clear SET and set CLR */
2057 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2058 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2061 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2062 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
2063 "output high\n", gpio_num, gpio_shift);
2064 /* clear CLR and set SET */
2065 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2066 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2073 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2074 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2079 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2081 u32 spio_mask = (1 << spio_num);
2084 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2085 (spio_num > MISC_REGISTERS_SPIO_7)) {
2086 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2090 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2091 /* read SPIO and mask except the float bits */
2092 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2095 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2096 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
2097 /* clear FLOAT and set CLR */
2098 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2099 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2102 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2103 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
2104 /* clear FLOAT and set SET */
2105 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2106 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2109 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2110 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
2112 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2119 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2120 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2125 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2127 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2128 switch (bp->link_vars.ieee_fc &
2129 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2130 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2131 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2135 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2136 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2140 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2141 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2145 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2151 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2153 if (!BP_NOMCP(bp)) {
2155 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2156 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2158 * Initialize link parameters structure variables
2159 * It is recommended to turn off RX FC for jumbo frames
2160 * for better performance
2162 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2163 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2165 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2167 bnx2x_acquire_phy_lock(bp);
2169 if (load_mode == LOAD_DIAG) {
2170 struct link_params *lp = &bp->link_params;
2171 lp->loopback_mode = LOOPBACK_XGXS;
2172 /* do PHY loopback at 10G speed, if possible */
2173 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2174 if (lp->speed_cap_mask[cfx_idx] &
2175 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2176 lp->req_line_speed[cfx_idx] =
2179 lp->req_line_speed[cfx_idx] =
2184 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2186 bnx2x_release_phy_lock(bp);
2188 bnx2x_calc_fc_adv(bp);
2190 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2191 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2192 bnx2x_link_report(bp);
2194 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2195 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2198 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2202 void bnx2x_link_set(struct bnx2x *bp)
2204 if (!BP_NOMCP(bp)) {
2205 bnx2x_acquire_phy_lock(bp);
2206 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2207 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2208 bnx2x_release_phy_lock(bp);
2210 bnx2x_calc_fc_adv(bp);
2212 BNX2X_ERR("Bootcode is missing - can not set link\n");
2215 static void bnx2x__link_reset(struct bnx2x *bp)
2217 if (!BP_NOMCP(bp)) {
2218 bnx2x_acquire_phy_lock(bp);
2219 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2220 bnx2x_release_phy_lock(bp);
2222 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2225 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2229 if (!BP_NOMCP(bp)) {
2230 bnx2x_acquire_phy_lock(bp);
2231 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2233 bnx2x_release_phy_lock(bp);
2235 BNX2X_ERR("Bootcode is missing - can not test link\n");
2240 static void bnx2x_init_port_minmax(struct bnx2x *bp)
2242 u32 r_param = bp->link_vars.line_speed / 8;
2243 u32 fair_periodic_timeout_usec;
2246 memset(&(bp->cmng.rs_vars), 0,
2247 sizeof(struct rate_shaping_vars_per_port));
2248 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
2250 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2251 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
2253 /* this is the threshold below which no timer arming will occur
2254 1.25 coefficient is for the threshold to be a little bigger
2255 than the real time, to compensate for timer in-accuracy */
2256 bp->cmng.rs_vars.rs_threshold =
2257 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
2259 /* resolution of fairness timer */
2260 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
2261 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2262 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
2264 /* this is the threshold below which we won't arm the timer anymore */
2265 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
2267 /* we multiply by 1e3/8 to get bytes/msec.
2268 We don't want the credits to pass a credit
2269 of the t_fair*FAIR_MEM (algorithm resolution) */
2270 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
2271 /* since each tick is 4 usec */
2272 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
2275 /* Calculates the sum of vn_min_rates.
2276 It's needed for further normalizing of the min_rates.
2278 sum of vn_min_rates.
2280 0 - if all the min_rates are 0.
2281 In the later case fainess algorithm should be deactivated.
2282 If not all min_rates are zero then those that are zeroes will be set to 1.
2284 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2289 bp->vn_weight_sum = 0;
2290 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2291 u32 vn_cfg = bp->mf_config[vn];
2292 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2293 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2295 /* Skip hidden vns */
2296 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2299 /* If min rate is zero - set it to 1 */
2301 vn_min_rate = DEF_MIN_RATE;
2305 bp->vn_weight_sum += vn_min_rate;
2308 /* if ETS or all min rates are zeros - disable fairness */
2309 if (BNX2X_IS_ETS_ENABLED(bp)) {
2310 bp->cmng.flags.cmng_enables &=
2311 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2312 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2313 } else if (all_zero) {
2314 bp->cmng.flags.cmng_enables &=
2315 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2316 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2317 " fairness will be disabled\n");
2319 bp->cmng.flags.cmng_enables |=
2320 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2323 /* returns func by VN for current port */
2324 static inline int func_by_vn(struct bnx2x *bp, int vn)
2326 return 2 * vn + BP_PORT(bp);
2329 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2331 struct rate_shaping_vars_per_vn m_rs_vn;
2332 struct fairness_vars_per_vn m_fair_vn;
2333 u32 vn_cfg = bp->mf_config[vn];
2334 int func = func_by_vn(bp, vn);
2335 u16 vn_min_rate, vn_max_rate;
2338 /* If function is hidden - set min and max to zeroes */
2339 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
2344 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2346 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2347 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2348 /* If fairness is enabled (not all min rates are zeroes) and
2349 if current min rate is zero - set it to 1.
2350 This is a requirement of the algorithm. */
2351 if (bp->vn_weight_sum && (vn_min_rate == 0))
2352 vn_min_rate = DEF_MIN_RATE;
2355 /* maxCfg in percents of linkspeed */
2356 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2358 /* maxCfg is absolute in 100Mb units */
2359 vn_max_rate = maxCfg * 100;
2363 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2364 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
2366 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
2367 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
2369 /* global vn counter - maximal Mbps for this vn */
2370 m_rs_vn.vn_counter.rate = vn_max_rate;
2372 /* quota - number of bytes transmitted in this period */
2373 m_rs_vn.vn_counter.quota =
2374 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2376 if (bp->vn_weight_sum) {
2377 /* credit for each period of the fairness algorithm:
2378 number of bytes in T_FAIR (the vn share the port rate).
2379 vn_weight_sum should not be larger than 10000, thus
2380 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2382 m_fair_vn.vn_credit_delta =
2383 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2384 (8 * bp->vn_weight_sum))),
2385 (bp->cmng.fair_vars.fair_threshold +
2387 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2388 m_fair_vn.vn_credit_delta);
2391 /* Store it to internal memory */
2392 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2393 REG_WR(bp, BAR_XSTRORM_INTMEM +
2394 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2395 ((u32 *)(&m_rs_vn))[i]);
2397 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2398 REG_WR(bp, BAR_XSTRORM_INTMEM +
2399 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2400 ((u32 *)(&m_fair_vn))[i]);
2403 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2405 if (CHIP_REV_IS_SLOW(bp))
2406 return CMNG_FNS_NONE;
2408 return CMNG_FNS_MINMAX;
2410 return CMNG_FNS_NONE;
2413 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2415 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2418 return; /* what should be the default bvalue in this case */
2420 /* For 2 port configuration the absolute function number formula
2422 * abs_func = 2 * vn + BP_PORT + BP_PATH
2424 * and there are 4 functions per port
2426 * For 4 port configuration it is
2427 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2429 * and there are 2 functions per port
2431 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2432 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2434 if (func >= E1H_FUNC_MAX)
2438 MF_CFG_RD(bp, func_mf_config[func].config);
2442 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2445 if (cmng_type == CMNG_FNS_MINMAX) {
2448 /* clear cmng_enables */
2449 bp->cmng.flags.cmng_enables = 0;
2451 /* read mf conf from shmem */
2453 bnx2x_read_mf_cfg(bp);
2455 /* Init rate shaping and fairness contexts */
2456 bnx2x_init_port_minmax(bp);
2458 /* vn_weight_sum and enable fairness if not 0 */
2459 bnx2x_calc_vn_weight_sum(bp);
2461 /* calculate and set min-max rate for each vn */
2463 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2464 bnx2x_init_vn_minmax(bp, vn);
2466 /* always enable rate shaping and fairness */
2467 bp->cmng.flags.cmng_enables |=
2468 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2469 if (!bp->vn_weight_sum)
2470 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2471 " fairness will be disabled\n");
2475 /* rate shaping and fairness are disabled */
2477 "rate shaping and fairness are disabled\n");
2480 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2485 /* Set the attention towards other drivers on the same port */
2486 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2487 if (vn == BP_VN(bp))
2490 func = func_by_vn(bp, vn);
2491 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2492 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2496 /* This function is called upon link interrupt */
2497 static void bnx2x_link_attn(struct bnx2x *bp)
2499 /* Make sure that we are synced with the current statistics */
2500 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2502 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2504 if (bp->link_vars.link_up) {
2506 /* dropless flow control */
2507 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2508 int port = BP_PORT(bp);
2509 u32 pause_enabled = 0;
2511 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2514 REG_WR(bp, BAR_USTRORM_INTMEM +
2515 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2519 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2520 struct host_port_stats *pstats;
2522 pstats = bnx2x_sp(bp, port_stats);
2523 /* reset old mac stats */
2524 memset(&(pstats->mac_stx[0]), 0,
2525 sizeof(struct mac_stx));
2527 if (bp->state == BNX2X_STATE_OPEN)
2528 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2531 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2532 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2534 if (cmng_fns != CMNG_FNS_NONE) {
2535 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2536 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2538 /* rate shaping and fairness are disabled */
2540 "single function mode without fairness\n");
2543 __bnx2x_link_report(bp);
2546 bnx2x_link_sync_notify(bp);
2549 void bnx2x__link_status_update(struct bnx2x *bp)
2551 if (bp->state != BNX2X_STATE_OPEN)
2554 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2556 if (bp->link_vars.link_up)
2557 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2559 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2561 /* indicate link status */
2562 bnx2x_link_report(bp);
2565 static void bnx2x_pmf_update(struct bnx2x *bp)
2567 int port = BP_PORT(bp);
2571 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2574 * We need the mb() to ensure the ordering between the writing to
2575 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2579 /* queue a periodic task */
2580 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2582 bnx2x_dcbx_pmf_update(bp);
2584 /* enable nig attention */
2585 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2586 if (bp->common.int_block == INT_BLOCK_HC) {
2587 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2588 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2589 } else if (!CHIP_IS_E1x(bp)) {
2590 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2591 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2594 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2602 * General service functions
2605 /* send the MCP a request, block until there is a reply */
2606 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2608 int mb_idx = BP_FW_MB_IDX(bp);
2612 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2614 mutex_lock(&bp->fw_mb_mutex);
2616 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2617 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2619 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2620 (command | seq), param);
2623 /* let the FW do it's magic ... */
2626 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2628 /* Give the FW up to 5 second (500*10ms) */
2629 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2631 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2632 cnt*delay, rc, seq);
2634 /* is this a reply to our command? */
2635 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2636 rc &= FW_MSG_CODE_MASK;
2639 BNX2X_ERR("FW failed to respond!\n");
2643 mutex_unlock(&bp->fw_mb_mutex);
2648 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2651 /* Statistics are not supported for CNIC Clients at the moment */
2658 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2660 if (CHIP_IS_E1x(bp)) {
2661 struct tstorm_eth_function_common_config tcfg = {0};
2663 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2666 /* Enable the function in the FW */
2667 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2668 storm_memset_func_en(bp, p->func_id, 1);
2671 if (p->func_flgs & FUNC_FLG_SPQ) {
2672 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2673 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2674 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2679 * bnx2x_get_tx_only_flags - Return common flags
2683 * @zero_stats TRUE if statistics zeroing is needed
2685 * Return the flags that are common for the Tx-only and not normal connections.
2687 static inline unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2688 struct bnx2x_fastpath *fp,
2691 unsigned long flags = 0;
2693 /* PF driver will always initialize the Queue to an ACTIVE state */
2694 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2696 /* tx only connections collect statistics (on the same index as the
2697 * parent connection). The statistics are zeroed when the parent
2698 * connection is initialized.
2700 if (stat_counter_valid(bp, fp)) {
2701 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2703 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2709 static inline unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2710 struct bnx2x_fastpath *fp,
2713 unsigned long flags = 0;
2715 /* calculate other queue flags */
2717 __set_bit(BNX2X_Q_FLG_OV, &flags);
2720 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2722 if (!fp->disable_tpa) {
2723 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2724 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2728 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2729 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2732 /* Always set HW VLAN stripping */
2733 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2736 return flags | bnx2x_get_common_flags(bp, fp, true);
2739 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2740 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2743 gen_init->stat_id = bnx2x_stats_id(fp);
2744 gen_init->spcl_id = fp->cl_id;
2746 /* Always use mini-jumbo MTU for FCoE L2 ring */
2748 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2750 gen_init->mtu = bp->dev->mtu;
2752 gen_init->cos = cos;
2755 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2756 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2757 struct bnx2x_rxq_setup_params *rxq_init)
2761 u16 tpa_agg_size = 0;
2763 if (!fp->disable_tpa) {
2764 pause->sge_th_lo = SGE_TH_LO(bp);
2765 pause->sge_th_hi = SGE_TH_HI(bp);
2767 /* validate SGE ring has enough to cross high threshold */
2768 WARN_ON(bp->dropless_fc &&
2769 pause->sge_th_hi + FW_PREFETCH_CNT >
2770 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2772 tpa_agg_size = min_t(u32,
2773 (min_t(u32, 8, MAX_SKB_FRAGS) *
2774 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2775 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2777 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2778 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2779 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2783 /* pause - not for e1 */
2784 if (!CHIP_IS_E1(bp)) {
2785 pause->bd_th_lo = BD_TH_LO(bp);
2786 pause->bd_th_hi = BD_TH_HI(bp);
2788 pause->rcq_th_lo = RCQ_TH_LO(bp);
2789 pause->rcq_th_hi = RCQ_TH_HI(bp);
2791 * validate that rings have enough entries to cross
2794 WARN_ON(bp->dropless_fc &&
2795 pause->bd_th_hi + FW_PREFETCH_CNT >
2797 WARN_ON(bp->dropless_fc &&
2798 pause->rcq_th_hi + FW_PREFETCH_CNT >
2799 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2805 rxq_init->dscr_map = fp->rx_desc_mapping;
2806 rxq_init->sge_map = fp->rx_sge_mapping;
2807 rxq_init->rcq_map = fp->rx_comp_mapping;
2808 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2810 /* This should be a maximum number of data bytes that may be
2811 * placed on the BD (not including paddings).
2813 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN -
2814 IP_HEADER_ALIGNMENT_PADDING;
2816 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2817 rxq_init->tpa_agg_sz = tpa_agg_size;
2818 rxq_init->sge_buf_sz = sge_sz;
2819 rxq_init->max_sges_pkt = max_sge;
2820 rxq_init->rss_engine_id = BP_FUNC(bp);
2822 /* Maximum number or simultaneous TPA aggregation for this Queue.
2824 * For PF Clients it should be the maximum avaliable number.
2825 * VF driver(s) may want to define it to a smaller value.
2827 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2829 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2830 rxq_init->fw_sb_id = fp->fw_sb_id;
2833 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2835 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2838 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2839 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2842 txq_init->dscr_map = fp->txdata[cos].tx_desc_mapping;
2843 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2844 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2845 txq_init->fw_sb_id = fp->fw_sb_id;
2848 * set the tss leading client id for TX classfication ==
2849 * leading RSS client id
2851 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2853 if (IS_FCOE_FP(fp)) {
2854 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2855 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2859 static void bnx2x_pf_init(struct bnx2x *bp)
2861 struct bnx2x_func_init_params func_init = {0};
2862 struct event_ring_data eq_data = { {0} };
2865 if (!CHIP_IS_E1x(bp)) {
2866 /* reset IGU PF statistics: MSIX + ATTN */
2868 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2869 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2870 (CHIP_MODE_IS_4_PORT(bp) ?
2871 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2873 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2874 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2875 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2876 (CHIP_MODE_IS_4_PORT(bp) ?
2877 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2880 /* function setup flags */
2881 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2883 /* This flag is relevant for E1x only.
2884 * E2 doesn't have a TPA configuration in a function level.
2886 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2888 func_init.func_flgs = flags;
2889 func_init.pf_id = BP_FUNC(bp);
2890 func_init.func_id = BP_FUNC(bp);
2891 func_init.spq_map = bp->spq_mapping;
2892 func_init.spq_prod = bp->spq_prod_idx;
2894 bnx2x_func_init(bp, &func_init);
2896 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2899 * Congestion management values depend on the link rate
2900 * There is no active link so initial link rate is set to 10 Gbps.
2901 * When the link comes up The congestion management values are
2902 * re-calculated according to the actual link rate.
2904 bp->link_vars.line_speed = SPEED_10000;
2905 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2907 /* Only the PMF sets the HW */
2909 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2911 /* init Event Queue */
2912 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2913 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2914 eq_data.producer = bp->eq_prod;
2915 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2916 eq_data.sb_id = DEF_SB_ID;
2917 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2921 static void bnx2x_e1h_disable(struct bnx2x *bp)
2923 int port = BP_PORT(bp);
2925 bnx2x_tx_disable(bp);
2927 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2930 static void bnx2x_e1h_enable(struct bnx2x *bp)
2932 int port = BP_PORT(bp);
2934 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2936 /* Tx queue should be only reenabled */
2937 netif_tx_wake_all_queues(bp->dev);
2940 * Should not call netif_carrier_on since it will be called if the link
2941 * is up when checking for link state
2945 /* called due to MCP event (on pmf):
2946 * reread new bandwidth configuration
2948 * notify others function about the change
2950 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2952 if (bp->link_vars.link_up) {
2953 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2954 bnx2x_link_sync_notify(bp);
2956 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2959 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2961 bnx2x_config_mf_bw(bp);
2962 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2965 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2967 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2969 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2972 * This is the only place besides the function initialization
2973 * where the bp->flags can change so it is done without any
2976 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2977 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2978 bp->flags |= MF_FUNC_DIS;
2980 bnx2x_e1h_disable(bp);
2982 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2983 bp->flags &= ~MF_FUNC_DIS;
2985 bnx2x_e1h_enable(bp);
2987 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2989 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2990 bnx2x_config_mf_bw(bp);
2991 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2994 /* Report results to MCP */
2996 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2998 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3001 /* must be called under the spq lock */
3002 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3004 struct eth_spe *next_spe = bp->spq_prod_bd;
3006 if (bp->spq_prod_bd == bp->spq_last_bd) {
3007 bp->spq_prod_bd = bp->spq;
3008 bp->spq_prod_idx = 0;
3009 DP(NETIF_MSG_TIMER, "end of spq\n");
3017 /* must be called under the spq lock */
3018 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
3020 int func = BP_FUNC(bp);
3023 * Make sure that BD data is updated before writing the producer:
3024 * BD data is written to the memory, the producer is read from the
3025 * memory, thus we need a full memory barrier to ensure the ordering.
3029 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3035 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3037 * @cmd: command to check
3038 * @cmd_type: command type
3040 static inline bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3042 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3043 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3044 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3045 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3046 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3047 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3048 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3057 * bnx2x_sp_post - place a single command on an SP ring
3059 * @bp: driver handle
3060 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3061 * @cid: SW CID the command is related to
3062 * @data_hi: command private data address (high 32 bits)
3063 * @data_lo: command private data address (low 32 bits)
3064 * @cmd_type: command type (e.g. NONE, ETH)
3066 * SP data is handled as if it's always an address pair, thus data fields are
3067 * not swapped to little endian in upper functions. Instead this function swaps
3068 * data as if it's two u32 fields.
3070 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3071 u32 data_hi, u32 data_lo, int cmd_type)
3073 struct eth_spe *spe;
3075 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3077 #ifdef BNX2X_STOP_ON_ERROR
3078 if (unlikely(bp->panic))
3082 spin_lock_bh(&bp->spq_lock);
3085 if (!atomic_read(&bp->eq_spq_left)) {
3086 BNX2X_ERR("BUG! EQ ring full!\n");
3087 spin_unlock_bh(&bp->spq_lock);
3091 } else if (!atomic_read(&bp->cq_spq_left)) {
3092 BNX2X_ERR("BUG! SPQ ring full!\n");
3093 spin_unlock_bh(&bp->spq_lock);
3098 spe = bnx2x_sp_get_next(bp);
3100 /* CID needs port number to be encoded int it */
3101 spe->hdr.conn_and_cmd_data =
3102 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3105 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3107 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3108 SPE_HDR_FUNCTION_ID);
3110 spe->hdr.type = cpu_to_le16(type);
3112 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3113 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3116 * It's ok if the actual decrement is issued towards the memory
3117 * somewhere between the spin_lock and spin_unlock. Thus no
3118 * more explict memory barrier is needed.
3121 atomic_dec(&bp->eq_spq_left);
3123 atomic_dec(&bp->cq_spq_left);
3126 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
3127 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) "
3128 "type(0x%x) left (CQ, EQ) (%x,%x)\n",
3129 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3130 (u32)(U64_LO(bp->spq_mapping) +
3131 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3132 HW_CID(bp, cid), data_hi, data_lo, type,
3133 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3135 bnx2x_sp_prod_update(bp);
3136 spin_unlock_bh(&bp->spq_lock);
3140 /* acquire split MCP access lock register */
3141 static int bnx2x_acquire_alr(struct bnx2x *bp)
3147 for (j = 0; j < 1000; j++) {
3149 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3150 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3151 if (val & (1L << 31))
3156 if (!(val & (1L << 31))) {
3157 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3164 /* release split MCP access lock register */
3165 static void bnx2x_release_alr(struct bnx2x *bp)
3167 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3170 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3171 #define BNX2X_DEF_SB_IDX 0x0002
3173 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3175 struct host_sp_status_block *def_sb = bp->def_status_blk;
3178 barrier(); /* status block is written to by the chip */
3179 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3180 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3181 rc |= BNX2X_DEF_SB_ATT_IDX;
3184 if (bp->def_idx != def_sb->sp_sb.running_index) {
3185 bp->def_idx = def_sb->sp_sb.running_index;
3186 rc |= BNX2X_DEF_SB_IDX;
3189 /* Do not reorder: indecies reading should complete before handling */
3195 * slow path service functions
3198 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3200 int port = BP_PORT(bp);
3201 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3202 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3203 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3204 NIG_REG_MASK_INTERRUPT_PORT0;
3209 if (bp->attn_state & asserted)
3210 BNX2X_ERR("IGU ERROR\n");
3212 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3213 aeu_mask = REG_RD(bp, aeu_addr);
3215 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3216 aeu_mask, asserted);
3217 aeu_mask &= ~(asserted & 0x3ff);
3218 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3220 REG_WR(bp, aeu_addr, aeu_mask);
3221 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3223 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3224 bp->attn_state |= asserted;
3225 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3227 if (asserted & ATTN_HARD_WIRED_MASK) {
3228 if (asserted & ATTN_NIG_FOR_FUNC) {
3230 bnx2x_acquire_phy_lock(bp);
3232 /* save nig interrupt mask */
3233 nig_mask = REG_RD(bp, nig_int_mask_addr);
3235 /* If nig_mask is not set, no need to call the update
3239 REG_WR(bp, nig_int_mask_addr, 0);
3241 bnx2x_link_attn(bp);
3244 /* handle unicore attn? */
3246 if (asserted & ATTN_SW_TIMER_4_FUNC)
3247 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3249 if (asserted & GPIO_2_FUNC)
3250 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3252 if (asserted & GPIO_3_FUNC)
3253 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3255 if (asserted & GPIO_4_FUNC)
3256 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3259 if (asserted & ATTN_GENERAL_ATTN_1) {
3260 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3263 if (asserted & ATTN_GENERAL_ATTN_2) {
3264 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3265 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3267 if (asserted & ATTN_GENERAL_ATTN_3) {
3268 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3269 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3272 if (asserted & ATTN_GENERAL_ATTN_4) {
3273 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3274 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3276 if (asserted & ATTN_GENERAL_ATTN_5) {
3277 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3278 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3280 if (asserted & ATTN_GENERAL_ATTN_6) {
3281 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3282 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3286 } /* if hardwired */
3288 if (bp->common.int_block == INT_BLOCK_HC)
3289 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3290 COMMAND_REG_ATTN_BITS_SET);
3292 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3294 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3295 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3296 REG_WR(bp, reg_addr, asserted);
3298 /* now set back the mask */
3299 if (asserted & ATTN_NIG_FOR_FUNC) {
3300 REG_WR(bp, nig_int_mask_addr, nig_mask);
3301 bnx2x_release_phy_lock(bp);
3305 static inline void bnx2x_fan_failure(struct bnx2x *bp)
3307 int port = BP_PORT(bp);
3309 /* mark the failure */
3312 dev_info.port_hw_config[port].external_phy_config);
3314 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3315 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3316 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3319 /* log the failure */
3320 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
3321 " the driver to shutdown the card to prevent permanent"
3322 " damage. Please contact OEM Support for assistance\n");
3325 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3327 int port = BP_PORT(bp);
3331 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3332 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3334 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3336 val = REG_RD(bp, reg_offset);
3337 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3338 REG_WR(bp, reg_offset, val);
3340 BNX2X_ERR("SPIO5 hw attention\n");
3342 /* Fan failure attention */
3343 bnx2x_hw_reset_phy(&bp->link_params);
3344 bnx2x_fan_failure(bp);
3347 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3348 bnx2x_acquire_phy_lock(bp);
3349 bnx2x_handle_module_detect_int(&bp->link_params);
3350 bnx2x_release_phy_lock(bp);
3353 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3355 val = REG_RD(bp, reg_offset);
3356 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3357 REG_WR(bp, reg_offset, val);
3359 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3360 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3365 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3369 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3371 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3372 BNX2X_ERR("DB hw attention 0x%x\n", val);
3373 /* DORQ discard attention */
3375 BNX2X_ERR("FATAL error from DORQ\n");
3378 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3380 int port = BP_PORT(bp);
3383 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3384 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3386 val = REG_RD(bp, reg_offset);
3387 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3388 REG_WR(bp, reg_offset, val);
3390 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3391 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3396 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3400 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3402 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3403 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3404 /* CFC error attention */
3406 BNX2X_ERR("FATAL error from CFC\n");
3409 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3410 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3411 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3412 /* RQ_USDMDP_FIFO_OVERFLOW */
3414 BNX2X_ERR("FATAL error from PXP\n");
3416 if (!CHIP_IS_E1x(bp)) {
3417 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3418 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3422 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3424 int port = BP_PORT(bp);
3427 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3428 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3430 val = REG_RD(bp, reg_offset);
3431 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3432 REG_WR(bp, reg_offset, val);
3434 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3435 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3440 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3444 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3446 if (attn & BNX2X_PMF_LINK_ASSERT) {
3447 int func = BP_FUNC(bp);
3449 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3450 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3451 func_mf_config[BP_ABS_FUNC(bp)].config);
3453 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3454 if (val & DRV_STATUS_DCC_EVENT_MASK)
3456 (val & DRV_STATUS_DCC_EVENT_MASK));
3458 if (val & DRV_STATUS_SET_MF_BW)
3459 bnx2x_set_mf_bw(bp);
3461 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3462 bnx2x_pmf_update(bp);
3465 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3466 bp->dcbx_enabled > 0)
3467 /* start dcbx state machine */
3468 bnx2x_dcbx_set_params(bp,
3469 BNX2X_DCBX_STATE_NEG_RECEIVED);
3470 if (bp->link_vars.periodic_flags &
3471 PERIODIC_FLAGS_LINK_EVENT) {
3472 /* sync with link */
3473 bnx2x_acquire_phy_lock(bp);
3474 bp->link_vars.periodic_flags &=
3475 ~PERIODIC_FLAGS_LINK_EVENT;
3476 bnx2x_release_phy_lock(bp);
3478 bnx2x_link_sync_notify(bp);
3479 bnx2x_link_report(bp);
3481 /* Always call it here: bnx2x_link_report() will
3482 * prevent the link indication duplication.
3484 bnx2x__link_status_update(bp);
3485 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3487 BNX2X_ERR("MC assert!\n");
3488 bnx2x_mc_assert(bp);
3489 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3490 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3491 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3492 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3495 } else if (attn & BNX2X_MCP_ASSERT) {
3497 BNX2X_ERR("MCP assert!\n");
3498 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3502 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3505 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3506 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3507 if (attn & BNX2X_GRC_TIMEOUT) {
3508 val = CHIP_IS_E1(bp) ? 0 :
3509 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3510 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3512 if (attn & BNX2X_GRC_RSV) {
3513 val = CHIP_IS_E1(bp) ? 0 :
3514 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3515 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3517 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3523 * 0-7 - Engine0 load counter.
3524 * 8-15 - Engine1 load counter.
3525 * 16 - Engine0 RESET_IN_PROGRESS bit.
3526 * 17 - Engine1 RESET_IN_PROGRESS bit.
3527 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3529 * 19 - Engine1 ONE_IS_LOADED.
3530 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3531 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3532 * just the one belonging to its engine).
3535 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3537 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3538 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3539 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3540 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3541 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3542 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3543 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3546 * Set the GLOBAL_RESET bit.
3548 * Should be run under rtnl lock
3550 void bnx2x_set_reset_global(struct bnx2x *bp)
3552 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3554 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3560 * Clear the GLOBAL_RESET bit.
3562 * Should be run under rtnl lock
3564 static inline void bnx2x_clear_reset_global(struct bnx2x *bp)
3566 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3568 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3574 * Checks the GLOBAL_RESET bit.
3576 * should be run under rtnl lock
3578 static inline bool bnx2x_reset_is_global(struct bnx2x *bp)
3580 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3582 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3583 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3587 * Clear RESET_IN_PROGRESS bit for the current engine.
3589 * Should be run under rtnl lock
3591 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3593 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3594 u32 bit = BP_PATH(bp) ?
3595 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3599 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3605 * Set RESET_IN_PROGRESS for the current engine.
3607 * should be run under rtnl lock
3609 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3611 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3612 u32 bit = BP_PATH(bp) ?
3613 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3617 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3623 * Checks the RESET_IN_PROGRESS bit for the given engine.
3624 * should be run under rtnl lock
3626 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3628 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3630 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3632 /* return false if bit is set */
3633 return (val & bit) ? false : true;
3637 * Increment the load counter for the current engine.
3639 * should be run under rtnl lock
3641 void bnx2x_inc_load_cnt(struct bnx2x *bp)
3643 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3644 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3645 BNX2X_PATH0_LOAD_CNT_MASK;
3646 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3647 BNX2X_PATH0_LOAD_CNT_SHIFT;
3649 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3651 /* get the current counter value */
3652 val1 = (val & mask) >> shift;
3657 /* clear the old value */
3660 /* set the new one */
3661 val |= ((val1 << shift) & mask);
3663 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3669 * bnx2x_dec_load_cnt - decrement the load counter
3671 * @bp: driver handle
3673 * Should be run under rtnl lock.
3674 * Decrements the load counter for the current engine. Returns
3675 * the new counter value.
3677 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3679 u32 val1, val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3680 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3681 BNX2X_PATH0_LOAD_CNT_MASK;
3682 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3683 BNX2X_PATH0_LOAD_CNT_SHIFT;
3685 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3687 /* get the current counter value */
3688 val1 = (val & mask) >> shift;
3693 /* clear the old value */
3696 /* set the new one */
3697 val |= ((val1 << shift) & mask);
3699 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3707 * Read the load counter for the current engine.
3709 * should be run under rtnl lock
3711 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp, int engine)
3713 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
3714 BNX2X_PATH0_LOAD_CNT_MASK);
3715 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3716 BNX2X_PATH0_LOAD_CNT_SHIFT);
3717 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3719 DP(NETIF_MSG_HW, "GLOB_REG=0x%08x\n", val);
3721 val = (val & mask) >> shift;
3723 DP(NETIF_MSG_HW, "load_cnt for engine %d = %d\n", engine, val);
3729 * Reset the load counter for the current engine.
3731 * should be run under rtnl lock
3733 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3735 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3736 u32 mask = (BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3737 BNX2X_PATH0_LOAD_CNT_MASK);
3739 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~mask));
3742 static inline void _print_next_block(int idx, const char *blk)
3749 static inline int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
3754 for (i = 0; sig; i++) {
3755 cur_bit = ((u32)0x1 << i);
3756 if (sig & cur_bit) {
3758 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3760 _print_next_block(par_num++, "BRB");
3762 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3764 _print_next_block(par_num++, "PARSER");
3766 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3768 _print_next_block(par_num++, "TSDM");
3770 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3772 _print_next_block(par_num++,
3775 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
3777 _print_next_block(par_num++, "TCM");
3779 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3781 _print_next_block(par_num++, "TSEMI");
3783 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3785 _print_next_block(par_num++, "XPB");
3797 static inline int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
3798 bool *global, bool print)
3802 for (i = 0; sig; i++) {
3803 cur_bit = ((u32)0x1 << i);
3804 if (sig & cur_bit) {
3806 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
3808 _print_next_block(par_num++, "PBF");
3810 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3812 _print_next_block(par_num++, "QM");
3814 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
3816 _print_next_block(par_num++, "TM");
3818 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3820 _print_next_block(par_num++, "XSDM");
3822 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
3824 _print_next_block(par_num++, "XCM");
3826 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3828 _print_next_block(par_num++, "XSEMI");
3830 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3832 _print_next_block(par_num++,
3835 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
3837 _print_next_block(par_num++, "NIG");
3839 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3841 _print_next_block(par_num++,
3845 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3847 _print_next_block(par_num++, "DEBUG");
3849 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3851 _print_next_block(par_num++, "USDM");
3853 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
3855 _print_next_block(par_num++, "UCM");
3857 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3859 _print_next_block(par_num++, "USEMI");
3861 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3863 _print_next_block(par_num++, "UPB");
3865 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3867 _print_next_block(par_num++, "CSDM");
3869 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
3871 _print_next_block(par_num++, "CCM");
3883 static inline int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
3888 for (i = 0; sig; i++) {
3889 cur_bit = ((u32)0x1 << i);
3890 if (sig & cur_bit) {
3892 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3894 _print_next_block(par_num++, "CSEMI");
3896 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3898 _print_next_block(par_num++, "PXP");
3900 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3902 _print_next_block(par_num++,
3903 "PXPPCICLOCKCLIENT");
3905 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3907 _print_next_block(par_num++, "CFC");
3909 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3911 _print_next_block(par_num++, "CDU");
3913 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
3915 _print_next_block(par_num++, "DMAE");
3917 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3919 _print_next_block(par_num++, "IGU");
3921 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3923 _print_next_block(par_num++, "MISC");
3935 static inline int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
3936 bool *global, bool print)
3940 for (i = 0; sig; i++) {
3941 cur_bit = ((u32)0x1 << i);
3942 if (sig & cur_bit) {
3944 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3946 _print_next_block(par_num++, "MCP ROM");
3949 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3951 _print_next_block(par_num++,
3955 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3957 _print_next_block(par_num++,
3961 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3963 _print_next_block(par_num++,
3977 static inline int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
3982 for (i = 0; sig; i++) {
3983 cur_bit = ((u32)0x1 << i);
3984 if (sig & cur_bit) {
3986 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
3988 _print_next_block(par_num++, "PGLUE_B");
3990 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
3992 _print_next_block(par_num++, "ATC");
4004 static inline bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4007 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4008 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4009 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4010 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4011 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4013 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
4014 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x "
4016 sig[0] & HW_PRTY_ASSERT_SET_0,
4017 sig[1] & HW_PRTY_ASSERT_SET_1,
4018 sig[2] & HW_PRTY_ASSERT_SET_2,
4019 sig[3] & HW_PRTY_ASSERT_SET_3,
4020 sig[4] & HW_PRTY_ASSERT_SET_4);
4023 "Parity errors detected in blocks: ");
4024 par_num = bnx2x_check_blocks_with_parity0(
4025 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4026 par_num = bnx2x_check_blocks_with_parity1(
4027 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4028 par_num = bnx2x_check_blocks_with_parity2(
4029 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4030 par_num = bnx2x_check_blocks_with_parity3(
4031 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4032 par_num = bnx2x_check_blocks_with_parity4(
4033 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4044 * bnx2x_chk_parity_attn - checks for parity attentions.
4046 * @bp: driver handle
4047 * @global: true if there was a global attention
4048 * @print: show parity attention in syslog
4050 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4052 struct attn_route attn = { {0} };
4053 int port = BP_PORT(bp);
4055 attn.sig[0] = REG_RD(bp,
4056 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4058 attn.sig[1] = REG_RD(bp,
4059 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4061 attn.sig[2] = REG_RD(bp,
4062 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4064 attn.sig[3] = REG_RD(bp,
4065 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4068 if (!CHIP_IS_E1x(bp))
4069 attn.sig[4] = REG_RD(bp,
4070 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4073 return bnx2x_parity_attn(bp, global, print, attn.sig);
4077 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4080 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4082 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4083 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4084 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4085 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4087 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4088 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4089 "INCORRECT_RCV_BEHAVIOR\n");
4090 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4091 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4092 "WAS_ERROR_ATTN\n");
4093 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4094 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4095 "VF_LENGTH_VIOLATION_ATTN\n");
4097 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4098 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4099 "VF_GRC_SPACE_VIOLATION_ATTN\n");
4101 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4102 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4103 "VF_MSIX_BAR_VIOLATION_ATTN\n");
4104 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4105 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4106 "TCPL_ERROR_ATTN\n");
4107 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4108 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4109 "TCPL_IN_TWO_RCBS_ATTN\n");
4110 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4111 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
4112 "CSSNOOP_FIFO_OVERFLOW\n");
4114 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4115 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4116 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4117 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4118 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4119 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4120 BNX2X_ERR("ATC_ATC_INT_STS_REG"
4121 "_ATC_TCPL_TO_NOT_PEND\n");
4122 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4123 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4124 "ATC_GPA_MULTIPLE_HITS\n");
4125 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4126 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4127 "ATC_RCPL_TO_EMPTY_CNT\n");
4128 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4129 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4130 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4131 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
4132 "ATC_IREQ_LESS_THAN_STU\n");
4135 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4136 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4137 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4138 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4139 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4144 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4146 struct attn_route attn, *group_mask;
4147 int port = BP_PORT(bp);
4152 bool global = false;
4154 /* need to take HW lock because MCP or other port might also
4155 try to handle this event */
4156 bnx2x_acquire_alr(bp);
4158 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4159 #ifndef BNX2X_STOP_ON_ERROR
4160 bp->recovery_state = BNX2X_RECOVERY_INIT;
4161 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4162 /* Disable HW interrupts */
4163 bnx2x_int_disable(bp);
4164 /* In case of parity errors don't handle attentions so that
4165 * other function would "see" parity errors.
4170 bnx2x_release_alr(bp);
4174 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4175 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4176 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4177 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4178 if (!CHIP_IS_E1x(bp))
4180 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4184 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4185 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4187 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4188 if (deasserted & (1 << index)) {
4189 group_mask = &bp->attn_group[index];
4191 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
4194 group_mask->sig[0], group_mask->sig[1],
4195 group_mask->sig[2], group_mask->sig[3],
4196 group_mask->sig[4]);
4198 bnx2x_attn_int_deasserted4(bp,
4199 attn.sig[4] & group_mask->sig[4]);
4200 bnx2x_attn_int_deasserted3(bp,
4201 attn.sig[3] & group_mask->sig[3]);
4202 bnx2x_attn_int_deasserted1(bp,
4203 attn.sig[1] & group_mask->sig[1]);
4204 bnx2x_attn_int_deasserted2(bp,
4205 attn.sig[2] & group_mask->sig[2]);
4206 bnx2x_attn_int_deasserted0(bp,
4207 attn.sig[0] & group_mask->sig[0]);
4211 bnx2x_release_alr(bp);
4213 if (bp->common.int_block == INT_BLOCK_HC)
4214 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4215 COMMAND_REG_ATTN_BITS_CLR);
4217 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4220 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4221 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4222 REG_WR(bp, reg_addr, val);
4224 if (~bp->attn_state & deasserted)
4225 BNX2X_ERR("IGU ERROR\n");
4227 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4228 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4230 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4231 aeu_mask = REG_RD(bp, reg_addr);
4233 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4234 aeu_mask, deasserted);
4235 aeu_mask |= (deasserted & 0x3ff);
4236 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4238 REG_WR(bp, reg_addr, aeu_mask);
4239 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4241 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4242 bp->attn_state &= ~deasserted;
4243 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4246 static void bnx2x_attn_int(struct bnx2x *bp)
4248 /* read local copy of bits */
4249 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4251 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4253 u32 attn_state = bp->attn_state;
4255 /* look for changed bits */
4256 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4257 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4260 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4261 attn_bits, attn_ack, asserted, deasserted);
4263 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4264 BNX2X_ERR("BAD attention state\n");
4266 /* handle bits that were raised */
4268 bnx2x_attn_int_asserted(bp, asserted);
4271 bnx2x_attn_int_deasserted(bp, deasserted);
4274 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4275 u16 index, u8 op, u8 update)
4277 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4279 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4283 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4285 /* No memory barriers */
4286 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4287 mmiowb(); /* keep prod updates ordered */
4291 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4292 union event_ring_elem *elem)
4294 u8 err = elem->message.error;
4296 if (!bp->cnic_eth_dev.starting_cid ||
4297 (cid < bp->cnic_eth_dev.starting_cid &&
4298 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4301 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4303 if (unlikely(err)) {
4305 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4307 bnx2x_panic_dump(bp);
4309 bnx2x_cnic_cfc_comp(bp, cid, err);
4314 static inline void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4316 struct bnx2x_mcast_ramrod_params rparam;
4319 memset(&rparam, 0, sizeof(rparam));
4321 rparam.mcast_obj = &bp->mcast_obj;
4323 netif_addr_lock_bh(bp->dev);
4325 /* Clear pending state for the last command */
4326 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4328 /* If there are pending mcast commands - send them */
4329 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4330 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4332 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4336 netif_addr_unlock_bh(bp->dev);
4339 static inline void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4340 union event_ring_elem *elem)
4342 unsigned long ramrod_flags = 0;
4344 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4345 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4347 /* Always push next commands out, don't wait here */
4348 __set_bit(RAMROD_CONT, &ramrod_flags);
4350 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4351 case BNX2X_FILTER_MAC_PENDING:
4353 if (cid == BNX2X_ISCSI_ETH_CID)
4354 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4357 vlan_mac_obj = &bp->fp[cid].mac_obj;
4360 vlan_mac_obj = &bp->fp[cid].mac_obj;
4362 case BNX2X_FILTER_MCAST_PENDING:
4363 /* This is only relevant for 57710 where multicast MACs are
4364 * configured as unicast MACs using the same ramrod.
4366 bnx2x_handle_mcast_eqe(bp);
4369 BNX2X_ERR("Unsupported classification command: %d\n",
4370 elem->message.data.eth_event.echo);
4374 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4377 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4379 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4384 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4387 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4389 netif_addr_lock_bh(bp->dev);
4391 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4393 /* Send rx_mode command again if was requested */
4394 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4395 bnx2x_set_storm_rx_mode(bp);
4397 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4399 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4400 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4402 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4405 netif_addr_unlock_bh(bp->dev);
4408 static inline struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4409 struct bnx2x *bp, u32 cid)
4411 DP(BNX2X_MSG_SP, "retrieving fp from cid %d", cid);
4413 if (cid == BNX2X_FCOE_ETH_CID)
4414 return &bnx2x_fcoe(bp, q_obj);
4417 return &bnx2x_fp(bp, CID_TO_FP(cid), q_obj);
4420 static void bnx2x_eq_int(struct bnx2x *bp)
4422 u16 hw_cons, sw_cons, sw_prod;
4423 union event_ring_elem *elem;
4427 struct bnx2x_queue_sp_obj *q_obj;
4428 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4429 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4431 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4433 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4434 * when we get the the next-page we nned to adjust so the loop
4435 * condition below will be met. The next element is the size of a
4436 * regular element and hence incrementing by 1
4438 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4441 /* This function may never run in parallel with itself for a
4442 * specific bp, thus there is no need in "paired" read memory
4445 sw_cons = bp->eq_cons;
4446 sw_prod = bp->eq_prod;
4448 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4449 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4451 for (; sw_cons != hw_cons;
4452 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4455 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4457 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4458 opcode = elem->message.opcode;
4461 /* handle eq element */
4463 case EVENT_RING_OPCODE_STAT_QUERY:
4464 DP(NETIF_MSG_TIMER, "got statistics comp event %d\n",
4466 /* nothing to do with stats comp */
4469 case EVENT_RING_OPCODE_CFC_DEL:
4470 /* handle according to cid range */
4472 * we may want to verify here that the bp state is
4476 "got delete ramrod for MULTI[%d]\n", cid);
4478 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4481 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4483 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4490 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4491 DP(BNX2X_MSG_SP, "got STOP TRAFFIC\n");
4492 if (f_obj->complete_cmd(bp, f_obj,
4493 BNX2X_F_CMD_TX_STOP))
4495 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4498 case EVENT_RING_OPCODE_START_TRAFFIC:
4499 DP(BNX2X_MSG_SP, "got START TRAFFIC\n");
4500 if (f_obj->complete_cmd(bp, f_obj,
4501 BNX2X_F_CMD_TX_START))
4503 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4505 case EVENT_RING_OPCODE_FUNCTION_START:
4506 DP(BNX2X_MSG_SP, "got FUNC_START ramrod\n");
4507 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4512 case EVENT_RING_OPCODE_FUNCTION_STOP:
4513 DP(BNX2X_MSG_SP, "got FUNC_STOP ramrod\n");
4514 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4520 switch (opcode | bp->state) {
4521 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4523 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4524 BNX2X_STATE_OPENING_WAIT4_PORT):
4525 cid = elem->message.data.eth_event.echo &
4527 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4529 rss_raw->clear_pending(rss_raw);
4532 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4533 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4534 case (EVENT_RING_OPCODE_SET_MAC |
4535 BNX2X_STATE_CLOSING_WAIT4_HALT):
4536 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4538 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4540 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4541 BNX2X_STATE_CLOSING_WAIT4_HALT):
4542 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4543 bnx2x_handle_classification_eqe(bp, elem);
4546 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4548 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4550 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4551 BNX2X_STATE_CLOSING_WAIT4_HALT):
4552 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4553 bnx2x_handle_mcast_eqe(bp);
4556 case (EVENT_RING_OPCODE_FILTERS_RULES |
4558 case (EVENT_RING_OPCODE_FILTERS_RULES |
4560 case (EVENT_RING_OPCODE_FILTERS_RULES |
4561 BNX2X_STATE_CLOSING_WAIT4_HALT):
4562 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4563 bnx2x_handle_rx_mode_eqe(bp);
4566 /* unknown event log error and continue */
4567 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4568 elem->message.opcode, bp->state);
4574 smp_mb__before_atomic_inc();
4575 atomic_add(spqe_cnt, &bp->eq_spq_left);
4577 bp->eq_cons = sw_cons;
4578 bp->eq_prod = sw_prod;
4579 /* Make sure that above mem writes were issued towards the memory */
4582 /* update producer */
4583 bnx2x_update_eq_prod(bp, bp->eq_prod);
4586 static void bnx2x_sp_task(struct work_struct *work)
4588 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4591 status = bnx2x_update_dsb_idx(bp);
4592 /* if (status == 0) */
4593 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4595 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
4598 if (status & BNX2X_DEF_SB_ATT_IDX) {
4600 status &= ~BNX2X_DEF_SB_ATT_IDX;
4603 /* SP events: STAT_QUERY and others */
4604 if (status & BNX2X_DEF_SB_IDX) {
4606 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
4608 if ((!NO_FCOE(bp)) &&
4609 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
4611 * Prevent local bottom-halves from running as
4612 * we are going to change the local NAPI list.
4615 napi_schedule(&bnx2x_fcoe(bp, napi));
4619 /* Handle EQ completions */
4622 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
4623 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
4625 status &= ~BNX2X_DEF_SB_IDX;
4628 if (unlikely(status))
4629 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
4632 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
4633 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
4636 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
4638 struct net_device *dev = dev_instance;
4639 struct bnx2x *bp = netdev_priv(dev);
4641 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
4642 IGU_INT_DISABLE, 0);
4644 #ifdef BNX2X_STOP_ON_ERROR
4645 if (unlikely(bp->panic))
4651 struct cnic_ops *c_ops;
4654 c_ops = rcu_dereference(bp->cnic_ops);
4656 c_ops->cnic_handler(bp->cnic_data, NULL);
4660 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
4665 /* end of slow path */
4668 void bnx2x_drv_pulse(struct bnx2x *bp)
4670 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
4671 bp->fw_drv_pulse_wr_seq);
4675 static void bnx2x_timer(unsigned long data)
4678 struct bnx2x *bp = (struct bnx2x *) data;
4680 if (!netif_running(bp->dev))
4684 struct bnx2x_fastpath *fp = &bp->fp[0];
4686 for_each_cos_in_tx_queue(fp, cos)
4687 bnx2x_tx_int(bp, &fp->txdata[cos]);
4688 bnx2x_rx_int(fp, 1000);
4691 if (!BP_NOMCP(bp)) {
4692 int mb_idx = BP_FW_MB_IDX(bp);
4696 ++bp->fw_drv_pulse_wr_seq;
4697 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
4698 /* TBD - add SYSTEM_TIME */
4699 drv_pulse = bp->fw_drv_pulse_wr_seq;
4700 bnx2x_drv_pulse(bp);
4702 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
4703 MCP_PULSE_SEQ_MASK);
4704 /* The delta between driver pulse and mcp response
4705 * should be 1 (before mcp response) or 0 (after mcp response)
4707 if ((drv_pulse != mcp_pulse) &&
4708 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
4709 /* someone lost a heartbeat... */
4710 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4711 drv_pulse, mcp_pulse);
4715 if (bp->state == BNX2X_STATE_OPEN)
4716 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
4718 mod_timer(&bp->timer, jiffies + bp->current_interval);
4721 /* end of Statistics */
4726 * nic init service functions
4729 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
4732 if (!(len%4) && !(addr%4))
4733 for (i = 0; i < len; i += 4)
4734 REG_WR(bp, addr + i, fill);
4736 for (i = 0; i < len; i++)
4737 REG_WR8(bp, addr + i, fill);
4741 /* helper: writes FP SP data to FW - data_size in dwords */
4742 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
4748 for (index = 0; index < data_size; index++)
4749 REG_WR(bp, BAR_CSTRORM_INTMEM +
4750 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
4752 *(sb_data_p + index));
4755 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
4759 struct hc_status_block_data_e2 sb_data_e2;
4760 struct hc_status_block_data_e1x sb_data_e1x;
4762 /* disable the function first */
4763 if (!CHIP_IS_E1x(bp)) {
4764 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4765 sb_data_e2.common.state = SB_DISABLED;
4766 sb_data_e2.common.p_func.vf_valid = false;
4767 sb_data_p = (u32 *)&sb_data_e2;
4768 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4770 memset(&sb_data_e1x, 0,
4771 sizeof(struct hc_status_block_data_e1x));
4772 sb_data_e1x.common.state = SB_DISABLED;
4773 sb_data_e1x.common.p_func.vf_valid = false;
4774 sb_data_p = (u32 *)&sb_data_e1x;
4775 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4777 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4779 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4780 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4781 CSTORM_STATUS_BLOCK_SIZE);
4782 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4783 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4784 CSTORM_SYNC_BLOCK_SIZE);
4787 /* helper: writes SP SB data to FW */
4788 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4789 struct hc_sp_status_block_data *sp_sb_data)
4791 int func = BP_FUNC(bp);
4793 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4794 REG_WR(bp, BAR_CSTRORM_INTMEM +
4795 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4797 *((u32 *)sp_sb_data + i));
4800 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4802 int func = BP_FUNC(bp);
4803 struct hc_sp_status_block_data sp_sb_data;
4804 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4806 sp_sb_data.state = SB_DISABLED;
4807 sp_sb_data.p_func.vf_valid = false;
4809 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4811 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4812 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4813 CSTORM_SP_STATUS_BLOCK_SIZE);
4814 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4815 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4816 CSTORM_SP_SYNC_BLOCK_SIZE);
4822 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4823 int igu_sb_id, int igu_seg_id)
4825 hc_sm->igu_sb_id = igu_sb_id;
4826 hc_sm->igu_seg_id = igu_seg_id;
4827 hc_sm->timer_value = 0xFF;
4828 hc_sm->time_to_expire = 0xFFFFFFFF;
4832 /* allocates state machine ids. */
4834 void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
4836 /* zero out state machine indices */
4838 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4841 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
4842 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
4843 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
4844 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
4848 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
4849 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4852 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
4853 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4854 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
4855 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4856 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
4857 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4858 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
4859 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
4862 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4863 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4867 struct hc_status_block_data_e2 sb_data_e2;
4868 struct hc_status_block_data_e1x sb_data_e1x;
4869 struct hc_status_block_sm *hc_sm_p;
4873 if (CHIP_INT_MODE_IS_BC(bp))
4874 igu_seg_id = HC_SEG_ACCESS_NORM;
4876 igu_seg_id = IGU_SEG_ACCESS_NORM;
4878 bnx2x_zero_fp_sb(bp, fw_sb_id);
4880 if (!CHIP_IS_E1x(bp)) {
4881 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4882 sb_data_e2.common.state = SB_ENABLED;
4883 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4884 sb_data_e2.common.p_func.vf_id = vfid;
4885 sb_data_e2.common.p_func.vf_valid = vf_valid;
4886 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4887 sb_data_e2.common.same_igu_sb_1b = true;
4888 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4889 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4890 hc_sm_p = sb_data_e2.common.state_machine;
4891 sb_data_p = (u32 *)&sb_data_e2;
4892 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4893 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
4895 memset(&sb_data_e1x, 0,
4896 sizeof(struct hc_status_block_data_e1x));
4897 sb_data_e1x.common.state = SB_ENABLED;
4898 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4899 sb_data_e1x.common.p_func.vf_id = 0xff;
4900 sb_data_e1x.common.p_func.vf_valid = false;
4901 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4902 sb_data_e1x.common.same_igu_sb_1b = true;
4903 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4904 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4905 hc_sm_p = sb_data_e1x.common.state_machine;
4906 sb_data_p = (u32 *)&sb_data_e1x;
4907 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4908 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
4911 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4912 igu_sb_id, igu_seg_id);
4913 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4914 igu_sb_id, igu_seg_id);
4916 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4918 /* write indecies to HW */
4919 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4922 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
4923 u16 tx_usec, u16 rx_usec)
4925 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
4927 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4928 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
4930 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4931 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
4933 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
4934 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
4938 static void bnx2x_init_def_sb(struct bnx2x *bp)
4940 struct host_sp_status_block *def_sb = bp->def_status_blk;
4941 dma_addr_t mapping = bp->def_status_blk_mapping;
4942 int igu_sp_sb_index;
4944 int port = BP_PORT(bp);
4945 int func = BP_FUNC(bp);
4949 struct hc_sp_status_block_data sp_sb_data;
4950 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4952 if (CHIP_INT_MODE_IS_BC(bp)) {
4953 igu_sp_sb_index = DEF_SB_IGU_ID;
4954 igu_seg_id = HC_SEG_ACCESS_DEF;
4956 igu_sp_sb_index = bp->igu_dsb_id;
4957 igu_seg_id = IGU_SEG_ACCESS_DEF;
4961 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4962 atten_status_block);
4963 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4967 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4968 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4969 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4971 /* take care of sig[0]..sig[4] */
4972 for (sindex = 0; sindex < 4; sindex++)
4973 bp->attn_group[index].sig[sindex] =
4974 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4976 if (!CHIP_IS_E1x(bp))
4978 * enable5 is separate from the rest of the registers,
4979 * and therefore the address skip is 4
4980 * and not 16 between the different groups
4982 bp->attn_group[index].sig[4] = REG_RD(bp,
4983 reg_offset + 0x10 + 0x4*index);
4985 bp->attn_group[index].sig[4] = 0;
4988 if (bp->common.int_block == INT_BLOCK_HC) {
4989 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4990 HC_REG_ATTN_MSG0_ADDR_L);
4992 REG_WR(bp, reg_offset, U64_LO(section));
4993 REG_WR(bp, reg_offset + 4, U64_HI(section));
4994 } else if (!CHIP_IS_E1x(bp)) {
4995 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4996 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4999 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5002 bnx2x_zero_sp_sb(bp);
5004 sp_sb_data.state = SB_ENABLED;
5005 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5006 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5007 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5008 sp_sb_data.igu_seg_id = igu_seg_id;
5009 sp_sb_data.p_func.pf_id = func;
5010 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5011 sp_sb_data.p_func.vf_id = 0xff;
5013 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5015 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5018 void bnx2x_update_coalesce(struct bnx2x *bp)
5022 for_each_eth_queue(bp, i)
5023 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5024 bp->tx_ticks, bp->rx_ticks);
5027 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5029 spin_lock_init(&bp->spq_lock);
5030 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5032 bp->spq_prod_idx = 0;
5033 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5034 bp->spq_prod_bd = bp->spq;
5035 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5038 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5041 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5042 union event_ring_elem *elem =
5043 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5045 elem->next_page.addr.hi =
5046 cpu_to_le32(U64_HI(bp->eq_mapping +
5047 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5048 elem->next_page.addr.lo =
5049 cpu_to_le32(U64_LO(bp->eq_mapping +
5050 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5053 bp->eq_prod = NUM_EQ_DESC;
5054 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5055 /* we want a warning message before it gets rought... */
5056 atomic_set(&bp->eq_spq_left,
5057 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5061 /* called with netif_addr_lock_bh() */
5062 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5063 unsigned long rx_mode_flags,
5064 unsigned long rx_accept_flags,
5065 unsigned long tx_accept_flags,
5066 unsigned long ramrod_flags)
5068 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5071 memset(&ramrod_param, 0, sizeof(ramrod_param));
5073 /* Prepare ramrod parameters */
5074 ramrod_param.cid = 0;
5075 ramrod_param.cl_id = cl_id;
5076 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5077 ramrod_param.func_id = BP_FUNC(bp);
5079 ramrod_param.pstate = &bp->sp_state;
5080 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5082 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5083 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5085 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5087 ramrod_param.ramrod_flags = ramrod_flags;
5088 ramrod_param.rx_mode_flags = rx_mode_flags;
5090 ramrod_param.rx_accept_flags = rx_accept_flags;
5091 ramrod_param.tx_accept_flags = tx_accept_flags;
5093 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5095 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5100 /* called with netif_addr_lock_bh() */
5101 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5103 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5104 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5109 /* Configure rx_mode of FCoE Queue */
5110 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5113 switch (bp->rx_mode) {
5114 case BNX2X_RX_MODE_NONE:
5116 * 'drop all' supersedes any accept flags that may have been
5117 * passed to the function.
5120 case BNX2X_RX_MODE_NORMAL:
5121 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5122 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5123 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5125 /* internal switching mode */
5126 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5127 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5128 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5131 case BNX2X_RX_MODE_ALLMULTI:
5132 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5133 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5134 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5136 /* internal switching mode */
5137 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5138 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5139 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5142 case BNX2X_RX_MODE_PROMISC:
5143 /* According to deffinition of SI mode, iface in promisc mode
5144 * should receive matched and unmatched (in resolution of port)
5147 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5148 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5149 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5150 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5152 /* internal switching mode */
5153 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5154 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5157 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5159 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5163 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5167 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5168 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5169 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5172 __set_bit(RAMROD_RX, &ramrod_flags);
5173 __set_bit(RAMROD_TX, &ramrod_flags);
5175 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5176 tx_accept_flags, ramrod_flags);
5179 static void bnx2x_init_internal_common(struct bnx2x *bp)
5185 * In switch independent mode, the TSTORM needs to accept
5186 * packets that failed classification, since approximate match
5187 * mac addresses aren't written to NIG LLH
5189 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5190 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5191 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5192 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5193 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5195 /* Zero this manually as its initialization is
5196 currently missing in the initTool */
5197 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5198 REG_WR(bp, BAR_USTRORM_INTMEM +
5199 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5200 if (!CHIP_IS_E1x(bp)) {
5201 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5202 CHIP_INT_MODE_IS_BC(bp) ?
5203 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5207 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5209 switch (load_code) {
5210 case FW_MSG_CODE_DRV_LOAD_COMMON:
5211 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5212 bnx2x_init_internal_common(bp);
5215 case FW_MSG_CODE_DRV_LOAD_PORT:
5219 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5220 /* internal memory per function is
5221 initialized inside bnx2x_pf_init */
5225 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5230 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5232 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5235 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5237 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5240 static inline u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5242 if (CHIP_IS_E1x(fp->bp))
5243 return BP_L_ID(fp->bp) + fp->index;
5244 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5245 return bnx2x_fp_igu_sb_id(fp);
5248 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5250 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5252 unsigned long q_type = 0;
5253 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5256 fp->cl_id = bnx2x_fp_cl_id(fp);
5257 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5258 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5259 /* qZone id equals to FW (per path) client id */
5260 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5263 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5264 /* Setup SB indicies */
5265 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5267 /* Configure Queue State object */
5268 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5269 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5271 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5274 for_each_cos_in_tx_queue(fp, cos) {
5275 bnx2x_init_txdata(bp, &fp->txdata[cos],
5276 CID_COS_TO_TX_ONLY_CID(fp->cid, cos),
5277 FP_COS_TO_TXQ(fp, cos),
5278 BNX2X_TX_SB_INDEX_BASE + cos);
5279 cids[cos] = fp->txdata[cos].cid;
5282 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, cids, fp->max_cos,
5283 BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5284 bnx2x_sp_mapping(bp, q_rdata), q_type);
5287 * Configure classification DBs: Always enable Tx switching
5289 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5291 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
5292 "cl_id %d fw_sb %d igu_sb %d\n",
5293 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5295 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5296 fp->fw_sb_id, fp->igu_sb_id);
5298 bnx2x_update_fpsb_idx(fp);
5301 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5305 for_each_eth_queue(bp, i)
5306 bnx2x_init_eth_fp(bp, i);
5309 bnx2x_init_fcoe_fp(bp);
5311 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5312 BNX2X_VF_ID_INVALID, false,
5313 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5317 /* Initialize MOD_ABS interrupts */
5318 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5319 bp->common.shmem_base, bp->common.shmem2_base,
5321 /* ensure status block indices were read */
5324 bnx2x_init_def_sb(bp);
5325 bnx2x_update_dsb_idx(bp);
5326 bnx2x_init_rx_rings(bp);
5327 bnx2x_init_tx_rings(bp);
5328 bnx2x_init_sp_ring(bp);
5329 bnx2x_init_eq_ring(bp);
5330 bnx2x_init_internal(bp, load_code);
5332 bnx2x_stats_init(bp);
5334 /* flush all before enabling interrupts */
5338 bnx2x_int_enable(bp);
5340 /* Check for SPIO5 */
5341 bnx2x_attn_int_deasserted0(bp,
5342 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5343 AEU_INPUTS_ATTN_BITS_SPIO5);
5346 /* end of nic init */
5349 * gzip service functions
5352 static int bnx2x_gunzip_init(struct bnx2x *bp)
5354 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5355 &bp->gunzip_mapping, GFP_KERNEL);
5356 if (bp->gunzip_buf == NULL)
5359 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5360 if (bp->strm == NULL)
5363 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5364 if (bp->strm->workspace == NULL)
5374 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5375 bp->gunzip_mapping);
5376 bp->gunzip_buf = NULL;
5379 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
5380 " un-compression\n");
5384 static void bnx2x_gunzip_end(struct bnx2x *bp)
5387 vfree(bp->strm->workspace);
5392 if (bp->gunzip_buf) {
5393 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5394 bp->gunzip_mapping);
5395 bp->gunzip_buf = NULL;
5399 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5403 /* check gzip header */
5404 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5405 BNX2X_ERR("Bad gzip header\n");
5413 if (zbuf[3] & FNAME)
5414 while ((zbuf[n++] != 0) && (n < len));
5416 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5417 bp->strm->avail_in = len - n;
5418 bp->strm->next_out = bp->gunzip_buf;
5419 bp->strm->avail_out = FW_BUF_SIZE;
5421 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5425 rc = zlib_inflate(bp->strm, Z_FINISH);
5426 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5427 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5430 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5431 if (bp->gunzip_outlen & 0x3)
5432 netdev_err(bp->dev, "Firmware decompression error:"
5433 " gunzip_outlen (%d) not aligned\n",
5435 bp->gunzip_outlen >>= 2;
5437 zlib_inflateEnd(bp->strm);
5439 if (rc == Z_STREAM_END)
5445 /* nic load/unload */
5448 * General service functions
5451 /* send a NIG loopback debug packet */
5452 static void bnx2x_lb_pckt(struct bnx2x *bp)
5456 /* Ethernet source and destination addresses */
5457 wb_write[0] = 0x55555555;
5458 wb_write[1] = 0x55555555;
5459 wb_write[2] = 0x20; /* SOP */
5460 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5462 /* NON-IP protocol */
5463 wb_write[0] = 0x09000000;
5464 wb_write[1] = 0x55555555;
5465 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5466 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5469 /* some of the internal memories
5470 * are not directly readable from the driver
5471 * to test them we send debug packets
5473 static int bnx2x_int_mem_test(struct bnx2x *bp)
5479 if (CHIP_REV_IS_FPGA(bp))
5481 else if (CHIP_REV_IS_EMUL(bp))
5486 /* Disable inputs of parser neighbor blocks */
5487 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5488 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5489 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5490 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5492 /* Write 0 to parser credits for CFC search request */
5493 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5495 /* send Ethernet packet */
5498 /* TODO do i reset NIG statistic? */
5499 /* Wait until NIG register shows 1 packet of size 0x10 */
5500 count = 1000 * factor;
5503 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5504 val = *bnx2x_sp(bp, wb_data[0]);
5512 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5516 /* Wait until PRS register shows 1 packet */
5517 count = 1000 * factor;
5519 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5527 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5531 /* Reset and init BRB, PRS */
5532 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5534 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5536 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5537 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5539 DP(NETIF_MSG_HW, "part2\n");
5541 /* Disable inputs of parser neighbor blocks */
5542 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5543 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5544 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5545 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5547 /* Write 0 to parser credits for CFC search request */
5548 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5550 /* send 10 Ethernet packets */
5551 for (i = 0; i < 10; i++)
5554 /* Wait until NIG register shows 10 + 1
5555 packets of size 11*0x10 = 0xb0 */
5556 count = 1000 * factor;
5559 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5560 val = *bnx2x_sp(bp, wb_data[0]);
5568 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5572 /* Wait until PRS register shows 2 packets */
5573 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5575 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5577 /* Write 1 to parser credits for CFC search request */
5578 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
5580 /* Wait until PRS register shows 3 packets */
5581 msleep(10 * factor);
5582 /* Wait until NIG register shows 1 packet of size 0x10 */
5583 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5585 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5587 /* clear NIG EOP FIFO */
5588 for (i = 0; i < 11; i++)
5589 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
5590 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
5592 BNX2X_ERR("clear of NIG failed\n");
5596 /* Reset and init BRB, PRS, NIG */
5597 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5599 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5601 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5602 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5605 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5608 /* Enable inputs of parser neighbor blocks */
5609 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
5610 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
5611 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
5612 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
5614 DP(NETIF_MSG_HW, "done\n");
5619 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
5621 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5622 if (!CHIP_IS_E1x(bp))
5623 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
5625 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
5626 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5627 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5629 * mask read length error interrupts in brb for parser
5630 * (parsing unit and 'checksum and crc' unit)
5631 * these errors are legal (PU reads fixed length and CAC can cause
5632 * read length error on truncated packets)
5634 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
5635 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
5636 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
5637 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
5638 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
5639 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
5640 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5641 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5642 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
5643 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
5644 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
5645 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5646 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5647 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
5648 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
5649 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
5650 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
5651 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5652 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5654 if (CHIP_REV_IS_FPGA(bp))
5655 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
5656 else if (!CHIP_IS_E1x(bp))
5657 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
5658 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5659 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5660 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5661 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5662 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
5664 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
5665 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
5666 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
5667 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
5668 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5670 if (!CHIP_IS_E1x(bp))
5671 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5672 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
5674 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
5675 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
5676 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5677 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
5680 static void bnx2x_reset_common(struct bnx2x *bp)
5685 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5688 if (CHIP_IS_E3(bp)) {
5689 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5690 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5693 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
5696 static void bnx2x_setup_dmae(struct bnx2x *bp)
5699 spin_lock_init(&bp->dmae_lock);
5702 static void bnx2x_init_pxp(struct bnx2x *bp)
5705 int r_order, w_order;
5707 pci_read_config_word(bp->pdev,
5708 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
5709 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
5710 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
5712 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5714 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
5718 bnx2x_init_pxp_arb(bp, r_order, w_order);
5721 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
5731 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
5732 SHARED_HW_CFG_FAN_FAILURE_MASK;
5734 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
5738 * The fan failure mechanism is usually related to the PHY type since
5739 * the power consumption of the board is affected by the PHY. Currently,
5740 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5742 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
5743 for (port = PORT_0; port < PORT_MAX; port++) {
5745 bnx2x_fan_failure_det_req(
5747 bp->common.shmem_base,
5748 bp->common.shmem2_base,
5752 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
5754 if (is_required == 0)
5757 /* Fan failure is indicated by SPIO 5 */
5758 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
5759 MISC_REGISTERS_SPIO_INPUT_HI_Z);
5761 /* set to active low mode */
5762 val = REG_RD(bp, MISC_REG_SPIO_INT);
5763 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
5764 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
5765 REG_WR(bp, MISC_REG_SPIO_INT, val);
5767 /* enable interrupt to signal the IGU */
5768 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
5769 val |= (1 << MISC_REGISTERS_SPIO_5);
5770 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
5773 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
5779 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
5782 switch (BP_ABS_FUNC(bp)) {
5784 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
5787 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
5790 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
5793 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
5796 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
5799 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
5802 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
5805 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
5811 REG_WR(bp, offset, pretend_func_num);
5813 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
5816 void bnx2x_pf_disable(struct bnx2x *bp)
5818 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
5819 val &= ~IGU_PF_CONF_FUNC_EN;
5821 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
5822 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5823 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
5826 static inline void bnx2x__common_init_phy(struct bnx2x *bp)
5828 u32 shmem_base[2], shmem2_base[2];
5829 shmem_base[0] = bp->common.shmem_base;
5830 shmem2_base[0] = bp->common.shmem2_base;
5831 if (!CHIP_IS_E1x(bp)) {
5833 SHMEM2_RD(bp, other_shmem_base_addr);
5835 SHMEM2_RD(bp, other_shmem2_base_addr);
5837 bnx2x_acquire_phy_lock(bp);
5838 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5839 bp->common.chip_id);
5840 bnx2x_release_phy_lock(bp);
5844 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5846 * @bp: driver handle
5848 static int bnx2x_init_hw_common(struct bnx2x *bp)
5852 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
5855 * take the UNDI lock to protect undi_unload flow from accessing
5856 * registers while we're resetting the chip
5858 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5860 bnx2x_reset_common(bp);
5861 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
5864 if (CHIP_IS_E3(bp)) {
5865 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
5866 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
5868 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
5870 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
5872 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
5874 if (!CHIP_IS_E1x(bp)) {
5878 * 4-port mode or 2-port mode we need to turn of master-enable
5879 * for everyone, after that, turn it back on for self.
5880 * so, we disregard multi-function or not, and always disable
5881 * for all functions on the given path, this means 0,2,4,6 for
5882 * path 0 and 1,3,5,7 for path 1
5884 for (abs_func_id = BP_PATH(bp);
5885 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
5886 if (abs_func_id == BP_ABS_FUNC(bp)) {
5888 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5893 bnx2x_pretend_func(bp, abs_func_id);
5894 /* clear pf enable */
5895 bnx2x_pf_disable(bp);
5896 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5900 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
5901 if (CHIP_IS_E1(bp)) {
5902 /* enable HW interrupt from PXP on USDM overflow
5903 bit 16 on INT_MASK_0 */
5904 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5907 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
5911 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5912 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5913 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5914 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5915 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5916 /* make sure this value is 0 */
5917 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5919 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5920 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5921 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5922 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5923 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5926 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5928 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5929 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5931 /* let the HW do it's magic ... */
5933 /* finish PXP init */
5934 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5936 BNX2X_ERR("PXP2 CFG failed\n");
5939 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5941 BNX2X_ERR("PXP2 RD_INIT failed\n");
5945 /* Timers bug workaround E2 only. We need to set the entire ILT to
5946 * have entries with value "0" and valid bit on.
5947 * This needs to be done by the first PF that is loaded in a path
5948 * (i.e. common phase)
5950 if (!CHIP_IS_E1x(bp)) {
5951 /* In E2 there is a bug in the timers block that can cause function 6 / 7
5952 * (i.e. vnic3) to start even if it is marked as "scan-off".
5953 * This occurs when a different function (func2,3) is being marked
5954 * as "scan-off". Real-life scenario for example: if a driver is being
5955 * load-unloaded while func6,7 are down. This will cause the timer to access
5956 * the ilt, translate to a logical address and send a request to read/write.
5957 * Since the ilt for the function that is down is not valid, this will cause
5958 * a translation error which is unrecoverable.
5959 * The Workaround is intended to make sure that when this happens nothing fatal
5960 * will occur. The workaround:
5961 * 1. First PF driver which loads on a path will:
5962 * a. After taking the chip out of reset, by using pretend,
5963 * it will write "0" to the following registers of
5965 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
5966 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
5967 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
5968 * And for itself it will write '1' to
5969 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
5970 * dmae-operations (writing to pram for example.)
5971 * note: can be done for only function 6,7 but cleaner this
5973 * b. Write zero+valid to the entire ILT.
5974 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
5975 * VNIC3 (of that port). The range allocated will be the
5976 * entire ILT. This is needed to prevent ILT range error.
5977 * 2. Any PF driver load flow:
5978 * a. ILT update with the physical addresses of the allocated
5980 * b. Wait 20msec. - note that this timeout is needed to make
5981 * sure there are no requests in one of the PXP internal
5982 * queues with "old" ILT addresses.
5983 * c. PF enable in the PGLC.
5984 * d. Clear the was_error of the PF in the PGLC. (could have
5985 * occured while driver was down)
5986 * e. PF enable in the CFC (WEAK + STRONG)
5987 * f. Timers scan enable
5988 * 3. PF driver unload flow:
5989 * a. Clear the Timers scan_en.
5990 * b. Polling for scan_on=0 for that PF.
5991 * c. Clear the PF enable bit in the PXP.
5992 * d. Clear the PF enable in the CFC (WEAK + STRONG)
5993 * e. Write zero+valid to all ILT entries (The valid bit must
5995 * f. If this is VNIC 3 of a port then also init
5996 * first_timers_ilt_entry to zero and last_timers_ilt_entry
5997 * to the last enrty in the ILT.
6000 * Currently the PF error in the PGLC is non recoverable.
6001 * In the future the there will be a recovery routine for this error.
6002 * Currently attention is masked.
6003 * Having an MCP lock on the load/unload process does not guarantee that
6004 * there is no Timer disable during Func6/7 enable. This is because the
6005 * Timers scan is currently being cleared by the MCP on FLR.
6006 * Step 2.d can be done only for PF6/7 and the driver can also check if
6007 * there is error before clearing it. But the flow above is simpler and
6009 * All ILT entries are written by zero+valid and not just PF6/7
6010 * ILT entries since in the future the ILT entries allocation for
6011 * PF-s might be dynamic.
6013 struct ilt_client_info ilt_cli;
6014 struct bnx2x_ilt ilt;
6015 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6016 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6018 /* initialize dummy TM client */
6020 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6021 ilt_cli.client_num = ILT_CLIENT_TM;
6023 /* Step 1: set zeroes to all ilt page entries with valid bit on
6024 * Step 2: set the timers first/last ilt entry to point
6025 * to the entire range to prevent ILT range error for 3rd/4th
6026 * vnic (this code assumes existance of the vnic)
6028 * both steps performed by call to bnx2x_ilt_client_init_op()
6029 * with dummy TM client
6031 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6032 * and his brother are split registers
6034 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6035 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6036 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6038 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6039 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6040 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6044 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6045 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6047 if (!CHIP_IS_E1x(bp)) {
6048 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6049 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6050 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6052 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6054 /* let the HW do it's magic ... */
6057 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6058 } while (factor-- && (val != 1));
6061 BNX2X_ERR("ATC_INIT failed\n");
6066 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6068 /* clean the DMAE memory */
6070 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6072 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6074 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6076 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6078 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6080 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6081 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6082 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6083 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6085 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6088 /* QM queues pointers table */
6089 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6091 /* soft reset pulse */
6092 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6093 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6096 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6099 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6100 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6101 if (!CHIP_REV_IS_SLOW(bp))
6102 /* enable hw interrupt from doorbell Q */
6103 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6105 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6107 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6108 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6110 if (!CHIP_IS_E1(bp))
6111 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6113 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp))
6114 /* Bit-map indicating which L2 hdrs may appear
6115 * after the basic Ethernet header
6117 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6118 bp->path_has_ovlan ? 7 : 6);
6120 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6121 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6122 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6123 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6125 if (!CHIP_IS_E1x(bp)) {
6126 /* reset VFC memories */
6127 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6128 VFC_MEMORIES_RST_REG_CAM_RST |
6129 VFC_MEMORIES_RST_REG_RAM_RST);
6130 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6131 VFC_MEMORIES_RST_REG_CAM_RST |
6132 VFC_MEMORIES_RST_REG_RAM_RST);
6137 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6138 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6139 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6140 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6143 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6145 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6148 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6149 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6150 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6152 if (!CHIP_IS_E1x(bp))
6153 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6154 bp->path_has_ovlan ? 7 : 6);
6156 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6158 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6161 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6162 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6163 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6164 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6165 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6166 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6167 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6168 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6169 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6170 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6172 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6174 if (sizeof(union cdu_context) != 1024)
6175 /* we currently assume that a context is 1024 bytes */
6176 dev_alert(&bp->pdev->dev, "please adjust the size "
6177 "of cdu_context(%ld)\n",
6178 (long)sizeof(union cdu_context));
6180 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6181 val = (4 << 24) + (0 << 12) + 1024;
6182 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6184 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6185 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6186 /* enable context validation interrupt from CFC */
6187 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6189 /* set the thresholds to prevent CFC/CDU race */
6190 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6192 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6194 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6195 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6197 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6198 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6200 /* Reset PCIE errors for debug */
6201 REG_WR(bp, 0x2814, 0xffffffff);
6202 REG_WR(bp, 0x3820, 0xffffffff);
6204 if (!CHIP_IS_E1x(bp)) {
6205 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6206 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6207 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6208 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6209 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6210 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6211 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6212 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6213 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6214 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6215 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6218 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6219 if (!CHIP_IS_E1(bp)) {
6220 /* in E3 this done in per-port section */
6221 if (!CHIP_IS_E3(bp))
6222 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6224 if (CHIP_IS_E1H(bp))
6225 /* not applicable for E2 (and above ...) */
6226 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6228 if (CHIP_REV_IS_SLOW(bp))
6231 /* finish CFC init */
6232 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6234 BNX2X_ERR("CFC LL_INIT failed\n");
6237 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6239 BNX2X_ERR("CFC AC_INIT failed\n");
6242 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6244 BNX2X_ERR("CFC CAM_INIT failed\n");
6247 REG_WR(bp, CFC_REG_DEBUG0, 0);
6249 if (CHIP_IS_E1(bp)) {
6250 /* read NIG statistic
6251 to see if this is our first up since powerup */
6252 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6253 val = *bnx2x_sp(bp, wb_data[0]);
6255 /* do internal memory self test */
6256 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6257 BNX2X_ERR("internal mem self test failed\n");
6262 bnx2x_setup_fan_failure_detection(bp);
6264 /* clear PXP2 attentions */
6265 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6267 bnx2x_enable_blocks_attention(bp);
6268 bnx2x_enable_blocks_parity(bp);
6270 if (!BP_NOMCP(bp)) {
6271 if (CHIP_IS_E1x(bp))
6272 bnx2x__common_init_phy(bp);
6274 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6280 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6282 * @bp: driver handle
6284 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6286 int rc = bnx2x_init_hw_common(bp);
6291 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6293 bnx2x__common_init_phy(bp);
6298 static int bnx2x_init_hw_port(struct bnx2x *bp)
6300 int port = BP_PORT(bp);
6301 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6305 bnx2x__link_reset(bp);
6307 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
6309 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6311 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6312 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6313 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6315 /* Timers bug workaround: disables the pf_master bit in pglue at
6316 * common phase, we need to enable it here before any dmae access are
6317 * attempted. Therefore we manually added the enable-master to the
6318 * port phase (it also happens in the function phase)
6320 if (!CHIP_IS_E1x(bp))
6321 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6323 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6324 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6325 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6326 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6328 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6329 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6330 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6331 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6333 /* QM cid (connection) count */
6334 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6337 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6338 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6339 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6342 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6344 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6345 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6348 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6349 else if (bp->dev->mtu > 4096) {
6350 if (bp->flags & ONE_PORT_FLAG)
6354 /* (24*1024 + val*4)/256 */
6355 low = 96 + (val/64) +
6356 ((val % 64) ? 1 : 0);
6359 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6360 high = low + 56; /* 14*1024/256 */
6361 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6362 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6365 if (CHIP_MODE_IS_4_PORT(bp))
6366 REG_WR(bp, (BP_PORT(bp) ?
6367 BRB1_REG_MAC_GUARANTIED_1 :
6368 BRB1_REG_MAC_GUARANTIED_0), 40);
6371 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6372 if (CHIP_IS_E3B0(bp))
6373 /* Ovlan exists only if we are in multi-function +
6374 * switch-dependent mode, in switch-independent there
6375 * is no ovlan headers
6377 REG_WR(bp, BP_PORT(bp) ?
6378 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6379 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6380 (bp->path_has_ovlan ? 7 : 6));
6382 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6383 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6384 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6385 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6387 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6388 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6389 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6390 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6392 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6393 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6395 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6397 if (CHIP_IS_E1x(bp)) {
6398 /* configure PBF to work without PAUSE mtu 9000 */
6399 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6401 /* update threshold */
6402 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6403 /* update init credit */
6404 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6407 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6409 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6413 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6415 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6416 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6418 if (CHIP_IS_E1(bp)) {
6419 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6420 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6422 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6424 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6426 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6427 /* init aeu_mask_attn_func_0/1:
6428 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6429 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6430 * bits 4-7 are used for "per vn group attention" */
6431 val = IS_MF(bp) ? 0xF7 : 0x7;
6432 /* Enable DCBX attention for all but E1 */
6433 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6434 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6436 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6438 if (!CHIP_IS_E1x(bp)) {
6439 /* Bit-map indicating which L2 hdrs may appear after the
6440 * basic Ethernet header
6442 REG_WR(bp, BP_PORT(bp) ?
6443 NIG_REG_P1_HDRS_AFTER_BASIC :
6444 NIG_REG_P0_HDRS_AFTER_BASIC,
6445 IS_MF_SD(bp) ? 7 : 6);
6448 REG_WR(bp, BP_PORT(bp) ?
6449 NIG_REG_LLH1_MF_MODE :
6450 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6452 if (!CHIP_IS_E3(bp))
6453 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6455 if (!CHIP_IS_E1(bp)) {
6456 /* 0x2 disable mf_ov, 0x1 enable */
6457 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6458 (IS_MF_SD(bp) ? 0x1 : 0x2));
6460 if (!CHIP_IS_E1x(bp)) {
6462 switch (bp->mf_mode) {
6463 case MULTI_FUNCTION_SD:
6466 case MULTI_FUNCTION_SI:
6471 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6472 NIG_REG_LLH0_CLS_TYPE), val);
6475 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6476 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6477 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6482 /* If SPIO5 is set to generate interrupts, enable it for this port */
6483 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6484 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6485 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6486 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6487 val = REG_RD(bp, reg_addr);
6488 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6489 REG_WR(bp, reg_addr, val);
6495 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6500 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6502 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6504 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
6507 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
6509 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
6512 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
6514 u32 i, base = FUNC_ILT_BASE(func);
6515 for (i = base; i < base + ILT_PER_FUNC; i++)
6516 bnx2x_ilt_wr(bp, i, 0);
6519 static int bnx2x_init_hw_func(struct bnx2x *bp)
6521 int port = BP_PORT(bp);
6522 int func = BP_FUNC(bp);
6523 int init_phase = PHASE_PF0 + func;
6524 struct bnx2x_ilt *ilt = BP_ILT(bp);
6527 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
6528 int i, main_mem_width;
6530 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
6532 /* FLR cleanup - hmmm */
6533 if (!CHIP_IS_E1x(bp))
6534 bnx2x_pf_flr_clnup(bp);
6536 /* set MSI reconfigure capability */
6537 if (bp->common.int_block == INT_BLOCK_HC) {
6538 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
6539 val = REG_RD(bp, addr);
6540 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
6541 REG_WR(bp, addr, val);
6544 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6545 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6548 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
6550 for (i = 0; i < L2_ILT_LINES(bp); i++) {
6551 ilt->lines[cdu_ilt_start + i].page =
6552 bp->context.vcxt + (ILT_PAGE_CIDS * i);
6553 ilt->lines[cdu_ilt_start + i].page_mapping =
6554 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
6555 /* cdu ilt pages are allocated manually so there's no need to
6558 bnx2x_ilt_init_op(bp, INITOP_SET);
6561 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
6563 /* T1 hash bits value determines the T1 number of entries */
6564 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
6569 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6570 #endif /* BCM_CNIC */
6572 if (!CHIP_IS_E1x(bp)) {
6573 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
6575 /* Turn on a single ISR mode in IGU if driver is going to use
6578 if (!(bp->flags & USING_MSIX_FLAG))
6579 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
6581 * Timers workaround bug: function init part.
6582 * Need to wait 20msec after initializing ILT,
6583 * needed to make sure there are no requests in
6584 * one of the PXP internal queues with "old" ILT addresses
6588 * Master enable - Due to WB DMAE writes performed before this
6589 * register is re-initialized as part of the regular function
6592 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6593 /* Enable the function in IGU */
6594 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
6599 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6601 if (!CHIP_IS_E1x(bp))
6602 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
6604 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6605 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6606 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6607 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6608 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6609 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6610 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6611 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6612 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6613 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6614 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6615 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6616 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6618 if (!CHIP_IS_E1x(bp))
6619 REG_WR(bp, QM_REG_PF_EN, 1);
6621 if (!CHIP_IS_E1x(bp)) {
6622 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6623 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6624 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6625 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
6627 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6629 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6630 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6631 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6632 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6633 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6634 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6635 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6636 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6637 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6638 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6639 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6640 if (!CHIP_IS_E1x(bp))
6641 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
6643 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6645 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6647 if (!CHIP_IS_E1x(bp))
6648 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
6651 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
6652 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
6655 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6657 /* HC init per function */
6658 if (bp->common.int_block == INT_BLOCK_HC) {
6659 if (CHIP_IS_E1H(bp)) {
6660 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6662 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6663 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6665 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6668 int num_segs, sb_idx, prod_offset;
6670 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
6672 if (!CHIP_IS_E1x(bp)) {
6673 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6674 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6677 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6679 if (!CHIP_IS_E1x(bp)) {
6683 * E2 mode: address 0-135 match to the mapping memory;
6684 * 136 - PF0 default prod; 137 - PF1 default prod;
6685 * 138 - PF2 default prod; 139 - PF3 default prod;
6686 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6687 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6690 * E1.5 mode - In backward compatible mode;
6691 * for non default SB; each even line in the memory
6692 * holds the U producer and each odd line hold
6693 * the C producer. The first 128 producers are for
6694 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6695 * producers are for the DSB for each PF.
6696 * Each PF has five segments: (the order inside each
6697 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6698 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6699 * 144-147 attn prods;
6701 /* non-default-status-blocks */
6702 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6703 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
6704 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
6705 prod_offset = (bp->igu_base_sb + sb_idx) *
6708 for (i = 0; i < num_segs; i++) {
6709 addr = IGU_REG_PROD_CONS_MEMORY +
6710 (prod_offset + i) * 4;
6711 REG_WR(bp, addr, 0);
6713 /* send consumer update with value 0 */
6714 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
6715 USTORM_ID, 0, IGU_INT_NOP, 1);
6716 bnx2x_igu_clear_sb(bp,
6717 bp->igu_base_sb + sb_idx);
6720 /* default-status-blocks */
6721 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
6722 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
6724 if (CHIP_MODE_IS_4_PORT(bp))
6725 dsb_idx = BP_FUNC(bp);
6727 dsb_idx = BP_VN(bp);
6729 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6730 IGU_BC_BASE_DSB_PROD + dsb_idx :
6731 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6734 * igu prods come in chunks of E1HVN_MAX (4) -
6735 * does not matters what is the current chip mode
6737 for (i = 0; i < (num_segs * E1HVN_MAX);
6739 addr = IGU_REG_PROD_CONS_MEMORY +
6740 (prod_offset + i)*4;
6741 REG_WR(bp, addr, 0);
6743 /* send consumer update with 0 */
6744 if (CHIP_INT_MODE_IS_BC(bp)) {
6745 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6746 USTORM_ID, 0, IGU_INT_NOP, 1);
6747 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6748 CSTORM_ID, 0, IGU_INT_NOP, 1);
6749 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6750 XSTORM_ID, 0, IGU_INT_NOP, 1);
6751 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6752 TSTORM_ID, 0, IGU_INT_NOP, 1);
6753 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6754 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6756 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6757 USTORM_ID, 0, IGU_INT_NOP, 1);
6758 bnx2x_ack_sb(bp, bp->igu_dsb_id,
6759 ATTENTION_ID, 0, IGU_INT_NOP, 1);
6761 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
6763 /* !!! these should become driver const once
6764 rf-tool supports split-68 const */
6765 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
6766 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
6767 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
6768 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
6769 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
6770 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
6774 /* Reset PCIE errors for debug */
6775 REG_WR(bp, 0x2114, 0xffffffff);
6776 REG_WR(bp, 0x2120, 0xffffffff);
6778 if (CHIP_IS_E1x(bp)) {
6779 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
6780 main_mem_base = HC_REG_MAIN_MEMORY +
6781 BP_PORT(bp) * (main_mem_size * 4);
6782 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
6785 val = REG_RD(bp, main_mem_prty_clr);
6787 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
6789 "function init (0x%x)!\n", val);
6791 /* Clear "false" parity errors in MSI-X table */
6792 for (i = main_mem_base;
6793 i < main_mem_base + main_mem_size * 4;
6794 i += main_mem_width) {
6795 bnx2x_read_dmae(bp, i, main_mem_width / 4);
6796 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
6797 i, main_mem_width / 4);
6799 /* Clear HC parity attention */
6800 REG_RD(bp, main_mem_prty_clr);
6803 #ifdef BNX2X_STOP_ON_ERROR
6804 /* Enable STORMs SP logging */
6805 REG_WR8(bp, BAR_USTRORM_INTMEM +
6806 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6807 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6808 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6809 REG_WR8(bp, BAR_CSTRORM_INTMEM +
6810 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6811 REG_WR8(bp, BAR_XSTRORM_INTMEM +
6812 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
6815 bnx2x_phy_probe(&bp->link_params);
6821 void bnx2x_free_mem(struct bnx2x *bp)
6824 bnx2x_free_fp_mem(bp);
6825 /* end of fastpath */
6827 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
6828 sizeof(struct host_sp_status_block));
6830 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6831 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6833 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
6834 sizeof(struct bnx2x_slowpath));
6836 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
6839 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
6841 BNX2X_FREE(bp->ilt->lines);
6844 if (!CHIP_IS_E1x(bp))
6845 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
6846 sizeof(struct host_hc_status_block_e2));
6848 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
6849 sizeof(struct host_hc_status_block_e1x));
6851 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
6854 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
6856 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
6857 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6860 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
6864 /* number of eth_queues */
6865 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp);
6867 /* Total number of FW statistics requests =
6868 * 1 for port stats + 1 for PF stats + num_eth_queues */
6869 bp->fw_stats_num = 2 + num_queue_stats;
6872 /* Request is built from stats_query_header and an array of
6873 * stats_query_cmd_group each of which contains
6874 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
6875 * configured in the stats_query_header.
6877 num_groups = (2 + num_queue_stats) / STATS_QUERY_CMD_COUNT +
6878 (((2 + num_queue_stats) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
6880 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
6881 num_groups * sizeof(struct stats_query_cmd_group);
6883 /* Data for statistics requests + stats_conter
6885 * stats_counter holds per-STORM counters that are incremented
6886 * when STORM has finished with the current request.
6888 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
6889 sizeof(struct per_pf_stats) +
6890 sizeof(struct per_queue_stats) * num_queue_stats +
6891 sizeof(struct stats_counter);
6893 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
6894 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6897 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
6898 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
6900 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
6901 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
6903 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
6904 bp->fw_stats_req_sz;
6908 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
6909 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
6914 int bnx2x_alloc_mem(struct bnx2x *bp)
6917 if (!CHIP_IS_E1x(bp))
6918 /* size = the status block + ramrod buffers */
6919 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
6920 sizeof(struct host_hc_status_block_e2));
6922 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
6923 sizeof(struct host_hc_status_block_e1x));
6925 /* allocate searcher T2 table */
6926 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
6930 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
6931 sizeof(struct host_sp_status_block));
6933 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
6934 sizeof(struct bnx2x_slowpath));
6936 /* Allocated memory for FW statistics */
6937 if (bnx2x_alloc_fw_stats_mem(bp))
6940 bp->context.size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
6942 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
6945 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
6947 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
6950 /* Slow path ring */
6951 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
6954 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
6955 BCM_PAGE_SIZE * NUM_EQ_PAGES);
6959 /* need to be done at the end, since it's self adjusting to amount
6960 * of memory available for RSS queues
6962 if (bnx2x_alloc_fp_mem(bp))
6972 * Init service functions
6975 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
6976 struct bnx2x_vlan_mac_obj *obj, bool set,
6977 int mac_type, unsigned long *ramrod_flags)
6980 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
6982 memset(&ramrod_param, 0, sizeof(ramrod_param));
6984 /* Fill general parameters */
6985 ramrod_param.vlan_mac_obj = obj;
6986 ramrod_param.ramrod_flags = *ramrod_flags;
6988 /* Fill a user request section if needed */
6989 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
6990 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
6992 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
6994 /* Set the command: ADD or DEL */
6996 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
6998 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7001 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7003 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7007 int bnx2x_del_all_macs(struct bnx2x *bp,
7008 struct bnx2x_vlan_mac_obj *mac_obj,
7009 int mac_type, bool wait_for_comp)
7012 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7014 /* Wait for completion of requested */
7016 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7018 /* Set the mac type of addresses we want to clear */
7019 __set_bit(mac_type, &vlan_mac_flags);
7021 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7023 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7028 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7030 unsigned long ramrod_flags = 0;
7032 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7034 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7035 /* Eth MAC is set on RSS leading client (fp[0]) */
7036 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->fp->mac_obj, set,
7037 BNX2X_ETH_MAC, &ramrod_flags);
7040 int bnx2x_setup_leading(struct bnx2x *bp)
7042 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7046 * bnx2x_set_int_mode - configure interrupt mode
7048 * @bp: driver handle
7050 * In case of MSI-X it will also try to enable MSI-X.
7052 static void __devinit bnx2x_set_int_mode(struct bnx2x *bp)
7056 bnx2x_enable_msi(bp);
7057 /* falling through... */
7059 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7060 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
7063 /* Set number of queues according to bp->multi_mode value */
7064 bnx2x_set_num_queues(bp);
7066 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
7069 /* if we can't use MSI-X we only need one fp,
7070 * so try to enable MSI-X with the requested number of fp's
7071 * and fallback to MSI or legacy INTx with one fp
7073 if (bnx2x_enable_msix(bp)) {
7074 /* failed to enable MSI-X */
7077 "Multi requested but failed to "
7078 "enable MSI-X (%d), "
7079 "set number of queues to %d\n",
7081 1 + NON_ETH_CONTEXT_USE);
7082 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7084 /* Try to enable MSI */
7085 if (!(bp->flags & DISABLE_MSI_FLAG))
7086 bnx2x_enable_msi(bp);
7092 /* must be called prioir to any HW initializations */
7093 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7095 return L2_ILT_LINES(bp);
7098 void bnx2x_ilt_set_info(struct bnx2x *bp)
7100 struct ilt_client_info *ilt_client;
7101 struct bnx2x_ilt *ilt = BP_ILT(bp);
7104 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7105 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7108 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7109 ilt_client->client_num = ILT_CLIENT_CDU;
7110 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7111 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7112 ilt_client->start = line;
7113 line += bnx2x_cid_ilt_lines(bp);
7115 line += CNIC_ILT_LINES;
7117 ilt_client->end = line - 1;
7119 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
7120 "flags 0x%x, hw psz %d\n",
7123 ilt_client->page_size,
7125 ilog2(ilt_client->page_size >> 12));
7128 if (QM_INIT(bp->qm_cid_count)) {
7129 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7130 ilt_client->client_num = ILT_CLIENT_QM;
7131 ilt_client->page_size = QM_ILT_PAGE_SZ;
7132 ilt_client->flags = 0;
7133 ilt_client->start = line;
7135 /* 4 bytes for each cid */
7136 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7139 ilt_client->end = line - 1;
7141 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
7142 "flags 0x%x, hw psz %d\n",
7145 ilt_client->page_size,
7147 ilog2(ilt_client->page_size >> 12));
7151 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7153 ilt_client->client_num = ILT_CLIENT_SRC;
7154 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7155 ilt_client->flags = 0;
7156 ilt_client->start = line;
7157 line += SRC_ILT_LINES;
7158 ilt_client->end = line - 1;
7160 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
7161 "flags 0x%x, hw psz %d\n",
7164 ilt_client->page_size,
7166 ilog2(ilt_client->page_size >> 12));
7169 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7173 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7175 ilt_client->client_num = ILT_CLIENT_TM;
7176 ilt_client->page_size = TM_ILT_PAGE_SZ;
7177 ilt_client->flags = 0;
7178 ilt_client->start = line;
7179 line += TM_ILT_LINES;
7180 ilt_client->end = line - 1;
7182 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
7183 "flags 0x%x, hw psz %d\n",
7186 ilt_client->page_size,
7188 ilog2(ilt_client->page_size >> 12));
7191 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7193 BUG_ON(line > ILT_MAX_LINES);
7197 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7199 * @bp: driver handle
7200 * @fp: pointer to fastpath
7201 * @init_params: pointer to parameters structure
7203 * parameters configured:
7204 * - HC configuration
7205 * - Queue's CDU context
7207 static inline void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7208 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7212 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7213 if (!IS_FCOE_FP(fp)) {
7214 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7215 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7217 /* If HC is supporterd, enable host coalescing in the transition
7220 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7221 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7224 init_params->rx.hc_rate = bp->rx_ticks ?
7225 (1000000 / bp->rx_ticks) : 0;
7226 init_params->tx.hc_rate = bp->tx_ticks ?
7227 (1000000 / bp->tx_ticks) : 0;
7230 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7234 * CQ index among the SB indices: FCoE clients uses the default
7235 * SB, therefore it's different.
7237 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7238 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7241 /* set maximum number of COSs supported by this queue */
7242 init_params->max_cos = fp->max_cos;
7244 DP(BNX2X_MSG_SP, "fp: %d setting queue params max cos to: %d",
7245 fp->index, init_params->max_cos);
7247 /* set the context pointers queue object */
7248 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++)
7249 init_params->cxts[cos] =
7250 &bp->context.vcxt[fp->txdata[cos].cid].eth;
7253 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7254 struct bnx2x_queue_state_params *q_params,
7255 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7256 int tx_index, bool leading)
7258 memset(tx_only_params, 0, sizeof(*tx_only_params));
7260 /* Set the command */
7261 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7263 /* Set tx-only QUEUE flags: don't zero statistics */
7264 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7266 /* choose the index of the cid to send the slow path on */
7267 tx_only_params->cid_index = tx_index;
7269 /* Set general TX_ONLY_SETUP parameters */
7270 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7272 /* Set Tx TX_ONLY_SETUP parameters */
7273 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7275 DP(BNX2X_MSG_SP, "preparing to send tx-only ramrod for connection:"
7276 "cos %d, primary cid %d, cid %d, "
7277 "client id %d, sp-client id %d, flags %lx",
7278 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7279 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7280 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7282 /* send the ramrod */
7283 return bnx2x_queue_state_change(bp, q_params);
7288 * bnx2x_setup_queue - setup queue
7290 * @bp: driver handle
7291 * @fp: pointer to fastpath
7292 * @leading: is leading
7294 * This function performs 2 steps in a Queue state machine
7295 * actually: 1) RESET->INIT 2) INIT->SETUP
7298 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7301 struct bnx2x_queue_state_params q_params = {0};
7302 struct bnx2x_queue_setup_params *setup_params =
7303 &q_params.params.setup;
7304 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7305 &q_params.params.tx_only;
7309 DP(BNX2X_MSG_SP, "setting up queue %d", fp->index);
7311 /* reset IGU state skip FCoE L2 queue */
7312 if (!IS_FCOE_FP(fp))
7313 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7316 q_params.q_obj = &fp->q_obj;
7317 /* We want to wait for completion in this context */
7318 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7320 /* Prepare the INIT parameters */
7321 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7323 /* Set the command */
7324 q_params.cmd = BNX2X_Q_CMD_INIT;
7326 /* Change the state to INIT */
7327 rc = bnx2x_queue_state_change(bp, &q_params);
7329 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7333 DP(BNX2X_MSG_SP, "init complete");
7336 /* Now move the Queue to the SETUP state... */
7337 memset(setup_params, 0, sizeof(*setup_params));
7339 /* Set QUEUE flags */
7340 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7342 /* Set general SETUP parameters */
7343 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7344 FIRST_TX_COS_INDEX);
7346 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7347 &setup_params->rxq_params);
7349 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7350 FIRST_TX_COS_INDEX);
7352 /* Set the command */
7353 q_params.cmd = BNX2X_Q_CMD_SETUP;
7355 /* Change the state to SETUP */
7356 rc = bnx2x_queue_state_change(bp, &q_params);
7358 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7362 /* loop through the relevant tx-only indices */
7363 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7364 tx_index < fp->max_cos;
7367 /* prepare and send tx-only ramrod*/
7368 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7369 tx_only_params, tx_index, leading);
7371 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7372 fp->index, tx_index);
7380 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7382 struct bnx2x_fastpath *fp = &bp->fp[index];
7383 struct bnx2x_fp_txdata *txdata;
7384 struct bnx2x_queue_state_params q_params = {0};
7387 DP(BNX2X_MSG_SP, "stopping queue %d cid %d", index, fp->cid);
7389 q_params.q_obj = &fp->q_obj;
7390 /* We want to wait for completion in this context */
7391 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7394 /* close tx-only connections */
7395 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7396 tx_index < fp->max_cos;
7399 /* ascertain this is a normal queue*/
7400 txdata = &fp->txdata[tx_index];
7402 DP(BNX2X_MSG_SP, "stopping tx-only queue %d",
7405 /* send halt terminate on tx-only connection */
7406 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7407 memset(&q_params.params.terminate, 0,
7408 sizeof(q_params.params.terminate));
7409 q_params.params.terminate.cid_index = tx_index;
7411 rc = bnx2x_queue_state_change(bp, &q_params);
7415 /* send halt terminate on tx-only connection */
7416 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7417 memset(&q_params.params.cfc_del, 0,
7418 sizeof(q_params.params.cfc_del));
7419 q_params.params.cfc_del.cid_index = tx_index;
7420 rc = bnx2x_queue_state_change(bp, &q_params);
7424 /* Stop the primary connection: */
7425 /* ...halt the connection */
7426 q_params.cmd = BNX2X_Q_CMD_HALT;
7427 rc = bnx2x_queue_state_change(bp, &q_params);
7431 /* ...terminate the connection */
7432 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7433 memset(&q_params.params.terminate, 0,
7434 sizeof(q_params.params.terminate));
7435 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
7436 rc = bnx2x_queue_state_change(bp, &q_params);
7439 /* ...delete cfc entry */
7440 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7441 memset(&q_params.params.cfc_del, 0,
7442 sizeof(q_params.params.cfc_del));
7443 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
7444 return bnx2x_queue_state_change(bp, &q_params);
7448 static void bnx2x_reset_func(struct bnx2x *bp)
7450 int port = BP_PORT(bp);
7451 int func = BP_FUNC(bp);
7454 /* Disable the function in the FW */
7455 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
7456 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
7457 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
7458 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
7461 for_each_eth_queue(bp, i) {
7462 struct bnx2x_fastpath *fp = &bp->fp[i];
7463 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7464 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
7470 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7471 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
7475 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7476 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
7479 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
7480 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
7484 if (bp->common.int_block == INT_BLOCK_HC) {
7485 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7486 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7488 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7489 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7493 /* Disable Timer scan */
7494 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
7496 * Wait for at least 10ms and up to 2 second for the timers scan to
7499 for (i = 0; i < 200; i++) {
7501 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
7506 bnx2x_clear_func_ilt(bp, func);
7508 /* Timers workaround bug for E2: if this is vnic-3,
7509 * we need to set the entire ilt range for this timers.
7511 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
7512 struct ilt_client_info ilt_cli;
7513 /* use dummy TM client */
7514 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7516 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7517 ilt_cli.client_num = ILT_CLIENT_TM;
7519 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
7522 /* this assumes that reset_port() called before reset_func()*/
7523 if (!CHIP_IS_E1x(bp))
7524 bnx2x_pf_disable(bp);
7529 static void bnx2x_reset_port(struct bnx2x *bp)
7531 int port = BP_PORT(bp);
7534 /* Reset physical Link */
7535 bnx2x__link_reset(bp);
7537 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7539 /* Do not rcv packets to BRB */
7540 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
7541 /* Do not direct rcv packets that are not for MCP to the BRB */
7542 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
7543 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7546 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
7549 /* Check for BRB port occupancy */
7550 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
7552 DP(NETIF_MSG_IFDOWN,
7553 "BRB1 is not empty %d blocks are occupied\n", val);
7555 /* TODO: Close Doorbell port? */
7558 static inline int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
7560 struct bnx2x_func_state_params func_params = {0};
7562 /* Prepare parameters for function state transitions */
7563 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7565 func_params.f_obj = &bp->func_obj;
7566 func_params.cmd = BNX2X_F_CMD_HW_RESET;
7568 func_params.params.hw_init.load_phase = load_code;
7570 return bnx2x_func_state_change(bp, &func_params);
7573 static inline int bnx2x_func_stop(struct bnx2x *bp)
7575 struct bnx2x_func_state_params func_params = {0};
7578 /* Prepare parameters for function state transitions */
7579 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7580 func_params.f_obj = &bp->func_obj;
7581 func_params.cmd = BNX2X_F_CMD_STOP;
7584 * Try to stop the function the 'good way'. If fails (in case
7585 * of a parity error during bnx2x_chip_cleanup()) and we are
7586 * not in a debug mode, perform a state transaction in order to
7587 * enable further HW_RESET transaction.
7589 rc = bnx2x_func_state_change(bp, &func_params);
7591 #ifdef BNX2X_STOP_ON_ERROR
7594 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry "
7596 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
7597 return bnx2x_func_state_change(bp, &func_params);
7605 * bnx2x_send_unload_req - request unload mode from the MCP.
7607 * @bp: driver handle
7608 * @unload_mode: requested function's unload mode
7610 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7612 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7615 int port = BP_PORT(bp);
7617 /* Select the UNLOAD request mode */
7618 if (unload_mode == UNLOAD_NORMAL)
7619 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7621 else if (bp->flags & NO_WOL_FLAG)
7622 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7625 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7626 u8 *mac_addr = bp->dev->dev_addr;
7628 /* The mac address is written to entries 1-4 to
7629 preserve entry 0 which is used by the PMF */
7630 u8 entry = (BP_VN(bp) + 1)*8;
7632 val = (mac_addr[0] << 8) | mac_addr[1];
7633 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7635 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7636 (mac_addr[4] << 8) | mac_addr[5];
7637 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7639 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7642 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7644 /* Send the request to the MCP */
7646 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7648 int path = BP_PATH(bp);
7650 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7652 path, load_count[path][0], load_count[path][1],
7653 load_count[path][2]);
7654 load_count[path][0]--;
7655 load_count[path][1 + port]--;
7656 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7658 path, load_count[path][0], load_count[path][1],
7659 load_count[path][2]);
7660 if (load_count[path][0] == 0)
7661 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7662 else if (load_count[path][1 + port] == 0)
7663 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7665 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7672 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7674 * @bp: driver handle
7676 void bnx2x_send_unload_done(struct bnx2x *bp)
7678 /* Report UNLOAD_DONE to MCP */
7680 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7683 static inline int bnx2x_func_wait_started(struct bnx2x *bp)
7686 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
7692 * (assumption: No Attention from MCP at this stage)
7693 * PMF probably in the middle of TXdisable/enable transaction
7694 * 1. Sync IRS for default SB
7695 * 2. Sync SP queue - this guarantes us that attention handling started
7696 * 3. Wait, that TXdisable/enable transaction completes
7698 * 1+2 guranty that if DCBx attention was scheduled it already changed
7699 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7700 * received complettion for the transaction the state is TX_STOPPED.
7701 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7705 /* make sure default SB ISR is done */
7707 synchronize_irq(bp->msix_table[0].vector);
7709 synchronize_irq(bp->pdev->irq);
7711 flush_workqueue(bnx2x_wq);
7713 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
7714 BNX2X_F_STATE_STARTED && tout--)
7717 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
7718 BNX2X_F_STATE_STARTED) {
7719 #ifdef BNX2X_STOP_ON_ERROR
7723 * Failed to complete the transaction in a "good way"
7724 * Force both transactions with CLR bit
7726 struct bnx2x_func_state_params func_params = {0};
7728 DP(BNX2X_MSG_SP, "Hmmm... unexpected function state! "
7729 "Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7731 func_params.f_obj = &bp->func_obj;
7732 __set_bit(RAMROD_DRV_CLR_ONLY,
7733 &func_params.ramrod_flags);
7735 /* STARTED-->TX_ST0PPED */
7736 func_params.cmd = BNX2X_F_CMD_TX_STOP;
7737 bnx2x_func_state_change(bp, &func_params);
7739 /* TX_ST0PPED-->STARTED */
7740 func_params.cmd = BNX2X_F_CMD_TX_START;
7741 return bnx2x_func_state_change(bp, &func_params);
7748 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7750 int port = BP_PORT(bp);
7753 struct bnx2x_mcast_ramrod_params rparam = {0};
7756 /* Wait until tx fastpath tasks complete */
7757 for_each_tx_queue(bp, i) {
7758 struct bnx2x_fastpath *fp = &bp->fp[i];
7760 for_each_cos_in_tx_queue(fp, cos)
7761 rc = bnx2x_clean_tx_queue(bp, &fp->txdata[cos]);
7762 #ifdef BNX2X_STOP_ON_ERROR
7768 /* Give HW time to discard old tx messages */
7769 usleep_range(1000, 1000);
7771 /* Clean all ETH MACs */
7772 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_ETH_MAC, false);
7774 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
7776 /* Clean up UC list */
7777 rc = bnx2x_del_all_macs(bp, &bp->fp[0].mac_obj, BNX2X_UC_LIST_MAC,
7780 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: "
7784 if (!CHIP_IS_E1(bp))
7785 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7787 /* Set "drop all" (stop Rx).
7788 * We need to take a netif_addr_lock() here in order to prevent
7789 * a race between the completion code and this code.
7791 netif_addr_lock_bh(bp->dev);
7792 /* Schedule the rx_mode command */
7793 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
7794 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
7796 bnx2x_set_storm_rx_mode(bp);
7798 /* Cleanup multicast configuration */
7799 rparam.mcast_obj = &bp->mcast_obj;
7800 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
7802 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
7804 netif_addr_unlock_bh(bp->dev);
7809 * Send the UNLOAD_REQUEST to the MCP. This will return if
7810 * this function should perform FUNC, PORT or COMMON HW
7813 reset_code = bnx2x_send_unload_req(bp, unload_mode);
7816 * (assumption: No Attention from MCP at this stage)
7817 * PMF probably in the middle of TXdisable/enable transaction
7819 rc = bnx2x_func_wait_started(bp);
7821 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7822 #ifdef BNX2X_STOP_ON_ERROR
7827 /* Close multi and leading connections
7828 * Completions for ramrods are collected in a synchronous way
7830 for_each_queue(bp, i)
7831 if (bnx2x_stop_queue(bp, i))
7832 #ifdef BNX2X_STOP_ON_ERROR
7837 /* If SP settings didn't get completed so far - something
7838 * very wrong has happen.
7840 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
7841 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
7843 #ifndef BNX2X_STOP_ON_ERROR
7846 rc = bnx2x_func_stop(bp);
7848 BNX2X_ERR("Function stop failed!\n");
7849 #ifdef BNX2X_STOP_ON_ERROR
7854 /* Disable HW interrupts, NAPI */
7855 bnx2x_netif_stop(bp, 1);
7860 /* Reset the chip */
7861 rc = bnx2x_reset_hw(bp, reset_code);
7863 BNX2X_ERR("HW_RESET failed\n");
7866 /* Report UNLOAD_DONE to MCP */
7867 bnx2x_send_unload_done(bp);
7870 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7874 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7876 if (CHIP_IS_E1(bp)) {
7877 int port = BP_PORT(bp);
7878 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7879 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7881 val = REG_RD(bp, addr);
7883 REG_WR(bp, addr, val);
7885 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7886 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7887 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7888 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7892 /* Close gates #2, #3 and #4: */
7893 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7897 /* Gates #2 and #4a are closed/opened for "not E1" only */
7898 if (!CHIP_IS_E1(bp)) {
7900 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
7902 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
7906 if (CHIP_IS_E1x(bp)) {
7907 /* Prevent interrupts from HC on both ports */
7908 val = REG_RD(bp, HC_REG_CONFIG_1);
7909 REG_WR(bp, HC_REG_CONFIG_1,
7910 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
7911 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
7913 val = REG_RD(bp, HC_REG_CONFIG_0);
7914 REG_WR(bp, HC_REG_CONFIG_0,
7915 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
7916 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
7918 /* Prevent incomming interrupts in IGU */
7919 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
7921 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
7923 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
7924 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
7927 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7928 close ? "closing" : "opening");
7932 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7934 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7936 /* Do some magic... */
7937 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7938 *magic_val = val & SHARED_MF_CLP_MAGIC;
7939 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7943 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7945 * @bp: driver handle
7946 * @magic_val: old value of the `magic' bit.
7948 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7950 /* Restore the `magic' bit value... */
7951 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7952 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7953 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7957 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7959 * @bp: driver handle
7960 * @magic_val: old value of 'magic' bit.
7962 * Takes care of CLP configurations.
7964 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7967 u32 validity_offset;
7969 DP(NETIF_MSG_HW, "Starting\n");
7971 /* Set `magic' bit in order to save MF config */
7972 if (!CHIP_IS_E1(bp))
7973 bnx2x_clp_reset_prep(bp, magic_val);
7975 /* Get shmem offset */
7976 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7977 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7979 /* Clear validity map flags */
7981 REG_WR(bp, shmem + validity_offset, 0);
7984 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7985 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7988 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7990 * @bp: driver handle
7992 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7994 /* special handling for emulation and FPGA,
7995 wait 10 times longer */
7996 if (CHIP_REV_IS_SLOW(bp))
7997 msleep(MCP_ONE_TIMEOUT*10);
7999 msleep(MCP_ONE_TIMEOUT);
8003 * initializes bp->common.shmem_base and waits for validity signature to appear
8005 static int bnx2x_init_shmem(struct bnx2x *bp)
8011 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8012 if (bp->common.shmem_base) {
8013 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8014 if (val & SHR_MEM_VALIDITY_MB)
8018 bnx2x_mcp_wait_one(bp);
8020 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8022 BNX2X_ERR("BAD MCP validity signature\n");
8027 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8029 int rc = bnx2x_init_shmem(bp);
8031 /* Restore the `magic' bit value */
8032 if (!CHIP_IS_E1(bp))
8033 bnx2x_clp_reset_done(bp, magic_val);
8038 static void bnx2x_pxp_prep(struct bnx2x *bp)
8040 if (!CHIP_IS_E1(bp)) {
8041 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8042 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8048 * Reset the whole chip except for:
8050 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8053 * - MISC (including AEU)
8057 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8059 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8060 u32 global_bits2, stay_reset2;
8063 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8064 * (per chip) blocks.
8067 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8068 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8070 /* Don't reset the following blocks */
8072 MISC_REGISTERS_RESET_REG_1_RST_HC |
8073 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8074 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8077 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8078 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8079 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8080 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8081 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8082 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8083 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8084 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8085 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8086 MISC_REGISTERS_RESET_REG_2_PGLC;
8089 * Keep the following blocks in reset:
8090 * - all xxMACs are handled by the bnx2x_link code.
8093 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8094 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8095 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8096 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8097 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8098 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8099 MISC_REGISTERS_RESET_REG_2_XMAC |
8100 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8102 /* Full reset masks according to the chip */
8103 reset_mask1 = 0xffffffff;
8106 reset_mask2 = 0xffff;
8107 else if (CHIP_IS_E1H(bp))
8108 reset_mask2 = 0x1ffff;
8109 else if (CHIP_IS_E2(bp))
8110 reset_mask2 = 0xfffff;
8111 else /* CHIP_IS_E3 */
8112 reset_mask2 = 0x3ffffff;
8114 /* Don't reset global blocks unless we need to */
8116 reset_mask2 &= ~global_bits2;
8119 * In case of attention in the QM, we need to reset PXP
8120 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8121 * because otherwise QM reset would release 'close the gates' shortly
8122 * before resetting the PXP, then the PSWRQ would send a write
8123 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8124 * read the payload data from PSWWR, but PSWWR would not
8125 * respond. The write queue in PGLUE would stuck, dmae commands
8126 * would not return. Therefore it's important to reset the second
8127 * reset register (containing the
8128 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8129 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8132 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8133 reset_mask2 & (~not_reset_mask2));
8135 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8136 reset_mask1 & (~not_reset_mask1));
8141 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8142 reset_mask2 & (~stay_reset2));
8147 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8152 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8153 * It should get cleared in no more than 1s.
8155 * @bp: driver handle
8157 * It should get cleared in no more than 1s. Returns 0 if
8158 * pending writes bit gets cleared.
8160 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8166 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8171 usleep_range(1000, 1000);
8172 } while (cnt-- > 0);
8175 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8183 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8187 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8190 /* Empty the Tetris buffer, wait for 1s */
8192 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8193 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8194 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8195 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8196 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8197 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8198 ((port_is_idle_0 & 0x1) == 0x1) &&
8199 ((port_is_idle_1 & 0x1) == 0x1) &&
8200 (pgl_exp_rom2 == 0xffffffff))
8202 usleep_range(1000, 1000);
8203 } while (cnt-- > 0);
8206 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
8208 " outstanding read requests after 1s!\n");
8209 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
8210 " port_is_idle_0=0x%08x,"
8211 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8212 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8219 /* Close gates #2, #3 and #4 */
8220 bnx2x_set_234_gates(bp, true);
8222 /* Poll for IGU VQs for 57712 and newer chips */
8223 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8227 /* TBD: Indicate that "process kill" is in progress to MCP */
8229 /* Clear "unprepared" bit */
8230 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8233 /* Make sure all is written to the chip before the reset */
8236 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8237 * PSWHST, GRC and PSWRD Tetris buffer.
8239 usleep_range(1000, 1000);
8241 /* Prepare to chip reset: */
8244 bnx2x_reset_mcp_prep(bp, &val);
8250 /* reset the chip */
8251 bnx2x_process_kill_chip_reset(bp, global);
8254 /* Recover after reset: */
8256 if (global && bnx2x_reset_mcp_comp(bp, val))
8259 /* TBD: Add resetting the NO_MCP mode DB here */
8264 /* Open the gates #2, #3 and #4 */
8265 bnx2x_set_234_gates(bp, false);
8267 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8268 * reset state, re-enable attentions. */
8273 int bnx2x_leader_reset(struct bnx2x *bp)
8276 bool global = bnx2x_reset_is_global(bp);
8278 /* Try to recover after the failure */
8279 if (bnx2x_process_kill(bp, global)) {
8280 netdev_err(bp->dev, "Something bad had happen on engine %d! "
8281 "Aii!\n", BP_PATH(bp));
8283 goto exit_leader_reset;
8287 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8290 bnx2x_set_reset_done(bp);
8292 bnx2x_clear_reset_global(bp);
8296 bnx2x_release_leader_lock(bp);
8301 static inline void bnx2x_recovery_failed(struct bnx2x *bp)
8303 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8305 /* Disconnect this device */
8306 netif_device_detach(bp->dev);
8309 * Block ifup for all function on this engine until "process kill"
8312 bnx2x_set_reset_in_progress(bp);
8314 /* Shut down the power */
8315 bnx2x_set_power_state(bp, PCI_D3hot);
8317 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8323 * Assumption: runs under rtnl lock. This together with the fact
8324 * that it's called only from bnx2x_sp_rtnl() ensure that it
8325 * will never be called when netif_running(bp->dev) is false.
8327 static void bnx2x_parity_recover(struct bnx2x *bp)
8329 bool global = false;
8331 DP(NETIF_MSG_HW, "Handling parity\n");
8333 switch (bp->recovery_state) {
8334 case BNX2X_RECOVERY_INIT:
8335 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8336 bnx2x_chk_parity_attn(bp, &global, false);
8338 /* Try to get a LEADER_LOCK HW lock */
8339 if (bnx2x_trylock_leader_lock(bp)) {
8340 bnx2x_set_reset_in_progress(bp);
8342 * Check if there is a global attention and if
8343 * there was a global attention, set the global
8348 bnx2x_set_reset_global(bp);
8353 /* Stop the driver */
8354 /* If interface has been removed - break */
8355 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8358 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8361 * Reset MCP command sequence number and MCP mail box
8362 * sequence as we are going to reset the MCP.
8366 bp->fw_drv_pulse_wr_seq = 0;
8369 /* Ensure "is_leader", MCP command sequence and
8370 * "recovery_state" update values are seen on other
8376 case BNX2X_RECOVERY_WAIT:
8377 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8378 if (bp->is_leader) {
8379 int other_engine = BP_PATH(bp) ? 0 : 1;
8380 u32 other_load_counter =
8381 bnx2x_get_load_cnt(bp, other_engine);
8383 bnx2x_get_load_cnt(bp, BP_PATH(bp));
8384 global = bnx2x_reset_is_global(bp);
8387 * In case of a parity in a global block, let
8388 * the first leader that performs a
8389 * leader_reset() reset the global blocks in
8390 * order to clear global attentions. Otherwise
8391 * the the gates will remain closed for that
8395 (global && other_load_counter)) {
8396 /* Wait until all other functions get
8399 schedule_delayed_work(&bp->sp_rtnl_task,
8403 /* If all other functions got down -
8404 * try to bring the chip back to
8405 * normal. In any case it's an exit
8406 * point for a leader.
8408 if (bnx2x_leader_reset(bp)) {
8409 bnx2x_recovery_failed(bp);
8413 /* If we are here, means that the
8414 * leader has succeeded and doesn't
8415 * want to be a leader any more. Try
8416 * to continue as a none-leader.
8420 } else { /* non-leader */
8421 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
8422 /* Try to get a LEADER_LOCK HW lock as
8423 * long as a former leader may have
8424 * been unloaded by the user or
8425 * released a leadership by another
8428 if (bnx2x_trylock_leader_lock(bp)) {
8429 /* I'm a leader now! Restart a
8436 schedule_delayed_work(&bp->sp_rtnl_task,
8442 * If there was a global attention, wait
8443 * for it to be cleared.
8445 if (bnx2x_reset_is_global(bp)) {
8446 schedule_delayed_work(
8452 if (bnx2x_nic_load(bp, LOAD_NORMAL))
8453 bnx2x_recovery_failed(bp);
8455 bp->recovery_state =
8456 BNX2X_RECOVERY_DONE;
8469 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8470 * scheduled on a general queue in order to prevent a dead lock.
8472 static void bnx2x_sp_rtnl_task(struct work_struct *work)
8474 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
8478 if (!netif_running(bp->dev))
8481 /* if stop on error is defined no recovery flows should be executed */
8482 #ifdef BNX2X_STOP_ON_ERROR
8483 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined "
8484 "so reset not done to allow debug dump,\n"
8485 "you will need to reboot when done\n");
8486 goto sp_rtnl_not_reset;
8489 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
8491 * Clear all pending SP commands as we are going to reset the
8494 bp->sp_rtnl_state = 0;
8497 bnx2x_parity_recover(bp);
8502 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
8504 * Clear all pending SP commands as we are going to reset the
8507 bp->sp_rtnl_state = 0;
8510 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
8511 bnx2x_nic_load(bp, LOAD_NORMAL);
8515 #ifdef BNX2X_STOP_ON_ERROR
8518 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
8519 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
8525 /* end of nic load/unload */
8527 static void bnx2x_period_task(struct work_struct *work)
8529 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
8531 if (!netif_running(bp->dev))
8532 goto period_task_exit;
8534 if (CHIP_REV_IS_SLOW(bp)) {
8535 BNX2X_ERR("period task called on emulation, ignoring\n");
8536 goto period_task_exit;
8539 bnx2x_acquire_phy_lock(bp);
8541 * The barrier is needed to ensure the ordering between the writing to
8542 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8547 bnx2x_period_func(&bp->link_params, &bp->link_vars);
8549 /* Re-queue task in 1 sec */
8550 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
8553 bnx2x_release_phy_lock(bp);
8559 * Init service functions
8562 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
8564 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
8565 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
8566 return base + (BP_ABS_FUNC(bp)) * stride;
8569 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
8571 u32 reg = bnx2x_get_pretend_reg(bp);
8573 /* Flush all outstanding writes */
8576 /* Pretend to be function 0 */
8578 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
8580 /* From now we are in the "like-E1" mode */
8581 bnx2x_int_disable(bp);
8583 /* Flush all outstanding writes */
8586 /* Restore the original function */
8587 REG_WR(bp, reg, BP_ABS_FUNC(bp));
8591 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
8594 bnx2x_int_disable(bp);
8596 bnx2x_undi_int_disable_e1h(bp);
8599 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
8603 /* Check if there is any driver already loaded */
8604 val = REG_RD(bp, MISC_REG_UNPREPARED);
8607 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8609 * Check if it is the UNDI driver
8610 * UNDI driver initializes CID offset for normal bell to 0x7
8612 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
8614 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8615 /* save our pf_num */
8616 int orig_pf_num = bp->pf_num;
8618 u32 swap_en, swap_val, value;
8620 /* clear the UNDI indication */
8621 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
8623 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8625 /* try unload UNDI on port 0 */
8628 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8629 DRV_MSG_SEQ_NUMBER_MASK);
8630 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8632 /* if UNDI is loaded on the other port */
8633 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
8635 /* send "DONE" for previous unload */
8636 bnx2x_fw_command(bp,
8637 DRV_MSG_CODE_UNLOAD_DONE, 0);
8639 /* unload UNDI on port 1 */
8642 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8643 DRV_MSG_SEQ_NUMBER_MASK);
8644 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8646 bnx2x_fw_command(bp, reset_code, 0);
8649 bnx2x_undi_int_disable(bp);
8652 /* close input traffic and wait for it */
8653 /* Do not rcv packets to BRB */
8654 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
8655 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
8656 /* Do not direct rcv packets that are not for MCP to
8658 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8659 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8661 REG_WR(bp, (port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8662 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
8665 /* save NIG port swap info */
8666 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
8667 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
8670 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8674 if (CHIP_IS_E3(bp)) {
8675 value |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
8676 value |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
8680 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8683 /* take the NIG out of reset and restore swap values */
8685 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
8686 MISC_REGISTERS_RESET_REG_1_RST_NIG);
8687 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
8688 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
8690 /* send unload done to the MCP */
8691 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8693 /* restore our func and fw_seq */
8694 bp->pf_num = orig_pf_num;
8696 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
8697 DRV_MSG_SEQ_NUMBER_MASK);
8700 /* now it's safe to release the lock */
8701 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
8705 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8707 u32 val, val2, val3, val4, id;
8710 /* Get the chip revision id and number. */
8711 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8712 val = REG_RD(bp, MISC_REG_CHIP_NUM);
8713 id = ((val & 0xffff) << 16);
8714 val = REG_RD(bp, MISC_REG_CHIP_REV);
8715 id |= ((val & 0xf) << 12);
8716 val = REG_RD(bp, MISC_REG_CHIP_METAL);
8717 id |= ((val & 0xff) << 4);
8718 val = REG_RD(bp, MISC_REG_BOND_ID);
8720 bp->common.chip_id = id;
8722 /* Set doorbell size */
8723 bp->db_size = (1 << BNX2X_DB_SHIFT);
8725 if (!CHIP_IS_E1x(bp)) {
8726 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
8728 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
8730 val = (val >> 1) & 1;
8731 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
8733 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
8736 if (CHIP_MODE_IS_4_PORT(bp))
8737 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
8739 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
8741 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
8742 bp->pfid = bp->pf_num; /* 0..7 */
8745 bp->link_params.chip_id = bp->common.chip_id;
8746 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
8748 val = (REG_RD(bp, 0x2874) & 0x55);
8749 if ((bp->common.chip_id & 0x1) ||
8750 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
8751 bp->flags |= ONE_PORT_FLAG;
8752 BNX2X_DEV_INFO("single port device\n");
8755 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
8756 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
8757 (val & MCPR_NVM_CFG4_FLASH_SIZE));
8758 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8759 bp->common.flash_size, bp->common.flash_size);
8761 bnx2x_init_shmem(bp);
8765 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
8766 MISC_REG_GENERIC_CR_1 :
8767 MISC_REG_GENERIC_CR_0));
8769 bp->link_params.shmem_base = bp->common.shmem_base;
8770 bp->link_params.shmem2_base = bp->common.shmem2_base;
8771 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8772 bp->common.shmem_base, bp->common.shmem2_base);
8774 if (!bp->common.shmem_base) {
8775 BNX2X_DEV_INFO("MCP not active\n");
8776 bp->flags |= NO_MCP_FLAG;
8780 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
8781 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
8783 bp->link_params.hw_led_mode = ((bp->common.hw_config &
8784 SHARED_HW_CFG_LED_MODE_MASK) >>
8785 SHARED_HW_CFG_LED_MODE_SHIFT);
8787 bp->link_params.feature_config_flags = 0;
8788 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
8789 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
8790 bp->link_params.feature_config_flags |=
8791 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8793 bp->link_params.feature_config_flags &=
8794 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
8796 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
8797 bp->common.bc_ver = val;
8798 BNX2X_DEV_INFO("bc_ver %X\n", val);
8799 if (val < BNX2X_BC_VER) {
8800 /* for now only warn
8801 * later we might need to enforce this */
8802 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
8803 "please upgrade BC\n", BNX2X_BC_VER, val);
8805 bp->link_params.feature_config_flags |=
8806 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
8807 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
8809 bp->link_params.feature_config_flags |=
8810 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
8811 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
8813 bp->link_params.feature_config_flags |=
8814 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
8815 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
8817 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
8818 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
8820 BNX2X_DEV_INFO("%sWoL capable\n",
8821 (bp->flags & NO_WOL_FLAG) ? "not " : "");
8823 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
8824 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
8825 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
8826 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
8828 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
8829 val, val2, val3, val4);
8832 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
8833 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
8835 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8837 int pfid = BP_FUNC(bp);
8840 u8 fid, igu_sb_cnt = 0;
8842 bp->igu_base_sb = 0xff;
8843 if (CHIP_INT_MODE_IS_BC(bp)) {
8845 igu_sb_cnt = bp->igu_sb_cnt;
8846 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8849 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
8850 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
8855 /* IGU in normal mode - read CAM */
8856 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
8858 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
8859 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
8862 if ((fid & IGU_FID_ENCODE_IS_PF)) {
8863 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
8865 if (IGU_VEC(val) == 0)
8866 /* default status block */
8867 bp->igu_dsb_id = igu_sb_id;
8869 if (bp->igu_base_sb == 0xff)
8870 bp->igu_base_sb = igu_sb_id;
8876 #ifdef CONFIG_PCI_MSI
8878 * It's expected that number of CAM entries for this functions is equal
8879 * to the number evaluated based on the MSI-X table size. We want a
8880 * harsh warning if these values are different!
8882 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
8885 if (igu_sb_cnt == 0)
8886 BNX2X_ERR("CAM configuration error\n");
8889 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
8892 int cfg_size = 0, idx, port = BP_PORT(bp);
8894 /* Aggregation of supported attributes of all external phys */
8895 bp->port.supported[0] = 0;
8896 bp->port.supported[1] = 0;
8897 switch (bp->link_params.num_phys) {
8899 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
8903 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
8907 if (bp->link_params.multi_phy_config &
8908 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
8909 bp->port.supported[1] =
8910 bp->link_params.phy[EXT_PHY1].supported;
8911 bp->port.supported[0] =
8912 bp->link_params.phy[EXT_PHY2].supported;
8914 bp->port.supported[0] =
8915 bp->link_params.phy[EXT_PHY1].supported;
8916 bp->port.supported[1] =
8917 bp->link_params.phy[EXT_PHY2].supported;
8923 if (!(bp->port.supported[0] || bp->port.supported[1])) {
8924 BNX2X_ERR("NVRAM config error. BAD phy config."
8925 "PHY1 config 0x%x, PHY2 config 0x%x\n",
8927 dev_info.port_hw_config[port].external_phy_config),
8929 dev_info.port_hw_config[port].external_phy_config2));
8934 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
8936 switch (switch_cfg) {
8938 bp->port.phy_addr = REG_RD(
8939 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
8941 case SWITCH_CFG_10G:
8942 bp->port.phy_addr = REG_RD(
8943 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
8946 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8947 bp->port.link_config[0]);
8951 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8952 /* mask what we support according to speed_cap_mask per configuration */
8953 for (idx = 0; idx < cfg_size; idx++) {
8954 if (!(bp->link_params.speed_cap_mask[idx] &
8955 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8956 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8958 if (!(bp->link_params.speed_cap_mask[idx] &
8959 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8960 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8962 if (!(bp->link_params.speed_cap_mask[idx] &
8963 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8964 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8966 if (!(bp->link_params.speed_cap_mask[idx] &
8967 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8968 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8970 if (!(bp->link_params.speed_cap_mask[idx] &
8971 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8972 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8973 SUPPORTED_1000baseT_Full);
8975 if (!(bp->link_params.speed_cap_mask[idx] &
8976 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8977 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8979 if (!(bp->link_params.speed_cap_mask[idx] &
8980 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8981 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8985 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8986 bp->port.supported[1]);
8989 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8991 u32 link_config, idx, cfg_size = 0;
8992 bp->port.advertising[0] = 0;
8993 bp->port.advertising[1] = 0;
8994 switch (bp->link_params.num_phys) {
9003 for (idx = 0; idx < cfg_size; idx++) {
9004 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9005 link_config = bp->port.link_config[idx];
9006 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9007 case PORT_FEATURE_LINK_SPEED_AUTO:
9008 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9009 bp->link_params.req_line_speed[idx] =
9011 bp->port.advertising[idx] |=
9012 bp->port.supported[idx];
9014 /* force 10G, no AN */
9015 bp->link_params.req_line_speed[idx] =
9017 bp->port.advertising[idx] |=
9018 (ADVERTISED_10000baseT_Full |
9024 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9025 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9026 bp->link_params.req_line_speed[idx] =
9028 bp->port.advertising[idx] |=
9029 (ADVERTISED_10baseT_Full |
9032 BNX2X_ERR("NVRAM config error. "
9033 "Invalid link_config 0x%x"
9034 " speed_cap_mask 0x%x\n",
9036 bp->link_params.speed_cap_mask[idx]);
9041 case PORT_FEATURE_LINK_SPEED_10M_HALF:
9042 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
9043 bp->link_params.req_line_speed[idx] =
9045 bp->link_params.req_duplex[idx] =
9047 bp->port.advertising[idx] |=
9048 (ADVERTISED_10baseT_Half |
9051 BNX2X_ERR("NVRAM config error. "
9052 "Invalid link_config 0x%x"
9053 " speed_cap_mask 0x%x\n",
9055 bp->link_params.speed_cap_mask[idx]);
9060 case PORT_FEATURE_LINK_SPEED_100M_FULL:
9061 if (bp->port.supported[idx] &
9062 SUPPORTED_100baseT_Full) {
9063 bp->link_params.req_line_speed[idx] =
9065 bp->port.advertising[idx] |=
9066 (ADVERTISED_100baseT_Full |
9069 BNX2X_ERR("NVRAM config error. "
9070 "Invalid link_config 0x%x"
9071 " speed_cap_mask 0x%x\n",
9073 bp->link_params.speed_cap_mask[idx]);
9078 case PORT_FEATURE_LINK_SPEED_100M_HALF:
9079 if (bp->port.supported[idx] &
9080 SUPPORTED_100baseT_Half) {
9081 bp->link_params.req_line_speed[idx] =
9083 bp->link_params.req_duplex[idx] =
9085 bp->port.advertising[idx] |=
9086 (ADVERTISED_100baseT_Half |
9089 BNX2X_ERR("NVRAM config error. "
9090 "Invalid link_config 0x%x"
9091 " speed_cap_mask 0x%x\n",
9093 bp->link_params.speed_cap_mask[idx]);
9098 case PORT_FEATURE_LINK_SPEED_1G:
9099 if (bp->port.supported[idx] &
9100 SUPPORTED_1000baseT_Full) {
9101 bp->link_params.req_line_speed[idx] =
9103 bp->port.advertising[idx] |=
9104 (ADVERTISED_1000baseT_Full |
9107 BNX2X_ERR("NVRAM config error. "
9108 "Invalid link_config 0x%x"
9109 " speed_cap_mask 0x%x\n",
9111 bp->link_params.speed_cap_mask[idx]);
9116 case PORT_FEATURE_LINK_SPEED_2_5G:
9117 if (bp->port.supported[idx] &
9118 SUPPORTED_2500baseX_Full) {
9119 bp->link_params.req_line_speed[idx] =
9121 bp->port.advertising[idx] |=
9122 (ADVERTISED_2500baseX_Full |
9125 BNX2X_ERR("NVRAM config error. "
9126 "Invalid link_config 0x%x"
9127 " speed_cap_mask 0x%x\n",
9129 bp->link_params.speed_cap_mask[idx]);
9134 case PORT_FEATURE_LINK_SPEED_10G_CX4:
9135 if (bp->port.supported[idx] &
9136 SUPPORTED_10000baseT_Full) {
9137 bp->link_params.req_line_speed[idx] =
9139 bp->port.advertising[idx] |=
9140 (ADVERTISED_10000baseT_Full |
9143 BNX2X_ERR("NVRAM config error. "
9144 "Invalid link_config 0x%x"
9145 " speed_cap_mask 0x%x\n",
9147 bp->link_params.speed_cap_mask[idx]);
9151 case PORT_FEATURE_LINK_SPEED_20G:
9152 bp->link_params.req_line_speed[idx] = SPEED_20000;
9156 BNX2X_ERR("NVRAM config error. "
9157 "BAD link speed link_config 0x%x\n",
9159 bp->link_params.req_line_speed[idx] =
9161 bp->port.advertising[idx] =
9162 bp->port.supported[idx];
9166 bp->link_params.req_flow_ctrl[idx] = (link_config &
9167 PORT_FEATURE_FLOW_CONTROL_MASK);
9168 if ((bp->link_params.req_flow_ctrl[idx] ==
9169 BNX2X_FLOW_CTRL_AUTO) &&
9170 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
9171 bp->link_params.req_flow_ctrl[idx] =
9172 BNX2X_FLOW_CTRL_NONE;
9175 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
9176 " 0x%x advertising 0x%x\n",
9177 bp->link_params.req_line_speed[idx],
9178 bp->link_params.req_duplex[idx],
9179 bp->link_params.req_flow_ctrl[idx],
9180 bp->port.advertising[idx]);
9184 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
9186 mac_hi = cpu_to_be16(mac_hi);
9187 mac_lo = cpu_to_be32(mac_lo);
9188 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
9189 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
9192 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
9194 int port = BP_PORT(bp);
9196 u32 ext_phy_type, ext_phy_config;
9198 bp->link_params.bp = bp;
9199 bp->link_params.port = port;
9201 bp->link_params.lane_config =
9202 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
9204 bp->link_params.speed_cap_mask[0] =
9206 dev_info.port_hw_config[port].speed_capability_mask);
9207 bp->link_params.speed_cap_mask[1] =
9209 dev_info.port_hw_config[port].speed_capability_mask2);
9210 bp->port.link_config[0] =
9211 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
9213 bp->port.link_config[1] =
9214 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
9216 bp->link_params.multi_phy_config =
9217 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
9218 /* If the device is capable of WoL, set the default state according
9221 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
9222 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
9223 (config & PORT_FEATURE_WOL_ENABLED));
9225 BNX2X_DEV_INFO("lane_config 0x%08x "
9226 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9227 bp->link_params.lane_config,
9228 bp->link_params.speed_cap_mask[0],
9229 bp->port.link_config[0]);
9231 bp->link_params.switch_cfg = (bp->port.link_config[0] &
9232 PORT_FEATURE_CONNECTED_SWITCH_MASK);
9233 bnx2x_phy_probe(&bp->link_params);
9234 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
9236 bnx2x_link_settings_requested(bp);
9239 * If connected directly, work with the internal PHY, otherwise, work
9240 * with the external PHY
9244 dev_info.port_hw_config[port].external_phy_config);
9245 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
9246 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9247 bp->mdio.prtad = bp->port.phy_addr;
9249 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
9250 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
9252 XGXS_EXT_PHY_ADDR(ext_phy_config);
9255 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9256 * In MF mode, it is set to cover self test cases
9259 bp->port.need_hw_lock = 1;
9261 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
9262 bp->common.shmem_base,
9263 bp->common.shmem2_base);
9267 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
9269 int port = BP_PORT(bp);
9270 int func = BP_ABS_FUNC(bp);
9272 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9273 drv_lic_key[port].max_iscsi_conn);
9274 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
9275 drv_lic_key[port].max_fcoe_conn);
9277 /* Get the number of maximum allowed iSCSI and FCoE connections */
9278 bp->cnic_eth_dev.max_iscsi_conn =
9279 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
9280 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
9282 bp->cnic_eth_dev.max_fcoe_conn =
9283 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
9284 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
9289 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9291 dev_info.port_hw_config[port].
9292 fcoe_wwn_port_name_upper);
9293 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9295 dev_info.port_hw_config[port].
9296 fcoe_wwn_port_name_lower);
9299 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9301 dev_info.port_hw_config[port].
9302 fcoe_wwn_node_name_upper);
9303 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9305 dev_info.port_hw_config[port].
9306 fcoe_wwn_node_name_lower);
9307 } else if (!IS_MF_SD(bp)) {
9308 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9311 * Read the WWN info only if the FCoE feature is enabled for
9314 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9316 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
9317 MF_CFG_RD(bp, func_ext_config[func].
9318 fcoe_wwn_port_name_upper);
9319 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
9320 MF_CFG_RD(bp, func_ext_config[func].
9321 fcoe_wwn_port_name_lower);
9324 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
9325 MF_CFG_RD(bp, func_ext_config[func].
9326 fcoe_wwn_node_name_upper);
9327 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
9328 MF_CFG_RD(bp, func_ext_config[func].
9329 fcoe_wwn_node_name_lower);
9333 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
9334 bp->cnic_eth_dev.max_iscsi_conn,
9335 bp->cnic_eth_dev.max_fcoe_conn);
9338 * If maximum allowed number of connections is zero -
9339 * disable the feature.
9341 if (!bp->cnic_eth_dev.max_iscsi_conn)
9342 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9344 if (!bp->cnic_eth_dev.max_fcoe_conn)
9345 bp->flags |= NO_FCOE_FLAG;
9349 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
9352 int func = BP_ABS_FUNC(bp);
9353 int port = BP_PORT(bp);
9355 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
9356 u8 *fip_mac = bp->fip_mac;
9359 /* Zero primary MAC configuration */
9360 memset(bp->dev->dev_addr, 0, ETH_ALEN);
9363 BNX2X_ERROR("warning: random MAC workaround active\n");
9364 random_ether_addr(bp->dev->dev_addr);
9365 } else if (IS_MF(bp)) {
9366 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
9367 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
9368 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
9369 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
9370 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9373 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9374 * FCoE MAC then the appropriate feature should be disabled.
9377 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
9378 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
9379 val2 = MF_CFG_RD(bp, func_ext_config[func].
9380 iscsi_mac_addr_upper);
9381 val = MF_CFG_RD(bp, func_ext_config[func].
9382 iscsi_mac_addr_lower);
9383 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9384 BNX2X_DEV_INFO("Read iSCSI MAC: "
9386 BNX2X_MAC_PRN_LIST(iscsi_mac));
9388 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
9390 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
9391 val2 = MF_CFG_RD(bp, func_ext_config[func].
9392 fcoe_mac_addr_upper);
9393 val = MF_CFG_RD(bp, func_ext_config[func].
9394 fcoe_mac_addr_lower);
9395 bnx2x_set_mac_buf(fip_mac, val, val2);
9396 BNX2X_DEV_INFO("Read FCoE L2 MAC to "
9398 BNX2X_MAC_PRN_LIST(fip_mac));
9401 bp->flags |= NO_FCOE_FLAG;
9405 /* in SF read MACs from port configuration */
9406 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
9407 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
9408 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
9411 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9413 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9415 bnx2x_set_mac_buf(iscsi_mac, val, val2);
9417 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
9418 fcoe_fip_mac_upper);
9419 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
9420 fcoe_fip_mac_lower);
9421 bnx2x_set_mac_buf(fip_mac, val, val2);
9425 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
9426 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
9429 /* Set the FCoE MAC in MF_SD mode */
9430 if (!CHIP_IS_E1x(bp) && IS_MF_SD(bp))
9431 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
9433 /* Disable iSCSI if MAC configuration is
9436 if (!is_valid_ether_addr(iscsi_mac)) {
9437 bp->flags |= NO_ISCSI_FLAG;
9438 memset(iscsi_mac, 0, ETH_ALEN);
9441 /* Disable FCoE if MAC configuration is
9444 if (!is_valid_ether_addr(fip_mac)) {
9445 bp->flags |= NO_FCOE_FLAG;
9446 memset(bp->fip_mac, 0, ETH_ALEN);
9450 if (!is_valid_ether_addr(bp->dev->dev_addr))
9451 dev_err(&bp->pdev->dev,
9452 "bad Ethernet MAC address configuration: "
9453 BNX2X_MAC_FMT", change it manually before bringing up "
9454 "the appropriate network interface\n",
9455 BNX2X_MAC_PRN_LIST(bp->dev->dev_addr));
9458 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9460 int /*abs*/func = BP_ABS_FUNC(bp);
9465 bnx2x_get_common_hwinfo(bp);
9468 * initialize IGU parameters
9470 if (CHIP_IS_E1x(bp)) {
9471 bp->common.int_block = INT_BLOCK_HC;
9473 bp->igu_dsb_id = DEF_SB_IGU_ID;
9474 bp->igu_base_sb = 0;
9476 bp->common.int_block = INT_BLOCK_IGU;
9478 /* do not allow device reset during IGU info preocessing */
9479 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9481 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9483 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9486 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9488 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
9489 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
9490 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
9492 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9494 usleep_range(1000, 1000);
9497 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
9498 dev_err(&bp->pdev->dev,
9499 "FORCING Normal Mode failed!!!\n");
9504 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
9505 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9506 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
9508 BNX2X_DEV_INFO("IGU Normal Mode\n");
9510 bnx2x_get_igu_cam_info(bp);
9512 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
9516 * set base FW non-default (fast path) status block id, this value is
9517 * used to initialize the fw_sb_id saved on the fp/queue structure to
9518 * determine the id used by the FW.
9520 if (CHIP_IS_E1x(bp))
9521 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
9523 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9524 * the same queue are indicated on the same IGU SB). So we prefer
9525 * FW and IGU SBs to be the same value.
9527 bp->base_fw_ndsb = bp->igu_base_sb;
9529 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9530 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
9531 bp->igu_sb_cnt, bp->base_fw_ndsb);
9534 * Initialize MF configuration
9541 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9542 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9543 bp->common.shmem2_base, SHMEM2_RD(bp, size),
9544 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
9546 if (SHMEM2_HAS(bp, mf_cfg_addr))
9547 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
9549 bp->common.mf_cfg_base = bp->common.shmem_base +
9550 offsetof(struct shmem_region, func_mb) +
9551 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
9553 * get mf configuration:
9554 * 1. existence of MF configuration
9555 * 2. MAC address must be legal (check only upper bytes)
9556 * for Switch-Independent mode;
9557 * OVLAN must be legal for Switch-Dependent mode
9558 * 3. SF_MODE configures specific MF mode
9560 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9561 /* get mf configuration */
9563 dev_info.shared_feature_config.config);
9564 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
9567 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
9568 val = MF_CFG_RD(bp, func_mf_config[func].
9570 /* check for legal mac (upper bytes)*/
9571 if (val != 0xffff) {
9572 bp->mf_mode = MULTI_FUNCTION_SI;
9573 bp->mf_config[vn] = MF_CFG_RD(bp,
9574 func_mf_config[func].config);
9576 BNX2X_DEV_INFO("illegal MAC address "
9579 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
9580 /* get OV configuration */
9582 func_mf_config[FUNC_0].e1hov_tag);
9583 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
9585 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9586 bp->mf_mode = MULTI_FUNCTION_SD;
9587 bp->mf_config[vn] = MF_CFG_RD(bp,
9588 func_mf_config[func].config);
9590 BNX2X_DEV_INFO("illegal OV for SD\n");
9593 /* Unknown configuration: reset mf_config */
9594 bp->mf_config[vn] = 0;
9595 BNX2X_DEV_INFO("unkown MF mode 0x%x\n", val);
9599 BNX2X_DEV_INFO("%s function mode\n",
9600 IS_MF(bp) ? "multi" : "single");
9602 switch (bp->mf_mode) {
9603 case MULTI_FUNCTION_SD:
9604 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
9605 FUNC_MF_CFG_E1HOV_TAG_MASK;
9606 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
9608 bp->path_has_ovlan = true;
9610 BNX2X_DEV_INFO("MF OV for func %d is %d "
9611 "(0x%04x)\n", func, bp->mf_ov,
9614 dev_err(&bp->pdev->dev,
9615 "No valid MF OV for func %d, "
9616 "aborting\n", func);
9620 case MULTI_FUNCTION_SI:
9621 BNX2X_DEV_INFO("func %d is in MF "
9622 "switch-independent mode\n", func);
9626 dev_err(&bp->pdev->dev,
9627 "VN %d is in a single function mode, "
9634 /* check if other port on the path needs ovlan:
9635 * Since MF configuration is shared between ports
9636 * Possible mixed modes are only
9637 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9639 if (CHIP_MODE_IS_4_PORT(bp) &&
9640 !bp->path_has_ovlan &&
9642 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
9643 u8 other_port = !BP_PORT(bp);
9644 u8 other_func = BP_PATH(bp) + 2*other_port;
9646 func_mf_config[other_func].e1hov_tag);
9647 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
9648 bp->path_has_ovlan = true;
9652 /* adjust igu_sb_cnt to MF for E1x */
9653 if (CHIP_IS_E1x(bp) && IS_MF(bp))
9654 bp->igu_sb_cnt /= E1HVN_MAX;
9657 bnx2x_get_port_hwinfo(bp);
9659 /* Get MAC addresses */
9660 bnx2x_get_mac_hwinfo(bp);
9663 bnx2x_get_cnic_info(bp);
9666 /* Get current FW pulse sequence */
9667 if (!BP_NOMCP(bp)) {
9668 int mb_idx = BP_FW_MB_IDX(bp);
9670 bp->fw_drv_pulse_wr_seq =
9671 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
9672 DRV_PULSE_SEQ_MASK);
9673 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
9679 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
9681 int cnt, i, block_end, rodi;
9682 char vpd_data[BNX2X_VPD_LEN+1];
9683 char str_id_reg[VENDOR_ID_LEN+1];
9684 char str_id_cap[VENDOR_ID_LEN+1];
9687 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
9688 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
9690 if (cnt < BNX2X_VPD_LEN)
9693 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
9694 PCI_VPD_LRDT_RO_DATA);
9699 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
9700 pci_vpd_lrdt_size(&vpd_data[i]);
9702 i += PCI_VPD_LRDT_TAG_SIZE;
9704 if (block_end > BNX2X_VPD_LEN)
9707 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9708 PCI_VPD_RO_KEYWORD_MFR_ID);
9712 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9714 if (len != VENDOR_ID_LEN)
9717 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9719 /* vendor specific info */
9720 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
9721 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
9722 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
9723 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
9725 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
9726 PCI_VPD_RO_KEYWORD_VENDOR0);
9728 len = pci_vpd_info_field_size(&vpd_data[rodi]);
9730 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
9732 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
9733 memcpy(bp->fw_ver, &vpd_data[rodi], len);
9734 bp->fw_ver[len] = ' ';
9743 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
9747 if (CHIP_REV_IS_FPGA(bp))
9748 SET_FLAGS(flags, MODE_FPGA);
9749 else if (CHIP_REV_IS_EMUL(bp))
9750 SET_FLAGS(flags, MODE_EMUL);
9752 SET_FLAGS(flags, MODE_ASIC);
9754 if (CHIP_MODE_IS_4_PORT(bp))
9755 SET_FLAGS(flags, MODE_PORT4);
9757 SET_FLAGS(flags, MODE_PORT2);
9760 SET_FLAGS(flags, MODE_E2);
9761 else if (CHIP_IS_E3(bp)) {
9762 SET_FLAGS(flags, MODE_E3);
9763 if (CHIP_REV(bp) == CHIP_REV_Ax)
9764 SET_FLAGS(flags, MODE_E3_A0);
9765 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
9766 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
9770 SET_FLAGS(flags, MODE_MF);
9771 switch (bp->mf_mode) {
9772 case MULTI_FUNCTION_SD:
9773 SET_FLAGS(flags, MODE_MF_SD);
9775 case MULTI_FUNCTION_SI:
9776 SET_FLAGS(flags, MODE_MF_SI);
9780 SET_FLAGS(flags, MODE_SF);
9782 #if defined(__LITTLE_ENDIAN)
9783 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
9784 #else /*(__BIG_ENDIAN)*/
9785 SET_FLAGS(flags, MODE_BIG_ENDIAN);
9787 INIT_MODE_FLAGS(bp) = flags;
9790 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
9796 mutex_init(&bp->port.phy_mutex);
9797 mutex_init(&bp->fw_mb_mutex);
9798 spin_lock_init(&bp->stats_lock);
9800 mutex_init(&bp->cnic_mutex);
9803 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
9804 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
9805 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
9806 rc = bnx2x_get_hwinfo(bp);
9810 bnx2x_set_modes_bitmap(bp);
9812 rc = bnx2x_alloc_mem_bp(bp);
9816 bnx2x_read_fwinfo(bp);
9820 /* need to reset chip if undi was active */
9822 bnx2x_undi_unload(bp);
9824 /* init fw_seq after undi_unload! */
9825 if (!BP_NOMCP(bp)) {
9827 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9828 DRV_MSG_SEQ_NUMBER_MASK);
9829 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9832 if (CHIP_REV_IS_FPGA(bp))
9833 dev_err(&bp->pdev->dev, "FPGA detected\n");
9835 if (BP_NOMCP(bp) && (func == 0))
9836 dev_err(&bp->pdev->dev, "MCP disabled, "
9837 "must load devices in order!\n");
9839 bp->multi_mode = multi_mode;
9843 bp->flags &= ~TPA_ENABLE_FLAG;
9844 bp->dev->features &= ~NETIF_F_LRO;
9846 bp->flags |= TPA_ENABLE_FLAG;
9847 bp->dev->features |= NETIF_F_LRO;
9849 bp->disable_tpa = disable_tpa;
9852 bp->dropless_fc = 0;
9854 bp->dropless_fc = dropless_fc;
9858 bp->tx_ring_size = MAX_TX_AVAIL;
9860 /* make sure that the numbers are in the right granularity */
9861 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
9862 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
9864 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
9865 bp->current_interval = (poll ? poll : timer_interval);
9867 init_timer(&bp->timer);
9868 bp->timer.expires = jiffies + bp->current_interval;
9869 bp->timer.data = (unsigned long) bp;
9870 bp->timer.function = bnx2x_timer;
9872 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
9873 bnx2x_dcbx_init_params(bp);
9876 if (CHIP_IS_E1x(bp))
9877 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
9879 bp->cnic_base_cl_id = FP_SB_MAX_E2;
9882 /* multiple tx priority */
9883 if (CHIP_IS_E1x(bp))
9884 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
9885 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
9886 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
9887 if (CHIP_IS_E3B0(bp))
9888 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
9894 /****************************************************************************
9895 * General service functions
9896 ****************************************************************************/
9899 * net_device service functions
9902 /* called with rtnl_lock */
9903 static int bnx2x_open(struct net_device *dev)
9905 struct bnx2x *bp = netdev_priv(dev);
9906 bool global = false;
9907 int other_engine = BP_PATH(bp) ? 0 : 1;
9908 u32 other_load_counter, load_counter;
9910 netif_carrier_off(dev);
9912 bnx2x_set_power_state(bp, PCI_D0);
9914 other_load_counter = bnx2x_get_load_cnt(bp, other_engine);
9915 load_counter = bnx2x_get_load_cnt(bp, BP_PATH(bp));
9918 * If parity had happen during the unload, then attentions
9919 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
9920 * want the first function loaded on the current engine to
9921 * complete the recovery.
9923 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
9924 bnx2x_chk_parity_attn(bp, &global, true))
9927 * If there are attentions and they are in a global
9928 * blocks, set the GLOBAL_RESET bit regardless whether
9929 * it will be this function that will complete the
9933 bnx2x_set_reset_global(bp);
9936 * Only the first function on the current engine should
9937 * try to recover in open. In case of attentions in
9938 * global blocks only the first in the chip should try
9941 if ((!load_counter &&
9942 (!global || !other_load_counter)) &&
9943 bnx2x_trylock_leader_lock(bp) &&
9944 !bnx2x_leader_reset(bp)) {
9945 netdev_info(bp->dev, "Recovered in open\n");
9949 /* recovery has failed... */
9950 bnx2x_set_power_state(bp, PCI_D3hot);
9951 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9953 netdev_err(bp->dev, "Recovery flow hasn't been properly"
9954 " completed yet. Try again later. If u still see this"
9955 " message after a few retries then power cycle is"
9961 bp->recovery_state = BNX2X_RECOVERY_DONE;
9962 return bnx2x_nic_load(bp, LOAD_OPEN);
9965 /* called with rtnl_lock */
9966 static int bnx2x_close(struct net_device *dev)
9968 struct bnx2x *bp = netdev_priv(dev);
9970 /* Unload the driver, release IRQs */
9971 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
9974 bnx2x_set_power_state(bp, PCI_D3hot);
9979 static inline int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
9980 struct bnx2x_mcast_ramrod_params *p)
9982 int mc_count = netdev_mc_count(bp->dev);
9983 struct bnx2x_mcast_list_elem *mc_mac =
9984 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
9985 struct netdev_hw_addr *ha;
9990 INIT_LIST_HEAD(&p->mcast_list);
9992 netdev_for_each_mc_addr(ha, bp->dev) {
9993 mc_mac->mac = bnx2x_mc_addr(ha);
9994 list_add_tail(&mc_mac->link, &p->mcast_list);
9998 p->mcast_list_len = mc_count;
10003 static inline void bnx2x_free_mcast_macs_list(
10004 struct bnx2x_mcast_ramrod_params *p)
10006 struct bnx2x_mcast_list_elem *mc_mac =
10007 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
10015 * bnx2x_set_uc_list - configure a new unicast MACs list.
10017 * @bp: driver handle
10019 * We will use zero (0) as a MAC type for these MACs.
10021 static inline int bnx2x_set_uc_list(struct bnx2x *bp)
10024 struct net_device *dev = bp->dev;
10025 struct netdev_hw_addr *ha;
10026 struct bnx2x_vlan_mac_obj *mac_obj = &bp->fp->mac_obj;
10027 unsigned long ramrod_flags = 0;
10029 /* First schedule a cleanup up of old configuration */
10030 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
10032 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
10036 netdev_for_each_uc_addr(ha, dev) {
10037 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
10038 BNX2X_UC_LIST_MAC, &ramrod_flags);
10040 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10046 /* Execute the pending commands */
10047 __set_bit(RAMROD_CONT, &ramrod_flags);
10048 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
10049 BNX2X_UC_LIST_MAC, &ramrod_flags);
10052 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
10054 struct net_device *dev = bp->dev;
10055 struct bnx2x_mcast_ramrod_params rparam = {0};
10058 rparam.mcast_obj = &bp->mcast_obj;
10060 /* first, clear all configured multicast MACs */
10061 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
10063 BNX2X_ERR("Failed to clear multicast "
10064 "configuration: %d\n", rc);
10068 /* then, configure a new MACs list */
10069 if (netdev_mc_count(dev)) {
10070 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
10072 BNX2X_ERR("Failed to create multicast MACs "
10077 /* Now add the new MACs */
10078 rc = bnx2x_config_mcast(bp, &rparam,
10079 BNX2X_MCAST_CMD_ADD);
10081 BNX2X_ERR("Failed to set a new multicast "
10082 "configuration: %d\n", rc);
10084 bnx2x_free_mcast_macs_list(&rparam);
10091 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10092 void bnx2x_set_rx_mode(struct net_device *dev)
10094 struct bnx2x *bp = netdev_priv(dev);
10095 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
10097 if (bp->state != BNX2X_STATE_OPEN) {
10098 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
10102 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
10104 if (dev->flags & IFF_PROMISC)
10105 rx_mode = BNX2X_RX_MODE_PROMISC;
10106 else if ((dev->flags & IFF_ALLMULTI) ||
10107 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
10109 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10111 /* some multicasts */
10112 if (bnx2x_set_mc_list(bp) < 0)
10113 rx_mode = BNX2X_RX_MODE_ALLMULTI;
10115 if (bnx2x_set_uc_list(bp) < 0)
10116 rx_mode = BNX2X_RX_MODE_PROMISC;
10119 bp->rx_mode = rx_mode;
10121 /* Schedule the rx_mode command */
10122 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
10123 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
10127 bnx2x_set_storm_rx_mode(bp);
10130 /* called with rtnl_lock */
10131 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
10132 int devad, u16 addr)
10134 struct bnx2x *bp = netdev_priv(netdev);
10138 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10139 prtad, devad, addr);
10141 /* The HW expects different devad if CL22 is used */
10142 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10144 bnx2x_acquire_phy_lock(bp);
10145 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
10146 bnx2x_release_phy_lock(bp);
10147 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
10154 /* called with rtnl_lock */
10155 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
10156 u16 addr, u16 value)
10158 struct bnx2x *bp = netdev_priv(netdev);
10161 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
10162 " value 0x%x\n", prtad, devad, addr, value);
10164 /* The HW expects different devad if CL22 is used */
10165 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
10167 bnx2x_acquire_phy_lock(bp);
10168 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
10169 bnx2x_release_phy_lock(bp);
10173 /* called with rtnl_lock */
10174 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10176 struct bnx2x *bp = netdev_priv(dev);
10177 struct mii_ioctl_data *mdio = if_mii(ifr);
10179 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10180 mdio->phy_id, mdio->reg_num, mdio->val_in);
10182 if (!netif_running(dev))
10185 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
10188 #ifdef CONFIG_NET_POLL_CONTROLLER
10189 static void poll_bnx2x(struct net_device *dev)
10191 struct bnx2x *bp = netdev_priv(dev);
10193 disable_irq(bp->pdev->irq);
10194 bnx2x_interrupt(bp->pdev->irq, dev);
10195 enable_irq(bp->pdev->irq);
10199 static const struct net_device_ops bnx2x_netdev_ops = {
10200 .ndo_open = bnx2x_open,
10201 .ndo_stop = bnx2x_close,
10202 .ndo_start_xmit = bnx2x_start_xmit,
10203 .ndo_select_queue = bnx2x_select_queue,
10204 .ndo_set_rx_mode = bnx2x_set_rx_mode,
10205 .ndo_set_mac_address = bnx2x_change_mac_addr,
10206 .ndo_validate_addr = eth_validate_addr,
10207 .ndo_do_ioctl = bnx2x_ioctl,
10208 .ndo_change_mtu = bnx2x_change_mtu,
10209 .ndo_fix_features = bnx2x_fix_features,
10210 .ndo_set_features = bnx2x_set_features,
10211 .ndo_tx_timeout = bnx2x_tx_timeout,
10212 #ifdef CONFIG_NET_POLL_CONTROLLER
10213 .ndo_poll_controller = poll_bnx2x,
10215 .ndo_setup_tc = bnx2x_setup_tc,
10217 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10218 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
10222 static inline int bnx2x_set_coherency_mask(struct bnx2x *bp)
10224 struct device *dev = &bp->pdev->dev;
10226 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
10227 bp->flags |= USING_DAC_FLAG;
10228 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
10229 dev_err(dev, "dma_set_coherent_mask failed, "
10233 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
10234 dev_err(dev, "System does not support DMA, aborting\n");
10241 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
10242 struct net_device *dev,
10243 unsigned long board_type)
10248 SET_NETDEV_DEV(dev, &pdev->dev);
10249 bp = netdev_priv(dev);
10254 bp->pf_num = PCI_FUNC(pdev->devfn);
10256 rc = pci_enable_device(pdev);
10258 dev_err(&bp->pdev->dev,
10259 "Cannot enable PCI device, aborting\n");
10263 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10264 dev_err(&bp->pdev->dev,
10265 "Cannot find PCI device base address, aborting\n");
10267 goto err_out_disable;
10270 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
10271 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
10272 " base address, aborting\n");
10274 goto err_out_disable;
10277 if (atomic_read(&pdev->enable_cnt) == 1) {
10278 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
10280 dev_err(&bp->pdev->dev,
10281 "Cannot obtain PCI resources, aborting\n");
10282 goto err_out_disable;
10285 pci_set_master(pdev);
10286 pci_save_state(pdev);
10289 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10290 if (bp->pm_cap == 0) {
10291 dev_err(&bp->pdev->dev,
10292 "Cannot find power management capability, aborting\n");
10294 goto err_out_release;
10297 if (!pci_is_pcie(pdev)) {
10298 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
10300 goto err_out_release;
10303 rc = bnx2x_set_coherency_mask(bp);
10305 goto err_out_release;
10307 dev->mem_start = pci_resource_start(pdev, 0);
10308 dev->base_addr = dev->mem_start;
10309 dev->mem_end = pci_resource_end(pdev, 0);
10311 dev->irq = pdev->irq;
10313 bp->regview = pci_ioremap_bar(pdev, 0);
10314 if (!bp->regview) {
10315 dev_err(&bp->pdev->dev,
10316 "Cannot map register space, aborting\n");
10318 goto err_out_release;
10321 bnx2x_set_power_state(bp, PCI_D0);
10323 /* clean indirect addresses */
10324 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
10325 PCICFG_VENDOR_ID_OFFSET);
10327 * Clean the following indirect addresses for all functions since it
10328 * is not used by the driver.
10330 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
10331 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
10332 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
10333 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
10335 if (CHIP_IS_E1x(bp)) {
10336 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
10337 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
10338 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
10339 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
10343 * Enable internal target-read (in case we are probed after PF FLR).
10344 * Must be done prior to any BAR read access. Only for 57712 and up
10346 if (board_type != BCM57710 &&
10347 board_type != BCM57711 &&
10348 board_type != BCM57711E)
10349 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
10351 /* Reset the load counter */
10352 bnx2x_clear_load_cnt(bp);
10354 dev->watchdog_timeo = TX_TIMEOUT;
10356 dev->netdev_ops = &bnx2x_netdev_ops;
10357 bnx2x_set_ethtool_ops(dev);
10359 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10360 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
10361 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
10363 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
10364 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
10366 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
10367 if (bp->flags & USING_DAC_FLAG)
10368 dev->features |= NETIF_F_HIGHDMA;
10370 /* Add Loopback capability to the device */
10371 dev->hw_features |= NETIF_F_LOOPBACK;
10374 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
10377 /* get_port_hwinfo() will set prtad and mmds properly */
10378 bp->mdio.prtad = MDIO_PRTAD_NONE;
10380 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10381 bp->mdio.dev = dev;
10382 bp->mdio.mdio_read = bnx2x_mdio_read;
10383 bp->mdio.mdio_write = bnx2x_mdio_write;
10388 if (atomic_read(&pdev->enable_cnt) == 1)
10389 pci_release_regions(pdev);
10392 pci_disable_device(pdev);
10393 pci_set_drvdata(pdev, NULL);
10399 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
10400 int *width, int *speed)
10402 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
10404 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
10406 /* return value of 1=2.5GHz 2=5GHz */
10407 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
10410 static int bnx2x_check_firmware(struct bnx2x *bp)
10412 const struct firmware *firmware = bp->firmware;
10413 struct bnx2x_fw_file_hdr *fw_hdr;
10414 struct bnx2x_fw_file_section *sections;
10415 u32 offset, len, num_ops;
10420 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
10423 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
10424 sections = (struct bnx2x_fw_file_section *)fw_hdr;
10426 /* Make sure none of the offsets and sizes make us read beyond
10427 * the end of the firmware data */
10428 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
10429 offset = be32_to_cpu(sections[i].offset);
10430 len = be32_to_cpu(sections[i].len);
10431 if (offset + len > firmware->size) {
10432 dev_err(&bp->pdev->dev,
10433 "Section %d length is out of bounds\n", i);
10438 /* Likewise for the init_ops offsets */
10439 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
10440 ops_offsets = (u16 *)(firmware->data + offset);
10441 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
10443 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
10444 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
10445 dev_err(&bp->pdev->dev,
10446 "Section offset %d is out of bounds\n", i);
10451 /* Check FW version */
10452 offset = be32_to_cpu(fw_hdr->fw_version.offset);
10453 fw_ver = firmware->data + offset;
10454 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
10455 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
10456 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
10457 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
10458 dev_err(&bp->pdev->dev,
10459 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10460 fw_ver[0], fw_ver[1], fw_ver[2],
10461 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
10462 BCM_5710_FW_MINOR_VERSION,
10463 BCM_5710_FW_REVISION_VERSION,
10464 BCM_5710_FW_ENGINEERING_VERSION);
10471 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10473 const __be32 *source = (const __be32 *)_source;
10474 u32 *target = (u32 *)_target;
10477 for (i = 0; i < n/4; i++)
10478 target[i] = be32_to_cpu(source[i]);
10482 Ops array is stored in the following format:
10483 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10485 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
10487 const __be32 *source = (const __be32 *)_source;
10488 struct raw_op *target = (struct raw_op *)_target;
10491 for (i = 0, j = 0; i < n/8; i++, j += 2) {
10492 tmp = be32_to_cpu(source[j]);
10493 target[i].op = (tmp >> 24) & 0xff;
10494 target[i].offset = tmp & 0xffffff;
10495 target[i].raw_data = be32_to_cpu(source[j + 1]);
10500 * IRO array is stored in the following format:
10501 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10503 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
10505 const __be32 *source = (const __be32 *)_source;
10506 struct iro *target = (struct iro *)_target;
10509 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
10510 target[i].base = be32_to_cpu(source[j]);
10512 tmp = be32_to_cpu(source[j]);
10513 target[i].m1 = (tmp >> 16) & 0xffff;
10514 target[i].m2 = tmp & 0xffff;
10516 tmp = be32_to_cpu(source[j]);
10517 target[i].m3 = (tmp >> 16) & 0xffff;
10518 target[i].size = tmp & 0xffff;
10523 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
10525 const __be16 *source = (const __be16 *)_source;
10526 u16 *target = (u16 *)_target;
10529 for (i = 0; i < n/2; i++)
10530 target[i] = be16_to_cpu(source[i]);
10533 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10535 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10536 bp->arr = kmalloc(len, GFP_KERNEL); \
10538 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
10541 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10542 (u8 *)bp->arr, len); \
10545 int bnx2x_init_firmware(struct bnx2x *bp)
10547 const char *fw_file_name;
10548 struct bnx2x_fw_file_hdr *fw_hdr;
10551 if (CHIP_IS_E1(bp))
10552 fw_file_name = FW_FILE_NAME_E1;
10553 else if (CHIP_IS_E1H(bp))
10554 fw_file_name = FW_FILE_NAME_E1H;
10555 else if (!CHIP_IS_E1x(bp))
10556 fw_file_name = FW_FILE_NAME_E2;
10558 BNX2X_ERR("Unsupported chip revision\n");
10562 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
10564 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
10566 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
10567 goto request_firmware_exit;
10570 rc = bnx2x_check_firmware(bp);
10572 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
10573 goto request_firmware_exit;
10576 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
10578 /* Initialize the pointers to the init arrays */
10580 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
10583 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
10586 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
10589 /* STORMs firmware */
10590 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10591 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
10592 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
10593 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
10594 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10595 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
10596 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
10597 be32_to_cpu(fw_hdr->usem_pram_data.offset);
10598 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10599 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
10600 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
10601 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
10602 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
10603 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
10604 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
10605 be32_to_cpu(fw_hdr->csem_pram_data.offset);
10607 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
10612 kfree(bp->init_ops_offsets);
10613 init_offsets_alloc_err:
10614 kfree(bp->init_ops);
10615 init_ops_alloc_err:
10616 kfree(bp->init_data);
10617 request_firmware_exit:
10618 release_firmware(bp->firmware);
10623 static void bnx2x_release_firmware(struct bnx2x *bp)
10625 kfree(bp->init_ops_offsets);
10626 kfree(bp->init_ops);
10627 kfree(bp->init_data);
10628 release_firmware(bp->firmware);
10632 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
10633 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
10634 .init_hw_cmn = bnx2x_init_hw_common,
10635 .init_hw_port = bnx2x_init_hw_port,
10636 .init_hw_func = bnx2x_init_hw_func,
10638 .reset_hw_cmn = bnx2x_reset_common,
10639 .reset_hw_port = bnx2x_reset_port,
10640 .reset_hw_func = bnx2x_reset_func,
10642 .gunzip_init = bnx2x_gunzip_init,
10643 .gunzip_end = bnx2x_gunzip_end,
10645 .init_fw = bnx2x_init_firmware,
10646 .release_fw = bnx2x_release_firmware,
10649 void bnx2x__init_func_obj(struct bnx2x *bp)
10651 /* Prepare DMAE related driver resources */
10652 bnx2x_setup_dmae(bp);
10654 bnx2x_init_func_obj(bp, &bp->func_obj,
10655 bnx2x_sp(bp, func_rdata),
10656 bnx2x_sp_mapping(bp, func_rdata),
10657 &bnx2x_func_sp_drv);
10660 /* must be called after sriov-enable */
10661 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp)
10663 int cid_count = BNX2X_L2_CID_COUNT(bp);
10666 cid_count += CNIC_CID_MAX;
10668 return roundup(cid_count, QM_CID_ROUND);
10672 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10677 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
10682 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
10685 * If MSI-X is not supported - return number of SBs needed to support
10686 * one fast path queue: one FP queue + SB for CNIC
10689 return 1 + CNIC_PRESENT;
10692 * The value in the PCI configuration space is the index of the last
10693 * entry, namely one less than the actual size of the table, which is
10694 * exactly what we want to return from this function: number of all SBs
10695 * without the default SB.
10697 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
10698 return control & PCI_MSIX_FLAGS_QSIZE;
10701 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
10702 const struct pci_device_id *ent)
10704 struct net_device *dev = NULL;
10706 int pcie_width, pcie_speed;
10707 int rc, max_non_def_sbs;
10708 int rx_count, tx_count, rss_count;
10710 * An estimated maximum supported CoS number according to the chip
10712 * We will try to roughly estimate the maximum number of CoSes this chip
10713 * may support in order to minimize the memory allocated for Tx
10714 * netdev_queue's. This number will be accurately calculated during the
10715 * initialization of bp->max_cos based on the chip versions AND chip
10716 * revision in the bnx2x_init_bp().
10718 u8 max_cos_est = 0;
10720 switch (ent->driver_data) {
10724 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
10729 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
10738 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
10742 pr_err("Unknown board_type (%ld), aborting\n",
10747 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
10750 * Do not allow the maximum SB count to grow above 16
10751 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
10752 * We will use the FP_SB_MAX_E1x macro for this matter.
10754 max_non_def_sbs = min_t(int, FP_SB_MAX_E1x, max_non_def_sbs);
10756 WARN_ON(!max_non_def_sbs);
10758 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
10759 rss_count = max_non_def_sbs - CNIC_PRESENT;
10761 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
10762 rx_count = rss_count + FCOE_PRESENT;
10765 * Maximum number of netdev Tx queues:
10766 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
10768 tx_count = MAX_TXQS_PER_COS * max_cos_est + FCOE_PRESENT;
10770 /* dev zeroed in init_etherdev */
10771 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
10773 dev_err(&pdev->dev, "Cannot allocate net device\n");
10777 bp = netdev_priv(dev);
10779 DP(NETIF_MSG_DRV, "Allocated netdev with %d tx and %d rx queues\n",
10780 tx_count, rx_count);
10782 bp->igu_sb_cnt = max_non_def_sbs;
10783 bp->msg_enable = debug;
10784 pci_set_drvdata(pdev, dev);
10786 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
10792 DP(NETIF_MSG_DRV, "max_non_def_sbs %d", max_non_def_sbs);
10794 rc = bnx2x_init_bp(bp);
10796 goto init_one_exit;
10799 * Map doorbels here as we need the real value of bp->max_cos which
10800 * is initialized in bnx2x_init_bp().
10802 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
10803 min_t(u64, BNX2X_DB_SIZE(bp),
10804 pci_resource_len(pdev, 2)));
10805 if (!bp->doorbells) {
10806 dev_err(&bp->pdev->dev,
10807 "Cannot map doorbell space, aborting\n");
10809 goto init_one_exit;
10812 /* calc qm_cid_count */
10813 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
10816 /* disable FCOE L2 queue for E1x and E3*/
10817 if (CHIP_IS_E1x(bp) || CHIP_IS_E3(bp))
10818 bp->flags |= NO_FCOE_FLAG;
10822 /* Configure interrupt mode: try to enable MSI-X/MSI if
10823 * needed, set bp->num_queues appropriately.
10825 bnx2x_set_int_mode(bp);
10827 /* Add all NAPI objects */
10828 bnx2x_add_all_napi(bp);
10830 rc = register_netdev(dev);
10832 dev_err(&pdev->dev, "Cannot register net device\n");
10833 goto init_one_exit;
10837 if (!NO_FCOE(bp)) {
10838 /* Add storage MAC address */
10840 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10845 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
10847 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
10848 " IRQ %d, ", board_info[ent->driver_data].name,
10849 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
10851 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
10852 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
10853 "5GHz (Gen2)" : "2.5GHz",
10854 dev->base_addr, bp->pdev->irq);
10855 pr_cont("node addr %pM\n", dev->dev_addr);
10861 iounmap(bp->regview);
10864 iounmap(bp->doorbells);
10868 if (atomic_read(&pdev->enable_cnt) == 1)
10869 pci_release_regions(pdev);
10871 pci_disable_device(pdev);
10872 pci_set_drvdata(pdev, NULL);
10877 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
10879 struct net_device *dev = pci_get_drvdata(pdev);
10883 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
10886 bp = netdev_priv(dev);
10889 /* Delete storage MAC address */
10890 if (!NO_FCOE(bp)) {
10892 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
10898 /* Delete app tlvs from dcbnl */
10899 bnx2x_dcbnl_update_applist(bp, true);
10902 unregister_netdev(dev);
10904 /* Delete all NAPI objects */
10905 bnx2x_del_all_napi(bp);
10907 /* Power on: we can't let PCI layer write to us while we are in D3 */
10908 bnx2x_set_power_state(bp, PCI_D0);
10910 /* Disable MSI/MSI-X */
10911 bnx2x_disable_msi(bp);
10914 bnx2x_set_power_state(bp, PCI_D3hot);
10916 /* Make sure RESET task is not scheduled before continuing */
10917 cancel_delayed_work_sync(&bp->sp_rtnl_task);
10920 iounmap(bp->regview);
10923 iounmap(bp->doorbells);
10925 bnx2x_free_mem_bp(bp);
10929 if (atomic_read(&pdev->enable_cnt) == 1)
10930 pci_release_regions(pdev);
10932 pci_disable_device(pdev);
10933 pci_set_drvdata(pdev, NULL);
10936 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
10940 bp->state = BNX2X_STATE_ERROR;
10942 bp->rx_mode = BNX2X_RX_MODE_NONE;
10945 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
10948 bnx2x_tx_disable(bp);
10950 bnx2x_netif_stop(bp, 0);
10952 del_timer_sync(&bp->timer);
10954 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
10957 bnx2x_free_irq(bp);
10959 /* Free SKBs, SGEs, TPA pool and driver internals */
10960 bnx2x_free_skbs(bp);
10962 for_each_rx_queue(bp, i)
10963 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
10965 bnx2x_free_mem(bp);
10967 bp->state = BNX2X_STATE_CLOSED;
10969 netif_carrier_off(bp->dev);
10974 static void bnx2x_eeh_recover(struct bnx2x *bp)
10978 mutex_init(&bp->port.phy_mutex);
10980 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
10981 bp->link_params.shmem_base = bp->common.shmem_base;
10982 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
10984 if (!bp->common.shmem_base ||
10985 (bp->common.shmem_base < 0xA0000) ||
10986 (bp->common.shmem_base >= 0xC0000)) {
10987 BNX2X_DEV_INFO("MCP not active\n");
10988 bp->flags |= NO_MCP_FLAG;
10992 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
10993 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10994 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
10995 BNX2X_ERR("BAD MCP validity signature\n");
10997 if (!BP_NOMCP(bp)) {
10999 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11000 DRV_MSG_SEQ_NUMBER_MASK);
11001 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11006 * bnx2x_io_error_detected - called when PCI error is detected
11007 * @pdev: Pointer to PCI device
11008 * @state: The current pci connection state
11010 * This function is called after a PCI bus error affecting
11011 * this device has been detected.
11013 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
11014 pci_channel_state_t state)
11016 struct net_device *dev = pci_get_drvdata(pdev);
11017 struct bnx2x *bp = netdev_priv(dev);
11021 netif_device_detach(dev);
11023 if (state == pci_channel_io_perm_failure) {
11025 return PCI_ERS_RESULT_DISCONNECT;
11028 if (netif_running(dev))
11029 bnx2x_eeh_nic_unload(bp);
11031 pci_disable_device(pdev);
11035 /* Request a slot reset */
11036 return PCI_ERS_RESULT_NEED_RESET;
11040 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11041 * @pdev: Pointer to PCI device
11043 * Restart the card from scratch, as if from a cold-boot.
11045 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
11047 struct net_device *dev = pci_get_drvdata(pdev);
11048 struct bnx2x *bp = netdev_priv(dev);
11052 if (pci_enable_device(pdev)) {
11053 dev_err(&pdev->dev,
11054 "Cannot re-enable PCI device after reset\n");
11056 return PCI_ERS_RESULT_DISCONNECT;
11059 pci_set_master(pdev);
11060 pci_restore_state(pdev);
11062 if (netif_running(dev))
11063 bnx2x_set_power_state(bp, PCI_D0);
11067 return PCI_ERS_RESULT_RECOVERED;
11071 * bnx2x_io_resume - called when traffic can start flowing again
11072 * @pdev: Pointer to PCI device
11074 * This callback is called when the error recovery driver tells us that
11075 * its OK to resume normal operation.
11077 static void bnx2x_io_resume(struct pci_dev *pdev)
11079 struct net_device *dev = pci_get_drvdata(pdev);
11080 struct bnx2x *bp = netdev_priv(dev);
11082 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
11083 netdev_err(bp->dev, "Handling parity error recovery. "
11084 "Try again later\n");
11090 bnx2x_eeh_recover(bp);
11092 if (netif_running(dev))
11093 bnx2x_nic_load(bp, LOAD_NORMAL);
11095 netif_device_attach(dev);
11100 static struct pci_error_handlers bnx2x_err_handler = {
11101 .error_detected = bnx2x_io_error_detected,
11102 .slot_reset = bnx2x_io_slot_reset,
11103 .resume = bnx2x_io_resume,
11106 static struct pci_driver bnx2x_pci_driver = {
11107 .name = DRV_MODULE_NAME,
11108 .id_table = bnx2x_pci_tbl,
11109 .probe = bnx2x_init_one,
11110 .remove = __devexit_p(bnx2x_remove_one),
11111 .suspend = bnx2x_suspend,
11112 .resume = bnx2x_resume,
11113 .err_handler = &bnx2x_err_handler,
11116 static int __init bnx2x_init(void)
11120 pr_info("%s", version);
11122 bnx2x_wq = create_singlethread_workqueue("bnx2x");
11123 if (bnx2x_wq == NULL) {
11124 pr_err("Cannot create workqueue\n");
11128 ret = pci_register_driver(&bnx2x_pci_driver);
11130 pr_err("Cannot register driver\n");
11131 destroy_workqueue(bnx2x_wq);
11136 static void __exit bnx2x_cleanup(void)
11138 pci_unregister_driver(&bnx2x_pci_driver);
11140 destroy_workqueue(bnx2x_wq);
11143 void bnx2x_notify_link_changed(struct bnx2x *bp)
11145 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
11148 module_init(bnx2x_init);
11149 module_exit(bnx2x_cleanup);
11153 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11155 * @bp: driver handle
11156 * @set: set or clear the CAM entry
11158 * This function will wait until the ramdord completion returns.
11159 * Return 0 if success, -ENODEV if ramrod doesn't return.
11161 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
11163 unsigned long ramrod_flags = 0;
11165 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
11166 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
11167 &bp->iscsi_l2_mac_obj, true,
11168 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
11171 /* count denotes the number of new completions we have seen */
11172 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
11174 struct eth_spe *spe;
11176 #ifdef BNX2X_STOP_ON_ERROR
11177 if (unlikely(bp->panic))
11181 spin_lock_bh(&bp->spq_lock);
11182 BUG_ON(bp->cnic_spq_pending < count);
11183 bp->cnic_spq_pending -= count;
11186 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
11187 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
11188 & SPE_HDR_CONN_TYPE) >>
11189 SPE_HDR_CONN_TYPE_SHIFT;
11190 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
11191 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
11193 /* Set validation for iSCSI L2 client before sending SETUP
11196 if (type == ETH_CONNECTION_TYPE) {
11197 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
11198 bnx2x_set_ctx_validation(bp, &bp->context.
11199 vcxt[BNX2X_ISCSI_ETH_CID].eth,
11200 BNX2X_ISCSI_ETH_CID);
11204 * There may be not more than 8 L2, not more than 8 L5 SPEs
11205 * and in the air. We also check that number of outstanding
11206 * COMMON ramrods is not more than the EQ and SPQ can
11209 if (type == ETH_CONNECTION_TYPE) {
11210 if (!atomic_read(&bp->cq_spq_left))
11213 atomic_dec(&bp->cq_spq_left);
11214 } else if (type == NONE_CONNECTION_TYPE) {
11215 if (!atomic_read(&bp->eq_spq_left))
11218 atomic_dec(&bp->eq_spq_left);
11219 } else if ((type == ISCSI_CONNECTION_TYPE) ||
11220 (type == FCOE_CONNECTION_TYPE)) {
11221 if (bp->cnic_spq_pending >=
11222 bp->cnic_eth_dev.max_kwqe_pending)
11225 bp->cnic_spq_pending++;
11227 BNX2X_ERR("Unknown SPE type: %d\n", type);
11232 spe = bnx2x_sp_get_next(bp);
11233 *spe = *bp->cnic_kwq_cons;
11235 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
11236 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
11238 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
11239 bp->cnic_kwq_cons = bp->cnic_kwq;
11241 bp->cnic_kwq_cons++;
11243 bnx2x_sp_prod_update(bp);
11244 spin_unlock_bh(&bp->spq_lock);
11247 static int bnx2x_cnic_sp_queue(struct net_device *dev,
11248 struct kwqe_16 *kwqes[], u32 count)
11250 struct bnx2x *bp = netdev_priv(dev);
11253 #ifdef BNX2X_STOP_ON_ERROR
11254 if (unlikely(bp->panic))
11258 spin_lock_bh(&bp->spq_lock);
11260 for (i = 0; i < count; i++) {
11261 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
11263 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
11266 *bp->cnic_kwq_prod = *spe;
11268 bp->cnic_kwq_pending++;
11270 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
11271 spe->hdr.conn_and_cmd_data, spe->hdr.type,
11272 spe->data.update_data_addr.hi,
11273 spe->data.update_data_addr.lo,
11274 bp->cnic_kwq_pending);
11276 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
11277 bp->cnic_kwq_prod = bp->cnic_kwq;
11279 bp->cnic_kwq_prod++;
11282 spin_unlock_bh(&bp->spq_lock);
11284 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
11285 bnx2x_cnic_sp_post(bp, 0);
11290 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11292 struct cnic_ops *c_ops;
11295 mutex_lock(&bp->cnic_mutex);
11296 c_ops = rcu_dereference_protected(bp->cnic_ops,
11297 lockdep_is_held(&bp->cnic_mutex));
11299 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11300 mutex_unlock(&bp->cnic_mutex);
11305 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
11307 struct cnic_ops *c_ops;
11311 c_ops = rcu_dereference(bp->cnic_ops);
11313 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
11320 * for commands that have no data
11322 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
11324 struct cnic_ctl_info ctl = {0};
11328 return bnx2x_cnic_ctl_send(bp, &ctl);
11331 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
11333 struct cnic_ctl_info ctl = {0};
11335 /* first we tell CNIC and only then we count this as a completion */
11336 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
11337 ctl.data.comp.cid = cid;
11338 ctl.data.comp.error = err;
11340 bnx2x_cnic_ctl_send_bh(bp, &ctl);
11341 bnx2x_cnic_sp_post(bp, 0);
11345 /* Called with netif_addr_lock_bh() taken.
11346 * Sets an rx_mode config for an iSCSI ETH client.
11348 * Completion should be checked outside.
11350 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
11352 unsigned long accept_flags = 0, ramrod_flags = 0;
11353 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11354 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
11357 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11358 * because it's the only way for UIO Queue to accept
11359 * multicasts (in non-promiscuous mode only one Queue per
11360 * function will receive multicast packets (leading in our
11363 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
11364 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
11365 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
11366 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
11368 /* Clear STOP_PENDING bit if START is requested */
11369 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
11371 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
11373 /* Clear START_PENDING bit if STOP is requested */
11374 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
11376 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
11377 set_bit(sched_state, &bp->sp_state);
11379 __set_bit(RAMROD_RX, &ramrod_flags);
11380 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
11386 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
11388 struct bnx2x *bp = netdev_priv(dev);
11391 switch (ctl->cmd) {
11392 case DRV_CTL_CTXTBL_WR_CMD: {
11393 u32 index = ctl->data.io.offset;
11394 dma_addr_t addr = ctl->data.io.dma_addr;
11396 bnx2x_ilt_wr(bp, index, addr);
11400 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
11401 int count = ctl->data.credit.credit_count;
11403 bnx2x_cnic_sp_post(bp, count);
11407 /* rtnl_lock is held. */
11408 case DRV_CTL_START_L2_CMD: {
11409 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11410 unsigned long sp_bits = 0;
11412 /* Configure the iSCSI classification object */
11413 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
11414 cp->iscsi_l2_client_id,
11415 cp->iscsi_l2_cid, BP_FUNC(bp),
11416 bnx2x_sp(bp, mac_rdata),
11417 bnx2x_sp_mapping(bp, mac_rdata),
11418 BNX2X_FILTER_MAC_PENDING,
11419 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
11422 /* Set iSCSI MAC address */
11423 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
11430 /* Start accepting on iSCSI L2 ring */
11432 netif_addr_lock_bh(dev);
11433 bnx2x_set_iscsi_eth_rx_mode(bp, true);
11434 netif_addr_unlock_bh(dev);
11436 /* bits to wait on */
11437 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11438 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
11440 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11441 BNX2X_ERR("rx_mode completion timed out!\n");
11446 /* rtnl_lock is held. */
11447 case DRV_CTL_STOP_L2_CMD: {
11448 unsigned long sp_bits = 0;
11450 /* Stop accepting on iSCSI L2 ring */
11451 netif_addr_lock_bh(dev);
11452 bnx2x_set_iscsi_eth_rx_mode(bp, false);
11453 netif_addr_unlock_bh(dev);
11455 /* bits to wait on */
11456 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
11457 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
11459 if (!bnx2x_wait_sp_comp(bp, sp_bits))
11460 BNX2X_ERR("rx_mode completion timed out!\n");
11465 /* Unset iSCSI L2 MAC */
11466 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
11467 BNX2X_ISCSI_ETH_MAC, true);
11470 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
11471 int count = ctl->data.credit.credit_count;
11473 smp_mb__before_atomic_inc();
11474 atomic_add(count, &bp->cq_spq_left);
11475 smp_mb__after_atomic_inc();
11480 BNX2X_ERR("unknown command %x\n", ctl->cmd);
11487 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
11489 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11491 if (bp->flags & USING_MSIX_FLAG) {
11492 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
11493 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
11494 cp->irq_arr[0].vector = bp->msix_table[1].vector;
11496 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
11497 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
11499 if (!CHIP_IS_E1x(bp))
11500 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
11502 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
11504 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
11505 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
11506 cp->irq_arr[1].status_blk = bp->def_status_blk;
11507 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
11508 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
11513 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
11516 struct bnx2x *bp = netdev_priv(dev);
11517 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11522 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
11526 bp->cnic_kwq_cons = bp->cnic_kwq;
11527 bp->cnic_kwq_prod = bp->cnic_kwq;
11528 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
11530 bp->cnic_spq_pending = 0;
11531 bp->cnic_kwq_pending = 0;
11533 bp->cnic_data = data;
11536 cp->drv_state |= CNIC_DRV_STATE_REGD;
11537 cp->iro_arr = bp->iro_arr;
11539 bnx2x_setup_cnic_irq_info(bp);
11541 rcu_assign_pointer(bp->cnic_ops, ops);
11546 static int bnx2x_unregister_cnic(struct net_device *dev)
11548 struct bnx2x *bp = netdev_priv(dev);
11549 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11551 mutex_lock(&bp->cnic_mutex);
11553 rcu_assign_pointer(bp->cnic_ops, NULL);
11554 mutex_unlock(&bp->cnic_mutex);
11556 kfree(bp->cnic_kwq);
11557 bp->cnic_kwq = NULL;
11562 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
11564 struct bnx2x *bp = netdev_priv(dev);
11565 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
11567 /* If both iSCSI and FCoE are disabled - return NULL in
11568 * order to indicate CNIC that it should not try to work
11569 * with this device.
11571 if (NO_ISCSI(bp) && NO_FCOE(bp))
11574 cp->drv_owner = THIS_MODULE;
11575 cp->chip_id = CHIP_ID(bp);
11576 cp->pdev = bp->pdev;
11577 cp->io_base = bp->regview;
11578 cp->io_base2 = bp->doorbells;
11579 cp->max_kwqe_pending = 8;
11580 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
11581 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
11582 bnx2x_cid_ilt_lines(bp);
11583 cp->ctx_tbl_len = CNIC_ILT_LINES;
11584 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
11585 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
11586 cp->drv_ctl = bnx2x_drv_ctl;
11587 cp->drv_register_cnic = bnx2x_register_cnic;
11588 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
11589 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
11590 cp->iscsi_l2_client_id =
11591 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
11592 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
11594 if (NO_ISCSI_OOO(bp))
11595 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
11598 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
11601 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
11603 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
11604 "starting cid %d\n",
11606 cp->ctx_tbl_offset,
11611 EXPORT_SYMBOL(bnx2x_cnic_probe);
11613 #endif /* BCM_CNIC */