1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2011 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/kernel.h>
21 #include <linux/device.h> /* for dev_info() */
22 #include <linux/timer.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/init.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/skbuff.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitops.h>
34 #include <linux/irq.h>
35 #include <linux/delay.h>
36 #include <asm/byteorder.h>
37 #include <linux/time.h>
38 #include <linux/ethtool.h>
39 #include <linux/mii.h>
40 #include <linux/if_vlan.h>
43 #include <net/checksum.h>
44 #include <net/ip6_checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/crc32c.h>
48 #include <linux/prefetch.h>
49 #include <linux/zlib.h>
51 #include <linux/stringify.h>
55 #include "bnx2x_init.h"
56 #include "bnx2x_init_ops.h"
57 #include "bnx2x_cmn.h"
58 #include "bnx2x_dcb.h"
60 #include <linux/firmware.h>
61 #include "bnx2x_fw_file_hdr.h"
63 #define FW_FILE_VERSION \
64 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
65 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
66 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
67 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
68 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
69 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
70 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
72 /* Time in jiffies before concluding the transmitter is hung */
73 #define TX_TIMEOUT (5*HZ)
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II 5771x 10Gigabit Ethernet Driver "
77 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
79 MODULE_AUTHOR("Eliezer Tamir");
80 MODULE_DESCRIPTION("Broadcom NetXtreme II "
81 "BCM57710/57711/57711E/57712/57712E Driver");
82 MODULE_LICENSE("GPL");
83 MODULE_VERSION(DRV_MODULE_VERSION);
84 MODULE_FIRMWARE(FW_FILE_NAME_E1);
85 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
86 MODULE_FIRMWARE(FW_FILE_NAME_E2);
88 static int multi_mode = 1;
89 module_param(multi_mode, int, 0);
90 MODULE_PARM_DESC(multi_mode, " Multi queue mode "
91 "(0 Disable; 1 Enable (default))");
94 module_param(num_queues, int, 0);
95 MODULE_PARM_DESC(num_queues, " Number of queues for multi_mode=1"
96 " (default is as a number of CPUs)");
98 static int disable_tpa;
99 module_param(disable_tpa, int, 0);
100 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
103 module_param(int_mode, int, 0);
104 MODULE_PARM_DESC(int_mode, " Force interrupt mode other then MSI-X "
107 static int dropless_fc;
108 module_param(dropless_fc, int, 0);
109 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
112 module_param(poll, int, 0);
113 MODULE_PARM_DESC(poll, " Use polling (for debug)");
115 static int mrrs = -1;
116 module_param(mrrs, int, 0);
117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
120 module_param(debug, int, 0);
121 MODULE_PARM_DESC(debug, " Default debug msglevel");
123 static struct workqueue_struct *bnx2x_wq;
126 static u8 ALL_ENODE_MACS[] = {0x01, 0x10, 0x18, 0x01, 0x00, 0x01};
129 enum bnx2x_board_type {
137 /* indexed by board_type, above */
140 } board_info[] __devinitdata = {
141 { "Broadcom NetXtreme II BCM57710 XGb" },
142 { "Broadcom NetXtreme II BCM57711 XGb" },
143 { "Broadcom NetXtreme II BCM57711E XGb" },
144 { "Broadcom NetXtreme II BCM57712 XGb" },
145 { "Broadcom NetXtreme II BCM57712E XGb" }
148 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
149 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
150 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
151 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
152 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
153 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712E), BCM57712E },
157 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
159 /****************************************************************************
160 * General service functions
161 ****************************************************************************/
163 static inline void __storm_memset_dma_mapping(struct bnx2x *bp,
164 u32 addr, dma_addr_t mapping)
166 REG_WR(bp, addr, U64_LO(mapping));
167 REG_WR(bp, addr + 4, U64_HI(mapping));
170 static inline void __storm_memset_fill(struct bnx2x *bp,
171 u32 addr, size_t size, u32 val)
174 for (i = 0; i < size/4; i++)
175 REG_WR(bp, addr + (i * 4), val);
178 static inline void storm_memset_ustats_zero(struct bnx2x *bp,
179 u8 port, u16 stat_id)
181 size_t size = sizeof(struct ustorm_per_client_stats);
183 u32 addr = BAR_USTRORM_INTMEM +
184 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
186 __storm_memset_fill(bp, addr, size, 0);
189 static inline void storm_memset_tstats_zero(struct bnx2x *bp,
190 u8 port, u16 stat_id)
192 size_t size = sizeof(struct tstorm_per_client_stats);
194 u32 addr = BAR_TSTRORM_INTMEM +
195 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
197 __storm_memset_fill(bp, addr, size, 0);
200 static inline void storm_memset_xstats_zero(struct bnx2x *bp,
201 u8 port, u16 stat_id)
203 size_t size = sizeof(struct xstorm_per_client_stats);
205 u32 addr = BAR_XSTRORM_INTMEM +
206 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, stat_id);
208 __storm_memset_fill(bp, addr, size, 0);
212 static inline void storm_memset_spq_addr(struct bnx2x *bp,
213 dma_addr_t mapping, u16 abs_fid)
215 u32 addr = XSEM_REG_FAST_MEMORY +
216 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
218 __storm_memset_dma_mapping(bp, addr, mapping);
221 static inline void storm_memset_ov(struct bnx2x *bp, u16 ov, u16 abs_fid)
223 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_E1HOV_OFFSET(abs_fid), ov);
226 static inline void storm_memset_func_cfg(struct bnx2x *bp,
227 struct tstorm_eth_function_common_config *tcfg,
230 size_t size = sizeof(struct tstorm_eth_function_common_config);
232 u32 addr = BAR_TSTRORM_INTMEM +
233 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
235 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
238 static inline void storm_memset_xstats_flags(struct bnx2x *bp,
239 struct stats_indication_flags *flags,
242 size_t size = sizeof(struct stats_indication_flags);
244 u32 addr = BAR_XSTRORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(abs_fid);
246 __storm_memset_struct(bp, addr, size, (u32 *)flags);
249 static inline void storm_memset_tstats_flags(struct bnx2x *bp,
250 struct stats_indication_flags *flags,
253 size_t size = sizeof(struct stats_indication_flags);
255 u32 addr = BAR_TSTRORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(abs_fid);
257 __storm_memset_struct(bp, addr, size, (u32 *)flags);
260 static inline void storm_memset_ustats_flags(struct bnx2x *bp,
261 struct stats_indication_flags *flags,
264 size_t size = sizeof(struct stats_indication_flags);
266 u32 addr = BAR_USTRORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(abs_fid);
268 __storm_memset_struct(bp, addr, size, (u32 *)flags);
271 static inline void storm_memset_cstats_flags(struct bnx2x *bp,
272 struct stats_indication_flags *flags,
275 size_t size = sizeof(struct stats_indication_flags);
277 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(abs_fid);
279 __storm_memset_struct(bp, addr, size, (u32 *)flags);
282 static inline void storm_memset_xstats_addr(struct bnx2x *bp,
283 dma_addr_t mapping, u16 abs_fid)
285 u32 addr = BAR_XSTRORM_INTMEM +
286 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
288 __storm_memset_dma_mapping(bp, addr, mapping);
291 static inline void storm_memset_tstats_addr(struct bnx2x *bp,
292 dma_addr_t mapping, u16 abs_fid)
294 u32 addr = BAR_TSTRORM_INTMEM +
295 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
297 __storm_memset_dma_mapping(bp, addr, mapping);
300 static inline void storm_memset_ustats_addr(struct bnx2x *bp,
301 dma_addr_t mapping, u16 abs_fid)
303 u32 addr = BAR_USTRORM_INTMEM +
304 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
306 __storm_memset_dma_mapping(bp, addr, mapping);
309 static inline void storm_memset_cstats_addr(struct bnx2x *bp,
310 dma_addr_t mapping, u16 abs_fid)
312 u32 addr = BAR_CSTRORM_INTMEM +
313 CSTORM_ETH_STATS_QUERY_ADDR_OFFSET(abs_fid);
315 __storm_memset_dma_mapping(bp, addr, mapping);
318 static inline void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
321 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
323 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
325 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
327 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
331 static inline void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
334 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
336 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
338 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
340 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
344 static inline void storm_memset_eq_data(struct bnx2x *bp,
345 struct event_ring_data *eq_data,
348 size_t size = sizeof(struct event_ring_data);
350 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
352 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
355 static inline void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
358 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
359 REG_WR16(bp, addr, eq_prod);
362 static inline void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
363 u16 fw_sb_id, u8 sb_index,
367 int index_offset = CHIP_IS_E2(bp) ?
368 offsetof(struct hc_status_block_data_e2, index_data) :
369 offsetof(struct hc_status_block_data_e1x, index_data);
370 u32 addr = BAR_CSTRORM_INTMEM +
371 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
373 sizeof(struct hc_index_data)*sb_index +
374 offsetof(struct hc_index_data, timeout);
375 REG_WR8(bp, addr, ticks);
376 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d ticks %d\n",
377 port, fw_sb_id, sb_index, ticks);
379 static inline void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
380 u16 fw_sb_id, u8 sb_index,
383 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
384 int index_offset = CHIP_IS_E2(bp) ?
385 offsetof(struct hc_status_block_data_e2, index_data) :
386 offsetof(struct hc_status_block_data_e1x, index_data);
387 u32 addr = BAR_CSTRORM_INTMEM +
388 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
390 sizeof(struct hc_index_data)*sb_index +
391 offsetof(struct hc_index_data, flags);
392 u16 flags = REG_RD16(bp, addr);
394 flags &= ~HC_INDEX_DATA_HC_ENABLED;
395 flags |= enable_flag;
396 REG_WR16(bp, addr, flags);
397 DP(NETIF_MSG_HW, "port %x fw_sb_id %d sb_index %d disable %d\n",
398 port, fw_sb_id, sb_index, disable);
402 * locking is done by mcp
404 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
406 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
407 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
408 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
409 PCICFG_VENDOR_ID_OFFSET);
412 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
416 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
417 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
418 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
419 PCICFG_VENDOR_ID_OFFSET);
424 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
425 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
426 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
427 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
428 #define DMAE_DP_DST_NONE "dst_addr [none]"
430 static void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae,
433 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
435 switch (dmae->opcode & DMAE_COMMAND_DST) {
436 case DMAE_CMD_DST_PCI:
437 if (src_type == DMAE_CMD_SRC_PCI)
438 DP(msglvl, "DMAE: opcode 0x%08x\n"
439 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
440 "comp_addr [%x:%08x], comp_val 0x%08x\n",
441 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
442 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
443 dmae->comp_addr_hi, dmae->comp_addr_lo,
446 DP(msglvl, "DMAE: opcode 0x%08x\n"
447 "src [%08x], len [%d*4], dst [%x:%08x]\n"
448 "comp_addr [%x:%08x], comp_val 0x%08x\n",
449 dmae->opcode, dmae->src_addr_lo >> 2,
450 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
451 dmae->comp_addr_hi, dmae->comp_addr_lo,
454 case DMAE_CMD_DST_GRC:
455 if (src_type == DMAE_CMD_SRC_PCI)
456 DP(msglvl, "DMAE: opcode 0x%08x\n"
457 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
458 "comp_addr [%x:%08x], comp_val 0x%08x\n",
459 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
460 dmae->len, dmae->dst_addr_lo >> 2,
461 dmae->comp_addr_hi, dmae->comp_addr_lo,
464 DP(msglvl, "DMAE: opcode 0x%08x\n"
465 "src [%08x], len [%d*4], dst [%08x]\n"
466 "comp_addr [%x:%08x], comp_val 0x%08x\n",
467 dmae->opcode, dmae->src_addr_lo >> 2,
468 dmae->len, dmae->dst_addr_lo >> 2,
469 dmae->comp_addr_hi, dmae->comp_addr_lo,
473 if (src_type == DMAE_CMD_SRC_PCI)
474 DP(msglvl, "DMAE: opcode 0x%08x\n"
475 DP_LEVEL "src_addr [%x:%08x] len [%d * 4] "
477 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
478 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
479 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
482 DP(msglvl, "DMAE: opcode 0x%08x\n"
483 DP_LEVEL "src_addr [%08x] len [%d * 4] "
485 DP_LEVEL "comp_addr [%x:%08x] comp_val 0x%08x\n",
486 dmae->opcode, dmae->src_addr_lo >> 2,
487 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
494 const u32 dmae_reg_go_c[] = {
495 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
496 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
497 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
498 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
501 /* copy command into DMAE command memory and set DMAE command go */
502 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
507 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
508 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
509 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
511 DP(BNX2X_MSG_OFF, "DMAE cmd[%d].%d (0x%08x) : 0x%08x\n",
512 idx, i, cmd_offset + i*4, *(((u32 *)dmae) + i));
514 REG_WR(bp, dmae_reg_go_c[idx], 1);
517 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
519 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
523 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
525 return opcode & ~DMAE_CMD_SRC_RESET;
528 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
529 bool with_comp, u8 comp_type)
533 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
534 (dst_type << DMAE_COMMAND_DST_SHIFT));
536 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
538 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
539 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) |
540 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
541 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
544 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
546 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
549 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
553 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
554 struct dmae_command *dmae,
555 u8 src_type, u8 dst_type)
557 memset(dmae, 0, sizeof(struct dmae_command));
560 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
561 true, DMAE_COMP_PCI);
563 /* fill in the completion parameters */
564 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
565 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
566 dmae->comp_val = DMAE_COMP_VAL;
569 /* issue a dmae command over the init-channel and wailt for completion */
570 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
571 struct dmae_command *dmae)
573 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
574 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
577 DP(BNX2X_MSG_OFF, "data before [0x%08x 0x%08x 0x%08x 0x%08x]\n",
578 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
579 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
581 /* lock the dmae channel */
582 spin_lock_bh(&bp->dmae_lock);
584 /* reset completion */
587 /* post the command on the channel used for initializations */
588 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
590 /* wait for completion */
592 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
593 DP(BNX2X_MSG_OFF, "wb_comp 0x%08x\n", *wb_comp);
596 BNX2X_ERR("DMAE timeout!\n");
603 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
604 BNX2X_ERR("DMAE PCI error!\n");
608 DP(BNX2X_MSG_OFF, "data after [0x%08x 0x%08x 0x%08x 0x%08x]\n",
609 bp->slowpath->wb_data[0], bp->slowpath->wb_data[1],
610 bp->slowpath->wb_data[2], bp->slowpath->wb_data[3]);
613 spin_unlock_bh(&bp->dmae_lock);
617 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
620 struct dmae_command dmae;
622 if (!bp->dmae_ready) {
623 u32 *data = bnx2x_sp(bp, wb_data[0]);
625 DP(BNX2X_MSG_OFF, "DMAE is not ready (dst_addr %08x len32 %d)"
626 " using indirect\n", dst_addr, len32);
627 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
631 /* set opcode and fixed command fields */
632 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
634 /* fill in addresses and len */
635 dmae.src_addr_lo = U64_LO(dma_addr);
636 dmae.src_addr_hi = U64_HI(dma_addr);
637 dmae.dst_addr_lo = dst_addr >> 2;
638 dmae.dst_addr_hi = 0;
641 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
643 /* issue the command and wait for completion */
644 bnx2x_issue_dmae_with_comp(bp, &dmae);
647 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
649 struct dmae_command dmae;
651 if (!bp->dmae_ready) {
652 u32 *data = bnx2x_sp(bp, wb_data[0]);
655 DP(BNX2X_MSG_OFF, "DMAE is not ready (src_addr %08x len32 %d)"
656 " using indirect\n", src_addr, len32);
657 for (i = 0; i < len32; i++)
658 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
662 /* set opcode and fixed command fields */
663 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
665 /* fill in addresses and len */
666 dmae.src_addr_lo = src_addr >> 2;
667 dmae.src_addr_hi = 0;
668 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
669 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
672 bnx2x_dp_dmae(bp, &dmae, BNX2X_MSG_OFF);
674 /* issue the command and wait for completion */
675 bnx2x_issue_dmae_with_comp(bp, &dmae);
678 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
681 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
684 while (len > dmae_wr_max) {
685 bnx2x_write_dmae(bp, phys_addr + offset,
686 addr + offset, dmae_wr_max);
687 offset += dmae_wr_max * 4;
691 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
694 /* used only for slowpath so not inlined */
695 static void bnx2x_wb_wr(struct bnx2x *bp, int reg, u32 val_hi, u32 val_lo)
699 wb_write[0] = val_hi;
700 wb_write[1] = val_lo;
701 REG_WR_DMAE(bp, reg, wb_write, 2);
705 static u64 bnx2x_wb_rd(struct bnx2x *bp, int reg)
709 REG_RD_DMAE(bp, reg, wb_data, 2);
711 return HILO_U64(wb_data[0], wb_data[1]);
715 static int bnx2x_mc_assert(struct bnx2x *bp)
719 u32 row0, row1, row2, row3;
722 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
723 XSTORM_ASSERT_LIST_INDEX_OFFSET);
725 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
727 /* print the asserts */
728 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
730 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
731 XSTORM_ASSERT_LIST_OFFSET(i));
732 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
733 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
734 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
735 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
736 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
737 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
739 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
740 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x"
741 " 0x%08x 0x%08x 0x%08x\n",
742 i, row3, row2, row1, row0);
750 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
751 TSTORM_ASSERT_LIST_INDEX_OFFSET);
753 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
755 /* print the asserts */
756 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
758 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
759 TSTORM_ASSERT_LIST_OFFSET(i));
760 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
761 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
762 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
763 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
764 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
765 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
767 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
768 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x"
769 " 0x%08x 0x%08x 0x%08x\n",
770 i, row3, row2, row1, row0);
778 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
779 CSTORM_ASSERT_LIST_INDEX_OFFSET);
781 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
783 /* print the asserts */
784 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
786 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
787 CSTORM_ASSERT_LIST_OFFSET(i));
788 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
789 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
790 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
791 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
792 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
793 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
795 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
796 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x"
797 " 0x%08x 0x%08x 0x%08x\n",
798 i, row3, row2, row1, row0);
806 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
807 USTORM_ASSERT_LIST_INDEX_OFFSET);
809 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
811 /* print the asserts */
812 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
814 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
815 USTORM_ASSERT_LIST_OFFSET(i));
816 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
817 USTORM_ASSERT_LIST_OFFSET(i) + 4);
818 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
819 USTORM_ASSERT_LIST_OFFSET(i) + 8);
820 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
821 USTORM_ASSERT_LIST_OFFSET(i) + 12);
823 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
824 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x"
825 " 0x%08x 0x%08x 0x%08x\n",
826 i, row3, row2, row1, row0);
836 static void bnx2x_fw_dump(struct bnx2x *bp)
842 u32 trace_shmem_base;
844 BNX2X_ERR("NO MCP - can not dump\n");
848 if (BP_PATH(bp) == 0)
849 trace_shmem_base = bp->common.shmem_base;
851 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
852 addr = trace_shmem_base - 0x0800 + 4;
853 mark = REG_RD(bp, addr);
854 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
855 + ((mark + 0x3) & ~0x3) - 0x08000000;
856 pr_err("begin fw dump (mark 0x%x)\n", mark);
859 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
860 for (word = 0; word < 8; word++)
861 data[word] = htonl(REG_RD(bp, offset + 4*word));
863 pr_cont("%s", (char *)data);
865 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
866 for (word = 0; word < 8; word++)
867 data[word] = htonl(REG_RD(bp, offset + 4*word));
869 pr_cont("%s", (char *)data);
871 pr_err("end of fw dump\n");
874 void bnx2x_panic_dump(struct bnx2x *bp)
878 struct hc_sp_status_block_data sp_sb_data;
879 int func = BP_FUNC(bp);
880 #ifdef BNX2X_STOP_ON_ERROR
881 u16 start = 0, end = 0;
884 bp->stats_state = STATS_STATE_DISABLED;
885 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
887 BNX2X_ERR("begin crash dump -----------------\n");
891 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x)"
892 " spq_prod_idx(0x%x)\n",
893 bp->def_idx, bp->def_att_idx,
894 bp->attn_state, bp->spq_prod_idx);
895 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
896 bp->def_status_blk->atten_status_block.attn_bits,
897 bp->def_status_blk->atten_status_block.attn_bits_ack,
898 bp->def_status_blk->atten_status_block.status_block_id,
899 bp->def_status_blk->atten_status_block.attn_bits_index);
901 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
903 bp->def_status_blk->sp_sb.index_values[i],
904 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
906 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
907 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
908 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
911 pr_cont("igu_sb_id(0x%x) igu_seg_id (0x%x) "
912 "pf_id(0x%x) vnic_id(0x%x) "
913 "vf_id(0x%x) vf_valid (0x%x)\n",
914 sp_sb_data.igu_sb_id,
915 sp_sb_data.igu_seg_id,
916 sp_sb_data.p_func.pf_id,
917 sp_sb_data.p_func.vnic_id,
918 sp_sb_data.p_func.vf_id,
919 sp_sb_data.p_func.vf_valid);
922 for_each_eth_queue(bp, i) {
923 struct bnx2x_fastpath *fp = &bp->fp[i];
925 struct hc_status_block_data_e2 sb_data_e2;
926 struct hc_status_block_data_e1x sb_data_e1x;
927 struct hc_status_block_sm *hc_sm_p =
929 sb_data_e2.common.state_machine :
930 sb_data_e1x.common.state_machine;
931 struct hc_index_data *hc_index_p =
933 sb_data_e2.index_data :
934 sb_data_e1x.index_data;
939 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x)"
940 " rx_comp_prod(0x%x)"
941 " rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
942 i, fp->rx_bd_prod, fp->rx_bd_cons,
944 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
945 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x)"
946 " fp_hc_idx(0x%x)\n",
947 fp->rx_sge_prod, fp->last_max_sge,
948 le16_to_cpu(fp->fp_hc_idx));
951 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x)"
952 " tx_bd_prod(0x%x) tx_bd_cons(0x%x)"
953 " *tx_cons_sb(0x%x)\n",
954 i, fp->tx_pkt_prod, fp->tx_pkt_cons, fp->tx_bd_prod,
955 fp->tx_bd_cons, le16_to_cpu(*fp->tx_cons_sb));
957 loop = CHIP_IS_E2(bp) ?
958 HC_SB_MAX_INDICES_E2 : HC_SB_MAX_INDICES_E1X;
966 BNX2X_ERR(" run indexes (");
967 for (j = 0; j < HC_SB_MAX_SM; j++)
969 fp->sb_running_index[j],
970 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
972 BNX2X_ERR(" indexes (");
973 for (j = 0; j < loop; j++)
975 fp->sb_index_values[j],
976 (j == loop - 1) ? ")" : " ");
978 data_size = CHIP_IS_E2(bp) ?
979 sizeof(struct hc_status_block_data_e2) :
980 sizeof(struct hc_status_block_data_e1x);
981 data_size /= sizeof(u32);
982 sb_data_p = CHIP_IS_E2(bp) ?
985 /* copy sb data in here */
986 for (j = 0; j < data_size; j++)
987 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
988 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
991 if (CHIP_IS_E2(bp)) {
992 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
993 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
994 sb_data_e2.common.p_func.pf_id,
995 sb_data_e2.common.p_func.vf_id,
996 sb_data_e2.common.p_func.vf_valid,
997 sb_data_e2.common.p_func.vnic_id,
998 sb_data_e2.common.same_igu_sb_1b);
1000 pr_cont("pf_id(0x%x) vf_id (0x%x) vf_valid(0x%x) "
1001 "vnic_id(0x%x) same_igu_sb_1b(0x%x)\n",
1002 sb_data_e1x.common.p_func.pf_id,
1003 sb_data_e1x.common.p_func.vf_id,
1004 sb_data_e1x.common.p_func.vf_valid,
1005 sb_data_e1x.common.p_func.vnic_id,
1006 sb_data_e1x.common.same_igu_sb_1b);
1010 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011 pr_cont("SM[%d] __flags (0x%x) "
1012 "igu_sb_id (0x%x) igu_seg_id(0x%x) "
1013 "time_to_expire (0x%x) "
1014 "timer_value(0x%x)\n", j,
1016 hc_sm_p[j].igu_sb_id,
1017 hc_sm_p[j].igu_seg_id,
1018 hc_sm_p[j].time_to_expire,
1019 hc_sm_p[j].timer_value);
1023 for (j = 0; j < loop; j++) {
1024 pr_cont("INDEX[%d] flags (0x%x) "
1025 "timeout (0x%x)\n", j,
1026 hc_index_p[j].flags,
1027 hc_index_p[j].timeout);
1031 #ifdef BNX2X_STOP_ON_ERROR
1034 for_each_rx_queue(bp, i) {
1035 struct bnx2x_fastpath *fp = &bp->fp[i];
1037 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1038 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1039 for (j = start; j != end; j = RX_BD(j + 1)) {
1040 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1041 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1043 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1044 i, j, rx_bd[1], rx_bd[0], sw_bd->skb);
1047 start = RX_SGE(fp->rx_sge_prod);
1048 end = RX_SGE(fp->last_max_sge);
1049 for (j = start; j != end; j = RX_SGE(j + 1)) {
1050 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1051 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1053 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1054 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1057 start = RCQ_BD(fp->rx_comp_cons - 10);
1058 end = RCQ_BD(fp->rx_comp_cons + 503);
1059 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1060 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1062 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1063 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1068 for_each_tx_queue(bp, i) {
1069 struct bnx2x_fastpath *fp = &bp->fp[i];
1071 start = TX_BD(le16_to_cpu(*fp->tx_cons_sb) - 10);
1072 end = TX_BD(le16_to_cpu(*fp->tx_cons_sb) + 245);
1073 for (j = start; j != end; j = TX_BD(j + 1)) {
1074 struct sw_tx_bd *sw_bd = &fp->tx_buf_ring[j];
1076 BNX2X_ERR("fp%d: packet[%x]=[%p,%x]\n",
1077 i, j, sw_bd->skb, sw_bd->first_bd);
1080 start = TX_BD(fp->tx_bd_cons - 10);
1081 end = TX_BD(fp->tx_bd_cons + 254);
1082 for (j = start; j != end; j = TX_BD(j + 1)) {
1083 u32 *tx_bd = (u32 *)&fp->tx_desc_ring[j];
1085 BNX2X_ERR("fp%d: tx_bd[%x]=[%x:%x:%x:%x]\n",
1086 i, j, tx_bd[0], tx_bd[1], tx_bd[2], tx_bd[3]);
1091 bnx2x_mc_assert(bp);
1092 BNX2X_ERR("end crash dump -----------------\n");
1095 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1097 int port = BP_PORT(bp);
1098 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1099 u32 val = REG_RD(bp, addr);
1100 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1101 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1104 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1105 HC_CONFIG_0_REG_INT_LINE_EN_0);
1106 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1107 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1109 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1110 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1111 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1112 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1114 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1115 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1116 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1117 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1119 if (!CHIP_IS_E1(bp)) {
1120 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1123 REG_WR(bp, addr, val);
1125 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1130 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1132 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n",
1133 val, port, addr, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1135 REG_WR(bp, addr, val);
1137 * Ensure that HC_CONFIG is written before leading/trailing edge config
1142 if (!CHIP_IS_E1(bp)) {
1143 /* init leading/trailing edge */
1145 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1147 /* enable nig and gpio3 attention */
1152 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1153 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1156 /* Make sure that interrupts are indeed enabled from here on */
1160 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1163 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1164 int msi = (bp->flags & USING_MSI_FLAG) ? 1 : 0;
1166 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1169 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1170 IGU_PF_CONF_SINGLE_ISR_EN);
1171 val |= (IGU_PF_CONF_FUNC_EN |
1172 IGU_PF_CONF_MSI_MSIX_EN |
1173 IGU_PF_CONF_ATTN_BIT_EN);
1175 val &= ~IGU_PF_CONF_INT_LINE_EN;
1176 val |= (IGU_PF_CONF_FUNC_EN |
1177 IGU_PF_CONF_MSI_MSIX_EN |
1178 IGU_PF_CONF_ATTN_BIT_EN |
1179 IGU_PF_CONF_SINGLE_ISR_EN);
1181 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1182 val |= (IGU_PF_CONF_FUNC_EN |
1183 IGU_PF_CONF_INT_LINE_EN |
1184 IGU_PF_CONF_ATTN_BIT_EN |
1185 IGU_PF_CONF_SINGLE_ISR_EN);
1188 DP(NETIF_MSG_INTR, "write 0x%x to IGU mode %s\n",
1189 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1191 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1195 /* init leading/trailing edge */
1197 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4)));
1199 /* enable nig and gpio3 attention */
1204 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1205 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1207 /* Make sure that interrupts are indeed enabled from here on */
1211 void bnx2x_int_enable(struct bnx2x *bp)
1213 if (bp->common.int_block == INT_BLOCK_HC)
1214 bnx2x_hc_int_enable(bp);
1216 bnx2x_igu_int_enable(bp);
1219 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1221 int port = BP_PORT(bp);
1222 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1223 u32 val = REG_RD(bp, addr);
1226 * in E1 we must use only PCI configuration space to disable
1227 * MSI/MSIX capablility
1228 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1230 if (CHIP_IS_E1(bp)) {
1231 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1232 * Use mask register to prevent from HC sending interrupts
1233 * after we exit the function
1235 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1237 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1238 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1239 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1241 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1242 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1243 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1244 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1246 DP(NETIF_MSG_INTR, "write %x to HC %d (addr 0x%x)\n",
1249 /* flush all outstanding writes */
1252 REG_WR(bp, addr, val);
1253 if (REG_RD(bp, addr) != val)
1254 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1257 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1259 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1261 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1262 IGU_PF_CONF_INT_LINE_EN |
1263 IGU_PF_CONF_ATTN_BIT_EN);
1265 DP(NETIF_MSG_INTR, "write %x to IGU\n", val);
1267 /* flush all outstanding writes */
1270 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1271 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1272 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1275 static void bnx2x_int_disable(struct bnx2x *bp)
1277 if (bp->common.int_block == INT_BLOCK_HC)
1278 bnx2x_hc_int_disable(bp);
1280 bnx2x_igu_int_disable(bp);
1283 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1285 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1288 /* disable interrupt handling */
1289 atomic_inc(&bp->intr_sem);
1290 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
1293 /* prevent the HW from sending interrupts */
1294 bnx2x_int_disable(bp);
1296 /* make sure all ISRs are done */
1298 synchronize_irq(bp->msix_table[0].vector);
1303 for_each_eth_queue(bp, i)
1304 synchronize_irq(bp->msix_table[i + offset].vector);
1306 synchronize_irq(bp->pdev->irq);
1308 /* make sure sp_task is not running */
1309 cancel_delayed_work(&bp->sp_task);
1310 flush_workqueue(bnx2x_wq);
1316 * General service functions
1319 /* Return true if succeeded to acquire the lock */
1320 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1323 u32 resource_bit = (1 << resource);
1324 int func = BP_FUNC(bp);
1325 u32 hw_lock_control_reg;
1327 DP(NETIF_MSG_HW, "Trying to take a lock on resource %d\n", resource);
1329 /* Validating that the resource is within range */
1330 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1332 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1333 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1338 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1340 hw_lock_control_reg =
1341 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1343 /* Try to acquire the lock */
1344 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1345 lock_status = REG_RD(bp, hw_lock_control_reg);
1346 if (lock_status & resource_bit)
1349 DP(NETIF_MSG_HW, "Failed to get a lock on resource %d\n", resource);
1354 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid);
1357 void bnx2x_sp_event(struct bnx2x_fastpath *fp,
1358 union eth_rx_cqe *rr_cqe)
1360 struct bnx2x *bp = fp->bp;
1361 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1362 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1365 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1366 fp->index, cid, command, bp->state,
1367 rr_cqe->ramrod_cqe.ramrod_type);
1369 switch (command | fp->state) {
1370 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BNX2X_FP_STATE_OPENING):
1371 DP(NETIF_MSG_IFUP, "got MULTI[%d] setup ramrod\n", cid);
1372 fp->state = BNX2X_FP_STATE_OPEN;
1375 case (RAMROD_CMD_ID_ETH_HALT | BNX2X_FP_STATE_HALTING):
1376 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] halt ramrod\n", cid);
1377 fp->state = BNX2X_FP_STATE_HALTED;
1380 case (RAMROD_CMD_ID_ETH_TERMINATE | BNX2X_FP_STATE_TERMINATING):
1381 DP(NETIF_MSG_IFDOWN, "got MULTI[%d] teminate ramrod\n", cid);
1382 fp->state = BNX2X_FP_STATE_TERMINATED;
1386 BNX2X_ERR("unexpected MC reply (%d) "
1387 "fp[%d] state is %x\n",
1388 command, fp->index, fp->state);
1392 smp_mb__before_atomic_inc();
1393 atomic_inc(&bp->cq_spq_left);
1394 /* push the change in fp->state and towards the memory */
1400 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1402 struct bnx2x *bp = netdev_priv(dev_instance);
1403 u16 status = bnx2x_ack_int(bp);
1407 /* Return here if interrupt is shared and it's not for us */
1408 if (unlikely(status == 0)) {
1409 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1412 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1414 /* Return here if interrupt is disabled */
1415 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
1416 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
1420 #ifdef BNX2X_STOP_ON_ERROR
1421 if (unlikely(bp->panic))
1425 for_each_eth_queue(bp, i) {
1426 struct bnx2x_fastpath *fp = &bp->fp[i];
1428 mask = 0x2 << (fp->index + CNIC_CONTEXT_USE);
1429 if (status & mask) {
1430 /* Handle Rx and Tx according to SB id */
1431 prefetch(fp->rx_cons_sb);
1432 prefetch(fp->tx_cons_sb);
1433 prefetch(&fp->sb_running_index[SM_RX_ID]);
1434 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1441 if (status & (mask | 0x1)) {
1442 struct cnic_ops *c_ops = NULL;
1445 c_ops = rcu_dereference(bp->cnic_ops);
1447 c_ops->cnic_handler(bp->cnic_data, NULL);
1454 if (unlikely(status & 0x1)) {
1455 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1462 if (unlikely(status))
1463 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1469 /* end of fast path */
1475 * General service functions
1478 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1481 u32 resource_bit = (1 << resource);
1482 int func = BP_FUNC(bp);
1483 u32 hw_lock_control_reg;
1486 /* Validating that the resource is within range */
1487 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1489 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1490 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1495 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1497 hw_lock_control_reg =
1498 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1501 /* Validating that the resource is not already taken */
1502 lock_status = REG_RD(bp, hw_lock_control_reg);
1503 if (lock_status & resource_bit) {
1504 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1505 lock_status, resource_bit);
1509 /* Try for 5 second every 5ms */
1510 for (cnt = 0; cnt < 1000; cnt++) {
1511 /* Try to acquire the lock */
1512 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1513 lock_status = REG_RD(bp, hw_lock_control_reg);
1514 if (lock_status & resource_bit)
1519 DP(NETIF_MSG_HW, "Timeout\n");
1523 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1526 u32 resource_bit = (1 << resource);
1527 int func = BP_FUNC(bp);
1528 u32 hw_lock_control_reg;
1530 DP(NETIF_MSG_HW, "Releasing a lock on resource %d\n", resource);
1532 /* Validating that the resource is within range */
1533 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1535 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1536 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1541 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1543 hw_lock_control_reg =
1544 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1547 /* Validating that the resource is currently taken */
1548 lock_status = REG_RD(bp, hw_lock_control_reg);
1549 if (!(lock_status & resource_bit)) {
1550 DP(NETIF_MSG_HW, "lock_status 0x%x resource_bit 0x%x\n",
1551 lock_status, resource_bit);
1555 REG_WR(bp, hw_lock_control_reg, resource_bit);
1560 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1562 /* The GPIO should be swapped if swap register is set and active */
1563 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1564 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1565 int gpio_shift = gpio_num +
1566 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1567 u32 gpio_mask = (1 << gpio_shift);
1571 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1572 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1576 /* read GPIO value */
1577 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1579 /* get the requested pin value */
1580 if ((gpio_reg & gpio_mask) == gpio_mask)
1585 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1590 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1592 /* The GPIO should be swapped if swap register is set and active */
1593 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1594 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1595 int gpio_shift = gpio_num +
1596 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1597 u32 gpio_mask = (1 << gpio_shift);
1600 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1601 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1605 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1606 /* read GPIO and mask except the float bits */
1607 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1610 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1611 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output low\n",
1612 gpio_num, gpio_shift);
1613 /* clear FLOAT and set CLR */
1614 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1615 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1618 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1619 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> output high\n",
1620 gpio_num, gpio_shift);
1621 /* clear FLOAT and set SET */
1622 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1623 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1626 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1627 DP(NETIF_MSG_LINK, "Set GPIO %d (shift %d) -> input\n",
1628 gpio_num, gpio_shift);
1630 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1637 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1638 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1643 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1645 /* The GPIO should be swapped if swap register is set and active */
1646 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1647 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1648 int gpio_shift = gpio_num +
1649 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1650 u32 gpio_mask = (1 << gpio_shift);
1653 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1654 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1658 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1660 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
1663 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
1664 DP(NETIF_MSG_LINK, "Clear GPIO INT %d (shift %d) -> "
1665 "output low\n", gpio_num, gpio_shift);
1666 /* clear SET and set CLR */
1667 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1668 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1671 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
1672 DP(NETIF_MSG_LINK, "Set GPIO INT %d (shift %d) -> "
1673 "output high\n", gpio_num, gpio_shift);
1674 /* clear CLR and set SET */
1675 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
1676 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
1683 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
1684 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1689 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
1691 u32 spio_mask = (1 << spio_num);
1694 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
1695 (spio_num > MISC_REGISTERS_SPIO_7)) {
1696 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
1700 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1701 /* read SPIO and mask except the float bits */
1702 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
1705 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
1706 DP(NETIF_MSG_LINK, "Set SPIO %d -> output low\n", spio_num);
1707 /* clear FLOAT and set CLR */
1708 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1709 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
1712 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
1713 DP(NETIF_MSG_LINK, "Set SPIO %d -> output high\n", spio_num);
1714 /* clear FLOAT and set SET */
1715 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1716 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
1719 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
1720 DP(NETIF_MSG_LINK, "Set SPIO %d -> input\n", spio_num);
1722 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
1729 REG_WR(bp, MISC_REG_SPIO, spio_reg);
1730 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
1735 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
1737 u32 sel_phy_idx = 0;
1738 if (bp->link_vars.link_up) {
1739 sel_phy_idx = EXT_PHY1;
1740 /* In case link is SERDES, check if the EXT_PHY2 is the one */
1741 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
1742 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
1743 sel_phy_idx = EXT_PHY2;
1746 switch (bnx2x_phy_selection(&bp->link_params)) {
1747 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
1748 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
1749 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
1750 sel_phy_idx = EXT_PHY1;
1752 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
1753 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
1754 sel_phy_idx = EXT_PHY2;
1759 * The selected actived PHY is always after swapping (in case PHY
1760 * swapping is enabled). So when swapping is enabled, we need to reverse
1764 if (bp->link_params.multi_phy_config &
1765 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
1766 if (sel_phy_idx == EXT_PHY1)
1767 sel_phy_idx = EXT_PHY2;
1768 else if (sel_phy_idx == EXT_PHY2)
1769 sel_phy_idx = EXT_PHY1;
1771 return LINK_CONFIG_IDX(sel_phy_idx);
1774 void bnx2x_calc_fc_adv(struct bnx2x *bp)
1776 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1777 switch (bp->link_vars.ieee_fc &
1778 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
1779 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
1780 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1784 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
1785 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
1789 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
1790 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
1794 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
1800 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
1802 if (!BP_NOMCP(bp)) {
1804 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
1805 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
1806 /* Initialize link parameters structure variables */
1807 /* It is recommended to turn off RX FC for jumbo frames
1808 for better performance */
1809 if ((CHIP_IS_E1x(bp)) && (bp->dev->mtu > 5000))
1810 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
1812 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
1814 bnx2x_acquire_phy_lock(bp);
1816 if (load_mode == LOAD_DIAG) {
1817 bp->link_params.loopback_mode = LOOPBACK_XGXS;
1818 bp->link_params.req_line_speed[cfx_idx] = SPEED_10000;
1821 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1823 bnx2x_release_phy_lock(bp);
1825 bnx2x_calc_fc_adv(bp);
1827 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
1828 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
1829 bnx2x_link_report(bp);
1831 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
1834 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
1838 void bnx2x_link_set(struct bnx2x *bp)
1840 if (!BP_NOMCP(bp)) {
1841 bnx2x_acquire_phy_lock(bp);
1842 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1843 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1844 bnx2x_release_phy_lock(bp);
1846 bnx2x_calc_fc_adv(bp);
1848 BNX2X_ERR("Bootcode is missing - can not set link\n");
1851 static void bnx2x__link_reset(struct bnx2x *bp)
1853 if (!BP_NOMCP(bp)) {
1854 bnx2x_acquire_phy_lock(bp);
1855 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
1856 bnx2x_release_phy_lock(bp);
1858 BNX2X_ERR("Bootcode is missing - can not reset link\n");
1861 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
1865 if (!BP_NOMCP(bp)) {
1866 bnx2x_acquire_phy_lock(bp);
1867 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
1869 bnx2x_release_phy_lock(bp);
1871 BNX2X_ERR("Bootcode is missing - can not test link\n");
1876 static void bnx2x_init_port_minmax(struct bnx2x *bp)
1878 u32 r_param = bp->link_vars.line_speed / 8;
1879 u32 fair_periodic_timeout_usec;
1882 memset(&(bp->cmng.rs_vars), 0,
1883 sizeof(struct rate_shaping_vars_per_port));
1884 memset(&(bp->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
1886 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
1887 bp->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
1889 /* this is the threshold below which no timer arming will occur
1890 1.25 coefficient is for the threshold to be a little bigger
1891 than the real time, to compensate for timer in-accuracy */
1892 bp->cmng.rs_vars.rs_threshold =
1893 (RS_PERIODIC_TIMEOUT_USEC * r_param * 5) / 4;
1895 /* resolution of fairness timer */
1896 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
1897 /* for 10G it is 1000usec. for 1G it is 10000usec. */
1898 t_fair = T_FAIR_COEF / bp->link_vars.line_speed;
1900 /* this is the threshold below which we won't arm the timer anymore */
1901 bp->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
1903 /* we multiply by 1e3/8 to get bytes/msec.
1904 We don't want the credits to pass a credit
1905 of the t_fair*FAIR_MEM (algorithm resolution) */
1906 bp->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
1907 /* since each tick is 4 usec */
1908 bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
1911 /* Calculates the sum of vn_min_rates.
1912 It's needed for further normalizing of the min_rates.
1914 sum of vn_min_rates.
1916 0 - if all the min_rates are 0.
1917 In the later case fainess algorithm should be deactivated.
1918 If not all min_rates are zero then those that are zeroes will be set to 1.
1920 static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
1925 bp->vn_weight_sum = 0;
1926 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
1927 u32 vn_cfg = bp->mf_config[vn];
1928 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1929 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1931 /* Skip hidden vns */
1932 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
1935 /* If min rate is zero - set it to 1 */
1937 vn_min_rate = DEF_MIN_RATE;
1941 bp->vn_weight_sum += vn_min_rate;
1944 /* ... only if all min rates are zeros - disable fairness */
1946 bp->cmng.flags.cmng_enables &=
1947 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1948 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
1949 " fairness will be disabled\n");
1951 bp->cmng.flags.cmng_enables |=
1952 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
1955 static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
1957 struct rate_shaping_vars_per_vn m_rs_vn;
1958 struct fairness_vars_per_vn m_fair_vn;
1959 u32 vn_cfg = bp->mf_config[vn];
1960 int func = 2*vn + BP_PORT(bp);
1961 u16 vn_min_rate, vn_max_rate;
1964 /* If function is hidden - set min and max to zeroes */
1965 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
1970 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
1972 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
1973 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
1974 /* If fairness is enabled (not all min rates are zeroes) and
1975 if current min rate is zero - set it to 1.
1976 This is a requirement of the algorithm. */
1977 if (bp->vn_weight_sum && (vn_min_rate == 0))
1978 vn_min_rate = DEF_MIN_RATE;
1981 /* maxCfg in percents of linkspeed */
1982 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
1984 /* maxCfg is absolute in 100Mb units */
1985 vn_max_rate = maxCfg * 100;
1989 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
1990 func, vn_min_rate, vn_max_rate, bp->vn_weight_sum);
1992 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
1993 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
1995 /* global vn counter - maximal Mbps for this vn */
1996 m_rs_vn.vn_counter.rate = vn_max_rate;
1998 /* quota - number of bytes transmitted in this period */
1999 m_rs_vn.vn_counter.quota =
2000 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
2002 if (bp->vn_weight_sum) {
2003 /* credit for each period of the fairness algorithm:
2004 number of bytes in T_FAIR (the vn share the port rate).
2005 vn_weight_sum should not be larger than 10000, thus
2006 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2008 m_fair_vn.vn_credit_delta =
2009 max_t(u32, (vn_min_rate * (T_FAIR_COEF /
2010 (8 * bp->vn_weight_sum))),
2011 (bp->cmng.fair_vars.fair_threshold +
2013 DP(NETIF_MSG_IFUP, "m_fair_vn.vn_credit_delta %d\n",
2014 m_fair_vn.vn_credit_delta);
2017 /* Store it to internal memory */
2018 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn)/4; i++)
2019 REG_WR(bp, BAR_XSTRORM_INTMEM +
2020 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + i * 4,
2021 ((u32 *)(&m_rs_vn))[i]);
2023 for (i = 0; i < sizeof(struct fairness_vars_per_vn)/4; i++)
2024 REG_WR(bp, BAR_XSTRORM_INTMEM +
2025 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + i * 4,
2026 ((u32 *)(&m_fair_vn))[i]);
2029 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2031 if (CHIP_REV_IS_SLOW(bp))
2032 return CMNG_FNS_NONE;
2034 return CMNG_FNS_MINMAX;
2036 return CMNG_FNS_NONE;
2039 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2041 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2044 return; /* what should be the default bvalue in this case */
2046 /* For 2 port configuration the absolute function number formula
2048 * abs_func = 2 * vn + BP_PORT + BP_PATH
2050 * and there are 4 functions per port
2052 * For 4 port configuration it is
2053 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2055 * and there are 2 functions per port
2057 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2058 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2060 if (func >= E1H_FUNC_MAX)
2064 MF_CFG_RD(bp, func_mf_config[func].config);
2068 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2071 if (cmng_type == CMNG_FNS_MINMAX) {
2074 /* clear cmng_enables */
2075 bp->cmng.flags.cmng_enables = 0;
2077 /* read mf conf from shmem */
2079 bnx2x_read_mf_cfg(bp);
2081 /* Init rate shaping and fairness contexts */
2082 bnx2x_init_port_minmax(bp);
2084 /* vn_weight_sum and enable fairness if not 0 */
2085 bnx2x_calc_vn_weight_sum(bp);
2087 /* calculate and set min-max rate for each vn */
2089 for (vn = VN_0; vn < E1HVN_MAX; vn++)
2090 bnx2x_init_vn_minmax(bp, vn);
2092 /* always enable rate shaping and fairness */
2093 bp->cmng.flags.cmng_enables |=
2094 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2095 if (!bp->vn_weight_sum)
2096 DP(NETIF_MSG_IFUP, "All MIN values are zeroes"
2097 " fairness will be disabled\n");
2101 /* rate shaping and fairness are disabled */
2103 "rate shaping and fairness are disabled\n");
2106 static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2108 int port = BP_PORT(bp);
2112 /* Set the attention towards other drivers on the same port */
2113 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
2114 if (vn == BP_E1HVN(bp))
2117 func = ((vn << 1) | port);
2118 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2119 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2123 /* This function is called upon link interrupt */
2124 static void bnx2x_link_attn(struct bnx2x *bp)
2126 /* Make sure that we are synced with the current statistics */
2127 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2129 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2131 if (bp->link_vars.link_up) {
2133 /* dropless flow control */
2134 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2135 int port = BP_PORT(bp);
2136 u32 pause_enabled = 0;
2138 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2141 REG_WR(bp, BAR_USTRORM_INTMEM +
2142 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2146 if (bp->link_vars.mac_type == MAC_TYPE_BMAC) {
2147 struct host_port_stats *pstats;
2149 pstats = bnx2x_sp(bp, port_stats);
2150 /* reset old bmac stats */
2151 memset(&(pstats->mac_stx[0]), 0,
2152 sizeof(struct mac_stx));
2154 if (bp->state == BNX2X_STATE_OPEN)
2155 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2158 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2159 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2161 if (cmng_fns != CMNG_FNS_NONE) {
2162 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2163 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2165 /* rate shaping and fairness are disabled */
2167 "single function mode without fairness\n");
2170 __bnx2x_link_report(bp);
2173 bnx2x_link_sync_notify(bp);
2176 void bnx2x__link_status_update(struct bnx2x *bp)
2178 if (bp->state != BNX2X_STATE_OPEN)
2181 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2183 if (bp->link_vars.link_up)
2184 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2186 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2188 /* indicate link status */
2189 bnx2x_link_report(bp);
2192 static void bnx2x_pmf_update(struct bnx2x *bp)
2194 int port = BP_PORT(bp);
2198 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2200 /* enable nig attention */
2201 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4)));
2202 if (bp->common.int_block == INT_BLOCK_HC) {
2203 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2204 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2205 } else if (CHIP_IS_E2(bp)) {
2206 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2207 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2210 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2218 * General service functions
2221 /* send the MCP a request, block until there is a reply */
2222 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2224 int mb_idx = BP_FW_MB_IDX(bp);
2225 u32 seq = ++bp->fw_seq;
2228 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2230 mutex_lock(&bp->fw_mb_mutex);
2231 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2232 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2234 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
2237 /* let the FW do it's magic ... */
2240 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2242 /* Give the FW up to 5 second (500*10ms) */
2243 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2245 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2246 cnt*delay, rc, seq);
2248 /* is this a reply to our command? */
2249 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2250 rc &= FW_MSG_CODE_MASK;
2253 BNX2X_ERR("FW failed to respond!\n");
2257 mutex_unlock(&bp->fw_mb_mutex);
2262 static u8 stat_counter_valid(struct bnx2x *bp, struct bnx2x_fastpath *fp)
2265 if (IS_FCOE_FP(fp) && IS_MF(bp))
2271 /* must be called under rtnl_lock */
2272 static void bnx2x_rxq_set_mac_filters(struct bnx2x *bp, u16 cl_id, u32 filters)
2274 u32 mask = (1 << cl_id);
2276 /* initial seeting is BNX2X_ACCEPT_NONE */
2277 u8 drop_all_ucast = 1, drop_all_bcast = 1, drop_all_mcast = 1;
2278 u8 accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2279 u8 unmatched_unicast = 0;
2281 if (filters & BNX2X_ACCEPT_UNMATCHED_UCAST)
2282 unmatched_unicast = 1;
2284 if (filters & BNX2X_PROMISCUOUS_MODE) {
2285 /* promiscious - accept all, drop none */
2286 drop_all_ucast = drop_all_bcast = drop_all_mcast = 0;
2287 accp_all_ucast = accp_all_bcast = accp_all_mcast = 1;
2290 * SI mode defines to accept in promiscuos mode
2291 * only unmatched packets
2293 unmatched_unicast = 1;
2297 if (filters & BNX2X_ACCEPT_UNICAST) {
2298 /* accept matched ucast */
2301 if (filters & BNX2X_ACCEPT_MULTICAST)
2302 /* accept matched mcast */
2305 if (filters & BNX2X_ACCEPT_ALL_UNICAST) {
2306 /* accept all mcast */
2310 if (filters & BNX2X_ACCEPT_ALL_MULTICAST) {
2311 /* accept all mcast */
2315 if (filters & BNX2X_ACCEPT_BROADCAST) {
2316 /* accept (all) bcast */
2321 bp->mac_filters.ucast_drop_all = drop_all_ucast ?
2322 bp->mac_filters.ucast_drop_all | mask :
2323 bp->mac_filters.ucast_drop_all & ~mask;
2325 bp->mac_filters.mcast_drop_all = drop_all_mcast ?
2326 bp->mac_filters.mcast_drop_all | mask :
2327 bp->mac_filters.mcast_drop_all & ~mask;
2329 bp->mac_filters.bcast_drop_all = drop_all_bcast ?
2330 bp->mac_filters.bcast_drop_all | mask :
2331 bp->mac_filters.bcast_drop_all & ~mask;
2333 bp->mac_filters.ucast_accept_all = accp_all_ucast ?
2334 bp->mac_filters.ucast_accept_all | mask :
2335 bp->mac_filters.ucast_accept_all & ~mask;
2337 bp->mac_filters.mcast_accept_all = accp_all_mcast ?
2338 bp->mac_filters.mcast_accept_all | mask :
2339 bp->mac_filters.mcast_accept_all & ~mask;
2341 bp->mac_filters.bcast_accept_all = accp_all_bcast ?
2342 bp->mac_filters.bcast_accept_all | mask :
2343 bp->mac_filters.bcast_accept_all & ~mask;
2345 bp->mac_filters.unmatched_unicast = unmatched_unicast ?
2346 bp->mac_filters.unmatched_unicast | mask :
2347 bp->mac_filters.unmatched_unicast & ~mask;
2350 static void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2352 struct tstorm_eth_function_common_config tcfg = {0};
2356 if (p->func_flgs & FUNC_FLG_TPA)
2357 tcfg.config_flags |=
2358 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
2361 rss_flgs = (p->rss->mode <<
2362 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT);
2364 if (p->rss->cap & RSS_IPV4_CAP)
2365 rss_flgs |= RSS_IPV4_CAP_MASK;
2366 if (p->rss->cap & RSS_IPV4_TCP_CAP)
2367 rss_flgs |= RSS_IPV4_TCP_CAP_MASK;
2368 if (p->rss->cap & RSS_IPV6_CAP)
2369 rss_flgs |= RSS_IPV6_CAP_MASK;
2370 if (p->rss->cap & RSS_IPV6_TCP_CAP)
2371 rss_flgs |= RSS_IPV6_TCP_CAP_MASK;
2373 tcfg.config_flags |= rss_flgs;
2374 tcfg.rss_result_mask = p->rss->result_mask;
2376 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2378 /* Enable the function in the FW */
2379 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2380 storm_memset_func_en(bp, p->func_id, 1);
2383 if (p->func_flgs & FUNC_FLG_STATS) {
2384 struct stats_indication_flags stats_flags = {0};
2385 stats_flags.collect_eth = 1;
2387 storm_memset_xstats_flags(bp, &stats_flags, p->func_id);
2388 storm_memset_xstats_addr(bp, p->fw_stat_map, p->func_id);
2390 storm_memset_tstats_flags(bp, &stats_flags, p->func_id);
2391 storm_memset_tstats_addr(bp, p->fw_stat_map, p->func_id);
2393 storm_memset_ustats_flags(bp, &stats_flags, p->func_id);
2394 storm_memset_ustats_addr(bp, p->fw_stat_map, p->func_id);
2396 storm_memset_cstats_flags(bp, &stats_flags, p->func_id);
2397 storm_memset_cstats_addr(bp, p->fw_stat_map, p->func_id);
2401 if (p->func_flgs & FUNC_FLG_SPQ) {
2402 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2403 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2404 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2408 static inline u16 bnx2x_get_cl_flags(struct bnx2x *bp,
2409 struct bnx2x_fastpath *fp)
2413 /* calculate queue flags */
2414 flags |= QUEUE_FLG_CACHE_ALIGN;
2415 flags |= QUEUE_FLG_HC;
2416 flags |= IS_MF_SD(bp) ? QUEUE_FLG_OV : 0;
2418 flags |= QUEUE_FLG_VLAN;
2419 DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
2421 if (!fp->disable_tpa)
2422 flags |= QUEUE_FLG_TPA;
2424 flags = stat_counter_valid(bp, fp) ?
2425 (flags | QUEUE_FLG_STATS) : (flags & ~QUEUE_FLG_STATS);
2430 static void bnx2x_pf_rx_cl_prep(struct bnx2x *bp,
2431 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2432 struct bnx2x_rxq_init_params *rxq_init)
2436 u16 tpa_agg_size = 0;
2438 /* calculate queue flags */
2439 u16 flags = bnx2x_get_cl_flags(bp, fp);
2441 if (!fp->disable_tpa) {
2442 pause->sge_th_hi = 250;
2443 pause->sge_th_lo = 150;
2444 tpa_agg_size = min_t(u32,
2445 (min_t(u32, 8, MAX_SKB_FRAGS) *
2446 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2447 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2449 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2450 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2451 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2455 /* pause - not for e1 */
2456 if (!CHIP_IS_E1(bp)) {
2457 pause->bd_th_hi = 350;
2458 pause->bd_th_lo = 250;
2459 pause->rcq_th_hi = 350;
2460 pause->rcq_th_lo = 250;
2461 pause->sge_th_hi = 0;
2462 pause->sge_th_lo = 0;
2467 rxq_init->flags = flags;
2468 rxq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2469 rxq_init->dscr_map = fp->rx_desc_mapping;
2470 rxq_init->sge_map = fp->rx_sge_mapping;
2471 rxq_init->rcq_map = fp->rx_comp_mapping;
2472 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2474 /* Always use mini-jumbo MTU for FCoE L2 ring */
2476 rxq_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2478 rxq_init->mtu = bp->dev->mtu;
2480 rxq_init->buf_sz = fp->rx_buf_size;
2481 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2482 rxq_init->cl_id = fp->cl_id;
2483 rxq_init->spcl_id = fp->cl_id;
2484 rxq_init->stat_id = fp->cl_id;
2485 rxq_init->tpa_agg_sz = tpa_agg_size;
2486 rxq_init->sge_buf_sz = sge_sz;
2487 rxq_init->max_sges_pkt = max_sge;
2488 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2489 rxq_init->fw_sb_id = fp->fw_sb_id;
2492 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2494 rxq_init->sb_cq_index = U_SB_ETH_RX_CQ_INDEX;
2496 rxq_init->cid = HW_CID(bp, fp->cid);
2498 rxq_init->hc_rate = bp->rx_ticks ? (1000000 / bp->rx_ticks) : 0;
2501 static void bnx2x_pf_tx_cl_prep(struct bnx2x *bp,
2502 struct bnx2x_fastpath *fp, struct bnx2x_txq_init_params *txq_init)
2504 u16 flags = bnx2x_get_cl_flags(bp, fp);
2506 txq_init->flags = flags;
2507 txq_init->cxt = &bp->context.vcxt[fp->cid].eth;
2508 txq_init->dscr_map = fp->tx_desc_mapping;
2509 txq_init->stat_id = fp->cl_id;
2510 txq_init->cid = HW_CID(bp, fp->cid);
2511 txq_init->sb_cq_index = C_SB_ETH_TX_CQ_INDEX;
2512 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2513 txq_init->fw_sb_id = fp->fw_sb_id;
2515 if (IS_FCOE_FP(fp)) {
2516 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2517 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2520 txq_init->hc_rate = bp->tx_ticks ? (1000000 / bp->tx_ticks) : 0;
2523 static void bnx2x_pf_init(struct bnx2x *bp)
2525 struct bnx2x_func_init_params func_init = {0};
2526 struct bnx2x_rss_params rss = {0};
2527 struct event_ring_data eq_data = { {0} };
2530 /* pf specific setups */
2531 if (!CHIP_IS_E1(bp))
2532 storm_memset_ov(bp, bp->mf_ov, BP_FUNC(bp));
2534 if (CHIP_IS_E2(bp)) {
2535 /* reset IGU PF statistics: MSIX + ATTN */
2537 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2538 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2539 (CHIP_MODE_IS_4_PORT(bp) ?
2540 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2542 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2543 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2544 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2545 (CHIP_MODE_IS_4_PORT(bp) ?
2546 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2549 /* function setup flags */
2550 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2552 if (CHIP_IS_E1x(bp))
2553 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2555 flags |= FUNC_FLG_TPA;
2557 /* function setup */
2560 * Although RSS is meaningless when there is a single HW queue we
2561 * still need it enabled in order to have HW Rx hash generated.
2563 rss.cap = (RSS_IPV4_CAP | RSS_IPV4_TCP_CAP |
2564 RSS_IPV6_CAP | RSS_IPV6_TCP_CAP);
2565 rss.mode = bp->multi_mode;
2566 rss.result_mask = MULTI_MASK;
2567 func_init.rss = &rss;
2569 func_init.func_flgs = flags;
2570 func_init.pf_id = BP_FUNC(bp);
2571 func_init.func_id = BP_FUNC(bp);
2572 func_init.fw_stat_map = bnx2x_sp_mapping(bp, fw_stats);
2573 func_init.spq_map = bp->spq_mapping;
2574 func_init.spq_prod = bp->spq_prod_idx;
2576 bnx2x_func_init(bp, &func_init);
2578 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2581 Congestion management values depend on the link rate
2582 There is no active link so initial link rate is set to 10 Gbps.
2583 When the link comes up The congestion management values are
2584 re-calculated according to the actual link rate.
2586 bp->link_vars.line_speed = SPEED_10000;
2587 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
2589 /* Only the PMF sets the HW */
2591 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2593 /* no rx until link is up */
2594 bp->rx_mode = BNX2X_RX_MODE_NONE;
2595 bnx2x_set_storm_rx_mode(bp);
2597 /* init Event Queue */
2598 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
2599 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
2600 eq_data.producer = bp->eq_prod;
2601 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
2602 eq_data.sb_id = DEF_SB_ID;
2603 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
2607 static void bnx2x_e1h_disable(struct bnx2x *bp)
2609 int port = BP_PORT(bp);
2611 netif_tx_disable(bp->dev);
2613 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
2615 netif_carrier_off(bp->dev);
2618 static void bnx2x_e1h_enable(struct bnx2x *bp)
2620 int port = BP_PORT(bp);
2622 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
2624 /* Tx queue should be only reenabled */
2625 netif_tx_wake_all_queues(bp->dev);
2628 * Should not call netif_carrier_on since it will be called if the link
2629 * is up when checking for link state
2633 /* called due to MCP event (on pmf):
2634 * reread new bandwidth configuration
2636 * notify others function about the change
2638 static inline void bnx2x_config_mf_bw(struct bnx2x *bp)
2640 if (bp->link_vars.link_up) {
2641 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
2642 bnx2x_link_sync_notify(bp);
2644 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2647 static inline void bnx2x_set_mf_bw(struct bnx2x *bp)
2649 bnx2x_config_mf_bw(bp);
2650 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
2653 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
2655 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
2657 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
2660 * This is the only place besides the function initialization
2661 * where the bp->flags can change so it is done without any
2664 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2665 DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
2666 bp->flags |= MF_FUNC_DIS;
2668 bnx2x_e1h_disable(bp);
2670 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2671 bp->flags &= ~MF_FUNC_DIS;
2673 bnx2x_e1h_enable(bp);
2675 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
2677 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
2678 bnx2x_config_mf_bw(bp);
2679 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
2682 /* Report results to MCP */
2684 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
2686 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
2689 /* must be called under the spq lock */
2690 static inline struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
2692 struct eth_spe *next_spe = bp->spq_prod_bd;
2694 if (bp->spq_prod_bd == bp->spq_last_bd) {
2695 bp->spq_prod_bd = bp->spq;
2696 bp->spq_prod_idx = 0;
2697 DP(NETIF_MSG_TIMER, "end of spq\n");
2705 /* must be called under the spq lock */
2706 static inline void bnx2x_sp_prod_update(struct bnx2x *bp)
2708 int func = BP_FUNC(bp);
2710 /* Make sure that BD data is updated before writing the producer */
2713 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
2718 /* the slow path queue is odd since completions arrive on the fastpath ring */
2719 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2720 u32 data_hi, u32 data_lo, int common)
2722 struct eth_spe *spe;
2725 #ifdef BNX2X_STOP_ON_ERROR
2726 if (unlikely(bp->panic))
2730 spin_lock_bh(&bp->spq_lock);
2733 if (!atomic_read(&bp->eq_spq_left)) {
2734 BNX2X_ERR("BUG! EQ ring full!\n");
2735 spin_unlock_bh(&bp->spq_lock);
2739 } else if (!atomic_read(&bp->cq_spq_left)) {
2740 BNX2X_ERR("BUG! SPQ ring full!\n");
2741 spin_unlock_bh(&bp->spq_lock);
2746 spe = bnx2x_sp_get_next(bp);
2748 /* CID needs port number to be encoded int it */
2749 spe->hdr.conn_and_cmd_data =
2750 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
2755 * FUNC_START, FUNC_STOP, CFC_DEL, STATS, SET_MAC
2756 * TRAFFIC_STOP, TRAFFIC_START
2758 type = (NONE_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2759 & SPE_HDR_CONN_TYPE;
2761 /* ETH ramrods: SETUP, HALT */
2762 type = (ETH_CONNECTION_TYPE << SPE_HDR_CONN_TYPE_SHIFT)
2763 & SPE_HDR_CONN_TYPE;
2765 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
2766 SPE_HDR_FUNCTION_ID);
2768 spe->hdr.type = cpu_to_le16(type);
2770 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
2771 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
2773 /* stats ramrod has it's own slot on the spq */
2774 if (command != RAMROD_CMD_ID_COMMON_STAT_QUERY) {
2775 /* It's ok if the actual decrement is issued towards the memory
2776 * somewhere between the spin_lock and spin_unlock. Thus no
2777 * more explict memory barrier is needed.
2780 atomic_dec(&bp->eq_spq_left);
2782 atomic_dec(&bp->cq_spq_left);
2786 DP(BNX2X_MSG_SP/*NETIF_MSG_TIMER*/,
2787 "SPQE[%x] (%x:%x) command %d hw_cid %x data (%x:%x) "
2788 "type(0x%x) left (ETH, COMMON) (%x,%x)\n",
2789 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
2790 (u32)(U64_LO(bp->spq_mapping) +
2791 (void *)bp->spq_prod_bd - (void *)bp->spq), command,
2792 HW_CID(bp, cid), data_hi, data_lo, type,
2793 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
2795 bnx2x_sp_prod_update(bp);
2796 spin_unlock_bh(&bp->spq_lock);
2800 /* acquire split MCP access lock register */
2801 static int bnx2x_acquire_alr(struct bnx2x *bp)
2807 for (j = 0; j < 1000; j++) {
2809 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
2810 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
2811 if (val & (1L << 31))
2816 if (!(val & (1L << 31))) {
2817 BNX2X_ERR("Cannot acquire MCP access lock register\n");
2824 /* release split MCP access lock register */
2825 static void bnx2x_release_alr(struct bnx2x *bp)
2827 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
2830 #define BNX2X_DEF_SB_ATT_IDX 0x0001
2831 #define BNX2X_DEF_SB_IDX 0x0002
2833 static inline u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
2835 struct host_sp_status_block *def_sb = bp->def_status_blk;
2838 barrier(); /* status block is written to by the chip */
2839 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
2840 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
2841 rc |= BNX2X_DEF_SB_ATT_IDX;
2844 if (bp->def_idx != def_sb->sp_sb.running_index) {
2845 bp->def_idx = def_sb->sp_sb.running_index;
2846 rc |= BNX2X_DEF_SB_IDX;
2849 /* Do not reorder: indecies reading should complete before handling */
2855 * slow path service functions
2858 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
2860 int port = BP_PORT(bp);
2861 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
2862 MISC_REG_AEU_MASK_ATTN_FUNC_0;
2863 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
2864 NIG_REG_MASK_INTERRUPT_PORT0;
2869 if (bp->attn_state & asserted)
2870 BNX2X_ERR("IGU ERROR\n");
2872 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2873 aeu_mask = REG_RD(bp, aeu_addr);
2875 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
2876 aeu_mask, asserted);
2877 aeu_mask &= ~(asserted & 0x3ff);
2878 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
2880 REG_WR(bp, aeu_addr, aeu_mask);
2881 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
2883 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
2884 bp->attn_state |= asserted;
2885 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
2887 if (asserted & ATTN_HARD_WIRED_MASK) {
2888 if (asserted & ATTN_NIG_FOR_FUNC) {
2890 bnx2x_acquire_phy_lock(bp);
2892 /* save nig interrupt mask */
2893 nig_mask = REG_RD(bp, nig_int_mask_addr);
2894 REG_WR(bp, nig_int_mask_addr, 0);
2896 bnx2x_link_attn(bp);
2898 /* handle unicore attn? */
2900 if (asserted & ATTN_SW_TIMER_4_FUNC)
2901 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
2903 if (asserted & GPIO_2_FUNC)
2904 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
2906 if (asserted & GPIO_3_FUNC)
2907 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
2909 if (asserted & GPIO_4_FUNC)
2910 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
2913 if (asserted & ATTN_GENERAL_ATTN_1) {
2914 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
2915 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
2917 if (asserted & ATTN_GENERAL_ATTN_2) {
2918 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
2919 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
2921 if (asserted & ATTN_GENERAL_ATTN_3) {
2922 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
2923 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
2926 if (asserted & ATTN_GENERAL_ATTN_4) {
2927 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
2928 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
2930 if (asserted & ATTN_GENERAL_ATTN_5) {
2931 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
2932 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
2934 if (asserted & ATTN_GENERAL_ATTN_6) {
2935 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
2936 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
2940 } /* if hardwired */
2942 if (bp->common.int_block == INT_BLOCK_HC)
2943 reg_addr = (HC_REG_COMMAND_REG + port*32 +
2944 COMMAND_REG_ATTN_BITS_SET);
2946 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
2948 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
2949 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
2950 REG_WR(bp, reg_addr, asserted);
2952 /* now set back the mask */
2953 if (asserted & ATTN_NIG_FOR_FUNC) {
2954 REG_WR(bp, nig_int_mask_addr, nig_mask);
2955 bnx2x_release_phy_lock(bp);
2959 static inline void bnx2x_fan_failure(struct bnx2x *bp)
2961 int port = BP_PORT(bp);
2963 /* mark the failure */
2966 dev_info.port_hw_config[port].external_phy_config);
2968 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2969 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
2970 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
2973 /* log the failure */
2974 netdev_err(bp->dev, "Fan Failure on Network Controller has caused"
2975 " the driver to shutdown the card to prevent permanent"
2976 " damage. Please contact OEM Support for assistance\n");
2979 static inline void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
2981 int port = BP_PORT(bp);
2985 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
2986 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
2988 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
2990 val = REG_RD(bp, reg_offset);
2991 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
2992 REG_WR(bp, reg_offset, val);
2994 BNX2X_ERR("SPIO5 hw attention\n");
2996 /* Fan failure attention */
2997 bnx2x_hw_reset_phy(&bp->link_params);
2998 bnx2x_fan_failure(bp);
3001 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
3002 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
3003 bnx2x_acquire_phy_lock(bp);
3004 bnx2x_handle_module_detect_int(&bp->link_params);
3005 bnx2x_release_phy_lock(bp);
3008 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3010 val = REG_RD(bp, reg_offset);
3011 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3012 REG_WR(bp, reg_offset, val);
3014 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3015 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3020 static inline void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3024 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3026 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3027 BNX2X_ERR("DB hw attention 0x%x\n", val);
3028 /* DORQ discard attention */
3030 BNX2X_ERR("FATAL error from DORQ\n");
3033 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3035 int port = BP_PORT(bp);
3038 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3039 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3041 val = REG_RD(bp, reg_offset);
3042 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3043 REG_WR(bp, reg_offset, val);
3045 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3046 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3051 static inline void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3055 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3057 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3058 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3059 /* CFC error attention */
3061 BNX2X_ERR("FATAL error from CFC\n");
3064 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3066 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3067 BNX2X_ERR("PXP hw attention 0x%x\n", val);
3068 /* RQ_USDMDP_FIFO_OVERFLOW */
3070 BNX2X_ERR("FATAL error from PXP\n");
3071 if (CHIP_IS_E2(bp)) {
3072 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3073 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3077 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3079 int port = BP_PORT(bp);
3082 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3083 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3085 val = REG_RD(bp, reg_offset);
3086 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3087 REG_WR(bp, reg_offset, val);
3089 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3090 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3095 static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3099 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3101 if (attn & BNX2X_PMF_LINK_ASSERT) {
3102 int func = BP_FUNC(bp);
3104 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3105 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3106 func_mf_config[BP_ABS_FUNC(bp)].config);
3108 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3109 if (val & DRV_STATUS_DCC_EVENT_MASK)
3111 (val & DRV_STATUS_DCC_EVENT_MASK));
3113 if (val & DRV_STATUS_SET_MF_BW)
3114 bnx2x_set_mf_bw(bp);
3116 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3117 bnx2x_pmf_update(bp);
3119 /* Always call it here: bnx2x_link_report() will
3120 * prevent the link indication duplication.
3122 bnx2x__link_status_update(bp);
3125 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3126 bp->dcbx_enabled > 0)
3127 /* start dcbx state machine */
3128 bnx2x_dcbx_set_params(bp,
3129 BNX2X_DCBX_STATE_NEG_RECEIVED);
3130 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3132 BNX2X_ERR("MC assert!\n");
3133 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3134 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3135 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3136 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3139 } else if (attn & BNX2X_MCP_ASSERT) {
3141 BNX2X_ERR("MCP assert!\n");
3142 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3146 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3149 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3150 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3151 if (attn & BNX2X_GRC_TIMEOUT) {
3152 val = CHIP_IS_E1(bp) ? 0 :
3153 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3154 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3156 if (attn & BNX2X_GRC_RSV) {
3157 val = CHIP_IS_E1(bp) ? 0 :
3158 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3159 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3161 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3165 #define BNX2X_MISC_GEN_REG MISC_REG_GENERIC_POR_1
3166 #define LOAD_COUNTER_BITS 16 /* Number of bits for load counter */
3167 #define LOAD_COUNTER_MASK (((u32)0x1 << LOAD_COUNTER_BITS) - 1)
3168 #define RESET_DONE_FLAG_MASK (~LOAD_COUNTER_MASK)
3169 #define RESET_DONE_FLAG_SHIFT LOAD_COUNTER_BITS
3172 * should be run under rtnl lock
3174 static inline void bnx2x_set_reset_done(struct bnx2x *bp)
3176 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3177 val &= ~(1 << RESET_DONE_FLAG_SHIFT);
3178 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3184 * should be run under rtnl lock
3186 static inline void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3188 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3190 REG_WR(bp, BNX2X_MISC_GEN_REG, val);
3196 * should be run under rtnl lock
3198 bool bnx2x_reset_is_done(struct bnx2x *bp)
3200 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3201 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3202 return (val & RESET_DONE_FLAG_MASK) ? false : true;
3206 * should be run under rtnl lock
3208 inline void bnx2x_inc_load_cnt(struct bnx2x *bp)
3210 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3212 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3214 val1 = ((val & LOAD_COUNTER_MASK) + 1) & LOAD_COUNTER_MASK;
3215 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3221 * should be run under rtnl lock
3223 u32 bnx2x_dec_load_cnt(struct bnx2x *bp)
3225 u32 val1, val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3227 DP(NETIF_MSG_HW, "Old GEN_REG_VAL=0x%08x\n", val);
3229 val1 = ((val & LOAD_COUNTER_MASK) - 1) & LOAD_COUNTER_MASK;
3230 REG_WR(bp, BNX2X_MISC_GEN_REG, (val & RESET_DONE_FLAG_MASK) | val1);
3238 * should be run under rtnl lock
3240 static inline u32 bnx2x_get_load_cnt(struct bnx2x *bp)
3242 return REG_RD(bp, BNX2X_MISC_GEN_REG) & LOAD_COUNTER_MASK;
3245 static inline void bnx2x_clear_load_cnt(struct bnx2x *bp)
3247 u32 val = REG_RD(bp, BNX2X_MISC_GEN_REG);
3248 REG_WR(bp, BNX2X_MISC_GEN_REG, val & (~LOAD_COUNTER_MASK));
3251 static inline void _print_next_block(int idx, const char *blk)
3258 static inline int bnx2x_print_blocks_with_parity0(u32 sig, int par_num)
3262 for (i = 0; sig; i++) {
3263 cur_bit = ((u32)0x1 << i);
3264 if (sig & cur_bit) {
3266 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
3267 _print_next_block(par_num++, "BRB");
3269 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
3270 _print_next_block(par_num++, "PARSER");
3272 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
3273 _print_next_block(par_num++, "TSDM");
3275 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
3276 _print_next_block(par_num++, "SEARCHER");
3278 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
3279 _print_next_block(par_num++, "TSEMI");
3291 static inline int bnx2x_print_blocks_with_parity1(u32 sig, int par_num)
3295 for (i = 0; sig; i++) {
3296 cur_bit = ((u32)0x1 << i);
3297 if (sig & cur_bit) {
3299 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
3300 _print_next_block(par_num++, "PBCLIENT");
3302 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
3303 _print_next_block(par_num++, "QM");
3305 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
3306 _print_next_block(par_num++, "XSDM");
3308 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
3309 _print_next_block(par_num++, "XSEMI");
3311 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
3312 _print_next_block(par_num++, "DOORBELLQ");
3314 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
3315 _print_next_block(par_num++, "VAUX PCI CORE");
3317 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
3318 _print_next_block(par_num++, "DEBUG");
3320 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
3321 _print_next_block(par_num++, "USDM");
3323 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
3324 _print_next_block(par_num++, "USEMI");
3326 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
3327 _print_next_block(par_num++, "UPB");
3329 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
3330 _print_next_block(par_num++, "CSDM");
3342 static inline int bnx2x_print_blocks_with_parity2(u32 sig, int par_num)
3346 for (i = 0; sig; i++) {
3347 cur_bit = ((u32)0x1 << i);
3348 if (sig & cur_bit) {
3350 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
3351 _print_next_block(par_num++, "CSEMI");
3353 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
3354 _print_next_block(par_num++, "PXP");
3356 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
3357 _print_next_block(par_num++,
3358 "PXPPCICLOCKCLIENT");
3360 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
3361 _print_next_block(par_num++, "CFC");
3363 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
3364 _print_next_block(par_num++, "CDU");
3366 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
3367 _print_next_block(par_num++, "IGU");
3369 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
3370 _print_next_block(par_num++, "MISC");
3382 static inline int bnx2x_print_blocks_with_parity3(u32 sig, int par_num)
3386 for (i = 0; sig; i++) {
3387 cur_bit = ((u32)0x1 << i);
3388 if (sig & cur_bit) {
3390 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
3391 _print_next_block(par_num++, "MCP ROM");
3393 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
3394 _print_next_block(par_num++, "MCP UMP RX");
3396 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
3397 _print_next_block(par_num++, "MCP UMP TX");
3399 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
3400 _print_next_block(par_num++, "MCP SCPAD");
3412 static inline bool bnx2x_parity_attn(struct bnx2x *bp, u32 sig0, u32 sig1,
3415 if ((sig0 & HW_PRTY_ASSERT_SET_0) || (sig1 & HW_PRTY_ASSERT_SET_1) ||
3416 (sig2 & HW_PRTY_ASSERT_SET_2) || (sig3 & HW_PRTY_ASSERT_SET_3)) {
3418 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention: "
3419 "[0]:0x%08x [1]:0x%08x "
3420 "[2]:0x%08x [3]:0x%08x\n",
3421 sig0 & HW_PRTY_ASSERT_SET_0,
3422 sig1 & HW_PRTY_ASSERT_SET_1,
3423 sig2 & HW_PRTY_ASSERT_SET_2,
3424 sig3 & HW_PRTY_ASSERT_SET_3);
3425 printk(KERN_ERR"%s: Parity errors detected in blocks: ",
3427 par_num = bnx2x_print_blocks_with_parity0(
3428 sig0 & HW_PRTY_ASSERT_SET_0, par_num);
3429 par_num = bnx2x_print_blocks_with_parity1(
3430 sig1 & HW_PRTY_ASSERT_SET_1, par_num);
3431 par_num = bnx2x_print_blocks_with_parity2(
3432 sig2 & HW_PRTY_ASSERT_SET_2, par_num);
3433 par_num = bnx2x_print_blocks_with_parity3(
3434 sig3 & HW_PRTY_ASSERT_SET_3, par_num);
3441 bool bnx2x_chk_parity_attn(struct bnx2x *bp)
3443 struct attn_route attn;
3444 int port = BP_PORT(bp);
3446 attn.sig[0] = REG_RD(bp,
3447 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
3449 attn.sig[1] = REG_RD(bp,
3450 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
3452 attn.sig[2] = REG_RD(bp,
3453 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
3455 attn.sig[3] = REG_RD(bp,
3456 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
3459 return bnx2x_parity_attn(bp, attn.sig[0], attn.sig[1], attn.sig[2],
3464 static inline void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
3467 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
3469 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
3470 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
3471 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
3472 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3474 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
3475 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3476 "INCORRECT_RCV_BEHAVIOR\n");
3477 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
3478 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3479 "WAS_ERROR_ATTN\n");
3480 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
3481 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3482 "VF_LENGTH_VIOLATION_ATTN\n");
3484 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
3485 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3486 "VF_GRC_SPACE_VIOLATION_ATTN\n");
3488 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
3489 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3490 "VF_MSIX_BAR_VIOLATION_ATTN\n");
3491 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
3492 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3493 "TCPL_ERROR_ATTN\n");
3494 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
3495 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3496 "TCPL_IN_TWO_RCBS_ATTN\n");
3497 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
3498 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_"
3499 "CSSNOOP_FIFO_OVERFLOW\n");
3501 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
3502 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
3503 BNX2X_ERR("ATC hw attention 0x%x\n", val);
3504 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
3505 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
3506 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
3507 BNX2X_ERR("ATC_ATC_INT_STS_REG"
3508 "_ATC_TCPL_TO_NOT_PEND\n");
3509 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
3510 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3511 "ATC_GPA_MULTIPLE_HITS\n");
3512 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
3513 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3514 "ATC_RCPL_TO_EMPTY_CNT\n");
3515 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
3516 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
3517 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
3518 BNX2X_ERR("ATC_ATC_INT_STS_REG_"
3519 "ATC_IREQ_LESS_THAN_STU\n");
3522 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3523 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
3524 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
3525 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
3526 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
3531 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
3533 struct attn_route attn, *group_mask;
3534 int port = BP_PORT(bp);
3540 /* need to take HW lock because MCP or other port might also
3541 try to handle this event */
3542 bnx2x_acquire_alr(bp);
3544 if (CHIP_PARITY_ENABLED(bp) && bnx2x_chk_parity_attn(bp)) {
3545 bp->recovery_state = BNX2X_RECOVERY_INIT;
3546 bnx2x_set_reset_in_progress(bp);
3547 schedule_delayed_work(&bp->reset_task, 0);
3548 /* Disable HW interrupts */
3549 bnx2x_int_disable(bp);
3550 bnx2x_release_alr(bp);
3551 /* In case of parity errors don't handle attentions so that
3552 * other function would "see" parity errors.
3557 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
3558 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
3559 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
3560 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
3563 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
3567 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
3568 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
3570 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
3571 if (deasserted & (1 << index)) {
3572 group_mask = &bp->attn_group[index];
3574 DP(NETIF_MSG_HW, "group[%d]: %08x %08x "
3577 group_mask->sig[0], group_mask->sig[1],
3578 group_mask->sig[2], group_mask->sig[3],
3579 group_mask->sig[4]);
3581 bnx2x_attn_int_deasserted4(bp,
3582 attn.sig[4] & group_mask->sig[4]);
3583 bnx2x_attn_int_deasserted3(bp,
3584 attn.sig[3] & group_mask->sig[3]);
3585 bnx2x_attn_int_deasserted1(bp,
3586 attn.sig[1] & group_mask->sig[1]);
3587 bnx2x_attn_int_deasserted2(bp,
3588 attn.sig[2] & group_mask->sig[2]);
3589 bnx2x_attn_int_deasserted0(bp,
3590 attn.sig[0] & group_mask->sig[0]);
3594 bnx2x_release_alr(bp);
3596 if (bp->common.int_block == INT_BLOCK_HC)
3597 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3598 COMMAND_REG_ATTN_BITS_CLR);
3600 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
3603 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
3604 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3605 REG_WR(bp, reg_addr, val);
3607 if (~bp->attn_state & deasserted)
3608 BNX2X_ERR("IGU ERROR\n");
3610 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3611 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3613 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3614 aeu_mask = REG_RD(bp, reg_addr);
3616 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
3617 aeu_mask, deasserted);
3618 aeu_mask |= (deasserted & 0x3ff);
3619 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3621 REG_WR(bp, reg_addr, aeu_mask);
3622 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3624 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3625 bp->attn_state &= ~deasserted;
3626 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3629 static void bnx2x_attn_int(struct bnx2x *bp)
3631 /* read local copy of bits */
3632 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
3634 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
3636 u32 attn_state = bp->attn_state;
3638 /* look for changed bits */
3639 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
3640 u32 deasserted = ~attn_bits & attn_ack & attn_state;
3643 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
3644 attn_bits, attn_ack, asserted, deasserted);
3646 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
3647 BNX2X_ERR("BAD attention state\n");
3649 /* handle bits that were raised */
3651 bnx2x_attn_int_asserted(bp, asserted);
3654 bnx2x_attn_int_deasserted(bp, deasserted);
3657 static inline void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
3659 /* No memory barriers */
3660 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
3661 mmiowb(); /* keep prod updates ordered */
3665 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
3666 union event_ring_elem *elem)
3668 if (!bp->cnic_eth_dev.starting_cid ||
3669 (cid < bp->cnic_eth_dev.starting_cid &&
3670 cid != bp->cnic_eth_dev.iscsi_l2_cid))
3673 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
3675 if (unlikely(elem->message.data.cfc_del_event.error)) {
3676 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
3678 bnx2x_panic_dump(bp);
3680 bnx2x_cnic_cfc_comp(bp, cid);
3685 static void bnx2x_eq_int(struct bnx2x *bp)
3687 u16 hw_cons, sw_cons, sw_prod;
3688 union event_ring_elem *elem;
3693 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
3695 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
3696 * when we get the the next-page we nned to adjust so the loop
3697 * condition below will be met. The next element is the size of a
3698 * regular element and hence incrementing by 1
3700 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
3703 /* This function may never run in parallel with itself for a
3704 * specific bp, thus there is no need in "paired" read memory
3707 sw_cons = bp->eq_cons;
3708 sw_prod = bp->eq_prod;
3710 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->cq_spq_left %u\n",
3711 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
3713 for (; sw_cons != hw_cons;
3714 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
3717 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
3719 cid = SW_CID(elem->message.data.cfc_del_event.cid);
3720 opcode = elem->message.opcode;
3723 /* handle eq element */
3725 case EVENT_RING_OPCODE_STAT_QUERY:
3726 DP(NETIF_MSG_TIMER, "got statistics comp event\n");
3727 /* nothing to do with stats comp */
3730 case EVENT_RING_OPCODE_CFC_DEL:
3731 /* handle according to cid range */
3733 * we may want to verify here that the bp state is
3736 DP(NETIF_MSG_IFDOWN,
3737 "got delete ramrod for MULTI[%d]\n", cid);
3739 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
3741 if (cid == BNX2X_FCOE_ETH_CID)
3742 bnx2x_fcoe(bp, state) = BNX2X_FP_STATE_CLOSED;
3745 bnx2x_fp(bp, cid, state) =
3746 BNX2X_FP_STATE_CLOSED;
3750 case EVENT_RING_OPCODE_STOP_TRAFFIC:
3751 DP(NETIF_MSG_IFUP, "got STOP TRAFFIC\n");
3752 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
3754 case EVENT_RING_OPCODE_START_TRAFFIC:
3755 DP(NETIF_MSG_IFUP, "got START TRAFFIC\n");
3756 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
3760 switch (opcode | bp->state) {
3761 case (EVENT_RING_OPCODE_FUNCTION_START |
3762 BNX2X_STATE_OPENING_WAIT4_PORT):
3763 DP(NETIF_MSG_IFUP, "got setup ramrod\n");
3764 bp->state = BNX2X_STATE_FUNC_STARTED;
3767 case (EVENT_RING_OPCODE_FUNCTION_STOP |
3768 BNX2X_STATE_CLOSING_WAIT4_HALT):
3769 DP(NETIF_MSG_IFDOWN, "got halt ramrod\n");
3770 bp->state = BNX2X_STATE_CLOSING_WAIT4_UNLOAD;
3773 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
3774 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
3775 DP(NETIF_MSG_IFUP, "got set mac ramrod\n");
3776 if (elem->message.data.set_mac_event.echo)
3777 bp->set_mac_pending = 0;
3780 case (EVENT_RING_OPCODE_SET_MAC |
3781 BNX2X_STATE_CLOSING_WAIT4_HALT):
3782 DP(NETIF_MSG_IFDOWN, "got (un)set mac ramrod\n");
3783 if (elem->message.data.set_mac_event.echo)
3784 bp->set_mac_pending = 0;
3787 /* unknown event log error and continue */
3788 BNX2X_ERR("Unknown EQ event %d\n",
3789 elem->message.opcode);
3795 smp_mb__before_atomic_inc();
3796 atomic_add(spqe_cnt, &bp->eq_spq_left);
3798 bp->eq_cons = sw_cons;
3799 bp->eq_prod = sw_prod;
3800 /* Make sure that above mem writes were issued towards the memory */
3803 /* update producer */
3804 bnx2x_update_eq_prod(bp, bp->eq_prod);
3807 static void bnx2x_sp_task(struct work_struct *work)
3809 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
3812 /* Return here if interrupt is disabled */
3813 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3814 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3818 status = bnx2x_update_dsb_idx(bp);
3819 /* if (status == 0) */
3820 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
3822 DP(NETIF_MSG_INTR, "got a slowpath interrupt (status 0x%x)\n", status);
3825 if (status & BNX2X_DEF_SB_ATT_IDX) {
3827 status &= ~BNX2X_DEF_SB_ATT_IDX;
3830 /* SP events: STAT_QUERY and others */
3831 if (status & BNX2X_DEF_SB_IDX) {
3833 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
3835 if ((!NO_FCOE(bp)) &&
3836 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp)))
3837 napi_schedule(&bnx2x_fcoe(bp, napi));
3839 /* Handle EQ completions */
3842 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
3843 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
3845 status &= ~BNX2X_DEF_SB_IDX;
3848 if (unlikely(status))
3849 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
3852 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
3853 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
3856 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
3858 struct net_device *dev = dev_instance;
3859 struct bnx2x *bp = netdev_priv(dev);
3861 /* Return here if interrupt is disabled */
3862 if (unlikely(atomic_read(&bp->intr_sem) != 0)) {
3863 DP(NETIF_MSG_INTR, "called but intr_sem not 0, returning\n");
3867 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
3868 IGU_INT_DISABLE, 0);
3870 #ifdef BNX2X_STOP_ON_ERROR
3871 if (unlikely(bp->panic))
3877 struct cnic_ops *c_ops;
3880 c_ops = rcu_dereference(bp->cnic_ops);
3882 c_ops->cnic_handler(bp->cnic_data, NULL);
3886 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
3891 /* end of slow path */
3893 static void bnx2x_timer(unsigned long data)
3895 struct bnx2x *bp = (struct bnx2x *) data;
3897 if (!netif_running(bp->dev))
3900 if (atomic_read(&bp->intr_sem) != 0)
3904 struct bnx2x_fastpath *fp = &bp->fp[0];
3907 bnx2x_rx_int(fp, 1000);
3910 if (!BP_NOMCP(bp)) {
3911 int mb_idx = BP_FW_MB_IDX(bp);
3915 ++bp->fw_drv_pulse_wr_seq;
3916 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
3917 /* TBD - add SYSTEM_TIME */
3918 drv_pulse = bp->fw_drv_pulse_wr_seq;
3919 SHMEM_WR(bp, func_mb[mb_idx].drv_pulse_mb, drv_pulse);
3921 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
3922 MCP_PULSE_SEQ_MASK);
3923 /* The delta between driver pulse and mcp response
3924 * should be 1 (before mcp response) or 0 (after mcp response)
3926 if ((drv_pulse != mcp_pulse) &&
3927 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
3928 /* someone lost a heartbeat... */
3929 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
3930 drv_pulse, mcp_pulse);
3934 if (bp->state == BNX2X_STATE_OPEN)
3935 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
3938 mod_timer(&bp->timer, jiffies + bp->current_interval);
3941 /* end of Statistics */
3946 * nic init service functions
3949 static inline void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
3952 if (!(len%4) && !(addr%4))
3953 for (i = 0; i < len; i += 4)
3954 REG_WR(bp, addr + i, fill);
3956 for (i = 0; i < len; i++)
3957 REG_WR8(bp, addr + i, fill);
3961 /* helper: writes FP SP data to FW - data_size in dwords */
3962 static inline void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
3968 for (index = 0; index < data_size; index++)
3969 REG_WR(bp, BAR_CSTRORM_INTMEM +
3970 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
3972 *(sb_data_p + index));
3975 static inline void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
3979 struct hc_status_block_data_e2 sb_data_e2;
3980 struct hc_status_block_data_e1x sb_data_e1x;
3982 /* disable the function first */
3983 if (CHIP_IS_E2(bp)) {
3984 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
3985 sb_data_e2.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3986 sb_data_e2.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3987 sb_data_e2.common.p_func.vf_valid = false;
3988 sb_data_p = (u32 *)&sb_data_e2;
3989 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
3991 memset(&sb_data_e1x, 0,
3992 sizeof(struct hc_status_block_data_e1x));
3993 sb_data_e1x.common.p_func.pf_id = HC_FUNCTION_DISABLED;
3994 sb_data_e1x.common.p_func.vf_id = HC_FUNCTION_DISABLED;
3995 sb_data_e1x.common.p_func.vf_valid = false;
3996 sb_data_p = (u32 *)&sb_data_e1x;
3997 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
3999 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4001 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4002 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
4003 CSTORM_STATUS_BLOCK_SIZE);
4004 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4005 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
4006 CSTORM_SYNC_BLOCK_SIZE);
4009 /* helper: writes SP SB data to FW */
4010 static inline void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
4011 struct hc_sp_status_block_data *sp_sb_data)
4013 int func = BP_FUNC(bp);
4015 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
4016 REG_WR(bp, BAR_CSTRORM_INTMEM +
4017 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
4019 *((u32 *)sp_sb_data + i));
4022 static inline void bnx2x_zero_sp_sb(struct bnx2x *bp)
4024 int func = BP_FUNC(bp);
4025 struct hc_sp_status_block_data sp_sb_data;
4026 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4028 sp_sb_data.p_func.pf_id = HC_FUNCTION_DISABLED;
4029 sp_sb_data.p_func.vf_id = HC_FUNCTION_DISABLED;
4030 sp_sb_data.p_func.vf_valid = false;
4032 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4034 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4035 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
4036 CSTORM_SP_STATUS_BLOCK_SIZE);
4037 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
4038 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
4039 CSTORM_SP_SYNC_BLOCK_SIZE);
4045 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
4046 int igu_sb_id, int igu_seg_id)
4048 hc_sm->igu_sb_id = igu_sb_id;
4049 hc_sm->igu_seg_id = igu_seg_id;
4050 hc_sm->timer_value = 0xFF;
4051 hc_sm->time_to_expire = 0xFFFFFFFF;
4054 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
4055 u8 vf_valid, int fw_sb_id, int igu_sb_id)
4059 struct hc_status_block_data_e2 sb_data_e2;
4060 struct hc_status_block_data_e1x sb_data_e1x;
4061 struct hc_status_block_sm *hc_sm_p;
4065 if (CHIP_INT_MODE_IS_BC(bp))
4066 igu_seg_id = HC_SEG_ACCESS_NORM;
4068 igu_seg_id = IGU_SEG_ACCESS_NORM;
4070 bnx2x_zero_fp_sb(bp, fw_sb_id);
4072 if (CHIP_IS_E2(bp)) {
4073 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
4074 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
4075 sb_data_e2.common.p_func.vf_id = vfid;
4076 sb_data_e2.common.p_func.vf_valid = vf_valid;
4077 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
4078 sb_data_e2.common.same_igu_sb_1b = true;
4079 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
4080 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
4081 hc_sm_p = sb_data_e2.common.state_machine;
4082 sb_data_p = (u32 *)&sb_data_e2;
4083 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
4085 memset(&sb_data_e1x, 0,
4086 sizeof(struct hc_status_block_data_e1x));
4087 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
4088 sb_data_e1x.common.p_func.vf_id = 0xff;
4089 sb_data_e1x.common.p_func.vf_valid = false;
4090 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
4091 sb_data_e1x.common.same_igu_sb_1b = true;
4092 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
4093 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
4094 hc_sm_p = sb_data_e1x.common.state_machine;
4095 sb_data_p = (u32 *)&sb_data_e1x;
4096 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
4099 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
4100 igu_sb_id, igu_seg_id);
4101 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
4102 igu_sb_id, igu_seg_id);
4104 DP(NETIF_MSG_HW, "Init FW SB %d\n", fw_sb_id);
4106 /* write indecies to HW */
4107 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
4110 static void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u16 fw_sb_id,
4111 u8 sb_index, u8 disable, u16 usec)
4113 int port = BP_PORT(bp);
4114 u8 ticks = usec / BNX2X_BTR;
4116 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4118 disable = disable ? 1 : (usec ? 0 : 1);
4119 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4122 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u16 fw_sb_id,
4123 u16 tx_usec, u16 rx_usec)
4125 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, U_SB_ETH_RX_CQ_INDEX,
4127 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, C_SB_ETH_TX_CQ_INDEX,
4131 static void bnx2x_init_def_sb(struct bnx2x *bp)
4133 struct host_sp_status_block *def_sb = bp->def_status_blk;
4134 dma_addr_t mapping = bp->def_status_blk_mapping;
4135 int igu_sp_sb_index;
4137 int port = BP_PORT(bp);
4138 int func = BP_FUNC(bp);
4142 struct hc_sp_status_block_data sp_sb_data;
4143 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
4145 if (CHIP_INT_MODE_IS_BC(bp)) {
4146 igu_sp_sb_index = DEF_SB_IGU_ID;
4147 igu_seg_id = HC_SEG_ACCESS_DEF;
4149 igu_sp_sb_index = bp->igu_dsb_id;
4150 igu_seg_id = IGU_SEG_ACCESS_DEF;
4154 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4155 atten_status_block);
4156 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
4160 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4161 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4162 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4164 /* take care of sig[0]..sig[4] */
4165 for (sindex = 0; sindex < 4; sindex++)
4166 bp->attn_group[index].sig[sindex] =
4167 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
4171 * enable5 is separate from the rest of the registers,
4172 * and therefore the address skip is 4
4173 * and not 16 between the different groups
4175 bp->attn_group[index].sig[4] = REG_RD(bp,
4176 reg_offset + 0x10 + 0x4*index);
4178 bp->attn_group[index].sig[4] = 0;
4181 if (bp->common.int_block == INT_BLOCK_HC) {
4182 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
4183 HC_REG_ATTN_MSG0_ADDR_L);
4185 REG_WR(bp, reg_offset, U64_LO(section));
4186 REG_WR(bp, reg_offset + 4, U64_HI(section));
4187 } else if (CHIP_IS_E2(bp)) {
4188 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
4189 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
4192 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
4195 bnx2x_zero_sp_sb(bp);
4197 sp_sb_data.host_sb_addr.lo = U64_LO(section);
4198 sp_sb_data.host_sb_addr.hi = U64_HI(section);
4199 sp_sb_data.igu_sb_id = igu_sp_sb_index;
4200 sp_sb_data.igu_seg_id = igu_seg_id;
4201 sp_sb_data.p_func.pf_id = func;
4202 sp_sb_data.p_func.vnic_id = BP_VN(bp);
4203 sp_sb_data.p_func.vf_id = 0xff;
4205 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
4207 bp->stats_pending = 0;
4208 bp->set_mac_pending = 0;
4210 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
4213 void bnx2x_update_coalesce(struct bnx2x *bp)
4217 for_each_eth_queue(bp, i)
4218 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
4219 bp->tx_ticks, bp->rx_ticks);
4222 static void bnx2x_init_sp_ring(struct bnx2x *bp)
4224 spin_lock_init(&bp->spq_lock);
4225 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
4227 bp->spq_prod_idx = 0;
4228 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
4229 bp->spq_prod_bd = bp->spq;
4230 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
4233 static void bnx2x_init_eq_ring(struct bnx2x *bp)
4236 for (i = 1; i <= NUM_EQ_PAGES; i++) {
4237 union event_ring_elem *elem =
4238 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
4240 elem->next_page.addr.hi =
4241 cpu_to_le32(U64_HI(bp->eq_mapping +
4242 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
4243 elem->next_page.addr.lo =
4244 cpu_to_le32(U64_LO(bp->eq_mapping +
4245 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
4248 bp->eq_prod = NUM_EQ_DESC;
4249 bp->eq_cons_sb = BNX2X_EQ_INDEX;
4250 /* we want a warning message before it gets rought... */
4251 atomic_set(&bp->eq_spq_left,
4252 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
4255 void bnx2x_push_indir_table(struct bnx2x *bp)
4257 int func = BP_FUNC(bp);
4260 if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
4263 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4264 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4265 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
4266 bp->fp->cl_id + bp->rx_indir_table[i]);
4269 static void bnx2x_init_ind_table(struct bnx2x *bp)
4273 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
4274 bp->rx_indir_table[i] = i % BNX2X_NUM_ETH_QUEUES(bp);
4276 bnx2x_push_indir_table(bp);
4279 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
4281 int mode = bp->rx_mode;
4282 int port = BP_PORT(bp);
4284 u32 def_q_filters = 0;
4286 /* All but management unicast packets should pass to the host as well */
4288 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
4289 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
4290 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
4291 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
4294 case BNX2X_RX_MODE_NONE: /* no Rx */
4295 def_q_filters = BNX2X_ACCEPT_NONE;
4298 cl_id = bnx2x_fcoe(bp, cl_id);
4299 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4304 case BNX2X_RX_MODE_NORMAL:
4305 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4306 BNX2X_ACCEPT_MULTICAST;
4309 cl_id = bnx2x_fcoe(bp, cl_id);
4310 bnx2x_rxq_set_mac_filters(bp, cl_id,
4311 BNX2X_ACCEPT_UNICAST |
4312 BNX2X_ACCEPT_MULTICAST);
4317 case BNX2X_RX_MODE_ALLMULTI:
4318 def_q_filters |= BNX2X_ACCEPT_UNICAST | BNX2X_ACCEPT_BROADCAST |
4319 BNX2X_ACCEPT_ALL_MULTICAST;
4322 * Prevent duplication of multicast packets by configuring FCoE
4323 * L2 Client to receive only matched unicast frames.
4326 cl_id = bnx2x_fcoe(bp, cl_id);
4327 bnx2x_rxq_set_mac_filters(bp, cl_id,
4328 BNX2X_ACCEPT_UNICAST);
4333 case BNX2X_RX_MODE_PROMISC:
4334 def_q_filters |= BNX2X_PROMISCUOUS_MODE;
4337 * Prevent packets duplication by configuring DROP_ALL for FCoE
4341 cl_id = bnx2x_fcoe(bp, cl_id);
4342 bnx2x_rxq_set_mac_filters(bp, cl_id, BNX2X_ACCEPT_NONE);
4345 /* pass management unicast packets as well */
4346 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
4350 BNX2X_ERR("BAD rx mode (%d)\n", mode);
4354 cl_id = BP_L_ID(bp);
4355 bnx2x_rxq_set_mac_filters(bp, cl_id, def_q_filters);
4358 (port ? NIG_REG_LLH1_BRB1_DRV_MASK :
4359 NIG_REG_LLH0_BRB1_DRV_MASK), llh_mask);
4361 DP(NETIF_MSG_IFUP, "rx mode %d\n"
4362 "drop_ucast 0x%x\ndrop_mcast 0x%x\ndrop_bcast 0x%x\n"
4363 "accp_ucast 0x%x\naccp_mcast 0x%x\naccp_bcast 0x%x\n"
4364 "unmatched_ucast 0x%x\n", mode,
4365 bp->mac_filters.ucast_drop_all,
4366 bp->mac_filters.mcast_drop_all,
4367 bp->mac_filters.bcast_drop_all,
4368 bp->mac_filters.ucast_accept_all,
4369 bp->mac_filters.mcast_accept_all,
4370 bp->mac_filters.bcast_accept_all,
4371 bp->mac_filters.unmatched_unicast
4374 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
4377 static void bnx2x_init_internal_common(struct bnx2x *bp)
4381 if (!CHIP_IS_E1(bp)) {
4383 /* xstorm needs to know whether to add ovlan to packets or not,
4384 * in switch-independent we'll write 0 to here... */
4385 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
4387 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
4389 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
4391 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
4397 * In switch independent mode, the TSTORM needs to accept
4398 * packets that failed classification, since approximate match
4399 * mac addresses aren't written to NIG LLH
4401 REG_WR8(bp, BAR_TSTRORM_INTMEM +
4402 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
4404 /* Zero this manually as its initialization is
4405 currently missing in the initTool */
4406 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
4407 REG_WR(bp, BAR_USTRORM_INTMEM +
4408 USTORM_AGG_DATA_OFFSET + i * 4, 0);
4409 if (CHIP_IS_E2(bp)) {
4410 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
4411 CHIP_INT_MODE_IS_BC(bp) ?
4412 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
4416 static void bnx2x_init_internal_port(struct bnx2x *bp)
4419 bnx2x_dcb_init_intmem_pfc(bp);
4422 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
4424 switch (load_code) {
4425 case FW_MSG_CODE_DRV_LOAD_COMMON:
4426 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
4427 bnx2x_init_internal_common(bp);
4430 case FW_MSG_CODE_DRV_LOAD_PORT:
4431 bnx2x_init_internal_port(bp);
4434 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
4435 /* internal memory per function is
4436 initialized inside bnx2x_pf_init */
4440 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
4445 static void bnx2x_init_fp_sb(struct bnx2x *bp, int fp_idx)
4447 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
4449 fp->state = BNX2X_FP_STATE_CLOSED;
4452 fp->cl_id = BP_L_ID(bp) + fp_idx;
4453 fp->fw_sb_id = bp->base_fw_ndsb + fp->cl_id + CNIC_CONTEXT_USE;
4454 fp->igu_sb_id = bp->igu_base_sb + fp_idx + CNIC_CONTEXT_USE;
4455 /* qZone id equals to FW (per path) client id */
4456 fp->cl_qzone_id = fp->cl_id +
4457 BP_PORT(bp)*(CHIP_IS_E2(bp) ? ETH_MAX_RX_CLIENTS_E2 :
4458 ETH_MAX_RX_CLIENTS_E1H);
4460 fp->ustorm_rx_prods_offset = CHIP_IS_E2(bp) ?
4461 USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id) :
4462 USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
4463 /* Setup SB indicies */
4464 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
4465 fp->tx_cons_sb = BNX2X_TX_SB_INDEX;
4467 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) "
4468 "cl_id %d fw_sb %d igu_sb %d\n",
4469 fp_idx, bp, fp->status_blk.e1x_sb, fp->cl_id, fp->fw_sb_id,
4471 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
4472 fp->fw_sb_id, fp->igu_sb_id);
4474 bnx2x_update_fpsb_idx(fp);
4477 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
4481 for_each_eth_queue(bp, i)
4482 bnx2x_init_fp_sb(bp, i);
4485 bnx2x_init_fcoe_fp(bp);
4487 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
4488 BNX2X_VF_ID_INVALID, false,
4489 CNIC_SB_ID(bp), CNIC_IGU_SB_ID(bp));
4493 /* ensure status block indices were read */
4496 bnx2x_init_def_sb(bp);
4497 bnx2x_update_dsb_idx(bp);
4498 bnx2x_init_rx_rings(bp);
4499 bnx2x_init_tx_rings(bp);
4500 bnx2x_init_sp_ring(bp);
4501 bnx2x_init_eq_ring(bp);
4502 bnx2x_init_internal(bp, load_code);
4504 bnx2x_init_ind_table(bp);
4505 bnx2x_stats_init(bp);
4507 /* At this point, we are ready for interrupts */
4508 atomic_set(&bp->intr_sem, 0);
4510 /* flush all before enabling interrupts */
4514 bnx2x_int_enable(bp);
4516 /* Check for SPIO5 */
4517 bnx2x_attn_int_deasserted0(bp,
4518 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
4519 AEU_INPUTS_ATTN_BITS_SPIO5);
4522 /* end of nic init */
4525 * gzip service functions
4528 static int bnx2x_gunzip_init(struct bnx2x *bp)
4530 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
4531 &bp->gunzip_mapping, GFP_KERNEL);
4532 if (bp->gunzip_buf == NULL)
4535 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
4536 if (bp->strm == NULL)
4539 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(),
4541 if (bp->strm->workspace == NULL)
4551 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4552 bp->gunzip_mapping);
4553 bp->gunzip_buf = NULL;
4556 netdev_err(bp->dev, "Cannot allocate firmware buffer for"
4557 " un-compression\n");
4561 static void bnx2x_gunzip_end(struct bnx2x *bp)
4564 kfree(bp->strm->workspace);
4569 if (bp->gunzip_buf) {
4570 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
4571 bp->gunzip_mapping);
4572 bp->gunzip_buf = NULL;
4576 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
4580 /* check gzip header */
4581 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
4582 BNX2X_ERR("Bad gzip header\n");
4590 if (zbuf[3] & FNAME)
4591 while ((zbuf[n++] != 0) && (n < len));
4593 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
4594 bp->strm->avail_in = len - n;
4595 bp->strm->next_out = bp->gunzip_buf;
4596 bp->strm->avail_out = FW_BUF_SIZE;
4598 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
4602 rc = zlib_inflate(bp->strm, Z_FINISH);
4603 if ((rc != Z_OK) && (rc != Z_STREAM_END))
4604 netdev_err(bp->dev, "Firmware decompression error: %s\n",
4607 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
4608 if (bp->gunzip_outlen & 0x3)
4609 netdev_err(bp->dev, "Firmware decompression error:"
4610 " gunzip_outlen (%d) not aligned\n",
4612 bp->gunzip_outlen >>= 2;
4614 zlib_inflateEnd(bp->strm);
4616 if (rc == Z_STREAM_END)
4622 /* nic load/unload */
4625 * General service functions
4628 /* send a NIG loopback debug packet */
4629 static void bnx2x_lb_pckt(struct bnx2x *bp)
4633 /* Ethernet source and destination addresses */
4634 wb_write[0] = 0x55555555;
4635 wb_write[1] = 0x55555555;
4636 wb_write[2] = 0x20; /* SOP */
4637 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4639 /* NON-IP protocol */
4640 wb_write[0] = 0x09000000;
4641 wb_write[1] = 0x55555555;
4642 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
4643 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
4646 /* some of the internal memories
4647 * are not directly readable from the driver
4648 * to test them we send debug packets
4650 static int bnx2x_int_mem_test(struct bnx2x *bp)
4656 if (CHIP_REV_IS_FPGA(bp))
4658 else if (CHIP_REV_IS_EMUL(bp))
4663 /* Disable inputs of parser neighbor blocks */
4664 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4665 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4666 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4667 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4669 /* Write 0 to parser credits for CFC search request */
4670 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4672 /* send Ethernet packet */
4675 /* TODO do i reset NIG statistic? */
4676 /* Wait until NIG register shows 1 packet of size 0x10 */
4677 count = 1000 * factor;
4680 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4681 val = *bnx2x_sp(bp, wb_data[0]);
4689 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4693 /* Wait until PRS register shows 1 packet */
4694 count = 1000 * factor;
4696 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4704 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4708 /* Reset and init BRB, PRS */
4709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4711 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4713 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4714 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4716 DP(NETIF_MSG_HW, "part2\n");
4718 /* Disable inputs of parser neighbor blocks */
4719 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
4720 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
4721 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
4722 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
4724 /* Write 0 to parser credits for CFC search request */
4725 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
4727 /* send 10 Ethernet packets */
4728 for (i = 0; i < 10; i++)
4731 /* Wait until NIG register shows 10 + 1
4732 packets of size 11*0x10 = 0xb0 */
4733 count = 1000 * factor;
4736 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
4737 val = *bnx2x_sp(bp, wb_data[0]);
4745 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
4749 /* Wait until PRS register shows 2 packets */
4750 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4752 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4754 /* Write 1 to parser credits for CFC search request */
4755 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
4757 /* Wait until PRS register shows 3 packets */
4758 msleep(10 * factor);
4759 /* Wait until NIG register shows 1 packet of size 0x10 */
4760 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
4762 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
4764 /* clear NIG EOP FIFO */
4765 for (i = 0; i < 11; i++)
4766 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
4767 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
4769 BNX2X_ERR("clear of NIG failed\n");
4773 /* Reset and init BRB, PRS, NIG */
4774 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
4776 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
4778 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
4779 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
4782 REG_WR(bp, PRS_REG_NIC_MODE, 1);
4785 /* Enable inputs of parser neighbor blocks */
4786 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
4787 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
4788 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
4789 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
4791 DP(NETIF_MSG_HW, "done\n");
4796 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
4798 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
4800 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
4802 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
4803 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
4804 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
4806 * mask read length error interrupts in brb for parser
4807 * (parsing unit and 'checksum and crc' unit)
4808 * these errors are legal (PU reads fixed length and CAC can cause
4809 * read length error on truncated packets)
4811 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
4812 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
4813 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
4814 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
4815 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
4816 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
4817 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
4818 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
4819 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
4820 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
4821 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
4822 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
4823 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
4824 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
4825 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
4826 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
4827 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
4828 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
4829 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
4831 if (CHIP_REV_IS_FPGA(bp))
4832 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
4833 else if (CHIP_IS_E2(bp))
4834 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
4835 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
4836 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
4837 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
4838 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
4839 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
4841 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
4842 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
4843 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
4844 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
4845 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
4846 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0); */
4847 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
4848 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
4849 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
4850 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
4853 static void bnx2x_reset_common(struct bnx2x *bp)
4856 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
4858 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 0x1403);
4861 static void bnx2x_init_pxp(struct bnx2x *bp)
4864 int r_order, w_order;
4866 pci_read_config_word(bp->pdev,
4867 bp->pcie_cap + PCI_EXP_DEVCTL, &devctl);
4868 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
4869 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4871 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
4873 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
4877 bnx2x_init_pxp_arb(bp, r_order, w_order);
4880 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
4890 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
4891 SHARED_HW_CFG_FAN_FAILURE_MASK;
4893 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
4897 * The fan failure mechanism is usually related to the PHY type since
4898 * the power consumption of the board is affected by the PHY. Currently,
4899 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
4901 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
4902 for (port = PORT_0; port < PORT_MAX; port++) {
4904 bnx2x_fan_failure_det_req(
4906 bp->common.shmem_base,
4907 bp->common.shmem2_base,
4911 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
4913 if (is_required == 0)
4916 /* Fan failure is indicated by SPIO 5 */
4917 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
4918 MISC_REGISTERS_SPIO_INPUT_HI_Z);
4920 /* set to active low mode */
4921 val = REG_RD(bp, MISC_REG_SPIO_INT);
4922 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
4923 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
4924 REG_WR(bp, MISC_REG_SPIO_INT, val);
4926 /* enable interrupt to signal the IGU */
4927 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
4928 val |= (1 << MISC_REGISTERS_SPIO_5);
4929 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
4932 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
4938 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
4941 switch (BP_ABS_FUNC(bp)) {
4943 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
4946 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
4949 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
4952 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
4955 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
4958 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
4961 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
4964 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
4970 REG_WR(bp, offset, pretend_func_num);
4972 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
4975 static void bnx2x_pf_disable(struct bnx2x *bp)
4977 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
4978 val &= ~IGU_PF_CONF_FUNC_EN;
4980 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
4981 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
4982 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
4985 static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
4989 DP(BNX2X_MSG_MCP, "starting common init func %d\n", BP_ABS_FUNC(bp));
4991 bnx2x_reset_common(bp);
4992 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
4993 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
4995 bnx2x_init_block(bp, MISC_BLOCK, COMMON_STAGE);
4996 if (!CHIP_IS_E1(bp))
4997 REG_WR(bp, MISC_REG_E1HMF_MODE, IS_MF(bp));
4999 if (CHIP_IS_E2(bp)) {
5003 * 4-port mode or 2-port mode we need to turn of master-enable
5004 * for everyone, after that, turn it back on for self.
5005 * so, we disregard multi-function or not, and always disable
5006 * for all functions on the given path, this means 0,2,4,6 for
5007 * path 0 and 1,3,5,7 for path 1
5009 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX*2; fid += 2) {
5010 if (fid == BP_ABS_FUNC(bp)) {
5012 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
5017 bnx2x_pretend_func(bp, fid);
5018 /* clear pf enable */
5019 bnx2x_pf_disable(bp);
5020 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5024 bnx2x_init_block(bp, PXP_BLOCK, COMMON_STAGE);
5025 if (CHIP_IS_E1(bp)) {
5026 /* enable HW interrupt from PXP on USDM overflow
5027 bit 16 on INT_MASK_0 */
5028 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
5031 bnx2x_init_block(bp, PXP2_BLOCK, COMMON_STAGE);
5035 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
5036 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
5037 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
5038 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
5039 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
5040 /* make sure this value is 0 */
5041 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
5043 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
5044 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
5045 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
5046 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
5047 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
5050 bnx2x_ilt_init_page_size(bp, INITOP_SET);
5052 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
5053 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
5055 /* let the HW do it's magic ... */
5057 /* finish PXP init */
5058 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
5060 BNX2X_ERR("PXP2 CFG failed\n");
5063 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
5065 BNX2X_ERR("PXP2 RD_INIT failed\n");
5069 /* Timers bug workaround E2 only. We need to set the entire ILT to
5070 * have entries with value "0" and valid bit on.
5071 * This needs to be done by the first PF that is loaded in a path
5072 * (i.e. common phase)
5074 if (CHIP_IS_E2(bp)) {
5075 struct ilt_client_info ilt_cli;
5076 struct bnx2x_ilt ilt;
5077 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
5078 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
5080 /* initialize dummy TM client */
5082 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
5083 ilt_cli.client_num = ILT_CLIENT_TM;
5085 /* Step 1: set zeroes to all ilt page entries with valid bit on
5086 * Step 2: set the timers first/last ilt entry to point
5087 * to the entire range to prevent ILT range error for 3rd/4th
5088 * vnic (this code assumes existence of the vnic)
5090 * both steps performed by call to bnx2x_ilt_client_init_op()
5091 * with dummy TM client
5093 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
5094 * and his brother are split registers
5096 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
5097 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
5098 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
5100 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
5101 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
5102 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
5106 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
5107 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
5109 if (CHIP_IS_E2(bp)) {
5110 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
5111 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
5112 bnx2x_init_block(bp, PGLUE_B_BLOCK, COMMON_STAGE);
5114 bnx2x_init_block(bp, ATC_BLOCK, COMMON_STAGE);
5116 /* let the HW do it's magic ... */
5119 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
5120 } while (factor-- && (val != 1));
5123 BNX2X_ERR("ATC_INIT failed\n");
5128 bnx2x_init_block(bp, DMAE_BLOCK, COMMON_STAGE);
5130 /* clean the DMAE memory */
5132 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8);
5134 bnx2x_init_block(bp, TCM_BLOCK, COMMON_STAGE);
5135 bnx2x_init_block(bp, UCM_BLOCK, COMMON_STAGE);
5136 bnx2x_init_block(bp, CCM_BLOCK, COMMON_STAGE);
5137 bnx2x_init_block(bp, XCM_BLOCK, COMMON_STAGE);
5139 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
5140 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
5141 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
5142 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
5144 bnx2x_init_block(bp, QM_BLOCK, COMMON_STAGE);
5146 if (CHIP_MODE_IS_4_PORT(bp))
5147 bnx2x_init_block(bp, QM_4PORT_BLOCK, COMMON_STAGE);
5149 /* QM queues pointers table */
5150 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
5152 /* soft reset pulse */
5153 REG_WR(bp, QM_REG_SOFT_RESET, 1);
5154 REG_WR(bp, QM_REG_SOFT_RESET, 0);
5157 bnx2x_init_block(bp, TIMERS_BLOCK, COMMON_STAGE);
5160 bnx2x_init_block(bp, DQ_BLOCK, COMMON_STAGE);
5161 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
5163 if (!CHIP_REV_IS_SLOW(bp)) {
5164 /* enable hw interrupt from doorbell Q */
5165 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
5168 bnx2x_init_block(bp, BRB1_BLOCK, COMMON_STAGE);
5169 if (CHIP_MODE_IS_4_PORT(bp)) {
5170 REG_WR(bp, BRB1_REG_FULL_LB_XOFF_THRESHOLD, 248);
5171 REG_WR(bp, BRB1_REG_FULL_LB_XON_THRESHOLD, 328);
5174 bnx2x_init_block(bp, PRS_BLOCK, COMMON_STAGE);
5175 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
5178 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5180 if (!CHIP_IS_E1(bp))
5181 REG_WR(bp, PRS_REG_E1HOV_MODE, IS_MF_SD(bp));
5183 if (CHIP_IS_E2(bp)) {
5184 /* Bit-map indicating which L2 hdrs may appear after the
5185 basic Ethernet header */
5186 int has_ovlan = IS_MF_SD(bp);
5187 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5188 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5191 bnx2x_init_block(bp, TSDM_BLOCK, COMMON_STAGE);
5192 bnx2x_init_block(bp, CSDM_BLOCK, COMMON_STAGE);
5193 bnx2x_init_block(bp, USDM_BLOCK, COMMON_STAGE);
5194 bnx2x_init_block(bp, XSDM_BLOCK, COMMON_STAGE);
5196 bnx2x_init_fill(bp, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5197 bnx2x_init_fill(bp, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5198 bnx2x_init_fill(bp, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5199 bnx2x_init_fill(bp, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(bp));
5201 bnx2x_init_block(bp, TSEM_BLOCK, COMMON_STAGE);
5202 bnx2x_init_block(bp, USEM_BLOCK, COMMON_STAGE);
5203 bnx2x_init_block(bp, CSEM_BLOCK, COMMON_STAGE);
5204 bnx2x_init_block(bp, XSEM_BLOCK, COMMON_STAGE);
5206 if (CHIP_MODE_IS_4_PORT(bp))
5207 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, COMMON_STAGE);
5210 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
5212 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
5215 bnx2x_init_block(bp, UPB_BLOCK, COMMON_STAGE);
5216 bnx2x_init_block(bp, XPB_BLOCK, COMMON_STAGE);
5217 bnx2x_init_block(bp, PBF_BLOCK, COMMON_STAGE);
5219 if (CHIP_IS_E2(bp)) {
5220 int has_ovlan = IS_MF_SD(bp);
5221 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, (has_ovlan ? 7 : 6));
5222 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, (has_ovlan ? 1 : 0));
5225 REG_WR(bp, SRC_REG_SOFT_RST, 1);
5226 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
5227 REG_WR(bp, i, random32());
5229 bnx2x_init_block(bp, SRCH_BLOCK, COMMON_STAGE);
5231 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
5232 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
5233 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
5234 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
5235 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
5236 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
5237 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
5238 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
5239 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
5240 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
5242 REG_WR(bp, SRC_REG_SOFT_RST, 0);
5244 if (sizeof(union cdu_context) != 1024)
5245 /* we currently assume that a context is 1024 bytes */
5246 dev_alert(&bp->pdev->dev, "please adjust the size "
5247 "of cdu_context(%ld)\n",
5248 (long)sizeof(union cdu_context));
5250 bnx2x_init_block(bp, CDU_BLOCK, COMMON_STAGE);
5251 val = (4 << 24) + (0 << 12) + 1024;
5252 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
5254 bnx2x_init_block(bp, CFC_BLOCK, COMMON_STAGE);
5255 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
5256 /* enable context validation interrupt from CFC */
5257 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
5259 /* set the thresholds to prevent CFC/CDU race */
5260 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
5262 bnx2x_init_block(bp, HC_BLOCK, COMMON_STAGE);
5264 if (CHIP_IS_E2(bp) && BP_NOMCP(bp))
5265 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
5267 bnx2x_init_block(bp, IGU_BLOCK, COMMON_STAGE);
5268 bnx2x_init_block(bp, MISC_AEU_BLOCK, COMMON_STAGE);
5270 bnx2x_init_block(bp, PXPCS_BLOCK, COMMON_STAGE);
5271 /* Reset PCIE errors for debug */
5272 REG_WR(bp, 0x2814, 0xffffffff);
5273 REG_WR(bp, 0x3820, 0xffffffff);
5275 if (CHIP_IS_E2(bp)) {
5276 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
5277 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
5278 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
5279 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
5280 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
5281 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
5282 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
5283 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
5284 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
5285 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
5286 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
5289 bnx2x_init_block(bp, EMAC0_BLOCK, COMMON_STAGE);
5290 bnx2x_init_block(bp, EMAC1_BLOCK, COMMON_STAGE);
5291 bnx2x_init_block(bp, DBU_BLOCK, COMMON_STAGE);
5292 bnx2x_init_block(bp, DBG_BLOCK, COMMON_STAGE);
5294 bnx2x_init_block(bp, NIG_BLOCK, COMMON_STAGE);
5295 if (!CHIP_IS_E1(bp)) {
5296 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
5297 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
5299 if (CHIP_IS_E2(bp)) {
5300 /* Bit-map indicating which L2 hdrs may appear after the
5301 basic Ethernet header */
5302 REG_WR(bp, NIG_REG_P0_HDRS_AFTER_BASIC, (IS_MF_SD(bp) ? 7 : 6));
5305 if (CHIP_REV_IS_SLOW(bp))
5308 /* finish CFC init */
5309 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
5311 BNX2X_ERR("CFC LL_INIT failed\n");
5314 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
5316 BNX2X_ERR("CFC AC_INIT failed\n");
5319 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
5321 BNX2X_ERR("CFC CAM_INIT failed\n");
5324 REG_WR(bp, CFC_REG_DEBUG0, 0);
5326 if (CHIP_IS_E1(bp)) {
5327 /* read NIG statistic
5328 to see if this is our first up since powerup */
5329 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5330 val = *bnx2x_sp(bp, wb_data[0]);
5332 /* do internal memory self test */
5333 if ((val == 0) && bnx2x_int_mem_test(bp)) {
5334 BNX2X_ERR("internal mem self test failed\n");
5339 bnx2x_setup_fan_failure_detection(bp);
5341 /* clear PXP2 attentions */
5342 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
5344 bnx2x_enable_blocks_attention(bp);
5345 if (CHIP_PARITY_ENABLED(bp))
5346 bnx2x_enable_blocks_parity(bp);
5348 if (!BP_NOMCP(bp)) {
5349 /* In E2 2-PORT mode, same ext phy is used for the two paths */
5350 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
5352 u32 shmem_base[2], shmem2_base[2];
5353 shmem_base[0] = bp->common.shmem_base;
5354 shmem2_base[0] = bp->common.shmem2_base;
5355 if (CHIP_IS_E2(bp)) {
5357 SHMEM2_RD(bp, other_shmem_base_addr);
5359 SHMEM2_RD(bp, other_shmem2_base_addr);
5361 bnx2x_acquire_phy_lock(bp);
5362 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
5363 bp->common.chip_id);
5364 bnx2x_release_phy_lock(bp);
5367 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
5372 static int bnx2x_init_hw_port(struct bnx2x *bp)
5374 int port = BP_PORT(bp);
5375 int init_stage = port ? PORT1_STAGE : PORT0_STAGE;
5379 DP(BNX2X_MSG_MCP, "starting port init port %d\n", port);
5381 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
5383 bnx2x_init_block(bp, PXP_BLOCK, init_stage);
5384 bnx2x_init_block(bp, PXP2_BLOCK, init_stage);
5386 /* Timers bug workaround: disables the pf_master bit in pglue at
5387 * common phase, we need to enable it here before any dmae access are
5388 * attempted. Therefore we manually added the enable-master to the
5389 * port phase (it also happens in the function phase)
5392 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5394 bnx2x_init_block(bp, TCM_BLOCK, init_stage);
5395 bnx2x_init_block(bp, UCM_BLOCK, init_stage);
5396 bnx2x_init_block(bp, CCM_BLOCK, init_stage);
5397 bnx2x_init_block(bp, XCM_BLOCK, init_stage);
5399 /* QM cid (connection) count */
5400 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
5403 bnx2x_init_block(bp, TIMERS_BLOCK, init_stage);
5404 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
5405 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
5408 bnx2x_init_block(bp, DQ_BLOCK, init_stage);
5410 if (CHIP_MODE_IS_4_PORT(bp))
5411 bnx2x_init_block(bp, QM_4PORT_BLOCK, init_stage);
5413 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
5414 bnx2x_init_block(bp, BRB1_BLOCK, init_stage);
5415 if (CHIP_REV_IS_SLOW(bp) && CHIP_IS_E1(bp)) {
5416 /* no pause for emulation and FPGA */
5421 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
5422 else if (bp->dev->mtu > 4096) {
5423 if (bp->flags & ONE_PORT_FLAG)
5427 /* (24*1024 + val*4)/256 */
5428 low = 96 + (val/64) +
5429 ((val % 64) ? 1 : 0);
5432 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
5433 high = low + 56; /* 14*1024/256 */
5435 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
5436 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
5439 if (CHIP_MODE_IS_4_PORT(bp)) {
5440 REG_WR(bp, BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 + port*8, 248);
5441 REG_WR(bp, BRB1_REG_PAUSE_0_XON_THRESHOLD_0 + port*8, 328);
5442 REG_WR(bp, (BP_PORT(bp) ? BRB1_REG_MAC_GUARANTIED_1 :
5443 BRB1_REG_MAC_GUARANTIED_0), 40);
5446 bnx2x_init_block(bp, PRS_BLOCK, init_stage);
5448 bnx2x_init_block(bp, TSDM_BLOCK, init_stage);
5449 bnx2x_init_block(bp, CSDM_BLOCK, init_stage);
5450 bnx2x_init_block(bp, USDM_BLOCK, init_stage);
5451 bnx2x_init_block(bp, XSDM_BLOCK, init_stage);
5453 bnx2x_init_block(bp, TSEM_BLOCK, init_stage);
5454 bnx2x_init_block(bp, USEM_BLOCK, init_stage);
5455 bnx2x_init_block(bp, CSEM_BLOCK, init_stage);
5456 bnx2x_init_block(bp, XSEM_BLOCK, init_stage);
5457 if (CHIP_MODE_IS_4_PORT(bp))
5458 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, init_stage);
5460 bnx2x_init_block(bp, UPB_BLOCK, init_stage);
5461 bnx2x_init_block(bp, XPB_BLOCK, init_stage);
5463 bnx2x_init_block(bp, PBF_BLOCK, init_stage);
5465 if (!CHIP_IS_E2(bp)) {
5466 /* configure PBF to work without PAUSE mtu 9000 */
5467 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
5469 /* update threshold */
5470 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
5471 /* update init credit */
5472 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
5475 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
5477 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
5481 bnx2x_init_block(bp, SRCH_BLOCK, init_stage);
5483 bnx2x_init_block(bp, CDU_BLOCK, init_stage);
5484 bnx2x_init_block(bp, CFC_BLOCK, init_stage);
5486 if (CHIP_IS_E1(bp)) {
5487 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5488 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5490 bnx2x_init_block(bp, HC_BLOCK, init_stage);
5492 bnx2x_init_block(bp, IGU_BLOCK, init_stage);
5494 bnx2x_init_block(bp, MISC_AEU_BLOCK, init_stage);
5495 /* init aeu_mask_attn_func_0/1:
5496 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
5497 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
5498 * bits 4-7 are used for "per vn group attention" */
5499 val = IS_MF(bp) ? 0xF7 : 0x7;
5500 /* Enable DCBX attention for all but E1 */
5501 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
5502 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
5504 bnx2x_init_block(bp, PXPCS_BLOCK, init_stage);
5505 bnx2x_init_block(bp, EMAC0_BLOCK, init_stage);
5506 bnx2x_init_block(bp, EMAC1_BLOCK, init_stage);
5507 bnx2x_init_block(bp, DBU_BLOCK, init_stage);
5508 bnx2x_init_block(bp, DBG_BLOCK, init_stage);
5510 bnx2x_init_block(bp, NIG_BLOCK, init_stage);
5512 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
5514 if (!CHIP_IS_E1(bp)) {
5515 /* 0x2 disable mf_ov, 0x1 enable */
5516 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
5517 (IS_MF_SD(bp) ? 0x1 : 0x2));
5519 if (CHIP_IS_E2(bp)) {
5521 switch (bp->mf_mode) {
5522 case MULTI_FUNCTION_SD:
5525 case MULTI_FUNCTION_SI:
5530 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
5531 NIG_REG_LLH0_CLS_TYPE), val);
5534 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
5535 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
5536 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
5540 bnx2x_init_block(bp, MCP_BLOCK, init_stage);
5541 bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
5542 if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
5543 bp->common.shmem2_base, port)) {
5544 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5545 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5546 val = REG_RD(bp, reg_addr);
5547 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
5548 REG_WR(bp, reg_addr, val);
5550 bnx2x__link_reset(bp);
5555 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
5560 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
5562 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
5564 bnx2x_wb_wr(bp, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
5567 static inline void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
5569 bnx2x_igu_clear_sb_gen(bp, idu_sb_id, true /*PF*/);
5572 static inline void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
5574 u32 i, base = FUNC_ILT_BASE(func);
5575 for (i = base; i < base + ILT_PER_FUNC; i++)
5576 bnx2x_ilt_wr(bp, i, 0);
5579 static int bnx2x_init_hw_func(struct bnx2x *bp)
5581 int port = BP_PORT(bp);
5582 int func = BP_FUNC(bp);
5583 struct bnx2x_ilt *ilt = BP_ILT(bp);
5586 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
5587 int i, main_mem_width;
5589 DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
5591 /* set MSI reconfigure capability */
5592 if (bp->common.int_block == INT_BLOCK_HC) {
5593 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
5594 val = REG_RD(bp, addr);
5595 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
5596 REG_WR(bp, addr, val);
5600 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
5602 for (i = 0; i < L2_ILT_LINES(bp); i++) {
5603 ilt->lines[cdu_ilt_start + i].page =
5604 bp->context.vcxt + (ILT_PAGE_CIDS * i);
5605 ilt->lines[cdu_ilt_start + i].page_mapping =
5606 bp->context.cxt_mapping + (CDU_ILT_PAGE_SZ * i);
5607 /* cdu ilt pages are allocated manually so there's no need to
5610 bnx2x_ilt_init_op(bp, INITOP_SET);
5613 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
5615 /* T1 hash bits value determines the T1 number of entries */
5616 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
5621 REG_WR(bp, PRS_REG_NIC_MODE, 1);
5622 #endif /* BCM_CNIC */
5624 if (CHIP_IS_E2(bp)) {
5625 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
5627 /* Turn on a single ISR mode in IGU if driver is going to use
5630 if (!(bp->flags & USING_MSIX_FLAG))
5631 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
5633 * Timers workaround bug: function init part.
5634 * Need to wait 20msec after initializing ILT,
5635 * needed to make sure there are no requests in
5636 * one of the PXP internal queues with "old" ILT addresses
5640 * Master enable - Due to WB DMAE writes performed before this
5641 * register is re-initialized as part of the regular function
5644 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
5645 /* Enable the function in IGU */
5646 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
5651 bnx2x_init_block(bp, PGLUE_B_BLOCK, FUNC0_STAGE + func);
5654 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
5656 bnx2x_init_block(bp, MISC_BLOCK, FUNC0_STAGE + func);
5657 bnx2x_init_block(bp, TCM_BLOCK, FUNC0_STAGE + func);
5658 bnx2x_init_block(bp, UCM_BLOCK, FUNC0_STAGE + func);
5659 bnx2x_init_block(bp, CCM_BLOCK, FUNC0_STAGE + func);
5660 bnx2x_init_block(bp, XCM_BLOCK, FUNC0_STAGE + func);
5661 bnx2x_init_block(bp, TSEM_BLOCK, FUNC0_STAGE + func);
5662 bnx2x_init_block(bp, USEM_BLOCK, FUNC0_STAGE + func);
5663 bnx2x_init_block(bp, CSEM_BLOCK, FUNC0_STAGE + func);
5664 bnx2x_init_block(bp, XSEM_BLOCK, FUNC0_STAGE + func);
5666 if (CHIP_IS_E2(bp)) {
5667 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_PATH_ID_OFFSET,
5669 REG_WR(bp, BAR_CSTRORM_INTMEM + CSTORM_PATH_ID_OFFSET,
5673 if (CHIP_MODE_IS_4_PORT(bp))
5674 bnx2x_init_block(bp, XSEM_4PORT_BLOCK, FUNC0_STAGE + func);
5677 REG_WR(bp, QM_REG_PF_EN, 1);
5679 bnx2x_init_block(bp, QM_BLOCK, FUNC0_STAGE + func);
5681 if (CHIP_MODE_IS_4_PORT(bp))
5682 bnx2x_init_block(bp, QM_4PORT_BLOCK, FUNC0_STAGE + func);
5684 bnx2x_init_block(bp, TIMERS_BLOCK, FUNC0_STAGE + func);
5685 bnx2x_init_block(bp, DQ_BLOCK, FUNC0_STAGE + func);
5686 bnx2x_init_block(bp, BRB1_BLOCK, FUNC0_STAGE + func);
5687 bnx2x_init_block(bp, PRS_BLOCK, FUNC0_STAGE + func);
5688 bnx2x_init_block(bp, TSDM_BLOCK, FUNC0_STAGE + func);
5689 bnx2x_init_block(bp, CSDM_BLOCK, FUNC0_STAGE + func);
5690 bnx2x_init_block(bp, USDM_BLOCK, FUNC0_STAGE + func);
5691 bnx2x_init_block(bp, XSDM_BLOCK, FUNC0_STAGE + func);
5692 bnx2x_init_block(bp, UPB_BLOCK, FUNC0_STAGE + func);
5693 bnx2x_init_block(bp, XPB_BLOCK, FUNC0_STAGE + func);
5694 bnx2x_init_block(bp, PBF_BLOCK, FUNC0_STAGE + func);
5696 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
5698 bnx2x_init_block(bp, CDU_BLOCK, FUNC0_STAGE + func);
5700 bnx2x_init_block(bp, CFC_BLOCK, FUNC0_STAGE + func);
5703 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
5706 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
5707 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
5710 bnx2x_init_block(bp, MISC_AEU_BLOCK, FUNC0_STAGE + func);
5712 /* HC init per function */
5713 if (bp->common.int_block == INT_BLOCK_HC) {
5714 if (CHIP_IS_E1H(bp)) {
5715 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5717 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
5718 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
5720 bnx2x_init_block(bp, HC_BLOCK, FUNC0_STAGE + func);
5723 int num_segs, sb_idx, prod_offset;
5725 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
5727 if (CHIP_IS_E2(bp)) {
5728 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
5729 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
5732 bnx2x_init_block(bp, IGU_BLOCK, FUNC0_STAGE + func);
5734 if (CHIP_IS_E2(bp)) {
5738 * E2 mode: address 0-135 match to the mapping memory;
5739 * 136 - PF0 default prod; 137 - PF1 default prod;
5740 * 138 - PF2 default prod; 139 - PF3 default prod;
5741 * 140 - PF0 attn prod; 141 - PF1 attn prod;
5742 * 142 - PF2 attn prod; 143 - PF3 attn prod;
5745 * E1.5 mode - In backward compatible mode;
5746 * for non default SB; each even line in the memory
5747 * holds the U producer and each odd line hold
5748 * the C producer. The first 128 producers are for
5749 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
5750 * producers are for the DSB for each PF.
5751 * Each PF has five segments: (the order inside each
5752 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
5753 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
5754 * 144-147 attn prods;
5756 /* non-default-status-blocks */
5757 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5758 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
5759 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
5760 prod_offset = (bp->igu_base_sb + sb_idx) *
5763 for (i = 0; i < num_segs; i++) {
5764 addr = IGU_REG_PROD_CONS_MEMORY +
5765 (prod_offset + i) * 4;
5766 REG_WR(bp, addr, 0);
5768 /* send consumer update with value 0 */
5769 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
5770 USTORM_ID, 0, IGU_INT_NOP, 1);
5771 bnx2x_igu_clear_sb(bp,
5772 bp->igu_base_sb + sb_idx);
5775 /* default-status-blocks */
5776 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
5777 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
5779 if (CHIP_MODE_IS_4_PORT(bp))
5780 dsb_idx = BP_FUNC(bp);
5782 dsb_idx = BP_E1HVN(bp);
5784 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
5785 IGU_BC_BASE_DSB_PROD + dsb_idx :
5786 IGU_NORM_BASE_DSB_PROD + dsb_idx);
5788 for (i = 0; i < (num_segs * E1HVN_MAX);
5790 addr = IGU_REG_PROD_CONS_MEMORY +
5791 (prod_offset + i)*4;
5792 REG_WR(bp, addr, 0);
5794 /* send consumer update with 0 */
5795 if (CHIP_INT_MODE_IS_BC(bp)) {
5796 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5797 USTORM_ID, 0, IGU_INT_NOP, 1);
5798 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5799 CSTORM_ID, 0, IGU_INT_NOP, 1);
5800 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5801 XSTORM_ID, 0, IGU_INT_NOP, 1);
5802 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5803 TSTORM_ID, 0, IGU_INT_NOP, 1);
5804 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5805 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5807 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5808 USTORM_ID, 0, IGU_INT_NOP, 1);
5809 bnx2x_ack_sb(bp, bp->igu_dsb_id,
5810 ATTENTION_ID, 0, IGU_INT_NOP, 1);
5812 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
5814 /* !!! these should become driver const once
5815 rf-tool supports split-68 const */
5816 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
5817 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
5818 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
5819 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
5820 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
5821 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
5825 /* Reset PCIE errors for debug */
5826 REG_WR(bp, 0x2114, 0xffffffff);
5827 REG_WR(bp, 0x2120, 0xffffffff);
5829 bnx2x_init_block(bp, EMAC0_BLOCK, FUNC0_STAGE + func);
5830 bnx2x_init_block(bp, EMAC1_BLOCK, FUNC0_STAGE + func);
5831 bnx2x_init_block(bp, DBU_BLOCK, FUNC0_STAGE + func);
5832 bnx2x_init_block(bp, DBG_BLOCK, FUNC0_STAGE + func);
5833 bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
5834 bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
5836 if (CHIP_IS_E1x(bp)) {
5837 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
5838 main_mem_base = HC_REG_MAIN_MEMORY +
5839 BP_PORT(bp) * (main_mem_size * 4);
5840 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
5843 val = REG_RD(bp, main_mem_prty_clr);
5845 DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
5847 "function init (0x%x)!\n", val);
5849 /* Clear "false" parity errors in MSI-X table */
5850 for (i = main_mem_base;
5851 i < main_mem_base + main_mem_size * 4;
5852 i += main_mem_width) {
5853 bnx2x_read_dmae(bp, i, main_mem_width / 4);
5854 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
5855 i, main_mem_width / 4);
5857 /* Clear HC parity attention */
5858 REG_RD(bp, main_mem_prty_clr);
5861 bnx2x_phy_probe(&bp->link_params);
5866 int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
5870 DP(BNX2X_MSG_MCP, "function %d load_code %x\n",
5871 BP_ABS_FUNC(bp), load_code);
5874 spin_lock_init(&bp->dmae_lock);
5876 switch (load_code) {
5877 case FW_MSG_CODE_DRV_LOAD_COMMON:
5878 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5879 rc = bnx2x_init_hw_common(bp, load_code);
5884 case FW_MSG_CODE_DRV_LOAD_PORT:
5885 rc = bnx2x_init_hw_port(bp);
5890 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5891 rc = bnx2x_init_hw_func(bp);
5897 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5901 if (!BP_NOMCP(bp)) {
5902 int mb_idx = BP_FW_MB_IDX(bp);
5904 bp->fw_drv_pulse_wr_seq =
5905 (SHMEM_RD(bp, func_mb[mb_idx].drv_pulse_mb) &
5906 DRV_PULSE_SEQ_MASK);
5907 DP(BNX2X_MSG_MCP, "drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
5911 bnx2x_gunzip_end(bp);
5916 void bnx2x_free_mem(struct bnx2x *bp)
5918 bnx2x_gunzip_end(bp);
5921 bnx2x_free_fp_mem(bp);
5922 /* end of fastpath */
5924 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
5925 sizeof(struct host_sp_status_block));
5927 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
5928 sizeof(struct bnx2x_slowpath));
5930 BNX2X_PCI_FREE(bp->context.vcxt, bp->context.cxt_mapping,
5933 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
5935 BNX2X_FREE(bp->ilt->lines);
5939 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
5940 sizeof(struct host_hc_status_block_e2));
5942 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
5943 sizeof(struct host_hc_status_block_e1x));
5945 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
5948 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
5950 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
5951 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5953 BNX2X_FREE(bp->rx_indir_table);
5957 int bnx2x_alloc_mem(struct bnx2x *bp)
5959 if (bnx2x_gunzip_init(bp))
5964 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
5965 sizeof(struct host_hc_status_block_e2));
5967 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
5968 sizeof(struct host_hc_status_block_e1x));
5970 /* allocate searcher T2 table */
5971 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
5975 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
5976 sizeof(struct host_sp_status_block));
5978 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
5979 sizeof(struct bnx2x_slowpath));
5981 bp->context.size = sizeof(union cdu_context) * bp->l2_cid_count;
5983 BNX2X_PCI_ALLOC(bp->context.vcxt, &bp->context.cxt_mapping,
5986 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
5988 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
5991 /* Slow path ring */
5992 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
5995 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
5996 BCM_PAGE_SIZE * NUM_EQ_PAGES);
5998 BNX2X_ALLOC(bp->rx_indir_table, sizeof(bp->rx_indir_table[0]) *
5999 TSTORM_INDIRECTION_TABLE_SIZE);
6002 /* need to be done at the end, since it's self adjusting to amount
6003 * of memory available for RSS queues
6005 if (bnx2x_alloc_fp_mem(bp))
6015 * Init service functions
6017 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6018 int *state_p, int flags);
6020 int bnx2x_func_start(struct bnx2x *bp)
6022 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0, 0, 0, 1);
6024 /* Wait for completion */
6025 return bnx2x_wait_ramrod(bp, BNX2X_STATE_FUNC_STARTED, 0, &(bp->state),
6026 WAIT_RAMROD_COMMON);
6029 static int bnx2x_func_stop(struct bnx2x *bp)
6031 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0, 0, 1);
6033 /* Wait for completion */
6034 return bnx2x_wait_ramrod(bp, BNX2X_STATE_CLOSING_WAIT4_UNLOAD,
6035 0, &(bp->state), WAIT_RAMROD_COMMON);
6039 * bnx2x_set_mac_addr_gen - set a MAC in a CAM for a few L2 Clients for E1x chips
6041 * @bp: driver handle
6042 * @set: set or clear an entry (1 or 0)
6043 * @mac: pointer to a buffer containing a MAC
6044 * @cl_bit_vec: bit vector of clients to register a MAC for
6045 * @cam_offset: offset in a CAM to use
6046 * @is_bcast: is the set MAC a broadcast address (for E1 only)
6048 static void bnx2x_set_mac_addr_gen(struct bnx2x *bp, int set, const u8 *mac,
6049 u32 cl_bit_vec, u8 cam_offset,
6052 struct mac_configuration_cmd *config =
6053 (struct mac_configuration_cmd *)bnx2x_sp(bp, mac_config);
6054 int ramrod_flags = WAIT_RAMROD_COMMON;
6056 bp->set_mac_pending = 1;
6058 config->hdr.length = 1;
6059 config->hdr.offset = cam_offset;
6060 config->hdr.client_id = 0xff;
6061 /* Mark the single MAC configuration ramrod as opposed to a
6062 * UC/MC list configuration).
6064 config->hdr.echo = 1;
6067 config->config_table[0].msb_mac_addr =
6068 swab16(*(u16 *)&mac[0]);
6069 config->config_table[0].middle_mac_addr =
6070 swab16(*(u16 *)&mac[2]);
6071 config->config_table[0].lsb_mac_addr =
6072 swab16(*(u16 *)&mac[4]);
6073 config->config_table[0].clients_bit_vector =
6074 cpu_to_le32(cl_bit_vec);
6075 config->config_table[0].vlan_id = 0;
6076 config->config_table[0].pf_id = BP_FUNC(bp);
6078 SET_FLAG(config->config_table[0].flags,
6079 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6080 T_ETH_MAC_COMMAND_SET);
6082 SET_FLAG(config->config_table[0].flags,
6083 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6084 T_ETH_MAC_COMMAND_INVALIDATE);
6087 SET_FLAG(config->config_table[0].flags,
6088 MAC_CONFIGURATION_ENTRY_BROADCAST, 1);
6090 DP(NETIF_MSG_IFUP, "%s MAC (%04x:%04x:%04x) PF_ID %d CLID mask %d\n",
6091 (set ? "setting" : "clearing"),
6092 config->config_table[0].msb_mac_addr,
6093 config->config_table[0].middle_mac_addr,
6094 config->config_table[0].lsb_mac_addr, BP_FUNC(bp), cl_bit_vec);
6098 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6099 U64_HI(bnx2x_sp_mapping(bp, mac_config)),
6100 U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
6102 /* Wait for a completion */
6103 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending, ramrod_flags);
6106 static int bnx2x_wait_ramrod(struct bnx2x *bp, int state, int idx,
6107 int *state_p, int flags)
6109 /* can take a while if any port is running */
6111 u8 poll = flags & WAIT_RAMROD_POLL;
6112 u8 common = flags & WAIT_RAMROD_COMMON;
6114 DP(NETIF_MSG_IFUP, "%s for state to become %x on IDX [%d]\n",
6115 poll ? "polling" : "waiting", state, idx);
6123 bnx2x_rx_int(bp->fp, 10);
6124 /* if index is different from 0
6125 * the reply for some commands will
6126 * be on the non default queue
6129 bnx2x_rx_int(&bp->fp[idx], 10);
6133 mb(); /* state is changed by bnx2x_sp_event() */
6134 if (*state_p == state) {
6135 #ifdef BNX2X_STOP_ON_ERROR
6136 DP(NETIF_MSG_IFUP, "exit (cnt %d)\n", 5000 - cnt);
6148 BNX2X_ERR("timeout %s for state %x on IDX [%d]\n",
6149 poll ? "polling" : "waiting", state, idx);
6150 #ifdef BNX2X_STOP_ON_ERROR
6157 static u8 bnx2x_e1h_cam_offset(struct bnx2x *bp, u8 rel_offset)
6159 if (CHIP_IS_E1H(bp))
6160 return E1H_FUNC_MAX * rel_offset + BP_FUNC(bp);
6161 else if (CHIP_MODE_IS_4_PORT(bp))
6162 return E2_FUNC_MAX * rel_offset + BP_FUNC(bp);
6164 return E2_FUNC_MAX * rel_offset + BP_VN(bp);
6168 * LLH CAM line allocations: currently only iSCSI and ETH macs are
6169 * relevant. In addition, current implementation is tuned for a
6173 LLH_CAM_ISCSI_ETH_LINE = 0,
6175 LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE
6178 static void bnx2x_set_mac_in_nig(struct bnx2x *bp,
6180 unsigned char *dev_addr,
6184 u32 mem_offset, ena_offset, mem_index;
6187 * 0..7 - goes to MEM
6188 * 8..15 - goes to MEM2
6191 if (!IS_MF_SI(bp) || index > LLH_CAM_MAX_PF_LINE)
6194 /* calculate memory start offset according to the mapping
6195 * and index in the memory */
6196 if (index < NIG_LLH_FUNC_MEM_MAX_OFFSET) {
6197 mem_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM :
6198 NIG_REG_LLH0_FUNC_MEM;
6199 ena_offset = BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
6200 NIG_REG_LLH0_FUNC_MEM_ENABLE;
6203 mem_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2 :
6204 NIG_REG_P0_LLH_FUNC_MEM2;
6205 ena_offset = BP_PORT(bp) ? NIG_REG_P1_LLH_FUNC_MEM2_ENABLE :
6206 NIG_REG_P0_LLH_FUNC_MEM2_ENABLE;
6207 mem_index = index - NIG_LLH_FUNC_MEM_MAX_OFFSET;
6211 /* LLH_FUNC_MEM is a u64 WB register */
6212 mem_offset += 8*mem_index;
6214 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
6215 (dev_addr[4] << 8) | dev_addr[5]);
6216 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
6218 REG_WR_DMAE(bp, mem_offset, wb_data, 2);
6221 /* enable/disable the entry */
6222 REG_WR(bp, ena_offset + 4*mem_index, set);
6226 void bnx2x_set_eth_mac(struct bnx2x *bp, int set)
6228 u8 cam_offset = (CHIP_IS_E1(bp) ? (BP_PORT(bp) ? 32 : 0) :
6229 bnx2x_e1h_cam_offset(bp, CAM_ETH_LINE));
6231 /* networking MAC */
6232 bnx2x_set_mac_addr_gen(bp, set, bp->dev->dev_addr,
6233 (1 << bp->fp->cl_id), cam_offset , 0);
6235 bnx2x_set_mac_in_nig(bp, set, bp->dev->dev_addr, LLH_CAM_ETH_LINE);
6237 if (CHIP_IS_E1(bp)) {
6239 static const u8 bcast[ETH_ALEN] = {
6240 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
6242 bnx2x_set_mac_addr_gen(bp, set, bcast, 0, cam_offset + 1, 1);
6246 static inline u8 bnx2x_e1_cam_mc_offset(struct bnx2x *bp)
6248 return CHIP_REV_IS_SLOW(bp) ?
6249 (BNX2X_MAX_EMUL_MULTI * (1 + BP_PORT(bp))) :
6250 (BNX2X_MAX_MULTICAST * (1 + BP_PORT(bp)));
6253 /* set mc list, do not wait as wait implies sleep and
6254 * set_rx_mode can be invoked from non-sleepable context.
6256 * Instead we use the same ramrod data buffer each time we need
6257 * to configure a list of addresses, and use the fact that the
6258 * list of MACs is changed in an incremental way and that the
6259 * function is called under the netif_addr_lock. A temporary
6260 * inconsistent CAM configuration (possible in case of a very fast
6261 * sequence of add/del/add on the host side) will shortly be
6262 * restored by the handler of the last ramrod.
6264 static int bnx2x_set_e1_mc_list(struct bnx2x *bp)
6267 struct net_device *dev = bp->dev;
6268 u8 offset = bnx2x_e1_cam_mc_offset(bp);
6269 struct netdev_hw_addr *ha;
6270 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6271 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6273 if (netdev_mc_count(dev) > BNX2X_MAX_MULTICAST)
6276 netdev_for_each_mc_addr(ha, dev) {
6278 config_cmd->config_table[i].msb_mac_addr =
6279 swab16(*(u16 *)&bnx2x_mc_addr(ha)[0]);
6280 config_cmd->config_table[i].middle_mac_addr =
6281 swab16(*(u16 *)&bnx2x_mc_addr(ha)[2]);
6282 config_cmd->config_table[i].lsb_mac_addr =
6283 swab16(*(u16 *)&bnx2x_mc_addr(ha)[4]);
6285 config_cmd->config_table[i].vlan_id = 0;
6286 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
6287 config_cmd->config_table[i].clients_bit_vector =
6288 cpu_to_le32(1 << BP_L_ID(bp));
6290 SET_FLAG(config_cmd->config_table[i].flags,
6291 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6292 T_ETH_MAC_COMMAND_SET);
6295 "setting MCAST[%d] (%04x:%04x:%04x)\n", i,
6296 config_cmd->config_table[i].msb_mac_addr,
6297 config_cmd->config_table[i].middle_mac_addr,
6298 config_cmd->config_table[i].lsb_mac_addr);
6301 old = config_cmd->hdr.length;
6303 for (; i < old; i++) {
6304 if (CAM_IS_INVALID(config_cmd->
6306 /* already invalidated */
6310 SET_FLAG(config_cmd->config_table[i].flags,
6311 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6312 T_ETH_MAC_COMMAND_INVALIDATE);
6318 config_cmd->hdr.length = i;
6319 config_cmd->hdr.offset = offset;
6320 config_cmd->hdr.client_id = 0xff;
6321 /* Mark that this ramrod doesn't use bp->set_mac_pending for
6324 config_cmd->hdr.echo = 0;
6328 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6329 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6332 void bnx2x_invalidate_e1_mc_list(struct bnx2x *bp)
6335 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, mcast_config);
6336 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, mcast_config);
6337 int ramrod_flags = WAIT_RAMROD_COMMON;
6338 u8 offset = bnx2x_e1_cam_mc_offset(bp);
6340 for (i = 0; i < BNX2X_MAX_MULTICAST; i++)
6341 SET_FLAG(config_cmd->config_table[i].flags,
6342 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
6343 T_ETH_MAC_COMMAND_INVALIDATE);
6347 config_cmd->hdr.length = BNX2X_MAX_MULTICAST;
6348 config_cmd->hdr.offset = offset;
6349 config_cmd->hdr.client_id = 0xff;
6350 /* We'll wait for a completion this time... */
6351 config_cmd->hdr.echo = 1;
6353 bp->set_mac_pending = 1;
6357 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
6358 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
6360 /* Wait for a completion */
6361 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
6366 /* Accept one or more multicasts */
6367 static int bnx2x_set_e1h_mc_list(struct bnx2x *bp)
6369 struct net_device *dev = bp->dev;
6370 struct netdev_hw_addr *ha;
6371 u32 mc_filter[MC_HASH_SIZE];
6372 u32 crc, bit, regidx;
6375 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
6377 netdev_for_each_mc_addr(ha, dev) {
6378 DP(NETIF_MSG_IFUP, "Adding mcast MAC: %pM\n",
6381 crc = crc32c_le(0, bnx2x_mc_addr(ha),
6383 bit = (crc >> 24) & 0xff;
6386 mc_filter[regidx] |= (1 << bit);
6389 for (i = 0; i < MC_HASH_SIZE; i++)
6390 REG_WR(bp, MC_HASH_OFFSET(bp, i),
6396 void bnx2x_invalidate_e1h_mc_list(struct bnx2x *bp)
6400 for (i = 0; i < MC_HASH_SIZE; i++)
6401 REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
6406 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
6408 * @bp: driver handle
6409 * @set: set or clear the CAM entry
6411 * This function will wait until the ramdord completion returns.
6412 * Return 0 if success, -ENODEV if ramrod doesn't return.
6414 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp, int set)
6416 u8 cam_offset = (CHIP_IS_E1(bp) ? ((BP_PORT(bp) ? 32 : 0) + 2) :
6417 bnx2x_e1h_cam_offset(bp, CAM_ISCSI_ETH_LINE));
6418 u32 iscsi_l2_cl_id = BNX2X_ISCSI_ETH_CL_ID +
6419 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
6420 u32 cl_bit_vec = (1 << iscsi_l2_cl_id);
6421 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
6423 /* Send a SET_MAC ramrod */
6424 bnx2x_set_mac_addr_gen(bp, set, iscsi_mac, cl_bit_vec,
6427 bnx2x_set_mac_in_nig(bp, set, iscsi_mac, LLH_CAM_ISCSI_ETH_LINE);
6433 * bnx2x_set_fip_eth_mac_addr - set FCoE L2 MAC(s)
6435 * @bp: driver handle
6436 * @set: set or clear the CAM entry
6438 * This function will wait until the ramrod completion returns.
6439 * Returns 0 if success, -ENODEV if ramrod doesn't return.
6441 int bnx2x_set_fip_eth_mac_addr(struct bnx2x *bp, int set)
6443 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6445 * CAM allocation for E1H
6446 * eth unicasts: by func number
6447 * iscsi: by func number
6448 * fip unicast: by func number
6449 * fip multicast: by func number
6451 bnx2x_set_mac_addr_gen(bp, set, bp->fip_mac,
6452 cl_bit_vec, bnx2x_e1h_cam_offset(bp, CAM_FIP_ETH_LINE), 0);
6457 int bnx2x_set_all_enode_macs(struct bnx2x *bp, int set)
6459 u32 cl_bit_vec = (1 << bnx2x_fcoe(bp, cl_id));
6462 * CAM allocation for E1H
6463 * eth unicasts: by func number
6464 * iscsi: by func number
6465 * fip unicast: by func number
6466 * fip multicast: by func number
6468 bnx2x_set_mac_addr_gen(bp, set, ALL_ENODE_MACS, cl_bit_vec,
6469 bnx2x_e1h_cam_offset(bp, CAM_FIP_MCAST_LINE), 0);
6475 static void bnx2x_fill_cl_init_data(struct bnx2x *bp,
6476 struct bnx2x_client_init_params *params,
6478 struct client_init_ramrod_data *data)
6480 /* Clear the buffer */
6481 memset(data, 0, sizeof(*data));
6484 data->general.client_id = params->rxq_params.cl_id;
6485 data->general.statistics_counter_id = params->rxq_params.stat_id;
6486 data->general.statistics_en_flg =
6487 (params->rxq_params.flags & QUEUE_FLG_STATS) ? 1 : 0;
6488 data->general.is_fcoe_flg =
6489 (params->ramrod_params.flags & CLIENT_IS_FCOE) ? 1 : 0;
6490 data->general.activate_flg = activate;
6491 data->general.sp_client_id = params->rxq_params.spcl_id;
6494 data->rx.tpa_en_flg =
6495 (params->rxq_params.flags & QUEUE_FLG_TPA) ? 1 : 0;
6496 data->rx.vmqueue_mode_en_flg = 0;
6497 data->rx.cache_line_alignment_log_size =
6498 params->rxq_params.cache_line_log;
6499 data->rx.enable_dynamic_hc =
6500 (params->rxq_params.flags & QUEUE_FLG_DHC) ? 1 : 0;
6501 data->rx.max_sges_for_packet = params->rxq_params.max_sges_pkt;
6502 data->rx.client_qzone_id = params->rxq_params.cl_qzone_id;
6503 data->rx.max_agg_size = params->rxq_params.tpa_agg_sz;
6505 /* We don't set drop flags */
6506 data->rx.drop_ip_cs_err_flg = 0;
6507 data->rx.drop_tcp_cs_err_flg = 0;
6508 data->rx.drop_ttl0_flg = 0;
6509 data->rx.drop_udp_cs_err_flg = 0;
6511 data->rx.inner_vlan_removal_enable_flg =
6512 (params->rxq_params.flags & QUEUE_FLG_VLAN) ? 1 : 0;
6513 data->rx.outer_vlan_removal_enable_flg =
6514 (params->rxq_params.flags & QUEUE_FLG_OV) ? 1 : 0;
6515 data->rx.status_block_id = params->rxq_params.fw_sb_id;
6516 data->rx.rx_sb_index_number = params->rxq_params.sb_cq_index;
6517 data->rx.bd_buff_size = cpu_to_le16(params->rxq_params.buf_sz);
6518 data->rx.sge_buff_size = cpu_to_le16(params->rxq_params.sge_buf_sz);
6519 data->rx.mtu = cpu_to_le16(params->rxq_params.mtu);
6520 data->rx.bd_page_base.lo =
6521 cpu_to_le32(U64_LO(params->rxq_params.dscr_map));
6522 data->rx.bd_page_base.hi =
6523 cpu_to_le32(U64_HI(params->rxq_params.dscr_map));
6524 data->rx.sge_page_base.lo =
6525 cpu_to_le32(U64_LO(params->rxq_params.sge_map));
6526 data->rx.sge_page_base.hi =
6527 cpu_to_le32(U64_HI(params->rxq_params.sge_map));
6528 data->rx.cqe_page_base.lo =
6529 cpu_to_le32(U64_LO(params->rxq_params.rcq_map));
6530 data->rx.cqe_page_base.hi =
6531 cpu_to_le32(U64_HI(params->rxq_params.rcq_map));
6532 data->rx.is_leading_rss =
6533 (params->ramrod_params.flags & CLIENT_IS_LEADING_RSS) ? 1 : 0;
6534 data->rx.is_approx_mcast = data->rx.is_leading_rss;
6537 data->tx.enforce_security_flg = 0; /* VF specific */
6538 data->tx.tx_status_block_id = params->txq_params.fw_sb_id;
6539 data->tx.tx_sb_index_number = params->txq_params.sb_cq_index;
6540 data->tx.mtu = 0; /* VF specific */
6541 data->tx.tx_bd_page_base.lo =
6542 cpu_to_le32(U64_LO(params->txq_params.dscr_map));
6543 data->tx.tx_bd_page_base.hi =
6544 cpu_to_le32(U64_HI(params->txq_params.dscr_map));
6546 /* flow control data */
6547 data->fc.cqe_pause_thr_low = cpu_to_le16(params->pause.rcq_th_lo);
6548 data->fc.cqe_pause_thr_high = cpu_to_le16(params->pause.rcq_th_hi);
6549 data->fc.bd_pause_thr_low = cpu_to_le16(params->pause.bd_th_lo);
6550 data->fc.bd_pause_thr_high = cpu_to_le16(params->pause.bd_th_hi);
6551 data->fc.sge_pause_thr_low = cpu_to_le16(params->pause.sge_th_lo);
6552 data->fc.sge_pause_thr_high = cpu_to_le16(params->pause.sge_th_hi);
6553 data->fc.rx_cos_mask = cpu_to_le16(params->pause.pri_map);
6555 data->fc.safc_group_num = params->txq_params.cos;
6556 data->fc.safc_group_en_flg =
6557 (params->txq_params.flags & QUEUE_FLG_COS) ? 1 : 0;
6558 data->fc.traffic_type =
6559 (params->ramrod_params.flags & CLIENT_IS_FCOE) ?
6560 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
6563 static inline void bnx2x_set_ctx_validation(struct eth_context *cxt, u32 cid)
6565 /* ustorm cxt validation */
6566 cxt->ustorm_ag_context.cdu_usage =
6567 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_UCM_AG,
6568 ETH_CONNECTION_TYPE);
6569 /* xcontext validation */
6570 cxt->xstorm_ag_context.cdu_reserved =
6571 CDU_RSRVD_VALUE_TYPE_A(cid, CDU_REGION_NUMBER_XCM_AG,
6572 ETH_CONNECTION_TYPE);
6575 static int bnx2x_setup_fw_client(struct bnx2x *bp,
6576 struct bnx2x_client_init_params *params,
6578 struct client_init_ramrod_data *data,
6579 dma_addr_t data_mapping)
6582 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
6583 int ramrod_flags = 0, rc;
6585 /* HC and context validation values */
6586 hc_usec = params->txq_params.hc_rate ?
6587 1000000 / params->txq_params.hc_rate : 0;
6588 bnx2x_update_coalesce_sb_index(bp,
6589 params->txq_params.fw_sb_id,
6590 params->txq_params.sb_cq_index,
6591 !(params->txq_params.flags & QUEUE_FLG_HC),
6594 *(params->ramrod_params.pstate) = BNX2X_FP_STATE_OPENING;
6596 hc_usec = params->rxq_params.hc_rate ?
6597 1000000 / params->rxq_params.hc_rate : 0;
6598 bnx2x_update_coalesce_sb_index(bp,
6599 params->rxq_params.fw_sb_id,
6600 params->rxq_params.sb_cq_index,
6601 !(params->rxq_params.flags & QUEUE_FLG_HC),
6604 bnx2x_set_ctx_validation(params->rxq_params.cxt,
6605 params->rxq_params.cid);
6608 if (params->txq_params.flags & QUEUE_FLG_STATS)
6609 storm_memset_xstats_zero(bp, BP_PORT(bp),
6610 params->txq_params.stat_id);
6612 if (params->rxq_params.flags & QUEUE_FLG_STATS) {
6613 storm_memset_ustats_zero(bp, BP_PORT(bp),
6614 params->rxq_params.stat_id);
6615 storm_memset_tstats_zero(bp, BP_PORT(bp),
6616 params->rxq_params.stat_id);
6619 /* Fill the ramrod data */
6620 bnx2x_fill_cl_init_data(bp, params, activate, data);
6624 * bnx2x_sp_post() takes a spin_lock thus no other explict memory
6625 * barrier except from mmiowb() is needed to impose a
6626 * proper ordering of memory operations.
6631 bnx2x_sp_post(bp, ramrod, params->ramrod_params.cid,
6632 U64_HI(data_mapping), U64_LO(data_mapping), 0);
6634 /* Wait for completion */
6635 rc = bnx2x_wait_ramrod(bp, params->ramrod_params.state,
6636 params->ramrod_params.index,
6637 params->ramrod_params.pstate,
6643 * bnx2x_set_int_mode - configure interrupt mode
6645 * @bp: driver handle
6647 * In case of MSI-X it will also try to enable MSI-X.
6649 static int __devinit bnx2x_set_int_mode(struct bnx2x *bp)
6653 switch (bp->int_mode) {
6655 bnx2x_enable_msi(bp);
6656 /* falling through... */
6658 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6659 DP(NETIF_MSG_IFUP, "set number of queues to 1\n");
6662 /* Set number of queues according to bp->multi_mode value */
6663 bnx2x_set_num_queues(bp);
6665 DP(NETIF_MSG_IFUP, "set number of queues to %d\n",
6668 /* if we can't use MSI-X we only need one fp,
6669 * so try to enable MSI-X with the requested number of fp's
6670 * and fallback to MSI or legacy INTx with one fp
6672 rc = bnx2x_enable_msix(bp);
6674 /* failed to enable MSI-X */
6677 "Multi requested but failed to "
6678 "enable MSI-X (%d), "
6679 "set number of queues to %d\n",
6681 1 + NONE_ETH_CONTEXT_USE);
6682 bp->num_queues = 1 + NONE_ETH_CONTEXT_USE;
6684 if (!(bp->flags & DISABLE_MSI_FLAG))
6685 bnx2x_enable_msi(bp);
6694 /* must be called prioir to any HW initializations */
6695 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
6697 return L2_ILT_LINES(bp);
6700 void bnx2x_ilt_set_info(struct bnx2x *bp)
6702 struct ilt_client_info *ilt_client;
6703 struct bnx2x_ilt *ilt = BP_ILT(bp);
6706 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
6707 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
6710 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
6711 ilt_client->client_num = ILT_CLIENT_CDU;
6712 ilt_client->page_size = CDU_ILT_PAGE_SZ;
6713 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
6714 ilt_client->start = line;
6715 line += L2_ILT_LINES(bp);
6717 line += CNIC_ILT_LINES;
6719 ilt_client->end = line - 1;
6721 DP(BNX2X_MSG_SP, "ilt client[CDU]: start %d, end %d, psz 0x%x, "
6722 "flags 0x%x, hw psz %d\n",
6725 ilt_client->page_size,
6727 ilog2(ilt_client->page_size >> 12));
6730 if (QM_INIT(bp->qm_cid_count)) {
6731 ilt_client = &ilt->clients[ILT_CLIENT_QM];
6732 ilt_client->client_num = ILT_CLIENT_QM;
6733 ilt_client->page_size = QM_ILT_PAGE_SZ;
6734 ilt_client->flags = 0;
6735 ilt_client->start = line;
6737 /* 4 bytes for each cid */
6738 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
6741 ilt_client->end = line - 1;
6743 DP(BNX2X_MSG_SP, "ilt client[QM]: start %d, end %d, psz 0x%x, "
6744 "flags 0x%x, hw psz %d\n",
6747 ilt_client->page_size,
6749 ilog2(ilt_client->page_size >> 12));
6753 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
6755 ilt_client->client_num = ILT_CLIENT_SRC;
6756 ilt_client->page_size = SRC_ILT_PAGE_SZ;
6757 ilt_client->flags = 0;
6758 ilt_client->start = line;
6759 line += SRC_ILT_LINES;
6760 ilt_client->end = line - 1;
6762 DP(BNX2X_MSG_SP, "ilt client[SRC]: start %d, end %d, psz 0x%x, "
6763 "flags 0x%x, hw psz %d\n",
6766 ilt_client->page_size,
6768 ilog2(ilt_client->page_size >> 12));
6771 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6775 ilt_client = &ilt->clients[ILT_CLIENT_TM];
6777 ilt_client->client_num = ILT_CLIENT_TM;
6778 ilt_client->page_size = TM_ILT_PAGE_SZ;
6779 ilt_client->flags = 0;
6780 ilt_client->start = line;
6781 line += TM_ILT_LINES;
6782 ilt_client->end = line - 1;
6784 DP(BNX2X_MSG_SP, "ilt client[TM]: start %d, end %d, psz 0x%x, "
6785 "flags 0x%x, hw psz %d\n",
6788 ilt_client->page_size,
6790 ilog2(ilt_client->page_size >> 12));
6793 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
6797 int bnx2x_setup_client(struct bnx2x *bp, struct bnx2x_fastpath *fp,
6800 struct bnx2x_client_init_params params = { {0} };
6803 /* reset IGU state skip FCoE L2 queue */
6804 if (!IS_FCOE_FP(fp))
6805 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
6808 params.ramrod_params.pstate = &fp->state;
6809 params.ramrod_params.state = BNX2X_FP_STATE_OPEN;
6810 params.ramrod_params.index = fp->index;
6811 params.ramrod_params.cid = fp->cid;
6815 params.ramrod_params.flags |= CLIENT_IS_FCOE;
6820 params.ramrod_params.flags |= CLIENT_IS_LEADING_RSS;
6822 bnx2x_pf_rx_cl_prep(bp, fp, ¶ms.pause, ¶ms.rxq_params);
6824 bnx2x_pf_tx_cl_prep(bp, fp, ¶ms.txq_params);
6826 rc = bnx2x_setup_fw_client(bp, ¶ms, 1,
6827 bnx2x_sp(bp, client_init_data),
6828 bnx2x_sp_mapping(bp, client_init_data));
6832 static int bnx2x_stop_fw_client(struct bnx2x *bp,
6833 struct bnx2x_client_ramrod_params *p)
6837 int poll_flag = p->poll ? WAIT_RAMROD_POLL : 0;
6839 /* halt the connection */
6840 *p->pstate = BNX2X_FP_STATE_HALTING;
6841 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_HALT, p->cid, 0,
6844 /* Wait for completion */
6845 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_HALTED, p->index,
6846 p->pstate, poll_flag);
6847 if (rc) /* timeout */
6850 *p->pstate = BNX2X_FP_STATE_TERMINATING;
6851 bnx2x_sp_post(bp, RAMROD_CMD_ID_ETH_TERMINATE, p->cid, 0,
6853 /* Wait for completion */
6854 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_TERMINATED, p->index,
6855 p->pstate, poll_flag);
6856 if (rc) /* timeout */
6860 /* delete cfc entry */
6861 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_CFC_DEL, p->cid, 0, 0, 1);
6863 /* Wait for completion */
6864 rc = bnx2x_wait_ramrod(bp, BNX2X_FP_STATE_CLOSED, p->index,
6865 p->pstate, WAIT_RAMROD_COMMON);
6869 static int bnx2x_stop_client(struct bnx2x *bp, int index)
6871 struct bnx2x_client_ramrod_params client_stop = {0};
6872 struct bnx2x_fastpath *fp = &bp->fp[index];
6874 client_stop.index = index;
6875 client_stop.cid = fp->cid;
6876 client_stop.cl_id = fp->cl_id;
6877 client_stop.pstate = &(fp->state);
6878 client_stop.poll = 0;
6880 return bnx2x_stop_fw_client(bp, &client_stop);
6884 static void bnx2x_reset_func(struct bnx2x *bp)
6886 int port = BP_PORT(bp);
6887 int func = BP_FUNC(bp);
6889 int pfunc_offset_fp = offsetof(struct hc_sb_data, p_func) +
6891 offsetof(struct hc_status_block_data_e2, common) :
6892 offsetof(struct hc_status_block_data_e1x, common));
6893 int pfunc_offset_sp = offsetof(struct hc_sp_status_block_data, p_func);
6894 int pfid_offset = offsetof(struct pci_entity, pf_id);
6896 /* Disable the function in the FW */
6897 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
6898 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
6899 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
6900 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
6903 for_each_eth_queue(bp, i) {
6904 struct bnx2x_fastpath *fp = &bp->fp[i];
6906 BAR_CSTRORM_INTMEM +
6907 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id)
6908 + pfunc_offset_fp + pfid_offset,
6909 HC_FUNCTION_DISABLED);
6914 BAR_CSTRORM_INTMEM +
6915 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
6916 pfunc_offset_sp + pfid_offset,
6917 HC_FUNCTION_DISABLED);
6920 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
6921 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
6925 if (bp->common.int_block == INT_BLOCK_HC) {
6926 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6927 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6929 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
6930 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
6934 /* Disable Timer scan */
6935 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
6937 * Wait for at least 10ms and up to 2 second for the timers scan to
6940 for (i = 0; i < 200; i++) {
6942 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
6947 bnx2x_clear_func_ilt(bp, func);
6949 /* Timers workaround bug for E2: if this is vnic-3,
6950 * we need to set the entire ilt range for this timers.
6952 if (CHIP_IS_E2(bp) && BP_VN(bp) == 3) {
6953 struct ilt_client_info ilt_cli;
6954 /* use dummy TM client */
6955 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6957 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6958 ilt_cli.client_num = ILT_CLIENT_TM;
6960 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
6963 /* this assumes that reset_port() called before reset_func()*/
6965 bnx2x_pf_disable(bp);
6970 static void bnx2x_reset_port(struct bnx2x *bp)
6972 int port = BP_PORT(bp);
6975 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6977 /* Do not rcv packets to BRB */
6978 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
6979 /* Do not direct rcv packets that are not for MCP to the BRB */
6980 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
6981 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
6984 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
6987 /* Check for BRB port occupancy */
6988 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
6990 DP(NETIF_MSG_IFDOWN,
6991 "BRB1 is not empty %d blocks are occupied\n", val);
6993 /* TODO: Close Doorbell port? */
6996 static void bnx2x_reset_chip(struct bnx2x *bp, u32 reset_code)
6998 DP(BNX2X_MSG_MCP, "function %d reset_code %x\n",
6999 BP_ABS_FUNC(bp), reset_code);
7001 switch (reset_code) {
7002 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
7003 bnx2x_reset_port(bp);
7004 bnx2x_reset_func(bp);
7005 bnx2x_reset_common(bp);
7008 case FW_MSG_CODE_DRV_UNLOAD_PORT:
7009 bnx2x_reset_port(bp);
7010 bnx2x_reset_func(bp);
7013 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
7014 bnx2x_reset_func(bp);
7018 BNX2X_ERR("Unknown reset_code (0x%x) from MCP\n", reset_code);
7024 static inline void bnx2x_del_fcoe_eth_macs(struct bnx2x *bp)
7026 if (bp->flags & FCOE_MACS_SET) {
7028 bnx2x_set_fip_eth_mac_addr(bp, 0);
7030 bnx2x_set_all_enode_macs(bp, 0);
7032 bp->flags &= ~FCOE_MACS_SET;
7037 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
7039 int port = BP_PORT(bp);
7043 /* Wait until tx fastpath tasks complete */
7044 for_each_tx_queue(bp, i) {
7045 struct bnx2x_fastpath *fp = &bp->fp[i];
7048 while (bnx2x_has_tx_work_unload(fp)) {
7051 BNX2X_ERR("timeout waiting for queue[%d]\n",
7053 #ifdef BNX2X_STOP_ON_ERROR
7064 /* Give HW time to discard old tx messages */
7067 bnx2x_set_eth_mac(bp, 0);
7069 bnx2x_invalidate_uc_list(bp);
7072 bnx2x_invalidate_e1_mc_list(bp);
7074 bnx2x_invalidate_e1h_mc_list(bp);
7075 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
7079 bnx2x_del_fcoe_eth_macs(bp);
7082 if (unload_mode == UNLOAD_NORMAL)
7083 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7085 else if (bp->flags & NO_WOL_FLAG)
7086 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
7089 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7090 u8 *mac_addr = bp->dev->dev_addr;
7092 /* The mac address is written to entries 1-4 to
7093 preserve entry 0 which is used by the PMF */
7094 u8 entry = (BP_E1HVN(bp) + 1)*8;
7096 val = (mac_addr[0] << 8) | mac_addr[1];
7097 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
7099 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
7100 (mac_addr[4] << 8) | mac_addr[5];
7101 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
7103 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
7106 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7108 /* Close multi and leading connections
7109 Completions for ramrods are collected in a synchronous way */
7110 for_each_queue(bp, i)
7112 if (bnx2x_stop_client(bp, i))
7113 #ifdef BNX2X_STOP_ON_ERROR
7119 rc = bnx2x_func_stop(bp);
7121 BNX2X_ERR("Function stop failed!\n");
7122 #ifdef BNX2X_STOP_ON_ERROR
7128 #ifndef BNX2X_STOP_ON_ERROR
7132 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7134 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] "
7135 "%d, %d, %d\n", BP_PATH(bp),
7136 load_count[BP_PATH(bp)][0],
7137 load_count[BP_PATH(bp)][1],
7138 load_count[BP_PATH(bp)][2]);
7139 load_count[BP_PATH(bp)][0]--;
7140 load_count[BP_PATH(bp)][1 + port]--;
7141 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] "
7142 "%d, %d, %d\n", BP_PATH(bp),
7143 load_count[BP_PATH(bp)][0], load_count[BP_PATH(bp)][1],
7144 load_count[BP_PATH(bp)][2]);
7145 if (load_count[BP_PATH(bp)][0] == 0)
7146 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
7147 else if (load_count[BP_PATH(bp)][1 + port] == 0)
7148 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
7150 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
7153 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
7154 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
7155 bnx2x__link_reset(bp);
7157 /* Disable HW interrupts, NAPI */
7158 bnx2x_netif_stop(bp, 1);
7163 /* Reset the chip */
7164 bnx2x_reset_chip(bp, reset_code);
7166 /* Report UNLOAD_DONE to MCP */
7168 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7172 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
7176 DP(NETIF_MSG_HW, "Disabling \"close the gates\"\n");
7178 if (CHIP_IS_E1(bp)) {
7179 int port = BP_PORT(bp);
7180 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7181 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7183 val = REG_RD(bp, addr);
7185 REG_WR(bp, addr, val);
7186 } else if (CHIP_IS_E1H(bp)) {
7187 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
7188 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
7189 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
7190 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
7194 /* Close gates #2, #3 and #4: */
7195 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
7199 /* Gates #2 and #4a are closed/opened for "not E1" only */
7200 if (!CHIP_IS_E1(bp)) {
7202 val = REG_RD(bp, PXP_REG_HST_DISCARD_DOORBELLS);
7203 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS,
7204 close ? (val | 0x1) : (val & (~(u32)1)));
7206 val = REG_RD(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES);
7207 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES,
7208 close ? (val | 0x1) : (val & (~(u32)1)));
7212 addr = BP_PORT(bp) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
7213 val = REG_RD(bp, addr);
7214 REG_WR(bp, addr, (!close) ? (val | 0x1) : (val & (~(u32)1)));
7216 DP(NETIF_MSG_HW, "%s gates #2, #3 and #4\n",
7217 close ? "closing" : "opening");
7221 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
7223 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
7225 /* Do some magic... */
7226 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7227 *magic_val = val & SHARED_MF_CLP_MAGIC;
7228 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
7232 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
7234 * @bp: driver handle
7235 * @magic_val: old value of the `magic' bit.
7237 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
7239 /* Restore the `magic' bit value... */
7240 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
7241 MF_CFG_WR(bp, shared_mf_config.clp_mb,
7242 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
7246 * bnx2x_reset_mcp_prep - prepare for MCP reset.
7248 * @bp: driver handle
7249 * @magic_val: old value of 'magic' bit.
7251 * Takes care of CLP configurations.
7253 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
7256 u32 validity_offset;
7258 DP(NETIF_MSG_HW, "Starting\n");
7260 /* Set `magic' bit in order to save MF config */
7261 if (!CHIP_IS_E1(bp))
7262 bnx2x_clp_reset_prep(bp, magic_val);
7264 /* Get shmem offset */
7265 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7266 validity_offset = offsetof(struct shmem_region, validity_map[0]);
7268 /* Clear validity map flags */
7270 REG_WR(bp, shmem + validity_offset, 0);
7273 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
7274 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
7277 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
7279 * @bp: driver handle
7281 static inline void bnx2x_mcp_wait_one(struct bnx2x *bp)
7283 /* special handling for emulation and FPGA,
7284 wait 10 times longer */
7285 if (CHIP_REV_IS_SLOW(bp))
7286 msleep(MCP_ONE_TIMEOUT*10);
7288 msleep(MCP_ONE_TIMEOUT);
7292 * initializes bp->common.shmem_base and waits for validity signature to appear
7294 static int bnx2x_init_shmem(struct bnx2x *bp)
7300 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
7301 if (bp->common.shmem_base) {
7302 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
7303 if (val & SHR_MEM_VALIDITY_MB)
7307 bnx2x_mcp_wait_one(bp);
7309 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
7311 BNX2X_ERR("BAD MCP validity signature\n");
7316 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
7318 int rc = bnx2x_init_shmem(bp);
7320 /* Restore the `magic' bit value */
7321 if (!CHIP_IS_E1(bp))
7322 bnx2x_clp_reset_done(bp, magic_val);
7327 static void bnx2x_pxp_prep(struct bnx2x *bp)
7329 if (!CHIP_IS_E1(bp)) {
7330 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
7331 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
7332 REG_WR(bp, PXP2_REG_RQ_CFG_DONE, 0);
7338 * Reset the whole chip except for:
7340 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
7343 * - MISC (including AEU)
7347 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp)
7349 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
7352 MISC_REGISTERS_RESET_REG_1_RST_HC |
7353 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
7354 MISC_REGISTERS_RESET_REG_1_RST_PXP;
7357 MISC_REGISTERS_RESET_REG_2_RST_MDIO |
7358 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
7359 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
7360 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
7361 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
7362 MISC_REGISTERS_RESET_REG_2_RST_GRC |
7363 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
7364 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B;
7366 reset_mask1 = 0xffffffff;
7369 reset_mask2 = 0xffff;
7371 reset_mask2 = 0x1ffff;
7373 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7374 reset_mask1 & (~not_reset_mask1));
7375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7376 reset_mask2 & (~not_reset_mask2));
7381 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
7382 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, reset_mask2);
7386 static int bnx2x_process_kill(struct bnx2x *bp)
7390 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
7393 /* Empty the Tetris buffer, wait for 1s */
7395 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
7396 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
7397 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
7398 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
7399 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
7400 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
7401 ((port_is_idle_0 & 0x1) == 0x1) &&
7402 ((port_is_idle_1 & 0x1) == 0x1) &&
7403 (pgl_exp_rom2 == 0xffffffff))
7406 } while (cnt-- > 0);
7409 DP(NETIF_MSG_HW, "Tetris buffer didn't get empty or there"
7411 " outstanding read requests after 1s!\n");
7412 DP(NETIF_MSG_HW, "sr_cnt=0x%08x, blk_cnt=0x%08x,"
7413 " port_is_idle_0=0x%08x,"
7414 " port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
7415 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
7422 /* Close gates #2, #3 and #4 */
7423 bnx2x_set_234_gates(bp, true);
7425 /* TBD: Indicate that "process kill" is in progress to MCP */
7427 /* Clear "unprepared" bit */
7428 REG_WR(bp, MISC_REG_UNPREPARED, 0);
7431 /* Make sure all is written to the chip before the reset */
7434 /* Wait for 1ms to empty GLUE and PCI-E core queues,
7435 * PSWHST, GRC and PSWRD Tetris buffer.
7439 /* Prepare to chip reset: */
7441 bnx2x_reset_mcp_prep(bp, &val);
7447 /* reset the chip */
7448 bnx2x_process_kill_chip_reset(bp);
7451 /* Recover after reset: */
7453 if (bnx2x_reset_mcp_comp(bp, val))
7459 /* Open the gates #2, #3 and #4 */
7460 bnx2x_set_234_gates(bp, false);
7462 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
7463 * reset state, re-enable attentions. */
7468 static int bnx2x_leader_reset(struct bnx2x *bp)
7471 /* Try to recover after the failure */
7472 if (bnx2x_process_kill(bp)) {
7473 printk(KERN_ERR "%s: Something bad had happen! Aii!\n",
7476 goto exit_leader_reset;
7479 /* Clear "reset is in progress" bit and update the driver state */
7480 bnx2x_set_reset_done(bp);
7481 bp->recovery_state = BNX2X_RECOVERY_DONE;
7485 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESERVED_08);
7490 /* Assumption: runs under rtnl lock. This together with the fact
7491 * that it's called only from bnx2x_reset_task() ensure that it
7492 * will never be called when netif_running(bp->dev) is false.
7494 static void bnx2x_parity_recover(struct bnx2x *bp)
7496 DP(NETIF_MSG_HW, "Handling parity\n");
7498 switch (bp->recovery_state) {
7499 case BNX2X_RECOVERY_INIT:
7500 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
7501 /* Try to get a LEADER_LOCK HW lock */
7502 if (bnx2x_trylock_hw_lock(bp,
7503 HW_LOCK_RESOURCE_RESERVED_08))
7506 /* Stop the driver */
7507 /* If interface has been removed - break */
7508 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
7511 bp->recovery_state = BNX2X_RECOVERY_WAIT;
7512 /* Ensure "is_leader" and "recovery_state"
7513 * update values are seen on other CPUs
7518 case BNX2X_RECOVERY_WAIT:
7519 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
7520 if (bp->is_leader) {
7521 u32 load_counter = bnx2x_get_load_cnt(bp);
7523 /* Wait until all other functions get
7526 schedule_delayed_work(&bp->reset_task,
7530 /* If all other functions got down -
7531 * try to bring the chip back to
7532 * normal. In any case it's an exit
7533 * point for a leader.
7535 if (bnx2x_leader_reset(bp) ||
7536 bnx2x_nic_load(bp, LOAD_NORMAL)) {
7537 printk(KERN_ERR"%s: Recovery "
7538 "has failed. Power cycle is "
7539 "needed.\n", bp->dev->name);
7540 /* Disconnect this device */
7541 netif_device_detach(bp->dev);
7542 /* Block ifup for all function
7543 * of this ASIC until
7544 * "process kill" or power
7547 bnx2x_set_reset_in_progress(bp);
7548 /* Shut down the power */
7549 bnx2x_set_power_state(bp,
7556 } else { /* non-leader */
7557 if (!bnx2x_reset_is_done(bp)) {
7558 /* Try to get a LEADER_LOCK HW lock as
7559 * long as a former leader may have
7560 * been unloaded by the user or
7561 * released a leadership by another
7564 if (bnx2x_trylock_hw_lock(bp,
7565 HW_LOCK_RESOURCE_RESERVED_08)) {
7566 /* I'm a leader now! Restart a
7573 schedule_delayed_work(&bp->reset_task,
7577 } else { /* A leader has completed
7578 * the "process kill". It's an exit
7579 * point for a non-leader.
7581 bnx2x_nic_load(bp, LOAD_NORMAL);
7582 bp->recovery_state =
7583 BNX2X_RECOVERY_DONE;
7594 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
7595 * scheduled on a general queue in order to prevent a dead lock.
7597 static void bnx2x_reset_task(struct work_struct *work)
7599 struct bnx2x *bp = container_of(work, struct bnx2x, reset_task.work);
7601 #ifdef BNX2X_STOP_ON_ERROR
7602 BNX2X_ERR("reset task called but STOP_ON_ERROR defined"
7603 " so reset not done to allow debug dump,\n"
7604 KERN_ERR " you will need to reboot when done\n");
7610 if (!netif_running(bp->dev))
7611 goto reset_task_exit;
7613 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE))
7614 bnx2x_parity_recover(bp);
7616 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
7617 bnx2x_nic_load(bp, LOAD_NORMAL);
7624 /* end of nic load/unload */
7627 * Init service functions
7630 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
7632 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
7633 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
7634 return base + (BP_ABS_FUNC(bp)) * stride;
7637 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
7639 u32 reg = bnx2x_get_pretend_reg(bp);
7641 /* Flush all outstanding writes */
7644 /* Pretend to be function 0 */
7646 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
7648 /* From now we are in the "like-E1" mode */
7649 bnx2x_int_disable(bp);
7651 /* Flush all outstanding writes */
7654 /* Restore the original function */
7655 REG_WR(bp, reg, BP_ABS_FUNC(bp));
7659 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
7662 bnx2x_int_disable(bp);
7664 bnx2x_undi_int_disable_e1h(bp);
7667 static void __devinit bnx2x_undi_unload(struct bnx2x *bp)
7671 /* Check if there is any driver already loaded */
7672 val = REG_RD(bp, MISC_REG_UNPREPARED);
7674 /* Check if it is the UNDI driver
7675 * UNDI driver initializes CID offset for normal bell to 0x7
7677 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7678 val = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
7680 u32 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7681 /* save our pf_num */
7682 int orig_pf_num = bp->pf_num;
7686 /* clear the UNDI indication */
7687 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
7689 BNX2X_DEV_INFO("UNDI is active! reset device\n");
7691 /* try unload UNDI on port 0 */
7694 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7695 DRV_MSG_SEQ_NUMBER_MASK);
7696 reset_code = bnx2x_fw_command(bp, reset_code, 0);
7698 /* if UNDI is loaded on the other port */
7699 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
7701 /* send "DONE" for previous unload */
7702 bnx2x_fw_command(bp,
7703 DRV_MSG_CODE_UNLOAD_DONE, 0);
7705 /* unload UNDI on port 1 */
7708 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7709 DRV_MSG_SEQ_NUMBER_MASK);
7710 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
7712 bnx2x_fw_command(bp, reset_code, 0);
7715 /* now it's safe to release the lock */
7716 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7718 bnx2x_undi_int_disable(bp);
7720 /* close input traffic and wait for it */
7721 /* Do not rcv packets to BRB */
7723 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_DRV_MASK :
7724 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
7725 /* Do not direct rcv packets that are not for MCP to
7728 (BP_PORT(bp) ? NIG_REG_LLH1_BRB1_NOT_MCP :
7729 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
7732 (BP_PORT(bp) ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7733 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
7736 /* save NIG port swap info */
7737 swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7738 swap_en = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7741 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7744 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
7746 /* take the NIG out of reset and restore swap values */
7748 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7749 MISC_REGISTERS_RESET_REG_1_RST_NIG);
7750 REG_WR(bp, NIG_REG_PORT_SWAP, swap_val);
7751 REG_WR(bp, NIG_REG_STRAP_OVERRIDE, swap_en);
7753 /* send unload done to the MCP */
7754 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
7756 /* restore our func and fw_seq */
7757 bp->pf_num = orig_pf_num;
7759 (SHMEM_RD(bp, func_mb[bp->pf_num].drv_mb_header) &
7760 DRV_MSG_SEQ_NUMBER_MASK);
7762 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_UNDI);
7766 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
7768 u32 val, val2, val3, val4, id;
7771 /* Get the chip revision id and number. */
7772 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
7773 val = REG_RD(bp, MISC_REG_CHIP_NUM);
7774 id = ((val & 0xffff) << 16);
7775 val = REG_RD(bp, MISC_REG_CHIP_REV);
7776 id |= ((val & 0xf) << 12);
7777 val = REG_RD(bp, MISC_REG_CHIP_METAL);
7778 id |= ((val & 0xff) << 4);
7779 val = REG_RD(bp, MISC_REG_BOND_ID);
7781 bp->common.chip_id = id;
7783 /* Set doorbell size */
7784 bp->db_size = (1 << BNX2X_DB_SHIFT);
7786 if (CHIP_IS_E2(bp)) {
7787 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
7789 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
7791 val = (val >> 1) & 1;
7792 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
7794 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
7797 if (CHIP_MODE_IS_4_PORT(bp))
7798 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
7800 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
7802 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
7803 bp->pfid = bp->pf_num; /* 0..7 */
7807 * set base FW non-default (fast path) status block id, this value is
7808 * used to initialize the fw_sb_id saved on the fp/queue structure to
7809 * determine the id used by the FW.
7811 if (CHIP_IS_E1x(bp))
7812 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x;
7814 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E2;
7816 bp->link_params.chip_id = bp->common.chip_id;
7817 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
7819 val = (REG_RD(bp, 0x2874) & 0x55);
7820 if ((bp->common.chip_id & 0x1) ||
7821 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
7822 bp->flags |= ONE_PORT_FLAG;
7823 BNX2X_DEV_INFO("single port device\n");
7826 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
7827 bp->common.flash_size = (NVRAM_1MB_SIZE <<
7828 (val & MCPR_NVM_CFG4_FLASH_SIZE));
7829 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
7830 bp->common.flash_size, bp->common.flash_size);
7832 bnx2x_init_shmem(bp);
7834 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
7835 MISC_REG_GENERIC_CR_1 :
7836 MISC_REG_GENERIC_CR_0));
7838 bp->link_params.shmem_base = bp->common.shmem_base;
7839 bp->link_params.shmem2_base = bp->common.shmem2_base;
7840 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
7841 bp->common.shmem_base, bp->common.shmem2_base);
7843 if (!bp->common.shmem_base) {
7844 BNX2X_DEV_INFO("MCP not active\n");
7845 bp->flags |= NO_MCP_FLAG;
7849 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
7850 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
7852 bp->link_params.hw_led_mode = ((bp->common.hw_config &
7853 SHARED_HW_CFG_LED_MODE_MASK) >>
7854 SHARED_HW_CFG_LED_MODE_SHIFT);
7856 bp->link_params.feature_config_flags = 0;
7857 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
7858 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
7859 bp->link_params.feature_config_flags |=
7860 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7862 bp->link_params.feature_config_flags &=
7863 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
7865 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
7866 bp->common.bc_ver = val;
7867 BNX2X_DEV_INFO("bc_ver %X\n", val);
7868 if (val < BNX2X_BC_VER) {
7869 /* for now only warn
7870 * later we might need to enforce this */
7871 BNX2X_ERR("This driver needs bc_ver %X but found %X, "
7872 "please upgrade BC\n", BNX2X_BC_VER, val);
7874 bp->link_params.feature_config_flags |=
7875 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
7876 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
7878 bp->link_params.feature_config_flags |=
7879 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
7880 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
7882 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
7883 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
7885 BNX2X_DEV_INFO("%sWoL capable\n",
7886 (bp->flags & NO_WOL_FLAG) ? "not " : "");
7888 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
7889 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
7890 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
7891 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
7893 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
7894 val, val2, val3, val4);
7897 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
7898 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
7900 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
7902 int pfid = BP_FUNC(bp);
7903 int vn = BP_E1HVN(bp);
7908 bp->igu_base_sb = 0xff;
7910 if (CHIP_INT_MODE_IS_BC(bp)) {
7911 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
7912 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7914 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
7917 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
7918 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
7923 /* IGU in normal mode - read CAM */
7924 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
7926 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
7927 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
7930 if ((fid & IGU_FID_ENCODE_IS_PF)) {
7931 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
7933 if (IGU_VEC(val) == 0)
7934 /* default status block */
7935 bp->igu_dsb_id = igu_sb_id;
7937 if (bp->igu_base_sb == 0xff)
7938 bp->igu_base_sb = igu_sb_id;
7943 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
7944 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
7945 if (bp->igu_sb_cnt == 0)
7946 BNX2X_ERR("CAM configuration error\n");
7949 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
7952 int cfg_size = 0, idx, port = BP_PORT(bp);
7954 /* Aggregation of supported attributes of all external phys */
7955 bp->port.supported[0] = 0;
7956 bp->port.supported[1] = 0;
7957 switch (bp->link_params.num_phys) {
7959 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
7963 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
7967 if (bp->link_params.multi_phy_config &
7968 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
7969 bp->port.supported[1] =
7970 bp->link_params.phy[EXT_PHY1].supported;
7971 bp->port.supported[0] =
7972 bp->link_params.phy[EXT_PHY2].supported;
7974 bp->port.supported[0] =
7975 bp->link_params.phy[EXT_PHY1].supported;
7976 bp->port.supported[1] =
7977 bp->link_params.phy[EXT_PHY2].supported;
7983 if (!(bp->port.supported[0] || bp->port.supported[1])) {
7984 BNX2X_ERR("NVRAM config error. BAD phy config."
7985 "PHY1 config 0x%x, PHY2 config 0x%x\n",
7987 dev_info.port_hw_config[port].external_phy_config),
7989 dev_info.port_hw_config[port].external_phy_config2));
7993 switch (switch_cfg) {
7995 bp->port.phy_addr = REG_RD(bp, NIG_REG_SERDES0_CTRL_PHY_ADDR +
7997 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8000 case SWITCH_CFG_10G:
8001 bp->port.phy_addr = REG_RD(bp, NIG_REG_XGXS0_CTRL_PHY_ADDR +
8003 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
8007 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
8008 bp->port.link_config[0]);
8011 /* mask what we support according to speed_cap_mask per configuration */
8012 for (idx = 0; idx < cfg_size; idx++) {
8013 if (!(bp->link_params.speed_cap_mask[idx] &
8014 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
8015 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
8017 if (!(bp->link_params.speed_cap_mask[idx] &
8018 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
8019 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
8021 if (!(bp->link_params.speed_cap_mask[idx] &
8022 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
8023 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
8025 if (!(bp->link_params.speed_cap_mask[idx] &
8026 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
8027 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
8029 if (!(bp->link_params.speed_cap_mask[idx] &
8030 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
8031 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
8032 SUPPORTED_1000baseT_Full);
8034 if (!(bp->link_params.speed_cap_mask[idx] &
8035 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8036 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
8038 if (!(bp->link_params.speed_cap_mask[idx] &
8039 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
8040 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
8044 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
8045 bp->port.supported[1]);
8048 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
8050 u32 link_config, idx, cfg_size = 0;
8051 bp->port.advertising[0] = 0;
8052 bp->port.advertising[1] = 0;
8053 switch (bp->link_params.num_phys) {
8062 for (idx = 0; idx < cfg_size; idx++) {
8063 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
8064 link_config = bp->port.link_config[idx];
8065 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
8066 case PORT_FEATURE_LINK_SPEED_AUTO:
8067 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
8068 bp->link_params.req_line_speed[idx] =
8070 bp->port.advertising[idx] |=
8071 bp->port.supported[idx];
8073 /* force 10G, no AN */
8074 bp->link_params.req_line_speed[idx] =
8076 bp->port.advertising[idx] |=
8077 (ADVERTISED_10000baseT_Full |
8083 case PORT_FEATURE_LINK_SPEED_10M_FULL:
8084 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
8085 bp->link_params.req_line_speed[idx] =
8087 bp->port.advertising[idx] |=
8088 (ADVERTISED_10baseT_Full |
8091 BNX2X_ERROR("NVRAM config error. "
8092 "Invalid link_config 0x%x"
8093 " speed_cap_mask 0x%x\n",
8095 bp->link_params.speed_cap_mask[idx]);
8100 case PORT_FEATURE_LINK_SPEED_10M_HALF:
8101 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
8102 bp->link_params.req_line_speed[idx] =
8104 bp->link_params.req_duplex[idx] =
8106 bp->port.advertising[idx] |=
8107 (ADVERTISED_10baseT_Half |
8110 BNX2X_ERROR("NVRAM config error. "
8111 "Invalid link_config 0x%x"
8112 " speed_cap_mask 0x%x\n",
8114 bp->link_params.speed_cap_mask[idx]);
8119 case PORT_FEATURE_LINK_SPEED_100M_FULL:
8120 if (bp->port.supported[idx] &
8121 SUPPORTED_100baseT_Full) {
8122 bp->link_params.req_line_speed[idx] =
8124 bp->port.advertising[idx] |=
8125 (ADVERTISED_100baseT_Full |
8128 BNX2X_ERROR("NVRAM config error. "
8129 "Invalid link_config 0x%x"
8130 " speed_cap_mask 0x%x\n",
8132 bp->link_params.speed_cap_mask[idx]);
8137 case PORT_FEATURE_LINK_SPEED_100M_HALF:
8138 if (bp->port.supported[idx] &
8139 SUPPORTED_100baseT_Half) {
8140 bp->link_params.req_line_speed[idx] =
8142 bp->link_params.req_duplex[idx] =
8144 bp->port.advertising[idx] |=
8145 (ADVERTISED_100baseT_Half |
8148 BNX2X_ERROR("NVRAM config error. "
8149 "Invalid link_config 0x%x"
8150 " speed_cap_mask 0x%x\n",
8152 bp->link_params.speed_cap_mask[idx]);
8157 case PORT_FEATURE_LINK_SPEED_1G:
8158 if (bp->port.supported[idx] &
8159 SUPPORTED_1000baseT_Full) {
8160 bp->link_params.req_line_speed[idx] =
8162 bp->port.advertising[idx] |=
8163 (ADVERTISED_1000baseT_Full |
8166 BNX2X_ERROR("NVRAM config error. "
8167 "Invalid link_config 0x%x"
8168 " speed_cap_mask 0x%x\n",
8170 bp->link_params.speed_cap_mask[idx]);
8175 case PORT_FEATURE_LINK_SPEED_2_5G:
8176 if (bp->port.supported[idx] &
8177 SUPPORTED_2500baseX_Full) {
8178 bp->link_params.req_line_speed[idx] =
8180 bp->port.advertising[idx] |=
8181 (ADVERTISED_2500baseX_Full |
8184 BNX2X_ERROR("NVRAM config error. "
8185 "Invalid link_config 0x%x"
8186 " speed_cap_mask 0x%x\n",
8188 bp->link_params.speed_cap_mask[idx]);
8193 case PORT_FEATURE_LINK_SPEED_10G_CX4:
8194 case PORT_FEATURE_LINK_SPEED_10G_KX4:
8195 case PORT_FEATURE_LINK_SPEED_10G_KR:
8196 if (bp->port.supported[idx] &
8197 SUPPORTED_10000baseT_Full) {
8198 bp->link_params.req_line_speed[idx] =
8200 bp->port.advertising[idx] |=
8201 (ADVERTISED_10000baseT_Full |
8204 BNX2X_ERROR("NVRAM config error. "
8205 "Invalid link_config 0x%x"
8206 " speed_cap_mask 0x%x\n",
8208 bp->link_params.speed_cap_mask[idx]);
8214 BNX2X_ERROR("NVRAM config error. "
8215 "BAD link speed link_config 0x%x\n",
8217 bp->link_params.req_line_speed[idx] =
8219 bp->port.advertising[idx] =
8220 bp->port.supported[idx];
8224 bp->link_params.req_flow_ctrl[idx] = (link_config &
8225 PORT_FEATURE_FLOW_CONTROL_MASK);
8226 if ((bp->link_params.req_flow_ctrl[idx] ==
8227 BNX2X_FLOW_CTRL_AUTO) &&
8228 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
8229 bp->link_params.req_flow_ctrl[idx] =
8230 BNX2X_FLOW_CTRL_NONE;
8233 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl"
8234 " 0x%x advertising 0x%x\n",
8235 bp->link_params.req_line_speed[idx],
8236 bp->link_params.req_duplex[idx],
8237 bp->link_params.req_flow_ctrl[idx],
8238 bp->port.advertising[idx]);
8242 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
8244 mac_hi = cpu_to_be16(mac_hi);
8245 mac_lo = cpu_to_be32(mac_lo);
8246 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
8247 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
8250 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
8252 int port = BP_PORT(bp);
8254 u32 ext_phy_type, ext_phy_config;
8256 bp->link_params.bp = bp;
8257 bp->link_params.port = port;
8259 bp->link_params.lane_config =
8260 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
8262 bp->link_params.speed_cap_mask[0] =
8264 dev_info.port_hw_config[port].speed_capability_mask);
8265 bp->link_params.speed_cap_mask[1] =
8267 dev_info.port_hw_config[port].speed_capability_mask2);
8268 bp->port.link_config[0] =
8269 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
8271 bp->port.link_config[1] =
8272 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
8274 bp->link_params.multi_phy_config =
8275 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
8276 /* If the device is capable of WoL, set the default state according
8279 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
8280 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
8281 (config & PORT_FEATURE_WOL_ENABLED));
8283 BNX2X_DEV_INFO("lane_config 0x%08x "
8284 "speed_cap_mask0 0x%08x link_config0 0x%08x\n",
8285 bp->link_params.lane_config,
8286 bp->link_params.speed_cap_mask[0],
8287 bp->port.link_config[0]);
8289 bp->link_params.switch_cfg = (bp->port.link_config[0] &
8290 PORT_FEATURE_CONNECTED_SWITCH_MASK);
8291 bnx2x_phy_probe(&bp->link_params);
8292 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
8294 bnx2x_link_settings_requested(bp);
8297 * If connected directly, work with the internal PHY, otherwise, work
8298 * with the external PHY
8302 dev_info.port_hw_config[port].external_phy_config);
8303 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
8304 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8305 bp->mdio.prtad = bp->port.phy_addr;
8307 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
8308 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
8310 XGXS_EXT_PHY_ADDR(ext_phy_config);
8313 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
8314 * In MF mode, it is set to cover self test cases
8317 bp->port.need_hw_lock = 1;
8319 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
8320 bp->common.shmem_base,
8321 bp->common.shmem2_base);
8325 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
8327 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8328 drv_lic_key[BP_PORT(bp)].max_iscsi_conn);
8329 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
8330 drv_lic_key[BP_PORT(bp)].max_fcoe_conn);
8332 /* Get the number of maximum allowed iSCSI and FCoE connections */
8333 bp->cnic_eth_dev.max_iscsi_conn =
8334 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
8335 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
8337 bp->cnic_eth_dev.max_fcoe_conn =
8338 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
8339 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
8341 BNX2X_DEV_INFO("max_iscsi_conn 0x%x max_fcoe_conn 0x%x\n",
8342 bp->cnic_eth_dev.max_iscsi_conn,
8343 bp->cnic_eth_dev.max_fcoe_conn);
8345 /* If mamimum allowed number of connections is zero -
8346 * disable the feature.
8348 if (!bp->cnic_eth_dev.max_iscsi_conn)
8349 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8351 if (!bp->cnic_eth_dev.max_fcoe_conn)
8352 bp->flags |= NO_FCOE_FLAG;
8356 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
8359 int func = BP_ABS_FUNC(bp);
8360 int port = BP_PORT(bp);
8362 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
8363 u8 *fip_mac = bp->fip_mac;
8367 BNX2X_ERROR("warning: random MAC workaround active\n");
8368 random_ether_addr(bp->dev->dev_addr);
8369 } else if (IS_MF(bp)) {
8370 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
8371 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
8372 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
8373 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
8374 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8377 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
8378 * FCoE MAC then the appropriate feature should be disabled.
8381 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
8382 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
8383 val2 = MF_CFG_RD(bp, func_ext_config[func].
8384 iscsi_mac_addr_upper);
8385 val = MF_CFG_RD(bp, func_ext_config[func].
8386 iscsi_mac_addr_lower);
8387 BNX2X_DEV_INFO("Read iSCSI MAC: "
8388 "0x%x:0x%04x\n", val2, val);
8389 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8391 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
8393 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
8394 val2 = MF_CFG_RD(bp, func_ext_config[func].
8395 fcoe_mac_addr_upper);
8396 val = MF_CFG_RD(bp, func_ext_config[func].
8397 fcoe_mac_addr_lower);
8398 BNX2X_DEV_INFO("Read FCoE MAC to "
8399 "0x%x:0x%04x\n", val2, val);
8400 bnx2x_set_mac_buf(fip_mac, val, val2);
8403 bp->flags |= NO_FCOE_FLAG;
8407 /* in SF read MACs from port configuration */
8408 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
8409 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
8410 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
8413 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
8415 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
8417 bnx2x_set_mac_buf(iscsi_mac, val, val2);
8421 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
8422 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
8425 /* Set the FCoE MAC in modes other then MF_SI */
8426 if (!CHIP_IS_E1x(bp)) {
8428 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
8429 else if (!IS_MF(bp))
8430 memcpy(fip_mac, iscsi_mac, ETH_ALEN);
8433 /* Disable iSCSI if MAC configuration is
8436 if (!is_valid_ether_addr(iscsi_mac)) {
8437 bp->flags |= NO_ISCSI_FLAG;
8438 memset(iscsi_mac, 0, ETH_ALEN);
8441 /* Disable FCoE if MAC configuration is
8444 if (!is_valid_ether_addr(fip_mac)) {
8445 bp->flags |= NO_FCOE_FLAG;
8446 memset(bp->fip_mac, 0, ETH_ALEN);
8451 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
8453 int /*abs*/func = BP_ABS_FUNC(bp);
8458 bnx2x_get_common_hwinfo(bp);
8460 if (CHIP_IS_E1x(bp)) {
8461 bp->common.int_block = INT_BLOCK_HC;
8463 bp->igu_dsb_id = DEF_SB_IGU_ID;
8464 bp->igu_base_sb = 0;
8465 bp->igu_sb_cnt = min_t(u8, FP_SB_MAX_E1x,
8466 NUM_IGU_SB_REQUIRED(bp->l2_cid_count));
8468 bp->common.int_block = INT_BLOCK_IGU;
8469 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8470 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
8471 DP(NETIF_MSG_PROBE, "IGU Backward Compatible Mode\n");
8472 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
8474 DP(NETIF_MSG_PROBE, "IGU Normal Mode\n");
8476 bnx2x_get_igu_cam_info(bp);
8479 DP(NETIF_MSG_PROBE, "igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n",
8480 bp->igu_dsb_id, bp->igu_base_sb, bp->igu_sb_cnt);
8483 * Initialize MF configuration
8490 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
8492 "shmem2base 0x%x, size %d, mfcfg offset %d\n",
8493 bp->common.shmem2_base, SHMEM2_RD(bp, size),
8494 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
8495 if (SHMEM2_HAS(bp, mf_cfg_addr))
8496 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
8498 bp->common.mf_cfg_base = bp->common.shmem_base +
8499 offsetof(struct shmem_region, func_mb) +
8500 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
8502 * get mf configuration:
8503 * 1. existence of MF configuration
8504 * 2. MAC address must be legal (check only upper bytes)
8505 * for Switch-Independent mode;
8506 * OVLAN must be legal for Switch-Dependent mode
8507 * 3. SF_MODE configures specific MF mode
8509 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
8510 /* get mf configuration */
8512 dev_info.shared_feature_config.config);
8513 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
8516 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
8517 val = MF_CFG_RD(bp, func_mf_config[func].
8519 /* check for legal mac (upper bytes)*/
8520 if (val != 0xffff) {
8521 bp->mf_mode = MULTI_FUNCTION_SI;
8522 bp->mf_config[vn] = MF_CFG_RD(bp,
8523 func_mf_config[func].config);
8525 DP(NETIF_MSG_PROBE, "illegal MAC "
8526 "address for SI\n");
8528 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
8529 /* get OV configuration */
8531 func_mf_config[FUNC_0].e1hov_tag);
8532 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
8534 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8535 bp->mf_mode = MULTI_FUNCTION_SD;
8536 bp->mf_config[vn] = MF_CFG_RD(bp,
8537 func_mf_config[func].config);
8539 DP(NETIF_MSG_PROBE, "illegal OV for "
8543 /* Unknown configuration: reset mf_config */
8544 bp->mf_config[vn] = 0;
8545 DP(NETIF_MSG_PROBE, "Unknown MF mode 0x%x\n",
8550 BNX2X_DEV_INFO("%s function mode\n",
8551 IS_MF(bp) ? "multi" : "single");
8553 switch (bp->mf_mode) {
8554 case MULTI_FUNCTION_SD:
8555 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
8556 FUNC_MF_CFG_E1HOV_TAG_MASK;
8557 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
8559 BNX2X_DEV_INFO("MF OV for func %d is %d"
8560 " (0x%04x)\n", func,
8561 bp->mf_ov, bp->mf_ov);
8563 BNX2X_ERR("No valid MF OV for func %d,"
8564 " aborting\n", func);
8568 case MULTI_FUNCTION_SI:
8569 BNX2X_DEV_INFO("func %d is in MF "
8570 "switch-independent mode\n", func);
8574 BNX2X_ERR("VN %d in single function mode,"
8583 /* adjust igu_sb_cnt to MF for E1x */
8584 if (CHIP_IS_E1x(bp) && IS_MF(bp))
8585 bp->igu_sb_cnt /= E1HVN_MAX;
8588 * adjust E2 sb count: to be removed when FW will support
8589 * more then 16 L2 clients
8591 #define MAX_L2_CLIENTS 16
8593 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt,
8594 MAX_L2_CLIENTS / (IS_MF(bp) ? 4 : 1));
8596 if (!BP_NOMCP(bp)) {
8597 bnx2x_get_port_hwinfo(bp);
8600 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
8601 DRV_MSG_SEQ_NUMBER_MASK);
8602 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
8605 /* Get MAC addresses */
8606 bnx2x_get_mac_hwinfo(bp);
8609 bnx2x_get_cnic_info(bp);
8615 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
8617 int cnt, i, block_end, rodi;
8618 char vpd_data[BNX2X_VPD_LEN+1];
8619 char str_id_reg[VENDOR_ID_LEN+1];
8620 char str_id_cap[VENDOR_ID_LEN+1];
8623 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_data);
8624 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
8626 if (cnt < BNX2X_VPD_LEN)
8629 i = pci_vpd_find_tag(vpd_data, 0, BNX2X_VPD_LEN,
8630 PCI_VPD_LRDT_RO_DATA);
8635 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
8636 pci_vpd_lrdt_size(&vpd_data[i]);
8638 i += PCI_VPD_LRDT_TAG_SIZE;
8640 if (block_end > BNX2X_VPD_LEN)
8643 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8644 PCI_VPD_RO_KEYWORD_MFR_ID);
8648 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8650 if (len != VENDOR_ID_LEN)
8653 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8655 /* vendor specific info */
8656 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
8657 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
8658 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
8659 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
8661 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
8662 PCI_VPD_RO_KEYWORD_VENDOR0);
8664 len = pci_vpd_info_field_size(&vpd_data[rodi]);
8666 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
8668 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
8669 memcpy(bp->fw_ver, &vpd_data[rodi], len);
8670 bp->fw_ver[len] = ' ';
8679 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
8685 /* Disable interrupt handling until HW is initialized */
8686 atomic_set(&bp->intr_sem, 1);
8687 smp_wmb(); /* Ensure that bp->intr_sem update is SMP-safe */
8689 mutex_init(&bp->port.phy_mutex);
8690 mutex_init(&bp->fw_mb_mutex);
8691 spin_lock_init(&bp->stats_lock);
8693 mutex_init(&bp->cnic_mutex);
8696 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
8697 INIT_DELAYED_WORK(&bp->reset_task, bnx2x_reset_task);
8699 rc = bnx2x_get_hwinfo(bp);
8702 rc = bnx2x_alloc_mem_bp(bp);
8704 bnx2x_read_fwinfo(bp);
8708 /* need to reset chip if undi was active */
8710 bnx2x_undi_unload(bp);
8712 if (CHIP_REV_IS_FPGA(bp))
8713 dev_err(&bp->pdev->dev, "FPGA detected\n");
8715 if (BP_NOMCP(bp) && (func == 0))
8716 dev_err(&bp->pdev->dev, "MCP disabled, "
8717 "must load devices in order!\n");
8719 bp->multi_mode = multi_mode;
8720 bp->int_mode = int_mode;
8724 bp->flags &= ~TPA_ENABLE_FLAG;
8725 bp->dev->features &= ~NETIF_F_LRO;
8727 bp->flags |= TPA_ENABLE_FLAG;
8728 bp->dev->features |= NETIF_F_LRO;
8730 bp->disable_tpa = disable_tpa;
8733 bp->dropless_fc = 0;
8735 bp->dropless_fc = dropless_fc;
8739 bp->tx_ring_size = MAX_TX_AVAIL;
8741 /* make sure that the numbers are in the right granularity */
8742 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
8743 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
8745 timer_interval = (CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ);
8746 bp->current_interval = (poll ? poll : timer_interval);
8748 init_timer(&bp->timer);
8749 bp->timer.expires = jiffies + bp->current_interval;
8750 bp->timer.data = (unsigned long) bp;
8751 bp->timer.function = bnx2x_timer;
8753 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
8754 bnx2x_dcbx_init_params(bp);
8760 /****************************************************************************
8761 * General service functions
8762 ****************************************************************************/
8764 /* called with rtnl_lock */
8765 static int bnx2x_open(struct net_device *dev)
8767 struct bnx2x *bp = netdev_priv(dev);
8769 netif_carrier_off(dev);
8771 bnx2x_set_power_state(bp, PCI_D0);
8773 if (!bnx2x_reset_is_done(bp)) {
8775 /* Reset MCP mail box sequence if there is on going
8780 /* If it's the first function to load and reset done
8781 * is still not cleared it may mean that. We don't
8782 * check the attention state here because it may have
8783 * already been cleared by a "common" reset but we
8784 * shell proceed with "process kill" anyway.
8786 if ((bnx2x_get_load_cnt(bp) == 0) &&
8787 bnx2x_trylock_hw_lock(bp,
8788 HW_LOCK_RESOURCE_RESERVED_08) &&
8789 (!bnx2x_leader_reset(bp))) {
8790 DP(NETIF_MSG_HW, "Recovered in open\n");
8794 bnx2x_set_power_state(bp, PCI_D3hot);
8796 printk(KERN_ERR"%s: Recovery flow hasn't been properly"
8797 " completed yet. Try again later. If u still see this"
8798 " message after a few retries then power cycle is"
8799 " required.\n", bp->dev->name);
8805 bp->recovery_state = BNX2X_RECOVERY_DONE;
8807 return bnx2x_nic_load(bp, LOAD_OPEN);
8810 /* called with rtnl_lock */
8811 static int bnx2x_close(struct net_device *dev)
8813 struct bnx2x *bp = netdev_priv(dev);
8815 /* Unload the driver, release IRQs */
8816 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
8817 bnx2x_set_power_state(bp, PCI_D3hot);
8822 #define E1_MAX_UC_LIST 29
8823 #define E1H_MAX_UC_LIST 30
8824 #define E2_MAX_UC_LIST 14
8825 static inline u8 bnx2x_max_uc_list(struct bnx2x *bp)
8828 return E1_MAX_UC_LIST;
8829 else if (CHIP_IS_E1H(bp))
8830 return E1H_MAX_UC_LIST;
8832 return E2_MAX_UC_LIST;
8836 static inline u8 bnx2x_uc_list_cam_offset(struct bnx2x *bp)
8839 /* CAM Entries for Port0:
8842 * 2 - iSCSI L2 ring ETH MAC
8845 * Port1 entries are allocated the same way starting from
8848 return 3 + 32 * BP_PORT(bp);
8849 else if (CHIP_IS_E1H(bp)) {
8851 * 0-7 - prim ETH MAC for each function
8852 * 8-15 - iSCSI L2 ring ETH MAC for each function
8853 * 16 till 255 UC MAC lists for each function
8855 * Remark: There is no FCoE support for E1H, thus FCoE related
8856 * MACs are not considered.
8858 return E1H_FUNC_MAX * (CAM_ISCSI_ETH_LINE + 1) +
8859 bnx2x_max_uc_list(bp) * BP_FUNC(bp);
8861 /* CAM Entries (there is a separate CAM per engine):
8862 * 0-4 - prim ETH MAC for each function
8863 * 4-7 - iSCSI L2 ring ETH MAC for each function
8864 * 8-11 - FIP ucast L2 MAC for each function
8865 * 12-15 - ALL_ENODE_MACS mcast MAC for each function
8866 * 16 till 71 UC MAC lists for each function
8869 (CHIP_MODE_IS_4_PORT(bp) ? BP_FUNC(bp) : BP_VN(bp));
8871 return E2_FUNC_MAX * (CAM_MAX_PF_LINE + 1) +
8872 bnx2x_max_uc_list(bp) * func_idx;
8876 /* set uc list, do not wait as wait implies sleep and
8877 * set_rx_mode can be invoked from non-sleepable context.
8879 * Instead we use the same ramrod data buffer each time we need
8880 * to configure a list of addresses, and use the fact that the
8881 * list of MACs is changed in an incremental way and that the
8882 * function is called under the netif_addr_lock. A temporary
8883 * inconsistent CAM configuration (possible in case of very fast
8884 * sequence of add/del/add on the host side) will shortly be
8885 * restored by the handler of the last ramrod.
8887 static int bnx2x_set_uc_list(struct bnx2x *bp)
8890 struct net_device *dev = bp->dev;
8891 u8 offset = bnx2x_uc_list_cam_offset(bp);
8892 struct netdev_hw_addr *ha;
8893 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8894 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8896 if (netdev_uc_count(dev) > bnx2x_max_uc_list(bp))
8899 netdev_for_each_uc_addr(ha, dev) {
8901 config_cmd->config_table[i].msb_mac_addr =
8902 swab16(*(u16 *)&bnx2x_uc_addr(ha)[0]);
8903 config_cmd->config_table[i].middle_mac_addr =
8904 swab16(*(u16 *)&bnx2x_uc_addr(ha)[2]);
8905 config_cmd->config_table[i].lsb_mac_addr =
8906 swab16(*(u16 *)&bnx2x_uc_addr(ha)[4]);
8908 config_cmd->config_table[i].vlan_id = 0;
8909 config_cmd->config_table[i].pf_id = BP_FUNC(bp);
8910 config_cmd->config_table[i].clients_bit_vector =
8911 cpu_to_le32(1 << BP_L_ID(bp));
8913 SET_FLAG(config_cmd->config_table[i].flags,
8914 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8915 T_ETH_MAC_COMMAND_SET);
8918 "setting UCAST[%d] (%04x:%04x:%04x)\n", i,
8919 config_cmd->config_table[i].msb_mac_addr,
8920 config_cmd->config_table[i].middle_mac_addr,
8921 config_cmd->config_table[i].lsb_mac_addr);
8925 /* Set uc MAC in NIG */
8926 bnx2x_set_mac_in_nig(bp, 1, bnx2x_uc_addr(ha),
8927 LLH_CAM_ETH_LINE + i);
8929 old = config_cmd->hdr.length;
8931 for (; i < old; i++) {
8932 if (CAM_IS_INVALID(config_cmd->
8934 /* already invalidated */
8938 SET_FLAG(config_cmd->config_table[i].flags,
8939 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8940 T_ETH_MAC_COMMAND_INVALIDATE);
8946 config_cmd->hdr.length = i;
8947 config_cmd->hdr.offset = offset;
8948 config_cmd->hdr.client_id = 0xff;
8949 /* Mark that this ramrod doesn't use bp->set_mac_pending for
8952 config_cmd->hdr.echo = 0;
8956 return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8957 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8961 void bnx2x_invalidate_uc_list(struct bnx2x *bp)
8964 struct mac_configuration_cmd *config_cmd = bnx2x_sp(bp, uc_mac_config);
8965 dma_addr_t config_cmd_map = bnx2x_sp_mapping(bp, uc_mac_config);
8966 int ramrod_flags = WAIT_RAMROD_COMMON;
8967 u8 offset = bnx2x_uc_list_cam_offset(bp);
8968 u8 max_list_size = bnx2x_max_uc_list(bp);
8970 for (i = 0; i < max_list_size; i++) {
8971 SET_FLAG(config_cmd->config_table[i].flags,
8972 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
8973 T_ETH_MAC_COMMAND_INVALIDATE);
8974 bnx2x_set_mac_in_nig(bp, 0, NULL, LLH_CAM_ETH_LINE + 1 + i);
8979 config_cmd->hdr.length = max_list_size;
8980 config_cmd->hdr.offset = offset;
8981 config_cmd->hdr.client_id = 0xff;
8982 /* We'll wait for a completion this time... */
8983 config_cmd->hdr.echo = 1;
8985 bp->set_mac_pending = 1;
8989 bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
8990 U64_HI(config_cmd_map), U64_LO(config_cmd_map), 1);
8992 /* Wait for a completion */
8993 bnx2x_wait_ramrod(bp, 0, 0, &bp->set_mac_pending,
8998 static inline int bnx2x_set_mc_list(struct bnx2x *bp)
9000 /* some multicasts */
9001 if (CHIP_IS_E1(bp)) {
9002 return bnx2x_set_e1_mc_list(bp);
9003 } else { /* E1H and newer */
9004 return bnx2x_set_e1h_mc_list(bp);
9008 /* called with netif_tx_lock from dev_mcast.c */
9009 void bnx2x_set_rx_mode(struct net_device *dev)
9011 struct bnx2x *bp = netdev_priv(dev);
9012 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
9014 if (bp->state != BNX2X_STATE_OPEN) {
9015 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
9019 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", dev->flags);
9021 if (dev->flags & IFF_PROMISC)
9022 rx_mode = BNX2X_RX_MODE_PROMISC;
9023 else if (dev->flags & IFF_ALLMULTI)
9024 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9026 /* some multicasts */
9027 if (bnx2x_set_mc_list(bp))
9028 rx_mode = BNX2X_RX_MODE_ALLMULTI;
9031 if (bnx2x_set_uc_list(bp))
9032 rx_mode = BNX2X_RX_MODE_PROMISC;
9035 bp->rx_mode = rx_mode;
9036 bnx2x_set_storm_rx_mode(bp);
9039 /* called with rtnl_lock */
9040 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
9041 int devad, u16 addr)
9043 struct bnx2x *bp = netdev_priv(netdev);
9047 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
9048 prtad, devad, addr);
9050 /* The HW expects different devad if CL22 is used */
9051 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9053 bnx2x_acquire_phy_lock(bp);
9054 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
9055 bnx2x_release_phy_lock(bp);
9056 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
9063 /* called with rtnl_lock */
9064 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
9065 u16 addr, u16 value)
9067 struct bnx2x *bp = netdev_priv(netdev);
9070 DP(NETIF_MSG_LINK, "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x,"
9071 " value 0x%x\n", prtad, devad, addr, value);
9073 /* The HW expects different devad if CL22 is used */
9074 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
9076 bnx2x_acquire_phy_lock(bp);
9077 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
9078 bnx2x_release_phy_lock(bp);
9082 /* called with rtnl_lock */
9083 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9085 struct bnx2x *bp = netdev_priv(dev);
9086 struct mii_ioctl_data *mdio = if_mii(ifr);
9088 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
9089 mdio->phy_id, mdio->reg_num, mdio->val_in);
9091 if (!netif_running(dev))
9094 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
9097 #ifdef CONFIG_NET_POLL_CONTROLLER
9098 static void poll_bnx2x(struct net_device *dev)
9100 struct bnx2x *bp = netdev_priv(dev);
9102 disable_irq(bp->pdev->irq);
9103 bnx2x_interrupt(bp->pdev->irq, dev);
9104 enable_irq(bp->pdev->irq);
9108 static const struct net_device_ops bnx2x_netdev_ops = {
9109 .ndo_open = bnx2x_open,
9110 .ndo_stop = bnx2x_close,
9111 .ndo_start_xmit = bnx2x_start_xmit,
9112 .ndo_select_queue = bnx2x_select_queue,
9113 .ndo_set_rx_mode = bnx2x_set_rx_mode,
9114 .ndo_set_mac_address = bnx2x_change_mac_addr,
9115 .ndo_validate_addr = eth_validate_addr,
9116 .ndo_do_ioctl = bnx2x_ioctl,
9117 .ndo_change_mtu = bnx2x_change_mtu,
9118 .ndo_fix_features = bnx2x_fix_features,
9119 .ndo_set_features = bnx2x_set_features,
9120 .ndo_tx_timeout = bnx2x_tx_timeout,
9121 #ifdef CONFIG_NET_POLL_CONTROLLER
9122 .ndo_poll_controller = poll_bnx2x,
9126 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
9127 struct net_device *dev)
9132 SET_NETDEV_DEV(dev, &pdev->dev);
9133 bp = netdev_priv(dev);
9138 bp->pf_num = PCI_FUNC(pdev->devfn);
9140 rc = pci_enable_device(pdev);
9142 dev_err(&bp->pdev->dev,
9143 "Cannot enable PCI device, aborting\n");
9147 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
9148 dev_err(&bp->pdev->dev,
9149 "Cannot find PCI device base address, aborting\n");
9151 goto err_out_disable;
9154 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
9155 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
9156 " base address, aborting\n");
9158 goto err_out_disable;
9161 if (atomic_read(&pdev->enable_cnt) == 1) {
9162 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
9164 dev_err(&bp->pdev->dev,
9165 "Cannot obtain PCI resources, aborting\n");
9166 goto err_out_disable;
9169 pci_set_master(pdev);
9170 pci_save_state(pdev);
9173 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
9174 if (bp->pm_cap == 0) {
9175 dev_err(&bp->pdev->dev,
9176 "Cannot find power management capability, aborting\n");
9178 goto err_out_release;
9181 bp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
9182 if (bp->pcie_cap == 0) {
9183 dev_err(&bp->pdev->dev,
9184 "Cannot find PCI Express capability, aborting\n");
9186 goto err_out_release;
9189 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) == 0) {
9190 bp->flags |= USING_DAC_FLAG;
9191 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)) != 0) {
9192 dev_err(&bp->pdev->dev, "dma_set_coherent_mask"
9193 " failed, aborting\n");
9195 goto err_out_release;
9198 } else if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
9199 dev_err(&bp->pdev->dev,
9200 "System does not support DMA, aborting\n");
9202 goto err_out_release;
9205 dev->mem_start = pci_resource_start(pdev, 0);
9206 dev->base_addr = dev->mem_start;
9207 dev->mem_end = pci_resource_end(pdev, 0);
9209 dev->irq = pdev->irq;
9211 bp->regview = pci_ioremap_bar(pdev, 0);
9213 dev_err(&bp->pdev->dev,
9214 "Cannot map register space, aborting\n");
9216 goto err_out_release;
9219 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
9220 min_t(u64, BNX2X_DB_SIZE(bp),
9221 pci_resource_len(pdev, 2)));
9222 if (!bp->doorbells) {
9223 dev_err(&bp->pdev->dev,
9224 "Cannot map doorbell space, aborting\n");
9229 bnx2x_set_power_state(bp, PCI_D0);
9231 /* clean indirect addresses */
9232 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
9233 PCICFG_VENDOR_ID_OFFSET);
9234 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(bp)*16, 0);
9235 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(bp)*16, 0);
9236 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(bp)*16, 0);
9237 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(bp)*16, 0);
9239 /* Reset the load counter */
9240 bnx2x_clear_load_cnt(bp);
9242 dev->watchdog_timeo = TX_TIMEOUT;
9244 dev->netdev_ops = &bnx2x_netdev_ops;
9245 bnx2x_set_ethtool_ops(dev);
9247 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9248 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
9249 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_HW_VLAN_TX;
9251 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
9252 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
9254 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
9255 if (bp->flags & USING_DAC_FLAG)
9256 dev->features |= NETIF_F_HIGHDMA;
9258 /* Add Loopback capability to the device */
9259 dev->hw_features |= NETIF_F_LOOPBACK;
9262 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
9265 /* get_port_hwinfo() will set prtad and mmds properly */
9266 bp->mdio.prtad = MDIO_PRTAD_NONE;
9268 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9270 bp->mdio.mdio_read = bnx2x_mdio_read;
9271 bp->mdio.mdio_write = bnx2x_mdio_write;
9277 iounmap(bp->regview);
9280 if (bp->doorbells) {
9281 iounmap(bp->doorbells);
9282 bp->doorbells = NULL;
9286 if (atomic_read(&pdev->enable_cnt) == 1)
9287 pci_release_regions(pdev);
9290 pci_disable_device(pdev);
9291 pci_set_drvdata(pdev, NULL);
9297 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
9298 int *width, int *speed)
9300 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
9302 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
9304 /* return value of 1=2.5GHz 2=5GHz */
9305 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
9308 static int bnx2x_check_firmware(struct bnx2x *bp)
9310 const struct firmware *firmware = bp->firmware;
9311 struct bnx2x_fw_file_hdr *fw_hdr;
9312 struct bnx2x_fw_file_section *sections;
9313 u32 offset, len, num_ops;
9318 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr))
9321 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
9322 sections = (struct bnx2x_fw_file_section *)fw_hdr;
9324 /* Make sure none of the offsets and sizes make us read beyond
9325 * the end of the firmware data */
9326 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
9327 offset = be32_to_cpu(sections[i].offset);
9328 len = be32_to_cpu(sections[i].len);
9329 if (offset + len > firmware->size) {
9330 dev_err(&bp->pdev->dev,
9331 "Section %d length is out of bounds\n", i);
9336 /* Likewise for the init_ops offsets */
9337 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
9338 ops_offsets = (u16 *)(firmware->data + offset);
9339 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
9341 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
9342 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
9343 dev_err(&bp->pdev->dev,
9344 "Section offset %d is out of bounds\n", i);
9349 /* Check FW version */
9350 offset = be32_to_cpu(fw_hdr->fw_version.offset);
9351 fw_ver = firmware->data + offset;
9352 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
9353 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
9354 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
9355 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
9356 dev_err(&bp->pdev->dev,
9357 "Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
9358 fw_ver[0], fw_ver[1], fw_ver[2],
9359 fw_ver[3], BCM_5710_FW_MAJOR_VERSION,
9360 BCM_5710_FW_MINOR_VERSION,
9361 BCM_5710_FW_REVISION_VERSION,
9362 BCM_5710_FW_ENGINEERING_VERSION);
9369 static inline void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9371 const __be32 *source = (const __be32 *)_source;
9372 u32 *target = (u32 *)_target;
9375 for (i = 0; i < n/4; i++)
9376 target[i] = be32_to_cpu(source[i]);
9380 Ops array is stored in the following format:
9381 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
9383 static inline void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
9385 const __be32 *source = (const __be32 *)_source;
9386 struct raw_op *target = (struct raw_op *)_target;
9389 for (i = 0, j = 0; i < n/8; i++, j += 2) {
9390 tmp = be32_to_cpu(source[j]);
9391 target[i].op = (tmp >> 24) & 0xff;
9392 target[i].offset = tmp & 0xffffff;
9393 target[i].raw_data = be32_to_cpu(source[j + 1]);
9398 * IRO array is stored in the following format:
9399 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
9401 static inline void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
9403 const __be32 *source = (const __be32 *)_source;
9404 struct iro *target = (struct iro *)_target;
9407 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
9408 target[i].base = be32_to_cpu(source[j]);
9410 tmp = be32_to_cpu(source[j]);
9411 target[i].m1 = (tmp >> 16) & 0xffff;
9412 target[i].m2 = tmp & 0xffff;
9414 tmp = be32_to_cpu(source[j]);
9415 target[i].m3 = (tmp >> 16) & 0xffff;
9416 target[i].size = tmp & 0xffff;
9421 static inline void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
9423 const __be16 *source = (const __be16 *)_source;
9424 u16 *target = (u16 *)_target;
9427 for (i = 0; i < n/2; i++)
9428 target[i] = be16_to_cpu(source[i]);
9431 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
9433 u32 len = be32_to_cpu(fw_hdr->arr.len); \
9434 bp->arr = kmalloc(len, GFP_KERNEL); \
9436 pr_err("Failed to allocate %d bytes for "#arr"\n", len); \
9439 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
9440 (u8 *)bp->arr, len); \
9443 int bnx2x_init_firmware(struct bnx2x *bp)
9445 const char *fw_file_name;
9446 struct bnx2x_fw_file_hdr *fw_hdr;
9450 fw_file_name = FW_FILE_NAME_E1;
9451 else if (CHIP_IS_E1H(bp))
9452 fw_file_name = FW_FILE_NAME_E1H;
9453 else if (CHIP_IS_E2(bp))
9454 fw_file_name = FW_FILE_NAME_E2;
9456 BNX2X_ERR("Unsupported chip revision\n");
9460 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
9462 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
9464 BNX2X_ERR("Can't load firmware file %s\n", fw_file_name);
9465 goto request_firmware_exit;
9468 rc = bnx2x_check_firmware(bp);
9470 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
9471 goto request_firmware_exit;
9474 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
9476 /* Initialize the pointers to the init arrays */
9478 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
9481 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
9484 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
9487 /* STORMs firmware */
9488 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9489 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
9490 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
9491 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
9492 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9493 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
9494 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
9495 be32_to_cpu(fw_hdr->usem_pram_data.offset);
9496 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9497 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
9498 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
9499 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
9500 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
9501 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
9502 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
9503 be32_to_cpu(fw_hdr->csem_pram_data.offset);
9505 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
9510 kfree(bp->init_ops_offsets);
9511 init_offsets_alloc_err:
9512 kfree(bp->init_ops);
9514 kfree(bp->init_data);
9515 request_firmware_exit:
9516 release_firmware(bp->firmware);
9521 static inline int bnx2x_set_qm_cid_count(struct bnx2x *bp, int l2_cid_count)
9523 int cid_count = L2_FP_COUNT(l2_cid_count);
9526 cid_count += CNIC_CID_MAX;
9528 return roundup(cid_count, QM_CID_ROUND);
9531 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
9532 const struct pci_device_id *ent)
9534 struct net_device *dev = NULL;
9536 int pcie_width, pcie_speed;
9539 switch (ent->driver_data) {
9543 cid_count = FP_SB_MAX_E1x;
9548 cid_count = FP_SB_MAX_E2;
9552 pr_err("Unknown board_type (%ld), aborting\n",
9557 cid_count += NONE_ETH_CONTEXT_USE + CNIC_CONTEXT_USE;
9559 /* dev zeroed in init_etherdev */
9560 dev = alloc_etherdev_mq(sizeof(*bp), cid_count);
9562 dev_err(&pdev->dev, "Cannot allocate net device\n");
9566 bp = netdev_priv(dev);
9567 bp->msg_enable = debug;
9569 pci_set_drvdata(pdev, dev);
9571 bp->l2_cid_count = cid_count;
9573 rc = bnx2x_init_dev(pdev, dev);
9579 rc = bnx2x_init_bp(bp);
9583 /* calc qm_cid_count */
9584 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp, cid_count);
9587 /* disable FCOE L2 queue for E1x*/
9588 if (CHIP_IS_E1x(bp))
9589 bp->flags |= NO_FCOE_FLAG;
9593 /* Configure interrupt mode: try to enable MSI-X/MSI if
9594 * needed, set bp->num_queues appropriately.
9596 bnx2x_set_int_mode(bp);
9598 /* Add all NAPI objects */
9599 bnx2x_add_all_napi(bp);
9601 rc = register_netdev(dev);
9603 dev_err(&pdev->dev, "Cannot register net device\n");
9609 /* Add storage MAC address */
9611 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9616 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
9618 netdev_info(dev, "%s (%c%d) PCI-E x%d %s found at mem %lx,"
9619 " IRQ %d, ", board_info[ent->driver_data].name,
9620 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
9622 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
9623 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
9624 "5GHz (Gen2)" : "2.5GHz",
9625 dev->base_addr, bp->pdev->irq);
9626 pr_cont("node addr %pM\n", dev->dev_addr);
9632 iounmap(bp->regview);
9635 iounmap(bp->doorbells);
9639 if (atomic_read(&pdev->enable_cnt) == 1)
9640 pci_release_regions(pdev);
9642 pci_disable_device(pdev);
9643 pci_set_drvdata(pdev, NULL);
9648 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
9650 struct net_device *dev = pci_get_drvdata(pdev);
9654 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
9657 bp = netdev_priv(dev);
9660 /* Delete storage MAC address */
9663 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
9669 /* Delete app tlvs from dcbnl */
9670 bnx2x_dcbnl_update_applist(bp, true);
9673 unregister_netdev(dev);
9675 /* Delete all NAPI objects */
9676 bnx2x_del_all_napi(bp);
9678 /* Power on: we can't let PCI layer write to us while we are in D3 */
9679 bnx2x_set_power_state(bp, PCI_D0);
9681 /* Disable MSI/MSI-X */
9682 bnx2x_disable_msi(bp);
9685 bnx2x_set_power_state(bp, PCI_D3hot);
9687 /* Make sure RESET task is not scheduled before continuing */
9688 cancel_delayed_work_sync(&bp->reset_task);
9691 iounmap(bp->regview);
9694 iounmap(bp->doorbells);
9696 bnx2x_free_mem_bp(bp);
9700 if (atomic_read(&pdev->enable_cnt) == 1)
9701 pci_release_regions(pdev);
9703 pci_disable_device(pdev);
9704 pci_set_drvdata(pdev, NULL);
9707 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
9711 bp->state = BNX2X_STATE_ERROR;
9713 bp->rx_mode = BNX2X_RX_MODE_NONE;
9715 bnx2x_netif_stop(bp, 0);
9716 netif_carrier_off(bp->dev);
9718 del_timer_sync(&bp->timer);
9719 bp->stats_state = STATS_STATE_DISABLED;
9720 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
9725 /* Free SKBs, SGEs, TPA pool and driver internals */
9726 bnx2x_free_skbs(bp);
9728 for_each_rx_queue(bp, i)
9729 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
9733 bp->state = BNX2X_STATE_CLOSED;
9738 static void bnx2x_eeh_recover(struct bnx2x *bp)
9742 mutex_init(&bp->port.phy_mutex);
9744 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9745 bp->link_params.shmem_base = bp->common.shmem_base;
9746 BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
9748 if (!bp->common.shmem_base ||
9749 (bp->common.shmem_base < 0xA0000) ||
9750 (bp->common.shmem_base >= 0xC0000)) {
9751 BNX2X_DEV_INFO("MCP not active\n");
9752 bp->flags |= NO_MCP_FLAG;
9756 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9757 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9758 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
9759 BNX2X_ERR("BAD MCP validity signature\n");
9761 if (!BP_NOMCP(bp)) {
9763 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
9764 DRV_MSG_SEQ_NUMBER_MASK);
9765 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
9770 * bnx2x_io_error_detected - called when PCI error is detected
9771 * @pdev: Pointer to PCI device
9772 * @state: The current pci connection state
9774 * This function is called after a PCI bus error affecting
9775 * this device has been detected.
9777 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
9778 pci_channel_state_t state)
9780 struct net_device *dev = pci_get_drvdata(pdev);
9781 struct bnx2x *bp = netdev_priv(dev);
9785 netif_device_detach(dev);
9787 if (state == pci_channel_io_perm_failure) {
9789 return PCI_ERS_RESULT_DISCONNECT;
9792 if (netif_running(dev))
9793 bnx2x_eeh_nic_unload(bp);
9795 pci_disable_device(pdev);
9799 /* Request a slot reset */
9800 return PCI_ERS_RESULT_NEED_RESET;
9804 * bnx2x_io_slot_reset - called after the PCI bus has been reset
9805 * @pdev: Pointer to PCI device
9807 * Restart the card from scratch, as if from a cold-boot.
9809 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
9811 struct net_device *dev = pci_get_drvdata(pdev);
9812 struct bnx2x *bp = netdev_priv(dev);
9816 if (pci_enable_device(pdev)) {
9818 "Cannot re-enable PCI device after reset\n");
9820 return PCI_ERS_RESULT_DISCONNECT;
9823 pci_set_master(pdev);
9824 pci_restore_state(pdev);
9826 if (netif_running(dev))
9827 bnx2x_set_power_state(bp, PCI_D0);
9831 return PCI_ERS_RESULT_RECOVERED;
9835 * bnx2x_io_resume - called when traffic can start flowing again
9836 * @pdev: Pointer to PCI device
9838 * This callback is called when the error recovery driver tells us that
9839 * its OK to resume normal operation.
9841 static void bnx2x_io_resume(struct pci_dev *pdev)
9843 struct net_device *dev = pci_get_drvdata(pdev);
9844 struct bnx2x *bp = netdev_priv(dev);
9846 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
9847 printk(KERN_ERR "Handling parity error recovery. "
9848 "Try again later\n");
9854 bnx2x_eeh_recover(bp);
9856 if (netif_running(dev))
9857 bnx2x_nic_load(bp, LOAD_NORMAL);
9859 netif_device_attach(dev);
9864 static struct pci_error_handlers bnx2x_err_handler = {
9865 .error_detected = bnx2x_io_error_detected,
9866 .slot_reset = bnx2x_io_slot_reset,
9867 .resume = bnx2x_io_resume,
9870 static struct pci_driver bnx2x_pci_driver = {
9871 .name = DRV_MODULE_NAME,
9872 .id_table = bnx2x_pci_tbl,
9873 .probe = bnx2x_init_one,
9874 .remove = __devexit_p(bnx2x_remove_one),
9875 .suspend = bnx2x_suspend,
9876 .resume = bnx2x_resume,
9877 .err_handler = &bnx2x_err_handler,
9880 static int __init bnx2x_init(void)
9884 pr_info("%s", version);
9886 bnx2x_wq = create_singlethread_workqueue("bnx2x");
9887 if (bnx2x_wq == NULL) {
9888 pr_err("Cannot create workqueue\n");
9892 ret = pci_register_driver(&bnx2x_pci_driver);
9894 pr_err("Cannot register driver\n");
9895 destroy_workqueue(bnx2x_wq);
9900 static void __exit bnx2x_cleanup(void)
9902 pci_unregister_driver(&bnx2x_pci_driver);
9904 destroy_workqueue(bnx2x_wq);
9907 module_init(bnx2x_init);
9908 module_exit(bnx2x_cleanup);
9912 /* count denotes the number of new completions we have seen */
9913 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
9915 struct eth_spe *spe;
9917 #ifdef BNX2X_STOP_ON_ERROR
9918 if (unlikely(bp->panic))
9922 spin_lock_bh(&bp->spq_lock);
9923 BUG_ON(bp->cnic_spq_pending < count);
9924 bp->cnic_spq_pending -= count;
9927 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
9928 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
9929 & SPE_HDR_CONN_TYPE) >>
9930 SPE_HDR_CONN_TYPE_SHIFT;
9932 /* Set validation for iSCSI L2 client before sending SETUP
9935 if (type == ETH_CONNECTION_TYPE) {
9936 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->
9937 hdr.conn_and_cmd_data) >>
9938 SPE_HDR_CMD_ID_SHIFT) & 0xff;
9940 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP)
9941 bnx2x_set_ctx_validation(&bp->context.
9942 vcxt[BNX2X_ISCSI_ETH_CID].eth,
9943 HW_CID(bp, BNX2X_ISCSI_ETH_CID));
9946 /* There may be not more than 8 L2 and not more than 8 L5 SPEs
9947 * We also check that the number of outstanding
9948 * COMMON ramrods is not more than the EQ and SPQ can
9951 if (type == ETH_CONNECTION_TYPE) {
9952 if (!atomic_read(&bp->cq_spq_left))
9955 atomic_dec(&bp->cq_spq_left);
9956 } else if (type == NONE_CONNECTION_TYPE) {
9957 if (!atomic_read(&bp->eq_spq_left))
9960 atomic_dec(&bp->eq_spq_left);
9961 } else if ((type == ISCSI_CONNECTION_TYPE) ||
9962 (type == FCOE_CONNECTION_TYPE)) {
9963 if (bp->cnic_spq_pending >=
9964 bp->cnic_eth_dev.max_kwqe_pending)
9967 bp->cnic_spq_pending++;
9969 BNX2X_ERR("Unknown SPE type: %d\n", type);
9974 spe = bnx2x_sp_get_next(bp);
9975 *spe = *bp->cnic_kwq_cons;
9977 DP(NETIF_MSG_TIMER, "pending on SPQ %d, on KWQ %d count %d\n",
9978 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
9980 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
9981 bp->cnic_kwq_cons = bp->cnic_kwq;
9983 bp->cnic_kwq_cons++;
9985 bnx2x_sp_prod_update(bp);
9986 spin_unlock_bh(&bp->spq_lock);
9989 static int bnx2x_cnic_sp_queue(struct net_device *dev,
9990 struct kwqe_16 *kwqes[], u32 count)
9992 struct bnx2x *bp = netdev_priv(dev);
9995 #ifdef BNX2X_STOP_ON_ERROR
9996 if (unlikely(bp->panic))
10000 spin_lock_bh(&bp->spq_lock);
10002 for (i = 0; i < count; i++) {
10003 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
10005 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
10008 *bp->cnic_kwq_prod = *spe;
10010 bp->cnic_kwq_pending++;
10012 DP(NETIF_MSG_TIMER, "L5 SPQE %x %x %x:%x pos %d\n",
10013 spe->hdr.conn_and_cmd_data, spe->hdr.type,
10014 spe->data.update_data_addr.hi,
10015 spe->data.update_data_addr.lo,
10016 bp->cnic_kwq_pending);
10018 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
10019 bp->cnic_kwq_prod = bp->cnic_kwq;
10021 bp->cnic_kwq_prod++;
10024 spin_unlock_bh(&bp->spq_lock);
10026 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
10027 bnx2x_cnic_sp_post(bp, 0);
10032 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10034 struct cnic_ops *c_ops;
10037 mutex_lock(&bp->cnic_mutex);
10038 c_ops = rcu_dereference_protected(bp->cnic_ops,
10039 lockdep_is_held(&bp->cnic_mutex));
10041 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10042 mutex_unlock(&bp->cnic_mutex);
10047 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
10049 struct cnic_ops *c_ops;
10053 c_ops = rcu_dereference(bp->cnic_ops);
10055 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
10062 * for commands that have no data
10064 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
10066 struct cnic_ctl_info ctl = {0};
10070 return bnx2x_cnic_ctl_send(bp, &ctl);
10073 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid)
10075 struct cnic_ctl_info ctl;
10077 /* first we tell CNIC and only then we count this as a completion */
10078 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
10079 ctl.data.comp.cid = cid;
10081 bnx2x_cnic_ctl_send_bh(bp, &ctl);
10082 bnx2x_cnic_sp_post(bp, 0);
10085 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
10087 struct bnx2x *bp = netdev_priv(dev);
10090 switch (ctl->cmd) {
10091 case DRV_CTL_CTXTBL_WR_CMD: {
10092 u32 index = ctl->data.io.offset;
10093 dma_addr_t addr = ctl->data.io.dma_addr;
10095 bnx2x_ilt_wr(bp, index, addr);
10099 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
10100 int count = ctl->data.credit.credit_count;
10102 bnx2x_cnic_sp_post(bp, count);
10106 /* rtnl_lock is held. */
10107 case DRV_CTL_START_L2_CMD: {
10108 u32 cli = ctl->data.ring.client_id;
10110 /* Clear FCoE FIP and ALL ENODE MACs addresses first */
10111 bnx2x_del_fcoe_eth_macs(bp);
10113 /* Set iSCSI MAC address */
10114 bnx2x_set_iscsi_eth_mac_addr(bp, 1);
10119 /* Start accepting on iSCSI L2 ring. Accept all multicasts
10120 * because it's the only way for UIO Client to accept
10121 * multicasts (in non-promiscuous mode only one Client per
10122 * function will receive multicast packets (leading in our
10125 bnx2x_rxq_set_mac_filters(bp, cli,
10126 BNX2X_ACCEPT_UNICAST |
10127 BNX2X_ACCEPT_BROADCAST |
10128 BNX2X_ACCEPT_ALL_MULTICAST);
10129 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10134 /* rtnl_lock is held. */
10135 case DRV_CTL_STOP_L2_CMD: {
10136 u32 cli = ctl->data.ring.client_id;
10138 /* Stop accepting on iSCSI L2 ring */
10139 bnx2x_rxq_set_mac_filters(bp, cli, BNX2X_ACCEPT_NONE);
10140 storm_memset_mac_filters(bp, &bp->mac_filters, BP_FUNC(bp));
10145 /* Unset iSCSI L2 MAC */
10146 bnx2x_set_iscsi_eth_mac_addr(bp, 0);
10149 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
10150 int count = ctl->data.credit.credit_count;
10152 smp_mb__before_atomic_inc();
10153 atomic_add(count, &bp->cq_spq_left);
10154 smp_mb__after_atomic_inc();
10158 case DRV_CTL_ISCSI_STOPPED_CMD: {
10159 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_ISCSI_STOPPED);
10164 BNX2X_ERR("unknown command %x\n", ctl->cmd);
10171 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
10173 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10175 if (bp->flags & USING_MSIX_FLAG) {
10176 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
10177 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
10178 cp->irq_arr[0].vector = bp->msix_table[1].vector;
10180 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
10181 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
10183 if (CHIP_IS_E2(bp))
10184 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
10186 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
10188 cp->irq_arr[0].status_blk_num = CNIC_SB_ID(bp);
10189 cp->irq_arr[0].status_blk_num2 = CNIC_IGU_SB_ID(bp);
10190 cp->irq_arr[1].status_blk = bp->def_status_blk;
10191 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
10192 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
10197 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
10200 struct bnx2x *bp = netdev_priv(dev);
10201 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10206 if (atomic_read(&bp->intr_sem) != 0)
10209 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
10213 bp->cnic_kwq_cons = bp->cnic_kwq;
10214 bp->cnic_kwq_prod = bp->cnic_kwq;
10215 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
10217 bp->cnic_spq_pending = 0;
10218 bp->cnic_kwq_pending = 0;
10220 bp->cnic_data = data;
10223 cp->drv_state = CNIC_DRV_STATE_REGD;
10224 cp->iro_arr = bp->iro_arr;
10226 bnx2x_setup_cnic_irq_info(bp);
10228 rcu_assign_pointer(bp->cnic_ops, ops);
10233 static int bnx2x_unregister_cnic(struct net_device *dev)
10235 struct bnx2x *bp = netdev_priv(dev);
10236 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10238 mutex_lock(&bp->cnic_mutex);
10240 rcu_assign_pointer(bp->cnic_ops, NULL);
10241 mutex_unlock(&bp->cnic_mutex);
10243 kfree(bp->cnic_kwq);
10244 bp->cnic_kwq = NULL;
10249 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
10251 struct bnx2x *bp = netdev_priv(dev);
10252 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
10254 /* If both iSCSI and FCoE are disabled - return NULL in
10255 * order to indicate CNIC that it should not try to work
10256 * with this device.
10258 if (NO_ISCSI(bp) && NO_FCOE(bp))
10261 cp->drv_owner = THIS_MODULE;
10262 cp->chip_id = CHIP_ID(bp);
10263 cp->pdev = bp->pdev;
10264 cp->io_base = bp->regview;
10265 cp->io_base2 = bp->doorbells;
10266 cp->max_kwqe_pending = 8;
10267 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
10268 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
10269 bnx2x_cid_ilt_lines(bp);
10270 cp->ctx_tbl_len = CNIC_ILT_LINES;
10271 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
10272 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
10273 cp->drv_ctl = bnx2x_drv_ctl;
10274 cp->drv_register_cnic = bnx2x_register_cnic;
10275 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
10276 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID;
10277 cp->iscsi_l2_client_id = BNX2X_ISCSI_ETH_CL_ID +
10278 BP_E1HVN(bp) * NONE_ETH_CONTEXT_USE;
10279 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID;
10281 if (NO_ISCSI_OOO(bp))
10282 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
10285 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
10288 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
10290 DP(BNX2X_MSG_SP, "page_size %d, tbl_offset %d, tbl_lines %d, "
10291 "starting cid %d\n",
10293 cp->ctx_tbl_offset,
10298 EXPORT_SYMBOL(bnx2x_cnic_probe);
10300 #endif /* BCM_CNIC */