drivers/net/bnx2x/bnx2x_init.h

   1 /* bnx2x_init.h: Broadcom Everest network driver.
   2  *               Structures and macroes needed during the initialization.
   3  *
   4  * Copyright (c) 2007-2011 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation.
   9  *
  10  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  11  * Written by: Eliezer Tamir
  12  * Modified by: Vladislav Zolotarov <vladz@broadcom.com>
  13  */
  14
  15 #ifndef BNX2X_INIT_H
  16 #define BNX2X_INIT_H
  17
  18 /* Init operation types and structures */
  19 enum {
  20         OP_RD = 0x1,    /* read a single register */
  21         OP_WR,          /* write a single register */
  22         OP_SW,          /* copy a string to the device */
  23         OP_ZR,          /* clear memory */
  24         OP_ZP,          /* unzip then copy with DMAE */
  25         OP_WR_64,       /* write 64 bit pattern */
  26         OP_WB,          /* copy a string using DMAE */
  27         OP_WB_ZR,       /* Clear a string using DMAE or indirect-wr */
  28         /* Skip the following ops if all of the init modes don't match */
  29         OP_IF_MODE_OR,
  30         /* Skip the following ops if any of the init modes don't match */
  31         OP_IF_MODE_AND,
  32         OP_MAX
  33 };
  34
  35 enum {
  36         STAGE_START,
  37         STAGE_END,
  38 };
  39
  40 /* Returns the index of start or end of a specific block stage in ops array*/
  41 #define BLOCK_OPS_IDX(block, stage, end) \
  42         (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
  43
  44
  45 /* structs for the various opcodes */
  46 struct raw_op {
  47         u32 op:8;
  48         u32 offset:24;
  49         u32 raw_data;
  50 };
  51
  52 struct op_read {
  53         u32 op:8;
  54         u32 offset:24;
  55         u32 val;
  56 };
  57
  58 struct op_write {
  59         u32 op:8;
  60         u32 offset:24;
  61         u32 val;
  62 };
  63
  64 struct op_arr_write {
  65         u32 op:8;
  66         u32 offset:24;
  67 #ifdef __BIG_ENDIAN
  68         u16 data_len;
  69         u16 data_off;
  70 #else /* __LITTLE_ENDIAN */
  71         u16 data_off;
  72         u16 data_len;
  73 #endif
  74 };
  75
  76 struct op_zero {
  77         u32 op:8;
  78         u32 offset:24;
  79         u32 len;
  80 };
  81
  82 struct op_if_mode {
  83         u32 op:8;
  84         u32 cmd_offset:24;
  85         u32 mode_bit_map;
  86 };
  87
  88
  89 union init_op {
  90         struct op_read          read;
  91         struct op_write         write;
  92         struct op_arr_write     arr_wr;
  93         struct op_zero          zero;
  94         struct raw_op           raw;
  95         struct op_if_mode       if_mode;
  96 };
  97
  98
  99 /* Init Phases */
 100 enum {
 101         PHASE_COMMON,
 102         PHASE_PORT0,
 103         PHASE_PORT1,
 104         PHASE_PF0,
 105         PHASE_PF1,
 106         PHASE_PF2,
 107         PHASE_PF3,
 108         PHASE_PF4,
 109         PHASE_PF5,
 110         PHASE_PF6,
 111         PHASE_PF7,
 112         NUM_OF_INIT_PHASES
 113 };
 114
 115 /* Init Modes */
 116 enum {
 117         MODE_ASIC                      = 0x00000001,
 118         MODE_FPGA                      = 0x00000002,
 119         MODE_EMUL                      = 0x00000004,
 120         MODE_E2                        = 0x00000008,
 121         MODE_E3                        = 0x00000010,
 122         MODE_PORT2                     = 0x00000020,
 123         MODE_PORT4                     = 0x00000040,
 124         MODE_SF                        = 0x00000080,
 125         MODE_MF                        = 0x00000100,
 126         MODE_MF_SD                     = 0x00000200,
 127         MODE_MF_SI                     = 0x00000400,
 128         MODE_MF_NIV                    = 0x00000800,
 129         MODE_E3_A0                     = 0x00001000,
 130         MODE_E3_B0                     = 0x00002000,
 131         MODE_COS_BC                    = 0x00004000,
 132         MODE_COS3                      = 0x00008000,
 133         MODE_COS6                      = 0x00010000,
 134         MODE_LITTLE_ENDIAN             = 0x00020000,
 135         MODE_BIG_ENDIAN                = 0x00040000,
 136 };
 137
 138 /* Init Blocks */
 139 enum {
 140         BLOCK_ATC,
 141         BLOCK_BRB1,
 142         BLOCK_CCM,
 143         BLOCK_CDU,
 144         BLOCK_CFC,
 145         BLOCK_CSDM,
 146         BLOCK_CSEM,
 147         BLOCK_DBG,
 148         BLOCK_DMAE,
 149         BLOCK_DORQ,
 150         BLOCK_HC,
 151         BLOCK_IGU,
 152         BLOCK_MISC,
 153         BLOCK_NIG,
 154         BLOCK_PBF,
 155         BLOCK_PGLUE_B,
 156         BLOCK_PRS,
 157         BLOCK_PXP2,
 158         BLOCK_PXP,
 159         BLOCK_QM,
 160         BLOCK_SRC,
 161         BLOCK_TCM,
 162         BLOCK_TM,
 163         BLOCK_TSDM,
 164         BLOCK_TSEM,
 165         BLOCK_UCM,
 166         BLOCK_UPB,
 167         BLOCK_USDM,
 168         BLOCK_USEM,
 169         BLOCK_XCM,
 170         BLOCK_XPB,
 171         BLOCK_XSDM,
 172         BLOCK_XSEM,
 173         BLOCK_MISC_AEU,
 174         NUM_OF_INIT_BLOCKS
 175 };
 176
 177 /* QM queue numbers */
 178 #define BNX2X_ETH_Q             0
 179 #define BNX2X_TOE_Q             3
 180 #define BNX2X_TOE_ACK_Q         6
 181 #define BNX2X_ISCSI_Q           9
 182 #define BNX2X_ISCSI_ACK_Q       8
 183 #define BNX2X_FCOE_Q            10
 184
 185 /* Vnics per mode */
 186 #define BNX2X_PORT2_MODE_NUM_VNICS 4
 187 #define BNX2X_PORT4_MODE_NUM_VNICS 2
 188
 189 /* COS offset for port1 in E3 B0 4port mode */
 190 #define BNX2X_E3B0_PORT1_COS_OFFSET 3
 191
 192 /* QM Register addresses */
 193 #define BNX2X_Q_VOQ_REG_ADDR(pf_q_num)\
 194         (QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
 195 #define BNX2X_VOQ_Q_REG_ADDR(cos, pf_q_num)\
 196         (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
 197 #define BNX2X_Q_CMDQ_REG_ADDR(pf_q_num)\
 198         (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
 199
 200 /* extracts the QM queue number for the specified port and vnic */
 201 #define BNX2X_PF_Q_NUM(q_num, port, vnic)\
 202         ((((port) << 1) | (vnic)) * 16 + (q_num))
 203
 204
 205 /* Maps the specified queue to the specified COS */
 206 static inline void bnx2x_map_q_cos(struct bnx2x *bp, u32 q_num, u32 new_cos)
 207 {
 208         /* find current COS mapping */
 209         u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);
 210
 211         /* check if queue->COS mapping has changed */
 212         if (curr_cos != new_cos) {
 213                 u32 num_vnics = BNX2X_PORT2_MODE_NUM_VNICS;
 214                 u32 reg_addr, reg_bit_map, vnic;
 215
 216                 /* update parameters for 4port mode */
 217                 if (INIT_MODE_FLAGS(bp) & MODE_PORT4) {
 218                         num_vnics = BNX2X_PORT4_MODE_NUM_VNICS;
 219                         if (BP_PORT(bp)) {
 220                                 curr_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
 221                                 new_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
 222                         }
 223                 }
 224
 225                 /* change queue mapping for each VNIC */
 226                 for (vnic = 0; vnic < num_vnics; vnic++) {
 227                         u32 pf_q_num =
 228                                 BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);
 229                         u32 q_bit_map = 1 << (pf_q_num & 0x1f);
 230
 231                         /* overwrite queue->VOQ mapping */
 232                         REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
 233
 234                         /* clear queue bit from current COS bit map */
 235                         reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
 236                         reg_bit_map = REG_RD(bp, reg_addr);
 237                         REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));
 238
 239                         /* set queue bit in new COS bit map */
 240                         reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
 241                         reg_bit_map = REG_RD(bp, reg_addr);
 242                         REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);
 243
 244                         /* set/clear queue bit in command-queue bit map
 245                         (E2/E3A0 only, valid COS values are 0/1) */
 246                         if (!(INIT_MODE_FLAGS(bp) & MODE_E3_B0)) {
 247                                 reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num);
 248                                 reg_bit_map = REG_RD(bp, reg_addr);
 249                                 q_bit_map = 1 << (2 * (pf_q_num & 0xf));
 250                                 reg_bit_map = new_cos ?
 251                                               (reg_bit_map | q_bit_map) :
 252                                               (reg_bit_map & (~q_bit_map));
 253                                 REG_WR(bp, reg_addr, reg_bit_map);
 254                         }
 255                 }
 256         }
 257 }
 258
 259 /* Configures the QM according to the specified per-traffic-type COSes */
 260 static inline void bnx2x_dcb_config_qm(struct bnx2x *bp,
 261                                        struct priority_cos *traffic_cos)
 262 {
 263         bnx2x_map_q_cos(bp, BNX2X_FCOE_Q,
 264                         traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
 265         bnx2x_map_q_cos(bp, BNX2X_ISCSI_Q,
 266                         traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
 267         if (INIT_MODE_FLAGS(bp) & MODE_COS_BC) {
 268                 /* required only in backward compatible COS mode */
 269                 bnx2x_map_q_cos(bp, BNX2X_ETH_Q,
 270                                 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
 271                 bnx2x_map_q_cos(bp, BNX2X_TOE_Q,
 272                                 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
 273                 bnx2x_map_q_cos(bp, BNX2X_TOE_ACK_Q,
 274                                 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
 275                 bnx2x_map_q_cos(bp, BNX2X_ISCSI_ACK_Q,
 276                                 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
 277         }
 278 }
 279
 280
 281 /* Returns the index of start or end of a specific block stage in ops array*/
 282 #define BLOCK_OPS_IDX(block, stage, end) \
 283                         (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
 284
 285
 286 #define INITOP_SET              0       /* set the HW directly */
 287 #define INITOP_CLEAR            1       /* clear the HW directly */
 288 #define INITOP_INIT             2       /* set the init-value array */
 289
 290 /****************************************************************************
 291 * ILT management
 292 ****************************************************************************/
 293 struct ilt_line {
 294         dma_addr_t page_mapping;
 295         void *page;
 296         u32 size;
 297 };
 298
 299 struct ilt_client_info {
 300         u32 page_size;
 301         u16 start;
 302         u16 end;
 303         u16 client_num;
 304         u16 flags;
 305 #define ILT_CLIENT_SKIP_INIT    0x1
 306 #define ILT_CLIENT_SKIP_MEM     0x2
 307 };
 308
 309 struct bnx2x_ilt {
 310         u32 start_line;
 311         struct ilt_line         *lines;
 312         struct ilt_client_info  clients[4];
 313 #define ILT_CLIENT_CDU  0
 314 #define ILT_CLIENT_QM   1
 315 #define ILT_CLIENT_SRC  2
 316 #define ILT_CLIENT_TM   3
 317 };
 318
 319 /****************************************************************************
 320 * SRC configuration
 321 ****************************************************************************/
 322 struct src_ent {
 323         u8 opaque[56];
 324         u64 next;
 325 };
 326
 327 /****************************************************************************
 328 * Parity configuration
 329 ****************************************************************************/
 330 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2) \
 331 { \
 332         block##_REG_##block##_PRTY_MASK, \
 333         block##_REG_##block##_PRTY_STS_CLR, \
 334         en_mask, {m1, m1h, m2}, #block \
 335 }
 336
 337 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2) \
 338 { \
 339         block##_REG_##block##_PRTY_MASK_0, \
 340         block##_REG_##block##_PRTY_STS_CLR_0, \
 341         en_mask, {m1, m1h, m2}, #block"_0" \
 342 }
 343
 344 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2) \
 345 { \
 346         block##_REG_##block##_PRTY_MASK_1, \
 347         block##_REG_##block##_PRTY_STS_CLR_1, \
 348         en_mask, {m1, m1h, m2}, #block"_1" \
 349 }
 350
 351 static const struct {
 352         u32 mask_addr;
 353         u32 sts_clr_addr;
 354         u32 en_mask;            /* Mask to enable parity attentions */
 355         struct {
 356                 u32 e1;         /* 57710 */
 357                 u32 e1h;        /* 57711 */
 358                 u32 e2;         /* 57712 */
 359         } reg_mask;             /* Register mask (all valid bits) */
 360         char name[7];           /* Block's longest name is 6 characters long
 361                                  * (name + suffix)
 362                                  */
 363 } bnx2x_blocks_parity_data[] = {
 364         /* bit 19 masked */
 365         /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
 366         /* bit 5,18,20-31 */
 367         /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
 368         /* bit 5 */
 369         /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
 370         /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
 371         /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
 372
 373         /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
 374          * want to handle "system kill" flow at the moment.
 375          */
 376         BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff),
 377         BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
 378         BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
 379         BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
 380         BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0),
 381         BLOCK_PRTY_INFO_0(NIG,  0xffffffff, 0, 0, 0xffffffff),
 382         BLOCK_PRTY_INFO_1(NIG,  0xffff, 0, 0, 0xffff),
 383         BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
 384         BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
 385         BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
 386         BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
 387         {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
 388                 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf,
 389                 {0xf, 0xf, 0xf}, "UPB"},
 390         {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
 391                 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
 392                 {0xf, 0xf, 0xf}, "XPB"},
 393         BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
 394         BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
 395         BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf),
 396         BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
 397         BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
 398         BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
 399         BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
 400         BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffffff),
 401         BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f),
 402         BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
 403         BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
 404         BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
 405         BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
 406         BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff),
 407         BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff),
 408         BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff),
 409         BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff),
 410         BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
 411         BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
 412         BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
 413         BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f),
 414         BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
 415         BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f),
 416         BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
 417         BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f),
 418 };
 419
 420
 421 /* [28] MCP Latched rom_parity
 422  * [29] MCP Latched ump_rx_parity
 423  * [30] MCP Latched ump_tx_parity
 424  * [31] MCP Latched scpad_parity
 425  */
 426 #define MISC_AEU_ENABLE_MCP_PRTY_BITS   \
 427         (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
 428          AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
 429          AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
 430          AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
 431
 432 /* Below registers control the MCP parity attention output. When
 433  * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
 434  * enabled, when cleared - disabled.
 435  */
 436 static const u32 mcp_attn_ctl_regs[] = {
 437         MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
 438         MISC_REG_AEU_ENABLE4_NIG_0,
 439         MISC_REG_AEU_ENABLE4_PXP_0,
 440         MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
 441         MISC_REG_AEU_ENABLE4_NIG_1,
 442         MISC_REG_AEU_ENABLE4_PXP_1
 443 };
 444
 445 static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
 446 {
 447         int i;
 448         u32 reg_val;
 449
 450         for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
 451                 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
 452
 453                 if (enable)
 454                         reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
 455                 else
 456                         reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
 457
 458                 REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
 459         }
 460 }
 461
 462 static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
 463 {
 464         if (CHIP_IS_E1(bp))
 465                 return bnx2x_blocks_parity_data[idx].reg_mask.e1;
 466         else if (CHIP_IS_E1H(bp))
 467                 return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
 468         else
 469                 return bnx2x_blocks_parity_data[idx].reg_mask.e2;
 470 }
 471
 472 static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
 473 {
 474         int i;
 475
 476         for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
 477                 u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
 478
 479                 if (dis_mask) {
 480                         REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
 481                                dis_mask);
 482                         DP(NETIF_MSG_HW, "Setting parity mask "
 483                                                  "for %s to\t\t0x%x\n",
 484                                     bnx2x_blocks_parity_data[i].name, dis_mask);
 485                 }
 486         }
 487
 488         /* Disable MCP parity attentions */
 489         bnx2x_set_mcp_parity(bp, false);
 490 }
 491
 492 /**
 493  * Clear the parity error status registers.
 494  */
 495 static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
 496 {
 497         int i;
 498         u32 reg_val, mcp_aeu_bits =
 499                 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
 500                 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
 501                 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
 502                 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
 503
 504         /* Clear SEM_FAST parities */
 505         REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
 506         REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
 507         REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
 508         REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
 509
 510         for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
 511                 u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
 512
 513                 if (reg_mask) {
 514                         reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
 515                                          sts_clr_addr);
 516                         if (reg_val & reg_mask)
 517                                 DP(NETIF_MSG_HW,
 518                                             "Parity errors in %s: 0x%x\n",
 519                                             bnx2x_blocks_parity_data[i].name,
 520                                             reg_val & reg_mask);
 521                 }
 522         }
 523
 524         /* Check if there were parity attentions in MCP */
 525         reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
 526         if (reg_val & mcp_aeu_bits)
 527                 DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
 528                    reg_val & mcp_aeu_bits);
 529
 530         /* Clear parity attentions in MCP:
 531          * [7]  clears Latched rom_parity
 532          * [8]  clears Latched ump_rx_parity
 533          * [9]  clears Latched ump_tx_parity
 534          * [10] clears Latched scpad_parity (both ports)
 535          */
 536         REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
 537 }
 538
 539 static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
 540 {
 541         int i;
 542
 543         for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
 544                 u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
 545
 546                 if (reg_mask)
 547                         REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
 548                                 bnx2x_blocks_parity_data[i].en_mask & reg_mask);
 549         }
 550
 551         /* Enable MCP parity attentions */
 552         bnx2x_set_mcp_parity(bp, true);
 553 }
 554
 555
 556 #endif /* BNX2X_INIT_H */
 557