1 /* bnx2x_init.h: Broadcom Everest network driver.
2 * Structures and macroes needed during the initialization.
4 * Copyright (c) 2007-2011 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation.
10 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
11 * Written by: Eliezer Tamir
12 * Modified by: Vladislav Zolotarov <vladz@broadcom.com>
18 /* Init operation types and structures */
20 OP_RD = 0x1, /* read a single register */
21 OP_WR, /* write a single register */
22 OP_SW, /* copy a string to the device */
23 OP_ZR, /* clear memory */
24 OP_ZP, /* unzip then copy with DMAE */
25 OP_WR_64, /* write 64 bit pattern */
26 OP_WB, /* copy a string using DMAE */
27 OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */
28 /* Skip the following ops if all of the init modes don't match */
30 /* Skip the following ops if any of the init modes don't match */
40 /* Returns the index of start or end of a specific block stage in ops array*/
41 #define BLOCK_OPS_IDX(block, stage, end) \
42 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
45 /* structs for the various opcodes */
70 #else /* __LITTLE_ENDIAN */
91 struct op_write write;
92 struct op_arr_write arr_wr;
95 struct op_if_mode if_mode;
117 MODE_ASIC = 0x00000001,
118 MODE_FPGA = 0x00000002,
119 MODE_EMUL = 0x00000004,
120 MODE_E2 = 0x00000008,
121 MODE_E3 = 0x00000010,
122 MODE_PORT2 = 0x00000020,
123 MODE_PORT4 = 0x00000040,
124 MODE_SF = 0x00000080,
125 MODE_MF = 0x00000100,
126 MODE_MF_SD = 0x00000200,
127 MODE_MF_SI = 0x00000400,
128 MODE_MF_NIV = 0x00000800,
129 MODE_E3_A0 = 0x00001000,
130 MODE_E3_B0 = 0x00002000,
131 MODE_COS_BC = 0x00004000,
132 MODE_COS3 = 0x00008000,
133 MODE_COS6 = 0x00010000,
134 MODE_LITTLE_ENDIAN = 0x00020000,
135 MODE_BIG_ENDIAN = 0x00040000,
177 /* QM queue numbers */
178 #define BNX2X_ETH_Q 0
179 #define BNX2X_TOE_Q 3
180 #define BNX2X_TOE_ACK_Q 6
181 #define BNX2X_ISCSI_Q 9
182 #define BNX2X_ISCSI_ACK_Q 8
183 #define BNX2X_FCOE_Q 10
186 #define BNX2X_PORT2_MODE_NUM_VNICS 4
187 #define BNX2X_PORT4_MODE_NUM_VNICS 2
189 /* COS offset for port1 in E3 B0 4port mode */
190 #define BNX2X_E3B0_PORT1_COS_OFFSET 3
192 /* QM Register addresses */
193 #define BNX2X_Q_VOQ_REG_ADDR(pf_q_num)\
194 (QM_REG_QVOQIDX_0 + 4 * (pf_q_num))
195 #define BNX2X_VOQ_Q_REG_ADDR(cos, pf_q_num)\
196 (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5)))
197 #define BNX2X_Q_CMDQ_REG_ADDR(pf_q_num)\
198 (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4))
200 /* extracts the QM queue number for the specified port and vnic */
201 #define BNX2X_PF_Q_NUM(q_num, port, vnic)\
202 ((((port) << 1) | (vnic)) * 16 + (q_num))
205 /* Maps the specified queue to the specified COS */
206 static inline void bnx2x_map_q_cos(struct bnx2x *bp, u32 q_num, u32 new_cos)
208 /* find current COS mapping */
209 u32 curr_cos = REG_RD(bp, QM_REG_QVOQIDX_0 + q_num * 4);
211 /* check if queue->COS mapping has changed */
212 if (curr_cos != new_cos) {
213 u32 num_vnics = BNX2X_PORT2_MODE_NUM_VNICS;
214 u32 reg_addr, reg_bit_map, vnic;
216 /* update parameters for 4port mode */
217 if (INIT_MODE_FLAGS(bp) & MODE_PORT4) {
218 num_vnics = BNX2X_PORT4_MODE_NUM_VNICS;
220 curr_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
221 new_cos += BNX2X_E3B0_PORT1_COS_OFFSET;
225 /* change queue mapping for each VNIC */
226 for (vnic = 0; vnic < num_vnics; vnic++) {
228 BNX2X_PF_Q_NUM(q_num, BP_PORT(bp), vnic);
229 u32 q_bit_map = 1 << (pf_q_num & 0x1f);
231 /* overwrite queue->VOQ mapping */
232 REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos);
234 /* clear queue bit from current COS bit map */
235 reg_addr = BNX2X_VOQ_Q_REG_ADDR(curr_cos, pf_q_num);
236 reg_bit_map = REG_RD(bp, reg_addr);
237 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map));
239 /* set queue bit in new COS bit map */
240 reg_addr = BNX2X_VOQ_Q_REG_ADDR(new_cos, pf_q_num);
241 reg_bit_map = REG_RD(bp, reg_addr);
242 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map);
244 /* set/clear queue bit in command-queue bit map
245 (E2/E3A0 only, valid COS values are 0/1) */
246 if (!(INIT_MODE_FLAGS(bp) & MODE_E3_B0)) {
247 reg_addr = BNX2X_Q_CMDQ_REG_ADDR(pf_q_num);
248 reg_bit_map = REG_RD(bp, reg_addr);
249 q_bit_map = 1 << (2 * (pf_q_num & 0xf));
250 reg_bit_map = new_cos ?
251 (reg_bit_map | q_bit_map) :
252 (reg_bit_map & (~q_bit_map));
253 REG_WR(bp, reg_addr, reg_bit_map);
259 /* Configures the QM according to the specified per-traffic-type COSes */
260 static inline void bnx2x_dcb_config_qm(struct bnx2x *bp,
261 struct priority_cos *traffic_cos)
263 bnx2x_map_q_cos(bp, BNX2X_FCOE_Q,
264 traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos);
265 bnx2x_map_q_cos(bp, BNX2X_ISCSI_Q,
266 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
267 if (INIT_MODE_FLAGS(bp) & MODE_COS_BC) {
268 /* required only in backward compatible COS mode */
269 bnx2x_map_q_cos(bp, BNX2X_ETH_Q,
270 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
271 bnx2x_map_q_cos(bp, BNX2X_TOE_Q,
272 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
273 bnx2x_map_q_cos(bp, BNX2X_TOE_ACK_Q,
274 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos);
275 bnx2x_map_q_cos(bp, BNX2X_ISCSI_ACK_Q,
276 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos);
281 /* Returns the index of start or end of a specific block stage in ops array*/
282 #define BLOCK_OPS_IDX(block, stage, end) \
283 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end))
286 #define INITOP_SET 0 /* set the HW directly */
287 #define INITOP_CLEAR 1 /* clear the HW directly */
288 #define INITOP_INIT 2 /* set the init-value array */
290 /****************************************************************************
292 ****************************************************************************/
294 dma_addr_t page_mapping;
299 struct ilt_client_info {
305 #define ILT_CLIENT_SKIP_INIT 0x1
306 #define ILT_CLIENT_SKIP_MEM 0x2
311 struct ilt_line *lines;
312 struct ilt_client_info clients[4];
313 #define ILT_CLIENT_CDU 0
314 #define ILT_CLIENT_QM 1
315 #define ILT_CLIENT_SRC 2
316 #define ILT_CLIENT_TM 3
319 /****************************************************************************
321 ****************************************************************************/
327 /****************************************************************************
328 * Parity configuration
329 ****************************************************************************/
330 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2) \
332 block##_REG_##block##_PRTY_MASK, \
333 block##_REG_##block##_PRTY_STS_CLR, \
334 en_mask, {m1, m1h, m2}, #block \
337 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2) \
339 block##_REG_##block##_PRTY_MASK_0, \
340 block##_REG_##block##_PRTY_STS_CLR_0, \
341 en_mask, {m1, m1h, m2}, #block"_0" \
344 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2) \
346 block##_REG_##block##_PRTY_MASK_1, \
347 block##_REG_##block##_PRTY_STS_CLR_1, \
348 en_mask, {m1, m1h, m2}, #block"_1" \
351 static const struct {
354 u32 en_mask; /* Mask to enable parity attentions */
359 } reg_mask; /* Register mask (all valid bits) */
360 char name[7]; /* Block's longest name is 6 characters long
363 } bnx2x_blocks_parity_data[] = {
365 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
367 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
369 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
370 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
371 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
373 /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't
374 * want to handle "system kill" flow at the moment.
376 BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff),
377 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff),
378 BLOCK_PRTY_INFO_1(PXP2, 0x7ff, 0x7f, 0x7f, 0x7ff),
379 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0),
380 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff),
381 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1),
382 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff),
383 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3),
384 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK,
385 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0,
386 {0xf, 0xf, 0xf}, "UPB"},
387 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK,
388 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0,
389 {0xf, 0xf, 0xf}, "XPB"},
390 BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7),
391 BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f),
392 BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf),
393 BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1),
394 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf),
395 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf),
396 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff),
397 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff),
398 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
399 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff),
400 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff),
401 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
402 BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f),
403 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
404 BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f),
405 BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
406 BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f),
407 BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff),
408 BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f),
412 /* [28] MCP Latched rom_parity
413 * [29] MCP Latched ump_rx_parity
414 * [30] MCP Latched ump_tx_parity
415 * [31] MCP Latched scpad_parity
417 #define MISC_AEU_ENABLE_MCP_PRTY_BITS \
418 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
419 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
420 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
421 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
423 /* Below registers control the MCP parity attention output. When
424 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
425 * enabled, when cleared - disabled.
427 static const u32 mcp_attn_ctl_regs[] = {
428 MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
429 MISC_REG_AEU_ENABLE4_NIG_0,
430 MISC_REG_AEU_ENABLE4_PXP_0,
431 MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
432 MISC_REG_AEU_ENABLE4_NIG_1,
433 MISC_REG_AEU_ENABLE4_PXP_1
436 static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
441 for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
442 reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
445 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
447 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
449 REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
453 static inline u32 bnx2x_parity_reg_mask(struct bnx2x *bp, int idx)
456 return bnx2x_blocks_parity_data[idx].reg_mask.e1;
457 else if (CHIP_IS_E1H(bp))
458 return bnx2x_blocks_parity_data[idx].reg_mask.e1h;
460 return bnx2x_blocks_parity_data[idx].reg_mask.e2;
463 static inline void bnx2x_disable_blocks_parity(struct bnx2x *bp)
467 for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
468 u32 dis_mask = bnx2x_parity_reg_mask(bp, i);
471 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
473 DP(NETIF_MSG_HW, "Setting parity mask "
474 "for %s to\t\t0x%x\n",
475 bnx2x_blocks_parity_data[i].name, dis_mask);
479 /* Disable MCP parity attentions */
480 bnx2x_set_mcp_parity(bp, false);
484 * Clear the parity error status registers.
486 static inline void bnx2x_clear_blocks_parity(struct bnx2x *bp)
489 u32 reg_val, mcp_aeu_bits =
490 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY |
491 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY |
492 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY |
493 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY;
495 /* Clear SEM_FAST parities */
496 REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
497 REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
498 REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
499 REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1);
501 for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
502 u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
505 reg_val = REG_RD(bp, bnx2x_blocks_parity_data[i].
507 if (reg_val & reg_mask)
509 "Parity errors in %s: 0x%x\n",
510 bnx2x_blocks_parity_data[i].name,
515 /* Check if there were parity attentions in MCP */
516 reg_val = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_MCP);
517 if (reg_val & mcp_aeu_bits)
518 DP(NETIF_MSG_HW, "Parity error in MCP: 0x%x\n",
519 reg_val & mcp_aeu_bits);
521 /* Clear parity attentions in MCP:
522 * [7] clears Latched rom_parity
523 * [8] clears Latched ump_rx_parity
524 * [9] clears Latched ump_tx_parity
525 * [10] clears Latched scpad_parity (both ports)
527 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780);
530 static inline void bnx2x_enable_blocks_parity(struct bnx2x *bp)
534 for (i = 0; i < ARRAY_SIZE(bnx2x_blocks_parity_data); i++) {
535 u32 reg_mask = bnx2x_parity_reg_mask(bp, i);
538 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr,
539 bnx2x_blocks_parity_data[i].en_mask & reg_mask);
542 /* Enable MCP parity attentions */
543 bnx2x_set_mcp_parity(bp, true);
547 #endif /* BNX2X_INIT_H */