drivers/net/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17 #include <linux/ethtool.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/types.h>
  20 #include <linux/sched.h>
  21 #include <linux/crc32.h>
  22
  23
  24 #include "bnx2x.h"
  25 #include "bnx2x_cmn.h"
  26 #include "bnx2x_dump.h"
  27 #include "bnx2x_init.h"
  28
  29 /* Note: in the format strings below %s is replaced by the queue-name which is
  30  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  31  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  32  */
  33 #define MAX_QUEUE_NAME_LEN      4
  34 static const struct {
  35         long offset;
  36         int size;
  37         char string[ETH_GSTRING_LEN];
  38 } bnx2x_q_stats_arr[] = {
  39 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  40         { Q_STATS_OFFSET32(error_bytes_received_hi),
  41                                                 8, "[%s]: rx_error_bytes" },
  42         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  43                                                 8, "[%s]: rx_ucast_packets" },
  44         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  45                                                 8, "[%s]: rx_mcast_packets" },
  46         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  47                                                 8, "[%s]: rx_bcast_packets" },
  48         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  49         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  50                                          4, "[%s]: rx_phy_ip_err_discards"},
  51         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  52                                          4, "[%s]: rx_skb_alloc_discard" },
  53         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  54
  55 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  56         { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  57                                                 8, "[%s]: tx_ucast_packets" },
  58         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  59                                                 8, "[%s]: tx_mcast_packets" },
  60         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  61                                                 8, "[%s]: tx_bcast_packets" }
  62 };
  63
  64 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  65
  66 static const struct {
  67         long offset;
  68         int size;
  69         u32 flags;
  70 #define STATS_FLAGS_PORT                1
  71 #define STATS_FLAGS_FUNC                2
  72 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  73         char string[ETH_GSTRING_LEN];
  74 } bnx2x_stats_arr[] = {
  75 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  76                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  77         { STATS_OFFSET32(error_bytes_received_hi),
  78                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  79         { STATS_OFFSET32(total_unicast_packets_received_hi),
  80                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  81         { STATS_OFFSET32(total_multicast_packets_received_hi),
  82                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  83         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  84                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  85         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  86                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  87         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  88                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  89         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  90                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  91         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  92                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  93 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  94                                 8, STATS_FLAGS_PORT, "rx_fragments" },
  95         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
  96                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
  97         { STATS_OFFSET32(no_buff_discard_hi),
  98                                 8, STATS_FLAGS_BOTH, "rx_discards" },
  99         { STATS_OFFSET32(mac_filter_discard),
 100                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 101         { STATS_OFFSET32(xxoverflow_discard),
 102                                 4, STATS_FLAGS_PORT, "rx_fw_discards" },
 103         { STATS_OFFSET32(brb_drop_hi),
 104                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 105         { STATS_OFFSET32(brb_truncate_hi),
 106                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 107         { STATS_OFFSET32(pause_frames_received_hi),
 108                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 109         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 110                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 111         { STATS_OFFSET32(nig_timer_max),
 112                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 113 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 114                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 115         { STATS_OFFSET32(rx_skb_alloc_failed),
 116                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 117         { STATS_OFFSET32(hw_csum_err),
 118                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 119
 120         { STATS_OFFSET32(total_bytes_transmitted_hi),
 121                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 122         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 123                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 124         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 125                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 126         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 127                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 128         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 129                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 130         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 131                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 132         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 133                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 134 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 135                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 136         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 137                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 138         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 139                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 140         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 141                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 142         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 143                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 144         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 145                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 146         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 147                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 148         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 149                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 150         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 151                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 152         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 153                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 154 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 155                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 156         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 157                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 158         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 159                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 160         { STATS_OFFSET32(pause_frames_sent_hi),
 161                                 8, STATS_FLAGS_PORT, "tx_pause_frames" }
 162 };
 163
 164 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 165 static int bnx2x_get_port_type(struct bnx2x *bp)
 166 {
 167         int port_type;
 168         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 169         switch (bp->link_params.phy[phy_idx].media_type) {
 170         case ETH_PHY_SFP_FIBER:
 171         case ETH_PHY_XFP_FIBER:
 172         case ETH_PHY_KR:
 173         case ETH_PHY_CX4:
 174                 port_type = PORT_FIBRE;
 175                 break;
 176         case ETH_PHY_DA_TWINAX:
 177                 port_type = PORT_DA;
 178                 break;
 179         case ETH_PHY_BASE_T:
 180                 port_type = PORT_TP;
 181                 break;
 182         case ETH_PHY_NOT_PRESENT:
 183                 port_type = PORT_NONE;
 184                 break;
 185         case ETH_PHY_UNSPECIFIED:
 186         default:
 187                 port_type = PORT_OTHER;
 188                 break;
 189         }
 190         return port_type;
 191 }
 192
 193 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 194 {
 195         struct bnx2x *bp = netdev_priv(dev);
 196         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 197
 198         /* Dual Media boards present all available port types */
 199         cmd->supported = bp->port.supported[cfg_idx] |
 200                 (bp->port.supported[cfg_idx ^ 1] &
 201                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 202         cmd->advertising = bp->port.advertising[cfg_idx];
 203
 204         if ((bp->state == BNX2X_STATE_OPEN) &&
 205             !(bp->flags & MF_FUNC_DIS) &&
 206             (bp->link_vars.link_up)) {
 207                 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 208                 cmd->duplex = bp->link_vars.duplex;
 209         } else {
 210                 ethtool_cmd_speed_set(
 211                         cmd, bp->link_params.req_line_speed[cfg_idx]);
 212                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 213         }
 214
 215         if (IS_MF(bp))
 216                 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 217
 218         cmd->port = bnx2x_get_port_type(bp);
 219
 220         cmd->phy_address = bp->mdio.prtad;
 221         cmd->transceiver = XCVR_INTERNAL;
 222
 223         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 224                 cmd->autoneg = AUTONEG_ENABLE;
 225         else
 226                 cmd->autoneg = AUTONEG_DISABLE;
 227
 228         cmd->maxtxpkt = 0;
 229         cmd->maxrxpkt = 0;
 230
 231         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 232            DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %u\n"
 233            DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 234            DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 235            cmd->cmd, cmd->supported, cmd->advertising,
 236            ethtool_cmd_speed(cmd),
 237            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 238            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 239
 240         return 0;
 241 }
 242
 243 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 244 {
 245         struct bnx2x *bp = netdev_priv(dev);
 246         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 247         u32 speed;
 248
 249         if (IS_MF_SD(bp))
 250                 return 0;
 251
 252         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 253            "  supported 0x%x  advertising 0x%x  speed %u\n"
 254            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 255            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 256            cmd->cmd, cmd->supported, cmd->advertising,
 257            ethtool_cmd_speed(cmd),
 258            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 259            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 260
 261         speed = ethtool_cmd_speed(cmd);
 262
 263         if (IS_MF_SI(bp)) {
 264                 u32 part;
 265                 u32 line_speed = bp->link_vars.line_speed;
 266
 267                 /* use 10G if no link detected */
 268                 if (!line_speed)
 269                         line_speed = 10000;
 270
 271                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 272                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 273                                        "is required, please upgrade BC\n",
 274                                        REQ_BC_VER_4_SET_MF_BW);
 275                         return -EINVAL;
 276                 }
 277
 278                 part = (speed * 100) / line_speed;
 279
 280                 if (line_speed < speed || !part) {
 281                         BNX2X_DEV_INFO("Speed setting should be in a range "
 282                                        "from 1%% to 100%% "
 283                                        "of actual line speed\n");
 284                         return -EINVAL;
 285                 }
 286
 287                 if (bp->state != BNX2X_STATE_OPEN)
 288                         /* store value for following "load" */
 289                         bp->pending_max = part;
 290                 else
 291                         bnx2x_update_max_mf_config(bp, part);
 292
 293                 return 0;
 294         }
 295
 296         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 297         old_multi_phy_config = bp->link_params.multi_phy_config;
 298         switch (cmd->port) {
 299         case PORT_TP:
 300                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 301                         break; /* no port change */
 302
 303                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 304                       bp->port.supported[1] & SUPPORTED_TP)) {
 305                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 306                         return -EINVAL;
 307                 }
 308                 bp->link_params.multi_phy_config &=
 309                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 310                 if (bp->link_params.multi_phy_config &
 311                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 312                         bp->link_params.multi_phy_config |=
 313                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 314                 else
 315                         bp->link_params.multi_phy_config |=
 316                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 317                 break;
 318         case PORT_FIBRE:
 319                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 320                         break; /* no port change */
 321
 322                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 323                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 324                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 325                         return -EINVAL;
 326                 }
 327                 bp->link_params.multi_phy_config &=
 328                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 329                 if (bp->link_params.multi_phy_config &
 330                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 331                         bp->link_params.multi_phy_config |=
 332                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 333                 else
 334                         bp->link_params.multi_phy_config |=
 335                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 336                 break;
 337         default:
 338                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 339                 return -EINVAL;
 340         }
 341         /* Save new config in case command complete successuly */
 342         new_multi_phy_config = bp->link_params.multi_phy_config;
 343         /* Get the new cfg_idx */
 344         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 345         /* Restore old config in case command failed */
 346         bp->link_params.multi_phy_config = old_multi_phy_config;
 347         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 348
 349         if (cmd->autoneg == AUTONEG_ENABLE) {
 350                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 351                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 352                         return -EINVAL;
 353                 }
 354
 355                 /* advertise the requested speed and duplex if supported */
 356                 cmd->advertising &= bp->port.supported[cfg_idx];
 357
 358                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 359                 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
 360                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
 361                                          cmd->advertising);
 362
 363         } else { /* forced speed */
 364                 /* advertise the requested speed and duplex if supported */
 365                 switch (speed) {
 366                 case SPEED_10:
 367                         if (cmd->duplex == DUPLEX_FULL) {
 368                                 if (!(bp->port.supported[cfg_idx] &
 369                                       SUPPORTED_10baseT_Full)) {
 370                                         DP(NETIF_MSG_LINK,
 371                                            "10M full not supported\n");
 372                                         return -EINVAL;
 373                                 }
 374
 375                                 advertising = (ADVERTISED_10baseT_Full |
 376                                                ADVERTISED_TP);
 377                         } else {
 378                                 if (!(bp->port.supported[cfg_idx] &
 379                                       SUPPORTED_10baseT_Half)) {
 380                                         DP(NETIF_MSG_LINK,
 381                                            "10M half not supported\n");
 382                                         return -EINVAL;
 383                                 }
 384
 385                                 advertising = (ADVERTISED_10baseT_Half |
 386                                                ADVERTISED_TP);
 387                         }
 388                         break;
 389
 390                 case SPEED_100:
 391                         if (cmd->duplex == DUPLEX_FULL) {
 392                                 if (!(bp->port.supported[cfg_idx] &
 393                                                 SUPPORTED_100baseT_Full)) {
 394                                         DP(NETIF_MSG_LINK,
 395                                            "100M full not supported\n");
 396                                         return -EINVAL;
 397                                 }
 398
 399                                 advertising = (ADVERTISED_100baseT_Full |
 400                                                ADVERTISED_TP);
 401                         } else {
 402                                 if (!(bp->port.supported[cfg_idx] &
 403                                                 SUPPORTED_100baseT_Half)) {
 404                                         DP(NETIF_MSG_LINK,
 405                                            "100M half not supported\n");
 406                                         return -EINVAL;
 407                                 }
 408
 409                                 advertising = (ADVERTISED_100baseT_Half |
 410                                                ADVERTISED_TP);
 411                         }
 412                         break;
 413
 414                 case SPEED_1000:
 415                         if (cmd->duplex != DUPLEX_FULL) {
 416                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 417                                 return -EINVAL;
 418                         }
 419
 420                         if (!(bp->port.supported[cfg_idx] &
 421                               SUPPORTED_1000baseT_Full)) {
 422                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 423                                 return -EINVAL;
 424                         }
 425
 426                         advertising = (ADVERTISED_1000baseT_Full |
 427                                        ADVERTISED_TP);
 428                         break;
 429
 430                 case SPEED_2500:
 431                         if (cmd->duplex != DUPLEX_FULL) {
 432                                 DP(NETIF_MSG_LINK,
 433                                    "2.5G half not supported\n");
 434                                 return -EINVAL;
 435                         }
 436
 437                         if (!(bp->port.supported[cfg_idx]
 438                               & SUPPORTED_2500baseX_Full)) {
 439                                 DP(NETIF_MSG_LINK,
 440                                    "2.5G full not supported\n");
 441                                 return -EINVAL;
 442                         }
 443
 444                         advertising = (ADVERTISED_2500baseX_Full |
 445                                        ADVERTISED_TP);
 446                         break;
 447
 448                 case SPEED_10000:
 449                         if (cmd->duplex != DUPLEX_FULL) {
 450                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 451                                 return -EINVAL;
 452                         }
 453
 454                         if (!(bp->port.supported[cfg_idx]
 455                               & SUPPORTED_10000baseT_Full)) {
 456                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 457                                 return -EINVAL;
 458                         }
 459
 460                         advertising = (ADVERTISED_10000baseT_Full |
 461                                        ADVERTISED_FIBRE);
 462                         break;
 463
 464                 default:
 465                         DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
 466                         return -EINVAL;
 467                 }
 468
 469                 bp->link_params.req_line_speed[cfg_idx] = speed;
 470                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 471                 bp->port.advertising[cfg_idx] = advertising;
 472         }
 473
 474         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 475            DP_LEVEL "  req_duplex %d  advertising 0x%x\n",
 476            bp->link_params.req_line_speed[cfg_idx],
 477            bp->link_params.req_duplex[cfg_idx],
 478            bp->port.advertising[cfg_idx]);
 479
 480         /* Set new config */
 481         bp->link_params.multi_phy_config = new_multi_phy_config;
 482         if (netif_running(dev)) {
 483                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 484                 bnx2x_link_set(bp);
 485         }
 486
 487         return 0;
 488 }
 489
 490 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 491 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 492 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 493
 494 static int bnx2x_get_regs_len(struct net_device *dev)
 495 {
 496         struct bnx2x *bp = netdev_priv(dev);
 497         int regdump_len = 0;
 498         int i, j, k;
 499
 500         if (CHIP_IS_E1(bp)) {
 501                 for (i = 0; i < REGS_COUNT; i++)
 502                         if (IS_E1_ONLINE(reg_addrs[i].info))
 503                                 regdump_len += reg_addrs[i].size;
 504
 505                 for (i = 0; i < WREGS_COUNT_E1; i++)
 506                         if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
 507                                 regdump_len += wreg_addrs_e1[i].size *
 508                                         (1 + wreg_addrs_e1[i].read_regs_count);
 509
 510         } else if (CHIP_IS_E1H(bp)) {
 511                 for (i = 0; i < REGS_COUNT; i++)
 512                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 513                                 regdump_len += reg_addrs[i].size;
 514
 515                 for (i = 0; i < WREGS_COUNT_E1H; i++)
 516                         if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
 517                                 regdump_len += wreg_addrs_e1h[i].size *
 518                                         (1 + wreg_addrs_e1h[i].read_regs_count);
 519         } else if (CHIP_IS_E2(bp)) {
 520                 for (i = 0; i < REGS_COUNT; i++)
 521                         if (IS_E2_ONLINE(reg_addrs[i].info))
 522                                 regdump_len += reg_addrs[i].size;
 523
 524                 for (i = 0; i < WREGS_COUNT_E2; i++)
 525                         if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
 526                                 regdump_len += wreg_addrs_e2[i].size *
 527                                         (1 + wreg_addrs_e2[i].read_regs_count);
 528
 529                 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
 530                         for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
 531                                 for (k = 0; k < PAGE_READ_REGS_E2; k++)
 532                                         if (IS_E2_ONLINE(page_read_regs_e2[k].
 533                                                          info))
 534                                                 regdump_len +=
 535                                                 page_read_regs_e2[k].size;
 536                         }
 537         }
 538         regdump_len *= 4;
 539         regdump_len += sizeof(struct dump_hdr);
 540
 541         return regdump_len;
 542 }
 543
 544 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
 545 {
 546         u32 i, j, k, n;
 547
 548         for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
 549                 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
 550                         REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
 551                         for (k = 0; k < PAGE_READ_REGS_E2; k++)
 552                                 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
 553                                         for (n = 0; n <
 554                                               page_read_regs_e2[k].size; n++)
 555                                                 *p++ = REG_RD(bp,
 556                                         page_read_regs_e2[k].addr + n*4);
 557                 }
 558         }
 559 }
 560
 561 static void bnx2x_get_regs(struct net_device *dev,
 562                            struct ethtool_regs *regs, void *_p)
 563 {
 564         u32 *p = _p, i, j;
 565         struct bnx2x *bp = netdev_priv(dev);
 566         struct dump_hdr dump_hdr = {0};
 567
 568         regs->version = 0;
 569         memset(p, 0, regs->len);
 570
 571         if (!netif_running(bp->dev))
 572                 return;
 573
 574         /* Disable parity attentions as long as following dump may
 575          * cause false alarms by reading never written registers. We
 576          * will re-enable parity attentions right after the dump.
 577          */
 578         bnx2x_disable_blocks_parity(bp);
 579
 580         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 581         dump_hdr.dump_sign = dump_sign_all;
 582         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 583         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 584         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 585         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 586
 587         if (CHIP_IS_E1(bp))
 588                 dump_hdr.info = RI_E1_ONLINE;
 589         else if (CHIP_IS_E1H(bp))
 590                 dump_hdr.info = RI_E1H_ONLINE;
 591         else if (CHIP_IS_E2(bp))
 592                 dump_hdr.info = RI_E2_ONLINE |
 593                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 594
 595         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 596         p += dump_hdr.hdr_size + 1;
 597
 598         if (CHIP_IS_E1(bp)) {
 599                 for (i = 0; i < REGS_COUNT; i++)
 600                         if (IS_E1_ONLINE(reg_addrs[i].info))
 601                                 for (j = 0; j < reg_addrs[i].size; j++)
 602                                         *p++ = REG_RD(bp,
 603                                                       reg_addrs[i].addr + j*4);
 604
 605         } else if (CHIP_IS_E1H(bp)) {
 606                 for (i = 0; i < REGS_COUNT; i++)
 607                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 608                                 for (j = 0; j < reg_addrs[i].size; j++)
 609                                         *p++ = REG_RD(bp,
 610                                                       reg_addrs[i].addr + j*4);
 611
 612         } else if (CHIP_IS_E2(bp)) {
 613                 for (i = 0; i < REGS_COUNT; i++)
 614                         if (IS_E2_ONLINE(reg_addrs[i].info))
 615                                 for (j = 0; j < reg_addrs[i].size; j++)
 616                                         *p++ = REG_RD(bp,
 617                                               reg_addrs[i].addr + j*4);
 618
 619                 bnx2x_read_pages_regs_e2(bp, p);
 620         }
 621         /* Re-enable parity attentions */
 622         bnx2x_clear_blocks_parity(bp);
 623         if (CHIP_PARITY_ENABLED(bp))
 624                 bnx2x_enable_blocks_parity(bp);
 625 }
 626
 627 #define PHY_FW_VER_LEN                  20
 628
 629 static void bnx2x_get_drvinfo(struct net_device *dev,
 630                               struct ethtool_drvinfo *info)
 631 {
 632         struct bnx2x *bp = netdev_priv(dev);
 633         u8 phy_fw_ver[PHY_FW_VER_LEN];
 634
 635         strcpy(info->driver, DRV_MODULE_NAME);
 636         strcpy(info->version, DRV_MODULE_VERSION);
 637
 638         phy_fw_ver[0] = '\0';
 639         if (bp->port.pmf) {
 640                 bnx2x_acquire_phy_lock(bp);
 641                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 642                                              (bp->state != BNX2X_STATE_CLOSED),
 643                                              phy_fw_ver, PHY_FW_VER_LEN);
 644                 bnx2x_release_phy_lock(bp);
 645         }
 646
 647         strncpy(info->fw_version, bp->fw_ver, 32);
 648         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 649                  "bc %d.%d.%d%s%s",
 650                  (bp->common.bc_ver & 0xff0000) >> 16,
 651                  (bp->common.bc_ver & 0xff00) >> 8,
 652                  (bp->common.bc_ver & 0xff),
 653                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 654         strcpy(info->bus_info, pci_name(bp->pdev));
 655         info->n_stats = BNX2X_NUM_STATS;
 656         info->testinfo_len = BNX2X_NUM_TESTS;
 657         info->eedump_len = bp->common.flash_size;
 658         info->regdump_len = bnx2x_get_regs_len(dev);
 659 }
 660
 661 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 662 {
 663         struct bnx2x *bp = netdev_priv(dev);
 664
 665         if (bp->flags & NO_WOL_FLAG) {
 666                 wol->supported = 0;
 667                 wol->wolopts = 0;
 668         } else {
 669                 wol->supported = WAKE_MAGIC;
 670                 if (bp->wol)
 671                         wol->wolopts = WAKE_MAGIC;
 672                 else
 673                         wol->wolopts = 0;
 674         }
 675         memset(&wol->sopass, 0, sizeof(wol->sopass));
 676 }
 677
 678 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 679 {
 680         struct bnx2x *bp = netdev_priv(dev);
 681
 682         if (wol->wolopts & ~WAKE_MAGIC)
 683                 return -EINVAL;
 684
 685         if (wol->wolopts & WAKE_MAGIC) {
 686                 if (bp->flags & NO_WOL_FLAG)
 687                         return -EINVAL;
 688
 689                 bp->wol = 1;
 690         } else
 691                 bp->wol = 0;
 692
 693         return 0;
 694 }
 695
 696 static u32 bnx2x_get_msglevel(struct net_device *dev)
 697 {
 698         struct bnx2x *bp = netdev_priv(dev);
 699
 700         return bp->msg_enable;
 701 }
 702
 703 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 704 {
 705         struct bnx2x *bp = netdev_priv(dev);
 706
 707         if (capable(CAP_NET_ADMIN)) {
 708                 /* dump MCP trace */
 709                 if (level & BNX2X_MSG_MCP)
 710                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 711                 bp->msg_enable = level;
 712         }
 713 }
 714
 715 static int bnx2x_nway_reset(struct net_device *dev)
 716 {
 717         struct bnx2x *bp = netdev_priv(dev);
 718
 719         if (!bp->port.pmf)
 720                 return 0;
 721
 722         if (netif_running(dev)) {
 723                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 724                 bnx2x_link_set(bp);
 725         }
 726
 727         return 0;
 728 }
 729
 730 static u32 bnx2x_get_link(struct net_device *dev)
 731 {
 732         struct bnx2x *bp = netdev_priv(dev);
 733
 734         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 735                 return 0;
 736
 737         return bp->link_vars.link_up;
 738 }
 739
 740 static int bnx2x_get_eeprom_len(struct net_device *dev)
 741 {
 742         struct bnx2x *bp = netdev_priv(dev);
 743
 744         return bp->common.flash_size;
 745 }
 746
 747 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 748 {
 749         int port = BP_PORT(bp);
 750         int count, i;
 751         u32 val = 0;
 752
 753         /* adjust timeout for emulation/FPGA */
 754         count = NVRAM_TIMEOUT_COUNT;
 755         if (CHIP_REV_IS_SLOW(bp))
 756                 count *= 100;
 757
 758         /* request access to nvram interface */
 759         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 760                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 761
 762         for (i = 0; i < count*10; i++) {
 763                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 764                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 765                         break;
 766
 767                 udelay(5);
 768         }
 769
 770         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 771                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 772                 return -EBUSY;
 773         }
 774
 775         return 0;
 776 }
 777
 778 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 779 {
 780         int port = BP_PORT(bp);
 781         int count, i;
 782         u32 val = 0;
 783
 784         /* adjust timeout for emulation/FPGA */
 785         count = NVRAM_TIMEOUT_COUNT;
 786         if (CHIP_REV_IS_SLOW(bp))
 787                 count *= 100;
 788
 789         /* relinquish nvram interface */
 790         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 791                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 792
 793         for (i = 0; i < count*10; i++) {
 794                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 795                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 796                         break;
 797
 798                 udelay(5);
 799         }
 800
 801         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 802                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 803                 return -EBUSY;
 804         }
 805
 806         return 0;
 807 }
 808
 809 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 810 {
 811         u32 val;
 812
 813         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 814
 815         /* enable both bits, even on read */
 816         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 817                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 818                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 819 }
 820
 821 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 822 {
 823         u32 val;
 824
 825         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 826
 827         /* disable both bits, even after read */
 828         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 829                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 830                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 831 }
 832
 833 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 834                                   u32 cmd_flags)
 835 {
 836         int count, i, rc;
 837         u32 val;
 838
 839         /* build the command word */
 840         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 841
 842         /* need to clear DONE bit separately */
 843         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 844
 845         /* address of the NVRAM to read from */
 846         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 847                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 848
 849         /* issue a read command */
 850         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 851
 852         /* adjust timeout for emulation/FPGA */
 853         count = NVRAM_TIMEOUT_COUNT;
 854         if (CHIP_REV_IS_SLOW(bp))
 855                 count *= 100;
 856
 857         /* wait for completion */
 858         *ret_val = 0;
 859         rc = -EBUSY;
 860         for (i = 0; i < count; i++) {
 861                 udelay(5);
 862                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 863
 864                 if (val & MCPR_NVM_COMMAND_DONE) {
 865                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
 866                         /* we read nvram data in cpu order
 867                          * but ethtool sees it as an array of bytes
 868                          * converting to big-endian will do the work */
 869                         *ret_val = cpu_to_be32(val);
 870                         rc = 0;
 871                         break;
 872                 }
 873         }
 874
 875         return rc;
 876 }
 877
 878 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
 879                             int buf_size)
 880 {
 881         int rc;
 882         u32 cmd_flags;
 883         __be32 val;
 884
 885         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
 886                 DP(BNX2X_MSG_NVM,
 887                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
 888                    offset, buf_size);
 889                 return -EINVAL;
 890         }
 891
 892         if (offset + buf_size > bp->common.flash_size) {
 893                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 894                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 895                    offset, buf_size, bp->common.flash_size);
 896                 return -EINVAL;
 897         }
 898
 899         /* request access to nvram interface */
 900         rc = bnx2x_acquire_nvram_lock(bp);
 901         if (rc)
 902                 return rc;
 903
 904         /* enable access to nvram interface */
 905         bnx2x_enable_nvram_access(bp);
 906
 907         /* read the first word(s) */
 908         cmd_flags = MCPR_NVM_COMMAND_FIRST;
 909         while ((buf_size > sizeof(u32)) && (rc == 0)) {
 910                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 911                 memcpy(ret_buf, &val, 4);
 912
 913                 /* advance to the next dword */
 914                 offset += sizeof(u32);
 915                 ret_buf += sizeof(u32);
 916                 buf_size -= sizeof(u32);
 917                 cmd_flags = 0;
 918         }
 919
 920         if (rc == 0) {
 921                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
 922                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 923                 memcpy(ret_buf, &val, 4);
 924         }
 925
 926         /* disable access to nvram interface */
 927         bnx2x_disable_nvram_access(bp);
 928         bnx2x_release_nvram_lock(bp);
 929
 930         return rc;
 931 }
 932
 933 static int bnx2x_get_eeprom(struct net_device *dev,
 934                             struct ethtool_eeprom *eeprom, u8 *eebuf)
 935 {
 936         struct bnx2x *bp = netdev_priv(dev);
 937         int rc;
 938
 939         if (!netif_running(dev))
 940                 return -EAGAIN;
 941
 942         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
 943            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
 944            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
 945            eeprom->len, eeprom->len);
 946
 947         /* parameters already validated in ethtool_get_eeprom */
 948
 949         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
 950
 951         return rc;
 952 }
 953
 954 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
 955                                    u32 cmd_flags)
 956 {
 957         int count, i, rc;
 958
 959         /* build the command word */
 960         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
 961
 962         /* need to clear DONE bit separately */
 963         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 964
 965         /* write the data */
 966         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
 967
 968         /* address of the NVRAM to write to */
 969         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 970                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 971
 972         /* issue the write command */
 973         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 974
 975         /* adjust timeout for emulation/FPGA */
 976         count = NVRAM_TIMEOUT_COUNT;
 977         if (CHIP_REV_IS_SLOW(bp))
 978                 count *= 100;
 979
 980         /* wait for completion */
 981         rc = -EBUSY;
 982         for (i = 0; i < count; i++) {
 983                 udelay(5);
 984                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 985                 if (val & MCPR_NVM_COMMAND_DONE) {
 986                         rc = 0;
 987                         break;
 988                 }
 989         }
 990
 991         return rc;
 992 }
 993
 994 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
 995
 996 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
 997                               int buf_size)
 998 {
 999         int rc;
1000         u32 cmd_flags;
1001         u32 align_offset;
1002         __be32 val;
1003
1004         if (offset + buf_size > bp->common.flash_size) {
1005                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1006                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1007                    offset, buf_size, bp->common.flash_size);
1008                 return -EINVAL;
1009         }
1010
1011         /* request access to nvram interface */
1012         rc = bnx2x_acquire_nvram_lock(bp);
1013         if (rc)
1014                 return rc;
1015
1016         /* enable access to nvram interface */
1017         bnx2x_enable_nvram_access(bp);
1018
1019         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1020         align_offset = (offset & ~0x03);
1021         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1022
1023         if (rc == 0) {
1024                 val &= ~(0xff << BYTE_OFFSET(offset));
1025                 val |= (*data_buf << BYTE_OFFSET(offset));
1026
1027                 /* nvram data is returned as an array of bytes
1028                  * convert it back to cpu order */
1029                 val = be32_to_cpu(val);
1030
1031                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1032                                              cmd_flags);
1033         }
1034
1035         /* disable access to nvram interface */
1036         bnx2x_disable_nvram_access(bp);
1037         bnx2x_release_nvram_lock(bp);
1038
1039         return rc;
1040 }
1041
1042 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1043                              int buf_size)
1044 {
1045         int rc;
1046         u32 cmd_flags;
1047         u32 val;
1048         u32 written_so_far;
1049
1050         if (buf_size == 1)      /* ethtool */
1051                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1052
1053         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1054                 DP(BNX2X_MSG_NVM,
1055                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1056                    offset, buf_size);
1057                 return -EINVAL;
1058         }
1059
1060         if (offset + buf_size > bp->common.flash_size) {
1061                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1062                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1063                    offset, buf_size, bp->common.flash_size);
1064                 return -EINVAL;
1065         }
1066
1067         /* request access to nvram interface */
1068         rc = bnx2x_acquire_nvram_lock(bp);
1069         if (rc)
1070                 return rc;
1071
1072         /* enable access to nvram interface */
1073         bnx2x_enable_nvram_access(bp);
1074
1075         written_so_far = 0;
1076         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1077         while ((written_so_far < buf_size) && (rc == 0)) {
1078                 if (written_so_far == (buf_size - sizeof(u32)))
1079                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1080                 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1081                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1082                 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1083                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1084
1085                 memcpy(&val, data_buf, 4);
1086
1087                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1088
1089                 /* advance to the next dword */
1090                 offset += sizeof(u32);
1091                 data_buf += sizeof(u32);
1092                 written_so_far += sizeof(u32);
1093                 cmd_flags = 0;
1094         }
1095
1096         /* disable access to nvram interface */
1097         bnx2x_disable_nvram_access(bp);
1098         bnx2x_release_nvram_lock(bp);
1099
1100         return rc;
1101 }
1102
1103 static int bnx2x_set_eeprom(struct net_device *dev,
1104                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1105 {
1106         struct bnx2x *bp = netdev_priv(dev);
1107         int port = BP_PORT(bp);
1108         int rc = 0;
1109         u32 ext_phy_config;
1110         if (!netif_running(dev))
1111                 return -EAGAIN;
1112
1113         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1114            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1115            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1116            eeprom->len, eeprom->len);
1117
1118         /* parameters already validated in ethtool_set_eeprom */
1119
1120         /* PHY eeprom can be accessed only by the PMF */
1121         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1122             !bp->port.pmf)
1123                 return -EINVAL;
1124
1125         ext_phy_config =
1126                 SHMEM_RD(bp,
1127                          dev_info.port_hw_config[port].external_phy_config);
1128
1129         if (eeprom->magic == 0x50485950) {
1130                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1131                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1132
1133                 bnx2x_acquire_phy_lock(bp);
1134                 rc |= bnx2x_link_reset(&bp->link_params,
1135                                        &bp->link_vars, 0);
1136                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1137                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1138                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1139                                        MISC_REGISTERS_GPIO_HIGH, port);
1140                 bnx2x_release_phy_lock(bp);
1141                 bnx2x_link_report(bp);
1142
1143         } else if (eeprom->magic == 0x50485952) {
1144                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1145                 if (bp->state == BNX2X_STATE_OPEN) {
1146                         bnx2x_acquire_phy_lock(bp);
1147                         rc |= bnx2x_link_reset(&bp->link_params,
1148                                                &bp->link_vars, 1);
1149
1150                         rc |= bnx2x_phy_init(&bp->link_params,
1151                                              &bp->link_vars);
1152                         bnx2x_release_phy_lock(bp);
1153                         bnx2x_calc_fc_adv(bp);
1154                 }
1155         } else if (eeprom->magic == 0x53985943) {
1156                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1157                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1158                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1159
1160                         /* DSP Remove Download Mode */
1161                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1162                                        MISC_REGISTERS_GPIO_LOW, port);
1163
1164                         bnx2x_acquire_phy_lock(bp);
1165
1166                         bnx2x_sfx7101_sp_sw_reset(bp,
1167                                                 &bp->link_params.phy[EXT_PHY1]);
1168
1169                         /* wait 0.5 sec to allow it to run */
1170                         msleep(500);
1171                         bnx2x_ext_phy_hw_reset(bp, port);
1172                         msleep(500);
1173                         bnx2x_release_phy_lock(bp);
1174                 }
1175         } else
1176                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1177
1178         return rc;
1179 }
1180
1181 static int bnx2x_get_coalesce(struct net_device *dev,
1182                               struct ethtool_coalesce *coal)
1183 {
1184         struct bnx2x *bp = netdev_priv(dev);
1185
1186         memset(coal, 0, sizeof(struct ethtool_coalesce));
1187
1188         coal->rx_coalesce_usecs = bp->rx_ticks;
1189         coal->tx_coalesce_usecs = bp->tx_ticks;
1190
1191         return 0;
1192 }
1193
1194 static int bnx2x_set_coalesce(struct net_device *dev,
1195                               struct ethtool_coalesce *coal)
1196 {
1197         struct bnx2x *bp = netdev_priv(dev);
1198
1199         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1200         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1201                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1202
1203         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1204         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1205                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1206
1207         if (netif_running(dev))
1208                 bnx2x_update_coalesce(bp);
1209
1210         return 0;
1211 }
1212
1213 static void bnx2x_get_ringparam(struct net_device *dev,
1214                                 struct ethtool_ringparam *ering)
1215 {
1216         struct bnx2x *bp = netdev_priv(dev);
1217
1218         ering->rx_max_pending = MAX_RX_AVAIL;
1219         ering->rx_mini_max_pending = 0;
1220         ering->rx_jumbo_max_pending = 0;
1221
1222         if (bp->rx_ring_size)
1223                 ering->rx_pending = bp->rx_ring_size;
1224         else
1225                 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1226                         ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1227                 else
1228                         ering->rx_pending = MAX_RX_AVAIL;
1229
1230         ering->rx_mini_pending = 0;
1231         ering->rx_jumbo_pending = 0;
1232
1233         ering->tx_max_pending = MAX_TX_AVAIL;
1234         ering->tx_pending = bp->tx_ring_size;
1235 }
1236
1237 static int bnx2x_set_ringparam(struct net_device *dev,
1238                                struct ethtool_ringparam *ering)
1239 {
1240         struct bnx2x *bp = netdev_priv(dev);
1241         int rc = 0;
1242
1243         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1244                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1245                 return -EAGAIN;
1246         }
1247
1248         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1249             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1250                                                     MIN_RX_SIZE_TPA)) ||
1251             (ering->tx_pending > MAX_TX_AVAIL) ||
1252             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1253                 return -EINVAL;
1254
1255         bp->rx_ring_size = ering->rx_pending;
1256         bp->tx_ring_size = ering->tx_pending;
1257
1258         if (netif_running(dev)) {
1259                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1260                 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
1261         }
1262
1263         return rc;
1264 }
1265
1266 static void bnx2x_get_pauseparam(struct net_device *dev,
1267                                  struct ethtool_pauseparam *epause)
1268 {
1269         struct bnx2x *bp = netdev_priv(dev);
1270         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1271         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1272                            BNX2X_FLOW_CTRL_AUTO);
1273
1274         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1275                             BNX2X_FLOW_CTRL_RX);
1276         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1277                             BNX2X_FLOW_CTRL_TX);
1278
1279         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1280            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1281            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1282 }
1283
1284 static int bnx2x_set_pauseparam(struct net_device *dev,
1285                                 struct ethtool_pauseparam *epause)
1286 {
1287         struct bnx2x *bp = netdev_priv(dev);
1288         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1289         if (IS_MF(bp))
1290                 return 0;
1291
1292         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1293            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1294            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1295
1296         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1297
1298         if (epause->rx_pause)
1299                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1300
1301         if (epause->tx_pause)
1302                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1303
1304         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1305                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1306
1307         if (epause->autoneg) {
1308                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1309                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1310                         return -EINVAL;
1311                 }
1312
1313                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1314                         bp->link_params.req_flow_ctrl[cfg_idx] =
1315                                 BNX2X_FLOW_CTRL_AUTO;
1316                 }
1317         }
1318
1319         DP(NETIF_MSG_LINK,
1320            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1321
1322         if (netif_running(dev)) {
1323                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1324                 bnx2x_link_set(bp);
1325         }
1326
1327         return 0;
1328 }
1329
1330 static const struct {
1331         char string[ETH_GSTRING_LEN];
1332 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1333         { "register_test (offline)" },
1334         { "memory_test (offline)" },
1335         { "loopback_test (offline)" },
1336         { "nvram_test (online)" },
1337         { "interrupt_test (online)" },
1338         { "link_test (online)" },
1339         { "idle check (online)" }
1340 };
1341
1342 static int bnx2x_test_registers(struct bnx2x *bp)
1343 {
1344         int idx, i, rc = -ENODEV;
1345         u32 wr_val = 0;
1346         int port = BP_PORT(bp);
1347         static const struct {
1348                 u32 offset0;
1349                 u32 offset1;
1350                 u32 mask;
1351         } reg_tbl[] = {
1352 /* 0 */         { BRB1_REG_PAUSE_LOW_THRESHOLD_0,      4, 0x000003ff },
1353                 { DORQ_REG_DB_ADDR0,                   4, 0xffffffff },
1354                 { HC_REG_AGG_INT_0,                    4, 0x000003ff },
1355                 { PBF_REG_MAC_IF0_ENABLE,              4, 0x00000001 },
1356                 { PBF_REG_P0_INIT_CRD,                 4, 0x000007ff },
1357                 { PRS_REG_CID_PORT_0,                  4, 0x00ffffff },
1358                 { PXP2_REG_PSWRQ_CDU0_L2P,             4, 0x000fffff },
1359                 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR,    8, 0x0003ffff },
1360                 { PXP2_REG_PSWRQ_TM0_L2P,              4, 0x000fffff },
1361                 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR,   8, 0x0003ffff },
1362 /* 10 */        { PXP2_REG_PSWRQ_TSDM0_L2P,            4, 0x000fffff },
1363                 { QM_REG_CONNNUM_0,                    4, 0x000fffff },
1364                 { TM_REG_LIN0_MAX_ACTIVE_CID,          4, 0x0003ffff },
1365                 { SRC_REG_KEYRSS0_0,                  40, 0xffffffff },
1366                 { SRC_REG_KEYRSS0_7,                  40, 0xffffffff },
1367                 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1368                 { XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
1369                 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
1370                 { NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
1371                 { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
1372 /* 20 */        { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
1373                 { NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
1374                 { NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
1375                 { NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
1376                 { NIG_REG_LLH0_ACPI_PAT_6_LEN,        68, 0x000000ff },
1377                 { NIG_REG_LLH0_ACPI_PAT_0_CRC,        68, 0xffffffff },
1378                 { NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
1379                 { NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
1380                 { NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
1381                 { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
1382 /* 30 */        { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
1383                 { NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
1384                 { NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
1385                 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1386                 { NIG_REG_STATUS_INTERRUPT_PORT0,      4, 0x07ffffff },
1387                 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1388                 { NIG_REG_SERDES0_CTRL_PHY_ADDR,      16, 0x0000001f },
1389
1390                 { 0xffffffff, 0, 0x00000000 }
1391         };
1392
1393         if (!netif_running(bp->dev))
1394                 return rc;
1395
1396         /* Repeat the test twice:
1397            First by writing 0x00000000, second by writing 0xffffffff */
1398         for (idx = 0; idx < 2; idx++) {
1399
1400                 switch (idx) {
1401                 case 0:
1402                         wr_val = 0;
1403                         break;
1404                 case 1:
1405                         wr_val = 0xffffffff;
1406                         break;
1407                 }
1408
1409                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1410                         u32 offset, mask, save_val, val;
1411                         if (CHIP_IS_E2(bp) &&
1412                             reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1413                                 continue;
1414
1415                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1416                         mask = reg_tbl[i].mask;
1417
1418                         save_val = REG_RD(bp, offset);
1419
1420                         REG_WR(bp, offset, wr_val & mask);
1421
1422                         val = REG_RD(bp, offset);
1423
1424                         /* Restore the original register's value */
1425                         REG_WR(bp, offset, save_val);
1426
1427                         /* verify value is as expected */
1428                         if ((val & mask) != (wr_val & mask)) {
1429                                 DP(NETIF_MSG_PROBE,
1430                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1431                                    offset, val, wr_val, mask);
1432                                 goto test_reg_exit;
1433                         }
1434                 }
1435         }
1436
1437         rc = 0;
1438
1439 test_reg_exit:
1440         return rc;
1441 }
1442
1443 static int bnx2x_test_memory(struct bnx2x *bp)
1444 {
1445         int i, j, rc = -ENODEV;
1446         u32 val;
1447         static const struct {
1448                 u32 offset;
1449                 int size;
1450         } mem_tbl[] = {
1451                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1452                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1453                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1454                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1455                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1456                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1457                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1458
1459                 { 0xffffffff, 0 }
1460         };
1461         static const struct {
1462                 char *name;
1463                 u32 offset;
1464                 u32 e1_mask;
1465                 u32 e1h_mask;
1466                 u32 e2_mask;
1467         } prty_tbl[] = {
1468                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,   0x3ffc0, 0,   0 },
1469                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,   0x2,     0x2, 0 },
1470                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0,       0,   0 },
1471                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,   0x3ffc0, 0,   0 },
1472                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,   0x3ffc0, 0,   0 },
1473                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,   0x3ffc1, 0,   0 },
1474
1475                 { NULL, 0xffffffff, 0, 0, 0 }
1476         };
1477
1478         if (!netif_running(bp->dev))
1479                 return rc;
1480
1481         /* pre-Check the parity status */
1482         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1483                 val = REG_RD(bp, prty_tbl[i].offset);
1484                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1485                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1486                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1487                         DP(NETIF_MSG_HW,
1488                            "%s is 0x%x\n", prty_tbl[i].name, val);
1489                         goto test_mem_exit;
1490                 }
1491         }
1492
1493         /* Go through all the memories */
1494         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1495                 for (j = 0; j < mem_tbl[i].size; j++)
1496                         REG_RD(bp, mem_tbl[i].offset + j*4);
1497
1498         /* Check the parity status */
1499         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1500                 val = REG_RD(bp, prty_tbl[i].offset);
1501                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1502                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1503                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1504                         DP(NETIF_MSG_HW,
1505                            "%s is 0x%x\n", prty_tbl[i].name, val);
1506                         goto test_mem_exit;
1507                 }
1508         }
1509
1510         rc = 0;
1511
1512 test_mem_exit:
1513         return rc;
1514 }
1515
1516 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1517 {
1518         int cnt = 1400;
1519
1520         if (link_up)
1521                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1522                         msleep(10);
1523 }
1524
1525 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1526 {
1527         unsigned int pkt_size, num_pkts, i;
1528         struct sk_buff *skb;
1529         unsigned char *packet;
1530         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1531         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1532         u16 tx_start_idx, tx_idx;
1533         u16 rx_start_idx, rx_idx;
1534         u16 pkt_prod, bd_prod;
1535         struct sw_tx_bd *tx_buf;
1536         struct eth_tx_start_bd *tx_start_bd;
1537         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1538         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1539         dma_addr_t mapping;
1540         union eth_rx_cqe *cqe;
1541         u8 cqe_fp_flags;
1542         struct sw_rx_bd *rx_buf;
1543         u16 len;
1544         int rc = -ENODEV;
1545
1546         /* check the loopback mode */
1547         switch (loopback_mode) {
1548         case BNX2X_PHY_LOOPBACK:
1549                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1550                         return -EINVAL;
1551                 break;
1552         case BNX2X_MAC_LOOPBACK:
1553                 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1554                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1555                 break;
1556         default:
1557                 return -EINVAL;
1558         }
1559
1560         /* prepare the loopback packet */
1561         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1562                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1563         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1564         if (!skb) {
1565                 rc = -ENOMEM;
1566                 goto test_loopback_exit;
1567         }
1568         packet = skb_put(skb, pkt_size);
1569         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1570         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1571         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1572         for (i = ETH_HLEN; i < pkt_size; i++)
1573                 packet[i] = (unsigned char) (i & 0xff);
1574
1575         /* send the loopback packet */
1576         num_pkts = 0;
1577         tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1578         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1579
1580         pkt_prod = fp_tx->tx_pkt_prod++;
1581         tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1582         tx_buf->first_bd = fp_tx->tx_bd_prod;
1583         tx_buf->skb = skb;
1584         tx_buf->flags = 0;
1585
1586         bd_prod = TX_BD(fp_tx->tx_bd_prod);
1587         tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1588         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1589                                  skb_headlen(skb), DMA_TO_DEVICE);
1590         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1591         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1592         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1593         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1594         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1595         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1596         SET_FLAG(tx_start_bd->general_data,
1597                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1598                  UNICAST_ADDRESS);
1599         SET_FLAG(tx_start_bd->general_data,
1600                  ETH_TX_START_BD_HDR_NBDS,
1601                  1);
1602
1603         /* turn on parsing and get a BD */
1604         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1605
1606         pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1607         pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1608
1609         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1610         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1611
1612         wmb();
1613
1614         fp_tx->tx_db.data.prod += 2;
1615         barrier();
1616         DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1617
1618         mmiowb();
1619
1620         num_pkts++;
1621         fp_tx->tx_bd_prod += 2; /* start + pbd */
1622
1623         udelay(100);
1624
1625         tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1626         if (tx_idx != tx_start_idx + num_pkts)
1627                 goto test_loopback_exit;
1628
1629         /* Unlike HC IGU won't generate an interrupt for status block
1630          * updates that have been performed while interrupts were
1631          * disabled.
1632          */
1633         if (bp->common.int_block == INT_BLOCK_IGU) {
1634                 /* Disable local BHes to prevent a dead-lock situation between
1635                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1636                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1637                  */
1638                 local_bh_disable();
1639                 bnx2x_tx_int(fp_tx);
1640                 local_bh_enable();
1641         }
1642
1643         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1644         if (rx_idx != rx_start_idx + num_pkts)
1645                 goto test_loopback_exit;
1646
1647         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1648         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1649         if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1650                 goto test_loopback_rx_exit;
1651
1652         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1653         if (len != pkt_size)
1654                 goto test_loopback_rx_exit;
1655
1656         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1657         skb = rx_buf->skb;
1658         skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1659         for (i = ETH_HLEN; i < pkt_size; i++)
1660                 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1661                         goto test_loopback_rx_exit;
1662
1663         rc = 0;
1664
1665 test_loopback_rx_exit:
1666
1667         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1668         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1669         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1670         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1671
1672         /* Update producers */
1673         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1674                              fp_rx->rx_sge_prod);
1675
1676 test_loopback_exit:
1677         bp->link_params.loopback_mode = LOOPBACK_NONE;
1678
1679         return rc;
1680 }
1681
1682 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1683 {
1684         int rc = 0, res;
1685
1686         if (BP_NOMCP(bp))
1687                 return rc;
1688
1689         if (!netif_running(bp->dev))
1690                 return BNX2X_LOOPBACK_FAILED;
1691
1692         bnx2x_netif_stop(bp, 1);
1693         bnx2x_acquire_phy_lock(bp);
1694
1695         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1696         if (res) {
1697                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1698                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1699         }
1700
1701         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1702         if (res) {
1703                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1704                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1705         }
1706
1707         bnx2x_release_phy_lock(bp);
1708         bnx2x_netif_start(bp);
1709
1710         return rc;
1711 }
1712
1713 #define CRC32_RESIDUAL                  0xdebb20e3
1714
1715 static int bnx2x_test_nvram(struct bnx2x *bp)
1716 {
1717         static const struct {
1718                 int offset;
1719                 int size;
1720         } nvram_tbl[] = {
1721                 {     0,  0x14 }, /* bootstrap */
1722                 {  0x14,  0xec }, /* dir */
1723                 { 0x100, 0x350 }, /* manuf_info */
1724                 { 0x450,  0xf0 }, /* feature_info */
1725                 { 0x640,  0x64 }, /* upgrade_key_info */
1726                 { 0x708,  0x70 }, /* manuf_key_info */
1727                 {     0,     0 }
1728         };
1729         __be32 buf[0x350 / 4];
1730         u8 *data = (u8 *)buf;
1731         int i, rc;
1732         u32 magic, crc;
1733
1734         if (BP_NOMCP(bp))
1735                 return 0;
1736
1737         rc = bnx2x_nvram_read(bp, 0, data, 4);
1738         if (rc) {
1739                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1740                 goto test_nvram_exit;
1741         }
1742
1743         magic = be32_to_cpu(buf[0]);
1744         if (magic != 0x669955aa) {
1745                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1746                 rc = -ENODEV;
1747                 goto test_nvram_exit;
1748         }
1749
1750         for (i = 0; nvram_tbl[i].size; i++) {
1751
1752                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1753                                       nvram_tbl[i].size);
1754                 if (rc) {
1755                         DP(NETIF_MSG_PROBE,
1756                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1757                         goto test_nvram_exit;
1758                 }
1759
1760                 crc = ether_crc_le(nvram_tbl[i].size, data);
1761                 if (crc != CRC32_RESIDUAL) {
1762                         DP(NETIF_MSG_PROBE,
1763                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1764                         rc = -ENODEV;
1765                         goto test_nvram_exit;
1766                 }
1767         }
1768
1769 test_nvram_exit:
1770         return rc;
1771 }
1772
1773 static int bnx2x_test_intr(struct bnx2x *bp)
1774 {
1775         struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1776         int i, rc;
1777
1778         if (!netif_running(bp->dev))
1779                 return -ENODEV;
1780
1781         config->hdr.length = 0;
1782         if (CHIP_IS_E1(bp))
1783                 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1784         else
1785                 config->hdr.offset = BP_FUNC(bp);
1786         config->hdr.client_id = bp->fp->cl_id;
1787         config->hdr.reserved1 = 0;
1788
1789         bp->set_mac_pending = 1;
1790         smp_wmb();
1791         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1792                            U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1793                            U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1794         if (rc == 0) {
1795                 for (i = 0; i < 10; i++) {
1796                         if (!bp->set_mac_pending)
1797                                 break;
1798                         smp_rmb();
1799                         msleep_interruptible(10);
1800                 }
1801                 if (i == 10)
1802                         rc = -ENODEV;
1803         }
1804
1805         return rc;
1806 }
1807
1808 static void bnx2x_self_test(struct net_device *dev,
1809                             struct ethtool_test *etest, u64 *buf)
1810 {
1811         struct bnx2x *bp = netdev_priv(dev);
1812         u8 is_serdes;
1813         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1814                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1815                 etest->flags |= ETH_TEST_FL_FAILED;
1816                 return;
1817         }
1818
1819         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1820
1821         if (!netif_running(dev))
1822                 return;
1823
1824         /* offline tests are not supported in MF mode */
1825         if (IS_MF(bp))
1826                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1827         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1828
1829         if (etest->flags & ETH_TEST_FL_OFFLINE) {
1830                 int port = BP_PORT(bp);
1831                 u32 val;
1832                 u8 link_up;
1833
1834                 /* save current value of input enable for TX port IF */
1835                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1836                 /* disable input for TX port IF */
1837                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1838
1839                 link_up = bp->link_vars.link_up;
1840
1841                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1842                 bnx2x_nic_load(bp, LOAD_DIAG);
1843                 /* wait until link state is restored */
1844                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1845
1846                 if (bnx2x_test_registers(bp) != 0) {
1847                         buf[0] = 1;
1848                         etest->flags |= ETH_TEST_FL_FAILED;
1849                 }
1850                 if (bnx2x_test_memory(bp) != 0) {
1851                         buf[1] = 1;
1852                         etest->flags |= ETH_TEST_FL_FAILED;
1853                 }
1854
1855                 buf[2] = bnx2x_test_loopback(bp, link_up);
1856                 if (buf[2] != 0)
1857                         etest->flags |= ETH_TEST_FL_FAILED;
1858
1859                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1860
1861                 /* restore input for TX port IF */
1862                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1863
1864                 bnx2x_nic_load(bp, LOAD_NORMAL);
1865                 /* wait until link state is restored */
1866                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1867         }
1868         if (bnx2x_test_nvram(bp) != 0) {
1869                 buf[3] = 1;
1870                 etest->flags |= ETH_TEST_FL_FAILED;
1871         }
1872         if (bnx2x_test_intr(bp) != 0) {
1873                 buf[4] = 1;
1874                 etest->flags |= ETH_TEST_FL_FAILED;
1875         }
1876
1877         if (bnx2x_link_test(bp, is_serdes) != 0) {
1878                 buf[5] = 1;
1879                 etest->flags |= ETH_TEST_FL_FAILED;
1880         }
1881
1882 #ifdef BNX2X_EXTRA_DEBUG
1883         bnx2x_panic_dump(bp);
1884 #endif
1885 }
1886
1887 #define IS_PORT_STAT(i) \
1888         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1889 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1890 #define IS_MF_MODE_STAT(bp) \
1891                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1892
1893 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1894 {
1895         struct bnx2x *bp = netdev_priv(dev);
1896         int i, num_stats;
1897
1898         switch (stringset) {
1899         case ETH_SS_STATS:
1900                 if (is_multi(bp)) {
1901                         num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1902                                 BNX2X_NUM_Q_STATS;
1903                         if (!IS_MF_MODE_STAT(bp))
1904                                 num_stats += BNX2X_NUM_STATS;
1905                 } else {
1906                         if (IS_MF_MODE_STAT(bp)) {
1907                                 num_stats = 0;
1908                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
1909                                         if (IS_FUNC_STAT(i))
1910                                                 num_stats++;
1911                         } else
1912                                 num_stats = BNX2X_NUM_STATS;
1913                 }
1914                 return num_stats;
1915
1916         case ETH_SS_TEST:
1917                 return BNX2X_NUM_TESTS;
1918
1919         default:
1920                 return -EINVAL;
1921         }
1922 }
1923
1924 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1925 {
1926         struct bnx2x *bp = netdev_priv(dev);
1927         int i, j, k;
1928         char queue_name[MAX_QUEUE_NAME_LEN+1];
1929
1930         switch (stringset) {
1931         case ETH_SS_STATS:
1932                 if (is_multi(bp)) {
1933                         k = 0;
1934                         for_each_napi_queue(bp, i) {
1935                                 memset(queue_name, 0, sizeof(queue_name));
1936
1937                                 if (IS_FCOE_IDX(i))
1938                                         sprintf(queue_name, "fcoe");
1939                                 else
1940                                         sprintf(queue_name, "%d", i);
1941
1942                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1943                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
1944                                                 ETH_GSTRING_LEN,
1945                                                 bnx2x_q_stats_arr[j].string,
1946                                                 queue_name);
1947                                 k += BNX2X_NUM_Q_STATS;
1948                         }
1949                         if (IS_MF_MODE_STAT(bp))
1950                                 break;
1951                         for (j = 0; j < BNX2X_NUM_STATS; j++)
1952                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1953                                        bnx2x_stats_arr[j].string);
1954                 } else {
1955                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1956                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
1957                                         continue;
1958                                 strcpy(buf + j*ETH_GSTRING_LEN,
1959                                        bnx2x_stats_arr[i].string);
1960                                 j++;
1961                         }
1962                 }
1963                 break;
1964
1965         case ETH_SS_TEST:
1966                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1967                 break;
1968         }
1969 }
1970
1971 static void bnx2x_get_ethtool_stats(struct net_device *dev,
1972                                     struct ethtool_stats *stats, u64 *buf)
1973 {
1974         struct bnx2x *bp = netdev_priv(dev);
1975         u32 *hw_stats, *offset;
1976         int i, j, k;
1977
1978         if (is_multi(bp)) {
1979                 k = 0;
1980                 for_each_napi_queue(bp, i) {
1981                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1982                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1983                                 if (bnx2x_q_stats_arr[j].size == 0) {
1984                                         /* skip this counter */
1985                                         buf[k + j] = 0;
1986                                         continue;
1987                                 }
1988                                 offset = (hw_stats +
1989                                           bnx2x_q_stats_arr[j].offset);
1990                                 if (bnx2x_q_stats_arr[j].size == 4) {
1991                                         /* 4-byte counter */
1992                                         buf[k + j] = (u64) *offset;
1993                                         continue;
1994                                 }
1995                                 /* 8-byte counter */
1996                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1997                         }
1998                         k += BNX2X_NUM_Q_STATS;
1999                 }
2000                 if (IS_MF_MODE_STAT(bp))
2001                         return;
2002                 hw_stats = (u32 *)&bp->eth_stats;
2003                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
2004                         if (bnx2x_stats_arr[j].size == 0) {
2005                                 /* skip this counter */
2006                                 buf[k + j] = 0;
2007                                 continue;
2008                         }
2009                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2010                         if (bnx2x_stats_arr[j].size == 4) {
2011                                 /* 4-byte counter */
2012                                 buf[k + j] = (u64) *offset;
2013                                 continue;
2014                         }
2015                         /* 8-byte counter */
2016                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2017                 }
2018         } else {
2019                 hw_stats = (u32 *)&bp->eth_stats;
2020                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2021                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2022                                 continue;
2023                         if (bnx2x_stats_arr[i].size == 0) {
2024                                 /* skip this counter */
2025                                 buf[j] = 0;
2026                                 j++;
2027                                 continue;
2028                         }
2029                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2030                         if (bnx2x_stats_arr[i].size == 4) {
2031                                 /* 4-byte counter */
2032                                 buf[j] = (u64) *offset;
2033                                 j++;
2034                                 continue;
2035                         }
2036                         /* 8-byte counter */
2037                         buf[j] = HILO_U64(*offset, *(offset + 1));
2038                         j++;
2039                 }
2040         }
2041 }
2042
2043 static int bnx2x_set_phys_id(struct net_device *dev,
2044                              enum ethtool_phys_id_state state)
2045 {
2046         struct bnx2x *bp = netdev_priv(dev);
2047
2048         if (!netif_running(dev))
2049                 return -EAGAIN;
2050
2051         if (!bp->port.pmf)
2052                 return -EOPNOTSUPP;
2053
2054         switch (state) {
2055         case ETHTOOL_ID_ACTIVE:
2056                 return 1;       /* cycle on/off once per second */
2057
2058         case ETHTOOL_ID_ON:
2059                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2060                               LED_MODE_ON, SPEED_1000);
2061                 break;
2062
2063         case ETHTOOL_ID_OFF:
2064                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2065                               LED_MODE_FRONT_PANEL_OFF, 0);
2066
2067                 break;
2068
2069         case ETHTOOL_ID_INACTIVE:
2070                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2071                               LED_MODE_OPER,
2072                               bp->link_vars.line_speed);
2073         }
2074
2075         return 0;
2076 }
2077
2078 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2079                            void *rules __always_unused)
2080 {
2081         struct bnx2x *bp = netdev_priv(dev);
2082
2083         switch (info->cmd) {
2084         case ETHTOOL_GRXRINGS:
2085                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2086                 return 0;
2087
2088         default:
2089                 return -EOPNOTSUPP;
2090         }
2091 }
2092
2093 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2094                                 struct ethtool_rxfh_indir *indir)
2095 {
2096         struct bnx2x *bp = netdev_priv(dev);
2097         size_t copy_size =
2098                 min_t(size_t, indir->size, TSTORM_INDIRECTION_TABLE_SIZE);
2099
2100         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2101                 return -EOPNOTSUPP;
2102
2103         indir->size = TSTORM_INDIRECTION_TABLE_SIZE;
2104         memcpy(indir->ring_index, bp->rx_indir_table,
2105                copy_size * sizeof(bp->rx_indir_table[0]));
2106         return 0;
2107 }
2108
2109 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2110                                 const struct ethtool_rxfh_indir *indir)
2111 {
2112         struct bnx2x *bp = netdev_priv(dev);
2113         size_t i;
2114
2115         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2116                 return -EOPNOTSUPP;
2117
2118         /* Validate size and indices */
2119         if (indir->size != TSTORM_INDIRECTION_TABLE_SIZE)
2120                 return -EINVAL;
2121         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
2122                 if (indir->ring_index[i] >= BNX2X_NUM_ETH_QUEUES(bp))
2123                         return -EINVAL;
2124
2125         memcpy(bp->rx_indir_table, indir->ring_index,
2126                indir->size * sizeof(bp->rx_indir_table[0]));
2127         bnx2x_push_indir_table(bp);
2128         return 0;
2129 }
2130
2131 static const struct ethtool_ops bnx2x_ethtool_ops = {
2132         .get_settings           = bnx2x_get_settings,
2133         .set_settings           = bnx2x_set_settings,
2134         .get_drvinfo            = bnx2x_get_drvinfo,
2135         .get_regs_len           = bnx2x_get_regs_len,
2136         .get_regs               = bnx2x_get_regs,
2137         .get_wol                = bnx2x_get_wol,
2138         .set_wol                = bnx2x_set_wol,
2139         .get_msglevel           = bnx2x_get_msglevel,
2140         .set_msglevel           = bnx2x_set_msglevel,
2141         .nway_reset             = bnx2x_nway_reset,
2142         .get_link               = bnx2x_get_link,
2143         .get_eeprom_len         = bnx2x_get_eeprom_len,
2144         .get_eeprom             = bnx2x_get_eeprom,
2145         .set_eeprom             = bnx2x_set_eeprom,
2146         .get_coalesce           = bnx2x_get_coalesce,
2147         .set_coalesce           = bnx2x_set_coalesce,
2148         .get_ringparam          = bnx2x_get_ringparam,
2149         .set_ringparam          = bnx2x_set_ringparam,
2150         .get_pauseparam         = bnx2x_get_pauseparam,
2151         .set_pauseparam         = bnx2x_set_pauseparam,
2152         .self_test              = bnx2x_self_test,
2153         .get_sset_count         = bnx2x_get_sset_count,
2154         .get_strings            = bnx2x_get_strings,
2155         .set_phys_id            = bnx2x_set_phys_id,
2156         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2157         .get_rxnfc              = bnx2x_get_rxnfc,
2158         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2159         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2160 };
2161
2162 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2163 {
2164         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2165 }