drivers/net/bnx2x/bnx2x_ethtool.c

   1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2011 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17 #include <linux/ethtool.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/types.h>
  20 #include <linux/sched.h>
  21 #include <linux/crc32.h>
  22
  23
  24 #include "bnx2x.h"
  25 #include "bnx2x_cmn.h"
  26 #include "bnx2x_dump.h"
  27 #include "bnx2x_init.h"
  28 #include "bnx2x_sp.h"
  29
  30 /* Note: in the format strings below %s is replaced by the queue-name which is
  31  * either its index or 'fcoe' for the fcoe queue. Make sure the format string
  32  * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
  33  */
  34 #define MAX_QUEUE_NAME_LEN      4
  35 static const struct {
  36         long offset;
  37         int size;
  38         char string[ETH_GSTRING_LEN];
  39 } bnx2x_q_stats_arr[] = {
  40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
  41         { Q_STATS_OFFSET32(error_bytes_received_hi),
  42                                                 8, "[%s]: rx_error_bytes" },
  43         { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
  44                                                 8, "[%s]: rx_ucast_packets" },
  45         { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
  46                                                 8, "[%s]: rx_mcast_packets" },
  47         { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
  48                                                 8, "[%s]: rx_bcast_packets" },
  49         { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
  50         { Q_STATS_OFFSET32(rx_err_discard_pkt),
  51                                          4, "[%s]: rx_phy_ip_err_discards"},
  52         { Q_STATS_OFFSET32(rx_skb_alloc_failed),
  53                                          4, "[%s]: rx_skb_alloc_discard" },
  54         { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
  55
  56 /* 10 */{ Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
  57         { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
  58                                                 8, "[%s]: tx_ucast_packets" },
  59         { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
  60                                                 8, "[%s]: tx_mcast_packets" },
  61         { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
  62                                                 8, "[%s]: tx_bcast_packets" }
  63 };
  64
  65 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
  66
  67 static const struct {
  68         long offset;
  69         int size;
  70         u32 flags;
  71 #define STATS_FLAGS_PORT                1
  72 #define STATS_FLAGS_FUNC                2
  73 #define STATS_FLAGS_BOTH                (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
  74         char string[ETH_GSTRING_LEN];
  75 } bnx2x_stats_arr[] = {
  76 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
  77                                 8, STATS_FLAGS_BOTH, "rx_bytes" },
  78         { STATS_OFFSET32(error_bytes_received_hi),
  79                                 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
  80         { STATS_OFFSET32(total_unicast_packets_received_hi),
  81                                 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
  82         { STATS_OFFSET32(total_multicast_packets_received_hi),
  83                                 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
  84         { STATS_OFFSET32(total_broadcast_packets_received_hi),
  85                                 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
  86         { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
  87                                 8, STATS_FLAGS_PORT, "rx_crc_errors" },
  88         { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
  89                                 8, STATS_FLAGS_PORT, "rx_align_errors" },
  90         { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
  91                                 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
  92         { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
  93                                 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
  94 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
  95                                 8, STATS_FLAGS_PORT, "rx_fragments" },
  96         { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
  97                                 8, STATS_FLAGS_PORT, "rx_jabbers" },
  98         { STATS_OFFSET32(no_buff_discard_hi),
  99                                 8, STATS_FLAGS_BOTH, "rx_discards" },
 100         { STATS_OFFSET32(mac_filter_discard),
 101                                 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
 102         { STATS_OFFSET32(xxoverflow_discard),
 103                                 4, STATS_FLAGS_PORT, "rx_fw_discards" },
 104         { STATS_OFFSET32(brb_drop_hi),
 105                                 8, STATS_FLAGS_PORT, "rx_brb_discard" },
 106         { STATS_OFFSET32(brb_truncate_hi),
 107                                 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
 108         { STATS_OFFSET32(pause_frames_received_hi),
 109                                 8, STATS_FLAGS_PORT, "rx_pause_frames" },
 110         { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
 111                                 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
 112         { STATS_OFFSET32(nig_timer_max),
 113                         4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
 114 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
 115                                 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
 116         { STATS_OFFSET32(rx_skb_alloc_failed),
 117                                 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
 118         { STATS_OFFSET32(hw_csum_err),
 119                                 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
 120
 121         { STATS_OFFSET32(total_bytes_transmitted_hi),
 122                                 8, STATS_FLAGS_BOTH, "tx_bytes" },
 123         { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
 124                                 8, STATS_FLAGS_PORT, "tx_error_bytes" },
 125         { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
 126                                 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
 127         { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
 128                                 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
 129         { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
 130                                 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
 131         { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
 132                                 8, STATS_FLAGS_PORT, "tx_mac_errors" },
 133         { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
 134                                 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
 135 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
 136                                 8, STATS_FLAGS_PORT, "tx_single_collisions" },
 137         { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
 138                                 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
 139         { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
 140                                 8, STATS_FLAGS_PORT, "tx_deferred" },
 141         { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
 142                                 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
 143         { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
 144                                 8, STATS_FLAGS_PORT, "tx_late_collisions" },
 145         { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
 146                                 8, STATS_FLAGS_PORT, "tx_total_collisions" },
 147         { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
 148                                 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
 149         { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
 150                         8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
 151         { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
 152                         8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
 153         { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
 154                         8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
 155 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
 156                         8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
 157         { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
 158                         8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
 159         { STATS_OFFSET32(etherstatspktsover1522octets_hi),
 160                         8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
 161         { STATS_OFFSET32(pause_frames_sent_hi),
 162                                 8, STATS_FLAGS_PORT, "tx_pause_frames" }
 163 };
 164
 165 #define BNX2X_NUM_STATS         ARRAY_SIZE(bnx2x_stats_arr)
 166 static int bnx2x_get_port_type(struct bnx2x *bp)
 167 {
 168         int port_type;
 169         u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
 170         switch (bp->link_params.phy[phy_idx].media_type) {
 171         case ETH_PHY_SFP_FIBER:
 172         case ETH_PHY_XFP_FIBER:
 173         case ETH_PHY_KR:
 174         case ETH_PHY_CX4:
 175                 port_type = PORT_FIBRE;
 176                 break;
 177         case ETH_PHY_DA_TWINAX:
 178                 port_type = PORT_DA;
 179                 break;
 180         case ETH_PHY_BASE_T:
 181                 port_type = PORT_TP;
 182                 break;
 183         case ETH_PHY_NOT_PRESENT:
 184                 port_type = PORT_NONE;
 185                 break;
 186         case ETH_PHY_UNSPECIFIED:
 187         default:
 188                 port_type = PORT_OTHER;
 189                 break;
 190         }
 191         return port_type;
 192 }
 193
 194 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 195 {
 196         struct bnx2x *bp = netdev_priv(dev);
 197         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
 198
 199         /* Dual Media boards present all available port types */
 200         cmd->supported = bp->port.supported[cfg_idx] |
 201                 (bp->port.supported[cfg_idx ^ 1] &
 202                  (SUPPORTED_TP | SUPPORTED_FIBRE));
 203         cmd->advertising = bp->port.advertising[cfg_idx];
 204
 205         if ((bp->state == BNX2X_STATE_OPEN) &&
 206             !(bp->flags & MF_FUNC_DIS) &&
 207             (bp->link_vars.link_up)) {
 208                 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
 209                 cmd->duplex = bp->link_vars.duplex;
 210         } else {
 211                 ethtool_cmd_speed_set(
 212                         cmd, bp->link_params.req_line_speed[cfg_idx]);
 213                 cmd->duplex = bp->link_params.req_duplex[cfg_idx];
 214         }
 215
 216         if (IS_MF(bp))
 217                 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
 218
 219         cmd->port = bnx2x_get_port_type(bp);
 220
 221         cmd->phy_address = bp->mdio.prtad;
 222         cmd->transceiver = XCVR_INTERNAL;
 223
 224         if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
 225                 cmd->autoneg = AUTONEG_ENABLE;
 226         else
 227                 cmd->autoneg = AUTONEG_DISABLE;
 228
 229         cmd->maxtxpkt = 0;
 230         cmd->maxrxpkt = 0;
 231
 232         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 233            DP_LEVEL "  supported 0x%x  advertising 0x%x  speed %u\n"
 234            DP_LEVEL "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 235            DP_LEVEL "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 236            cmd->cmd, cmd->supported, cmd->advertising,
 237            ethtool_cmd_speed(cmd),
 238            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 239            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 240
 241         return 0;
 242 }
 243
 244 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 245 {
 246         struct bnx2x *bp = netdev_priv(dev);
 247         u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
 248         u32 speed;
 249
 250         if (IS_MF_SD(bp))
 251                 return 0;
 252
 253         DP(NETIF_MSG_LINK, "ethtool_cmd: cmd %d\n"
 254            "  supported 0x%x  advertising 0x%x  speed %u\n"
 255            "  duplex %d  port %d  phy_address %d  transceiver %d\n"
 256            "  autoneg %d  maxtxpkt %d  maxrxpkt %d\n",
 257            cmd->cmd, cmd->supported, cmd->advertising,
 258            ethtool_cmd_speed(cmd),
 259            cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
 260            cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
 261
 262         speed = ethtool_cmd_speed(cmd);
 263
 264         if (IS_MF_SI(bp)) {
 265                 u32 part;
 266                 u32 line_speed = bp->link_vars.line_speed;
 267
 268                 /* use 10G if no link detected */
 269                 if (!line_speed)
 270                         line_speed = 10000;
 271
 272                 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
 273                         BNX2X_DEV_INFO("To set speed BC %X or higher "
 274                                        "is required, please upgrade BC\n",
 275                                        REQ_BC_VER_4_SET_MF_BW);
 276                         return -EINVAL;
 277                 }
 278
 279                 part = (speed * 100) / line_speed;
 280
 281                 if (line_speed < speed || !part) {
 282                         BNX2X_DEV_INFO("Speed setting should be in a range "
 283                                        "from 1%% to 100%% "
 284                                        "of actual line speed\n");
 285                         return -EINVAL;
 286                 }
 287
 288                 if (bp->state != BNX2X_STATE_OPEN)
 289                         /* store value for following "load" */
 290                         bp->pending_max = part;
 291                 else
 292                         bnx2x_update_max_mf_config(bp, part);
 293
 294                 return 0;
 295         }
 296
 297         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 298         old_multi_phy_config = bp->link_params.multi_phy_config;
 299         switch (cmd->port) {
 300         case PORT_TP:
 301                 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
 302                         break; /* no port change */
 303
 304                 if (!(bp->port.supported[0] & SUPPORTED_TP ||
 305                       bp->port.supported[1] & SUPPORTED_TP)) {
 306                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 307                         return -EINVAL;
 308                 }
 309                 bp->link_params.multi_phy_config &=
 310                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 311                 if (bp->link_params.multi_phy_config &
 312                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 313                         bp->link_params.multi_phy_config |=
 314                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 315                 else
 316                         bp->link_params.multi_phy_config |=
 317                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 318                 break;
 319         case PORT_FIBRE:
 320                 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
 321                         break; /* no port change */
 322
 323                 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
 324                       bp->port.supported[1] & SUPPORTED_FIBRE)) {
 325                         DP(NETIF_MSG_LINK, "Unsupported port type\n");
 326                         return -EINVAL;
 327                 }
 328                 bp->link_params.multi_phy_config &=
 329                         ~PORT_HW_CFG_PHY_SELECTION_MASK;
 330                 if (bp->link_params.multi_phy_config &
 331                     PORT_HW_CFG_PHY_SWAPPED_ENABLED)
 332                         bp->link_params.multi_phy_config |=
 333                         PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
 334                 else
 335                         bp->link_params.multi_phy_config |=
 336                         PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
 337                 break;
 338         default:
 339                 DP(NETIF_MSG_LINK, "Unsupported port type\n");
 340                 return -EINVAL;
 341         }
 342         /* Save new config in case command complete successuly */
 343         new_multi_phy_config = bp->link_params.multi_phy_config;
 344         /* Get the new cfg_idx */
 345         cfg_idx = bnx2x_get_link_cfg_idx(bp);
 346         /* Restore old config in case command failed */
 347         bp->link_params.multi_phy_config = old_multi_phy_config;
 348         DP(NETIF_MSG_LINK, "cfg_idx = %x\n", cfg_idx);
 349
 350         if (cmd->autoneg == AUTONEG_ENABLE) {
 351                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
 352                         DP(NETIF_MSG_LINK, "Autoneg not supported\n");
 353                         return -EINVAL;
 354                 }
 355
 356                 /* advertise the requested speed and duplex if supported */
 357                 cmd->advertising &= bp->port.supported[cfg_idx];
 358
 359                 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
 360                 bp->link_params.req_duplex[cfg_idx] = DUPLEX_FULL;
 361                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Autoneg |
 362                                          cmd->advertising);
 363
 364         } else { /* forced speed */
 365                 /* advertise the requested speed and duplex if supported */
 366                 switch (speed) {
 367                 case SPEED_10:
 368                         if (cmd->duplex == DUPLEX_FULL) {
 369                                 if (!(bp->port.supported[cfg_idx] &
 370                                       SUPPORTED_10baseT_Full)) {
 371                                         DP(NETIF_MSG_LINK,
 372                                            "10M full not supported\n");
 373                                         return -EINVAL;
 374                                 }
 375
 376                                 advertising = (ADVERTISED_10baseT_Full |
 377                                                ADVERTISED_TP);
 378                         } else {
 379                                 if (!(bp->port.supported[cfg_idx] &
 380                                       SUPPORTED_10baseT_Half)) {
 381                                         DP(NETIF_MSG_LINK,
 382                                            "10M half not supported\n");
 383                                         return -EINVAL;
 384                                 }
 385
 386                                 advertising = (ADVERTISED_10baseT_Half |
 387                                                ADVERTISED_TP);
 388                         }
 389                         break;
 390
 391                 case SPEED_100:
 392                         if (cmd->duplex == DUPLEX_FULL) {
 393                                 if (!(bp->port.supported[cfg_idx] &
 394                                                 SUPPORTED_100baseT_Full)) {
 395                                         DP(NETIF_MSG_LINK,
 396                                            "100M full not supported\n");
 397                                         return -EINVAL;
 398                                 }
 399
 400                                 advertising = (ADVERTISED_100baseT_Full |
 401                                                ADVERTISED_TP);
 402                         } else {
 403                                 if (!(bp->port.supported[cfg_idx] &
 404                                                 SUPPORTED_100baseT_Half)) {
 405                                         DP(NETIF_MSG_LINK,
 406                                            "100M half not supported\n");
 407                                         return -EINVAL;
 408                                 }
 409
 410                                 advertising = (ADVERTISED_100baseT_Half |
 411                                                ADVERTISED_TP);
 412                         }
 413                         break;
 414
 415                 case SPEED_1000:
 416                         if (cmd->duplex != DUPLEX_FULL) {
 417                                 DP(NETIF_MSG_LINK, "1G half not supported\n");
 418                                 return -EINVAL;
 419                         }
 420
 421                         if (!(bp->port.supported[cfg_idx] &
 422                               SUPPORTED_1000baseT_Full)) {
 423                                 DP(NETIF_MSG_LINK, "1G full not supported\n");
 424                                 return -EINVAL;
 425                         }
 426
 427                         advertising = (ADVERTISED_1000baseT_Full |
 428                                        ADVERTISED_TP);
 429                         break;
 430
 431                 case SPEED_2500:
 432                         if (cmd->duplex != DUPLEX_FULL) {
 433                                 DP(NETIF_MSG_LINK,
 434                                    "2.5G half not supported\n");
 435                                 return -EINVAL;
 436                         }
 437
 438                         if (!(bp->port.supported[cfg_idx]
 439                               & SUPPORTED_2500baseX_Full)) {
 440                                 DP(NETIF_MSG_LINK,
 441                                    "2.5G full not supported\n");
 442                                 return -EINVAL;
 443                         }
 444
 445                         advertising = (ADVERTISED_2500baseX_Full |
 446                                        ADVERTISED_TP);
 447                         break;
 448
 449                 case SPEED_10000:
 450                         if (cmd->duplex != DUPLEX_FULL) {
 451                                 DP(NETIF_MSG_LINK, "10G half not supported\n");
 452                                 return -EINVAL;
 453                         }
 454
 455                         if (!(bp->port.supported[cfg_idx]
 456                               & SUPPORTED_10000baseT_Full)) {
 457                                 DP(NETIF_MSG_LINK, "10G full not supported\n");
 458                                 return -EINVAL;
 459                         }
 460
 461                         advertising = (ADVERTISED_10000baseT_Full |
 462                                        ADVERTISED_FIBRE);
 463                         break;
 464
 465                 default:
 466                         DP(NETIF_MSG_LINK, "Unsupported speed %u\n", speed);
 467                         return -EINVAL;
 468                 }
 469
 470                 bp->link_params.req_line_speed[cfg_idx] = speed;
 471                 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
 472                 bp->port.advertising[cfg_idx] = advertising;
 473         }
 474
 475         DP(NETIF_MSG_LINK, "req_line_speed %d\n"
 476            DP_LEVEL "  req_duplex %d  advertising 0x%x\n",
 477            bp->link_params.req_line_speed[cfg_idx],
 478            bp->link_params.req_duplex[cfg_idx],
 479            bp->port.advertising[cfg_idx]);
 480
 481         /* Set new config */
 482         bp->link_params.multi_phy_config = new_multi_phy_config;
 483         if (netif_running(dev)) {
 484                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 485                 bnx2x_link_set(bp);
 486         }
 487
 488         return 0;
 489 }
 490
 491 #define IS_E1_ONLINE(info)      (((info) & RI_E1_ONLINE) == RI_E1_ONLINE)
 492 #define IS_E1H_ONLINE(info)     (((info) & RI_E1H_ONLINE) == RI_E1H_ONLINE)
 493 #define IS_E2_ONLINE(info)      (((info) & RI_E2_ONLINE) == RI_E2_ONLINE)
 494
 495 static int bnx2x_get_regs_len(struct net_device *dev)
 496 {
 497         struct bnx2x *bp = netdev_priv(dev);
 498         int regdump_len = 0;
 499         int i, j, k;
 500
 501         if (CHIP_IS_E1(bp)) {
 502                 for (i = 0; i < REGS_COUNT; i++)
 503                         if (IS_E1_ONLINE(reg_addrs[i].info))
 504                                 regdump_len += reg_addrs[i].size;
 505
 506                 for (i = 0; i < WREGS_COUNT_E1; i++)
 507                         if (IS_E1_ONLINE(wreg_addrs_e1[i].info))
 508                                 regdump_len += wreg_addrs_e1[i].size *
 509                                         (1 + wreg_addrs_e1[i].read_regs_count);
 510
 511         } else if (CHIP_IS_E1H(bp)) {
 512                 for (i = 0; i < REGS_COUNT; i++)
 513                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 514                                 regdump_len += reg_addrs[i].size;
 515
 516                 for (i = 0; i < WREGS_COUNT_E1H; i++)
 517                         if (IS_E1H_ONLINE(wreg_addrs_e1h[i].info))
 518                                 regdump_len += wreg_addrs_e1h[i].size *
 519                                         (1 + wreg_addrs_e1h[i].read_regs_count);
 520         } else if (CHIP_IS_E2(bp)) {
 521                 for (i = 0; i < REGS_COUNT; i++)
 522                         if (IS_E2_ONLINE(reg_addrs[i].info))
 523                                 regdump_len += reg_addrs[i].size;
 524
 525                 for (i = 0; i < WREGS_COUNT_E2; i++)
 526                         if (IS_E2_ONLINE(wreg_addrs_e2[i].info))
 527                                 regdump_len += wreg_addrs_e2[i].size *
 528                                         (1 + wreg_addrs_e2[i].read_regs_count);
 529
 530                 for (i = 0; i < PAGE_MODE_VALUES_E2; i++)
 531                         for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
 532                                 for (k = 0; k < PAGE_READ_REGS_E2; k++)
 533                                         if (IS_E2_ONLINE(page_read_regs_e2[k].
 534                                                          info))
 535                                                 regdump_len +=
 536                                                 page_read_regs_e2[k].size;
 537                         }
 538         }
 539         regdump_len *= 4;
 540         regdump_len += sizeof(struct dump_hdr);
 541
 542         return regdump_len;
 543 }
 544
 545 static inline void bnx2x_read_pages_regs_e2(struct bnx2x *bp, u32 *p)
 546 {
 547         u32 i, j, k, n;
 548
 549         for (i = 0; i < PAGE_MODE_VALUES_E2; i++) {
 550                 for (j = 0; j < PAGE_WRITE_REGS_E2; j++) {
 551                         REG_WR(bp, page_write_regs_e2[j], page_vals_e2[i]);
 552                         for (k = 0; k < PAGE_READ_REGS_E2; k++)
 553                                 if (IS_E2_ONLINE(page_read_regs_e2[k].info))
 554                                         for (n = 0; n <
 555                                               page_read_regs_e2[k].size; n++)
 556                                                 *p++ = REG_RD(bp,
 557                                         page_read_regs_e2[k].addr + n*4);
 558                 }
 559         }
 560 }
 561
 562 static void bnx2x_get_regs(struct net_device *dev,
 563                            struct ethtool_regs *regs, void *_p)
 564 {
 565         u32 *p = _p, i, j;
 566         struct bnx2x *bp = netdev_priv(dev);
 567         struct dump_hdr dump_hdr = {0};
 568
 569         regs->version = 0;
 570         memset(p, 0, regs->len);
 571
 572         if (!netif_running(bp->dev))
 573                 return;
 574
 575         /* Disable parity attentions as long as following dump may
 576          * cause false alarms by reading never written registers. We
 577          * will re-enable parity attentions right after the dump.
 578          */
 579         bnx2x_disable_blocks_parity(bp);
 580
 581         dump_hdr.hdr_size = (sizeof(struct dump_hdr) / 4) - 1;
 582         dump_hdr.dump_sign = dump_sign_all;
 583         dump_hdr.xstorm_waitp = REG_RD(bp, XSTORM_WAITP_ADDR);
 584         dump_hdr.tstorm_waitp = REG_RD(bp, TSTORM_WAITP_ADDR);
 585         dump_hdr.ustorm_waitp = REG_RD(bp, USTORM_WAITP_ADDR);
 586         dump_hdr.cstorm_waitp = REG_RD(bp, CSTORM_WAITP_ADDR);
 587
 588         if (CHIP_IS_E1(bp))
 589                 dump_hdr.info = RI_E1_ONLINE;
 590         else if (CHIP_IS_E1H(bp))
 591                 dump_hdr.info = RI_E1H_ONLINE;
 592         else if (CHIP_IS_E2(bp))
 593                 dump_hdr.info = RI_E2_ONLINE |
 594                 (BP_PATH(bp) ? RI_PATH1_DUMP : RI_PATH0_DUMP);
 595
 596         memcpy(p, &dump_hdr, sizeof(struct dump_hdr));
 597         p += dump_hdr.hdr_size + 1;
 598
 599         if (CHIP_IS_E1(bp)) {
 600                 for (i = 0; i < REGS_COUNT; i++)
 601                         if (IS_E1_ONLINE(reg_addrs[i].info))
 602                                 for (j = 0; j < reg_addrs[i].size; j++)
 603                                         *p++ = REG_RD(bp,
 604                                                       reg_addrs[i].addr + j*4);
 605
 606         } else if (CHIP_IS_E1H(bp)) {
 607                 for (i = 0; i < REGS_COUNT; i++)
 608                         if (IS_E1H_ONLINE(reg_addrs[i].info))
 609                                 for (j = 0; j < reg_addrs[i].size; j++)
 610                                         *p++ = REG_RD(bp,
 611                                                       reg_addrs[i].addr + j*4);
 612
 613         } else if (CHIP_IS_E2(bp)) {
 614                 for (i = 0; i < REGS_COUNT; i++)
 615                         if (IS_E2_ONLINE(reg_addrs[i].info))
 616                                 for (j = 0; j < reg_addrs[i].size; j++)
 617                                         *p++ = REG_RD(bp,
 618                                               reg_addrs[i].addr + j*4);
 619
 620                 bnx2x_read_pages_regs_e2(bp, p);
 621         }
 622         /* Re-enable parity attentions */
 623         bnx2x_clear_blocks_parity(bp);
 624         if (CHIP_PARITY_ENABLED(bp))
 625                 bnx2x_enable_blocks_parity(bp);
 626 }
 627
 628 #define PHY_FW_VER_LEN                  20
 629
 630 static void bnx2x_get_drvinfo(struct net_device *dev,
 631                               struct ethtool_drvinfo *info)
 632 {
 633         struct bnx2x *bp = netdev_priv(dev);
 634         u8 phy_fw_ver[PHY_FW_VER_LEN];
 635
 636         strcpy(info->driver, DRV_MODULE_NAME);
 637         strcpy(info->version, DRV_MODULE_VERSION);
 638
 639         phy_fw_ver[0] = '\0';
 640         if (bp->port.pmf) {
 641                 bnx2x_acquire_phy_lock(bp);
 642                 bnx2x_get_ext_phy_fw_version(&bp->link_params,
 643                                              (bp->state != BNX2X_STATE_CLOSED),
 644                                              phy_fw_ver, PHY_FW_VER_LEN);
 645                 bnx2x_release_phy_lock(bp);
 646         }
 647
 648         strncpy(info->fw_version, bp->fw_ver, 32);
 649         snprintf(info->fw_version + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
 650                  "bc %d.%d.%d%s%s",
 651                  (bp->common.bc_ver & 0xff0000) >> 16,
 652                  (bp->common.bc_ver & 0xff00) >> 8,
 653                  (bp->common.bc_ver & 0xff),
 654                  ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
 655         strcpy(info->bus_info, pci_name(bp->pdev));
 656         info->n_stats = BNX2X_NUM_STATS;
 657         info->testinfo_len = BNX2X_NUM_TESTS;
 658         info->eedump_len = bp->common.flash_size;
 659         info->regdump_len = bnx2x_get_regs_len(dev);
 660 }
 661
 662 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 663 {
 664         struct bnx2x *bp = netdev_priv(dev);
 665
 666         if (bp->flags & NO_WOL_FLAG) {
 667                 wol->supported = 0;
 668                 wol->wolopts = 0;
 669         } else {
 670                 wol->supported = WAKE_MAGIC;
 671                 if (bp->wol)
 672                         wol->wolopts = WAKE_MAGIC;
 673                 else
 674                         wol->wolopts = 0;
 675         }
 676         memset(&wol->sopass, 0, sizeof(wol->sopass));
 677 }
 678
 679 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 680 {
 681         struct bnx2x *bp = netdev_priv(dev);
 682
 683         if (wol->wolopts & ~WAKE_MAGIC)
 684                 return -EINVAL;
 685
 686         if (wol->wolopts & WAKE_MAGIC) {
 687                 if (bp->flags & NO_WOL_FLAG)
 688                         return -EINVAL;
 689
 690                 bp->wol = 1;
 691         } else
 692                 bp->wol = 0;
 693
 694         return 0;
 695 }
 696
 697 static u32 bnx2x_get_msglevel(struct net_device *dev)
 698 {
 699         struct bnx2x *bp = netdev_priv(dev);
 700
 701         return bp->msg_enable;
 702 }
 703
 704 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
 705 {
 706         struct bnx2x *bp = netdev_priv(dev);
 707
 708         if (capable(CAP_NET_ADMIN)) {
 709                 /* dump MCP trace */
 710                 if (level & BNX2X_MSG_MCP)
 711                         bnx2x_fw_dump_lvl(bp, KERN_INFO);
 712                 bp->msg_enable = level;
 713         }
 714 }
 715
 716 static int bnx2x_nway_reset(struct net_device *dev)
 717 {
 718         struct bnx2x *bp = netdev_priv(dev);
 719
 720         if (!bp->port.pmf)
 721                 return 0;
 722
 723         if (netif_running(dev)) {
 724                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
 725                 bnx2x_link_set(bp);
 726         }
 727
 728         return 0;
 729 }
 730
 731 static u32 bnx2x_get_link(struct net_device *dev)
 732 {
 733         struct bnx2x *bp = netdev_priv(dev);
 734
 735         if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
 736                 return 0;
 737
 738         return bp->link_vars.link_up;
 739 }
 740
 741 static int bnx2x_get_eeprom_len(struct net_device *dev)
 742 {
 743         struct bnx2x *bp = netdev_priv(dev);
 744
 745         return bp->common.flash_size;
 746 }
 747
 748 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
 749 {
 750         int port = BP_PORT(bp);
 751         int count, i;
 752         u32 val = 0;
 753
 754         /* adjust timeout for emulation/FPGA */
 755         count = NVRAM_TIMEOUT_COUNT;
 756         if (CHIP_REV_IS_SLOW(bp))
 757                 count *= 100;
 758
 759         /* request access to nvram interface */
 760         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 761                (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
 762
 763         for (i = 0; i < count*10; i++) {
 764                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 765                 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
 766                         break;
 767
 768                 udelay(5);
 769         }
 770
 771         if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
 772                 DP(BNX2X_MSG_NVM, "cannot get access to nvram interface\n");
 773                 return -EBUSY;
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
 780 {
 781         int port = BP_PORT(bp);
 782         int count, i;
 783         u32 val = 0;
 784
 785         /* adjust timeout for emulation/FPGA */
 786         count = NVRAM_TIMEOUT_COUNT;
 787         if (CHIP_REV_IS_SLOW(bp))
 788                 count *= 100;
 789
 790         /* relinquish nvram interface */
 791         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
 792                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
 793
 794         for (i = 0; i < count*10; i++) {
 795                 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
 796                 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
 797                         break;
 798
 799                 udelay(5);
 800         }
 801
 802         if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
 803                 DP(BNX2X_MSG_NVM, "cannot free access to nvram interface\n");
 804                 return -EBUSY;
 805         }
 806
 807         return 0;
 808 }
 809
 810 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
 811 {
 812         u32 val;
 813
 814         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 815
 816         /* enable both bits, even on read */
 817         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 818                (val | MCPR_NVM_ACCESS_ENABLE_EN |
 819                       MCPR_NVM_ACCESS_ENABLE_WR_EN));
 820 }
 821
 822 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
 823 {
 824         u32 val;
 825
 826         val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
 827
 828         /* disable both bits, even after read */
 829         REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
 830                (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
 831                         MCPR_NVM_ACCESS_ENABLE_WR_EN)));
 832 }
 833
 834 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
 835                                   u32 cmd_flags)
 836 {
 837         int count, i, rc;
 838         u32 val;
 839
 840         /* build the command word */
 841         cmd_flags |= MCPR_NVM_COMMAND_DOIT;
 842
 843         /* need to clear DONE bit separately */
 844         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 845
 846         /* address of the NVRAM to read from */
 847         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 848                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 849
 850         /* issue a read command */
 851         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 852
 853         /* adjust timeout for emulation/FPGA */
 854         count = NVRAM_TIMEOUT_COUNT;
 855         if (CHIP_REV_IS_SLOW(bp))
 856                 count *= 100;
 857
 858         /* wait for completion */
 859         *ret_val = 0;
 860         rc = -EBUSY;
 861         for (i = 0; i < count; i++) {
 862                 udelay(5);
 863                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 864
 865                 if (val & MCPR_NVM_COMMAND_DONE) {
 866                         val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
 867                         /* we read nvram data in cpu order
 868                          * but ethtool sees it as an array of bytes
 869                          * converting to big-endian will do the work */
 870                         *ret_val = cpu_to_be32(val);
 871                         rc = 0;
 872                         break;
 873                 }
 874         }
 875
 876         return rc;
 877 }
 878
 879 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
 880                             int buf_size)
 881 {
 882         int rc;
 883         u32 cmd_flags;
 884         __be32 val;
 885
 886         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
 887                 DP(BNX2X_MSG_NVM,
 888                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
 889                    offset, buf_size);
 890                 return -EINVAL;
 891         }
 892
 893         if (offset + buf_size > bp->common.flash_size) {
 894                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
 895                                   " buf_size (0x%x) > flash_size (0x%x)\n",
 896                    offset, buf_size, bp->common.flash_size);
 897                 return -EINVAL;
 898         }
 899
 900         /* request access to nvram interface */
 901         rc = bnx2x_acquire_nvram_lock(bp);
 902         if (rc)
 903                 return rc;
 904
 905         /* enable access to nvram interface */
 906         bnx2x_enable_nvram_access(bp);
 907
 908         /* read the first word(s) */
 909         cmd_flags = MCPR_NVM_COMMAND_FIRST;
 910         while ((buf_size > sizeof(u32)) && (rc == 0)) {
 911                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 912                 memcpy(ret_buf, &val, 4);
 913
 914                 /* advance to the next dword */
 915                 offset += sizeof(u32);
 916                 ret_buf += sizeof(u32);
 917                 buf_size -= sizeof(u32);
 918                 cmd_flags = 0;
 919         }
 920
 921         if (rc == 0) {
 922                 cmd_flags |= MCPR_NVM_COMMAND_LAST;
 923                 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
 924                 memcpy(ret_buf, &val, 4);
 925         }
 926
 927         /* disable access to nvram interface */
 928         bnx2x_disable_nvram_access(bp);
 929         bnx2x_release_nvram_lock(bp);
 930
 931         return rc;
 932 }
 933
 934 static int bnx2x_get_eeprom(struct net_device *dev,
 935                             struct ethtool_eeprom *eeprom, u8 *eebuf)
 936 {
 937         struct bnx2x *bp = netdev_priv(dev);
 938         int rc;
 939
 940         if (!netif_running(dev))
 941                 return -EAGAIN;
 942
 943         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
 944            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
 945            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
 946            eeprom->len, eeprom->len);
 947
 948         /* parameters already validated in ethtool_get_eeprom */
 949
 950         rc = bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
 951
 952         return rc;
 953 }
 954
 955 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
 956                                    u32 cmd_flags)
 957 {
 958         int count, i, rc;
 959
 960         /* build the command word */
 961         cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
 962
 963         /* need to clear DONE bit separately */
 964         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
 965
 966         /* write the data */
 967         REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
 968
 969         /* address of the NVRAM to write to */
 970         REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
 971                (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
 972
 973         /* issue the write command */
 974         REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
 975
 976         /* adjust timeout for emulation/FPGA */
 977         count = NVRAM_TIMEOUT_COUNT;
 978         if (CHIP_REV_IS_SLOW(bp))
 979                 count *= 100;
 980
 981         /* wait for completion */
 982         rc = -EBUSY;
 983         for (i = 0; i < count; i++) {
 984                 udelay(5);
 985                 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
 986                 if (val & MCPR_NVM_COMMAND_DONE) {
 987                         rc = 0;
 988                         break;
 989                 }
 990         }
 991
 992         return rc;
 993 }
 994
 995 #define BYTE_OFFSET(offset)             (8 * (offset & 0x03))
 996
 997 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
 998                               int buf_size)
 999 {
1000         int rc;
1001         u32 cmd_flags;
1002         u32 align_offset;
1003         __be32 val;
1004
1005         if (offset + buf_size > bp->common.flash_size) {
1006                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1007                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1008                    offset, buf_size, bp->common.flash_size);
1009                 return -EINVAL;
1010         }
1011
1012         /* request access to nvram interface */
1013         rc = bnx2x_acquire_nvram_lock(bp);
1014         if (rc)
1015                 return rc;
1016
1017         /* enable access to nvram interface */
1018         bnx2x_enable_nvram_access(bp);
1019
1020         cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1021         align_offset = (offset & ~0x03);
1022         rc = bnx2x_nvram_read_dword(bp, align_offset, &val, cmd_flags);
1023
1024         if (rc == 0) {
1025                 val &= ~(0xff << BYTE_OFFSET(offset));
1026                 val |= (*data_buf << BYTE_OFFSET(offset));
1027
1028                 /* nvram data is returned as an array of bytes
1029                  * convert it back to cpu order */
1030                 val = be32_to_cpu(val);
1031
1032                 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1033                                              cmd_flags);
1034         }
1035
1036         /* disable access to nvram interface */
1037         bnx2x_disable_nvram_access(bp);
1038         bnx2x_release_nvram_lock(bp);
1039
1040         return rc;
1041 }
1042
1043 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1044                              int buf_size)
1045 {
1046         int rc;
1047         u32 cmd_flags;
1048         u32 val;
1049         u32 written_so_far;
1050
1051         if (buf_size == 1)      /* ethtool */
1052                 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1053
1054         if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1055                 DP(BNX2X_MSG_NVM,
1056                    "Invalid parameter: offset 0x%x  buf_size 0x%x\n",
1057                    offset, buf_size);
1058                 return -EINVAL;
1059         }
1060
1061         if (offset + buf_size > bp->common.flash_size) {
1062                 DP(BNX2X_MSG_NVM, "Invalid parameter: offset (0x%x) +"
1063                                   " buf_size (0x%x) > flash_size (0x%x)\n",
1064                    offset, buf_size, bp->common.flash_size);
1065                 return -EINVAL;
1066         }
1067
1068         /* request access to nvram interface */
1069         rc = bnx2x_acquire_nvram_lock(bp);
1070         if (rc)
1071                 return rc;
1072
1073         /* enable access to nvram interface */
1074         bnx2x_enable_nvram_access(bp);
1075
1076         written_so_far = 0;
1077         cmd_flags = MCPR_NVM_COMMAND_FIRST;
1078         while ((written_so_far < buf_size) && (rc == 0)) {
1079                 if (written_so_far == (buf_size - sizeof(u32)))
1080                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1081                 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
1082                         cmd_flags |= MCPR_NVM_COMMAND_LAST;
1083                 else if ((offset % NVRAM_PAGE_SIZE) == 0)
1084                         cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1085
1086                 memcpy(&val, data_buf, 4);
1087
1088                 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1089
1090                 /* advance to the next dword */
1091                 offset += sizeof(u32);
1092                 data_buf += sizeof(u32);
1093                 written_so_far += sizeof(u32);
1094                 cmd_flags = 0;
1095         }
1096
1097         /* disable access to nvram interface */
1098         bnx2x_disable_nvram_access(bp);
1099         bnx2x_release_nvram_lock(bp);
1100
1101         return rc;
1102 }
1103
1104 static int bnx2x_set_eeprom(struct net_device *dev,
1105                             struct ethtool_eeprom *eeprom, u8 *eebuf)
1106 {
1107         struct bnx2x *bp = netdev_priv(dev);
1108         int port = BP_PORT(bp);
1109         int rc = 0;
1110         u32 ext_phy_config;
1111         if (!netif_running(dev))
1112                 return -EAGAIN;
1113
1114         DP(BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1115            DP_LEVEL "  magic 0x%x  offset 0x%x (%d)  len 0x%x (%d)\n",
1116            eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1117            eeprom->len, eeprom->len);
1118
1119         /* parameters already validated in ethtool_set_eeprom */
1120
1121         /* PHY eeprom can be accessed only by the PMF */
1122         if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1123             !bp->port.pmf)
1124                 return -EINVAL;
1125
1126         ext_phy_config =
1127                 SHMEM_RD(bp,
1128                          dev_info.port_hw_config[port].external_phy_config);
1129
1130         if (eeprom->magic == 0x50485950) {
1131                 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1132                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1133
1134                 bnx2x_acquire_phy_lock(bp);
1135                 rc |= bnx2x_link_reset(&bp->link_params,
1136                                        &bp->link_vars, 0);
1137                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1138                                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1139                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1140                                        MISC_REGISTERS_GPIO_HIGH, port);
1141                 bnx2x_release_phy_lock(bp);
1142                 bnx2x_link_report(bp);
1143
1144         } else if (eeprom->magic == 0x50485952) {
1145                 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1146                 if (bp->state == BNX2X_STATE_OPEN) {
1147                         bnx2x_acquire_phy_lock(bp);
1148                         rc |= bnx2x_link_reset(&bp->link_params,
1149                                                &bp->link_vars, 1);
1150
1151                         rc |= bnx2x_phy_init(&bp->link_params,
1152                                              &bp->link_vars);
1153                         bnx2x_release_phy_lock(bp);
1154                         bnx2x_calc_fc_adv(bp);
1155                 }
1156         } else if (eeprom->magic == 0x53985943) {
1157                 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1158                 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1159                                        PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1160
1161                         /* DSP Remove Download Mode */
1162                         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1163                                        MISC_REGISTERS_GPIO_LOW, port);
1164
1165                         bnx2x_acquire_phy_lock(bp);
1166
1167                         bnx2x_sfx7101_sp_sw_reset(bp,
1168                                                 &bp->link_params.phy[EXT_PHY1]);
1169
1170                         /* wait 0.5 sec to allow it to run */
1171                         msleep(500);
1172                         bnx2x_ext_phy_hw_reset(bp, port);
1173                         msleep(500);
1174                         bnx2x_release_phy_lock(bp);
1175                 }
1176         } else
1177                 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1178
1179         return rc;
1180 }
1181
1182 static int bnx2x_get_coalesce(struct net_device *dev,
1183                               struct ethtool_coalesce *coal)
1184 {
1185         struct bnx2x *bp = netdev_priv(dev);
1186
1187         memset(coal, 0, sizeof(struct ethtool_coalesce));
1188
1189         coal->rx_coalesce_usecs = bp->rx_ticks;
1190         coal->tx_coalesce_usecs = bp->tx_ticks;
1191
1192         return 0;
1193 }
1194
1195 static int bnx2x_set_coalesce(struct net_device *dev,
1196                               struct ethtool_coalesce *coal)
1197 {
1198         struct bnx2x *bp = netdev_priv(dev);
1199
1200         bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1201         if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1202                 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1203
1204         bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1205         if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1206                 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1207
1208         if (netif_running(dev))
1209                 bnx2x_update_coalesce(bp);
1210
1211         return 0;
1212 }
1213
1214 static void bnx2x_get_ringparam(struct net_device *dev,
1215                                 struct ethtool_ringparam *ering)
1216 {
1217         struct bnx2x *bp = netdev_priv(dev);
1218
1219         ering->rx_max_pending = MAX_RX_AVAIL;
1220         ering->rx_mini_max_pending = 0;
1221         ering->rx_jumbo_max_pending = 0;
1222
1223         if (bp->rx_ring_size)
1224                 ering->rx_pending = bp->rx_ring_size;
1225         else
1226                 if (bp->state == BNX2X_STATE_OPEN && bp->num_queues)
1227                         ering->rx_pending = MAX_RX_AVAIL/bp->num_queues;
1228                 else
1229                         ering->rx_pending = MAX_RX_AVAIL;
1230
1231         ering->rx_mini_pending = 0;
1232         ering->rx_jumbo_pending = 0;
1233
1234         ering->tx_max_pending = MAX_TX_AVAIL;
1235         ering->tx_pending = bp->tx_ring_size;
1236 }
1237
1238 static int bnx2x_set_ringparam(struct net_device *dev,
1239                                struct ethtool_ringparam *ering)
1240 {
1241         struct bnx2x *bp = netdev_priv(dev);
1242
1243         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1244                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1245                 return -EAGAIN;
1246         }
1247
1248         if ((ering->rx_pending > MAX_RX_AVAIL) ||
1249             (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1250                                                     MIN_RX_SIZE_TPA)) ||
1251             (ering->tx_pending > MAX_TX_AVAIL) ||
1252             (ering->tx_pending <= MAX_SKB_FRAGS + 4))
1253                 return -EINVAL;
1254
1255         bp->rx_ring_size = ering->rx_pending;
1256         bp->tx_ring_size = ering->tx_pending;
1257
1258         return bnx2x_reload_if_running(dev);
1259 }
1260
1261 static void bnx2x_get_pauseparam(struct net_device *dev,
1262                                  struct ethtool_pauseparam *epause)
1263 {
1264         struct bnx2x *bp = netdev_priv(dev);
1265         int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1266         epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1267                            BNX2X_FLOW_CTRL_AUTO);
1268
1269         epause->rx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX) ==
1270                             BNX2X_FLOW_CTRL_RX);
1271         epause->tx_pause = ((bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX) ==
1272                             BNX2X_FLOW_CTRL_TX);
1273
1274         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1275            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1276            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1277 }
1278
1279 static int bnx2x_set_pauseparam(struct net_device *dev,
1280                                 struct ethtool_pauseparam *epause)
1281 {
1282         struct bnx2x *bp = netdev_priv(dev);
1283         u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1284         if (IS_MF(bp))
1285                 return 0;
1286
1287         DP(NETIF_MSG_LINK, "ethtool_pauseparam: cmd %d\n"
1288            DP_LEVEL "  autoneg %d  rx_pause %d  tx_pause %d\n",
1289            epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1290
1291         bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1292
1293         if (epause->rx_pause)
1294                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1295
1296         if (epause->tx_pause)
1297                 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1298
1299         if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1300                 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1301
1302         if (epause->autoneg) {
1303                 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1304                         DP(NETIF_MSG_LINK, "autoneg not supported\n");
1305                         return -EINVAL;
1306                 }
1307
1308                 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1309                         bp->link_params.req_flow_ctrl[cfg_idx] =
1310                                 BNX2X_FLOW_CTRL_AUTO;
1311                 }
1312         }
1313
1314         DP(NETIF_MSG_LINK,
1315            "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1316
1317         if (netif_running(dev)) {
1318                 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1319                 bnx2x_link_set(bp);
1320         }
1321
1322         return 0;
1323 }
1324
1325 static const struct {
1326         char string[ETH_GSTRING_LEN];
1327 } bnx2x_tests_str_arr[BNX2X_NUM_TESTS] = {
1328         { "register_test (offline)" },
1329         { "memory_test (offline)" },
1330         { "loopback_test (offline)" },
1331         { "nvram_test (online)" },
1332         { "interrupt_test (online)" },
1333         { "link_test (online)" },
1334         { "idle check (online)" }
1335 };
1336
1337 static int bnx2x_test_registers(struct bnx2x *bp)
1338 {
1339         int idx, i, rc = -ENODEV;
1340         u32 wr_val = 0;
1341         int port = BP_PORT(bp);
1342         static const struct {
1343                 u32 offset0;
1344                 u32 offset1;
1345                 u32 mask;
1346         } reg_tbl[] = {
1347 /* 0 */         { BRB1_REG_PAUSE_LOW_THRESHOLD_0,      4, 0x000003ff },
1348                 { DORQ_REG_DB_ADDR0,                   4, 0xffffffff },
1349                 { HC_REG_AGG_INT_0,                    4, 0x000003ff },
1350                 { PBF_REG_MAC_IF0_ENABLE,              4, 0x00000001 },
1351                 { PBF_REG_P0_INIT_CRD,                 4, 0x000007ff },
1352                 { PRS_REG_CID_PORT_0,                  4, 0x00ffffff },
1353                 { PXP2_REG_PSWRQ_CDU0_L2P,             4, 0x000fffff },
1354                 { PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR,    8, 0x0003ffff },
1355                 { PXP2_REG_PSWRQ_TM0_L2P,              4, 0x000fffff },
1356                 { PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR,   8, 0x0003ffff },
1357 /* 10 */        { PXP2_REG_PSWRQ_TSDM0_L2P,            4, 0x000fffff },
1358                 { QM_REG_CONNNUM_0,                    4, 0x000fffff },
1359                 { TM_REG_LIN0_MAX_ACTIVE_CID,          4, 0x0003ffff },
1360                 { SRC_REG_KEYRSS0_0,                  40, 0xffffffff },
1361                 { SRC_REG_KEYRSS0_7,                  40, 0xffffffff },
1362                 { XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
1363                 { XCM_REG_WU_DA_CNT_CMD00,             4, 0x00000003 },
1364                 { XCM_REG_GLB_DEL_ACK_MAX_CNT_0,       4, 0x000000ff },
1365                 { NIG_REG_LLH0_T_BIT,                  4, 0x00000001 },
1366                 { NIG_REG_EMAC0_IN_EN,                 4, 0x00000001 },
1367 /* 20 */        { NIG_REG_BMAC0_IN_EN,                 4, 0x00000001 },
1368                 { NIG_REG_XCM0_OUT_EN,                 4, 0x00000001 },
1369                 { NIG_REG_BRB0_OUT_EN,                 4, 0x00000001 },
1370                 { NIG_REG_LLH0_XCM_MASK,               4, 0x00000007 },
1371                 { NIG_REG_LLH0_ACPI_PAT_6_LEN,        68, 0x000000ff },
1372                 { NIG_REG_LLH0_ACPI_PAT_0_CRC,        68, 0xffffffff },
1373                 { NIG_REG_LLH0_DEST_MAC_0_0,         160, 0xffffffff },
1374                 { NIG_REG_LLH0_DEST_IP_0_1,          160, 0xffffffff },
1375                 { NIG_REG_LLH0_IPV4_IPV6_0,          160, 0x00000001 },
1376                 { NIG_REG_LLH0_DEST_UDP_0,           160, 0x0000ffff },
1377 /* 30 */        { NIG_REG_LLH0_DEST_TCP_0,           160, 0x0000ffff },
1378                 { NIG_REG_LLH0_VLAN_ID_0,            160, 0x00000fff },
1379                 { NIG_REG_XGXS_SERDES0_MODE_SEL,       4, 0x00000001 },
1380                 { NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001 },
1381                 { NIG_REG_STATUS_INTERRUPT_PORT0,      4, 0x07ffffff },
1382                 { NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
1383                 { NIG_REG_SERDES0_CTRL_PHY_ADDR,      16, 0x0000001f },
1384
1385                 { 0xffffffff, 0, 0x00000000 }
1386         };
1387
1388         if (!netif_running(bp->dev))
1389                 return rc;
1390
1391         /* Repeat the test twice:
1392            First by writing 0x00000000, second by writing 0xffffffff */
1393         for (idx = 0; idx < 2; idx++) {
1394
1395                 switch (idx) {
1396                 case 0:
1397                         wr_val = 0;
1398                         break;
1399                 case 1:
1400                         wr_val = 0xffffffff;
1401                         break;
1402                 }
1403
1404                 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
1405                         u32 offset, mask, save_val, val;
1406                         if (CHIP_IS_E2(bp) &&
1407                             reg_tbl[i].offset0 == HC_REG_AGG_INT_0)
1408                                 continue;
1409
1410                         offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
1411                         mask = reg_tbl[i].mask;
1412
1413                         save_val = REG_RD(bp, offset);
1414
1415                         REG_WR(bp, offset, wr_val & mask);
1416
1417                         val = REG_RD(bp, offset);
1418
1419                         /* Restore the original register's value */
1420                         REG_WR(bp, offset, save_val);
1421
1422                         /* verify value is as expected */
1423                         if ((val & mask) != (wr_val & mask)) {
1424                                 DP(NETIF_MSG_PROBE,
1425                                    "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
1426                                    offset, val, wr_val, mask);
1427                                 goto test_reg_exit;
1428                         }
1429                 }
1430         }
1431
1432         rc = 0;
1433
1434 test_reg_exit:
1435         return rc;
1436 }
1437
1438 static int bnx2x_test_memory(struct bnx2x *bp)
1439 {
1440         int i, j, rc = -ENODEV;
1441         u32 val;
1442         static const struct {
1443                 u32 offset;
1444                 int size;
1445         } mem_tbl[] = {
1446                 { CCM_REG_XX_DESCR_TABLE,   CCM_REG_XX_DESCR_TABLE_SIZE },
1447                 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
1448                 { CFC_REG_LINK_LIST,        CFC_REG_LINK_LIST_SIZE },
1449                 { DMAE_REG_CMD_MEM,         DMAE_REG_CMD_MEM_SIZE },
1450                 { TCM_REG_XX_DESCR_TABLE,   TCM_REG_XX_DESCR_TABLE_SIZE },
1451                 { UCM_REG_XX_DESCR_TABLE,   UCM_REG_XX_DESCR_TABLE_SIZE },
1452                 { XCM_REG_XX_DESCR_TABLE,   XCM_REG_XX_DESCR_TABLE_SIZE },
1453
1454                 { 0xffffffff, 0 }
1455         };
1456         static const struct {
1457                 char *name;
1458                 u32 offset;
1459                 u32 e1_mask;
1460                 u32 e1h_mask;
1461                 u32 e2_mask;
1462         } prty_tbl[] = {
1463                 { "CCM_PRTY_STS",  CCM_REG_CCM_PRTY_STS,   0x3ffc0, 0,   0 },
1464                 { "CFC_PRTY_STS",  CFC_REG_CFC_PRTY_STS,   0x2,     0x2, 0 },
1465                 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS, 0,       0,   0 },
1466                 { "TCM_PRTY_STS",  TCM_REG_TCM_PRTY_STS,   0x3ffc0, 0,   0 },
1467                 { "UCM_PRTY_STS",  UCM_REG_UCM_PRTY_STS,   0x3ffc0, 0,   0 },
1468                 { "XCM_PRTY_STS",  XCM_REG_XCM_PRTY_STS,   0x3ffc1, 0,   0 },
1469
1470                 { NULL, 0xffffffff, 0, 0, 0 }
1471         };
1472
1473         if (!netif_running(bp->dev))
1474                 return rc;
1475
1476         /* pre-Check the parity status */
1477         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1478                 val = REG_RD(bp, prty_tbl[i].offset);
1479                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1480                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1481                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1482                         DP(NETIF_MSG_HW,
1483                            "%s is 0x%x\n", prty_tbl[i].name, val);
1484                         goto test_mem_exit;
1485                 }
1486         }
1487
1488         /* Go through all the memories */
1489         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
1490                 for (j = 0; j < mem_tbl[i].size; j++)
1491                         REG_RD(bp, mem_tbl[i].offset + j*4);
1492
1493         /* Check the parity status */
1494         for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
1495                 val = REG_RD(bp, prty_tbl[i].offset);
1496                 if ((CHIP_IS_E1(bp) && (val & ~(prty_tbl[i].e1_mask))) ||
1497                     (CHIP_IS_E1H(bp) && (val & ~(prty_tbl[i].e1h_mask))) ||
1498                     (CHIP_IS_E2(bp) && (val & ~(prty_tbl[i].e2_mask)))) {
1499                         DP(NETIF_MSG_HW,
1500                            "%s is 0x%x\n", prty_tbl[i].name, val);
1501                         goto test_mem_exit;
1502                 }
1503         }
1504
1505         rc = 0;
1506
1507 test_mem_exit:
1508         return rc;
1509 }
1510
1511 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
1512 {
1513         int cnt = 1400;
1514
1515         if (link_up)
1516                 while (bnx2x_link_test(bp, is_serdes) && cnt--)
1517                         msleep(10);
1518 }
1519
1520 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode, u8 link_up)
1521 {
1522         unsigned int pkt_size, num_pkts, i;
1523         struct sk_buff *skb;
1524         unsigned char *packet;
1525         struct bnx2x_fastpath *fp_rx = &bp->fp[0];
1526         struct bnx2x_fastpath *fp_tx = &bp->fp[0];
1527         u16 tx_start_idx, tx_idx;
1528         u16 rx_start_idx, rx_idx;
1529         u16 pkt_prod, bd_prod;
1530         struct sw_tx_bd *tx_buf;
1531         struct eth_tx_start_bd *tx_start_bd;
1532         struct eth_tx_parse_bd_e1x  *pbd_e1x = NULL;
1533         struct eth_tx_parse_bd_e2  *pbd_e2 = NULL;
1534         dma_addr_t mapping;
1535         union eth_rx_cqe *cqe;
1536         u8 cqe_fp_flags;
1537         struct sw_rx_bd *rx_buf;
1538         u16 len;
1539         int rc = -ENODEV;
1540
1541         /* check the loopback mode */
1542         switch (loopback_mode) {
1543         case BNX2X_PHY_LOOPBACK:
1544                 if (bp->link_params.loopback_mode != LOOPBACK_XGXS)
1545                         return -EINVAL;
1546                 break;
1547         case BNX2X_MAC_LOOPBACK:
1548                 bp->link_params.loopback_mode = LOOPBACK_BMAC;
1549                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
1550                 break;
1551         default:
1552                 return -EINVAL;
1553         }
1554
1555         /* prepare the loopback packet */
1556         pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
1557                      bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
1558         skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
1559         if (!skb) {
1560                 rc = -ENOMEM;
1561                 goto test_loopback_exit;
1562         }
1563         packet = skb_put(skb, pkt_size);
1564         memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
1565         memset(packet + ETH_ALEN, 0, ETH_ALEN);
1566         memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
1567         for (i = ETH_HLEN; i < pkt_size; i++)
1568                 packet[i] = (unsigned char) (i & 0xff);
1569
1570         /* send the loopback packet */
1571         num_pkts = 0;
1572         tx_start_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1573         rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1574
1575         pkt_prod = fp_tx->tx_pkt_prod++;
1576         tx_buf = &fp_tx->tx_buf_ring[TX_BD(pkt_prod)];
1577         tx_buf->first_bd = fp_tx->tx_bd_prod;
1578         tx_buf->skb = skb;
1579         tx_buf->flags = 0;
1580
1581         bd_prod = TX_BD(fp_tx->tx_bd_prod);
1582         tx_start_bd = &fp_tx->tx_desc_ring[bd_prod].start_bd;
1583         mapping = dma_map_single(&bp->pdev->dev, skb->data,
1584                                  skb_headlen(skb), DMA_TO_DEVICE);
1585         tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
1586         tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
1587         tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
1588         tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
1589         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
1590         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
1591         SET_FLAG(tx_start_bd->general_data,
1592                  ETH_TX_START_BD_ETH_ADDR_TYPE,
1593                  UNICAST_ADDRESS);
1594         SET_FLAG(tx_start_bd->general_data,
1595                  ETH_TX_START_BD_HDR_NBDS,
1596                  1);
1597
1598         /* turn on parsing and get a BD */
1599         bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
1600
1601         pbd_e1x = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e1x;
1602         pbd_e2 = &fp_tx->tx_desc_ring[bd_prod].parse_bd_e2;
1603
1604         memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
1605         memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
1606
1607         wmb();
1608
1609         fp_tx->tx_db.data.prod += 2;
1610         barrier();
1611         DOORBELL(bp, fp_tx->index, fp_tx->tx_db.raw);
1612
1613         mmiowb();
1614
1615         num_pkts++;
1616         fp_tx->tx_bd_prod += 2; /* start + pbd */
1617
1618         udelay(100);
1619
1620         tx_idx = le16_to_cpu(*fp_tx->tx_cons_sb);
1621         if (tx_idx != tx_start_idx + num_pkts)
1622                 goto test_loopback_exit;
1623
1624         /* Unlike HC IGU won't generate an interrupt for status block
1625          * updates that have been performed while interrupts were
1626          * disabled.
1627          */
1628         if (bp->common.int_block == INT_BLOCK_IGU) {
1629                 /* Disable local BHes to prevent a dead-lock situation between
1630                  * sch_direct_xmit() and bnx2x_run_loopback() (calling
1631                  * bnx2x_tx_int()), as both are taking netif_tx_lock().
1632                  */
1633                 local_bh_disable();
1634                 bnx2x_tx_int(fp_tx);
1635                 local_bh_enable();
1636         }
1637
1638         rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
1639         if (rx_idx != rx_start_idx + num_pkts)
1640                 goto test_loopback_exit;
1641
1642         cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
1643         cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
1644         if (CQE_TYPE(cqe_fp_flags) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
1645                 goto test_loopback_rx_exit;
1646
1647         len = le16_to_cpu(cqe->fast_path_cqe.pkt_len);
1648         if (len != pkt_size)
1649                 goto test_loopback_rx_exit;
1650
1651         rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
1652         skb = rx_buf->skb;
1653         skb_reserve(skb, cqe->fast_path_cqe.placement_offset);
1654         for (i = ETH_HLEN; i < pkt_size; i++)
1655                 if (*(skb->data + i) != (unsigned char) (i & 0xff))
1656                         goto test_loopback_rx_exit;
1657
1658         rc = 0;
1659
1660 test_loopback_rx_exit:
1661
1662         fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
1663         fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
1664         fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
1665         fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
1666
1667         /* Update producers */
1668         bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
1669                              fp_rx->rx_sge_prod);
1670
1671 test_loopback_exit:
1672         bp->link_params.loopback_mode = LOOPBACK_NONE;
1673
1674         return rc;
1675 }
1676
1677 static int bnx2x_test_loopback(struct bnx2x *bp, u8 link_up)
1678 {
1679         int rc = 0, res;
1680
1681         if (BP_NOMCP(bp))
1682                 return rc;
1683
1684         if (!netif_running(bp->dev))
1685                 return BNX2X_LOOPBACK_FAILED;
1686
1687         bnx2x_netif_stop(bp, 1);
1688         bnx2x_acquire_phy_lock(bp);
1689
1690         res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK, link_up);
1691         if (res) {
1692                 DP(NETIF_MSG_PROBE, "  PHY loopback failed  (res %d)\n", res);
1693                 rc |= BNX2X_PHY_LOOPBACK_FAILED;
1694         }
1695
1696         res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK, link_up);
1697         if (res) {
1698                 DP(NETIF_MSG_PROBE, "  MAC loopback failed  (res %d)\n", res);
1699                 rc |= BNX2X_MAC_LOOPBACK_FAILED;
1700         }
1701
1702         bnx2x_release_phy_lock(bp);
1703         bnx2x_netif_start(bp);
1704
1705         return rc;
1706 }
1707
1708 #define CRC32_RESIDUAL                  0xdebb20e3
1709
1710 static int bnx2x_test_nvram(struct bnx2x *bp)
1711 {
1712         static const struct {
1713                 int offset;
1714                 int size;
1715         } nvram_tbl[] = {
1716                 {     0,  0x14 }, /* bootstrap */
1717                 {  0x14,  0xec }, /* dir */
1718                 { 0x100, 0x350 }, /* manuf_info */
1719                 { 0x450,  0xf0 }, /* feature_info */
1720                 { 0x640,  0x64 }, /* upgrade_key_info */
1721                 { 0x708,  0x70 }, /* manuf_key_info */
1722                 {     0,     0 }
1723         };
1724         __be32 buf[0x350 / 4];
1725         u8 *data = (u8 *)buf;
1726         int i, rc;
1727         u32 magic, crc;
1728
1729         if (BP_NOMCP(bp))
1730                 return 0;
1731
1732         rc = bnx2x_nvram_read(bp, 0, data, 4);
1733         if (rc) {
1734                 DP(NETIF_MSG_PROBE, "magic value read (rc %d)\n", rc);
1735                 goto test_nvram_exit;
1736         }
1737
1738         magic = be32_to_cpu(buf[0]);
1739         if (magic != 0x669955aa) {
1740                 DP(NETIF_MSG_PROBE, "magic value (0x%08x)\n", magic);
1741                 rc = -ENODEV;
1742                 goto test_nvram_exit;
1743         }
1744
1745         for (i = 0; nvram_tbl[i].size; i++) {
1746
1747                 rc = bnx2x_nvram_read(bp, nvram_tbl[i].offset, data,
1748                                       nvram_tbl[i].size);
1749                 if (rc) {
1750                         DP(NETIF_MSG_PROBE,
1751                            "nvram_tbl[%d] read data (rc %d)\n", i, rc);
1752                         goto test_nvram_exit;
1753                 }
1754
1755                 crc = ether_crc_le(nvram_tbl[i].size, data);
1756                 if (crc != CRC32_RESIDUAL) {
1757                         DP(NETIF_MSG_PROBE,
1758                            "nvram_tbl[%d] crc value (0x%08x)\n", i, crc);
1759                         rc = -ENODEV;
1760                         goto test_nvram_exit;
1761                 }
1762         }
1763
1764 test_nvram_exit:
1765         return rc;
1766 }
1767
1768 static int bnx2x_test_intr(struct bnx2x *bp)
1769 {
1770         struct mac_configuration_cmd *config = bnx2x_sp(bp, mac_config);
1771         int i, rc;
1772
1773         if (!netif_running(bp->dev))
1774                 return -ENODEV;
1775
1776         config->hdr.length = 0;
1777         if (CHIP_IS_E1(bp))
1778                 config->hdr.offset = (BP_PORT(bp) ? 32 : 0);
1779         else
1780                 config->hdr.offset = BP_FUNC(bp);
1781         config->hdr.client_id = bp->fp->cl_id;
1782         config->hdr.reserved1 = 0;
1783
1784         bp->set_mac_pending = 1;
1785         smp_wmb();
1786         rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_MAC, 0,
1787                            U64_HI(bnx2x_sp_mapping(bp, mac_config)),
1788                            U64_LO(bnx2x_sp_mapping(bp, mac_config)), 1);
1789         if (rc == 0) {
1790                 for (i = 0; i < 10; i++) {
1791                         if (!bp->set_mac_pending)
1792                                 break;
1793                         smp_rmb();
1794                         msleep_interruptible(10);
1795                 }
1796                 if (i == 10)
1797                         rc = -ENODEV;
1798         }
1799
1800         return rc;
1801 }
1802
1803 static void bnx2x_self_test(struct net_device *dev,
1804                             struct ethtool_test *etest, u64 *buf)
1805 {
1806         struct bnx2x *bp = netdev_priv(dev);
1807         u8 is_serdes;
1808         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1809                 printk(KERN_ERR "Handling parity error recovery. Try again later\n");
1810                 etest->flags |= ETH_TEST_FL_FAILED;
1811                 return;
1812         }
1813
1814         memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS);
1815
1816         if (!netif_running(dev))
1817                 return;
1818
1819         /* offline tests are not supported in MF mode */
1820         if (IS_MF(bp))
1821                 etest->flags &= ~ETH_TEST_FL_OFFLINE;
1822         is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
1823
1824         if (etest->flags & ETH_TEST_FL_OFFLINE) {
1825                 int port = BP_PORT(bp);
1826                 u32 val;
1827                 u8 link_up;
1828
1829                 /* save current value of input enable for TX port IF */
1830                 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
1831                 /* disable input for TX port IF */
1832                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
1833
1834                 link_up = bp->link_vars.link_up;
1835
1836                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1837                 bnx2x_nic_load(bp, LOAD_DIAG);
1838                 /* wait until link state is restored */
1839                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1840
1841                 if (bnx2x_test_registers(bp) != 0) {
1842                         buf[0] = 1;
1843                         etest->flags |= ETH_TEST_FL_FAILED;
1844                 }
1845                 if (bnx2x_test_memory(bp) != 0) {
1846                         buf[1] = 1;
1847                         etest->flags |= ETH_TEST_FL_FAILED;
1848                 }
1849
1850                 buf[2] = bnx2x_test_loopback(bp, link_up);
1851                 if (buf[2] != 0)
1852                         etest->flags |= ETH_TEST_FL_FAILED;
1853
1854                 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
1855
1856                 /* restore input for TX port IF */
1857                 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
1858
1859                 bnx2x_nic_load(bp, LOAD_NORMAL);
1860                 /* wait until link state is restored */
1861                 bnx2x_wait_for_link(bp, link_up, is_serdes);
1862         }
1863         if (bnx2x_test_nvram(bp) != 0) {
1864                 buf[3] = 1;
1865                 etest->flags |= ETH_TEST_FL_FAILED;
1866         }
1867         if (bnx2x_test_intr(bp) != 0) {
1868                 buf[4] = 1;
1869                 etest->flags |= ETH_TEST_FL_FAILED;
1870         }
1871
1872         if (bnx2x_link_test(bp, is_serdes) != 0) {
1873                 buf[5] = 1;
1874                 etest->flags |= ETH_TEST_FL_FAILED;
1875         }
1876
1877 #ifdef BNX2X_EXTRA_DEBUG
1878         bnx2x_panic_dump(bp);
1879 #endif
1880 }
1881
1882 #define IS_PORT_STAT(i) \
1883         ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
1884 #define IS_FUNC_STAT(i)         (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
1885 #define IS_MF_MODE_STAT(bp) \
1886                         (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
1887
1888 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
1889 {
1890         struct bnx2x *bp = netdev_priv(dev);
1891         int i, num_stats;
1892
1893         switch (stringset) {
1894         case ETH_SS_STATS:
1895                 if (is_multi(bp)) {
1896                         num_stats = BNX2X_NUM_STAT_QUEUES(bp) *
1897                                 BNX2X_NUM_Q_STATS;
1898                         if (!IS_MF_MODE_STAT(bp))
1899                                 num_stats += BNX2X_NUM_STATS;
1900                 } else {
1901                         if (IS_MF_MODE_STAT(bp)) {
1902                                 num_stats = 0;
1903                                 for (i = 0; i < BNX2X_NUM_STATS; i++)
1904                                         if (IS_FUNC_STAT(i))
1905                                                 num_stats++;
1906                         } else
1907                                 num_stats = BNX2X_NUM_STATS;
1908                 }
1909                 return num_stats;
1910
1911         case ETH_SS_TEST:
1912                 return BNX2X_NUM_TESTS;
1913
1914         default:
1915                 return -EINVAL;
1916         }
1917 }
1918
1919 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
1920 {
1921         struct bnx2x *bp = netdev_priv(dev);
1922         int i, j, k;
1923         char queue_name[MAX_QUEUE_NAME_LEN+1];
1924
1925         switch (stringset) {
1926         case ETH_SS_STATS:
1927                 if (is_multi(bp)) {
1928                         k = 0;
1929                         for_each_napi_queue(bp, i) {
1930                                 memset(queue_name, 0, sizeof(queue_name));
1931
1932                                 if (IS_FCOE_IDX(i))
1933                                         sprintf(queue_name, "fcoe");
1934                                 else
1935                                         sprintf(queue_name, "%d", i);
1936
1937                                 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
1938                                         snprintf(buf + (k + j)*ETH_GSTRING_LEN,
1939                                                 ETH_GSTRING_LEN,
1940                                                 bnx2x_q_stats_arr[j].string,
1941                                                 queue_name);
1942                                 k += BNX2X_NUM_Q_STATS;
1943                         }
1944                         if (IS_MF_MODE_STAT(bp))
1945                                 break;
1946                         for (j = 0; j < BNX2X_NUM_STATS; j++)
1947                                 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
1948                                        bnx2x_stats_arr[j].string);
1949                 } else {
1950                         for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
1951                                 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
1952                                         continue;
1953                                 strcpy(buf + j*ETH_GSTRING_LEN,
1954                                        bnx2x_stats_arr[i].string);
1955                                 j++;
1956                         }
1957                 }
1958                 break;
1959
1960         case ETH_SS_TEST:
1961                 memcpy(buf, bnx2x_tests_str_arr, sizeof(bnx2x_tests_str_arr));
1962                 break;
1963         }
1964 }
1965
1966 static void bnx2x_get_ethtool_stats(struct net_device *dev,
1967                                     struct ethtool_stats *stats, u64 *buf)
1968 {
1969         struct bnx2x *bp = netdev_priv(dev);
1970         u32 *hw_stats, *offset;
1971         int i, j, k;
1972
1973         if (is_multi(bp)) {
1974                 k = 0;
1975                 for_each_napi_queue(bp, i) {
1976                         hw_stats = (u32 *)&bp->fp[i].eth_q_stats;
1977                         for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
1978                                 if (bnx2x_q_stats_arr[j].size == 0) {
1979                                         /* skip this counter */
1980                                         buf[k + j] = 0;
1981                                         continue;
1982                                 }
1983                                 offset = (hw_stats +
1984                                           bnx2x_q_stats_arr[j].offset);
1985                                 if (bnx2x_q_stats_arr[j].size == 4) {
1986                                         /* 4-byte counter */
1987                                         buf[k + j] = (u64) *offset;
1988                                         continue;
1989                                 }
1990                                 /* 8-byte counter */
1991                                 buf[k + j] = HILO_U64(*offset, *(offset + 1));
1992                         }
1993                         k += BNX2X_NUM_Q_STATS;
1994                 }
1995                 if (IS_MF_MODE_STAT(bp))
1996                         return;
1997                 hw_stats = (u32 *)&bp->eth_stats;
1998                 for (j = 0; j < BNX2X_NUM_STATS; j++) {
1999                         if (bnx2x_stats_arr[j].size == 0) {
2000                                 /* skip this counter */
2001                                 buf[k + j] = 0;
2002                                 continue;
2003                         }
2004                         offset = (hw_stats + bnx2x_stats_arr[j].offset);
2005                         if (bnx2x_stats_arr[j].size == 4) {
2006                                 /* 4-byte counter */
2007                                 buf[k + j] = (u64) *offset;
2008                                 continue;
2009                         }
2010                         /* 8-byte counter */
2011                         buf[k + j] = HILO_U64(*offset, *(offset + 1));
2012                 }
2013         } else {
2014                 hw_stats = (u32 *)&bp->eth_stats;
2015                 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
2016                         if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
2017                                 continue;
2018                         if (bnx2x_stats_arr[i].size == 0) {
2019                                 /* skip this counter */
2020                                 buf[j] = 0;
2021                                 j++;
2022                                 continue;
2023                         }
2024                         offset = (hw_stats + bnx2x_stats_arr[i].offset);
2025                         if (bnx2x_stats_arr[i].size == 4) {
2026                                 /* 4-byte counter */
2027                                 buf[j] = (u64) *offset;
2028                                 j++;
2029                                 continue;
2030                         }
2031                         /* 8-byte counter */
2032                         buf[j] = HILO_U64(*offset, *(offset + 1));
2033                         j++;
2034                 }
2035         }
2036 }
2037
2038 static int bnx2x_set_phys_id(struct net_device *dev,
2039                              enum ethtool_phys_id_state state)
2040 {
2041         struct bnx2x *bp = netdev_priv(dev);
2042
2043         if (!netif_running(dev))
2044                 return -EAGAIN;
2045
2046         if (!bp->port.pmf)
2047                 return -EOPNOTSUPP;
2048
2049         switch (state) {
2050         case ETHTOOL_ID_ACTIVE:
2051                 return 1;       /* cycle on/off once per second */
2052
2053         case ETHTOOL_ID_ON:
2054                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2055                               LED_MODE_ON, SPEED_1000);
2056                 break;
2057
2058         case ETHTOOL_ID_OFF:
2059                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2060                               LED_MODE_FRONT_PANEL_OFF, 0);
2061
2062                 break;
2063
2064         case ETHTOOL_ID_INACTIVE:
2065                 bnx2x_set_led(&bp->link_params, &bp->link_vars,
2066                               LED_MODE_OPER,
2067                               bp->link_vars.line_speed);
2068         }
2069
2070         return 0;
2071 }
2072
2073 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2074                            void *rules __always_unused)
2075 {
2076         struct bnx2x *bp = netdev_priv(dev);
2077
2078         switch (info->cmd) {
2079         case ETHTOOL_GRXRINGS:
2080                 info->data = BNX2X_NUM_ETH_QUEUES(bp);
2081                 return 0;
2082
2083         default:
2084                 return -EOPNOTSUPP;
2085         }
2086 }
2087
2088 static int bnx2x_get_rxfh_indir(struct net_device *dev,
2089                                 struct ethtool_rxfh_indir *indir)
2090 {
2091         struct bnx2x *bp = netdev_priv(dev);
2092         size_t copy_size =
2093                 min_t(size_t, indir->size, TSTORM_INDIRECTION_TABLE_SIZE);
2094
2095         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2096                 return -EOPNOTSUPP;
2097
2098         indir->size = TSTORM_INDIRECTION_TABLE_SIZE;
2099         memcpy(indir->ring_index, bp->rx_indir_table,
2100                copy_size * sizeof(bp->rx_indir_table[0]));
2101         return 0;
2102 }
2103
2104 static int bnx2x_set_rxfh_indir(struct net_device *dev,
2105                                 const struct ethtool_rxfh_indir *indir)
2106 {
2107         struct bnx2x *bp = netdev_priv(dev);
2108         size_t i;
2109
2110         if (bp->multi_mode == ETH_RSS_MODE_DISABLED)
2111                 return -EOPNOTSUPP;
2112
2113         /* Validate size and indices */
2114         if (indir->size != TSTORM_INDIRECTION_TABLE_SIZE)
2115                 return -EINVAL;
2116         for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
2117                 if (indir->ring_index[i] >= BNX2X_NUM_ETH_QUEUES(bp))
2118                         return -EINVAL;
2119
2120         memcpy(bp->rx_indir_table, indir->ring_index,
2121                indir->size * sizeof(bp->rx_indir_table[0]));
2122         bnx2x_push_indir_table(bp);
2123         return 0;
2124 }
2125
2126 static const struct ethtool_ops bnx2x_ethtool_ops = {
2127         .get_settings           = bnx2x_get_settings,
2128         .set_settings           = bnx2x_set_settings,
2129         .get_drvinfo            = bnx2x_get_drvinfo,
2130         .get_regs_len           = bnx2x_get_regs_len,
2131         .get_regs               = bnx2x_get_regs,
2132         .get_wol                = bnx2x_get_wol,
2133         .set_wol                = bnx2x_set_wol,
2134         .get_msglevel           = bnx2x_get_msglevel,
2135         .set_msglevel           = bnx2x_set_msglevel,
2136         .nway_reset             = bnx2x_nway_reset,
2137         .get_link               = bnx2x_get_link,
2138         .get_eeprom_len         = bnx2x_get_eeprom_len,
2139         .get_eeprom             = bnx2x_get_eeprom,
2140         .set_eeprom             = bnx2x_set_eeprom,
2141         .get_coalesce           = bnx2x_get_coalesce,
2142         .set_coalesce           = bnx2x_set_coalesce,
2143         .get_ringparam          = bnx2x_get_ringparam,
2144         .set_ringparam          = bnx2x_set_ringparam,
2145         .get_pauseparam         = bnx2x_get_pauseparam,
2146         .set_pauseparam         = bnx2x_set_pauseparam,
2147         .self_test              = bnx2x_self_test,
2148         .get_sset_count         = bnx2x_get_sset_count,
2149         .get_strings            = bnx2x_get_strings,
2150         .set_phys_id            = bnx2x_set_phys_id,
2151         .get_ethtool_stats      = bnx2x_get_ethtool_stats,
2152         .get_rxnfc              = bnx2x_get_rxnfc,
2153         .get_rxfh_indir         = bnx2x_get_rxfh_indir,
2154         .set_rxfh_indir         = bnx2x_set_rxfh_indir,
2155 };
2156
2157 void bnx2x_set_ethtool_ops(struct net_device *netdev)
2158 {
2159         SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
2160 }