1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <asm/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
45 #include <net/checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/prefetch.h>
51 #include <linux/cache.h>
52 #include <linux/zlib.h>
57 #define DRV_MODULE_NAME "bnx2"
58 #define PFX DRV_MODULE_NAME ": "
59 #define DRV_MODULE_VERSION "1.4.43"
60 #define DRV_MODULE_RELDATE "June 28, 2006"
62 #define RUN_AT(x) (jiffies + (x))
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (5*HZ)
67 static const char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
75 static int disable_msi = 0;
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
90 /* indexed by board_t, above */
93 } board_info[] __devinitdata = {
94 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
95 { "HP NC370T Multifunction Gigabit Server Adapter" },
96 { "HP NC370i Multifunction Gigabit Server Adapter" },
97 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
98 { "HP NC370F Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
100 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 static struct pci_device_id bnx2_pci_tbl[] = {
104 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
105 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
106 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
107 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
113 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
121 static struct flash_spec flash_table[] =
124 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
125 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
126 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
128 /* Expansion entry 0001 */
129 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
130 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
131 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
133 /* Saifun SA25F010 (non-buffered flash) */
134 /* strap, cfg1, & write1 need updates */
135 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
138 "Non-buffered flash (128kB)"},
139 /* Saifun SA25F020 (non-buffered flash) */
140 /* strap, cfg1, & write1 need updates */
141 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
142 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
143 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
144 "Non-buffered flash (256kB)"},
145 /* Expansion entry 0100 */
146 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
147 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
148 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
150 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
151 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
152 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
153 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
154 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
155 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
156 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
157 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
158 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
159 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
160 /* Saifun SA25F005 (non-buffered flash) */
161 /* strap, cfg1, & write1 need updates */
162 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
163 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
164 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
165 "Non-buffered flash (64kB)"},
167 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
168 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
169 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
171 /* Expansion entry 1001 */
172 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
173 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
176 /* Expansion entry 1010 */
177 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
178 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
181 /* ATMEL AT45DB011B (buffered flash) */
182 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
183 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
184 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
185 "Buffered flash (128kB)"},
186 /* Expansion entry 1100 */
187 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
188 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
191 /* Expansion entry 1101 */
192 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
193 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
196 /* Ateml Expansion entry 1110 */
197 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
198 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
199 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1110 (Atmel)"},
201 /* ATMEL AT45DB021B (buffered flash) */
202 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
203 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
204 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
205 "Buffered flash (256kB)"},
208 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
210 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
212 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
214 if (diff > MAX_TX_DESC_CNT)
215 diff = (diff & MAX_TX_DESC_CNT) - 1;
216 return (bp->tx_ring_size - diff);
220 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
222 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
223 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
227 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
229 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
230 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
234 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
237 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
238 REG_WR(bp, BNX2_CTX_DATA, val);
242 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
247 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
248 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
249 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
251 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
252 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
257 val1 = (bp->phy_addr << 21) | (reg << 16) |
258 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
259 BNX2_EMAC_MDIO_COMM_START_BUSY;
260 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
262 for (i = 0; i < 50; i++) {
265 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
266 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
269 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
270 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
276 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
285 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
286 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
287 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
289 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
290 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
299 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
304 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
305 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
306 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
308 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
309 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
314 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
315 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
316 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
317 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
319 for (i = 0; i < 50; i++) {
322 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
323 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
329 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
334 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
335 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
336 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
338 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
339 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
348 bnx2_disable_int(struct bnx2 *bp)
350 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
351 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
352 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
356 bnx2_enable_int(struct bnx2 *bp)
358 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
359 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
360 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
362 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
363 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
365 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
369 bnx2_disable_int_sync(struct bnx2 *bp)
371 atomic_inc(&bp->intr_sem);
372 bnx2_disable_int(bp);
373 synchronize_irq(bp->pdev->irq);
377 bnx2_netif_stop(struct bnx2 *bp)
379 bnx2_disable_int_sync(bp);
380 if (netif_running(bp->dev)) {
381 netif_poll_disable(bp->dev);
382 netif_tx_disable(bp->dev);
383 bp->dev->trans_start = jiffies; /* prevent tx timeout */
388 bnx2_netif_start(struct bnx2 *bp)
390 if (atomic_dec_and_test(&bp->intr_sem)) {
391 if (netif_running(bp->dev)) {
392 netif_wake_queue(bp->dev);
393 netif_poll_enable(bp->dev);
400 bnx2_free_mem(struct bnx2 *bp)
404 if (bp->status_blk) {
405 pci_free_consistent(bp->pdev, bp->status_stats_size,
406 bp->status_blk, bp->status_blk_mapping);
407 bp->status_blk = NULL;
408 bp->stats_blk = NULL;
410 if (bp->tx_desc_ring) {
411 pci_free_consistent(bp->pdev,
412 sizeof(struct tx_bd) * TX_DESC_CNT,
413 bp->tx_desc_ring, bp->tx_desc_mapping);
414 bp->tx_desc_ring = NULL;
416 kfree(bp->tx_buf_ring);
417 bp->tx_buf_ring = NULL;
418 for (i = 0; i < bp->rx_max_ring; i++) {
419 if (bp->rx_desc_ring[i])
420 pci_free_consistent(bp->pdev,
421 sizeof(struct rx_bd) * RX_DESC_CNT,
423 bp->rx_desc_mapping[i]);
424 bp->rx_desc_ring[i] = NULL;
426 vfree(bp->rx_buf_ring);
427 bp->rx_buf_ring = NULL;
431 bnx2_alloc_mem(struct bnx2 *bp)
433 int i, status_blk_size;
435 bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
437 if (bp->tx_buf_ring == NULL)
440 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
441 sizeof(struct tx_bd) *
443 &bp->tx_desc_mapping);
444 if (bp->tx_desc_ring == NULL)
447 bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
449 if (bp->rx_buf_ring == NULL)
452 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
455 for (i = 0; i < bp->rx_max_ring; i++) {
456 bp->rx_desc_ring[i] =
457 pci_alloc_consistent(bp->pdev,
458 sizeof(struct rx_bd) * RX_DESC_CNT,
459 &bp->rx_desc_mapping[i]);
460 if (bp->rx_desc_ring[i] == NULL)
465 /* Combine status and statistics blocks into one allocation. */
466 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
467 bp->status_stats_size = status_blk_size +
468 sizeof(struct statistics_block);
470 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
471 &bp->status_blk_mapping);
472 if (bp->status_blk == NULL)
475 memset(bp->status_blk, 0, bp->status_stats_size);
477 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
480 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
490 bnx2_report_fw_link(struct bnx2 *bp)
492 u32 fw_link_status = 0;
497 switch (bp->line_speed) {
499 if (bp->duplex == DUPLEX_HALF)
500 fw_link_status = BNX2_LINK_STATUS_10HALF;
502 fw_link_status = BNX2_LINK_STATUS_10FULL;
505 if (bp->duplex == DUPLEX_HALF)
506 fw_link_status = BNX2_LINK_STATUS_100HALF;
508 fw_link_status = BNX2_LINK_STATUS_100FULL;
511 if (bp->duplex == DUPLEX_HALF)
512 fw_link_status = BNX2_LINK_STATUS_1000HALF;
514 fw_link_status = BNX2_LINK_STATUS_1000FULL;
517 if (bp->duplex == DUPLEX_HALF)
518 fw_link_status = BNX2_LINK_STATUS_2500HALF;
520 fw_link_status = BNX2_LINK_STATUS_2500FULL;
524 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
527 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
529 bnx2_read_phy(bp, MII_BMSR, &bmsr);
530 bnx2_read_phy(bp, MII_BMSR, &bmsr);
532 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
533 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
534 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
536 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
540 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
542 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
546 bnx2_report_link(struct bnx2 *bp)
549 netif_carrier_on(bp->dev);
550 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
552 printk("%d Mbps ", bp->line_speed);
554 if (bp->duplex == DUPLEX_FULL)
555 printk("full duplex");
557 printk("half duplex");
560 if (bp->flow_ctrl & FLOW_CTRL_RX) {
561 printk(", receive ");
562 if (bp->flow_ctrl & FLOW_CTRL_TX)
563 printk("& transmit ");
566 printk(", transmit ");
568 printk("flow control ON");
573 netif_carrier_off(bp->dev);
574 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
577 bnx2_report_fw_link(bp);
581 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
583 u32 local_adv, remote_adv;
586 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
587 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
589 if (bp->duplex == DUPLEX_FULL) {
590 bp->flow_ctrl = bp->req_flow_ctrl;
595 if (bp->duplex != DUPLEX_FULL) {
599 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
600 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
603 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
604 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
605 bp->flow_ctrl |= FLOW_CTRL_TX;
606 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
607 bp->flow_ctrl |= FLOW_CTRL_RX;
611 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
612 bnx2_read_phy(bp, MII_LPA, &remote_adv);
614 if (bp->phy_flags & PHY_SERDES_FLAG) {
615 u32 new_local_adv = 0;
616 u32 new_remote_adv = 0;
618 if (local_adv & ADVERTISE_1000XPAUSE)
619 new_local_adv |= ADVERTISE_PAUSE_CAP;
620 if (local_adv & ADVERTISE_1000XPSE_ASYM)
621 new_local_adv |= ADVERTISE_PAUSE_ASYM;
622 if (remote_adv & ADVERTISE_1000XPAUSE)
623 new_remote_adv |= ADVERTISE_PAUSE_CAP;
624 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
625 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
627 local_adv = new_local_adv;
628 remote_adv = new_remote_adv;
631 /* See Table 28B-3 of 802.3ab-1999 spec. */
632 if (local_adv & ADVERTISE_PAUSE_CAP) {
633 if(local_adv & ADVERTISE_PAUSE_ASYM) {
634 if (remote_adv & ADVERTISE_PAUSE_CAP) {
635 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
637 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
638 bp->flow_ctrl = FLOW_CTRL_RX;
642 if (remote_adv & ADVERTISE_PAUSE_CAP) {
643 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
647 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
648 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
649 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
651 bp->flow_ctrl = FLOW_CTRL_TX;
657 bnx2_5708s_linkup(struct bnx2 *bp)
662 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
663 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
664 case BCM5708S_1000X_STAT1_SPEED_10:
665 bp->line_speed = SPEED_10;
667 case BCM5708S_1000X_STAT1_SPEED_100:
668 bp->line_speed = SPEED_100;
670 case BCM5708S_1000X_STAT1_SPEED_1G:
671 bp->line_speed = SPEED_1000;
673 case BCM5708S_1000X_STAT1_SPEED_2G5:
674 bp->line_speed = SPEED_2500;
677 if (val & BCM5708S_1000X_STAT1_FD)
678 bp->duplex = DUPLEX_FULL;
680 bp->duplex = DUPLEX_HALF;
686 bnx2_5706s_linkup(struct bnx2 *bp)
688 u32 bmcr, local_adv, remote_adv, common;
691 bp->line_speed = SPEED_1000;
693 bnx2_read_phy(bp, MII_BMCR, &bmcr);
694 if (bmcr & BMCR_FULLDPLX) {
695 bp->duplex = DUPLEX_FULL;
698 bp->duplex = DUPLEX_HALF;
701 if (!(bmcr & BMCR_ANENABLE)) {
705 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
706 bnx2_read_phy(bp, MII_LPA, &remote_adv);
708 common = local_adv & remote_adv;
709 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
711 if (common & ADVERTISE_1000XFULL) {
712 bp->duplex = DUPLEX_FULL;
715 bp->duplex = DUPLEX_HALF;
723 bnx2_copper_linkup(struct bnx2 *bp)
727 bnx2_read_phy(bp, MII_BMCR, &bmcr);
728 if (bmcr & BMCR_ANENABLE) {
729 u32 local_adv, remote_adv, common;
731 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
732 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
734 common = local_adv & (remote_adv >> 2);
735 if (common & ADVERTISE_1000FULL) {
736 bp->line_speed = SPEED_1000;
737 bp->duplex = DUPLEX_FULL;
739 else if (common & ADVERTISE_1000HALF) {
740 bp->line_speed = SPEED_1000;
741 bp->duplex = DUPLEX_HALF;
744 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
745 bnx2_read_phy(bp, MII_LPA, &remote_adv);
747 common = local_adv & remote_adv;
748 if (common & ADVERTISE_100FULL) {
749 bp->line_speed = SPEED_100;
750 bp->duplex = DUPLEX_FULL;
752 else if (common & ADVERTISE_100HALF) {
753 bp->line_speed = SPEED_100;
754 bp->duplex = DUPLEX_HALF;
756 else if (common & ADVERTISE_10FULL) {
757 bp->line_speed = SPEED_10;
758 bp->duplex = DUPLEX_FULL;
760 else if (common & ADVERTISE_10HALF) {
761 bp->line_speed = SPEED_10;
762 bp->duplex = DUPLEX_HALF;
771 if (bmcr & BMCR_SPEED100) {
772 bp->line_speed = SPEED_100;
775 bp->line_speed = SPEED_10;
777 if (bmcr & BMCR_FULLDPLX) {
778 bp->duplex = DUPLEX_FULL;
781 bp->duplex = DUPLEX_HALF;
789 bnx2_set_mac_link(struct bnx2 *bp)
793 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
794 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
795 (bp->duplex == DUPLEX_HALF)) {
796 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
799 /* Configure the EMAC mode register. */
800 val = REG_RD(bp, BNX2_EMAC_MODE);
802 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
803 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
807 switch (bp->line_speed) {
809 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
810 val |= BNX2_EMAC_MODE_PORT_MII_10;
815 val |= BNX2_EMAC_MODE_PORT_MII;
818 val |= BNX2_EMAC_MODE_25G;
821 val |= BNX2_EMAC_MODE_PORT_GMII;
826 val |= BNX2_EMAC_MODE_PORT_GMII;
829 /* Set the MAC to operate in the appropriate duplex mode. */
830 if (bp->duplex == DUPLEX_HALF)
831 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
832 REG_WR(bp, BNX2_EMAC_MODE, val);
834 /* Enable/disable rx PAUSE. */
835 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
837 if (bp->flow_ctrl & FLOW_CTRL_RX)
838 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
839 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
841 /* Enable/disable tx PAUSE. */
842 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
843 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
845 if (bp->flow_ctrl & FLOW_CTRL_TX)
846 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
847 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
849 /* Acknowledge the interrupt. */
850 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
856 bnx2_set_link(struct bnx2 *bp)
861 if (bp->loopback == MAC_LOOPBACK) {
866 link_up = bp->link_up;
868 bnx2_read_phy(bp, MII_BMSR, &bmsr);
869 bnx2_read_phy(bp, MII_BMSR, &bmsr);
871 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
872 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
875 val = REG_RD(bp, BNX2_EMAC_STATUS);
876 if (val & BNX2_EMAC_STATUS_LINK)
877 bmsr |= BMSR_LSTATUS;
879 bmsr &= ~BMSR_LSTATUS;
882 if (bmsr & BMSR_LSTATUS) {
885 if (bp->phy_flags & PHY_SERDES_FLAG) {
886 if (CHIP_NUM(bp) == CHIP_NUM_5706)
887 bnx2_5706s_linkup(bp);
888 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
889 bnx2_5708s_linkup(bp);
892 bnx2_copper_linkup(bp);
894 bnx2_resolve_flow_ctrl(bp);
897 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
898 (bp->autoneg & AUTONEG_SPEED)) {
902 bnx2_read_phy(bp, MII_BMCR, &bmcr);
903 if (!(bmcr & BMCR_ANENABLE)) {
904 bnx2_write_phy(bp, MII_BMCR, bmcr |
908 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
912 if (bp->link_up != link_up) {
913 bnx2_report_link(bp);
916 bnx2_set_mac_link(bp);
922 bnx2_reset_phy(struct bnx2 *bp)
927 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
929 #define PHY_RESET_MAX_WAIT 100
930 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
933 bnx2_read_phy(bp, MII_BMCR, ®);
934 if (!(reg & BMCR_RESET)) {
939 if (i == PHY_RESET_MAX_WAIT) {
946 bnx2_phy_get_pause_adv(struct bnx2 *bp)
950 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
951 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
953 if (bp->phy_flags & PHY_SERDES_FLAG) {
954 adv = ADVERTISE_1000XPAUSE;
957 adv = ADVERTISE_PAUSE_CAP;
960 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
961 if (bp->phy_flags & PHY_SERDES_FLAG) {
962 adv = ADVERTISE_1000XPSE_ASYM;
965 adv = ADVERTISE_PAUSE_ASYM;
968 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
969 if (bp->phy_flags & PHY_SERDES_FLAG) {
970 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
973 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
980 bnx2_setup_serdes_phy(struct bnx2 *bp)
985 if (!(bp->autoneg & AUTONEG_SPEED)) {
987 int force_link_down = 0;
989 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
990 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
991 if (up1 & BCM5708S_UP1_2G5) {
992 up1 &= ~BCM5708S_UP1_2G5;
993 bnx2_write_phy(bp, BCM5708S_UP1, up1);
998 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
999 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1001 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1002 new_bmcr = bmcr & ~BMCR_ANENABLE;
1003 new_bmcr |= BMCR_SPEED1000;
1004 if (bp->req_duplex == DUPLEX_FULL) {
1005 adv |= ADVERTISE_1000XFULL;
1006 new_bmcr |= BMCR_FULLDPLX;
1009 adv |= ADVERTISE_1000XHALF;
1010 new_bmcr &= ~BMCR_FULLDPLX;
1012 if ((new_bmcr != bmcr) || (force_link_down)) {
1013 /* Force a link down visible on the other side */
1015 bnx2_write_phy(bp, MII_ADVERTISE, adv &
1016 ~(ADVERTISE_1000XFULL |
1017 ADVERTISE_1000XHALF));
1018 bnx2_write_phy(bp, MII_BMCR, bmcr |
1019 BMCR_ANRESTART | BMCR_ANENABLE);
1022 netif_carrier_off(bp->dev);
1023 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1025 bnx2_write_phy(bp, MII_ADVERTISE, adv);
1026 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1031 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1032 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
1033 up1 |= BCM5708S_UP1_2G5;
1034 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1037 if (bp->advertising & ADVERTISED_1000baseT_Full)
1038 new_adv |= ADVERTISE_1000XFULL;
1040 new_adv |= bnx2_phy_get_pause_adv(bp);
1042 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1043 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1045 bp->serdes_an_pending = 0;
1046 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1047 /* Force a link down visible on the other side */
1051 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1052 for (i = 0; i < 110; i++) {
1057 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1058 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1060 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1061 /* Speed up link-up time when the link partner
1062 * does not autonegotiate which is very common
1063 * in blade servers. Some blade servers use
1064 * IPMI for kerboard input and it's important
1065 * to minimize link disruptions. Autoneg. involves
1066 * exchanging base pages plus 3 next pages and
1067 * normally completes in about 120 msec.
1069 bp->current_interval = SERDES_AN_TIMEOUT;
1070 bp->serdes_an_pending = 1;
1071 mod_timer(&bp->timer, jiffies + bp->current_interval);
1078 #define ETHTOOL_ALL_FIBRE_SPEED \
1079 (ADVERTISED_1000baseT_Full)
1081 #define ETHTOOL_ALL_COPPER_SPEED \
1082 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1083 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1084 ADVERTISED_1000baseT_Full)
1086 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1087 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1089 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1092 bnx2_setup_copper_phy(struct bnx2 *bp)
1097 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1099 if (bp->autoneg & AUTONEG_SPEED) {
1100 u32 adv_reg, adv1000_reg;
1101 u32 new_adv_reg = 0;
1102 u32 new_adv1000_reg = 0;
1104 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1105 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1106 ADVERTISE_PAUSE_ASYM);
1108 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1109 adv1000_reg &= PHY_ALL_1000_SPEED;
1111 if (bp->advertising & ADVERTISED_10baseT_Half)
1112 new_adv_reg |= ADVERTISE_10HALF;
1113 if (bp->advertising & ADVERTISED_10baseT_Full)
1114 new_adv_reg |= ADVERTISE_10FULL;
1115 if (bp->advertising & ADVERTISED_100baseT_Half)
1116 new_adv_reg |= ADVERTISE_100HALF;
1117 if (bp->advertising & ADVERTISED_100baseT_Full)
1118 new_adv_reg |= ADVERTISE_100FULL;
1119 if (bp->advertising & ADVERTISED_1000baseT_Full)
1120 new_adv1000_reg |= ADVERTISE_1000FULL;
1122 new_adv_reg |= ADVERTISE_CSMA;
1124 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1126 if ((adv1000_reg != new_adv1000_reg) ||
1127 (adv_reg != new_adv_reg) ||
1128 ((bmcr & BMCR_ANENABLE) == 0)) {
1130 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1131 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1132 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1135 else if (bp->link_up) {
1136 /* Flow ctrl may have changed from auto to forced */
1137 /* or vice-versa. */
1139 bnx2_resolve_flow_ctrl(bp);
1140 bnx2_set_mac_link(bp);
1146 if (bp->req_line_speed == SPEED_100) {
1147 new_bmcr |= BMCR_SPEED100;
1149 if (bp->req_duplex == DUPLEX_FULL) {
1150 new_bmcr |= BMCR_FULLDPLX;
1152 if (new_bmcr != bmcr) {
1156 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1157 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1159 if (bmsr & BMSR_LSTATUS) {
1160 /* Force link down */
1161 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1164 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1165 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1167 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
1170 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1172 /* Normally, the new speed is setup after the link has
1173 * gone down and up again. In some cases, link will not go
1174 * down so we need to set up the new speed here.
1176 if (bmsr & BMSR_LSTATUS) {
1177 bp->line_speed = bp->req_line_speed;
1178 bp->duplex = bp->req_duplex;
1179 bnx2_resolve_flow_ctrl(bp);
1180 bnx2_set_mac_link(bp);
1187 bnx2_setup_phy(struct bnx2 *bp)
1189 if (bp->loopback == MAC_LOOPBACK)
1192 if (bp->phy_flags & PHY_SERDES_FLAG) {
1193 return (bnx2_setup_serdes_phy(bp));
1196 return (bnx2_setup_copper_phy(bp));
1201 bnx2_init_5708s_phy(struct bnx2 *bp)
1205 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1206 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1207 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1209 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1210 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1211 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1213 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1214 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1215 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1217 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1218 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1219 val |= BCM5708S_UP1_2G5;
1220 bnx2_write_phy(bp, BCM5708S_UP1, val);
1223 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1224 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1225 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1226 /* increase tx signal amplitude */
1227 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1228 BCM5708S_BLK_ADDR_TX_MISC);
1229 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1230 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1231 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1232 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1235 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1236 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1241 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1242 BNX2_SHARED_HW_CFG_CONFIG);
1243 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1244 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1245 BCM5708S_BLK_ADDR_TX_MISC);
1246 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1247 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1248 BCM5708S_BLK_ADDR_DIG);
1255 bnx2_init_5706s_phy(struct bnx2 *bp)
1257 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1259 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
1260 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
1263 if (bp->dev->mtu > 1500) {
1266 /* Set extended packet length bit */
1267 bnx2_write_phy(bp, 0x18, 0x7);
1268 bnx2_read_phy(bp, 0x18, &val);
1269 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1271 bnx2_write_phy(bp, 0x1c, 0x6c00);
1272 bnx2_read_phy(bp, 0x1c, &val);
1273 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1278 bnx2_write_phy(bp, 0x18, 0x7);
1279 bnx2_read_phy(bp, 0x18, &val);
1280 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1282 bnx2_write_phy(bp, 0x1c, 0x6c00);
1283 bnx2_read_phy(bp, 0x1c, &val);
1284 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1291 bnx2_init_copper_phy(struct bnx2 *bp)
1295 bp->phy_flags |= PHY_CRC_FIX_FLAG;
1297 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1298 bnx2_write_phy(bp, 0x18, 0x0c00);
1299 bnx2_write_phy(bp, 0x17, 0x000a);
1300 bnx2_write_phy(bp, 0x15, 0x310b);
1301 bnx2_write_phy(bp, 0x17, 0x201f);
1302 bnx2_write_phy(bp, 0x15, 0x9506);
1303 bnx2_write_phy(bp, 0x17, 0x401f);
1304 bnx2_write_phy(bp, 0x15, 0x14e2);
1305 bnx2_write_phy(bp, 0x18, 0x0400);
1308 if (bp->dev->mtu > 1500) {
1309 /* Set extended packet length bit */
1310 bnx2_write_phy(bp, 0x18, 0x7);
1311 bnx2_read_phy(bp, 0x18, &val);
1312 bnx2_write_phy(bp, 0x18, val | 0x4000);
1314 bnx2_read_phy(bp, 0x10, &val);
1315 bnx2_write_phy(bp, 0x10, val | 0x1);
1318 bnx2_write_phy(bp, 0x18, 0x7);
1319 bnx2_read_phy(bp, 0x18, &val);
1320 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1322 bnx2_read_phy(bp, 0x10, &val);
1323 bnx2_write_phy(bp, 0x10, val & ~0x1);
1326 /* ethernet@wirespeed */
1327 bnx2_write_phy(bp, 0x18, 0x7007);
1328 bnx2_read_phy(bp, 0x18, &val);
1329 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1335 bnx2_init_phy(struct bnx2 *bp)
1340 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1341 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1343 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1347 bnx2_read_phy(bp, MII_PHYSID1, &val);
1348 bp->phy_id = val << 16;
1349 bnx2_read_phy(bp, MII_PHYSID2, &val);
1350 bp->phy_id |= val & 0xffff;
1352 if (bp->phy_flags & PHY_SERDES_FLAG) {
1353 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1354 rc = bnx2_init_5706s_phy(bp);
1355 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1356 rc = bnx2_init_5708s_phy(bp);
1359 rc = bnx2_init_copper_phy(bp);
1368 bnx2_set_mac_loopback(struct bnx2 *bp)
1372 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1373 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1374 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1375 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1380 static int bnx2_test_link(struct bnx2 *);
1383 bnx2_set_phy_loopback(struct bnx2 *bp)
1388 spin_lock_bh(&bp->phy_lock);
1389 rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1391 spin_unlock_bh(&bp->phy_lock);
1395 for (i = 0; i < 10; i++) {
1396 if (bnx2_test_link(bp) == 0)
1401 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1402 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1403 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1404 BNX2_EMAC_MODE_25G);
1406 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1407 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1413 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1419 msg_data |= bp->fw_wr_seq;
1421 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1423 /* wait for an acknowledgement. */
1424 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1427 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1429 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1432 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1435 /* If we timed out, inform the firmware that this is the case. */
1436 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1438 printk(KERN_ERR PFX "fw sync timeout, reset code = "
1441 msg_data &= ~BNX2_DRV_MSG_CODE;
1442 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1444 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1449 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1456 bnx2_init_context(struct bnx2 *bp)
1462 u32 vcid_addr, pcid_addr, offset;
1466 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1469 vcid_addr = GET_PCID_ADDR(vcid);
1471 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1476 pcid_addr = GET_PCID_ADDR(new_vcid);
1479 vcid_addr = GET_CID_ADDR(vcid);
1480 pcid_addr = vcid_addr;
1483 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1484 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1486 /* Zero out the context. */
1487 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1488 CTX_WR(bp, 0x00, offset, 0);
1491 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1492 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1497 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1503 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1504 if (good_mbuf == NULL) {
1505 printk(KERN_ERR PFX "Failed to allocate memory in "
1506 "bnx2_alloc_bad_rbuf\n");
1510 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1511 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1515 /* Allocate a bunch of mbufs and save the good ones in an array. */
1516 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1517 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1518 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1520 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1522 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1524 /* The addresses with Bit 9 set are bad memory blocks. */
1525 if (!(val & (1 << 9))) {
1526 good_mbuf[good_mbuf_cnt] = (u16) val;
1530 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1533 /* Free the good ones back to the mbuf pool thus discarding
1534 * all the bad ones. */
1535 while (good_mbuf_cnt) {
1538 val = good_mbuf[good_mbuf_cnt];
1539 val = (val << 9) | val | 1;
1541 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1548 bnx2_set_mac_addr(struct bnx2 *bp)
1551 u8 *mac_addr = bp->dev->dev_addr;
1553 val = (mac_addr[0] << 8) | mac_addr[1];
1555 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1557 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1558 (mac_addr[4] << 8) | mac_addr[5];
1560 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1564 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1566 struct sk_buff *skb;
1567 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1569 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
1570 unsigned long align;
1572 skb = dev_alloc_skb(bp->rx_buf_size);
1577 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1578 skb_reserve(skb, 8 - align);
1582 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1583 PCI_DMA_FROMDEVICE);
1586 pci_unmap_addr_set(rx_buf, mapping, mapping);
1588 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1589 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1591 bp->rx_prod_bseq += bp->rx_buf_use_size;
1597 bnx2_phy_int(struct bnx2 *bp)
1599 u32 new_link_state, old_link_state;
1601 new_link_state = bp->status_blk->status_attn_bits &
1602 STATUS_ATTN_BITS_LINK_STATE;
1603 old_link_state = bp->status_blk->status_attn_bits_ack &
1604 STATUS_ATTN_BITS_LINK_STATE;
1605 if (new_link_state != old_link_state) {
1606 if (new_link_state) {
1607 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1608 STATUS_ATTN_BITS_LINK_STATE);
1611 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1612 STATUS_ATTN_BITS_LINK_STATE);
1619 bnx2_tx_int(struct bnx2 *bp)
1621 struct status_block *sblk = bp->status_blk;
1622 u16 hw_cons, sw_cons, sw_ring_cons;
1625 hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1626 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1629 sw_cons = bp->tx_cons;
1631 while (sw_cons != hw_cons) {
1632 struct sw_bd *tx_buf;
1633 struct sk_buff *skb;
1636 sw_ring_cons = TX_RING_IDX(sw_cons);
1638 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1641 /* partial BD completions possible with TSO packets */
1642 if (skb_is_gso(skb)) {
1643 u16 last_idx, last_ring_idx;
1645 last_idx = sw_cons +
1646 skb_shinfo(skb)->nr_frags + 1;
1647 last_ring_idx = sw_ring_cons +
1648 skb_shinfo(skb)->nr_frags + 1;
1649 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1652 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1657 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1658 skb_headlen(skb), PCI_DMA_TODEVICE);
1661 last = skb_shinfo(skb)->nr_frags;
1663 for (i = 0; i < last; i++) {
1664 sw_cons = NEXT_TX_BD(sw_cons);
1666 pci_unmap_page(bp->pdev,
1668 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1670 skb_shinfo(skb)->frags[i].size,
1674 sw_cons = NEXT_TX_BD(sw_cons);
1676 tx_free_bd += last + 1;
1680 hw_cons = bp->hw_tx_cons =
1681 sblk->status_tx_quick_consumer_index0;
1683 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1688 bp->tx_cons = sw_cons;
1690 if (unlikely(netif_queue_stopped(bp->dev))) {
1691 spin_lock(&bp->tx_lock);
1692 if ((netif_queue_stopped(bp->dev)) &&
1693 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1695 netif_wake_queue(bp->dev);
1697 spin_unlock(&bp->tx_lock);
1702 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1705 struct sw_bd *cons_rx_buf, *prod_rx_buf;
1706 struct rx_bd *cons_bd, *prod_bd;
1708 cons_rx_buf = &bp->rx_buf_ring[cons];
1709 prod_rx_buf = &bp->rx_buf_ring[prod];
1711 pci_dma_sync_single_for_device(bp->pdev,
1712 pci_unmap_addr(cons_rx_buf, mapping),
1713 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1715 bp->rx_prod_bseq += bp->rx_buf_use_size;
1717 prod_rx_buf->skb = skb;
1722 pci_unmap_addr_set(prod_rx_buf, mapping,
1723 pci_unmap_addr(cons_rx_buf, mapping));
1725 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
1726 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1727 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
1728 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
1732 bnx2_rx_int(struct bnx2 *bp, int budget)
1734 struct status_block *sblk = bp->status_blk;
1735 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1736 struct l2_fhdr *rx_hdr;
1739 hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1740 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1743 sw_cons = bp->rx_cons;
1744 sw_prod = bp->rx_prod;
1746 /* Memory barrier necessary as speculative reads of the rx
1747 * buffer can be ahead of the index in the status block
1750 while (sw_cons != hw_cons) {
1753 struct sw_bd *rx_buf;
1754 struct sk_buff *skb;
1755 dma_addr_t dma_addr;
1757 sw_ring_cons = RX_RING_IDX(sw_cons);
1758 sw_ring_prod = RX_RING_IDX(sw_prod);
1760 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1765 dma_addr = pci_unmap_addr(rx_buf, mapping);
1767 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
1768 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1770 rx_hdr = (struct l2_fhdr *) skb->data;
1771 len = rx_hdr->l2_fhdr_pkt_len - 4;
1773 if ((status = rx_hdr->l2_fhdr_status) &
1774 (L2_FHDR_ERRORS_BAD_CRC |
1775 L2_FHDR_ERRORS_PHY_DECODE |
1776 L2_FHDR_ERRORS_ALIGNMENT |
1777 L2_FHDR_ERRORS_TOO_SHORT |
1778 L2_FHDR_ERRORS_GIANT_FRAME)) {
1783 /* Since we don't have a jumbo ring, copy small packets
1786 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1787 struct sk_buff *new_skb;
1789 new_skb = dev_alloc_skb(len + 2);
1790 if (new_skb == NULL)
1794 memcpy(new_skb->data,
1795 skb->data + bp->rx_offset - 2,
1798 skb_reserve(new_skb, 2);
1799 skb_put(new_skb, len);
1800 new_skb->dev = bp->dev;
1802 bnx2_reuse_rx_skb(bp, skb,
1803 sw_ring_cons, sw_ring_prod);
1807 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1808 pci_unmap_single(bp->pdev, dma_addr,
1809 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1811 skb_reserve(skb, bp->rx_offset);
1816 bnx2_reuse_rx_skb(bp, skb,
1817 sw_ring_cons, sw_ring_prod);
1821 skb->protocol = eth_type_trans(skb, bp->dev);
1823 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1824 (ntohs(skb->protocol) != 0x8100)) {
1831 skb->ip_summed = CHECKSUM_NONE;
1833 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1834 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1836 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1837 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1838 skb->ip_summed = CHECKSUM_UNNECESSARY;
1842 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1843 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1844 rx_hdr->l2_fhdr_vlan_tag);
1848 netif_receive_skb(skb);
1850 bp->dev->last_rx = jiffies;
1854 sw_cons = NEXT_RX_BD(sw_cons);
1855 sw_prod = NEXT_RX_BD(sw_prod);
1857 if ((rx_pkt == budget))
1860 /* Refresh hw_cons to see if there is new work */
1861 if (sw_cons == hw_cons) {
1862 hw_cons = bp->hw_rx_cons =
1863 sblk->status_rx_quick_consumer_index0;
1864 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1869 bp->rx_cons = sw_cons;
1870 bp->rx_prod = sw_prod;
1872 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1874 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1882 /* MSI ISR - The only difference between this and the INTx ISR
1883 * is that the MSI interrupt is always serviced.
1886 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1888 struct net_device *dev = dev_instance;
1889 struct bnx2 *bp = netdev_priv(dev);
1891 prefetch(bp->status_blk);
1892 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1893 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1894 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1896 /* Return here if interrupt is disabled. */
1897 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1900 netif_rx_schedule(dev);
1906 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1908 struct net_device *dev = dev_instance;
1909 struct bnx2 *bp = netdev_priv(dev);
1911 /* When using INTx, it is possible for the interrupt to arrive
1912 * at the CPU before the status block posted prior to the
1913 * interrupt. Reading a register will flush the status block.
1914 * When using MSI, the MSI message will always complete after
1915 * the status block write.
1917 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1918 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1919 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1922 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1923 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1924 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1926 /* Return here if interrupt is shared and is disabled. */
1927 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1930 netif_rx_schedule(dev);
1936 bnx2_has_work(struct bnx2 *bp)
1938 struct status_block *sblk = bp->status_blk;
1940 if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
1941 (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
1944 if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
1952 bnx2_poll(struct net_device *dev, int *budget)
1954 struct bnx2 *bp = netdev_priv(dev);
1956 if ((bp->status_blk->status_attn_bits &
1957 STATUS_ATTN_BITS_LINK_STATE) !=
1958 (bp->status_blk->status_attn_bits_ack &
1959 STATUS_ATTN_BITS_LINK_STATE)) {
1961 spin_lock(&bp->phy_lock);
1963 spin_unlock(&bp->phy_lock);
1965 /* This is needed to take care of transient status
1966 * during link changes.
1968 REG_WR(bp, BNX2_HC_COMMAND,
1969 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
1970 REG_RD(bp, BNX2_HC_COMMAND);
1973 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
1976 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
1977 int orig_budget = *budget;
1980 if (orig_budget > dev->quota)
1981 orig_budget = dev->quota;
1983 work_done = bnx2_rx_int(bp, orig_budget);
1984 *budget -= work_done;
1985 dev->quota -= work_done;
1988 bp->last_status_idx = bp->status_blk->status_idx;
1991 if (!bnx2_has_work(bp)) {
1992 netif_rx_complete(dev);
1993 if (likely(bp->flags & USING_MSI_FLAG)) {
1994 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1995 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1996 bp->last_status_idx);
1999 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2000 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2001 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2002 bp->last_status_idx);
2004 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2005 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2006 bp->last_status_idx);
2013 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2014 * from set_multicast.
2017 bnx2_set_rx_mode(struct net_device *dev)
2019 struct bnx2 *bp = netdev_priv(dev);
2020 u32 rx_mode, sort_mode;
2023 spin_lock_bh(&bp->phy_lock);
2025 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2026 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2027 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2029 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2030 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2032 if (!(bp->flags & ASF_ENABLE_FLAG))
2033 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2035 if (dev->flags & IFF_PROMISC) {
2036 /* Promiscuous mode. */
2037 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2038 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
2040 else if (dev->flags & IFF_ALLMULTI) {
2041 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2042 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2045 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2048 /* Accept one or more multicast(s). */
2049 struct dev_mc_list *mclist;
2050 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2055 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2057 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2058 i++, mclist = mclist->next) {
2060 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2062 regidx = (bit & 0xe0) >> 5;
2064 mc_filter[regidx] |= (1 << bit);
2067 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2068 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2072 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2075 if (rx_mode != bp->rx_mode) {
2076 bp->rx_mode = rx_mode;
2077 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2080 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2081 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2082 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2084 spin_unlock_bh(&bp->phy_lock);
2087 #define FW_BUF_SIZE 0x8000
2090 bnx2_gunzip_init(struct bnx2 *bp)
2092 if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
2095 if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
2098 bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
2099 if (bp->strm->workspace == NULL)
2109 vfree(bp->gunzip_buf);
2110 bp->gunzip_buf = NULL;
2113 printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
2114 "uncompression.\n", bp->dev->name);
2119 bnx2_gunzip_end(struct bnx2 *bp)
2121 kfree(bp->strm->workspace);
2126 if (bp->gunzip_buf) {
2127 vfree(bp->gunzip_buf);
2128 bp->gunzip_buf = NULL;
2133 bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
2137 /* check gzip header */
2138 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
2144 if (zbuf[3] & FNAME)
2145 while ((zbuf[n++] != 0) && (n < len));
2147 bp->strm->next_in = zbuf + n;
2148 bp->strm->avail_in = len - n;
2149 bp->strm->next_out = bp->gunzip_buf;
2150 bp->strm->avail_out = FW_BUF_SIZE;
2152 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
2156 rc = zlib_inflate(bp->strm, Z_FINISH);
2158 *outlen = FW_BUF_SIZE - bp->strm->avail_out;
2159 *outbuf = bp->gunzip_buf;
2161 if ((rc != Z_OK) && (rc != Z_STREAM_END))
2162 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
2163 bp->dev->name, bp->strm->msg);
2165 zlib_inflateEnd(bp->strm);
2167 if (rc == Z_STREAM_END)
2174 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2181 for (i = 0; i < rv2p_code_len; i += 8) {
2182 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2184 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2187 if (rv2p_proc == RV2P_PROC1) {
2188 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2189 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2192 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2193 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2197 /* Reset the processor, un-stall is done later. */
2198 if (rv2p_proc == RV2P_PROC1) {
2199 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2202 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2207 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2213 val = REG_RD_IND(bp, cpu_reg->mode);
2214 val |= cpu_reg->mode_value_halt;
2215 REG_WR_IND(bp, cpu_reg->mode, val);
2216 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2218 /* Load the Text area. */
2219 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2223 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2224 REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2228 /* Load the Data area. */
2229 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2233 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2234 REG_WR_IND(bp, offset, fw->data[j]);
2238 /* Load the SBSS area. */
2239 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2243 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2244 REG_WR_IND(bp, offset, fw->sbss[j]);
2248 /* Load the BSS area. */
2249 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2253 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2254 REG_WR_IND(bp, offset, fw->bss[j]);
2258 /* Load the Read-Only area. */
2259 offset = cpu_reg->spad_base +
2260 (fw->rodata_addr - cpu_reg->mips_view_base);
2264 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2265 REG_WR_IND(bp, offset, fw->rodata[j]);
2269 /* Clear the pre-fetch instruction. */
2270 REG_WR_IND(bp, cpu_reg->inst, 0);
2271 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2273 /* Start the CPU. */
2274 val = REG_RD_IND(bp, cpu_reg->mode);
2275 val &= ~cpu_reg->mode_value_halt;
2276 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2277 REG_WR_IND(bp, cpu_reg->mode, val);
2281 bnx2_init_cpus(struct bnx2 *bp)
2283 struct cpu_reg cpu_reg;
2289 if ((rc = bnx2_gunzip_init(bp)) != 0)
2292 /* Initialize the RV2P processor. */
2293 rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
2298 load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
2300 rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
2305 load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
2307 /* Initialize the RX Processor. */
2308 cpu_reg.mode = BNX2_RXP_CPU_MODE;
2309 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2310 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2311 cpu_reg.state = BNX2_RXP_CPU_STATE;
2312 cpu_reg.state_value_clear = 0xffffff;
2313 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2314 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2315 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2316 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2317 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2318 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2319 cpu_reg.mips_view_base = 0x8000000;
2321 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
2322 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
2323 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
2324 fw.start_addr = bnx2_RXP_b06FwStartAddr;
2326 fw.text_addr = bnx2_RXP_b06FwTextAddr;
2327 fw.text_len = bnx2_RXP_b06FwTextLen;
2330 rc = bnx2_gunzip(bp, bnx2_RXP_b06FwText, sizeof(bnx2_RXP_b06FwText),
2337 fw.data_addr = bnx2_RXP_b06FwDataAddr;
2338 fw.data_len = bnx2_RXP_b06FwDataLen;
2340 fw.data = bnx2_RXP_b06FwData;
2342 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
2343 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
2345 fw.sbss = bnx2_RXP_b06FwSbss;
2347 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
2348 fw.bss_len = bnx2_RXP_b06FwBssLen;
2350 fw.bss = bnx2_RXP_b06FwBss;
2352 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
2353 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
2354 fw.rodata_index = 0;
2355 fw.rodata = bnx2_RXP_b06FwRodata;
2357 load_cpu_fw(bp, &cpu_reg, &fw);
2359 /* Initialize the TX Processor. */
2360 cpu_reg.mode = BNX2_TXP_CPU_MODE;
2361 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2362 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2363 cpu_reg.state = BNX2_TXP_CPU_STATE;
2364 cpu_reg.state_value_clear = 0xffffff;
2365 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2366 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2367 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2368 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2369 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2370 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2371 cpu_reg.mips_view_base = 0x8000000;
2373 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
2374 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
2375 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
2376 fw.start_addr = bnx2_TXP_b06FwStartAddr;
2378 fw.text_addr = bnx2_TXP_b06FwTextAddr;
2379 fw.text_len = bnx2_TXP_b06FwTextLen;
2382 rc = bnx2_gunzip(bp, bnx2_TXP_b06FwText, sizeof(bnx2_TXP_b06FwText),
2389 fw.data_addr = bnx2_TXP_b06FwDataAddr;
2390 fw.data_len = bnx2_TXP_b06FwDataLen;
2392 fw.data = bnx2_TXP_b06FwData;
2394 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
2395 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
2397 fw.sbss = bnx2_TXP_b06FwSbss;
2399 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
2400 fw.bss_len = bnx2_TXP_b06FwBssLen;
2402 fw.bss = bnx2_TXP_b06FwBss;
2404 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
2405 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
2406 fw.rodata_index = 0;
2407 fw.rodata = bnx2_TXP_b06FwRodata;
2409 load_cpu_fw(bp, &cpu_reg, &fw);
2411 /* Initialize the TX Patch-up Processor. */
2412 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2413 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2414 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2415 cpu_reg.state = BNX2_TPAT_CPU_STATE;
2416 cpu_reg.state_value_clear = 0xffffff;
2417 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2418 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2419 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2420 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2421 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2422 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2423 cpu_reg.mips_view_base = 0x8000000;
2425 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
2426 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
2427 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
2428 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
2430 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
2431 fw.text_len = bnx2_TPAT_b06FwTextLen;
2434 rc = bnx2_gunzip(bp, bnx2_TPAT_b06FwText, sizeof(bnx2_TPAT_b06FwText),
2441 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
2442 fw.data_len = bnx2_TPAT_b06FwDataLen;
2444 fw.data = bnx2_TPAT_b06FwData;
2446 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
2447 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
2449 fw.sbss = bnx2_TPAT_b06FwSbss;
2451 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
2452 fw.bss_len = bnx2_TPAT_b06FwBssLen;
2454 fw.bss = bnx2_TPAT_b06FwBss;
2456 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
2457 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
2458 fw.rodata_index = 0;
2459 fw.rodata = bnx2_TPAT_b06FwRodata;
2461 load_cpu_fw(bp, &cpu_reg, &fw);
2463 /* Initialize the Completion Processor. */
2464 cpu_reg.mode = BNX2_COM_CPU_MODE;
2465 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2466 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2467 cpu_reg.state = BNX2_COM_CPU_STATE;
2468 cpu_reg.state_value_clear = 0xffffff;
2469 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2470 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2471 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2472 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2473 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2474 cpu_reg.spad_base = BNX2_COM_SCRATCH;
2475 cpu_reg.mips_view_base = 0x8000000;
2477 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
2478 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
2479 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
2480 fw.start_addr = bnx2_COM_b06FwStartAddr;
2482 fw.text_addr = bnx2_COM_b06FwTextAddr;
2483 fw.text_len = bnx2_COM_b06FwTextLen;
2486 rc = bnx2_gunzip(bp, bnx2_COM_b06FwText, sizeof(bnx2_COM_b06FwText),
2493 fw.data_addr = bnx2_COM_b06FwDataAddr;
2494 fw.data_len = bnx2_COM_b06FwDataLen;
2496 fw.data = bnx2_COM_b06FwData;
2498 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
2499 fw.sbss_len = bnx2_COM_b06FwSbssLen;
2501 fw.sbss = bnx2_COM_b06FwSbss;
2503 fw.bss_addr = bnx2_COM_b06FwBssAddr;
2504 fw.bss_len = bnx2_COM_b06FwBssLen;
2506 fw.bss = bnx2_COM_b06FwBss;
2508 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
2509 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2510 fw.rodata_index = 0;
2511 fw.rodata = bnx2_COM_b06FwRodata;
2513 load_cpu_fw(bp, &cpu_reg, &fw);
2516 bnx2_gunzip_end(bp);
2521 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2525 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2531 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2532 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2533 PCI_PM_CTRL_PME_STATUS);
2535 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2536 /* delay required during transition out of D3hot */
2539 val = REG_RD(bp, BNX2_EMAC_MODE);
2540 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2541 val &= ~BNX2_EMAC_MODE_MPKT;
2542 REG_WR(bp, BNX2_EMAC_MODE, val);
2544 val = REG_RD(bp, BNX2_RPM_CONFIG);
2545 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2546 REG_WR(bp, BNX2_RPM_CONFIG, val);
2557 autoneg = bp->autoneg;
2558 advertising = bp->advertising;
2560 bp->autoneg = AUTONEG_SPEED;
2561 bp->advertising = ADVERTISED_10baseT_Half |
2562 ADVERTISED_10baseT_Full |
2563 ADVERTISED_100baseT_Half |
2564 ADVERTISED_100baseT_Full |
2567 bnx2_setup_copper_phy(bp);
2569 bp->autoneg = autoneg;
2570 bp->advertising = advertising;
2572 bnx2_set_mac_addr(bp);
2574 val = REG_RD(bp, BNX2_EMAC_MODE);
2576 /* Enable port mode. */
2577 val &= ~BNX2_EMAC_MODE_PORT;
2578 val |= BNX2_EMAC_MODE_PORT_MII |
2579 BNX2_EMAC_MODE_MPKT_RCVD |
2580 BNX2_EMAC_MODE_ACPI_RCVD |
2581 BNX2_EMAC_MODE_MPKT;
2583 REG_WR(bp, BNX2_EMAC_MODE, val);
2585 /* receive all multicast */
2586 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2587 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2590 REG_WR(bp, BNX2_EMAC_RX_MODE,
2591 BNX2_EMAC_RX_MODE_SORT_MODE);
2593 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2594 BNX2_RPM_SORT_USER0_MC_EN;
2595 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2596 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2597 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2598 BNX2_RPM_SORT_USER0_ENA);
2600 /* Need to enable EMAC and RPM for WOL. */
2601 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2602 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2603 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2604 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2606 val = REG_RD(bp, BNX2_RPM_CONFIG);
2607 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2608 REG_WR(bp, BNX2_RPM_CONFIG, val);
2610 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2613 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2616 if (!(bp->flags & NO_WOL_FLAG))
2617 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2619 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2620 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2621 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2630 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2632 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2635 /* No more memory access after this point until
2636 * device is brought back to D0.
2648 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2653 /* Request access to the flash interface. */
2654 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2655 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2656 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2657 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2663 if (j >= NVRAM_TIMEOUT_COUNT)
2670 bnx2_release_nvram_lock(struct bnx2 *bp)
2675 /* Relinquish nvram interface. */
2676 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2678 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2679 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2680 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2686 if (j >= NVRAM_TIMEOUT_COUNT)
2694 bnx2_enable_nvram_write(struct bnx2 *bp)
2698 val = REG_RD(bp, BNX2_MISC_CFG);
2699 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2701 if (!bp->flash_info->buffered) {
2704 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2705 REG_WR(bp, BNX2_NVM_COMMAND,
2706 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2708 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2711 val = REG_RD(bp, BNX2_NVM_COMMAND);
2712 if (val & BNX2_NVM_COMMAND_DONE)
2716 if (j >= NVRAM_TIMEOUT_COUNT)
2723 bnx2_disable_nvram_write(struct bnx2 *bp)
2727 val = REG_RD(bp, BNX2_MISC_CFG);
2728 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2733 bnx2_enable_nvram_access(struct bnx2 *bp)
2737 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2738 /* Enable both bits, even on read. */
2739 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2740 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2744 bnx2_disable_nvram_access(struct bnx2 *bp)
2748 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2749 /* Disable both bits, even after read. */
2750 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2751 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2752 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2756 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2761 if (bp->flash_info->buffered)
2762 /* Buffered flash, no erase needed */
2765 /* Build an erase command */
2766 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2767 BNX2_NVM_COMMAND_DOIT;
2769 /* Need to clear DONE bit separately. */
2770 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2772 /* Address of the NVRAM to read from. */
2773 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2775 /* Issue an erase command. */
2776 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2778 /* Wait for completion. */
2779 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2784 val = REG_RD(bp, BNX2_NVM_COMMAND);
2785 if (val & BNX2_NVM_COMMAND_DONE)
2789 if (j >= NVRAM_TIMEOUT_COUNT)
2796 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2801 /* Build the command word. */
2802 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2804 /* Calculate an offset of a buffered flash. */
2805 if (bp->flash_info->buffered) {
2806 offset = ((offset / bp->flash_info->page_size) <<
2807 bp->flash_info->page_bits) +
2808 (offset % bp->flash_info->page_size);
2811 /* Need to clear DONE bit separately. */
2812 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2814 /* Address of the NVRAM to read from. */
2815 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2817 /* Issue a read command. */
2818 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2820 /* Wait for completion. */
2821 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2826 val = REG_RD(bp, BNX2_NVM_COMMAND);
2827 if (val & BNX2_NVM_COMMAND_DONE) {
2828 val = REG_RD(bp, BNX2_NVM_READ);
2830 val = be32_to_cpu(val);
2831 memcpy(ret_val, &val, 4);
2835 if (j >= NVRAM_TIMEOUT_COUNT)
2843 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2848 /* Build the command word. */
2849 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2851 /* Calculate an offset of a buffered flash. */
2852 if (bp->flash_info->buffered) {
2853 offset = ((offset / bp->flash_info->page_size) <<
2854 bp->flash_info->page_bits) +
2855 (offset % bp->flash_info->page_size);
2858 /* Need to clear DONE bit separately. */
2859 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2861 memcpy(&val32, val, 4);
2862 val32 = cpu_to_be32(val32);
2864 /* Write the data. */
2865 REG_WR(bp, BNX2_NVM_WRITE, val32);
2867 /* Address of the NVRAM to write to. */
2868 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2870 /* Issue the write command. */
2871 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2873 /* Wait for completion. */
2874 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2877 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2880 if (j >= NVRAM_TIMEOUT_COUNT)
2887 bnx2_init_nvram(struct bnx2 *bp)
2890 int j, entry_count, rc;
2891 struct flash_spec *flash;
2893 /* Determine the selected interface. */
2894 val = REG_RD(bp, BNX2_NVM_CFG1);
2896 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2899 if (val & 0x40000000) {
2901 /* Flash interface has been reconfigured */
2902 for (j = 0, flash = &flash_table[0]; j < entry_count;
2904 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2905 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2906 bp->flash_info = flash;
2913 /* Not yet been reconfigured */
2915 if (val & (1 << 23))
2916 mask = FLASH_BACKUP_STRAP_MASK;
2918 mask = FLASH_STRAP_MASK;
2920 for (j = 0, flash = &flash_table[0]; j < entry_count;
2923 if ((val & mask) == (flash->strapping & mask)) {
2924 bp->flash_info = flash;
2926 /* Request access to the flash interface. */
2927 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2930 /* Enable access to flash interface */
2931 bnx2_enable_nvram_access(bp);
2933 /* Reconfigure the flash interface */
2934 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2935 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2936 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2937 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2939 /* Disable access to flash interface */
2940 bnx2_disable_nvram_access(bp);
2941 bnx2_release_nvram_lock(bp);
2946 } /* if (val & 0x40000000) */
2948 if (j == entry_count) {
2949 bp->flash_info = NULL;
2950 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2954 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2955 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2957 bp->flash_size = val;
2959 bp->flash_size = bp->flash_info->total_size;
2965 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2969 u32 cmd_flags, offset32, len32, extra;
2974 /* Request access to the flash interface. */
2975 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2978 /* Enable access to flash interface */
2979 bnx2_enable_nvram_access(bp);
2992 pre_len = 4 - (offset & 3);
2994 if (pre_len >= len32) {
2996 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2997 BNX2_NVM_COMMAND_LAST;
3000 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3003 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3008 memcpy(ret_buf, buf + (offset & 3), pre_len);
3015 extra = 4 - (len32 & 3);
3016 len32 = (len32 + 4) & ~3;
3023 cmd_flags = BNX2_NVM_COMMAND_LAST;
3025 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3026 BNX2_NVM_COMMAND_LAST;
3028 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3030 memcpy(ret_buf, buf, 4 - extra);
3032 else if (len32 > 0) {
3035 /* Read the first word. */
3039 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3041 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3043 /* Advance to the next dword. */
3048 while (len32 > 4 && rc == 0) {
3049 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3051 /* Advance to the next dword. */
3060 cmd_flags = BNX2_NVM_COMMAND_LAST;
3061 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3063 memcpy(ret_buf, buf, 4 - extra);
3066 /* Disable access to flash interface */
3067 bnx2_disable_nvram_access(bp);
3069 bnx2_release_nvram_lock(bp);
3075 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3078 u32 written, offset32, len32;
3079 u8 *buf, start[4], end[4], *flash_buffer = NULL;
3081 int align_start, align_end;
3086 align_start = align_end = 0;
3088 if ((align_start = (offset32 & 3))) {
3090 len32 += align_start;
3091 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3096 if ((len32 > 4) || !align_start) {
3097 align_end = 4 - (len32 & 3);
3099 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
3106 if (align_start || align_end) {
3107 buf = kmalloc(len32, GFP_KERNEL);
3111 memcpy(buf, start, 4);
3114 memcpy(buf + len32 - 4, end, 4);
3116 memcpy(buf + align_start, data_buf, buf_size);
3119 if (bp->flash_info->buffered == 0) {
3120 flash_buffer = kmalloc(264, GFP_KERNEL);
3121 if (flash_buffer == NULL) {
3123 goto nvram_write_end;
3128 while ((written < len32) && (rc == 0)) {
3129 u32 page_start, page_end, data_start, data_end;
3130 u32 addr, cmd_flags;
3133 /* Find the page_start addr */
3134 page_start = offset32 + written;
3135 page_start -= (page_start % bp->flash_info->page_size);
3136 /* Find the page_end addr */
3137 page_end = page_start + bp->flash_info->page_size;
3138 /* Find the data_start addr */
3139 data_start = (written == 0) ? offset32 : page_start;
3140 /* Find the data_end addr */
3141 data_end = (page_end > offset32 + len32) ?
3142 (offset32 + len32) : page_end;
3144 /* Request access to the flash interface. */
3145 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3146 goto nvram_write_end;
3148 /* Enable access to flash interface */
3149 bnx2_enable_nvram_access(bp);
3151 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3152 if (bp->flash_info->buffered == 0) {
3155 /* Read the whole page into the buffer
3156 * (non-buffer flash only) */
3157 for (j = 0; j < bp->flash_info->page_size; j += 4) {
3158 if (j == (bp->flash_info->page_size - 4)) {
3159 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3161 rc = bnx2_nvram_read_dword(bp,
3167 goto nvram_write_end;
3173 /* Enable writes to flash interface (unlock write-protect) */
3174 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3175 goto nvram_write_end;
3177 /* Erase the page */
3178 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3179 goto nvram_write_end;
3181 /* Re-enable the write again for the actual write */
3182 bnx2_enable_nvram_write(bp);
3184 /* Loop to write back the buffer data from page_start to
3187 if (bp->flash_info->buffered == 0) {
3188 for (addr = page_start; addr < data_start;
3189 addr += 4, i += 4) {
3191 rc = bnx2_nvram_write_dword(bp, addr,
3192 &flash_buffer[i], cmd_flags);
3195 goto nvram_write_end;
3201 /* Loop to write the new data from data_start to data_end */
3202 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3203 if ((addr == page_end - 4) ||
3204 ((bp->flash_info->buffered) &&
3205 (addr == data_end - 4))) {
3207 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3209 rc = bnx2_nvram_write_dword(bp, addr, buf,
3213 goto nvram_write_end;
3219 /* Loop to write back the buffer data from data_end
3221 if (bp->flash_info->buffered == 0) {
3222 for (addr = data_end; addr < page_end;
3223 addr += 4, i += 4) {
3225 if (addr == page_end-4) {
3226 cmd_flags = BNX2_NVM_COMMAND_LAST;
3228 rc = bnx2_nvram_write_dword(bp, addr,
3229 &flash_buffer[i], cmd_flags);
3232 goto nvram_write_end;
3238 /* Disable writes to flash interface (lock write-protect) */
3239 bnx2_disable_nvram_write(bp);
3241 /* Disable access to flash interface */
3242 bnx2_disable_nvram_access(bp);
3243 bnx2_release_nvram_lock(bp);
3245 /* Increment written */
3246 written += data_end - data_start;
3250 if (bp->flash_info->buffered == 0)
3251 kfree(flash_buffer);
3253 if (align_start || align_end)
3259 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3264 /* Wait for the current PCI transaction to complete before
3265 * issuing a reset. */
3266 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3267 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3268 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3269 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3270 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3271 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3274 /* Wait for the firmware to tell us it is ok to issue a reset. */
3275 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3277 /* Deposit a driver reset signature so the firmware knows that
3278 * this is a soft reset. */
3279 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3280 BNX2_DRV_RESET_SIGNATURE_MAGIC);
3282 /* Do a dummy read to force the chip to complete all current transaction
3283 * before we issue a reset. */
3284 val = REG_RD(bp, BNX2_MISC_ID);
3286 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3287 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3288 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3291 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3293 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3294 (CHIP_ID(bp) == CHIP_ID_5706_A1))
3297 /* Reset takes approximate 30 usec */
3298 for (i = 0; i < 10; i++) {
3299 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3300 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3301 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3307 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3308 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3309 printk(KERN_ERR PFX "Chip reset did not complete\n");
3313 /* Make sure byte swapping is properly configured. */
3314 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3315 if (val != 0x01020304) {
3316 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3320 /* Wait for the firmware to finish its initialization. */
3321 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3325 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3326 /* Adjust the voltage regular to two steps lower. The default
3327 * of this register is 0x0000000e. */
3328 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3330 /* Remove bad rbuf memory from the free pool. */
3331 rc = bnx2_alloc_bad_rbuf(bp);
3338 bnx2_init_chip(struct bnx2 *bp)
3343 /* Make sure the interrupt is not active. */
3344 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3346 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3347 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3349 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3351 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3352 DMA_READ_CHANS << 12 |
3353 DMA_WRITE_CHANS << 16;
3355 val |= (0x2 << 20) | (1 << 11);
3357 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3360 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3361 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3362 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3364 REG_WR(bp, BNX2_DMA_CONFIG, val);
3366 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3367 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3368 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3369 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3372 if (bp->flags & PCIX_FLAG) {
3375 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3377 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3378 val16 & ~PCI_X_CMD_ERO);
3381 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3382 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3383 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3384 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3386 /* Initialize context mapping and zero out the quick contexts. The
3387 * context block must have already been enabled. */
3388 bnx2_init_context(bp);
3390 if ((rc = bnx2_init_cpus(bp)) != 0)
3393 bnx2_init_nvram(bp);
3395 bnx2_set_mac_addr(bp);
3397 val = REG_RD(bp, BNX2_MQ_CONFIG);
3398 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3399 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3400 REG_WR(bp, BNX2_MQ_CONFIG, val);
3402 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3403 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3404 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3406 val = (BCM_PAGE_BITS - 8) << 24;
3407 REG_WR(bp, BNX2_RV2P_CONFIG, val);
3409 /* Configure page size. */
3410 val = REG_RD(bp, BNX2_TBDR_CONFIG);
3411 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3412 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3413 REG_WR(bp, BNX2_TBDR_CONFIG, val);
3415 val = bp->mac_addr[0] +
3416 (bp->mac_addr[1] << 8) +
3417 (bp->mac_addr[2] << 16) +
3419 (bp->mac_addr[4] << 8) +
3420 (bp->mac_addr[5] << 16);
3421 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3423 /* Program the MTU. Also include 4 bytes for CRC32. */
3424 val = bp->dev->mtu + ETH_HLEN + 4;
3425 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3426 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3427 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3429 bp->last_status_idx = 0;
3430 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3432 /* Set up how to generate a link change interrupt. */
3433 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3435 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3436 (u64) bp->status_blk_mapping & 0xffffffff);
3437 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3439 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3440 (u64) bp->stats_blk_mapping & 0xffffffff);
3441 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3442 (u64) bp->stats_blk_mapping >> 32);
3444 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3445 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3447 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3448 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3450 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3451 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3453 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3455 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3457 REG_WR(bp, BNX2_HC_COM_TICKS,
3458 (bp->com_ticks_int << 16) | bp->com_ticks);
3460 REG_WR(bp, BNX2_HC_CMD_TICKS,
3461 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3463 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3464 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3466 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3467 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3469 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3470 BNX2_HC_CONFIG_TX_TMR_MODE |
3471 BNX2_HC_CONFIG_COLLECT_STATS);
3474 /* Clear internal stats counters. */
3475 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3477 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3479 if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3480 BNX2_PORT_FEATURE_ASF_ENABLED)
3481 bp->flags |= ASF_ENABLE_FLAG;
3483 /* Initialize the receive filter. */
3484 bnx2_set_rx_mode(bp->dev);
3486 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3489 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3490 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3494 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
3501 bnx2_init_tx_ring(struct bnx2 *bp)
3506 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3508 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3509 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3514 bp->tx_prod_bseq = 0;
3516 val = BNX2_L2CTX_TYPE_TYPE_L2;
3517 val |= BNX2_L2CTX_TYPE_SIZE_L2;
3518 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
3520 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
3522 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
3524 val = (u64) bp->tx_desc_mapping >> 32;
3525 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
3527 val = (u64) bp->tx_desc_mapping & 0xffffffff;
3528 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
3532 bnx2_init_rx_ring(struct bnx2 *bp)
3536 u16 prod, ring_prod;
3539 /* 8 for CRC and VLAN */
3540 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3541 /* 8 for alignment */
3542 bp->rx_buf_size = bp->rx_buf_use_size + 8;
3544 ring_prod = prod = bp->rx_prod = 0;
3547 bp->rx_prod_bseq = 0;
3549 for (i = 0; i < bp->rx_max_ring; i++) {
3552 rxbd = &bp->rx_desc_ring[i][0];
3553 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
3554 rxbd->rx_bd_len = bp->rx_buf_use_size;
3555 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3557 if (i == (bp->rx_max_ring - 1))
3561 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
3562 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
3566 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3567 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3569 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3571 val = (u64) bp->rx_desc_mapping[0] >> 32;
3572 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3574 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
3575 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3577 for (i = 0; i < bp->rx_ring_size; i++) {
3578 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3581 prod = NEXT_RX_BD(prod);
3582 ring_prod = RX_RING_IDX(prod);
3586 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3588 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3592 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
3596 bp->rx_ring_size = size;
3598 while (size > MAX_RX_DESC_CNT) {
3599 size -= MAX_RX_DESC_CNT;
3602 /* round to next power of 2 */
3604 while ((max & num_rings) == 0)
3607 if (num_rings != max)
3610 bp->rx_max_ring = max;
3611 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
3615 bnx2_free_tx_skbs(struct bnx2 *bp)
3619 if (bp->tx_buf_ring == NULL)
3622 for (i = 0; i < TX_DESC_CNT; ) {
3623 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3624 struct sk_buff *skb = tx_buf->skb;
3632 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3633 skb_headlen(skb), PCI_DMA_TODEVICE);
3637 last = skb_shinfo(skb)->nr_frags;
3638 for (j = 0; j < last; j++) {
3639 tx_buf = &bp->tx_buf_ring[i + j + 1];
3640 pci_unmap_page(bp->pdev,
3641 pci_unmap_addr(tx_buf, mapping),
3642 skb_shinfo(skb)->frags[j].size,
3652 bnx2_free_rx_skbs(struct bnx2 *bp)
3656 if (bp->rx_buf_ring == NULL)
3659 for (i = 0; i < bp->rx_max_ring_idx; i++) {
3660 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3661 struct sk_buff *skb = rx_buf->skb;
3666 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3667 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3676 bnx2_free_skbs(struct bnx2 *bp)
3678 bnx2_free_tx_skbs(bp);
3679 bnx2_free_rx_skbs(bp);
3683 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3687 rc = bnx2_reset_chip(bp, reset_code);
3692 if ((rc = bnx2_init_chip(bp)) != 0)
3695 bnx2_init_tx_ring(bp);
3696 bnx2_init_rx_ring(bp);
3701 bnx2_init_nic(struct bnx2 *bp)
3705 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3714 bnx2_test_registers(struct bnx2 *bp)
3718 static const struct {
3724 { 0x006c, 0, 0x00000000, 0x0000003f },
3725 { 0x0090, 0, 0xffffffff, 0x00000000 },
3726 { 0x0094, 0, 0x00000000, 0x00000000 },
3728 { 0x0404, 0, 0x00003f00, 0x00000000 },
3729 { 0x0418, 0, 0x00000000, 0xffffffff },
3730 { 0x041c, 0, 0x00000000, 0xffffffff },
3731 { 0x0420, 0, 0x00000000, 0x80ffffff },
3732 { 0x0424, 0, 0x00000000, 0x00000000 },
3733 { 0x0428, 0, 0x00000000, 0x00000001 },
3734 { 0x0450, 0, 0x00000000, 0x0000ffff },
3735 { 0x0454, 0, 0x00000000, 0xffffffff },
3736 { 0x0458, 0, 0x00000000, 0xffffffff },
3738 { 0x0808, 0, 0x00000000, 0xffffffff },
3739 { 0x0854, 0, 0x00000000, 0xffffffff },
3740 { 0x0868, 0, 0x00000000, 0x77777777 },
3741 { 0x086c, 0, 0x00000000, 0x77777777 },
3742 { 0x0870, 0, 0x00000000, 0x77777777 },
3743 { 0x0874, 0, 0x00000000, 0x77777777 },
3745 { 0x0c00, 0, 0x00000000, 0x00000001 },
3746 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3747 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3749 { 0x1000, 0, 0x00000000, 0x00000001 },
3750 { 0x1004, 0, 0x00000000, 0x000f0001 },
3752 { 0x1408, 0, 0x01c00800, 0x00000000 },
3753 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3754 { 0x14a8, 0, 0x00000000, 0x000001ff },
3755 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3756 { 0x14b0, 0, 0x00000002, 0x00000001 },
3757 { 0x14b8, 0, 0x00000000, 0x00000000 },
3758 { 0x14c0, 0, 0x00000000, 0x00000009 },
3759 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3760 { 0x14cc, 0, 0x00000000, 0x00000001 },
3761 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3763 { 0x1800, 0, 0x00000000, 0x00000001 },
3764 { 0x1804, 0, 0x00000000, 0x00000003 },
3766 { 0x2800, 0, 0x00000000, 0x00000001 },
3767 { 0x2804, 0, 0x00000000, 0x00003f01 },
3768 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3769 { 0x2810, 0, 0xffff0000, 0x00000000 },
3770 { 0x2814, 0, 0xffff0000, 0x00000000 },
3771 { 0x2818, 0, 0xffff0000, 0x00000000 },
3772 { 0x281c, 0, 0xffff0000, 0x00000000 },
3773 { 0x2834, 0, 0xffffffff, 0x00000000 },
3774 { 0x2840, 0, 0x00000000, 0xffffffff },
3775 { 0x2844, 0, 0x00000000, 0xffffffff },
3776 { 0x2848, 0, 0xffffffff, 0x00000000 },
3777 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3779 { 0x2c00, 0, 0x00000000, 0x00000011 },
3780 { 0x2c04, 0, 0x00000000, 0x00030007 },
3782 { 0x3c00, 0, 0x00000000, 0x00000001 },
3783 { 0x3c04, 0, 0x00000000, 0x00070000 },
3784 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3785 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3786 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3787 { 0x3c14, 0, 0x00000000, 0xffffffff },
3788 { 0x3c18, 0, 0x00000000, 0xffffffff },
3789 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3790 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3792 { 0x5004, 0, 0x00000000, 0x0000007f },
3793 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3794 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3796 { 0x5c00, 0, 0x00000000, 0x00000001 },
3797 { 0x5c04, 0, 0x00000000, 0x0003000f },
3798 { 0x5c08, 0, 0x00000003, 0x00000000 },
3799 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3800 { 0x5c10, 0, 0x00000000, 0xffffffff },
3801 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3802 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3803 { 0x5c88, 0, 0x00000000, 0x00077373 },
3804 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3806 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3807 { 0x680c, 0, 0xffffffff, 0x00000000 },
3808 { 0x6810, 0, 0xffffffff, 0x00000000 },
3809 { 0x6814, 0, 0xffffffff, 0x00000000 },
3810 { 0x6818, 0, 0xffffffff, 0x00000000 },
3811 { 0x681c, 0, 0xffffffff, 0x00000000 },
3812 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3813 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3814 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3815 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3816 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3817 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3818 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3819 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3820 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3821 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3822 { 0x684c, 0, 0xffffffff, 0x00000000 },
3823 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3824 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3825 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3826 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3827 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3828 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3830 { 0xffff, 0, 0x00000000, 0x00000000 },
3834 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3835 u32 offset, rw_mask, ro_mask, save_val, val;
3837 offset = (u32) reg_tbl[i].offset;
3838 rw_mask = reg_tbl[i].rw_mask;
3839 ro_mask = reg_tbl[i].ro_mask;
3841 save_val = readl(bp->regview + offset);
3843 writel(0, bp->regview + offset);
3845 val = readl(bp->regview + offset);
3846 if ((val & rw_mask) != 0) {
3850 if ((val & ro_mask) != (save_val & ro_mask)) {
3854 writel(0xffffffff, bp->regview + offset);
3856 val = readl(bp->regview + offset);
3857 if ((val & rw_mask) != rw_mask) {
3861 if ((val & ro_mask) != (save_val & ro_mask)) {
3865 writel(save_val, bp->regview + offset);
3869 writel(save_val, bp->regview + offset);
3877 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3879 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3880 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3883 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3886 for (offset = 0; offset < size; offset += 4) {
3888 REG_WR_IND(bp, start + offset, test_pattern[i]);
3890 if (REG_RD_IND(bp, start + offset) !=
3900 bnx2_test_memory(struct bnx2 *bp)
3904 static const struct {
3908 { 0x60000, 0x4000 },
3909 { 0xa0000, 0x3000 },
3910 { 0xe0000, 0x4000 },
3911 { 0x120000, 0x4000 },
3912 { 0x1a0000, 0x4000 },
3913 { 0x160000, 0x4000 },
3917 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3918 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3919 mem_tbl[i].len)) != 0) {
3927 #define BNX2_MAC_LOOPBACK 0
3928 #define BNX2_PHY_LOOPBACK 1
3931 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3933 unsigned int pkt_size, num_pkts, i;
3934 struct sk_buff *skb, *rx_skb;
3935 unsigned char *packet;
3936 u16 rx_start_idx, rx_idx;
3939 struct sw_bd *rx_buf;
3940 struct l2_fhdr *rx_hdr;
3943 if (loopback_mode == BNX2_MAC_LOOPBACK) {
3944 bp->loopback = MAC_LOOPBACK;
3945 bnx2_set_mac_loopback(bp);
3947 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
3949 bnx2_set_phy_loopback(bp);
3955 skb = dev_alloc_skb(pkt_size);
3958 packet = skb_put(skb, pkt_size);
3959 memcpy(packet, bp->mac_addr, 6);
3960 memset(packet + 6, 0x0, 8);
3961 for (i = 14; i < pkt_size; i++)
3962 packet[i] = (unsigned char) (i & 0xff);
3964 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3967 REG_WR(bp, BNX2_HC_COMMAND,
3968 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3970 REG_RD(bp, BNX2_HC_COMMAND);
3973 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3977 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
3979 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3980 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3981 txbd->tx_bd_mss_nbytes = pkt_size;
3982 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3985 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
3986 bp->tx_prod_bseq += pkt_size;
3988 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, bp->tx_prod);
3989 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
3993 REG_WR(bp, BNX2_HC_COMMAND,
3994 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3996 REG_RD(bp, BNX2_HC_COMMAND);
4000 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4003 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4004 goto loopback_test_done;
4007 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4008 if (rx_idx != rx_start_idx + num_pkts) {
4009 goto loopback_test_done;
4012 rx_buf = &bp->rx_buf_ring[rx_start_idx];
4013 rx_skb = rx_buf->skb;
4015 rx_hdr = (struct l2_fhdr *) rx_skb->data;
4016 skb_reserve(rx_skb, bp->rx_offset);
4018 pci_dma_sync_single_for_cpu(bp->pdev,
4019 pci_unmap_addr(rx_buf, mapping),
4020 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4022 if (rx_hdr->l2_fhdr_status &
4023 (L2_FHDR_ERRORS_BAD_CRC |
4024 L2_FHDR_ERRORS_PHY_DECODE |
4025 L2_FHDR_ERRORS_ALIGNMENT |
4026 L2_FHDR_ERRORS_TOO_SHORT |
4027 L2_FHDR_ERRORS_GIANT_FRAME)) {
4029 goto loopback_test_done;
4032 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4033 goto loopback_test_done;
4036 for (i = 14; i < pkt_size; i++) {
4037 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4038 goto loopback_test_done;
4049 #define BNX2_MAC_LOOPBACK_FAILED 1
4050 #define BNX2_PHY_LOOPBACK_FAILED 2
4051 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
4052 BNX2_PHY_LOOPBACK_FAILED)
4055 bnx2_test_loopback(struct bnx2 *bp)
4059 if (!netif_running(bp->dev))
4060 return BNX2_LOOPBACK_FAILED;
4062 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4063 spin_lock_bh(&bp->phy_lock);
4065 spin_unlock_bh(&bp->phy_lock);
4066 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4067 rc |= BNX2_MAC_LOOPBACK_FAILED;
4068 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4069 rc |= BNX2_PHY_LOOPBACK_FAILED;
4073 #define NVRAM_SIZE 0x200
4074 #define CRC32_RESIDUAL 0xdebb20e3
4077 bnx2_test_nvram(struct bnx2 *bp)
4079 u32 buf[NVRAM_SIZE / 4];
4080 u8 *data = (u8 *) buf;
4084 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4085 goto test_nvram_done;
4087 magic = be32_to_cpu(buf[0]);
4088 if (magic != 0x669955aa) {
4090 goto test_nvram_done;
4093 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4094 goto test_nvram_done;
4096 csum = ether_crc_le(0x100, data);
4097 if (csum != CRC32_RESIDUAL) {
4099 goto test_nvram_done;
4102 csum = ether_crc_le(0x100, data + 0x100);
4103 if (csum != CRC32_RESIDUAL) {
4112 bnx2_test_link(struct bnx2 *bp)
4116 spin_lock_bh(&bp->phy_lock);
4117 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4118 bnx2_read_phy(bp, MII_BMSR, &bmsr);
4119 spin_unlock_bh(&bp->phy_lock);
4121 if (bmsr & BMSR_LSTATUS) {
4128 bnx2_test_intr(struct bnx2 *bp)
4133 if (!netif_running(bp->dev))
4136 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4138 /* This register is not touched during run-time. */
4139 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4140 REG_RD(bp, BNX2_HC_COMMAND);
4142 for (i = 0; i < 10; i++) {
4143 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4149 msleep_interruptible(10);
4158 bnx2_timer(unsigned long data)
4160 struct bnx2 *bp = (struct bnx2 *) data;
4163 if (!netif_running(bp->dev))
4166 if (atomic_read(&bp->intr_sem) != 0)
4167 goto bnx2_restart_timer;
4169 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4170 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4172 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4174 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
4175 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
4177 spin_lock(&bp->phy_lock);
4178 if (bp->serdes_an_pending) {
4179 bp->serdes_an_pending--;
4181 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4184 bp->current_interval = bp->timer_interval;
4186 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4188 if (bmcr & BMCR_ANENABLE) {
4191 bnx2_write_phy(bp, 0x1c, 0x7c00);
4192 bnx2_read_phy(bp, 0x1c, &phy1);
4194 bnx2_write_phy(bp, 0x17, 0x0f01);
4195 bnx2_read_phy(bp, 0x15, &phy2);
4196 bnx2_write_phy(bp, 0x17, 0x0f01);
4197 bnx2_read_phy(bp, 0x15, &phy2);
4199 if ((phy1 & 0x10) && /* SIGNAL DETECT */
4200 !(phy2 & 0x20)) { /* no CONFIG */
4202 bmcr &= ~BMCR_ANENABLE;
4203 bmcr |= BMCR_SPEED1000 |
4205 bnx2_write_phy(bp, MII_BMCR, bmcr);
4207 PHY_PARALLEL_DETECT_FLAG;
4211 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4212 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4215 bnx2_write_phy(bp, 0x17, 0x0f01);
4216 bnx2_read_phy(bp, 0x15, &phy2);
4220 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4221 bmcr |= BMCR_ANENABLE;
4222 bnx2_write_phy(bp, MII_BMCR, bmcr);
4224 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4229 bp->current_interval = bp->timer_interval;
4231 spin_unlock(&bp->phy_lock);
4235 mod_timer(&bp->timer, jiffies + bp->current_interval);
4238 /* Called with rtnl_lock */
4240 bnx2_open(struct net_device *dev)
4242 struct bnx2 *bp = netdev_priv(dev);
4245 bnx2_set_power_state(bp, PCI_D0);
4246 bnx2_disable_int(bp);
4248 rc = bnx2_alloc_mem(bp);
4252 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4253 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4256 if (pci_enable_msi(bp->pdev) == 0) {
4257 bp->flags |= USING_MSI_FLAG;
4258 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4262 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4263 IRQF_SHARED, dev->name, dev);
4267 rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED,
4275 rc = bnx2_init_nic(bp);
4278 free_irq(bp->pdev->irq, dev);
4279 if (bp->flags & USING_MSI_FLAG) {
4280 pci_disable_msi(bp->pdev);
4281 bp->flags &= ~USING_MSI_FLAG;
4288 mod_timer(&bp->timer, jiffies + bp->current_interval);
4290 atomic_set(&bp->intr_sem, 0);
4292 bnx2_enable_int(bp);
4294 if (bp->flags & USING_MSI_FLAG) {
4295 /* Test MSI to make sure it is working
4296 * If MSI test fails, go back to INTx mode
4298 if (bnx2_test_intr(bp) != 0) {
4299 printk(KERN_WARNING PFX "%s: No interrupt was generated"
4300 " using MSI, switching to INTx mode. Please"
4301 " report this failure to the PCI maintainer"
4302 " and include system chipset information.\n",
4305 bnx2_disable_int(bp);
4306 free_irq(bp->pdev->irq, dev);
4307 pci_disable_msi(bp->pdev);
4308 bp->flags &= ~USING_MSI_FLAG;
4310 rc = bnx2_init_nic(bp);
4313 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4314 IRQF_SHARED, dev->name, dev);
4319 del_timer_sync(&bp->timer);
4322 bnx2_enable_int(bp);
4325 if (bp->flags & USING_MSI_FLAG) {
4326 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4329 netif_start_queue(dev);
4335 bnx2_reset_task(void *data)
4337 struct bnx2 *bp = data;
4339 if (!netif_running(bp->dev))
4342 bp->in_reset_task = 1;
4343 bnx2_netif_stop(bp);
4347 atomic_set(&bp->intr_sem, 1);
4348 bnx2_netif_start(bp);
4349 bp->in_reset_task = 0;
4353 bnx2_tx_timeout(struct net_device *dev)
4355 struct bnx2 *bp = netdev_priv(dev);
4357 /* This allows the netif to be shutdown gracefully before resetting */
4358 schedule_work(&bp->reset_task);
4362 /* Called with rtnl_lock */
4364 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4366 struct bnx2 *bp = netdev_priv(dev);
4368 bnx2_netif_stop(bp);
4371 bnx2_set_rx_mode(dev);
4373 bnx2_netif_start(bp);
4376 /* Called with rtnl_lock */
4378 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4380 struct bnx2 *bp = netdev_priv(dev);
4382 bnx2_netif_stop(bp);
4385 bp->vlgrp->vlan_devices[vid] = NULL;
4386 bnx2_set_rx_mode(dev);
4388 bnx2_netif_start(bp);
4392 /* Called with netif_tx_lock.
4393 * hard_start_xmit is pseudo-lockless - a lock is only required when
4394 * the tx queue is full. This way, we get the benefit of lockless
4395 * operations most of the time without the complexities to handle
4396 * netif_stop_queue/wake_queue race conditions.
4399 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4401 struct bnx2 *bp = netdev_priv(dev);
4404 struct sw_bd *tx_buf;
4405 u32 len, vlan_tag_flags, last_frag, mss;
4406 u16 prod, ring_prod;
4409 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4410 netif_stop_queue(dev);
4411 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4414 return NETDEV_TX_BUSY;
4416 len = skb_headlen(skb);
4418 ring_prod = TX_RING_IDX(prod);
4421 if (skb->ip_summed == CHECKSUM_HW) {
4422 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4425 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4427 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4430 if ((mss = skb_shinfo(skb)->gso_size) &&
4431 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4432 u32 tcp_opt_len, ip_tcp_len;
4434 if (skb_header_cloned(skb) &&
4435 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4437 return NETDEV_TX_OK;
4440 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4441 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4444 if (skb->h.th->doff > 5) {
4445 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4447 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4449 skb->nh.iph->check = 0;
4450 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4452 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4456 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4457 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4458 (tcp_opt_len >> 2)) << 8;
4467 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4469 tx_buf = &bp->tx_buf_ring[ring_prod];
4471 pci_unmap_addr_set(tx_buf, mapping, mapping);
4473 txbd = &bp->tx_desc_ring[ring_prod];
4475 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4476 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4477 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4478 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4480 last_frag = skb_shinfo(skb)->nr_frags;
4482 for (i = 0; i < last_frag; i++) {
4483 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4485 prod = NEXT_TX_BD(prod);
4486 ring_prod = TX_RING_IDX(prod);
4487 txbd = &bp->tx_desc_ring[ring_prod];
4490 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4491 len, PCI_DMA_TODEVICE);
4492 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4495 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4496 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4497 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4498 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4501 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4503 prod = NEXT_TX_BD(prod);
4504 bp->tx_prod_bseq += skb->len;
4506 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4507 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4512 dev->trans_start = jiffies;
4514 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4515 spin_lock(&bp->tx_lock);
4516 netif_stop_queue(dev);
4518 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4519 netif_wake_queue(dev);
4520 spin_unlock(&bp->tx_lock);
4523 return NETDEV_TX_OK;
4526 /* Called with rtnl_lock */
4528 bnx2_close(struct net_device *dev)
4530 struct bnx2 *bp = netdev_priv(dev);
4533 /* Calling flush_scheduled_work() may deadlock because
4534 * linkwatch_event() may be on the workqueue and it will try to get
4535 * the rtnl_lock which we are holding.
4537 while (bp->in_reset_task)
4540 bnx2_netif_stop(bp);
4541 del_timer_sync(&bp->timer);
4542 if (bp->flags & NO_WOL_FLAG)
4543 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
4545 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4547 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4548 bnx2_reset_chip(bp, reset_code);
4549 free_irq(bp->pdev->irq, dev);
4550 if (bp->flags & USING_MSI_FLAG) {
4551 pci_disable_msi(bp->pdev);
4552 bp->flags &= ~USING_MSI_FLAG;
4557 netif_carrier_off(bp->dev);
4558 bnx2_set_power_state(bp, PCI_D3hot);
4562 #define GET_NET_STATS64(ctr) \
4563 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4564 (unsigned long) (ctr##_lo)
4566 #define GET_NET_STATS32(ctr) \
4569 #if (BITS_PER_LONG == 64)
4570 #define GET_NET_STATS GET_NET_STATS64
4572 #define GET_NET_STATS GET_NET_STATS32
4575 static struct net_device_stats *
4576 bnx2_get_stats(struct net_device *dev)
4578 struct bnx2 *bp = netdev_priv(dev);
4579 struct statistics_block *stats_blk = bp->stats_blk;
4580 struct net_device_stats *net_stats = &bp->net_stats;
4582 if (bp->stats_blk == NULL) {
4585 net_stats->rx_packets =
4586 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4587 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4588 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4590 net_stats->tx_packets =
4591 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4592 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4593 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4595 net_stats->rx_bytes =
4596 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4598 net_stats->tx_bytes =
4599 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4601 net_stats->multicast =
4602 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4604 net_stats->collisions =
4605 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4607 net_stats->rx_length_errors =
4608 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4609 stats_blk->stat_EtherStatsOverrsizePkts);
4611 net_stats->rx_over_errors =
4612 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4614 net_stats->rx_frame_errors =
4615 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4617 net_stats->rx_crc_errors =
4618 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4620 net_stats->rx_errors = net_stats->rx_length_errors +
4621 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4622 net_stats->rx_crc_errors;
4624 net_stats->tx_aborted_errors =
4625 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4626 stats_blk->stat_Dot3StatsLateCollisions);
4628 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4629 (CHIP_ID(bp) == CHIP_ID_5708_A0))
4630 net_stats->tx_carrier_errors = 0;
4632 net_stats->tx_carrier_errors =
4634 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4637 net_stats->tx_errors =
4639 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4641 net_stats->tx_aborted_errors +
4642 net_stats->tx_carrier_errors;
4644 net_stats->rx_missed_errors =
4645 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
4646 stats_blk->stat_FwRxDrop);
4651 /* All ethtool functions called with rtnl_lock */
4654 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4656 struct bnx2 *bp = netdev_priv(dev);
4658 cmd->supported = SUPPORTED_Autoneg;
4659 if (bp->phy_flags & PHY_SERDES_FLAG) {
4660 cmd->supported |= SUPPORTED_1000baseT_Full |
4663 cmd->port = PORT_FIBRE;
4666 cmd->supported |= SUPPORTED_10baseT_Half |
4667 SUPPORTED_10baseT_Full |
4668 SUPPORTED_100baseT_Half |
4669 SUPPORTED_100baseT_Full |
4670 SUPPORTED_1000baseT_Full |
4673 cmd->port = PORT_TP;
4676 cmd->advertising = bp->advertising;
4678 if (bp->autoneg & AUTONEG_SPEED) {
4679 cmd->autoneg = AUTONEG_ENABLE;
4682 cmd->autoneg = AUTONEG_DISABLE;
4685 if (netif_carrier_ok(dev)) {
4686 cmd->speed = bp->line_speed;
4687 cmd->duplex = bp->duplex;
4694 cmd->transceiver = XCVR_INTERNAL;
4695 cmd->phy_address = bp->phy_addr;
4701 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4703 struct bnx2 *bp = netdev_priv(dev);
4704 u8 autoneg = bp->autoneg;
4705 u8 req_duplex = bp->req_duplex;
4706 u16 req_line_speed = bp->req_line_speed;
4707 u32 advertising = bp->advertising;
4709 if (cmd->autoneg == AUTONEG_ENABLE) {
4710 autoneg |= AUTONEG_SPEED;
4712 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4714 /* allow advertising 1 speed */
4715 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4716 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4717 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4718 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4720 if (bp->phy_flags & PHY_SERDES_FLAG)
4723 advertising = cmd->advertising;
4726 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4727 advertising = cmd->advertising;
4729 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4733 if (bp->phy_flags & PHY_SERDES_FLAG) {
4734 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4737 advertising = ETHTOOL_ALL_COPPER_SPEED;
4740 advertising |= ADVERTISED_Autoneg;
4743 if (bp->phy_flags & PHY_SERDES_FLAG) {
4744 if ((cmd->speed != SPEED_1000) ||
4745 (cmd->duplex != DUPLEX_FULL)) {
4749 else if (cmd->speed == SPEED_1000) {
4752 autoneg &= ~AUTONEG_SPEED;
4753 req_line_speed = cmd->speed;
4754 req_duplex = cmd->duplex;
4758 bp->autoneg = autoneg;
4759 bp->advertising = advertising;
4760 bp->req_line_speed = req_line_speed;
4761 bp->req_duplex = req_duplex;
4763 spin_lock_bh(&bp->phy_lock);
4767 spin_unlock_bh(&bp->phy_lock);
4773 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4775 struct bnx2 *bp = netdev_priv(dev);
4777 strcpy(info->driver, DRV_MODULE_NAME);
4778 strcpy(info->version, DRV_MODULE_VERSION);
4779 strcpy(info->bus_info, pci_name(bp->pdev));
4780 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4781 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4782 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4783 info->fw_version[1] = info->fw_version[3] = '.';
4784 info->fw_version[5] = 0;
4787 #define BNX2_REGDUMP_LEN (32 * 1024)
4790 bnx2_get_regs_len(struct net_device *dev)
4792 return BNX2_REGDUMP_LEN;
4796 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
4798 u32 *p = _p, i, offset;
4800 struct bnx2 *bp = netdev_priv(dev);
4801 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
4802 0x0800, 0x0880, 0x0c00, 0x0c10,
4803 0x0c30, 0x0d08, 0x1000, 0x101c,
4804 0x1040, 0x1048, 0x1080, 0x10a4,
4805 0x1400, 0x1490, 0x1498, 0x14f0,
4806 0x1500, 0x155c, 0x1580, 0x15dc,
4807 0x1600, 0x1658, 0x1680, 0x16d8,
4808 0x1800, 0x1820, 0x1840, 0x1854,
4809 0x1880, 0x1894, 0x1900, 0x1984,
4810 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
4811 0x1c80, 0x1c94, 0x1d00, 0x1d84,
4812 0x2000, 0x2030, 0x23c0, 0x2400,
4813 0x2800, 0x2820, 0x2830, 0x2850,
4814 0x2b40, 0x2c10, 0x2fc0, 0x3058,
4815 0x3c00, 0x3c94, 0x4000, 0x4010,
4816 0x4080, 0x4090, 0x43c0, 0x4458,
4817 0x4c00, 0x4c18, 0x4c40, 0x4c54,
4818 0x4fc0, 0x5010, 0x53c0, 0x5444,
4819 0x5c00, 0x5c18, 0x5c80, 0x5c90,
4820 0x5fc0, 0x6000, 0x6400, 0x6428,
4821 0x6800, 0x6848, 0x684c, 0x6860,
4822 0x6888, 0x6910, 0x8000 };
4826 memset(p, 0, BNX2_REGDUMP_LEN);
4828 if (!netif_running(bp->dev))
4832 offset = reg_boundaries[0];
4834 while (offset < BNX2_REGDUMP_LEN) {
4835 *p++ = REG_RD(bp, offset);
4837 if (offset == reg_boundaries[i + 1]) {
4838 offset = reg_boundaries[i + 2];
4839 p = (u32 *) (orig_p + offset);
4846 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4848 struct bnx2 *bp = netdev_priv(dev);
4850 if (bp->flags & NO_WOL_FLAG) {
4855 wol->supported = WAKE_MAGIC;
4857 wol->wolopts = WAKE_MAGIC;
4861 memset(&wol->sopass, 0, sizeof(wol->sopass));
4865 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4867 struct bnx2 *bp = netdev_priv(dev);
4869 if (wol->wolopts & ~WAKE_MAGIC)
4872 if (wol->wolopts & WAKE_MAGIC) {
4873 if (bp->flags & NO_WOL_FLAG)
4885 bnx2_nway_reset(struct net_device *dev)
4887 struct bnx2 *bp = netdev_priv(dev);
4890 if (!(bp->autoneg & AUTONEG_SPEED)) {
4894 spin_lock_bh(&bp->phy_lock);
4896 /* Force a link down visible on the other side */
4897 if (bp->phy_flags & PHY_SERDES_FLAG) {
4898 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4899 spin_unlock_bh(&bp->phy_lock);
4903 spin_lock_bh(&bp->phy_lock);
4904 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4905 bp->current_interval = SERDES_AN_TIMEOUT;
4906 bp->serdes_an_pending = 1;
4907 mod_timer(&bp->timer, jiffies + bp->current_interval);
4911 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4912 bmcr &= ~BMCR_LOOPBACK;
4913 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4915 spin_unlock_bh(&bp->phy_lock);
4921 bnx2_get_eeprom_len(struct net_device *dev)
4923 struct bnx2 *bp = netdev_priv(dev);
4925 if (bp->flash_info == NULL)
4928 return (int) bp->flash_size;
4932 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4935 struct bnx2 *bp = netdev_priv(dev);
4938 /* parameters already validated in ethtool_get_eeprom */
4940 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4946 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4949 struct bnx2 *bp = netdev_priv(dev);
4952 /* parameters already validated in ethtool_set_eeprom */
4954 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4960 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4962 struct bnx2 *bp = netdev_priv(dev);
4964 memset(coal, 0, sizeof(struct ethtool_coalesce));
4966 coal->rx_coalesce_usecs = bp->rx_ticks;
4967 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4968 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4969 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4971 coal->tx_coalesce_usecs = bp->tx_ticks;
4972 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4973 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4974 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4976 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4982 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4984 struct bnx2 *bp = netdev_priv(dev);
4986 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4987 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4989 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4990 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4992 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4993 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4995 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4996 if (bp->rx_quick_cons_trip_int > 0xff)
4997 bp->rx_quick_cons_trip_int = 0xff;
4999 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5000 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5002 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5003 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5005 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5006 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5008 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5009 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5012 bp->stats_ticks = coal->stats_block_coalesce_usecs;
5013 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
5014 bp->stats_ticks &= 0xffff00;
5016 if (netif_running(bp->dev)) {
5017 bnx2_netif_stop(bp);
5019 bnx2_netif_start(bp);
5026 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5028 struct bnx2 *bp = netdev_priv(dev);
5030 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5031 ering->rx_mini_max_pending = 0;
5032 ering->rx_jumbo_max_pending = 0;
5034 ering->rx_pending = bp->rx_ring_size;
5035 ering->rx_mini_pending = 0;
5036 ering->rx_jumbo_pending = 0;
5038 ering->tx_max_pending = MAX_TX_DESC_CNT;
5039 ering->tx_pending = bp->tx_ring_size;
5043 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5045 struct bnx2 *bp = netdev_priv(dev);
5047 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5048 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5049 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5053 if (netif_running(bp->dev)) {
5054 bnx2_netif_stop(bp);
5055 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5060 bnx2_set_rx_ring_size(bp, ering->rx_pending);
5061 bp->tx_ring_size = ering->tx_pending;
5063 if (netif_running(bp->dev)) {
5066 rc = bnx2_alloc_mem(bp);
5070 bnx2_netif_start(bp);
5077 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5079 struct bnx2 *bp = netdev_priv(dev);
5081 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5082 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5083 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5087 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5089 struct bnx2 *bp = netdev_priv(dev);
5091 bp->req_flow_ctrl = 0;
5092 if (epause->rx_pause)
5093 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5094 if (epause->tx_pause)
5095 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5097 if (epause->autoneg) {
5098 bp->autoneg |= AUTONEG_FLOW_CTRL;
5101 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5104 spin_lock_bh(&bp->phy_lock);
5108 spin_unlock_bh(&bp->phy_lock);
5114 bnx2_get_rx_csum(struct net_device *dev)
5116 struct bnx2 *bp = netdev_priv(dev);
5122 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5124 struct bnx2 *bp = netdev_priv(dev);
5131 bnx2_set_tso(struct net_device *dev, u32 data)
5134 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5136 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
5140 #define BNX2_NUM_STATS 46
5143 char string[ETH_GSTRING_LEN];
5144 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5146 { "rx_error_bytes" },
5148 { "tx_error_bytes" },
5149 { "rx_ucast_packets" },
5150 { "rx_mcast_packets" },
5151 { "rx_bcast_packets" },
5152 { "tx_ucast_packets" },
5153 { "tx_mcast_packets" },
5154 { "tx_bcast_packets" },
5155 { "tx_mac_errors" },
5156 { "tx_carrier_errors" },
5157 { "rx_crc_errors" },
5158 { "rx_align_errors" },
5159 { "tx_single_collisions" },
5160 { "tx_multi_collisions" },
5162 { "tx_excess_collisions" },
5163 { "tx_late_collisions" },
5164 { "tx_total_collisions" },
5167 { "rx_undersize_packets" },
5168 { "rx_oversize_packets" },
5169 { "rx_64_byte_packets" },
5170 { "rx_65_to_127_byte_packets" },
5171 { "rx_128_to_255_byte_packets" },
5172 { "rx_256_to_511_byte_packets" },
5173 { "rx_512_to_1023_byte_packets" },
5174 { "rx_1024_to_1522_byte_packets" },
5175 { "rx_1523_to_9022_byte_packets" },
5176 { "tx_64_byte_packets" },
5177 { "tx_65_to_127_byte_packets" },
5178 { "tx_128_to_255_byte_packets" },
5179 { "tx_256_to_511_byte_packets" },
5180 { "tx_512_to_1023_byte_packets" },
5181 { "tx_1024_to_1522_byte_packets" },
5182 { "tx_1523_to_9022_byte_packets" },
5183 { "rx_xon_frames" },
5184 { "rx_xoff_frames" },
5185 { "tx_xon_frames" },
5186 { "tx_xoff_frames" },
5187 { "rx_mac_ctrl_frames" },
5188 { "rx_filtered_packets" },
5190 { "rx_fw_discards" },
5193 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5195 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5196 STATS_OFFSET32(stat_IfHCInOctets_hi),
5197 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5198 STATS_OFFSET32(stat_IfHCOutOctets_hi),
5199 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5200 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5201 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5202 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5203 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5204 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5205 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5206 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5207 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5208 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5209 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5210 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5211 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5212 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5213 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5214 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5215 STATS_OFFSET32(stat_EtherStatsCollisions),
5216 STATS_OFFSET32(stat_EtherStatsFragments),
5217 STATS_OFFSET32(stat_EtherStatsJabbers),
5218 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5219 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5220 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5221 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5222 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5223 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5224 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5225 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5226 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5227 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5228 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5229 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5230 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5231 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5232 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5233 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5234 STATS_OFFSET32(stat_XonPauseFramesReceived),
5235 STATS_OFFSET32(stat_XoffPauseFramesReceived),
5236 STATS_OFFSET32(stat_OutXonSent),
5237 STATS_OFFSET32(stat_OutXoffSent),
5238 STATS_OFFSET32(stat_MacControlFramesReceived),
5239 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5240 STATS_OFFSET32(stat_IfInMBUFDiscards),
5241 STATS_OFFSET32(stat_FwRxDrop),
5244 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5245 * skipped because of errata.
5247 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5248 8,0,8,8,8,8,8,8,8,8,
5249 4,0,4,4,4,4,4,4,4,4,
5250 4,4,4,4,4,4,4,4,4,4,
5251 4,4,4,4,4,4,4,4,4,4,
5255 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5256 8,0,8,8,8,8,8,8,8,8,
5257 4,4,4,4,4,4,4,4,4,4,
5258 4,4,4,4,4,4,4,4,4,4,
5259 4,4,4,4,4,4,4,4,4,4,
5263 #define BNX2_NUM_TESTS 6
5266 char string[ETH_GSTRING_LEN];
5267 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5268 { "register_test (offline)" },
5269 { "memory_test (offline)" },
5270 { "loopback_test (offline)" },
5271 { "nvram_test (online)" },
5272 { "interrupt_test (online)" },
5273 { "link_test (online)" },
5277 bnx2_self_test_count(struct net_device *dev)
5279 return BNX2_NUM_TESTS;
5283 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5285 struct bnx2 *bp = netdev_priv(dev);
5287 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5288 if (etest->flags & ETH_TEST_FL_OFFLINE) {
5289 bnx2_netif_stop(bp);
5290 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5293 if (bnx2_test_registers(bp) != 0) {
5295 etest->flags |= ETH_TEST_FL_FAILED;
5297 if (bnx2_test_memory(bp) != 0) {
5299 etest->flags |= ETH_TEST_FL_FAILED;
5301 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
5302 etest->flags |= ETH_TEST_FL_FAILED;
5304 if (!netif_running(bp->dev)) {
5305 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5309 bnx2_netif_start(bp);
5312 /* wait for link up */
5313 msleep_interruptible(3000);
5314 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
5315 msleep_interruptible(4000);
5318 if (bnx2_test_nvram(bp) != 0) {
5320 etest->flags |= ETH_TEST_FL_FAILED;
5322 if (bnx2_test_intr(bp) != 0) {
5324 etest->flags |= ETH_TEST_FL_FAILED;
5327 if (bnx2_test_link(bp) != 0) {
5329 etest->flags |= ETH_TEST_FL_FAILED;
5335 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5337 switch (stringset) {
5339 memcpy(buf, bnx2_stats_str_arr,
5340 sizeof(bnx2_stats_str_arr));
5343 memcpy(buf, bnx2_tests_str_arr,
5344 sizeof(bnx2_tests_str_arr));
5350 bnx2_get_stats_count(struct net_device *dev)
5352 return BNX2_NUM_STATS;
5356 bnx2_get_ethtool_stats(struct net_device *dev,
5357 struct ethtool_stats *stats, u64 *buf)
5359 struct bnx2 *bp = netdev_priv(dev);
5361 u32 *hw_stats = (u32 *) bp->stats_blk;
5362 u8 *stats_len_arr = NULL;
5364 if (hw_stats == NULL) {
5365 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5369 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5370 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5371 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5372 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5373 stats_len_arr = bnx2_5706_stats_len_arr;
5375 stats_len_arr = bnx2_5708_stats_len_arr;
5377 for (i = 0; i < BNX2_NUM_STATS; i++) {
5378 if (stats_len_arr[i] == 0) {
5379 /* skip this counter */
5383 if (stats_len_arr[i] == 4) {
5384 /* 4-byte counter */
5386 *(hw_stats + bnx2_stats_offset_arr[i]);
5389 /* 8-byte counter */
5390 buf[i] = (((u64) *(hw_stats +
5391 bnx2_stats_offset_arr[i])) << 32) +
5392 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5397 bnx2_phys_id(struct net_device *dev, u32 data)
5399 struct bnx2 *bp = netdev_priv(dev);
5406 save = REG_RD(bp, BNX2_MISC_CFG);
5407 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5409 for (i = 0; i < (data * 2); i++) {
5411 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5414 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5415 BNX2_EMAC_LED_1000MB_OVERRIDE |
5416 BNX2_EMAC_LED_100MB_OVERRIDE |
5417 BNX2_EMAC_LED_10MB_OVERRIDE |
5418 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5419 BNX2_EMAC_LED_TRAFFIC);
5421 msleep_interruptible(500);
5422 if (signal_pending(current))
5425 REG_WR(bp, BNX2_EMAC_LED, 0);
5426 REG_WR(bp, BNX2_MISC_CFG, save);
5430 static struct ethtool_ops bnx2_ethtool_ops = {
5431 .get_settings = bnx2_get_settings,
5432 .set_settings = bnx2_set_settings,
5433 .get_drvinfo = bnx2_get_drvinfo,
5434 .get_regs_len = bnx2_get_regs_len,
5435 .get_regs = bnx2_get_regs,
5436 .get_wol = bnx2_get_wol,
5437 .set_wol = bnx2_set_wol,
5438 .nway_reset = bnx2_nway_reset,
5439 .get_link = ethtool_op_get_link,
5440 .get_eeprom_len = bnx2_get_eeprom_len,
5441 .get_eeprom = bnx2_get_eeprom,
5442 .set_eeprom = bnx2_set_eeprom,
5443 .get_coalesce = bnx2_get_coalesce,
5444 .set_coalesce = bnx2_set_coalesce,
5445 .get_ringparam = bnx2_get_ringparam,
5446 .set_ringparam = bnx2_set_ringparam,
5447 .get_pauseparam = bnx2_get_pauseparam,
5448 .set_pauseparam = bnx2_set_pauseparam,
5449 .get_rx_csum = bnx2_get_rx_csum,
5450 .set_rx_csum = bnx2_set_rx_csum,
5451 .get_tx_csum = ethtool_op_get_tx_csum,
5452 .set_tx_csum = ethtool_op_set_tx_csum,
5453 .get_sg = ethtool_op_get_sg,
5454 .set_sg = ethtool_op_set_sg,
5456 .get_tso = ethtool_op_get_tso,
5457 .set_tso = bnx2_set_tso,
5459 .self_test_count = bnx2_self_test_count,
5460 .self_test = bnx2_self_test,
5461 .get_strings = bnx2_get_strings,
5462 .phys_id = bnx2_phys_id,
5463 .get_stats_count = bnx2_get_stats_count,
5464 .get_ethtool_stats = bnx2_get_ethtool_stats,
5465 .get_perm_addr = ethtool_op_get_perm_addr,
5468 /* Called with rtnl_lock */
5470 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5472 struct mii_ioctl_data *data = if_mii(ifr);
5473 struct bnx2 *bp = netdev_priv(dev);
5478 data->phy_id = bp->phy_addr;
5484 spin_lock_bh(&bp->phy_lock);
5485 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5486 spin_unlock_bh(&bp->phy_lock);
5488 data->val_out = mii_regval;
5494 if (!capable(CAP_NET_ADMIN))
5497 spin_lock_bh(&bp->phy_lock);
5498 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5499 spin_unlock_bh(&bp->phy_lock);
5510 /* Called with rtnl_lock */
5512 bnx2_change_mac_addr(struct net_device *dev, void *p)
5514 struct sockaddr *addr = p;
5515 struct bnx2 *bp = netdev_priv(dev);
5517 if (!is_valid_ether_addr(addr->sa_data))
5520 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5521 if (netif_running(dev))
5522 bnx2_set_mac_addr(bp);
5527 /* Called with rtnl_lock */
5529 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5531 struct bnx2 *bp = netdev_priv(dev);
5533 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5534 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5538 if (netif_running(dev)) {
5539 bnx2_netif_stop(bp);
5543 bnx2_netif_start(bp);
5548 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5550 poll_bnx2(struct net_device *dev)
5552 struct bnx2 *bp = netdev_priv(dev);
5554 disable_irq(bp->pdev->irq);
5555 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5556 enable_irq(bp->pdev->irq);
5560 static int __devinit
5561 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5564 unsigned long mem_len;
5568 SET_MODULE_OWNER(dev);
5569 SET_NETDEV_DEV(dev, &pdev->dev);
5570 bp = netdev_priv(dev);
5575 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5576 rc = pci_enable_device(pdev);
5578 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.");
5582 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5584 "Cannot find PCI device base address, aborting.\n");
5586 goto err_out_disable;
5589 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5591 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
5592 goto err_out_disable;
5595 pci_set_master(pdev);
5597 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5598 if (bp->pm_cap == 0) {
5600 "Cannot find power management capability, aborting.\n");
5602 goto err_out_release;
5605 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5606 if (bp->pcix_cap == 0) {
5607 dev_err(&pdev->dev, "Cannot find PCIX capability, aborting.\n");
5609 goto err_out_release;
5612 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5613 bp->flags |= USING_DAC_FLAG;
5614 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5616 "pci_set_consistent_dma_mask failed, aborting.\n");
5618 goto err_out_release;
5621 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5622 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
5624 goto err_out_release;
5630 spin_lock_init(&bp->phy_lock);
5631 spin_lock_init(&bp->tx_lock);
5632 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5634 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5635 mem_len = MB_GET_CID_ADDR(17);
5636 dev->mem_end = dev->mem_start + mem_len;
5637 dev->irq = pdev->irq;
5639 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5642 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
5644 goto err_out_release;
5647 /* Configure byte swap and enable write to the reg_window registers.
5648 * Rely on CPU to do target byte swapping on big endian systems
5649 * The chip's target access swapping will not swap all accesses
5651 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5652 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5653 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5655 bnx2_set_power_state(bp, PCI_D0);
5657 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5659 /* Get bus information. */
5660 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5661 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5664 bp->flags |= PCIX_FLAG;
5666 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5668 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5670 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5671 bp->bus_speed_mhz = 133;
5674 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5675 bp->bus_speed_mhz = 100;
5678 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5679 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5680 bp->bus_speed_mhz = 66;
5683 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5684 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5685 bp->bus_speed_mhz = 50;
5688 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5689 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5690 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5691 bp->bus_speed_mhz = 33;
5696 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5697 bp->bus_speed_mhz = 66;
5699 bp->bus_speed_mhz = 33;
5702 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5703 bp->flags |= PCI_32BIT_FLAG;
5705 /* 5706A0 may falsely detect SERR and PERR. */
5706 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5707 reg = REG_RD(bp, PCI_COMMAND);
5708 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5709 REG_WR(bp, PCI_COMMAND, reg);
5711 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5712 !(bp->flags & PCIX_FLAG)) {
5715 "5706 A1 can only be used in a PCIX bus, aborting.\n");
5719 bnx2_init_nvram(bp);
5721 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5723 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5724 BNX2_SHM_HDR_SIGNATURE_SIG)
5725 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
5727 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5729 /* Get the permanent MAC address. First we need to make sure the
5730 * firmware is actually running.
5732 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5734 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5735 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5736 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
5741 bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5743 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5744 bp->mac_addr[0] = (u8) (reg >> 8);
5745 bp->mac_addr[1] = (u8) reg;
5747 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5748 bp->mac_addr[2] = (u8) (reg >> 24);
5749 bp->mac_addr[3] = (u8) (reg >> 16);
5750 bp->mac_addr[4] = (u8) (reg >> 8);
5751 bp->mac_addr[5] = (u8) reg;
5753 bp->tx_ring_size = MAX_TX_DESC_CNT;
5754 bnx2_set_rx_ring_size(bp, 100);
5758 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5760 bp->tx_quick_cons_trip_int = 20;
5761 bp->tx_quick_cons_trip = 20;
5762 bp->tx_ticks_int = 80;
5765 bp->rx_quick_cons_trip_int = 6;
5766 bp->rx_quick_cons_trip = 6;
5767 bp->rx_ticks_int = 18;
5770 bp->stats_ticks = 1000000 & 0xffff00;
5772 bp->timer_interval = HZ;
5773 bp->current_interval = HZ;
5777 /* Disable WOL support if we are running on a SERDES chip. */
5778 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5779 bp->phy_flags |= PHY_SERDES_FLAG;
5780 bp->flags |= NO_WOL_FLAG;
5781 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
5783 reg = REG_RD_IND(bp, bp->shmem_base +
5784 BNX2_SHARED_HW_CFG_CONFIG);
5785 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5786 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5790 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
5791 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5792 (CHIP_ID(bp) == CHIP_ID_5708_B1))
5793 bp->flags |= NO_WOL_FLAG;
5795 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5796 bp->tx_quick_cons_trip_int =
5797 bp->tx_quick_cons_trip;
5798 bp->tx_ticks_int = bp->tx_ticks;
5799 bp->rx_quick_cons_trip_int =
5800 bp->rx_quick_cons_trip;
5801 bp->rx_ticks_int = bp->rx_ticks;
5802 bp->comp_prod_trip_int = bp->comp_prod_trip;
5803 bp->com_ticks_int = bp->com_ticks;
5804 bp->cmd_ticks_int = bp->cmd_ticks;
5807 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5808 bp->req_line_speed = 0;
5809 if (bp->phy_flags & PHY_SERDES_FLAG) {
5810 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5812 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5813 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5814 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5816 bp->req_line_speed = bp->line_speed = SPEED_1000;
5817 bp->req_duplex = DUPLEX_FULL;
5821 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5824 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5826 init_timer(&bp->timer);
5827 bp->timer.expires = RUN_AT(bp->timer_interval);
5828 bp->timer.data = (unsigned long) bp;
5829 bp->timer.function = bnx2_timer;
5835 iounmap(bp->regview);
5840 pci_release_regions(pdev);
5843 pci_disable_device(pdev);
5844 pci_set_drvdata(pdev, NULL);
5850 static int __devinit
5851 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5853 static int version_printed = 0;
5854 struct net_device *dev = NULL;
5858 if (version_printed++ == 0)
5859 printk(KERN_INFO "%s", version);
5861 /* dev zeroed in init_etherdev */
5862 dev = alloc_etherdev(sizeof(*bp));
5867 rc = bnx2_init_board(pdev, dev);
5873 dev->open = bnx2_open;
5874 dev->hard_start_xmit = bnx2_start_xmit;
5875 dev->stop = bnx2_close;
5876 dev->get_stats = bnx2_get_stats;
5877 dev->set_multicast_list = bnx2_set_rx_mode;
5878 dev->do_ioctl = bnx2_ioctl;
5879 dev->set_mac_address = bnx2_change_mac_addr;
5880 dev->change_mtu = bnx2_change_mtu;
5881 dev->tx_timeout = bnx2_tx_timeout;
5882 dev->watchdog_timeo = TX_TIMEOUT;
5884 dev->vlan_rx_register = bnx2_vlan_rx_register;
5885 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5887 dev->poll = bnx2_poll;
5888 dev->ethtool_ops = &bnx2_ethtool_ops;
5891 bp = netdev_priv(dev);
5893 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5894 dev->poll_controller = poll_bnx2;
5897 if ((rc = register_netdev(dev))) {
5898 dev_err(&pdev->dev, "Cannot register net device\n");
5900 iounmap(bp->regview);
5901 pci_release_regions(pdev);
5902 pci_disable_device(pdev);
5903 pci_set_drvdata(pdev, NULL);
5908 pci_set_drvdata(pdev, dev);
5910 memcpy(dev->dev_addr, bp->mac_addr, 6);
5911 memcpy(dev->perm_addr, bp->mac_addr, 6);
5912 bp->name = board_info[ent->driver_data].name,
5913 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5917 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5918 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5919 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5920 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5925 printk("node addr ");
5926 for (i = 0; i < 6; i++)
5927 printk("%2.2x", dev->dev_addr[i]);
5930 dev->features |= NETIF_F_SG;
5931 if (bp->flags & USING_DAC_FLAG)
5932 dev->features |= NETIF_F_HIGHDMA;
5933 dev->features |= NETIF_F_IP_CSUM;
5935 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5938 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5941 netif_carrier_off(bp->dev);
5946 static void __devexit
5947 bnx2_remove_one(struct pci_dev *pdev)
5949 struct net_device *dev = pci_get_drvdata(pdev);
5950 struct bnx2 *bp = netdev_priv(dev);
5952 flush_scheduled_work();
5954 unregister_netdev(dev);
5957 iounmap(bp->regview);
5960 pci_release_regions(pdev);
5961 pci_disable_device(pdev);
5962 pci_set_drvdata(pdev, NULL);
5966 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5968 struct net_device *dev = pci_get_drvdata(pdev);
5969 struct bnx2 *bp = netdev_priv(dev);
5972 if (!netif_running(dev))
5975 flush_scheduled_work();
5976 bnx2_netif_stop(bp);
5977 netif_device_detach(dev);
5978 del_timer_sync(&bp->timer);
5979 if (bp->flags & NO_WOL_FLAG)
5980 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5982 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5984 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5985 bnx2_reset_chip(bp, reset_code);
5987 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5992 bnx2_resume(struct pci_dev *pdev)
5994 struct net_device *dev = pci_get_drvdata(pdev);
5995 struct bnx2 *bp = netdev_priv(dev);
5997 if (!netif_running(dev))
6000 bnx2_set_power_state(bp, PCI_D0);
6001 netif_device_attach(dev);
6003 bnx2_netif_start(bp);
6007 static struct pci_driver bnx2_pci_driver = {
6008 .name = DRV_MODULE_NAME,
6009 .id_table = bnx2_pci_tbl,
6010 .probe = bnx2_init_one,
6011 .remove = __devexit_p(bnx2_remove_one),
6012 .suspend = bnx2_suspend,
6013 .resume = bnx2_resume,
6016 static int __init bnx2_init(void)
6018 return pci_module_init(&bnx2_pci_driver);
6021 static void __exit bnx2_cleanup(void)
6023 pci_unregister_driver(&bnx2_pci_driver);
6026 module_init(bnx2_init);
6027 module_exit(bnx2_cleanup);