1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2010 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
17 #include <linux/kernel.h>
18 #include <linux/timer.h>
19 #include <linux/errno.h>
20 #include <linux/ioport.h>
21 #include <linux/slab.h>
22 #include <linux/vmalloc.h>
23 #include <linux/interrupt.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/netdevice.h>
27 #include <linux/etherdevice.h>
28 #include <linux/skbuff.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/bitops.h>
33 #include <linux/delay.h>
34 #include <asm/byteorder.h>
36 #include <linux/time.h>
37 #include <linux/ethtool.h>
38 #include <linux/mii.h>
39 #include <linux/if_vlan.h>
40 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
45 #include <net/checksum.h>
46 #include <linux/workqueue.h>
47 #include <linux/crc32.h>
48 #include <linux/prefetch.h>
49 #include <linux/cache.h>
50 #include <linux/firmware.h>
51 #include <linux/log2.h>
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
60 #define DRV_MODULE_NAME "bnx2"
61 #define DRV_MODULE_VERSION "2.0.15"
62 #define DRV_MODULE_RELDATE "May 4, 2010"
63 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j6.fw"
64 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
65 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j15.fw"
66 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
67 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
69 #define RUN_AT(x) (jiffies + (x))
71 /* Time in jiffies before concluding the transmitter is hung. */
72 #define TX_TIMEOUT (5*HZ)
74 static char version[] __devinitdata =
75 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
77 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
78 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
79 MODULE_LICENSE("GPL");
80 MODULE_VERSION(DRV_MODULE_VERSION);
81 MODULE_FIRMWARE(FW_MIPS_FILE_06);
82 MODULE_FIRMWARE(FW_RV2P_FILE_06);
83 MODULE_FIRMWARE(FW_MIPS_FILE_09);
84 MODULE_FIRMWARE(FW_RV2P_FILE_09);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
87 static int disable_msi = 0;
89 module_param(disable_msi, int, 0);
90 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
106 /* indexed by board_t, above */
109 } board_info[] __devinitdata = {
110 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
111 { "HP NC370T Multifunction Gigabit Server Adapter" },
112 { "HP NC370i Multifunction Gigabit Server Adapter" },
113 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
114 { "HP NC370F Multifunction Gigabit Server Adapter" },
115 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
117 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
119 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
123 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
125 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
126 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
127 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
128 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
130 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
132 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
133 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
134 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
136 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
138 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
140 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
142 { PCI_VENDOR_ID_BROADCOM, 0x163b,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
144 { PCI_VENDOR_ID_BROADCOM, 0x163c,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
149 static const struct flash_spec flash_table[] =
151 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
152 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
154 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
155 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
156 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
158 /* Expansion entry 0001 */
159 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
160 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
161 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
163 /* Saifun SA25F010 (non-buffered flash) */
164 /* strap, cfg1, & write1 need updates */
165 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
168 "Non-buffered flash (128kB)"},
169 /* Saifun SA25F020 (non-buffered flash) */
170 /* strap, cfg1, & write1 need updates */
171 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
172 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
173 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
174 "Non-buffered flash (256kB)"},
175 /* Expansion entry 0100 */
176 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
177 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
178 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
180 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
181 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
182 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
183 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
184 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
185 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
186 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
187 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
188 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
189 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
190 /* Saifun SA25F005 (non-buffered flash) */
191 /* strap, cfg1, & write1 need updates */
192 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
195 "Non-buffered flash (64kB)"},
197 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
198 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
199 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
201 /* Expansion entry 1001 */
202 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 /* Expansion entry 1010 */
207 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
211 /* ATMEL AT45DB011B (buffered flash) */
212 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
215 "Buffered flash (128kB)"},
216 /* Expansion entry 1100 */
217 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
218 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
219 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
221 /* Expansion entry 1101 */
222 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
223 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
224 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
226 /* Ateml Expansion entry 1110 */
227 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
228 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
229 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
230 "Entry 1110 (Atmel)"},
231 /* ATMEL AT45DB021B (buffered flash) */
232 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
233 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
234 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
235 "Buffered flash (256kB)"},
238 static const struct flash_spec flash_5709 = {
239 .flags = BNX2_NV_BUFFERED,
240 .page_bits = BCM5709_FLASH_PAGE_BITS,
241 .page_size = BCM5709_FLASH_PAGE_SIZE,
242 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
243 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
244 .name = "5709 Buffered flash (256kB)",
247 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
249 static void bnx2_init_napi(struct bnx2 *bp);
250 static void bnx2_del_napi(struct bnx2 *bp);
252 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
261 diff = txr->tx_prod - txr->tx_cons;
262 if (unlikely(diff >= TX_DESC_CNT)) {
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
267 return (bp->tx_ring_size - diff);
271 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
275 spin_lock_bh(&bp->indirect_lock);
276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
285 spin_lock_bh(&bp->indirect_lock);
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
288 spin_unlock_bh(&bp->indirect_lock);
292 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
298 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
300 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
304 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
307 spin_lock_bh(&bp->indirect_lock);
308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
324 spin_unlock_bh(&bp->indirect_lock);
329 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
350 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
377 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
389 bp->cnic_data = data;
390 rcu_assign_pointer(bp->cnic_ops, ops);
393 cp->drv_state = CNIC_DRV_STATE_REGD;
395 bnx2_setup_cnic_irq_info(bp);
400 static int bnx2_unregister_cnic(struct net_device *dev)
402 struct bnx2 *bp = netdev_priv(dev);
403 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
406 mutex_lock(&bp->cnic_lock);
408 bnapi->cnic_present = 0;
409 rcu_assign_pointer(bp->cnic_ops, NULL);
410 mutex_unlock(&bp->cnic_lock);
415 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
417 struct bnx2 *bp = netdev_priv(dev);
418 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
420 cp->drv_owner = THIS_MODULE;
421 cp->chip_id = bp->chip_id;
423 cp->io_base = bp->regview;
424 cp->drv_ctl = bnx2_drv_ctl;
425 cp->drv_register_cnic = bnx2_register_cnic;
426 cp->drv_unregister_cnic = bnx2_unregister_cnic;
430 EXPORT_SYMBOL(bnx2_cnic_probe);
433 bnx2_cnic_stop(struct bnx2 *bp)
435 struct cnic_ops *c_ops;
436 struct cnic_ctl_info info;
438 mutex_lock(&bp->cnic_lock);
439 c_ops = bp->cnic_ops;
441 info.cmd = CNIC_CTL_STOP_CMD;
442 c_ops->cnic_ctl(bp->cnic_data, &info);
444 mutex_unlock(&bp->cnic_lock);
448 bnx2_cnic_start(struct bnx2 *bp)
450 struct cnic_ops *c_ops;
451 struct cnic_ctl_info info;
453 mutex_lock(&bp->cnic_lock);
454 c_ops = bp->cnic_ops;
456 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
457 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
459 bnapi->cnic_tag = bnapi->last_status_idx;
461 info.cmd = CNIC_CTL_START_CMD;
462 c_ops->cnic_ctl(bp->cnic_data, &info);
464 mutex_unlock(&bp->cnic_lock);
470 bnx2_cnic_stop(struct bnx2 *bp)
475 bnx2_cnic_start(struct bnx2 *bp)
482 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
487 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
488 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
489 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
491 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
492 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
497 val1 = (bp->phy_addr << 21) | (reg << 16) |
498 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
499 BNX2_EMAC_MDIO_COMM_START_BUSY;
500 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
502 for (i = 0; i < 50; i++) {
505 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
506 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
509 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
510 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
516 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
525 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
526 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
527 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
529 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
530 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
539 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
544 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
545 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
546 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
548 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
549 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
554 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
555 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
556 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
557 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
559 for (i = 0; i < 50; i++) {
562 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
563 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
569 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
574 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
575 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
576 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
578 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
579 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
588 bnx2_disable_int(struct bnx2 *bp)
591 struct bnx2_napi *bnapi;
593 for (i = 0; i < bp->irq_nvecs; i++) {
594 bnapi = &bp->bnx2_napi[i];
595 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
596 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
598 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
602 bnx2_enable_int(struct bnx2 *bp)
605 struct bnx2_napi *bnapi;
607 for (i = 0; i < bp->irq_nvecs; i++) {
608 bnapi = &bp->bnx2_napi[i];
610 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
611 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
612 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
613 bnapi->last_status_idx);
615 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
616 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
617 bnapi->last_status_idx);
619 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
623 bnx2_disable_int_sync(struct bnx2 *bp)
627 atomic_inc(&bp->intr_sem);
628 if (!netif_running(bp->dev))
631 bnx2_disable_int(bp);
632 for (i = 0; i < bp->irq_nvecs; i++)
633 synchronize_irq(bp->irq_tbl[i].vector);
637 bnx2_napi_disable(struct bnx2 *bp)
641 for (i = 0; i < bp->irq_nvecs; i++)
642 napi_disable(&bp->bnx2_napi[i].napi);
646 bnx2_napi_enable(struct bnx2 *bp)
650 for (i = 0; i < bp->irq_nvecs; i++)
651 napi_enable(&bp->bnx2_napi[i].napi);
655 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
659 if (netif_running(bp->dev)) {
660 bnx2_napi_disable(bp);
661 netif_tx_disable(bp->dev);
663 bnx2_disable_int_sync(bp);
664 netif_carrier_off(bp->dev); /* prevent tx timeout */
668 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
670 if (atomic_dec_and_test(&bp->intr_sem)) {
671 if (netif_running(bp->dev)) {
672 netif_tx_wake_all_queues(bp->dev);
673 spin_lock_bh(&bp->phy_lock);
675 netif_carrier_on(bp->dev);
676 spin_unlock_bh(&bp->phy_lock);
677 bnx2_napi_enable(bp);
686 bnx2_free_tx_mem(struct bnx2 *bp)
690 for (i = 0; i < bp->num_tx_rings; i++) {
691 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
692 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
694 if (txr->tx_desc_ring) {
695 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
697 txr->tx_desc_mapping);
698 txr->tx_desc_ring = NULL;
700 kfree(txr->tx_buf_ring);
701 txr->tx_buf_ring = NULL;
706 bnx2_free_rx_mem(struct bnx2 *bp)
710 for (i = 0; i < bp->num_rx_rings; i++) {
711 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
712 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
715 for (j = 0; j < bp->rx_max_ring; j++) {
716 if (rxr->rx_desc_ring[j])
717 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
718 rxr->rx_desc_ring[j],
719 rxr->rx_desc_mapping[j]);
720 rxr->rx_desc_ring[j] = NULL;
722 vfree(rxr->rx_buf_ring);
723 rxr->rx_buf_ring = NULL;
725 for (j = 0; j < bp->rx_max_pg_ring; j++) {
726 if (rxr->rx_pg_desc_ring[j])
727 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
728 rxr->rx_pg_desc_ring[j],
729 rxr->rx_pg_desc_mapping[j]);
730 rxr->rx_pg_desc_ring[j] = NULL;
732 vfree(rxr->rx_pg_ring);
733 rxr->rx_pg_ring = NULL;
738 bnx2_alloc_tx_mem(struct bnx2 *bp)
742 for (i = 0; i < bp->num_tx_rings; i++) {
743 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
744 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
746 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
747 if (txr->tx_buf_ring == NULL)
751 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
752 &txr->tx_desc_mapping);
753 if (txr->tx_desc_ring == NULL)
760 bnx2_alloc_rx_mem(struct bnx2 *bp)
764 for (i = 0; i < bp->num_rx_rings; i++) {
765 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
766 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
770 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
771 if (rxr->rx_buf_ring == NULL)
774 memset(rxr->rx_buf_ring, 0,
775 SW_RXBD_RING_SIZE * bp->rx_max_ring);
777 for (j = 0; j < bp->rx_max_ring; j++) {
778 rxr->rx_desc_ring[j] =
779 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
780 &rxr->rx_desc_mapping[j]);
781 if (rxr->rx_desc_ring[j] == NULL)
786 if (bp->rx_pg_ring_size) {
787 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
789 if (rxr->rx_pg_ring == NULL)
792 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
796 for (j = 0; j < bp->rx_max_pg_ring; j++) {
797 rxr->rx_pg_desc_ring[j] =
798 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
799 &rxr->rx_pg_desc_mapping[j]);
800 if (rxr->rx_pg_desc_ring[j] == NULL)
809 bnx2_free_mem(struct bnx2 *bp)
812 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
814 bnx2_free_tx_mem(bp);
815 bnx2_free_rx_mem(bp);
817 for (i = 0; i < bp->ctx_pages; i++) {
818 if (bp->ctx_blk[i]) {
819 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
821 bp->ctx_blk_mapping[i]);
822 bp->ctx_blk[i] = NULL;
825 if (bnapi->status_blk.msi) {
826 pci_free_consistent(bp->pdev, bp->status_stats_size,
827 bnapi->status_blk.msi,
828 bp->status_blk_mapping);
829 bnapi->status_blk.msi = NULL;
830 bp->stats_blk = NULL;
835 bnx2_alloc_mem(struct bnx2 *bp)
837 int i, status_blk_size, err;
838 struct bnx2_napi *bnapi;
841 /* Combine status and statistics blocks into one allocation. */
842 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
843 if (bp->flags & BNX2_FLAG_MSIX_CAP)
844 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
845 BNX2_SBLK_MSIX_ALIGN_SIZE);
846 bp->status_stats_size = status_blk_size +
847 sizeof(struct statistics_block);
849 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
850 &bp->status_blk_mapping);
851 if (status_blk == NULL)
854 memset(status_blk, 0, bp->status_stats_size);
856 bnapi = &bp->bnx2_napi[0];
857 bnapi->status_blk.msi = status_blk;
858 bnapi->hw_tx_cons_ptr =
859 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
860 bnapi->hw_rx_cons_ptr =
861 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
862 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
863 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
864 struct status_block_msix *sblk;
866 bnapi = &bp->bnx2_napi[i];
868 sblk = (void *) (status_blk +
869 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
870 bnapi->status_blk.msix = sblk;
871 bnapi->hw_tx_cons_ptr =
872 &sblk->status_tx_quick_consumer_index;
873 bnapi->hw_rx_cons_ptr =
874 &sblk->status_rx_quick_consumer_index;
875 bnapi->int_num = i << 24;
879 bp->stats_blk = status_blk + status_blk_size;
881 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
883 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
884 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
885 if (bp->ctx_pages == 0)
887 for (i = 0; i < bp->ctx_pages; i++) {
888 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
890 &bp->ctx_blk_mapping[i]);
891 if (bp->ctx_blk[i] == NULL)
896 err = bnx2_alloc_rx_mem(bp);
900 err = bnx2_alloc_tx_mem(bp);
912 bnx2_report_fw_link(struct bnx2 *bp)
914 u32 fw_link_status = 0;
916 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
922 switch (bp->line_speed) {
924 if (bp->duplex == DUPLEX_HALF)
925 fw_link_status = BNX2_LINK_STATUS_10HALF;
927 fw_link_status = BNX2_LINK_STATUS_10FULL;
930 if (bp->duplex == DUPLEX_HALF)
931 fw_link_status = BNX2_LINK_STATUS_100HALF;
933 fw_link_status = BNX2_LINK_STATUS_100FULL;
936 if (bp->duplex == DUPLEX_HALF)
937 fw_link_status = BNX2_LINK_STATUS_1000HALF;
939 fw_link_status = BNX2_LINK_STATUS_1000FULL;
942 if (bp->duplex == DUPLEX_HALF)
943 fw_link_status = BNX2_LINK_STATUS_2500HALF;
945 fw_link_status = BNX2_LINK_STATUS_2500FULL;
949 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
952 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
954 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
955 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
957 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
958 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
959 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
961 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
965 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
967 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
971 bnx2_xceiver_str(struct bnx2 *bp)
973 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
974 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
979 bnx2_report_link(struct bnx2 *bp)
982 netif_carrier_on(bp->dev);
983 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
984 bnx2_xceiver_str(bp),
986 bp->duplex == DUPLEX_FULL ? "full" : "half");
989 if (bp->flow_ctrl & FLOW_CTRL_RX) {
990 pr_cont(", receive ");
991 if (bp->flow_ctrl & FLOW_CTRL_TX)
992 pr_cont("& transmit ");
995 pr_cont(", transmit ");
997 pr_cont("flow control ON");
1001 netif_carrier_off(bp->dev);
1002 netdev_err(bp->dev, "NIC %s Link is Down\n",
1003 bnx2_xceiver_str(bp));
1006 bnx2_report_fw_link(bp);
1010 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1012 u32 local_adv, remote_adv;
1015 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1016 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1018 if (bp->duplex == DUPLEX_FULL) {
1019 bp->flow_ctrl = bp->req_flow_ctrl;
1024 if (bp->duplex != DUPLEX_FULL) {
1028 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1029 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1032 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1033 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1034 bp->flow_ctrl |= FLOW_CTRL_TX;
1035 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1036 bp->flow_ctrl |= FLOW_CTRL_RX;
1040 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1041 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1043 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1044 u32 new_local_adv = 0;
1045 u32 new_remote_adv = 0;
1047 if (local_adv & ADVERTISE_1000XPAUSE)
1048 new_local_adv |= ADVERTISE_PAUSE_CAP;
1049 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1050 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1051 if (remote_adv & ADVERTISE_1000XPAUSE)
1052 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1053 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1054 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1056 local_adv = new_local_adv;
1057 remote_adv = new_remote_adv;
1060 /* See Table 28B-3 of 802.3ab-1999 spec. */
1061 if (local_adv & ADVERTISE_PAUSE_CAP) {
1062 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1063 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1064 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1066 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1067 bp->flow_ctrl = FLOW_CTRL_RX;
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1076 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1077 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1078 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1080 bp->flow_ctrl = FLOW_CTRL_TX;
1086 bnx2_5709s_linkup(struct bnx2 *bp)
1092 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1093 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1094 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1096 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1097 bp->line_speed = bp->req_line_speed;
1098 bp->duplex = bp->req_duplex;
1101 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1103 case MII_BNX2_GP_TOP_AN_SPEED_10:
1104 bp->line_speed = SPEED_10;
1106 case MII_BNX2_GP_TOP_AN_SPEED_100:
1107 bp->line_speed = SPEED_100;
1109 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1110 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1111 bp->line_speed = SPEED_1000;
1113 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1114 bp->line_speed = SPEED_2500;
1117 if (val & MII_BNX2_GP_TOP_AN_FD)
1118 bp->duplex = DUPLEX_FULL;
1120 bp->duplex = DUPLEX_HALF;
1125 bnx2_5708s_linkup(struct bnx2 *bp)
1130 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1131 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1132 case BCM5708S_1000X_STAT1_SPEED_10:
1133 bp->line_speed = SPEED_10;
1135 case BCM5708S_1000X_STAT1_SPEED_100:
1136 bp->line_speed = SPEED_100;
1138 case BCM5708S_1000X_STAT1_SPEED_1G:
1139 bp->line_speed = SPEED_1000;
1141 case BCM5708S_1000X_STAT1_SPEED_2G5:
1142 bp->line_speed = SPEED_2500;
1145 if (val & BCM5708S_1000X_STAT1_FD)
1146 bp->duplex = DUPLEX_FULL;
1148 bp->duplex = DUPLEX_HALF;
1154 bnx2_5706s_linkup(struct bnx2 *bp)
1156 u32 bmcr, local_adv, remote_adv, common;
1159 bp->line_speed = SPEED_1000;
1161 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1162 if (bmcr & BMCR_FULLDPLX) {
1163 bp->duplex = DUPLEX_FULL;
1166 bp->duplex = DUPLEX_HALF;
1169 if (!(bmcr & BMCR_ANENABLE)) {
1173 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1174 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1176 common = local_adv & remote_adv;
1177 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1179 if (common & ADVERTISE_1000XFULL) {
1180 bp->duplex = DUPLEX_FULL;
1183 bp->duplex = DUPLEX_HALF;
1191 bnx2_copper_linkup(struct bnx2 *bp)
1195 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1196 if (bmcr & BMCR_ANENABLE) {
1197 u32 local_adv, remote_adv, common;
1199 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1200 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1202 common = local_adv & (remote_adv >> 2);
1203 if (common & ADVERTISE_1000FULL) {
1204 bp->line_speed = SPEED_1000;
1205 bp->duplex = DUPLEX_FULL;
1207 else if (common & ADVERTISE_1000HALF) {
1208 bp->line_speed = SPEED_1000;
1209 bp->duplex = DUPLEX_HALF;
1212 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1213 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1215 common = local_adv & remote_adv;
1216 if (common & ADVERTISE_100FULL) {
1217 bp->line_speed = SPEED_100;
1218 bp->duplex = DUPLEX_FULL;
1220 else if (common & ADVERTISE_100HALF) {
1221 bp->line_speed = SPEED_100;
1222 bp->duplex = DUPLEX_HALF;
1224 else if (common & ADVERTISE_10FULL) {
1225 bp->line_speed = SPEED_10;
1226 bp->duplex = DUPLEX_FULL;
1228 else if (common & ADVERTISE_10HALF) {
1229 bp->line_speed = SPEED_10;
1230 bp->duplex = DUPLEX_HALF;
1239 if (bmcr & BMCR_SPEED100) {
1240 bp->line_speed = SPEED_100;
1243 bp->line_speed = SPEED_10;
1245 if (bmcr & BMCR_FULLDPLX) {
1246 bp->duplex = DUPLEX_FULL;
1249 bp->duplex = DUPLEX_HALF;
1257 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1259 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1261 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1262 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1265 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1266 u32 lo_water, hi_water;
1268 if (bp->flow_ctrl & FLOW_CTRL_TX)
1269 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1271 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1272 if (lo_water >= bp->rx_ring_size)
1275 hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
1277 if (hi_water <= lo_water)
1280 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1281 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1285 else if (hi_water == 0)
1287 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1289 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1293 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1298 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1301 bnx2_init_rx_context(bp, cid);
1306 bnx2_set_mac_link(struct bnx2 *bp)
1310 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1311 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1312 (bp->duplex == DUPLEX_HALF)) {
1313 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1316 /* Configure the EMAC mode register. */
1317 val = REG_RD(bp, BNX2_EMAC_MODE);
1319 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1320 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1321 BNX2_EMAC_MODE_25G_MODE);
1324 switch (bp->line_speed) {
1326 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1327 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1332 val |= BNX2_EMAC_MODE_PORT_MII;
1335 val |= BNX2_EMAC_MODE_25G_MODE;
1338 val |= BNX2_EMAC_MODE_PORT_GMII;
1343 val |= BNX2_EMAC_MODE_PORT_GMII;
1346 /* Set the MAC to operate in the appropriate duplex mode. */
1347 if (bp->duplex == DUPLEX_HALF)
1348 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1349 REG_WR(bp, BNX2_EMAC_MODE, val);
1351 /* Enable/disable rx PAUSE. */
1352 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1354 if (bp->flow_ctrl & FLOW_CTRL_RX)
1355 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1356 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1358 /* Enable/disable tx PAUSE. */
1359 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1360 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1362 if (bp->flow_ctrl & FLOW_CTRL_TX)
1363 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1364 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1366 /* Acknowledge the interrupt. */
1367 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1369 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1370 bnx2_init_all_rx_contexts(bp);
1374 bnx2_enable_bmsr1(struct bnx2 *bp)
1376 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1377 (CHIP_NUM(bp) == CHIP_NUM_5709))
1378 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1379 MII_BNX2_BLK_ADDR_GP_STATUS);
1383 bnx2_disable_bmsr1(struct bnx2 *bp)
1385 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1386 (CHIP_NUM(bp) == CHIP_NUM_5709))
1387 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1388 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1392 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1397 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1400 if (bp->autoneg & AUTONEG_SPEED)
1401 bp->advertising |= ADVERTISED_2500baseX_Full;
1403 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1404 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1406 bnx2_read_phy(bp, bp->mii_up1, &up1);
1407 if (!(up1 & BCM5708S_UP1_2G5)) {
1408 up1 |= BCM5708S_UP1_2G5;
1409 bnx2_write_phy(bp, bp->mii_up1, up1);
1413 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1414 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1415 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1421 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1426 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1429 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1430 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1432 bnx2_read_phy(bp, bp->mii_up1, &up1);
1433 if (up1 & BCM5708S_UP1_2G5) {
1434 up1 &= ~BCM5708S_UP1_2G5;
1435 bnx2_write_phy(bp, bp->mii_up1, up1);
1439 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1440 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1441 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1447 bnx2_enable_forced_2g5(struct bnx2 *bp)
1449 u32 uninitialized_var(bmcr);
1452 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1455 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1458 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1459 MII_BNX2_BLK_ADDR_SERDES_DIG);
1460 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1461 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1462 val |= MII_BNX2_SD_MISC1_FORCE |
1463 MII_BNX2_SD_MISC1_FORCE_2_5G;
1464 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1467 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1468 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1469 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1471 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1472 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1474 bmcr |= BCM5708S_BMCR_FORCE_2500;
1482 if (bp->autoneg & AUTONEG_SPEED) {
1483 bmcr &= ~BMCR_ANENABLE;
1484 if (bp->req_duplex == DUPLEX_FULL)
1485 bmcr |= BMCR_FULLDPLX;
1487 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1491 bnx2_disable_forced_2g5(struct bnx2 *bp)
1493 u32 uninitialized_var(bmcr);
1496 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1499 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1502 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1503 MII_BNX2_BLK_ADDR_SERDES_DIG);
1504 if (!bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val)) {
1505 val &= ~MII_BNX2_SD_MISC1_FORCE;
1506 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1509 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1510 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1511 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1513 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1514 err = bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1516 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1524 if (bp->autoneg & AUTONEG_SPEED)
1525 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1526 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1530 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1534 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1535 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1537 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1539 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1543 bnx2_set_link(struct bnx2 *bp)
1548 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1553 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1556 link_up = bp->link_up;
1558 bnx2_enable_bmsr1(bp);
1559 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1560 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1561 bnx2_disable_bmsr1(bp);
1563 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1564 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1567 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1568 bnx2_5706s_force_link_dn(bp, 0);
1569 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1571 val = REG_RD(bp, BNX2_EMAC_STATUS);
1573 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1574 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1575 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1577 if ((val & BNX2_EMAC_STATUS_LINK) &&
1578 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1579 bmsr |= BMSR_LSTATUS;
1581 bmsr &= ~BMSR_LSTATUS;
1584 if (bmsr & BMSR_LSTATUS) {
1587 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1588 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1589 bnx2_5706s_linkup(bp);
1590 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1591 bnx2_5708s_linkup(bp);
1592 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1593 bnx2_5709s_linkup(bp);
1596 bnx2_copper_linkup(bp);
1598 bnx2_resolve_flow_ctrl(bp);
1601 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1602 (bp->autoneg & AUTONEG_SPEED))
1603 bnx2_disable_forced_2g5(bp);
1605 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1608 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1609 bmcr |= BMCR_ANENABLE;
1610 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1612 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1617 if (bp->link_up != link_up) {
1618 bnx2_report_link(bp);
1621 bnx2_set_mac_link(bp);
1627 bnx2_reset_phy(struct bnx2 *bp)
1632 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1634 #define PHY_RESET_MAX_WAIT 100
1635 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1638 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1639 if (!(reg & BMCR_RESET)) {
1644 if (i == PHY_RESET_MAX_WAIT) {
1651 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1655 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1656 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1658 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1659 adv = ADVERTISE_1000XPAUSE;
1662 adv = ADVERTISE_PAUSE_CAP;
1665 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1666 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1667 adv = ADVERTISE_1000XPSE_ASYM;
1670 adv = ADVERTISE_PAUSE_ASYM;
1673 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1674 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1675 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1678 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1684 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1687 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1688 __releases(&bp->phy_lock)
1689 __acquires(&bp->phy_lock)
1691 u32 speed_arg = 0, pause_adv;
1693 pause_adv = bnx2_phy_get_pause_adv(bp);
1695 if (bp->autoneg & AUTONEG_SPEED) {
1696 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1697 if (bp->advertising & ADVERTISED_10baseT_Half)
1698 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1699 if (bp->advertising & ADVERTISED_10baseT_Full)
1700 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1701 if (bp->advertising & ADVERTISED_100baseT_Half)
1702 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1703 if (bp->advertising & ADVERTISED_100baseT_Full)
1704 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1705 if (bp->advertising & ADVERTISED_1000baseT_Full)
1706 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1707 if (bp->advertising & ADVERTISED_2500baseX_Full)
1708 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1710 if (bp->req_line_speed == SPEED_2500)
1711 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1712 else if (bp->req_line_speed == SPEED_1000)
1713 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1714 else if (bp->req_line_speed == SPEED_100) {
1715 if (bp->req_duplex == DUPLEX_FULL)
1716 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1718 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1719 } else if (bp->req_line_speed == SPEED_10) {
1720 if (bp->req_duplex == DUPLEX_FULL)
1721 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1723 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1727 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1728 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1729 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1730 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1732 if (port == PORT_TP)
1733 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1734 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1736 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1738 spin_unlock_bh(&bp->phy_lock);
1739 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1740 spin_lock_bh(&bp->phy_lock);
1746 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1747 __releases(&bp->phy_lock)
1748 __acquires(&bp->phy_lock)
1753 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1754 return (bnx2_setup_remote_phy(bp, port));
1756 if (!(bp->autoneg & AUTONEG_SPEED)) {
1758 int force_link_down = 0;
1760 if (bp->req_line_speed == SPEED_2500) {
1761 if (!bnx2_test_and_enable_2g5(bp))
1762 force_link_down = 1;
1763 } else if (bp->req_line_speed == SPEED_1000) {
1764 if (bnx2_test_and_disable_2g5(bp))
1765 force_link_down = 1;
1767 bnx2_read_phy(bp, bp->mii_adv, &adv);
1768 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1770 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1771 new_bmcr = bmcr & ~BMCR_ANENABLE;
1772 new_bmcr |= BMCR_SPEED1000;
1774 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1775 if (bp->req_line_speed == SPEED_2500)
1776 bnx2_enable_forced_2g5(bp);
1777 else if (bp->req_line_speed == SPEED_1000) {
1778 bnx2_disable_forced_2g5(bp);
1779 new_bmcr &= ~0x2000;
1782 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1783 if (bp->req_line_speed == SPEED_2500)
1784 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1786 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1789 if (bp->req_duplex == DUPLEX_FULL) {
1790 adv |= ADVERTISE_1000XFULL;
1791 new_bmcr |= BMCR_FULLDPLX;
1794 adv |= ADVERTISE_1000XHALF;
1795 new_bmcr &= ~BMCR_FULLDPLX;
1797 if ((new_bmcr != bmcr) || (force_link_down)) {
1798 /* Force a link down visible on the other side */
1800 bnx2_write_phy(bp, bp->mii_adv, adv &
1801 ~(ADVERTISE_1000XFULL |
1802 ADVERTISE_1000XHALF));
1803 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1804 BMCR_ANRESTART | BMCR_ANENABLE);
1807 netif_carrier_off(bp->dev);
1808 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1809 bnx2_report_link(bp);
1811 bnx2_write_phy(bp, bp->mii_adv, adv);
1812 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1814 bnx2_resolve_flow_ctrl(bp);
1815 bnx2_set_mac_link(bp);
1820 bnx2_test_and_enable_2g5(bp);
1822 if (bp->advertising & ADVERTISED_1000baseT_Full)
1823 new_adv |= ADVERTISE_1000XFULL;
1825 new_adv |= bnx2_phy_get_pause_adv(bp);
1827 bnx2_read_phy(bp, bp->mii_adv, &adv);
1828 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1830 bp->serdes_an_pending = 0;
1831 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1832 /* Force a link down visible on the other side */
1834 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1835 spin_unlock_bh(&bp->phy_lock);
1837 spin_lock_bh(&bp->phy_lock);
1840 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1841 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1843 /* Speed up link-up time when the link partner
1844 * does not autonegotiate which is very common
1845 * in blade servers. Some blade servers use
1846 * IPMI for kerboard input and it's important
1847 * to minimize link disruptions. Autoneg. involves
1848 * exchanging base pages plus 3 next pages and
1849 * normally completes in about 120 msec.
1851 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1852 bp->serdes_an_pending = 1;
1853 mod_timer(&bp->timer, jiffies + bp->current_interval);
1855 bnx2_resolve_flow_ctrl(bp);
1856 bnx2_set_mac_link(bp);
1862 #define ETHTOOL_ALL_FIBRE_SPEED \
1863 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1864 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1865 (ADVERTISED_1000baseT_Full)
1867 #define ETHTOOL_ALL_COPPER_SPEED \
1868 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1869 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1870 ADVERTISED_1000baseT_Full)
1872 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1873 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1875 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1878 bnx2_set_default_remote_link(struct bnx2 *bp)
1882 if (bp->phy_port == PORT_TP)
1883 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1885 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1887 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1888 bp->req_line_speed = 0;
1889 bp->autoneg |= AUTONEG_SPEED;
1890 bp->advertising = ADVERTISED_Autoneg;
1891 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1892 bp->advertising |= ADVERTISED_10baseT_Half;
1893 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1894 bp->advertising |= ADVERTISED_10baseT_Full;
1895 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1896 bp->advertising |= ADVERTISED_100baseT_Half;
1897 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1898 bp->advertising |= ADVERTISED_100baseT_Full;
1899 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1900 bp->advertising |= ADVERTISED_1000baseT_Full;
1901 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1902 bp->advertising |= ADVERTISED_2500baseX_Full;
1905 bp->advertising = 0;
1906 bp->req_duplex = DUPLEX_FULL;
1907 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1908 bp->req_line_speed = SPEED_10;
1909 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1910 bp->req_duplex = DUPLEX_HALF;
1912 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1913 bp->req_line_speed = SPEED_100;
1914 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1915 bp->req_duplex = DUPLEX_HALF;
1917 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1918 bp->req_line_speed = SPEED_1000;
1919 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1920 bp->req_line_speed = SPEED_2500;
1925 bnx2_set_default_link(struct bnx2 *bp)
1927 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1928 bnx2_set_default_remote_link(bp);
1932 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1933 bp->req_line_speed = 0;
1934 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1937 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1939 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1940 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1941 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1943 bp->req_line_speed = bp->line_speed = SPEED_1000;
1944 bp->req_duplex = DUPLEX_FULL;
1947 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1951 bnx2_send_heart_beat(struct bnx2 *bp)
1956 spin_lock(&bp->indirect_lock);
1957 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1958 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1959 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1960 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1961 spin_unlock(&bp->indirect_lock);
1965 bnx2_remote_phy_event(struct bnx2 *bp)
1968 u8 link_up = bp->link_up;
1971 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1973 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1974 bnx2_send_heart_beat(bp);
1976 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1978 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1984 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1985 bp->duplex = DUPLEX_FULL;
1987 case BNX2_LINK_STATUS_10HALF:
1988 bp->duplex = DUPLEX_HALF;
1989 case BNX2_LINK_STATUS_10FULL:
1990 bp->line_speed = SPEED_10;
1992 case BNX2_LINK_STATUS_100HALF:
1993 bp->duplex = DUPLEX_HALF;
1994 case BNX2_LINK_STATUS_100BASE_T4:
1995 case BNX2_LINK_STATUS_100FULL:
1996 bp->line_speed = SPEED_100;
1998 case BNX2_LINK_STATUS_1000HALF:
1999 bp->duplex = DUPLEX_HALF;
2000 case BNX2_LINK_STATUS_1000FULL:
2001 bp->line_speed = SPEED_1000;
2003 case BNX2_LINK_STATUS_2500HALF:
2004 bp->duplex = DUPLEX_HALF;
2005 case BNX2_LINK_STATUS_2500FULL:
2006 bp->line_speed = SPEED_2500;
2014 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2015 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2016 if (bp->duplex == DUPLEX_FULL)
2017 bp->flow_ctrl = bp->req_flow_ctrl;
2019 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2020 bp->flow_ctrl |= FLOW_CTRL_TX;
2021 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2022 bp->flow_ctrl |= FLOW_CTRL_RX;
2025 old_port = bp->phy_port;
2026 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2027 bp->phy_port = PORT_FIBRE;
2029 bp->phy_port = PORT_TP;
2031 if (old_port != bp->phy_port)
2032 bnx2_set_default_link(bp);
2035 if (bp->link_up != link_up)
2036 bnx2_report_link(bp);
2038 bnx2_set_mac_link(bp);
2042 bnx2_set_remote_link(struct bnx2 *bp)
2046 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2048 case BNX2_FW_EVT_CODE_LINK_EVENT:
2049 bnx2_remote_phy_event(bp);
2051 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2053 bnx2_send_heart_beat(bp);
2060 bnx2_setup_copper_phy(struct bnx2 *bp)
2061 __releases(&bp->phy_lock)
2062 __acquires(&bp->phy_lock)
2067 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2069 if (bp->autoneg & AUTONEG_SPEED) {
2070 u32 adv_reg, adv1000_reg;
2071 u32 new_adv_reg = 0;
2072 u32 new_adv1000_reg = 0;
2074 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2075 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2076 ADVERTISE_PAUSE_ASYM);
2078 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2079 adv1000_reg &= PHY_ALL_1000_SPEED;
2081 if (bp->advertising & ADVERTISED_10baseT_Half)
2082 new_adv_reg |= ADVERTISE_10HALF;
2083 if (bp->advertising & ADVERTISED_10baseT_Full)
2084 new_adv_reg |= ADVERTISE_10FULL;
2085 if (bp->advertising & ADVERTISED_100baseT_Half)
2086 new_adv_reg |= ADVERTISE_100HALF;
2087 if (bp->advertising & ADVERTISED_100baseT_Full)
2088 new_adv_reg |= ADVERTISE_100FULL;
2089 if (bp->advertising & ADVERTISED_1000baseT_Full)
2090 new_adv1000_reg |= ADVERTISE_1000FULL;
2092 new_adv_reg |= ADVERTISE_CSMA;
2094 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2096 if ((adv1000_reg != new_adv1000_reg) ||
2097 (adv_reg != new_adv_reg) ||
2098 ((bmcr & BMCR_ANENABLE) == 0)) {
2100 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2101 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2102 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2105 else if (bp->link_up) {
2106 /* Flow ctrl may have changed from auto to forced */
2107 /* or vice-versa. */
2109 bnx2_resolve_flow_ctrl(bp);
2110 bnx2_set_mac_link(bp);
2116 if (bp->req_line_speed == SPEED_100) {
2117 new_bmcr |= BMCR_SPEED100;
2119 if (bp->req_duplex == DUPLEX_FULL) {
2120 new_bmcr |= BMCR_FULLDPLX;
2122 if (new_bmcr != bmcr) {
2125 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2126 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2128 if (bmsr & BMSR_LSTATUS) {
2129 /* Force link down */
2130 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2131 spin_unlock_bh(&bp->phy_lock);
2133 spin_lock_bh(&bp->phy_lock);
2135 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2136 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2139 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2141 /* Normally, the new speed is setup after the link has
2142 * gone down and up again. In some cases, link will not go
2143 * down so we need to set up the new speed here.
2145 if (bmsr & BMSR_LSTATUS) {
2146 bp->line_speed = bp->req_line_speed;
2147 bp->duplex = bp->req_duplex;
2148 bnx2_resolve_flow_ctrl(bp);
2149 bnx2_set_mac_link(bp);
2152 bnx2_resolve_flow_ctrl(bp);
2153 bnx2_set_mac_link(bp);
2159 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2160 __releases(&bp->phy_lock)
2161 __acquires(&bp->phy_lock)
2163 if (bp->loopback == MAC_LOOPBACK)
2166 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2167 return (bnx2_setup_serdes_phy(bp, port));
2170 return (bnx2_setup_copper_phy(bp));
2175 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2179 bp->mii_bmcr = MII_BMCR + 0x10;
2180 bp->mii_bmsr = MII_BMSR + 0x10;
2181 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2182 bp->mii_adv = MII_ADVERTISE + 0x10;
2183 bp->mii_lpa = MII_LPA + 0x10;
2184 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2186 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2187 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2189 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2193 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2195 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2196 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2197 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2198 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2200 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2201 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2202 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2203 val |= BCM5708S_UP1_2G5;
2205 val &= ~BCM5708S_UP1_2G5;
2206 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2208 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2209 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2210 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2211 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2213 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2215 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2216 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2217 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2219 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2225 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2232 bp->mii_up1 = BCM5708S_UP1;
2234 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2235 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2236 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2238 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2239 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2240 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2242 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2243 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2244 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2246 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2247 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2248 val |= BCM5708S_UP1_2G5;
2249 bnx2_write_phy(bp, BCM5708S_UP1, val);
2252 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2253 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2254 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2255 /* increase tx signal amplitude */
2256 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2257 BCM5708S_BLK_ADDR_TX_MISC);
2258 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2259 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2260 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2261 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2264 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2265 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2270 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2271 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2272 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2273 BCM5708S_BLK_ADDR_TX_MISC);
2274 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2275 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2276 BCM5708S_BLK_ADDR_DIG);
2283 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2288 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2290 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2291 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2293 if (bp->dev->mtu > 1500) {
2296 /* Set extended packet length bit */
2297 bnx2_write_phy(bp, 0x18, 0x7);
2298 bnx2_read_phy(bp, 0x18, &val);
2299 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2301 bnx2_write_phy(bp, 0x1c, 0x6c00);
2302 bnx2_read_phy(bp, 0x1c, &val);
2303 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2308 bnx2_write_phy(bp, 0x18, 0x7);
2309 bnx2_read_phy(bp, 0x18, &val);
2310 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2312 bnx2_write_phy(bp, 0x1c, 0x6c00);
2313 bnx2_read_phy(bp, 0x1c, &val);
2314 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2321 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2328 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2329 bnx2_write_phy(bp, 0x18, 0x0c00);
2330 bnx2_write_phy(bp, 0x17, 0x000a);
2331 bnx2_write_phy(bp, 0x15, 0x310b);
2332 bnx2_write_phy(bp, 0x17, 0x201f);
2333 bnx2_write_phy(bp, 0x15, 0x9506);
2334 bnx2_write_phy(bp, 0x17, 0x401f);
2335 bnx2_write_phy(bp, 0x15, 0x14e2);
2336 bnx2_write_phy(bp, 0x18, 0x0400);
2339 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2340 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2341 MII_BNX2_DSP_EXPAND_REG | 0x8);
2342 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2344 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2347 if (bp->dev->mtu > 1500) {
2348 /* Set extended packet length bit */
2349 bnx2_write_phy(bp, 0x18, 0x7);
2350 bnx2_read_phy(bp, 0x18, &val);
2351 bnx2_write_phy(bp, 0x18, val | 0x4000);
2353 bnx2_read_phy(bp, 0x10, &val);
2354 bnx2_write_phy(bp, 0x10, val | 0x1);
2357 bnx2_write_phy(bp, 0x18, 0x7);
2358 bnx2_read_phy(bp, 0x18, &val);
2359 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2361 bnx2_read_phy(bp, 0x10, &val);
2362 bnx2_write_phy(bp, 0x10, val & ~0x1);
2365 /* ethernet@wirespeed */
2366 bnx2_write_phy(bp, 0x18, 0x7007);
2367 bnx2_read_phy(bp, 0x18, &val);
2368 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2374 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2375 __releases(&bp->phy_lock)
2376 __acquires(&bp->phy_lock)
2381 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2382 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2384 bp->mii_bmcr = MII_BMCR;
2385 bp->mii_bmsr = MII_BMSR;
2386 bp->mii_bmsr1 = MII_BMSR;
2387 bp->mii_adv = MII_ADVERTISE;
2388 bp->mii_lpa = MII_LPA;
2390 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2392 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2395 bnx2_read_phy(bp, MII_PHYSID1, &val);
2396 bp->phy_id = val << 16;
2397 bnx2_read_phy(bp, MII_PHYSID2, &val);
2398 bp->phy_id |= val & 0xffff;
2400 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2401 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2402 rc = bnx2_init_5706s_phy(bp, reset_phy);
2403 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2404 rc = bnx2_init_5708s_phy(bp, reset_phy);
2405 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2406 rc = bnx2_init_5709s_phy(bp, reset_phy);
2409 rc = bnx2_init_copper_phy(bp, reset_phy);
2414 rc = bnx2_setup_phy(bp, bp->phy_port);
2420 bnx2_set_mac_loopback(struct bnx2 *bp)
2424 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2425 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2426 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2427 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2432 static int bnx2_test_link(struct bnx2 *);
2435 bnx2_set_phy_loopback(struct bnx2 *bp)
2440 spin_lock_bh(&bp->phy_lock);
2441 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2443 spin_unlock_bh(&bp->phy_lock);
2447 for (i = 0; i < 10; i++) {
2448 if (bnx2_test_link(bp) == 0)
2453 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2454 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2455 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2456 BNX2_EMAC_MODE_25G_MODE);
2458 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2459 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2465 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2471 msg_data |= bp->fw_wr_seq;
2473 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2478 /* wait for an acknowledgement. */
2479 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2482 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2484 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2487 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2490 /* If we timed out, inform the firmware that this is the case. */
2491 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2493 pr_err("fw sync timeout, reset code = %x\n", msg_data);
2495 msg_data &= ~BNX2_DRV_MSG_CODE;
2496 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2498 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2503 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2510 bnx2_init_5709_context(struct bnx2 *bp)
2515 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2516 val |= (BCM_PAGE_BITS - 8) << 16;
2517 REG_WR(bp, BNX2_CTX_COMMAND, val);
2518 for (i = 0; i < 10; i++) {
2519 val = REG_RD(bp, BNX2_CTX_COMMAND);
2520 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2524 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2527 for (i = 0; i < bp->ctx_pages; i++) {
2531 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2535 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2536 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2537 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2538 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2539 (u64) bp->ctx_blk_mapping[i] >> 32);
2540 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2541 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2542 for (j = 0; j < 10; j++) {
2544 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2545 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2549 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2558 bnx2_init_context(struct bnx2 *bp)
2564 u32 vcid_addr, pcid_addr, offset;
2569 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2572 vcid_addr = GET_PCID_ADDR(vcid);
2574 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2579 pcid_addr = GET_PCID_ADDR(new_vcid);
2582 vcid_addr = GET_CID_ADDR(vcid);
2583 pcid_addr = vcid_addr;
2586 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2587 vcid_addr += (i << PHY_CTX_SHIFT);
2588 pcid_addr += (i << PHY_CTX_SHIFT);
2590 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2591 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2593 /* Zero out the context. */
2594 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2595 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2601 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2607 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2608 if (good_mbuf == NULL) {
2609 pr_err("Failed to allocate memory in %s\n", __func__);
2613 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2614 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2618 /* Allocate a bunch of mbufs and save the good ones in an array. */
2619 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2620 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2621 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2622 BNX2_RBUF_COMMAND_ALLOC_REQ);
2624 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2626 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2628 /* The addresses with Bit 9 set are bad memory blocks. */
2629 if (!(val & (1 << 9))) {
2630 good_mbuf[good_mbuf_cnt] = (u16) val;
2634 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2637 /* Free the good ones back to the mbuf pool thus discarding
2638 * all the bad ones. */
2639 while (good_mbuf_cnt) {
2642 val = good_mbuf[good_mbuf_cnt];
2643 val = (val << 9) | val | 1;
2645 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2652 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2656 val = (mac_addr[0] << 8) | mac_addr[1];
2658 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2660 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2661 (mac_addr[4] << 8) | mac_addr[5];
2663 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2667 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2670 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2671 struct rx_bd *rxbd =
2672 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2673 struct page *page = alloc_page(GFP_ATOMIC);
2677 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2678 PCI_DMA_FROMDEVICE);
2679 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2685 dma_unmap_addr_set(rx_pg, mapping, mapping);
2686 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2687 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2692 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2694 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2695 struct page *page = rx_pg->page;
2700 pci_unmap_page(bp->pdev, dma_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2701 PCI_DMA_FROMDEVICE);
2708 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2710 struct sk_buff *skb;
2711 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2713 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2714 unsigned long align;
2716 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2721 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2722 skb_reserve(skb, BNX2_RX_ALIGN - align);
2724 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2725 PCI_DMA_FROMDEVICE);
2726 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2732 rx_buf->desc = (struct l2_fhdr *) skb->data;
2733 dma_unmap_addr_set(rx_buf, mapping, mapping);
2735 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2736 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2738 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2744 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2746 struct status_block *sblk = bnapi->status_blk.msi;
2747 u32 new_link_state, old_link_state;
2750 new_link_state = sblk->status_attn_bits & event;
2751 old_link_state = sblk->status_attn_bits_ack & event;
2752 if (new_link_state != old_link_state) {
2754 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2756 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2764 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2766 spin_lock(&bp->phy_lock);
2768 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2770 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2771 bnx2_set_remote_link(bp);
2773 spin_unlock(&bp->phy_lock);
2778 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2782 /* Tell compiler that status block fields can change. */
2784 cons = *bnapi->hw_tx_cons_ptr;
2786 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2792 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2794 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2795 u16 hw_cons, sw_cons, sw_ring_cons;
2796 int tx_pkt = 0, index;
2797 struct netdev_queue *txq;
2799 index = (bnapi - bp->bnx2_napi);
2800 txq = netdev_get_tx_queue(bp->dev, index);
2802 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2803 sw_cons = txr->tx_cons;
2805 while (sw_cons != hw_cons) {
2806 struct sw_tx_bd *tx_buf;
2807 struct sk_buff *skb;
2810 sw_ring_cons = TX_RING_IDX(sw_cons);
2812 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2815 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2816 prefetch(&skb->end);
2818 /* partial BD completions possible with TSO packets */
2819 if (tx_buf->is_gso) {
2820 u16 last_idx, last_ring_idx;
2822 last_idx = sw_cons + tx_buf->nr_frags + 1;
2823 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2824 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2827 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2832 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
2833 skb_headlen(skb), PCI_DMA_TODEVICE);
2836 last = tx_buf->nr_frags;
2838 for (i = 0; i < last; i++) {
2839 sw_cons = NEXT_TX_BD(sw_cons);
2841 pci_unmap_page(bp->pdev,
2843 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2845 skb_shinfo(skb)->frags[i].size,
2849 sw_cons = NEXT_TX_BD(sw_cons);
2853 if (tx_pkt == budget)
2856 if (hw_cons == sw_cons)
2857 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2860 txr->hw_tx_cons = hw_cons;
2861 txr->tx_cons = sw_cons;
2863 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2864 * before checking for netif_tx_queue_stopped(). Without the
2865 * memory barrier, there is a small possibility that bnx2_start_xmit()
2866 * will miss it and cause the queue to be stopped forever.
2870 if (unlikely(netif_tx_queue_stopped(txq)) &&
2871 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2872 __netif_tx_lock(txq, smp_processor_id());
2873 if ((netif_tx_queue_stopped(txq)) &&
2874 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2875 netif_tx_wake_queue(txq);
2876 __netif_tx_unlock(txq);
2883 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2884 struct sk_buff *skb, int count)
2886 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2887 struct rx_bd *cons_bd, *prod_bd;
2890 u16 cons = rxr->rx_pg_cons;
2892 cons_rx_pg = &rxr->rx_pg_ring[cons];
2894 /* The caller was unable to allocate a new page to replace the
2895 * last one in the frags array, so we need to recycle that page
2896 * and then free the skb.
2900 struct skb_shared_info *shinfo;
2902 shinfo = skb_shinfo(skb);
2904 page = shinfo->frags[shinfo->nr_frags].page;
2905 shinfo->frags[shinfo->nr_frags].page = NULL;
2907 cons_rx_pg->page = page;
2911 hw_prod = rxr->rx_pg_prod;
2913 for (i = 0; i < count; i++) {
2914 prod = RX_PG_RING_IDX(hw_prod);
2916 prod_rx_pg = &rxr->rx_pg_ring[prod];
2917 cons_rx_pg = &rxr->rx_pg_ring[cons];
2918 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2919 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2922 prod_rx_pg->page = cons_rx_pg->page;
2923 cons_rx_pg->page = NULL;
2924 dma_unmap_addr_set(prod_rx_pg, mapping,
2925 dma_unmap_addr(cons_rx_pg, mapping));
2927 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2928 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2931 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2932 hw_prod = NEXT_RX_BD(hw_prod);
2934 rxr->rx_pg_prod = hw_prod;
2935 rxr->rx_pg_cons = cons;
2939 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2940 struct sk_buff *skb, u16 cons, u16 prod)
2942 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2943 struct rx_bd *cons_bd, *prod_bd;
2945 cons_rx_buf = &rxr->rx_buf_ring[cons];
2946 prod_rx_buf = &rxr->rx_buf_ring[prod];
2948 pci_dma_sync_single_for_device(bp->pdev,
2949 dma_unmap_addr(cons_rx_buf, mapping),
2950 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2952 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2954 prod_rx_buf->skb = skb;
2955 prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
2960 dma_unmap_addr_set(prod_rx_buf, mapping,
2961 dma_unmap_addr(cons_rx_buf, mapping));
2963 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2964 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2965 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2966 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2970 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2971 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2975 u16 prod = ring_idx & 0xffff;
2977 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2978 if (unlikely(err)) {
2979 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2981 unsigned int raw_len = len + 4;
2982 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2984 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2989 skb_reserve(skb, BNX2_RX_OFFSET);
2990 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2991 PCI_DMA_FROMDEVICE);
2997 unsigned int i, frag_len, frag_size, pages;
2998 struct sw_pg *rx_pg;
2999 u16 pg_cons = rxr->rx_pg_cons;
3000 u16 pg_prod = rxr->rx_pg_prod;
3002 frag_size = len + 4 - hdr_len;
3003 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
3004 skb_put(skb, hdr_len);
3006 for (i = 0; i < pages; i++) {
3007 dma_addr_t mapping_old;
3009 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3010 if (unlikely(frag_len <= 4)) {
3011 unsigned int tail = 4 - frag_len;
3013 rxr->rx_pg_cons = pg_cons;
3014 rxr->rx_pg_prod = pg_prod;
3015 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3022 &skb_shinfo(skb)->frags[i - 1];
3024 skb->data_len -= tail;
3025 skb->truesize -= tail;
3029 rx_pg = &rxr->rx_pg_ring[pg_cons];
3031 /* Don't unmap yet. If we're unable to allocate a new
3032 * page, we need to recycle the page and the DMA addr.
3034 mapping_old = dma_unmap_addr(rx_pg, mapping);
3038 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3041 err = bnx2_alloc_rx_page(bp, rxr,
3042 RX_PG_RING_IDX(pg_prod));
3043 if (unlikely(err)) {
3044 rxr->rx_pg_cons = pg_cons;
3045 rxr->rx_pg_prod = pg_prod;
3046 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3051 pci_unmap_page(bp->pdev, mapping_old,
3052 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3054 frag_size -= frag_len;
3055 skb->data_len += frag_len;
3056 skb->truesize += frag_len;
3057 skb->len += frag_len;
3059 pg_prod = NEXT_RX_BD(pg_prod);
3060 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3062 rxr->rx_pg_prod = pg_prod;
3063 rxr->rx_pg_cons = pg_cons;
3069 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3073 /* Tell compiler that status block fields can change. */
3075 cons = *bnapi->hw_rx_cons_ptr;
3077 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3083 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3085 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3086 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3087 struct l2_fhdr *rx_hdr;
3088 int rx_pkt = 0, pg_ring_used = 0;
3090 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3091 sw_cons = rxr->rx_cons;
3092 sw_prod = rxr->rx_prod;
3094 /* Memory barrier necessary as speculative reads of the rx
3095 * buffer can be ahead of the index in the status block
3098 while (sw_cons != hw_cons) {
3099 unsigned int len, hdr_len;
3101 struct sw_bd *rx_buf, *next_rx_buf;
3102 struct sk_buff *skb;
3103 dma_addr_t dma_addr;
3105 int hw_vlan __maybe_unused = 0;
3107 sw_ring_cons = RX_RING_IDX(sw_cons);
3108 sw_ring_prod = RX_RING_IDX(sw_prod);
3110 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3115 &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3116 prefetch(next_rx_buf->desc);
3120 dma_addr = dma_unmap_addr(rx_buf, mapping);
3122 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3123 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3124 PCI_DMA_FROMDEVICE);
3126 rx_hdr = rx_buf->desc;
3127 len = rx_hdr->l2_fhdr_pkt_len;
3128 status = rx_hdr->l2_fhdr_status;
3131 if (status & L2_FHDR_STATUS_SPLIT) {
3132 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3134 } else if (len > bp->rx_jumbo_thresh) {
3135 hdr_len = bp->rx_jumbo_thresh;
3139 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3140 L2_FHDR_ERRORS_PHY_DECODE |
3141 L2_FHDR_ERRORS_ALIGNMENT |
3142 L2_FHDR_ERRORS_TOO_SHORT |
3143 L2_FHDR_ERRORS_GIANT_FRAME))) {
3145 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3150 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3152 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3159 if (len <= bp->rx_copy_thresh) {
3160 struct sk_buff *new_skb;
3162 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3163 if (new_skb == NULL) {
3164 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3170 skb_copy_from_linear_data_offset(skb,
3172 new_skb->data, len + 6);
3173 skb_reserve(new_skb, 6);
3174 skb_put(new_skb, len);
3176 bnx2_reuse_rx_skb(bp, rxr, skb,
3177 sw_ring_cons, sw_ring_prod);
3180 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3181 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3184 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3185 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3186 vtag = rx_hdr->l2_fhdr_vlan_tag;
3193 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3196 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3197 ve->h_vlan_proto = htons(ETH_P_8021Q);
3198 ve->h_vlan_TCI = htons(vtag);
3203 skb->protocol = eth_type_trans(skb, bp->dev);
3205 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3206 (ntohs(skb->protocol) != 0x8100)) {
3213 skb->ip_summed = CHECKSUM_NONE;
3215 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3216 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3218 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3219 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3220 skb->ip_summed = CHECKSUM_UNNECESSARY;
3222 if ((bp->dev->features & NETIF_F_RXHASH) &&
3223 ((status & L2_FHDR_STATUS_USE_RXHASH) ==
3224 L2_FHDR_STATUS_USE_RXHASH))
3225 skb->rxhash = rx_hdr->l2_fhdr_hash;
3227 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3231 vlan_gro_receive(&bnapi->napi, bp->vlgrp, vtag, skb);
3234 napi_gro_receive(&bnapi->napi, skb);
3239 sw_cons = NEXT_RX_BD(sw_cons);
3240 sw_prod = NEXT_RX_BD(sw_prod);
3242 if ((rx_pkt == budget))
3245 /* Refresh hw_cons to see if there is new work */
3246 if (sw_cons == hw_cons) {
3247 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3251 rxr->rx_cons = sw_cons;
3252 rxr->rx_prod = sw_prod;
3255 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3257 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3259 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3267 /* MSI ISR - The only difference between this and the INTx ISR
3268 * is that the MSI interrupt is always serviced.
3271 bnx2_msi(int irq, void *dev_instance)
3273 struct bnx2_napi *bnapi = dev_instance;
3274 struct bnx2 *bp = bnapi->bp;
3276 prefetch(bnapi->status_blk.msi);
3277 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3278 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3279 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3281 /* Return here if interrupt is disabled. */
3282 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3285 napi_schedule(&bnapi->napi);
3291 bnx2_msi_1shot(int irq, void *dev_instance)
3293 struct bnx2_napi *bnapi = dev_instance;
3294 struct bnx2 *bp = bnapi->bp;
3296 prefetch(bnapi->status_blk.msi);
3298 /* Return here if interrupt is disabled. */
3299 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3302 napi_schedule(&bnapi->napi);
3308 bnx2_interrupt(int irq, void *dev_instance)
3310 struct bnx2_napi *bnapi = dev_instance;
3311 struct bnx2 *bp = bnapi->bp;
3312 struct status_block *sblk = bnapi->status_blk.msi;
3314 /* When using INTx, it is possible for the interrupt to arrive
3315 * at the CPU before the status block posted prior to the
3316 * interrupt. Reading a register will flush the status block.
3317 * When using MSI, the MSI message will always complete after
3318 * the status block write.
3320 if ((sblk->status_idx == bnapi->last_status_idx) &&
3321 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3322 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3325 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3326 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3327 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3329 /* Read back to deassert IRQ immediately to avoid too many
3330 * spurious interrupts.
3332 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3334 /* Return here if interrupt is shared and is disabled. */
3335 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3338 if (napi_schedule_prep(&bnapi->napi)) {
3339 bnapi->last_status_idx = sblk->status_idx;
3340 __napi_schedule(&bnapi->napi);
3347 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3349 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3350 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3352 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3353 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3358 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3359 STATUS_ATTN_BITS_TIMER_ABORT)
3362 bnx2_has_work(struct bnx2_napi *bnapi)
3364 struct status_block *sblk = bnapi->status_blk.msi;
3366 if (bnx2_has_fast_work(bnapi))
3370 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3374 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3375 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3382 bnx2_chk_missed_msi(struct bnx2 *bp)
3384 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3387 if (bnx2_has_work(bnapi)) {
3388 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3389 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3392 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3393 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3394 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3395 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3396 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3400 bp->idle_chk_status_idx = bnapi->last_status_idx;
3404 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3406 struct cnic_ops *c_ops;
3408 if (!bnapi->cnic_present)
3412 c_ops = rcu_dereference(bp->cnic_ops);
3414 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3415 bnapi->status_blk.msi);
3420 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3422 struct status_block *sblk = bnapi->status_blk.msi;
3423 u32 status_attn_bits = sblk->status_attn_bits;
3424 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3426 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3427 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3429 bnx2_phy_int(bp, bnapi);
3431 /* This is needed to take care of transient status
3432 * during link changes.
3434 REG_WR(bp, BNX2_HC_COMMAND,
3435 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3436 REG_RD(bp, BNX2_HC_COMMAND);
3440 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3441 int work_done, int budget)
3443 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3444 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3446 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3447 bnx2_tx_int(bp, bnapi, 0);
3449 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3450 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3455 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3457 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3458 struct bnx2 *bp = bnapi->bp;
3460 struct status_block_msix *sblk = bnapi->status_blk.msix;
3463 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3464 if (unlikely(work_done >= budget))
3467 bnapi->last_status_idx = sblk->status_idx;
3468 /* status idx must be read before checking for more work. */
3470 if (likely(!bnx2_has_fast_work(bnapi))) {
3472 napi_complete(napi);
3473 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3474 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3475 bnapi->last_status_idx);
3482 static int bnx2_poll(struct napi_struct *napi, int budget)
3484 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3485 struct bnx2 *bp = bnapi->bp;
3487 struct status_block *sblk = bnapi->status_blk.msi;
3490 bnx2_poll_link(bp, bnapi);
3492 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3495 bnx2_poll_cnic(bp, bnapi);
3498 /* bnapi->last_status_idx is used below to tell the hw how
3499 * much work has been processed, so we must read it before
3500 * checking for more work.
3502 bnapi->last_status_idx = sblk->status_idx;
3504 if (unlikely(work_done >= budget))
3508 if (likely(!bnx2_has_work(bnapi))) {
3509 napi_complete(napi);
3510 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3511 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3512 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3513 bnapi->last_status_idx);
3516 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3517 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3518 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3519 bnapi->last_status_idx);
3521 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3522 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3523 bnapi->last_status_idx);
3531 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3532 * from set_multicast.
3535 bnx2_set_rx_mode(struct net_device *dev)
3537 struct bnx2 *bp = netdev_priv(dev);
3538 u32 rx_mode, sort_mode;
3539 struct netdev_hw_addr *ha;
3542 if (!netif_running(dev))
3545 spin_lock_bh(&bp->phy_lock);
3547 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3548 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3549 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3551 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3552 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3554 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3555 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3557 if (dev->flags & IFF_PROMISC) {
3558 /* Promiscuous mode. */
3559 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3560 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3561 BNX2_RPM_SORT_USER0_PROM_VLAN;
3563 else if (dev->flags & IFF_ALLMULTI) {
3564 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3565 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3568 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3571 /* Accept one or more multicast(s). */
3572 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3577 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3579 netdev_for_each_mc_addr(ha, dev) {
3580 crc = ether_crc_le(ETH_ALEN, ha->addr);
3582 regidx = (bit & 0xe0) >> 5;
3584 mc_filter[regidx] |= (1 << bit);
3587 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3588 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3592 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3595 if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3596 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3597 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3598 BNX2_RPM_SORT_USER0_PROM_VLAN;
3599 } else if (!(dev->flags & IFF_PROMISC)) {
3600 /* Add all entries into to the match filter list */
3602 netdev_for_each_uc_addr(ha, dev) {
3603 bnx2_set_mac_addr(bp, ha->addr,
3604 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3606 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3612 if (rx_mode != bp->rx_mode) {
3613 bp->rx_mode = rx_mode;
3614 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3617 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3618 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3619 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3621 spin_unlock_bh(&bp->phy_lock);
3624 static int __devinit
3625 check_fw_section(const struct firmware *fw,
3626 const struct bnx2_fw_file_section *section,
3627 u32 alignment, bool non_empty)
3629 u32 offset = be32_to_cpu(section->offset);
3630 u32 len = be32_to_cpu(section->len);
3632 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3634 if ((non_empty && len == 0) || len > fw->size - offset ||
3635 len & (alignment - 1))
3640 static int __devinit
3641 check_mips_fw_entry(const struct firmware *fw,
3642 const struct bnx2_mips_fw_file_entry *entry)
3644 if (check_fw_section(fw, &entry->text, 4, true) ||
3645 check_fw_section(fw, &entry->data, 4, false) ||
3646 check_fw_section(fw, &entry->rodata, 4, false))
3651 static int __devinit
3652 bnx2_request_firmware(struct bnx2 *bp)
3654 const char *mips_fw_file, *rv2p_fw_file;
3655 const struct bnx2_mips_fw_file *mips_fw;
3656 const struct bnx2_rv2p_fw_file *rv2p_fw;
3659 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3660 mips_fw_file = FW_MIPS_FILE_09;
3661 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3662 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3663 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3665 rv2p_fw_file = FW_RV2P_FILE_09;
3667 mips_fw_file = FW_MIPS_FILE_06;
3668 rv2p_fw_file = FW_RV2P_FILE_06;
3671 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3673 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3677 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3679 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3682 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3683 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3684 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3685 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3686 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3687 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3688 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3689 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3690 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3693 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3694 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3695 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3696 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3704 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3707 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3708 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3709 rv2p_code |= RV2P_BD_PAGE_SIZE;
3716 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3717 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3719 u32 rv2p_code_len, file_offset;
3724 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3725 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3727 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3729 if (rv2p_proc == RV2P_PROC1) {
3730 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3731 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3733 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3734 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3737 for (i = 0; i < rv2p_code_len; i += 8) {
3738 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3740 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3743 val = (i / 8) | cmd;
3744 REG_WR(bp, addr, val);
3747 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3748 for (i = 0; i < 8; i++) {
3751 loc = be32_to_cpu(fw_entry->fixup[i]);
3752 if (loc && ((loc * 4) < rv2p_code_len)) {
3753 code = be32_to_cpu(*(rv2p_code + loc - 1));
3754 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3755 code = be32_to_cpu(*(rv2p_code + loc));
3756 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3757 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3759 val = (loc / 2) | cmd;
3760 REG_WR(bp, addr, val);
3764 /* Reset the processor, un-stall is done later. */
3765 if (rv2p_proc == RV2P_PROC1) {
3766 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3769 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3776 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3777 const struct bnx2_mips_fw_file_entry *fw_entry)
3779 u32 addr, len, file_offset;
3785 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3786 val |= cpu_reg->mode_value_halt;
3787 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3788 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3790 /* Load the Text area. */
3791 addr = be32_to_cpu(fw_entry->text.addr);
3792 len = be32_to_cpu(fw_entry->text.len);
3793 file_offset = be32_to_cpu(fw_entry->text.offset);
3794 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3796 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3800 for (j = 0; j < (len / 4); j++, offset += 4)
3801 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3804 /* Load the Data area. */
3805 addr = be32_to_cpu(fw_entry->data.addr);
3806 len = be32_to_cpu(fw_entry->data.len);
3807 file_offset = be32_to_cpu(fw_entry->data.offset);
3808 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3810 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3814 for (j = 0; j < (len / 4); j++, offset += 4)
3815 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3818 /* Load the Read-Only area. */
3819 addr = be32_to_cpu(fw_entry->rodata.addr);
3820 len = be32_to_cpu(fw_entry->rodata.len);
3821 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3822 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3824 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3828 for (j = 0; j < (len / 4); j++, offset += 4)
3829 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3832 /* Clear the pre-fetch instruction. */
3833 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3835 val = be32_to_cpu(fw_entry->start_addr);
3836 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3838 /* Start the CPU. */
3839 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3840 val &= ~cpu_reg->mode_value_halt;
3841 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3842 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3848 bnx2_init_cpus(struct bnx2 *bp)
3850 const struct bnx2_mips_fw_file *mips_fw =
3851 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3852 const struct bnx2_rv2p_fw_file *rv2p_fw =
3853 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3856 /* Initialize the RV2P processor. */
3857 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3858 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3860 /* Initialize the RX Processor. */
3861 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3865 /* Initialize the TX Processor. */
3866 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3870 /* Initialize the TX Patch-up Processor. */
3871 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3875 /* Initialize the Completion Processor. */
3876 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3880 /* Initialize the Command Processor. */
3881 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3888 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3892 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3898 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3899 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3900 PCI_PM_CTRL_PME_STATUS);
3902 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3903 /* delay required during transition out of D3hot */
3906 val = REG_RD(bp, BNX2_EMAC_MODE);
3907 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3908 val &= ~BNX2_EMAC_MODE_MPKT;
3909 REG_WR(bp, BNX2_EMAC_MODE, val);
3911 val = REG_RD(bp, BNX2_RPM_CONFIG);
3912 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3913 REG_WR(bp, BNX2_RPM_CONFIG, val);
3924 autoneg = bp->autoneg;
3925 advertising = bp->advertising;
3927 if (bp->phy_port == PORT_TP) {
3928 bp->autoneg = AUTONEG_SPEED;
3929 bp->advertising = ADVERTISED_10baseT_Half |
3930 ADVERTISED_10baseT_Full |
3931 ADVERTISED_100baseT_Half |
3932 ADVERTISED_100baseT_Full |
3936 spin_lock_bh(&bp->phy_lock);
3937 bnx2_setup_phy(bp, bp->phy_port);
3938 spin_unlock_bh(&bp->phy_lock);
3940 bp->autoneg = autoneg;
3941 bp->advertising = advertising;
3943 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3945 val = REG_RD(bp, BNX2_EMAC_MODE);
3947 /* Enable port mode. */
3948 val &= ~BNX2_EMAC_MODE_PORT;
3949 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3950 BNX2_EMAC_MODE_ACPI_RCVD |
3951 BNX2_EMAC_MODE_MPKT;
3952 if (bp->phy_port == PORT_TP)
3953 val |= BNX2_EMAC_MODE_PORT_MII;
3955 val |= BNX2_EMAC_MODE_PORT_GMII;
3956 if (bp->line_speed == SPEED_2500)
3957 val |= BNX2_EMAC_MODE_25G_MODE;
3960 REG_WR(bp, BNX2_EMAC_MODE, val);
3962 /* receive all multicast */
3963 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3964 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3967 REG_WR(bp, BNX2_EMAC_RX_MODE,
3968 BNX2_EMAC_RX_MODE_SORT_MODE);
3970 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3971 BNX2_RPM_SORT_USER0_MC_EN;
3972 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3973 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3974 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3975 BNX2_RPM_SORT_USER0_ENA);
3977 /* Need to enable EMAC and RPM for WOL. */
3978 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3979 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3980 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3981 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3983 val = REG_RD(bp, BNX2_RPM_CONFIG);
3984 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3985 REG_WR(bp, BNX2_RPM_CONFIG, val);
3987 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3990 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3993 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3994 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3997 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3998 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3999 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
4008 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4010 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4013 /* No more memory access after this point until
4014 * device is brought back to D0.
4026 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4031 /* Request access to the flash interface. */
4032 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4033 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4034 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4035 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4041 if (j >= NVRAM_TIMEOUT_COUNT)
4048 bnx2_release_nvram_lock(struct bnx2 *bp)
4053 /* Relinquish nvram interface. */
4054 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4056 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4057 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4058 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4064 if (j >= NVRAM_TIMEOUT_COUNT)
4072 bnx2_enable_nvram_write(struct bnx2 *bp)
4076 val = REG_RD(bp, BNX2_MISC_CFG);
4077 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4079 if (bp->flash_info->flags & BNX2_NV_WREN) {
4082 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4083 REG_WR(bp, BNX2_NVM_COMMAND,
4084 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4086 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4089 val = REG_RD(bp, BNX2_NVM_COMMAND);
4090 if (val & BNX2_NVM_COMMAND_DONE)
4094 if (j >= NVRAM_TIMEOUT_COUNT)
4101 bnx2_disable_nvram_write(struct bnx2 *bp)
4105 val = REG_RD(bp, BNX2_MISC_CFG);
4106 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4111 bnx2_enable_nvram_access(struct bnx2 *bp)
4115 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4116 /* Enable both bits, even on read. */
4117 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4118 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4122 bnx2_disable_nvram_access(struct bnx2 *bp)
4126 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4127 /* Disable both bits, even after read. */
4128 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4129 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4130 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4134 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4139 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4140 /* Buffered flash, no erase needed */
4143 /* Build an erase command */
4144 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4145 BNX2_NVM_COMMAND_DOIT;
4147 /* Need to clear DONE bit separately. */
4148 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4150 /* Address of the NVRAM to read from. */
4151 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4153 /* Issue an erase command. */
4154 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4156 /* Wait for completion. */
4157 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4162 val = REG_RD(bp, BNX2_NVM_COMMAND);
4163 if (val & BNX2_NVM_COMMAND_DONE)
4167 if (j >= NVRAM_TIMEOUT_COUNT)
4174 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4179 /* Build the command word. */
4180 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4182 /* Calculate an offset of a buffered flash, not needed for 5709. */
4183 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4184 offset = ((offset / bp->flash_info->page_size) <<
4185 bp->flash_info->page_bits) +
4186 (offset % bp->flash_info->page_size);
4189 /* Need to clear DONE bit separately. */
4190 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4192 /* Address of the NVRAM to read from. */
4193 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4195 /* Issue a read command. */
4196 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4198 /* Wait for completion. */
4199 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4204 val = REG_RD(bp, BNX2_NVM_COMMAND);
4205 if (val & BNX2_NVM_COMMAND_DONE) {
4206 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4207 memcpy(ret_val, &v, 4);
4211 if (j >= NVRAM_TIMEOUT_COUNT)
4219 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4225 /* Build the command word. */
4226 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4228 /* Calculate an offset of a buffered flash, not needed for 5709. */
4229 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4230 offset = ((offset / bp->flash_info->page_size) <<
4231 bp->flash_info->page_bits) +
4232 (offset % bp->flash_info->page_size);
4235 /* Need to clear DONE bit separately. */
4236 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4238 memcpy(&val32, val, 4);
4240 /* Write the data. */
4241 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4243 /* Address of the NVRAM to write to. */
4244 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4246 /* Issue the write command. */
4247 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4249 /* Wait for completion. */
4250 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4253 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4256 if (j >= NVRAM_TIMEOUT_COUNT)
4263 bnx2_init_nvram(struct bnx2 *bp)
4266 int j, entry_count, rc = 0;
4267 const struct flash_spec *flash;
4269 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4270 bp->flash_info = &flash_5709;
4271 goto get_flash_size;
4274 /* Determine the selected interface. */
4275 val = REG_RD(bp, BNX2_NVM_CFG1);
4277 entry_count = ARRAY_SIZE(flash_table);
4279 if (val & 0x40000000) {
4281 /* Flash interface has been reconfigured */
4282 for (j = 0, flash = &flash_table[0]; j < entry_count;
4284 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4285 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4286 bp->flash_info = flash;
4293 /* Not yet been reconfigured */
4295 if (val & (1 << 23))
4296 mask = FLASH_BACKUP_STRAP_MASK;
4298 mask = FLASH_STRAP_MASK;
4300 for (j = 0, flash = &flash_table[0]; j < entry_count;
4303 if ((val & mask) == (flash->strapping & mask)) {
4304 bp->flash_info = flash;
4306 /* Request access to the flash interface. */
4307 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4310 /* Enable access to flash interface */
4311 bnx2_enable_nvram_access(bp);
4313 /* Reconfigure the flash interface */
4314 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4315 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4316 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4317 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4319 /* Disable access to flash interface */
4320 bnx2_disable_nvram_access(bp);
4321 bnx2_release_nvram_lock(bp);
4326 } /* if (val & 0x40000000) */
4328 if (j == entry_count) {
4329 bp->flash_info = NULL;
4330 pr_alert("Unknown flash/EEPROM type\n");
4335 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4336 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4338 bp->flash_size = val;
4340 bp->flash_size = bp->flash_info->total_size;
4346 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4350 u32 cmd_flags, offset32, len32, extra;
4355 /* Request access to the flash interface. */
4356 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4359 /* Enable access to flash interface */
4360 bnx2_enable_nvram_access(bp);
4373 pre_len = 4 - (offset & 3);
4375 if (pre_len >= len32) {
4377 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4378 BNX2_NVM_COMMAND_LAST;
4381 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4384 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4389 memcpy(ret_buf, buf + (offset & 3), pre_len);
4396 extra = 4 - (len32 & 3);
4397 len32 = (len32 + 4) & ~3;
4404 cmd_flags = BNX2_NVM_COMMAND_LAST;
4406 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4407 BNX2_NVM_COMMAND_LAST;
4409 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4411 memcpy(ret_buf, buf, 4 - extra);
4413 else if (len32 > 0) {
4416 /* Read the first word. */
4420 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4422 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4424 /* Advance to the next dword. */
4429 while (len32 > 4 && rc == 0) {
4430 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4432 /* Advance to the next dword. */
4441 cmd_flags = BNX2_NVM_COMMAND_LAST;
4442 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4444 memcpy(ret_buf, buf, 4 - extra);
4447 /* Disable access to flash interface */
4448 bnx2_disable_nvram_access(bp);
4450 bnx2_release_nvram_lock(bp);
4456 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4459 u32 written, offset32, len32;
4460 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4462 int align_start, align_end;
4467 align_start = align_end = 0;
4469 if ((align_start = (offset32 & 3))) {
4471 len32 += align_start;
4474 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4479 align_end = 4 - (len32 & 3);
4481 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4485 if (align_start || align_end) {
4486 align_buf = kmalloc(len32, GFP_KERNEL);
4487 if (align_buf == NULL)
4490 memcpy(align_buf, start, 4);
4493 memcpy(align_buf + len32 - 4, end, 4);
4495 memcpy(align_buf + align_start, data_buf, buf_size);
4499 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4500 flash_buffer = kmalloc(264, GFP_KERNEL);
4501 if (flash_buffer == NULL) {
4503 goto nvram_write_end;
4508 while ((written < len32) && (rc == 0)) {
4509 u32 page_start, page_end, data_start, data_end;
4510 u32 addr, cmd_flags;
4513 /* Find the page_start addr */
4514 page_start = offset32 + written;
4515 page_start -= (page_start % bp->flash_info->page_size);
4516 /* Find the page_end addr */
4517 page_end = page_start + bp->flash_info->page_size;
4518 /* Find the data_start addr */
4519 data_start = (written == 0) ? offset32 : page_start;
4520 /* Find the data_end addr */
4521 data_end = (page_end > offset32 + len32) ?
4522 (offset32 + len32) : page_end;
4524 /* Request access to the flash interface. */
4525 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4526 goto nvram_write_end;
4528 /* Enable access to flash interface */
4529 bnx2_enable_nvram_access(bp);
4531 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4532 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4535 /* Read the whole page into the buffer
4536 * (non-buffer flash only) */
4537 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4538 if (j == (bp->flash_info->page_size - 4)) {
4539 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4541 rc = bnx2_nvram_read_dword(bp,
4547 goto nvram_write_end;
4553 /* Enable writes to flash interface (unlock write-protect) */
4554 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4555 goto nvram_write_end;
4557 /* Loop to write back the buffer data from page_start to
4560 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4561 /* Erase the page */
4562 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4563 goto nvram_write_end;
4565 /* Re-enable the write again for the actual write */
4566 bnx2_enable_nvram_write(bp);
4568 for (addr = page_start; addr < data_start;
4569 addr += 4, i += 4) {
4571 rc = bnx2_nvram_write_dword(bp, addr,
4572 &flash_buffer[i], cmd_flags);
4575 goto nvram_write_end;
4581 /* Loop to write the new data from data_start to data_end */
4582 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4583 if ((addr == page_end - 4) ||
4584 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4585 (addr == data_end - 4))) {
4587 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4589 rc = bnx2_nvram_write_dword(bp, addr, buf,
4593 goto nvram_write_end;
4599 /* Loop to write back the buffer data from data_end
4601 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4602 for (addr = data_end; addr < page_end;
4603 addr += 4, i += 4) {
4605 if (addr == page_end-4) {
4606 cmd_flags = BNX2_NVM_COMMAND_LAST;
4608 rc = bnx2_nvram_write_dword(bp, addr,
4609 &flash_buffer[i], cmd_flags);
4612 goto nvram_write_end;
4618 /* Disable writes to flash interface (lock write-protect) */
4619 bnx2_disable_nvram_write(bp);
4621 /* Disable access to flash interface */
4622 bnx2_disable_nvram_access(bp);
4623 bnx2_release_nvram_lock(bp);
4625 /* Increment written */
4626 written += data_end - data_start;
4630 kfree(flash_buffer);
4636 bnx2_init_fw_cap(struct bnx2 *bp)
4640 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4641 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4643 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4644 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4646 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4647 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4650 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4651 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4652 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4655 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4656 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4659 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4661 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4662 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4663 bp->phy_port = PORT_FIBRE;
4665 bp->phy_port = PORT_TP;
4667 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4668 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4671 if (netif_running(bp->dev) && sig)
4672 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4676 bnx2_setup_msix_tbl(struct bnx2 *bp)
4678 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4680 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4681 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4685 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4691 /* Wait for the current PCI transaction to complete before
4692 * issuing a reset. */
4693 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4694 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4695 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4696 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4697 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4698 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4701 /* Wait for the firmware to tell us it is ok to issue a reset. */
4702 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4704 /* Deposit a driver reset signature so the firmware knows that
4705 * this is a soft reset. */
4706 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4707 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4709 /* Do a dummy read to force the chip to complete all current transaction
4710 * before we issue a reset. */
4711 val = REG_RD(bp, BNX2_MISC_ID);
4713 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4714 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4715 REG_RD(bp, BNX2_MISC_COMMAND);
4718 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4719 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4721 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4724 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4725 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4726 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4729 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4731 /* Reading back any register after chip reset will hang the
4732 * bus on 5706 A0 and A1. The msleep below provides plenty
4733 * of margin for write posting.
4735 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4736 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4739 /* Reset takes approximate 30 usec */
4740 for (i = 0; i < 10; i++) {
4741 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4742 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4743 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4748 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4749 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4750 pr_err("Chip reset did not complete\n");
4755 /* Make sure byte swapping is properly configured. */
4756 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4757 if (val != 0x01020304) {
4758 pr_err("Chip not in correct endian mode\n");
4762 /* Wait for the firmware to finish its initialization. */
4763 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4767 spin_lock_bh(&bp->phy_lock);
4768 old_port = bp->phy_port;
4769 bnx2_init_fw_cap(bp);
4770 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4771 old_port != bp->phy_port)
4772 bnx2_set_default_remote_link(bp);
4773 spin_unlock_bh(&bp->phy_lock);
4775 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4776 /* Adjust the voltage regular to two steps lower. The default
4777 * of this register is 0x0000000e. */
4778 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4780 /* Remove bad rbuf memory from the free pool. */
4781 rc = bnx2_alloc_bad_rbuf(bp);
4784 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4785 bnx2_setup_msix_tbl(bp);
4786 /* Prevent MSIX table reads and write from timing out */
4787 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4788 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4795 bnx2_init_chip(struct bnx2 *bp)
4800 /* Make sure the interrupt is not active. */
4801 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4803 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4804 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4806 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4808 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4809 DMA_READ_CHANS << 12 |
4810 DMA_WRITE_CHANS << 16;
4812 val |= (0x2 << 20) | (1 << 11);
4814 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4817 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4818 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4819 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4821 REG_WR(bp, BNX2_DMA_CONFIG, val);
4823 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4824 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4825 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4826 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4829 if (bp->flags & BNX2_FLAG_PCIX) {
4832 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4834 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4835 val16 & ~PCI_X_CMD_ERO);
4838 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4839 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4840 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4841 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4843 /* Initialize context mapping and zero out the quick contexts. The
4844 * context block must have already been enabled. */
4845 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4846 rc = bnx2_init_5709_context(bp);
4850 bnx2_init_context(bp);
4852 if ((rc = bnx2_init_cpus(bp)) != 0)
4855 bnx2_init_nvram(bp);
4857 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4859 val = REG_RD(bp, BNX2_MQ_CONFIG);
4860 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4861 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4862 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4863 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4864 if (CHIP_REV(bp) == CHIP_REV_Ax)
4865 val |= BNX2_MQ_CONFIG_HALT_DIS;
4868 REG_WR(bp, BNX2_MQ_CONFIG, val);
4870 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4871 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4872 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4874 val = (BCM_PAGE_BITS - 8) << 24;
4875 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4877 /* Configure page size. */
4878 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4879 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4880 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4881 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4883 val = bp->mac_addr[0] +
4884 (bp->mac_addr[1] << 8) +
4885 (bp->mac_addr[2] << 16) +
4887 (bp->mac_addr[4] << 8) +
4888 (bp->mac_addr[5] << 16);
4889 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4891 /* Program the MTU. Also include 4 bytes for CRC32. */
4893 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4894 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4895 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4896 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4901 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4902 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4903 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4905 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4906 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4907 bp->bnx2_napi[i].last_status_idx = 0;
4909 bp->idle_chk_status_idx = 0xffff;
4911 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4913 /* Set up how to generate a link change interrupt. */
4914 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4916 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4917 (u64) bp->status_blk_mapping & 0xffffffff);
4918 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4920 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4921 (u64) bp->stats_blk_mapping & 0xffffffff);
4922 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4923 (u64) bp->stats_blk_mapping >> 32);
4925 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4926 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4928 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4929 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4931 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4932 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4934 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4936 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4938 REG_WR(bp, BNX2_HC_COM_TICKS,
4939 (bp->com_ticks_int << 16) | bp->com_ticks);
4941 REG_WR(bp, BNX2_HC_CMD_TICKS,
4942 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4944 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4945 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4947 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4948 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4950 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4951 val = BNX2_HC_CONFIG_COLLECT_STATS;
4953 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4954 BNX2_HC_CONFIG_COLLECT_STATS;
4957 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4958 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4959 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4961 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4964 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4965 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4967 REG_WR(bp, BNX2_HC_CONFIG, val);
4969 for (i = 1; i < bp->irq_nvecs; i++) {
4970 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4971 BNX2_HC_SB_CONFIG_1;
4974 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4975 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4976 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4978 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4979 (bp->tx_quick_cons_trip_int << 16) |
4980 bp->tx_quick_cons_trip);
4982 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4983 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4985 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4986 (bp->rx_quick_cons_trip_int << 16) |
4987 bp->rx_quick_cons_trip);
4989 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4990 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4993 /* Clear internal stats counters. */
4994 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4996 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4998 /* Initialize the receive filter. */
4999 bnx2_set_rx_mode(bp->dev);
5001 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5002 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
5003 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
5004 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
5006 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
5009 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5010 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5014 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5020 bnx2_clear_ring_states(struct bnx2 *bp)
5022 struct bnx2_napi *bnapi;
5023 struct bnx2_tx_ring_info *txr;
5024 struct bnx2_rx_ring_info *rxr;
5027 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5028 bnapi = &bp->bnx2_napi[i];
5029 txr = &bnapi->tx_ring;
5030 rxr = &bnapi->rx_ring;
5033 txr->hw_tx_cons = 0;
5034 rxr->rx_prod_bseq = 0;
5037 rxr->rx_pg_prod = 0;
5038 rxr->rx_pg_cons = 0;
5043 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5045 u32 val, offset0, offset1, offset2, offset3;
5046 u32 cid_addr = GET_CID_ADDR(cid);
5048 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5049 offset0 = BNX2_L2CTX_TYPE_XI;
5050 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5051 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5052 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5054 offset0 = BNX2_L2CTX_TYPE;
5055 offset1 = BNX2_L2CTX_CMD_TYPE;
5056 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5057 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5059 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5060 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5062 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5063 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5065 val = (u64) txr->tx_desc_mapping >> 32;
5066 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5068 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5069 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5073 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5077 struct bnx2_napi *bnapi;
5078 struct bnx2_tx_ring_info *txr;
5080 bnapi = &bp->bnx2_napi[ring_num];
5081 txr = &bnapi->tx_ring;
5086 cid = TX_TSS_CID + ring_num - 1;
5088 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5090 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5092 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5093 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5096 txr->tx_prod_bseq = 0;
5098 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5099 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5101 bnx2_init_tx_context(bp, cid, txr);
5105 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5111 for (i = 0; i < num_rings; i++) {
5114 rxbd = &rx_ring[i][0];
5115 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5116 rxbd->rx_bd_len = buf_size;
5117 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5119 if (i == (num_rings - 1))
5123 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5124 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5129 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5132 u16 prod, ring_prod;
5133 u32 cid, rx_cid_addr, val;
5134 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5135 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5140 cid = RX_RSS_CID + ring_num - 1;
5142 rx_cid_addr = GET_CID_ADDR(cid);
5144 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5145 bp->rx_buf_use_size, bp->rx_max_ring);
5147 bnx2_init_rx_context(bp, cid);
5149 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5150 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5151 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5154 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5155 if (bp->rx_pg_ring_size) {
5156 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5157 rxr->rx_pg_desc_mapping,
5158 PAGE_SIZE, bp->rx_max_pg_ring);
5159 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5160 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5161 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5162 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5164 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5165 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5167 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5168 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5170 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5171 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5174 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5175 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5177 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5178 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5180 ring_prod = prod = rxr->rx_pg_prod;
5181 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5182 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) {
5183 netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5184 ring_num, i, bp->rx_pg_ring_size);
5187 prod = NEXT_RX_BD(prod);
5188 ring_prod = RX_PG_RING_IDX(prod);
5190 rxr->rx_pg_prod = prod;
5192 ring_prod = prod = rxr->rx_prod;
5193 for (i = 0; i < bp->rx_ring_size; i++) {
5194 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) {
5195 netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5196 ring_num, i, bp->rx_ring_size);
5199 prod = NEXT_RX_BD(prod);
5200 ring_prod = RX_RING_IDX(prod);
5202 rxr->rx_prod = prod;
5204 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5205 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5206 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5208 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5209 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5211 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5215 bnx2_init_all_rings(struct bnx2 *bp)
5220 bnx2_clear_ring_states(bp);
5222 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5223 for (i = 0; i < bp->num_tx_rings; i++)
5224 bnx2_init_tx_ring(bp, i);
5226 if (bp->num_tx_rings > 1)
5227 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5230 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5231 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5233 for (i = 0; i < bp->num_rx_rings; i++)
5234 bnx2_init_rx_ring(bp, i);
5236 if (bp->num_rx_rings > 1) {
5238 u8 *tbl = (u8 *) &tbl_32;
5240 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5241 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5243 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5244 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5247 BNX2_RXP_SCRATCH_RSS_TBL + i,
5248 cpu_to_be32(tbl_32));
5251 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5252 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5254 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5259 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5261 u32 max, num_rings = 1;
5263 while (ring_size > MAX_RX_DESC_CNT) {
5264 ring_size -= MAX_RX_DESC_CNT;
5267 /* round to next power of 2 */
5269 while ((max & num_rings) == 0)
5272 if (num_rings != max)
5279 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5281 u32 rx_size, rx_space, jumbo_size;
5283 /* 8 for CRC and VLAN */
5284 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5286 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5287 sizeof(struct skb_shared_info);
5289 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5290 bp->rx_pg_ring_size = 0;
5291 bp->rx_max_pg_ring = 0;
5292 bp->rx_max_pg_ring_idx = 0;
5293 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5294 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5296 jumbo_size = size * pages;
5297 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5298 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5300 bp->rx_pg_ring_size = jumbo_size;
5301 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5303 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5304 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5305 bp->rx_copy_thresh = 0;
5308 bp->rx_buf_use_size = rx_size;
5310 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5311 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5312 bp->rx_ring_size = size;
5313 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5314 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5318 bnx2_free_tx_skbs(struct bnx2 *bp)
5322 for (i = 0; i < bp->num_tx_rings; i++) {
5323 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5324 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5327 if (txr->tx_buf_ring == NULL)
5330 for (j = 0; j < TX_DESC_CNT; ) {
5331 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5332 struct sk_buff *skb = tx_buf->skb;
5340 pci_unmap_single(bp->pdev,
5341 dma_unmap_addr(tx_buf, mapping),
5347 last = tx_buf->nr_frags;
5349 for (k = 0; k < last; k++, j++) {
5350 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5351 pci_unmap_page(bp->pdev,
5352 dma_unmap_addr(tx_buf, mapping),
5353 skb_shinfo(skb)->frags[k].size,
5362 bnx2_free_rx_skbs(struct bnx2 *bp)
5366 for (i = 0; i < bp->num_rx_rings; i++) {
5367 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5368 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5371 if (rxr->rx_buf_ring == NULL)
5374 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5375 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5376 struct sk_buff *skb = rx_buf->skb;
5381 pci_unmap_single(bp->pdev,
5382 dma_unmap_addr(rx_buf, mapping),
5383 bp->rx_buf_use_size,
5384 PCI_DMA_FROMDEVICE);
5390 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5391 bnx2_free_rx_page(bp, rxr, j);
5396 bnx2_free_skbs(struct bnx2 *bp)
5398 bnx2_free_tx_skbs(bp);
5399 bnx2_free_rx_skbs(bp);
5403 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5407 rc = bnx2_reset_chip(bp, reset_code);
5412 if ((rc = bnx2_init_chip(bp)) != 0)
5415 bnx2_init_all_rings(bp);
5420 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5424 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5427 spin_lock_bh(&bp->phy_lock);
5428 bnx2_init_phy(bp, reset_phy);
5430 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5431 bnx2_remote_phy_event(bp);
5432 spin_unlock_bh(&bp->phy_lock);
5437 bnx2_shutdown_chip(struct bnx2 *bp)
5441 if (bp->flags & BNX2_FLAG_NO_WOL)
5442 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5444 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5446 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5448 return bnx2_reset_chip(bp, reset_code);
5452 bnx2_test_registers(struct bnx2 *bp)
5456 static const struct {
5459 #define BNX2_FL_NOT_5709 1
5463 { 0x006c, 0, 0x00000000, 0x0000003f },
5464 { 0x0090, 0, 0xffffffff, 0x00000000 },
5465 { 0x0094, 0, 0x00000000, 0x00000000 },
5467 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5468 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5469 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5470 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5471 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5472 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5473 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5474 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5475 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5477 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5478 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5479 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5480 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5481 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5482 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5484 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5485 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5486 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5488 { 0x1000, 0, 0x00000000, 0x00000001 },
5489 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5491 { 0x1408, 0, 0x01c00800, 0x00000000 },
5492 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5493 { 0x14a8, 0, 0x00000000, 0x000001ff },
5494 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5495 { 0x14b0, 0, 0x00000002, 0x00000001 },
5496 { 0x14b8, 0, 0x00000000, 0x00000000 },
5497 { 0x14c0, 0, 0x00000000, 0x00000009 },
5498 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5499 { 0x14cc, 0, 0x00000000, 0x00000001 },
5500 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5502 { 0x1800, 0, 0x00000000, 0x00000001 },
5503 { 0x1804, 0, 0x00000000, 0x00000003 },
5505 { 0x2800, 0, 0x00000000, 0x00000001 },
5506 { 0x2804, 0, 0x00000000, 0x00003f01 },
5507 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5508 { 0x2810, 0, 0xffff0000, 0x00000000 },
5509 { 0x2814, 0, 0xffff0000, 0x00000000 },
5510 { 0x2818, 0, 0xffff0000, 0x00000000 },
5511 { 0x281c, 0, 0xffff0000, 0x00000000 },
5512 { 0x2834, 0, 0xffffffff, 0x00000000 },
5513 { 0x2840, 0, 0x00000000, 0xffffffff },
5514 { 0x2844, 0, 0x00000000, 0xffffffff },
5515 { 0x2848, 0, 0xffffffff, 0x00000000 },
5516 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5518 { 0x2c00, 0, 0x00000000, 0x00000011 },
5519 { 0x2c04, 0, 0x00000000, 0x00030007 },
5521 { 0x3c00, 0, 0x00000000, 0x00000001 },
5522 { 0x3c04, 0, 0x00000000, 0x00070000 },
5523 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5524 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5525 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5526 { 0x3c14, 0, 0x00000000, 0xffffffff },
5527 { 0x3c18, 0, 0x00000000, 0xffffffff },
5528 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5529 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5531 { 0x5004, 0, 0x00000000, 0x0000007f },
5532 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5534 { 0x5c00, 0, 0x00000000, 0x00000001 },
5535 { 0x5c04, 0, 0x00000000, 0x0003000f },
5536 { 0x5c08, 0, 0x00000003, 0x00000000 },
5537 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5538 { 0x5c10, 0, 0x00000000, 0xffffffff },
5539 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5540 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5541 { 0x5c88, 0, 0x00000000, 0x00077373 },
5542 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5544 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5545 { 0x680c, 0, 0xffffffff, 0x00000000 },
5546 { 0x6810, 0, 0xffffffff, 0x00000000 },
5547 { 0x6814, 0, 0xffffffff, 0x00000000 },
5548 { 0x6818, 0, 0xffffffff, 0x00000000 },
5549 { 0x681c, 0, 0xffffffff, 0x00000000 },
5550 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5551 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5552 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5553 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5554 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5555 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5556 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5557 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5558 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5559 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5560 { 0x684c, 0, 0xffffffff, 0x00000000 },
5561 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5562 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5563 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5564 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5565 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5566 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5568 { 0xffff, 0, 0x00000000, 0x00000000 },
5573 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5576 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5577 u32 offset, rw_mask, ro_mask, save_val, val;
5578 u16 flags = reg_tbl[i].flags;
5580 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5583 offset = (u32) reg_tbl[i].offset;
5584 rw_mask = reg_tbl[i].rw_mask;
5585 ro_mask = reg_tbl[i].ro_mask;
5587 save_val = readl(bp->regview + offset);
5589 writel(0, bp->regview + offset);
5591 val = readl(bp->regview + offset);
5592 if ((val & rw_mask) != 0) {
5596 if ((val & ro_mask) != (save_val & ro_mask)) {
5600 writel(0xffffffff, bp->regview + offset);
5602 val = readl(bp->regview + offset);
5603 if ((val & rw_mask) != rw_mask) {
5607 if ((val & ro_mask) != (save_val & ro_mask)) {
5611 writel(save_val, bp->regview + offset);
5615 writel(save_val, bp->regview + offset);
5623 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5625 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5626 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5629 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5632 for (offset = 0; offset < size; offset += 4) {
5634 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5636 if (bnx2_reg_rd_ind(bp, start + offset) !=
5646 bnx2_test_memory(struct bnx2 *bp)
5650 static struct mem_entry {
5653 } mem_tbl_5706[] = {
5654 { 0x60000, 0x4000 },
5655 { 0xa0000, 0x3000 },
5656 { 0xe0000, 0x4000 },
5657 { 0x120000, 0x4000 },
5658 { 0x1a0000, 0x4000 },
5659 { 0x160000, 0x4000 },
5663 { 0x60000, 0x4000 },
5664 { 0xa0000, 0x3000 },
5665 { 0xe0000, 0x4000 },
5666 { 0x120000, 0x4000 },
5667 { 0x1a0000, 0x4000 },
5670 struct mem_entry *mem_tbl;
5672 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5673 mem_tbl = mem_tbl_5709;
5675 mem_tbl = mem_tbl_5706;
5677 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5678 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5679 mem_tbl[i].len)) != 0) {
5687 #define BNX2_MAC_LOOPBACK 0
5688 #define BNX2_PHY_LOOPBACK 1
5691 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5693 unsigned int pkt_size, num_pkts, i;
5694 struct sk_buff *skb, *rx_skb;
5695 unsigned char *packet;
5696 u16 rx_start_idx, rx_idx;
5699 struct sw_bd *rx_buf;
5700 struct l2_fhdr *rx_hdr;
5702 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5703 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5704 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5708 txr = &tx_napi->tx_ring;
5709 rxr = &bnapi->rx_ring;
5710 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5711 bp->loopback = MAC_LOOPBACK;
5712 bnx2_set_mac_loopback(bp);
5714 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5715 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5718 bp->loopback = PHY_LOOPBACK;
5719 bnx2_set_phy_loopback(bp);
5724 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5725 skb = netdev_alloc_skb(bp->dev, pkt_size);
5728 packet = skb_put(skb, pkt_size);
5729 memcpy(packet, bp->dev->dev_addr, 6);
5730 memset(packet + 6, 0x0, 8);
5731 for (i = 14; i < pkt_size; i++)
5732 packet[i] = (unsigned char) (i & 0xff);
5734 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5736 if (pci_dma_mapping_error(bp->pdev, map)) {
5741 REG_WR(bp, BNX2_HC_COMMAND,
5742 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5744 REG_RD(bp, BNX2_HC_COMMAND);
5747 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5751 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5753 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5754 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5755 txbd->tx_bd_mss_nbytes = pkt_size;
5756 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5759 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5760 txr->tx_prod_bseq += pkt_size;
5762 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5763 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5767 REG_WR(bp, BNX2_HC_COMMAND,
5768 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5770 REG_RD(bp, BNX2_HC_COMMAND);
5774 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5777 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5778 goto loopback_test_done;
5780 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5781 if (rx_idx != rx_start_idx + num_pkts) {
5782 goto loopback_test_done;
5785 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5786 rx_skb = rx_buf->skb;
5788 rx_hdr = rx_buf->desc;
5789 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5791 pci_dma_sync_single_for_cpu(bp->pdev,
5792 dma_unmap_addr(rx_buf, mapping),
5793 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5795 if (rx_hdr->l2_fhdr_status &
5796 (L2_FHDR_ERRORS_BAD_CRC |
5797 L2_FHDR_ERRORS_PHY_DECODE |
5798 L2_FHDR_ERRORS_ALIGNMENT |
5799 L2_FHDR_ERRORS_TOO_SHORT |
5800 L2_FHDR_ERRORS_GIANT_FRAME)) {
5802 goto loopback_test_done;
5805 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5806 goto loopback_test_done;
5809 for (i = 14; i < pkt_size; i++) {
5810 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5811 goto loopback_test_done;
5822 #define BNX2_MAC_LOOPBACK_FAILED 1
5823 #define BNX2_PHY_LOOPBACK_FAILED 2
5824 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5825 BNX2_PHY_LOOPBACK_FAILED)
5828 bnx2_test_loopback(struct bnx2 *bp)
5832 if (!netif_running(bp->dev))
5833 return BNX2_LOOPBACK_FAILED;
5835 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5836 spin_lock_bh(&bp->phy_lock);
5837 bnx2_init_phy(bp, 1);
5838 spin_unlock_bh(&bp->phy_lock);
5839 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5840 rc |= BNX2_MAC_LOOPBACK_FAILED;
5841 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5842 rc |= BNX2_PHY_LOOPBACK_FAILED;
5846 #define NVRAM_SIZE 0x200
5847 #define CRC32_RESIDUAL 0xdebb20e3
5850 bnx2_test_nvram(struct bnx2 *bp)
5852 __be32 buf[NVRAM_SIZE / 4];
5853 u8 *data = (u8 *) buf;
5857 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5858 goto test_nvram_done;
5860 magic = be32_to_cpu(buf[0]);
5861 if (magic != 0x669955aa) {
5863 goto test_nvram_done;
5866 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5867 goto test_nvram_done;
5869 csum = ether_crc_le(0x100, data);
5870 if (csum != CRC32_RESIDUAL) {
5872 goto test_nvram_done;
5875 csum = ether_crc_le(0x100, data + 0x100);
5876 if (csum != CRC32_RESIDUAL) {
5885 bnx2_test_link(struct bnx2 *bp)
5889 if (!netif_running(bp->dev))
5892 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5897 spin_lock_bh(&bp->phy_lock);
5898 bnx2_enable_bmsr1(bp);
5899 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5900 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5901 bnx2_disable_bmsr1(bp);
5902 spin_unlock_bh(&bp->phy_lock);
5904 if (bmsr & BMSR_LSTATUS) {
5911 bnx2_test_intr(struct bnx2 *bp)
5916 if (!netif_running(bp->dev))
5919 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5921 /* This register is not touched during run-time. */
5922 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5923 REG_RD(bp, BNX2_HC_COMMAND);
5925 for (i = 0; i < 10; i++) {
5926 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5932 msleep_interruptible(10);
5940 /* Determining link for parallel detection. */
5942 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5944 u32 mode_ctl, an_dbg, exp;
5946 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5949 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5950 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5952 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5955 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5956 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5957 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5959 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5962 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5963 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5964 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5966 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5973 bnx2_5706_serdes_timer(struct bnx2 *bp)
5977 spin_lock(&bp->phy_lock);
5978 if (bp->serdes_an_pending) {
5979 bp->serdes_an_pending--;
5981 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5984 bp->current_interval = BNX2_TIMER_INTERVAL;
5986 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5988 if (bmcr & BMCR_ANENABLE) {
5989 if (bnx2_5706_serdes_has_link(bp)) {
5990 bmcr &= ~BMCR_ANENABLE;
5991 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5992 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5993 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5997 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5998 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
6001 bnx2_write_phy(bp, 0x17, 0x0f01);
6002 bnx2_read_phy(bp, 0x15, &phy2);
6006 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6007 bmcr |= BMCR_ANENABLE;
6008 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6010 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
6013 bp->current_interval = BNX2_TIMER_INTERVAL;
6018 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6019 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6020 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6022 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6023 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6024 bnx2_5706s_force_link_dn(bp, 1);
6025 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6028 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6031 spin_unlock(&bp->phy_lock);
6035 bnx2_5708_serdes_timer(struct bnx2 *bp)
6037 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6040 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6041 bp->serdes_an_pending = 0;
6045 spin_lock(&bp->phy_lock);
6046 if (bp->serdes_an_pending)
6047 bp->serdes_an_pending--;
6048 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6051 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6052 if (bmcr & BMCR_ANENABLE) {
6053 bnx2_enable_forced_2g5(bp);
6054 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6056 bnx2_disable_forced_2g5(bp);
6057 bp->serdes_an_pending = 2;
6058 bp->current_interval = BNX2_TIMER_INTERVAL;
6062 bp->current_interval = BNX2_TIMER_INTERVAL;
6064 spin_unlock(&bp->phy_lock);
6068 bnx2_timer(unsigned long data)
6070 struct bnx2 *bp = (struct bnx2 *) data;
6072 if (!netif_running(bp->dev))
6075 if (atomic_read(&bp->intr_sem) != 0)
6076 goto bnx2_restart_timer;
6078 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6079 BNX2_FLAG_USING_MSI)
6080 bnx2_chk_missed_msi(bp);
6082 bnx2_send_heart_beat(bp);
6084 bp->stats_blk->stat_FwRxDrop =
6085 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6087 /* workaround occasional corrupted counters */
6088 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6089 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6090 BNX2_HC_COMMAND_STATS_NOW);
6092 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6093 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6094 bnx2_5706_serdes_timer(bp);
6096 bnx2_5708_serdes_timer(bp);
6100 mod_timer(&bp->timer, jiffies + bp->current_interval);
6104 bnx2_request_irq(struct bnx2 *bp)
6106 unsigned long flags;
6107 struct bnx2_irq *irq;
6110 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6113 flags = IRQF_SHARED;
6115 for (i = 0; i < bp->irq_nvecs; i++) {
6116 irq = &bp->irq_tbl[i];
6117 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6127 bnx2_free_irq(struct bnx2 *bp)
6129 struct bnx2_irq *irq;
6132 for (i = 0; i < bp->irq_nvecs; i++) {
6133 irq = &bp->irq_tbl[i];
6135 free_irq(irq->vector, &bp->bnx2_napi[i]);
6138 if (bp->flags & BNX2_FLAG_USING_MSI)
6139 pci_disable_msi(bp->pdev);
6140 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6141 pci_disable_msix(bp->pdev);
6143 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6147 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6150 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6151 struct net_device *dev = bp->dev;
6152 const int len = sizeof(bp->irq_tbl[0].name);
6154 bnx2_setup_msix_tbl(bp);
6155 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6156 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6157 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6159 /* Need to flush the previous three writes to ensure MSI-X
6160 * is setup properly */
6161 REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6163 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6164 msix_ent[i].entry = i;
6165 msix_ent[i].vector = 0;
6168 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6172 bp->irq_nvecs = msix_vecs;
6173 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6174 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6175 bp->irq_tbl[i].vector = msix_ent[i].vector;
6176 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6177 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6182 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6184 int cpus = num_online_cpus();
6185 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6187 bp->irq_tbl[0].handler = bnx2_interrupt;
6188 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6190 bp->irq_tbl[0].vector = bp->pdev->irq;
6192 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
6193 bnx2_enable_msix(bp, msix_vecs);
6195 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6196 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6197 if (pci_enable_msi(bp->pdev) == 0) {
6198 bp->flags |= BNX2_FLAG_USING_MSI;
6199 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6200 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6201 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6203 bp->irq_tbl[0].handler = bnx2_msi;
6205 bp->irq_tbl[0].vector = bp->pdev->irq;
6209 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6210 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6212 bp->num_rx_rings = bp->irq_nvecs;
6215 /* Called with rtnl_lock */
6217 bnx2_open(struct net_device *dev)
6219 struct bnx2 *bp = netdev_priv(dev);
6222 netif_carrier_off(dev);
6224 bnx2_set_power_state(bp, PCI_D0);
6225 bnx2_disable_int(bp);
6227 bnx2_setup_int_mode(bp, disable_msi);
6229 bnx2_napi_enable(bp);
6230 rc = bnx2_alloc_mem(bp);
6234 rc = bnx2_request_irq(bp);
6238 rc = bnx2_init_nic(bp, 1);
6242 mod_timer(&bp->timer, jiffies + bp->current_interval);
6244 atomic_set(&bp->intr_sem, 0);
6246 memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6248 bnx2_enable_int(bp);
6250 if (bp->flags & BNX2_FLAG_USING_MSI) {
6251 /* Test MSI to make sure it is working
6252 * If MSI test fails, go back to INTx mode
6254 if (bnx2_test_intr(bp) != 0) {
6255 netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6257 bnx2_disable_int(bp);
6260 bnx2_setup_int_mode(bp, 1);
6262 rc = bnx2_init_nic(bp, 0);
6265 rc = bnx2_request_irq(bp);
6268 del_timer_sync(&bp->timer);
6271 bnx2_enable_int(bp);
6274 if (bp->flags & BNX2_FLAG_USING_MSI)
6275 netdev_info(dev, "using MSI\n");
6276 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6277 netdev_info(dev, "using MSIX\n");
6279 netif_tx_start_all_queues(dev);
6284 bnx2_napi_disable(bp);
6293 bnx2_reset_task(struct work_struct *work)
6295 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6298 if (!netif_running(bp->dev)) {
6303 bnx2_netif_stop(bp, true);
6305 bnx2_init_nic(bp, 1);
6307 atomic_set(&bp->intr_sem, 1);
6308 bnx2_netif_start(bp, true);
6313 bnx2_dump_state(struct bnx2 *bp)
6315 struct net_device *dev = bp->dev;
6318 netdev_err(dev, "DEBUG: intr_sem[%x]\n", atomic_read(&bp->intr_sem));
6319 netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
6320 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6321 REG_RD(bp, BNX2_EMAC_RX_STATUS));
6322 netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
6323 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6324 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6325 mcp_p0 = BNX2_MCP_STATE_P0;
6326 mcp_p1 = BNX2_MCP_STATE_P1;
6328 mcp_p0 = BNX2_MCP_STATE_P0_5708;
6329 mcp_p1 = BNX2_MCP_STATE_P1_5708;
6331 netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
6332 bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
6333 netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6334 REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6335 if (bp->flags & BNX2_FLAG_USING_MSIX)
6336 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6337 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6341 bnx2_tx_timeout(struct net_device *dev)
6343 struct bnx2 *bp = netdev_priv(dev);
6345 bnx2_dump_state(bp);
6347 /* This allows the netif to be shutdown gracefully before resetting */
6348 schedule_work(&bp->reset_task);
6352 /* Called with rtnl_lock */
6354 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6356 struct bnx2 *bp = netdev_priv(dev);
6358 if (netif_running(dev))
6359 bnx2_netif_stop(bp, false);
6363 if (!netif_running(dev))
6366 bnx2_set_rx_mode(dev);
6367 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6368 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6370 bnx2_netif_start(bp, false);
6374 /* Called with netif_tx_lock.
6375 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6376 * netif_wake_queue().
6379 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6381 struct bnx2 *bp = netdev_priv(dev);
6384 struct sw_tx_bd *tx_buf;
6385 u32 len, vlan_tag_flags, last_frag, mss;
6386 u16 prod, ring_prod;
6388 struct bnx2_napi *bnapi;
6389 struct bnx2_tx_ring_info *txr;
6390 struct netdev_queue *txq;
6392 /* Determine which tx ring we will be placed on */
6393 i = skb_get_queue_mapping(skb);
6394 bnapi = &bp->bnx2_napi[i];
6395 txr = &bnapi->tx_ring;
6396 txq = netdev_get_tx_queue(dev, i);
6398 if (unlikely(bnx2_tx_avail(bp, txr) <
6399 (skb_shinfo(skb)->nr_frags + 1))) {
6400 netif_tx_stop_queue(txq);
6401 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6403 return NETDEV_TX_BUSY;
6405 len = skb_headlen(skb);
6406 prod = txr->tx_prod;
6407 ring_prod = TX_RING_IDX(prod);
6410 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6411 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6415 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6417 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6420 if ((mss = skb_shinfo(skb)->gso_size)) {
6424 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6426 tcp_opt_len = tcp_optlen(skb);
6428 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6429 u32 tcp_off = skb_transport_offset(skb) -
6430 sizeof(struct ipv6hdr) - ETH_HLEN;
6432 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6433 TX_BD_FLAGS_SW_FLAGS;
6434 if (likely(tcp_off == 0))
6435 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6438 vlan_tag_flags |= ((tcp_off & 0x3) <<
6439 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6440 ((tcp_off & 0x10) <<
6441 TX_BD_FLAGS_TCP6_OFF4_SHL);
6442 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6446 if (tcp_opt_len || (iph->ihl > 5)) {
6447 vlan_tag_flags |= ((iph->ihl - 5) +
6448 (tcp_opt_len >> 2)) << 8;
6454 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6455 if (pci_dma_mapping_error(bp->pdev, mapping)) {
6457 return NETDEV_TX_OK;
6460 tx_buf = &txr->tx_buf_ring[ring_prod];
6462 dma_unmap_addr_set(tx_buf, mapping, mapping);
6464 txbd = &txr->tx_desc_ring[ring_prod];
6466 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6467 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6468 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6469 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6471 last_frag = skb_shinfo(skb)->nr_frags;
6472 tx_buf->nr_frags = last_frag;
6473 tx_buf->is_gso = skb_is_gso(skb);
6475 for (i = 0; i < last_frag; i++) {
6476 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6478 prod = NEXT_TX_BD(prod);
6479 ring_prod = TX_RING_IDX(prod);
6480 txbd = &txr->tx_desc_ring[ring_prod];
6483 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6484 len, PCI_DMA_TODEVICE);
6485 if (pci_dma_mapping_error(bp->pdev, mapping))
6487 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6490 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6491 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6492 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6493 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6496 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6498 prod = NEXT_TX_BD(prod);
6499 txr->tx_prod_bseq += skb->len;
6501 REG_WR16(bp, txr->tx_bidx_addr, prod);
6502 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6506 txr->tx_prod = prod;
6508 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6509 netif_tx_stop_queue(txq);
6510 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6511 netif_tx_wake_queue(txq);
6514 return NETDEV_TX_OK;
6516 /* save value of frag that failed */
6519 /* start back at beginning and unmap skb */
6520 prod = txr->tx_prod;
6521 ring_prod = TX_RING_IDX(prod);
6522 tx_buf = &txr->tx_buf_ring[ring_prod];
6524 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
6525 skb_headlen(skb), PCI_DMA_TODEVICE);
6527 /* unmap remaining mapped pages */
6528 for (i = 0; i < last_frag; i++) {
6529 prod = NEXT_TX_BD(prod);
6530 ring_prod = TX_RING_IDX(prod);
6531 tx_buf = &txr->tx_buf_ring[ring_prod];
6532 pci_unmap_page(bp->pdev, dma_unmap_addr(tx_buf, mapping),
6533 skb_shinfo(skb)->frags[i].size,
6538 return NETDEV_TX_OK;
6541 /* Called with rtnl_lock */
6543 bnx2_close(struct net_device *dev)
6545 struct bnx2 *bp = netdev_priv(dev);
6547 cancel_work_sync(&bp->reset_task);
6549 bnx2_disable_int_sync(bp);
6550 bnx2_napi_disable(bp);
6551 del_timer_sync(&bp->timer);
6552 bnx2_shutdown_chip(bp);
6558 netif_carrier_off(bp->dev);
6559 bnx2_set_power_state(bp, PCI_D3hot);
6564 bnx2_save_stats(struct bnx2 *bp)
6566 u32 *hw_stats = (u32 *) bp->stats_blk;
6567 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6570 /* The 1st 10 counters are 64-bit counters */
6571 for (i = 0; i < 20; i += 2) {
6575 hi = temp_stats[i] + hw_stats[i];
6576 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6577 if (lo > 0xffffffff)
6580 temp_stats[i + 1] = lo & 0xffffffff;
6583 for ( ; i < sizeof(struct statistics_block) / 4; i++)
6584 temp_stats[i] += hw_stats[i];
6587 #define GET_64BIT_NET_STATS64(ctr) \
6588 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6589 (unsigned long) (ctr##_lo)
6591 #define GET_64BIT_NET_STATS32(ctr) \
6594 #if (BITS_PER_LONG == 64)
6595 #define GET_64BIT_NET_STATS(ctr) \
6596 GET_64BIT_NET_STATS64(bp->stats_blk->ctr) + \
6597 GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6599 #define GET_64BIT_NET_STATS(ctr) \
6600 GET_64BIT_NET_STATS32(bp->stats_blk->ctr) + \
6601 GET_64BIT_NET_STATS32(bp->temp_stats_blk->ctr)
6604 #define GET_32BIT_NET_STATS(ctr) \
6605 (unsigned long) (bp->stats_blk->ctr + \
6606 bp->temp_stats_blk->ctr)
6608 static struct net_device_stats *
6609 bnx2_get_stats(struct net_device *dev)
6611 struct bnx2 *bp = netdev_priv(dev);
6612 struct net_device_stats *net_stats = &dev->stats;
6614 if (bp->stats_blk == NULL) {
6617 net_stats->rx_packets =
6618 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6619 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6620 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6622 net_stats->tx_packets =
6623 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6624 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6625 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6627 net_stats->rx_bytes =
6628 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6630 net_stats->tx_bytes =
6631 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6633 net_stats->multicast =
6634 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts);
6636 net_stats->collisions =
6637 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6639 net_stats->rx_length_errors =
6640 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6641 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6643 net_stats->rx_over_errors =
6644 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6645 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6647 net_stats->rx_frame_errors =
6648 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6650 net_stats->rx_crc_errors =
6651 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6653 net_stats->rx_errors = net_stats->rx_length_errors +
6654 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6655 net_stats->rx_crc_errors;
6657 net_stats->tx_aborted_errors =
6658 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6659 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6661 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6662 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6663 net_stats->tx_carrier_errors = 0;
6665 net_stats->tx_carrier_errors =
6666 GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6669 net_stats->tx_errors =
6670 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6671 net_stats->tx_aborted_errors +
6672 net_stats->tx_carrier_errors;
6674 net_stats->rx_missed_errors =
6675 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6676 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6677 GET_32BIT_NET_STATS(stat_FwRxDrop);
6682 /* All ethtool functions called with rtnl_lock */
6685 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6687 struct bnx2 *bp = netdev_priv(dev);
6688 int support_serdes = 0, support_copper = 0;
6690 cmd->supported = SUPPORTED_Autoneg;
6691 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6694 } else if (bp->phy_port == PORT_FIBRE)
6699 if (support_serdes) {
6700 cmd->supported |= SUPPORTED_1000baseT_Full |
6702 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6703 cmd->supported |= SUPPORTED_2500baseX_Full;
6706 if (support_copper) {
6707 cmd->supported |= SUPPORTED_10baseT_Half |
6708 SUPPORTED_10baseT_Full |
6709 SUPPORTED_100baseT_Half |
6710 SUPPORTED_100baseT_Full |
6711 SUPPORTED_1000baseT_Full |
6716 spin_lock_bh(&bp->phy_lock);
6717 cmd->port = bp->phy_port;
6718 cmd->advertising = bp->advertising;
6720 if (bp->autoneg & AUTONEG_SPEED) {
6721 cmd->autoneg = AUTONEG_ENABLE;
6724 cmd->autoneg = AUTONEG_DISABLE;
6727 if (netif_carrier_ok(dev)) {
6728 cmd->speed = bp->line_speed;
6729 cmd->duplex = bp->duplex;
6735 spin_unlock_bh(&bp->phy_lock);
6737 cmd->transceiver = XCVR_INTERNAL;
6738 cmd->phy_address = bp->phy_addr;
6744 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6746 struct bnx2 *bp = netdev_priv(dev);
6747 u8 autoneg = bp->autoneg;
6748 u8 req_duplex = bp->req_duplex;
6749 u16 req_line_speed = bp->req_line_speed;
6750 u32 advertising = bp->advertising;
6753 spin_lock_bh(&bp->phy_lock);
6755 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6756 goto err_out_unlock;
6758 if (cmd->port != bp->phy_port &&
6759 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6760 goto err_out_unlock;
6762 /* If device is down, we can store the settings only if the user
6763 * is setting the currently active port.
6765 if (!netif_running(dev) && cmd->port != bp->phy_port)
6766 goto err_out_unlock;
6768 if (cmd->autoneg == AUTONEG_ENABLE) {
6769 autoneg |= AUTONEG_SPEED;
6771 advertising = cmd->advertising;
6772 if (cmd->port == PORT_TP) {
6773 advertising &= ETHTOOL_ALL_COPPER_SPEED;
6775 advertising = ETHTOOL_ALL_COPPER_SPEED;
6777 advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6779 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6781 advertising |= ADVERTISED_Autoneg;
6784 if (cmd->port == PORT_FIBRE) {
6785 if ((cmd->speed != SPEED_1000 &&
6786 cmd->speed != SPEED_2500) ||
6787 (cmd->duplex != DUPLEX_FULL))
6788 goto err_out_unlock;
6790 if (cmd->speed == SPEED_2500 &&
6791 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6792 goto err_out_unlock;
6794 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6795 goto err_out_unlock;
6797 autoneg &= ~AUTONEG_SPEED;
6798 req_line_speed = cmd->speed;
6799 req_duplex = cmd->duplex;
6803 bp->autoneg = autoneg;
6804 bp->advertising = advertising;
6805 bp->req_line_speed = req_line_speed;
6806 bp->req_duplex = req_duplex;
6809 /* If device is down, the new settings will be picked up when it is
6812 if (netif_running(dev))
6813 err = bnx2_setup_phy(bp, cmd->port);
6816 spin_unlock_bh(&bp->phy_lock);
6822 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6824 struct bnx2 *bp = netdev_priv(dev);
6826 strcpy(info->driver, DRV_MODULE_NAME);
6827 strcpy(info->version, DRV_MODULE_VERSION);
6828 strcpy(info->bus_info, pci_name(bp->pdev));
6829 strcpy(info->fw_version, bp->fw_version);
6832 #define BNX2_REGDUMP_LEN (32 * 1024)
6835 bnx2_get_regs_len(struct net_device *dev)
6837 return BNX2_REGDUMP_LEN;
6841 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6843 u32 *p = _p, i, offset;
6845 struct bnx2 *bp = netdev_priv(dev);
6846 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6847 0x0800, 0x0880, 0x0c00, 0x0c10,
6848 0x0c30, 0x0d08, 0x1000, 0x101c,
6849 0x1040, 0x1048, 0x1080, 0x10a4,
6850 0x1400, 0x1490, 0x1498, 0x14f0,
6851 0x1500, 0x155c, 0x1580, 0x15dc,
6852 0x1600, 0x1658, 0x1680, 0x16d8,
6853 0x1800, 0x1820, 0x1840, 0x1854,
6854 0x1880, 0x1894, 0x1900, 0x1984,
6855 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6856 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6857 0x2000, 0x2030, 0x23c0, 0x2400,
6858 0x2800, 0x2820, 0x2830, 0x2850,
6859 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6860 0x3c00, 0x3c94, 0x4000, 0x4010,
6861 0x4080, 0x4090, 0x43c0, 0x4458,
6862 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6863 0x4fc0, 0x5010, 0x53c0, 0x5444,
6864 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6865 0x5fc0, 0x6000, 0x6400, 0x6428,
6866 0x6800, 0x6848, 0x684c, 0x6860,
6867 0x6888, 0x6910, 0x8000 };
6871 memset(p, 0, BNX2_REGDUMP_LEN);
6873 if (!netif_running(bp->dev))
6877 offset = reg_boundaries[0];
6879 while (offset < BNX2_REGDUMP_LEN) {
6880 *p++ = REG_RD(bp, offset);
6882 if (offset == reg_boundaries[i + 1]) {
6883 offset = reg_boundaries[i + 2];
6884 p = (u32 *) (orig_p + offset);
6891 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6893 struct bnx2 *bp = netdev_priv(dev);
6895 if (bp->flags & BNX2_FLAG_NO_WOL) {
6900 wol->supported = WAKE_MAGIC;
6902 wol->wolopts = WAKE_MAGIC;
6906 memset(&wol->sopass, 0, sizeof(wol->sopass));
6910 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6912 struct bnx2 *bp = netdev_priv(dev);
6914 if (wol->wolopts & ~WAKE_MAGIC)
6917 if (wol->wolopts & WAKE_MAGIC) {
6918 if (bp->flags & BNX2_FLAG_NO_WOL)
6930 bnx2_nway_reset(struct net_device *dev)
6932 struct bnx2 *bp = netdev_priv(dev);
6935 if (!netif_running(dev))
6938 if (!(bp->autoneg & AUTONEG_SPEED)) {
6942 spin_lock_bh(&bp->phy_lock);
6944 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6947 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6948 spin_unlock_bh(&bp->phy_lock);
6952 /* Force a link down visible on the other side */
6953 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6954 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6955 spin_unlock_bh(&bp->phy_lock);
6959 spin_lock_bh(&bp->phy_lock);
6961 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6962 bp->serdes_an_pending = 1;
6963 mod_timer(&bp->timer, jiffies + bp->current_interval);
6966 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6967 bmcr &= ~BMCR_LOOPBACK;
6968 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6970 spin_unlock_bh(&bp->phy_lock);
6976 bnx2_get_link(struct net_device *dev)
6978 struct bnx2 *bp = netdev_priv(dev);
6984 bnx2_get_eeprom_len(struct net_device *dev)
6986 struct bnx2 *bp = netdev_priv(dev);
6988 if (bp->flash_info == NULL)
6991 return (int) bp->flash_size;
6995 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6998 struct bnx2 *bp = netdev_priv(dev);
7001 if (!netif_running(dev))
7004 /* parameters already validated in ethtool_get_eeprom */
7006 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
7012 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7015 struct bnx2 *bp = netdev_priv(dev);
7018 if (!netif_running(dev))
7021 /* parameters already validated in ethtool_set_eeprom */
7023 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7029 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7031 struct bnx2 *bp = netdev_priv(dev);
7033 memset(coal, 0, sizeof(struct ethtool_coalesce));
7035 coal->rx_coalesce_usecs = bp->rx_ticks;
7036 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7037 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7038 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7040 coal->tx_coalesce_usecs = bp->tx_ticks;
7041 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7042 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7043 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7045 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7051 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7053 struct bnx2 *bp = netdev_priv(dev);
7055 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7056 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7058 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7059 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7061 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7062 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7064 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7065 if (bp->rx_quick_cons_trip_int > 0xff)
7066 bp->rx_quick_cons_trip_int = 0xff;
7068 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7069 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7071 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7072 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7074 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7075 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7077 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7078 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7081 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7082 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7083 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7084 bp->stats_ticks = USEC_PER_SEC;
7086 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7087 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7088 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7090 if (netif_running(bp->dev)) {
7091 bnx2_netif_stop(bp, true);
7092 bnx2_init_nic(bp, 0);
7093 bnx2_netif_start(bp, true);
7100 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7102 struct bnx2 *bp = netdev_priv(dev);
7104 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7105 ering->rx_mini_max_pending = 0;
7106 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7108 ering->rx_pending = bp->rx_ring_size;
7109 ering->rx_mini_pending = 0;
7110 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7112 ering->tx_max_pending = MAX_TX_DESC_CNT;
7113 ering->tx_pending = bp->tx_ring_size;
7117 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7119 if (netif_running(bp->dev)) {
7120 /* Reset will erase chipset stats; save them */
7121 bnx2_save_stats(bp);
7123 bnx2_netif_stop(bp, true);
7124 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7129 bnx2_set_rx_ring_size(bp, rx);
7130 bp->tx_ring_size = tx;
7132 if (netif_running(bp->dev)) {
7135 rc = bnx2_alloc_mem(bp);
7137 rc = bnx2_init_nic(bp, 0);
7140 bnx2_napi_enable(bp);
7145 mutex_lock(&bp->cnic_lock);
7146 /* Let cnic know about the new status block. */
7147 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7148 bnx2_setup_cnic_irq_info(bp);
7149 mutex_unlock(&bp->cnic_lock);
7151 bnx2_netif_start(bp, true);
7157 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7159 struct bnx2 *bp = netdev_priv(dev);
7162 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7163 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7164 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7168 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7173 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7175 struct bnx2 *bp = netdev_priv(dev);
7177 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7178 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7179 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7183 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7185 struct bnx2 *bp = netdev_priv(dev);
7187 bp->req_flow_ctrl = 0;
7188 if (epause->rx_pause)
7189 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7190 if (epause->tx_pause)
7191 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7193 if (epause->autoneg) {
7194 bp->autoneg |= AUTONEG_FLOW_CTRL;
7197 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7200 if (netif_running(dev)) {
7201 spin_lock_bh(&bp->phy_lock);
7202 bnx2_setup_phy(bp, bp->phy_port);
7203 spin_unlock_bh(&bp->phy_lock);
7210 bnx2_get_rx_csum(struct net_device *dev)
7212 struct bnx2 *bp = netdev_priv(dev);
7218 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7220 struct bnx2 *bp = netdev_priv(dev);
7227 bnx2_set_tso(struct net_device *dev, u32 data)
7229 struct bnx2 *bp = netdev_priv(dev);
7232 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7233 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7234 dev->features |= NETIF_F_TSO6;
7236 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7242 char string[ETH_GSTRING_LEN];
7243 } bnx2_stats_str_arr[] = {
7245 { "rx_error_bytes" },
7247 { "tx_error_bytes" },
7248 { "rx_ucast_packets" },
7249 { "rx_mcast_packets" },
7250 { "rx_bcast_packets" },
7251 { "tx_ucast_packets" },
7252 { "tx_mcast_packets" },
7253 { "tx_bcast_packets" },
7254 { "tx_mac_errors" },
7255 { "tx_carrier_errors" },
7256 { "rx_crc_errors" },
7257 { "rx_align_errors" },
7258 { "tx_single_collisions" },
7259 { "tx_multi_collisions" },
7261 { "tx_excess_collisions" },
7262 { "tx_late_collisions" },
7263 { "tx_total_collisions" },
7266 { "rx_undersize_packets" },
7267 { "rx_oversize_packets" },
7268 { "rx_64_byte_packets" },
7269 { "rx_65_to_127_byte_packets" },
7270 { "rx_128_to_255_byte_packets" },
7271 { "rx_256_to_511_byte_packets" },
7272 { "rx_512_to_1023_byte_packets" },
7273 { "rx_1024_to_1522_byte_packets" },
7274 { "rx_1523_to_9022_byte_packets" },
7275 { "tx_64_byte_packets" },
7276 { "tx_65_to_127_byte_packets" },
7277 { "tx_128_to_255_byte_packets" },
7278 { "tx_256_to_511_byte_packets" },
7279 { "tx_512_to_1023_byte_packets" },
7280 { "tx_1024_to_1522_byte_packets" },
7281 { "tx_1523_to_9022_byte_packets" },
7282 { "rx_xon_frames" },
7283 { "rx_xoff_frames" },
7284 { "tx_xon_frames" },
7285 { "tx_xoff_frames" },
7286 { "rx_mac_ctrl_frames" },
7287 { "rx_filtered_packets" },
7288 { "rx_ftq_discards" },
7290 { "rx_fw_discards" },
7293 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7294 sizeof(bnx2_stats_str_arr[0]))
7296 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7298 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7299 STATS_OFFSET32(stat_IfHCInOctets_hi),
7300 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7301 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7302 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7303 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7304 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7305 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7306 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7307 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7308 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7309 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7310 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7311 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7312 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7313 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7314 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7315 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7316 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7317 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7318 STATS_OFFSET32(stat_EtherStatsCollisions),
7319 STATS_OFFSET32(stat_EtherStatsFragments),
7320 STATS_OFFSET32(stat_EtherStatsJabbers),
7321 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7322 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7323 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7324 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7325 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7326 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7327 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7328 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7329 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7330 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7331 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7332 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7333 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7334 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7335 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7336 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7337 STATS_OFFSET32(stat_XonPauseFramesReceived),
7338 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7339 STATS_OFFSET32(stat_OutXonSent),
7340 STATS_OFFSET32(stat_OutXoffSent),
7341 STATS_OFFSET32(stat_MacControlFramesReceived),
7342 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7343 STATS_OFFSET32(stat_IfInFTQDiscards),
7344 STATS_OFFSET32(stat_IfInMBUFDiscards),
7345 STATS_OFFSET32(stat_FwRxDrop),
7348 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7349 * skipped because of errata.
7351 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7352 8,0,8,8,8,8,8,8,8,8,
7353 4,0,4,4,4,4,4,4,4,4,
7354 4,4,4,4,4,4,4,4,4,4,
7355 4,4,4,4,4,4,4,4,4,4,
7359 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7360 8,0,8,8,8,8,8,8,8,8,
7361 4,4,4,4,4,4,4,4,4,4,
7362 4,4,4,4,4,4,4,4,4,4,
7363 4,4,4,4,4,4,4,4,4,4,
7367 #define BNX2_NUM_TESTS 6
7370 char string[ETH_GSTRING_LEN];
7371 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7372 { "register_test (offline)" },
7373 { "memory_test (offline)" },
7374 { "loopback_test (offline)" },
7375 { "nvram_test (online)" },
7376 { "interrupt_test (online)" },
7377 { "link_test (online)" },
7381 bnx2_get_sset_count(struct net_device *dev, int sset)
7385 return BNX2_NUM_TESTS;
7387 return BNX2_NUM_STATS;
7394 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7396 struct bnx2 *bp = netdev_priv(dev);
7398 bnx2_set_power_state(bp, PCI_D0);
7400 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7401 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7404 bnx2_netif_stop(bp, true);
7405 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7408 if (bnx2_test_registers(bp) != 0) {
7410 etest->flags |= ETH_TEST_FL_FAILED;
7412 if (bnx2_test_memory(bp) != 0) {
7414 etest->flags |= ETH_TEST_FL_FAILED;
7416 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7417 etest->flags |= ETH_TEST_FL_FAILED;
7419 if (!netif_running(bp->dev))
7420 bnx2_shutdown_chip(bp);
7422 bnx2_init_nic(bp, 1);
7423 bnx2_netif_start(bp, true);
7426 /* wait for link up */
7427 for (i = 0; i < 7; i++) {
7430 msleep_interruptible(1000);
7434 if (bnx2_test_nvram(bp) != 0) {
7436 etest->flags |= ETH_TEST_FL_FAILED;
7438 if (bnx2_test_intr(bp) != 0) {
7440 etest->flags |= ETH_TEST_FL_FAILED;
7443 if (bnx2_test_link(bp) != 0) {
7445 etest->flags |= ETH_TEST_FL_FAILED;
7448 if (!netif_running(bp->dev))
7449 bnx2_set_power_state(bp, PCI_D3hot);
7453 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7455 switch (stringset) {
7457 memcpy(buf, bnx2_stats_str_arr,
7458 sizeof(bnx2_stats_str_arr));
7461 memcpy(buf, bnx2_tests_str_arr,
7462 sizeof(bnx2_tests_str_arr));
7468 bnx2_get_ethtool_stats(struct net_device *dev,
7469 struct ethtool_stats *stats, u64 *buf)
7471 struct bnx2 *bp = netdev_priv(dev);
7473 u32 *hw_stats = (u32 *) bp->stats_blk;
7474 u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7475 u8 *stats_len_arr = NULL;
7477 if (hw_stats == NULL) {
7478 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7482 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7483 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7484 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7485 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7486 stats_len_arr = bnx2_5706_stats_len_arr;
7488 stats_len_arr = bnx2_5708_stats_len_arr;
7490 for (i = 0; i < BNX2_NUM_STATS; i++) {
7491 unsigned long offset;
7493 if (stats_len_arr[i] == 0) {
7494 /* skip this counter */
7499 offset = bnx2_stats_offset_arr[i];
7500 if (stats_len_arr[i] == 4) {
7501 /* 4-byte counter */
7502 buf[i] = (u64) *(hw_stats + offset) +
7503 *(temp_stats + offset);
7506 /* 8-byte counter */
7507 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7508 *(hw_stats + offset + 1) +
7509 (((u64) *(temp_stats + offset)) << 32) +
7510 *(temp_stats + offset + 1);
7515 bnx2_phys_id(struct net_device *dev, u32 data)
7517 struct bnx2 *bp = netdev_priv(dev);
7521 bnx2_set_power_state(bp, PCI_D0);
7526 save = REG_RD(bp, BNX2_MISC_CFG);
7527 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7529 for (i = 0; i < (data * 2); i++) {
7531 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7534 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7535 BNX2_EMAC_LED_1000MB_OVERRIDE |
7536 BNX2_EMAC_LED_100MB_OVERRIDE |
7537 BNX2_EMAC_LED_10MB_OVERRIDE |
7538 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7539 BNX2_EMAC_LED_TRAFFIC);
7541 msleep_interruptible(500);
7542 if (signal_pending(current))
7545 REG_WR(bp, BNX2_EMAC_LED, 0);
7546 REG_WR(bp, BNX2_MISC_CFG, save);
7548 if (!netif_running(dev))
7549 bnx2_set_power_state(bp, PCI_D3hot);
7555 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7557 struct bnx2 *bp = netdev_priv(dev);
7559 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7560 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7562 return (ethtool_op_set_tx_csum(dev, data));
7566 bnx2_set_flags(struct net_device *dev, u32 data)
7568 return ethtool_op_set_flags(dev, data, ETH_FLAG_RXHASH);
7571 static const struct ethtool_ops bnx2_ethtool_ops = {
7572 .get_settings = bnx2_get_settings,
7573 .set_settings = bnx2_set_settings,
7574 .get_drvinfo = bnx2_get_drvinfo,
7575 .get_regs_len = bnx2_get_regs_len,
7576 .get_regs = bnx2_get_regs,
7577 .get_wol = bnx2_get_wol,
7578 .set_wol = bnx2_set_wol,
7579 .nway_reset = bnx2_nway_reset,
7580 .get_link = bnx2_get_link,
7581 .get_eeprom_len = bnx2_get_eeprom_len,
7582 .get_eeprom = bnx2_get_eeprom,
7583 .set_eeprom = bnx2_set_eeprom,
7584 .get_coalesce = bnx2_get_coalesce,
7585 .set_coalesce = bnx2_set_coalesce,
7586 .get_ringparam = bnx2_get_ringparam,
7587 .set_ringparam = bnx2_set_ringparam,
7588 .get_pauseparam = bnx2_get_pauseparam,
7589 .set_pauseparam = bnx2_set_pauseparam,
7590 .get_rx_csum = bnx2_get_rx_csum,
7591 .set_rx_csum = bnx2_set_rx_csum,
7592 .set_tx_csum = bnx2_set_tx_csum,
7593 .set_sg = ethtool_op_set_sg,
7594 .set_tso = bnx2_set_tso,
7595 .self_test = bnx2_self_test,
7596 .get_strings = bnx2_get_strings,
7597 .phys_id = bnx2_phys_id,
7598 .get_ethtool_stats = bnx2_get_ethtool_stats,
7599 .get_sset_count = bnx2_get_sset_count,
7600 .set_flags = bnx2_set_flags,
7601 .get_flags = ethtool_op_get_flags,
7604 /* Called with rtnl_lock */
7606 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7608 struct mii_ioctl_data *data = if_mii(ifr);
7609 struct bnx2 *bp = netdev_priv(dev);
7614 data->phy_id = bp->phy_addr;
7620 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7623 if (!netif_running(dev))
7626 spin_lock_bh(&bp->phy_lock);
7627 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7628 spin_unlock_bh(&bp->phy_lock);
7630 data->val_out = mii_regval;
7636 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7639 if (!netif_running(dev))
7642 spin_lock_bh(&bp->phy_lock);
7643 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7644 spin_unlock_bh(&bp->phy_lock);
7655 /* Called with rtnl_lock */
7657 bnx2_change_mac_addr(struct net_device *dev, void *p)
7659 struct sockaddr *addr = p;
7660 struct bnx2 *bp = netdev_priv(dev);
7662 if (!is_valid_ether_addr(addr->sa_data))
7665 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7666 if (netif_running(dev))
7667 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7672 /* Called with rtnl_lock */
7674 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7676 struct bnx2 *bp = netdev_priv(dev);
7678 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7679 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7683 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7686 #ifdef CONFIG_NET_POLL_CONTROLLER
7688 poll_bnx2(struct net_device *dev)
7690 struct bnx2 *bp = netdev_priv(dev);
7693 for (i = 0; i < bp->irq_nvecs; i++) {
7694 struct bnx2_irq *irq = &bp->irq_tbl[i];
7696 disable_irq(irq->vector);
7697 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7698 enable_irq(irq->vector);
7703 static void __devinit
7704 bnx2_get_5709_media(struct bnx2 *bp)
7706 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7707 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7710 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7712 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7713 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7717 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7718 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7720 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7722 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7727 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7735 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7741 static void __devinit
7742 bnx2_get_pci_speed(struct bnx2 *bp)
7746 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7747 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7750 bp->flags |= BNX2_FLAG_PCIX;
7752 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7754 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7756 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7757 bp->bus_speed_mhz = 133;
7760 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7761 bp->bus_speed_mhz = 100;
7764 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7765 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7766 bp->bus_speed_mhz = 66;
7769 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7770 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7771 bp->bus_speed_mhz = 50;
7774 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7775 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7776 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7777 bp->bus_speed_mhz = 33;
7782 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7783 bp->bus_speed_mhz = 66;
7785 bp->bus_speed_mhz = 33;
7788 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7789 bp->flags |= BNX2_FLAG_PCI_32BIT;
7793 static void __devinit
7794 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7798 unsigned int block_end, rosize, len;
7800 #define BNX2_VPD_NVRAM_OFFSET 0x300
7801 #define BNX2_VPD_LEN 128
7802 #define BNX2_MAX_VER_SLEN 30
7804 data = kmalloc(256, GFP_KERNEL);
7808 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7813 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7814 data[i] = data[i + BNX2_VPD_LEN + 3];
7815 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7816 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7817 data[i + 3] = data[i + BNX2_VPD_LEN];
7820 i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7824 rosize = pci_vpd_lrdt_size(&data[i]);
7825 i += PCI_VPD_LRDT_TAG_SIZE;
7826 block_end = i + rosize;
7828 if (block_end > BNX2_VPD_LEN)
7831 j = pci_vpd_find_info_keyword(data, i, rosize,
7832 PCI_VPD_RO_KEYWORD_MFR_ID);
7836 len = pci_vpd_info_field_size(&data[j]);
7838 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7839 if (j + len > block_end || len != 4 ||
7840 memcmp(&data[j], "1028", 4))
7843 j = pci_vpd_find_info_keyword(data, i, rosize,
7844 PCI_VPD_RO_KEYWORD_VENDOR0);
7848 len = pci_vpd_info_field_size(&data[j]);
7850 j += PCI_VPD_INFO_FLD_HDR_SIZE;
7851 if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
7854 memcpy(bp->fw_version, &data[j], len);
7855 bp->fw_version[len] = ' ';
7861 static int __devinit
7862 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7865 unsigned long mem_len;
7868 u64 dma_mask, persist_dma_mask;
7870 SET_NETDEV_DEV(dev, &pdev->dev);
7871 bp = netdev_priv(dev);
7876 bp->temp_stats_blk =
7877 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7879 if (bp->temp_stats_blk == NULL) {
7884 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7885 rc = pci_enable_device(pdev);
7887 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7891 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7893 "Cannot find PCI device base address, aborting\n");
7895 goto err_out_disable;
7898 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7900 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7901 goto err_out_disable;
7904 pci_set_master(pdev);
7905 pci_save_state(pdev);
7907 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7908 if (bp->pm_cap == 0) {
7910 "Cannot find power management capability, aborting\n");
7912 goto err_out_release;
7918 spin_lock_init(&bp->phy_lock);
7919 spin_lock_init(&bp->indirect_lock);
7921 mutex_init(&bp->cnic_lock);
7923 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7925 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7926 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7927 dev->mem_end = dev->mem_start + mem_len;
7928 dev->irq = pdev->irq;
7930 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7933 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
7935 goto err_out_release;
7938 /* Configure byte swap and enable write to the reg_window registers.
7939 * Rely on CPU to do target byte swapping on big endian systems
7940 * The chip's target access swapping will not swap all accesses
7942 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7943 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7944 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7946 bnx2_set_power_state(bp, PCI_D0);
7948 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7950 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7951 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7953 "Cannot find PCIE capability, aborting\n");
7957 bp->flags |= BNX2_FLAG_PCIE;
7958 if (CHIP_REV(bp) == CHIP_REV_Ax)
7959 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7961 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7962 if (bp->pcix_cap == 0) {
7964 "Cannot find PCIX capability, aborting\n");
7968 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7971 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7972 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7973 bp->flags |= BNX2_FLAG_MSIX_CAP;
7976 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7977 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7978 bp->flags |= BNX2_FLAG_MSI_CAP;
7981 /* 5708 cannot support DMA addresses > 40-bit. */
7982 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7983 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7985 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7987 /* Configure DMA attributes. */
7988 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7989 dev->features |= NETIF_F_HIGHDMA;
7990 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7993 "pci_set_consistent_dma_mask failed, aborting\n");
7996 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7997 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
8001 if (!(bp->flags & BNX2_FLAG_PCIE))
8002 bnx2_get_pci_speed(bp);
8004 /* 5706A0 may falsely detect SERR and PERR. */
8005 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8006 reg = REG_RD(bp, PCI_COMMAND);
8007 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
8008 REG_WR(bp, PCI_COMMAND, reg);
8010 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
8011 !(bp->flags & BNX2_FLAG_PCIX)) {
8014 "5706 A1 can only be used in a PCIX bus, aborting\n");
8018 bnx2_init_nvram(bp);
8020 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
8022 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
8023 BNX2_SHM_HDR_SIGNATURE_SIG) {
8024 u32 off = PCI_FUNC(pdev->devfn) << 2;
8026 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8028 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8030 /* Get the permanent MAC address. First we need to make sure the
8031 * firmware is actually running.
8033 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8035 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8036 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
8037 dev_err(&pdev->dev, "Firmware not running, aborting\n");
8042 bnx2_read_vpd_fw_ver(bp);
8044 j = strlen(bp->fw_version);
8045 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8046 for (i = 0; i < 3 && j < 24; i++) {
8050 bp->fw_version[j++] = 'b';
8051 bp->fw_version[j++] = 'c';
8052 bp->fw_version[j++] = ' ';
8054 num = (u8) (reg >> (24 - (i * 8)));
8055 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8056 if (num >= k || !skip0 || k == 1) {
8057 bp->fw_version[j++] = (num / k) + '0';
8062 bp->fw_version[j++] = '.';
8064 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8065 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8068 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8069 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8071 for (i = 0; i < 30; i++) {
8072 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8073 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8078 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8079 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8080 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8081 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8082 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8085 bp->fw_version[j++] = ' ';
8086 for (i = 0; i < 3 && j < 28; i++) {
8087 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8089 memcpy(&bp->fw_version[j], ®, 4);
8094 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8095 bp->mac_addr[0] = (u8) (reg >> 8);
8096 bp->mac_addr[1] = (u8) reg;
8098 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8099 bp->mac_addr[2] = (u8) (reg >> 24);
8100 bp->mac_addr[3] = (u8) (reg >> 16);
8101 bp->mac_addr[4] = (u8) (reg >> 8);
8102 bp->mac_addr[5] = (u8) reg;
8104 bp->tx_ring_size = MAX_TX_DESC_CNT;
8105 bnx2_set_rx_ring_size(bp, 255);
8109 bp->tx_quick_cons_trip_int = 2;
8110 bp->tx_quick_cons_trip = 20;
8111 bp->tx_ticks_int = 18;
8114 bp->rx_quick_cons_trip_int = 2;
8115 bp->rx_quick_cons_trip = 12;
8116 bp->rx_ticks_int = 18;
8119 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8121 bp->current_interval = BNX2_TIMER_INTERVAL;
8125 /* Disable WOL support if we are running on a SERDES chip. */
8126 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8127 bnx2_get_5709_media(bp);
8128 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8129 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8131 bp->phy_port = PORT_TP;
8132 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8133 bp->phy_port = PORT_FIBRE;
8134 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8135 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8136 bp->flags |= BNX2_FLAG_NO_WOL;
8139 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8140 /* Don't do parallel detect on this board because of
8141 * some board problems. The link will not go down
8142 * if we do parallel detect.
8144 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8145 pdev->subsystem_device == 0x310c)
8146 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8149 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8150 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8152 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8153 CHIP_NUM(bp) == CHIP_NUM_5708)
8154 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8155 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8156 (CHIP_REV(bp) == CHIP_REV_Ax ||
8157 CHIP_REV(bp) == CHIP_REV_Bx))
8158 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8160 bnx2_init_fw_cap(bp);
8162 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8163 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8164 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8165 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8166 bp->flags |= BNX2_FLAG_NO_WOL;
8170 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8171 bp->tx_quick_cons_trip_int =
8172 bp->tx_quick_cons_trip;
8173 bp->tx_ticks_int = bp->tx_ticks;
8174 bp->rx_quick_cons_trip_int =
8175 bp->rx_quick_cons_trip;
8176 bp->rx_ticks_int = bp->rx_ticks;
8177 bp->comp_prod_trip_int = bp->comp_prod_trip;
8178 bp->com_ticks_int = bp->com_ticks;
8179 bp->cmd_ticks_int = bp->cmd_ticks;
8182 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8184 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8185 * with byte enables disabled on the unused 32-bit word. This is legal
8186 * but causes problems on the AMD 8132 which will eventually stop
8187 * responding after a while.
8189 * AMD believes this incompatibility is unique to the 5706, and
8190 * prefers to locally disable MSI rather than globally disabling it.
8192 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8193 struct pci_dev *amd_8132 = NULL;
8195 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8196 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8199 if (amd_8132->revision >= 0x10 &&
8200 amd_8132->revision <= 0x13) {
8202 pci_dev_put(amd_8132);
8208 bnx2_set_default_link(bp);
8209 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8211 init_timer(&bp->timer);
8212 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8213 bp->timer.data = (unsigned long) bp;
8214 bp->timer.function = bnx2_timer;
8220 iounmap(bp->regview);
8225 pci_release_regions(pdev);
8228 pci_disable_device(pdev);
8229 pci_set_drvdata(pdev, NULL);
8235 static char * __devinit
8236 bnx2_bus_string(struct bnx2 *bp, char *str)
8240 if (bp->flags & BNX2_FLAG_PCIE) {
8241 s += sprintf(s, "PCI Express");
8243 s += sprintf(s, "PCI");
8244 if (bp->flags & BNX2_FLAG_PCIX)
8245 s += sprintf(s, "-X");
8246 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8247 s += sprintf(s, " 32-bit");
8249 s += sprintf(s, " 64-bit");
8250 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8256 bnx2_del_napi(struct bnx2 *bp)
8260 for (i = 0; i < bp->irq_nvecs; i++)
8261 netif_napi_del(&bp->bnx2_napi[i].napi);
8265 bnx2_init_napi(struct bnx2 *bp)
8269 for (i = 0; i < bp->irq_nvecs; i++) {
8270 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8271 int (*poll)(struct napi_struct *, int);
8276 poll = bnx2_poll_msix;
8278 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8283 static const struct net_device_ops bnx2_netdev_ops = {
8284 .ndo_open = bnx2_open,
8285 .ndo_start_xmit = bnx2_start_xmit,
8286 .ndo_stop = bnx2_close,
8287 .ndo_get_stats = bnx2_get_stats,
8288 .ndo_set_rx_mode = bnx2_set_rx_mode,
8289 .ndo_do_ioctl = bnx2_ioctl,
8290 .ndo_validate_addr = eth_validate_addr,
8291 .ndo_set_mac_address = bnx2_change_mac_addr,
8292 .ndo_change_mtu = bnx2_change_mtu,
8293 .ndo_tx_timeout = bnx2_tx_timeout,
8295 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8297 #ifdef CONFIG_NET_POLL_CONTROLLER
8298 .ndo_poll_controller = poll_bnx2,
8302 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8305 dev->vlan_features |= flags;
8309 static int __devinit
8310 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8312 static int version_printed = 0;
8313 struct net_device *dev = NULL;
8318 if (version_printed++ == 0)
8319 pr_info("%s", version);
8321 /* dev zeroed in init_etherdev */
8322 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8327 rc = bnx2_init_board(pdev, dev);
8333 dev->netdev_ops = &bnx2_netdev_ops;
8334 dev->watchdog_timeo = TX_TIMEOUT;
8335 dev->ethtool_ops = &bnx2_ethtool_ops;
8337 bp = netdev_priv(dev);
8339 pci_set_drvdata(pdev, dev);
8341 rc = bnx2_request_firmware(bp);
8345 memcpy(dev->dev_addr, bp->mac_addr, 6);
8346 memcpy(dev->perm_addr, bp->mac_addr, 6);
8348 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO |
8350 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8351 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8352 dev->features |= NETIF_F_IPV6_CSUM;
8353 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8356 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8358 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8359 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8360 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8361 dev->features |= NETIF_F_TSO6;
8362 vlan_features_add(dev, NETIF_F_TSO6);
8364 if ((rc = register_netdev(dev))) {
8365 dev_err(&pdev->dev, "Cannot register net device\n");
8369 netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8370 board_info[ent->driver_data].name,
8371 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8372 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8373 bnx2_bus_string(bp, str),
8375 bp->pdev->irq, dev->dev_addr);
8380 if (bp->mips_firmware)
8381 release_firmware(bp->mips_firmware);
8382 if (bp->rv2p_firmware)
8383 release_firmware(bp->rv2p_firmware);
8386 iounmap(bp->regview);
8387 pci_release_regions(pdev);
8388 pci_disable_device(pdev);
8389 pci_set_drvdata(pdev, NULL);
8394 static void __devexit
8395 bnx2_remove_one(struct pci_dev *pdev)
8397 struct net_device *dev = pci_get_drvdata(pdev);
8398 struct bnx2 *bp = netdev_priv(dev);
8400 flush_scheduled_work();
8402 unregister_netdev(dev);
8404 if (bp->mips_firmware)
8405 release_firmware(bp->mips_firmware);
8406 if (bp->rv2p_firmware)
8407 release_firmware(bp->rv2p_firmware);
8410 iounmap(bp->regview);
8412 kfree(bp->temp_stats_blk);
8415 pci_release_regions(pdev);
8416 pci_disable_device(pdev);
8417 pci_set_drvdata(pdev, NULL);
8421 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8423 struct net_device *dev = pci_get_drvdata(pdev);
8424 struct bnx2 *bp = netdev_priv(dev);
8426 /* PCI register 4 needs to be saved whether netif_running() or not.
8427 * MSI address and data need to be saved if using MSI and
8430 pci_save_state(pdev);
8431 if (!netif_running(dev))
8434 flush_scheduled_work();
8435 bnx2_netif_stop(bp, true);
8436 netif_device_detach(dev);
8437 del_timer_sync(&bp->timer);
8438 bnx2_shutdown_chip(bp);
8440 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8445 bnx2_resume(struct pci_dev *pdev)
8447 struct net_device *dev = pci_get_drvdata(pdev);
8448 struct bnx2 *bp = netdev_priv(dev);
8450 pci_restore_state(pdev);
8451 if (!netif_running(dev))
8454 bnx2_set_power_state(bp, PCI_D0);
8455 netif_device_attach(dev);
8456 bnx2_init_nic(bp, 1);
8457 bnx2_netif_start(bp, true);
8462 * bnx2_io_error_detected - called when PCI error is detected
8463 * @pdev: Pointer to PCI device
8464 * @state: The current pci connection state
8466 * This function is called after a PCI bus error affecting
8467 * this device has been detected.
8469 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8470 pci_channel_state_t state)
8472 struct net_device *dev = pci_get_drvdata(pdev);
8473 struct bnx2 *bp = netdev_priv(dev);
8476 netif_device_detach(dev);
8478 if (state == pci_channel_io_perm_failure) {
8480 return PCI_ERS_RESULT_DISCONNECT;
8483 if (netif_running(dev)) {
8484 bnx2_netif_stop(bp, true);
8485 del_timer_sync(&bp->timer);
8486 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8489 pci_disable_device(pdev);
8492 /* Request a slot slot reset. */
8493 return PCI_ERS_RESULT_NEED_RESET;
8497 * bnx2_io_slot_reset - called after the pci bus has been reset.
8498 * @pdev: Pointer to PCI device
8500 * Restart the card from scratch, as if from a cold-boot.
8502 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8504 struct net_device *dev = pci_get_drvdata(pdev);
8505 struct bnx2 *bp = netdev_priv(dev);
8508 if (pci_enable_device(pdev)) {
8510 "Cannot re-enable PCI device after reset\n");
8512 return PCI_ERS_RESULT_DISCONNECT;
8514 pci_set_master(pdev);
8515 pci_restore_state(pdev);
8516 pci_save_state(pdev);
8518 if (netif_running(dev)) {
8519 bnx2_set_power_state(bp, PCI_D0);
8520 bnx2_init_nic(bp, 1);
8524 return PCI_ERS_RESULT_RECOVERED;
8528 * bnx2_io_resume - called when traffic can start flowing again.
8529 * @pdev: Pointer to PCI device
8531 * This callback is called when the error recovery driver tells us that
8532 * its OK to resume normal operation.
8534 static void bnx2_io_resume(struct pci_dev *pdev)
8536 struct net_device *dev = pci_get_drvdata(pdev);
8537 struct bnx2 *bp = netdev_priv(dev);
8540 if (netif_running(dev))
8541 bnx2_netif_start(bp, true);
8543 netif_device_attach(dev);
8547 static struct pci_error_handlers bnx2_err_handler = {
8548 .error_detected = bnx2_io_error_detected,
8549 .slot_reset = bnx2_io_slot_reset,
8550 .resume = bnx2_io_resume,
8553 static struct pci_driver bnx2_pci_driver = {
8554 .name = DRV_MODULE_NAME,
8555 .id_table = bnx2_pci_tbl,
8556 .probe = bnx2_init_one,
8557 .remove = __devexit_p(bnx2_remove_one),
8558 .suspend = bnx2_suspend,
8559 .resume = bnx2_resume,
8560 .err_handler = &bnx2_err_handler,
8563 static int __init bnx2_init(void)
8565 return pci_register_driver(&bnx2_pci_driver);
8568 static void __exit bnx2_cleanup(void)
8570 pci_unregister_driver(&bnx2_pci_driver);
8573 module_init(bnx2_init);
8574 module_exit(bnx2_cleanup);