drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004-2010 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/timer.h>
  19 #include <linux/errno.h>
  20 #include <linux/ioport.h>
  21 #include <linux/slab.h>
  22 #include <linux/vmalloc.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/pci.h>
  25 #include <linux/init.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/skbuff.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/bitops.h>
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33 #include <linux/delay.h>
  34 #include <asm/byteorder.h>
  35 #include <asm/page.h>
  36 #include <linux/time.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/mii.h>
  39 #include <linux/if_vlan.h>
  40 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  41 #define BCM_VLAN 1
  42 #endif
  43 #include <net/ip.h>
  44 #include <net/tcp.h>
  45 #include <net/checksum.h>
  46 #include <linux/workqueue.h>
  47 #include <linux/crc32.h>
  48 #include <linux/prefetch.h>
  49 #include <linux/cache.h>
  50 #include <linux/firmware.h>
  51 #include <linux/log2.h>
  52
  53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
  54 #define BCM_CNIC 1
  55 #include "cnic_if.h"
  56 #endif
  57 #include "bnx2.h"
  58 #include "bnx2_fw.h"
  59
  60 #define DRV_MODULE_NAME         "bnx2"
  61 #define DRV_MODULE_VERSION      "2.0.15"
  62 #define DRV_MODULE_RELDATE      "May 4, 2010"
  63 #define FW_MIPS_FILE_06         "bnx2/bnx2-mips-06-5.0.0.j6.fw"
  64 #define FW_RV2P_FILE_06         "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
  65 #define FW_MIPS_FILE_09         "bnx2/bnx2-mips-09-5.0.0.j15.fw"
  66 #define FW_RV2P_FILE_09_Ax      "bnx2/bnx2-rv2p-09ax-5.0.0.j10.fw"
  67 #define FW_RV2P_FILE_09         "bnx2/bnx2-rv2p-09-5.0.0.j10.fw"
  68
  69 #define RUN_AT(x) (jiffies + (x))
  70
  71 /* Time in jiffies before concluding the transmitter is hung. */
  72 #define TX_TIMEOUT  (5*HZ)
  73
  74 static char version[] __devinitdata =
  75         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  76
  77 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  78 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
  79 MODULE_LICENSE("GPL");
  80 MODULE_VERSION(DRV_MODULE_VERSION);
  81 MODULE_FIRMWARE(FW_MIPS_FILE_06);
  82 MODULE_FIRMWARE(FW_RV2P_FILE_06);
  83 MODULE_FIRMWARE(FW_MIPS_FILE_09);
  84 MODULE_FIRMWARE(FW_RV2P_FILE_09);
  85 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
  86
  87 static int disable_msi = 0;
  88
  89 module_param(disable_msi, int, 0);
  90 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  91
  92 typedef enum {
  93         BCM5706 = 0,
  94         NC370T,
  95         NC370I,
  96         BCM5706S,
  97         NC370F,
  98         BCM5708,
  99         BCM5708S,
 100         BCM5709,
 101         BCM5709S,
 102         BCM5716,
 103         BCM5716S,
 104 } board_t;
 105
 106 /* indexed by board_t, above */
 107 static struct {
 108         char *name;
 109 } board_info[] __devinitdata = {
 110         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
 111         { "HP NC370T Multifunction Gigabit Server Adapter" },
 112         { "HP NC370i Multifunction Gigabit Server Adapter" },
 113         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 114         { "HP NC370F Multifunction Gigabit Server Adapter" },
 115         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 116         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 117         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 118         { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 119         { "Broadcom NetXtreme II BCM5716 1000Base-T" },
 120         { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
 121         };
 122
 123 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
 124         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 125           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 126         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 127           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 128         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 129           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 130         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 131           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 132         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 133           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 134         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 135           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 136         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 137           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 138         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 139           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 140         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
 141           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
 142         { PCI_VENDOR_ID_BROADCOM, 0x163b,
 143           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
 144         { PCI_VENDOR_ID_BROADCOM, 0x163c,
 145           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
 146         { 0, }
 147 };
 148
 149 static const struct flash_spec flash_table[] =
 150 {
 151 #define BUFFERED_FLAGS          (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
 152 #define NONBUFFERED_FLAGS       (BNX2_NV_WREN)
 153         /* Slow EEPROM */
 154         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 155          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 156          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 157          "EEPROM - slow"},
 158         /* Expansion entry 0001 */
 159         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 160          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 161          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 162          "Entry 0001"},
 163         /* Saifun SA25F010 (non-buffered flash) */
 164         /* strap, cfg1, & write1 need updates */
 165         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 166          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 167          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 168          "Non-buffered flash (128kB)"},
 169         /* Saifun SA25F020 (non-buffered flash) */
 170         /* strap, cfg1, & write1 need updates */
 171         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 172          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 173          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 174          "Non-buffered flash (256kB)"},
 175         /* Expansion entry 0100 */
 176         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 177          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 178          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 179          "Entry 0100"},
 180         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 181         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 183          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 184          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 185         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 186         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 187          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 188          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 189          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 190         /* Saifun SA25F005 (non-buffered flash) */
 191         /* strap, cfg1, & write1 need updates */
 192         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 193          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 194          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 195          "Non-buffered flash (64kB)"},
 196         /* Fast EEPROM */
 197         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 198          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 199          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 200          "EEPROM - fast"},
 201         /* Expansion entry 1001 */
 202         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 204          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 205          "Entry 1001"},
 206         /* Expansion entry 1010 */
 207         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 208          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 209          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 210          "Entry 1010"},
 211         /* ATMEL AT45DB011B (buffered flash) */
 212         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 213          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 214          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 215          "Buffered flash (128kB)"},
 216         /* Expansion entry 1100 */
 217         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 218          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 219          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 220          "Entry 1100"},
 221         /* Expansion entry 1101 */
 222         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 223          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 224          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 225          "Entry 1101"},
 226         /* Ateml Expansion entry 1110 */
 227         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 228          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 229          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 230          "Entry 1110 (Atmel)"},
 231         /* ATMEL AT45DB021B (buffered flash) */
 232         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 233          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 234          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 235          "Buffered flash (256kB)"},
 236 };
 237
 238 static const struct flash_spec flash_5709 = {
 239         .flags          = BNX2_NV_BUFFERED,
 240         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 241         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 242         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 243         .total_size     = BUFFERED_FLASH_TOTAL_SIZE*2,
 244         .name           = "5709 Buffered flash (256kB)",
 245 };
 246
 247 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 248
 249 static void bnx2_init_napi(struct bnx2 *bp);
 250 static void bnx2_del_napi(struct bnx2 *bp);
 251
 252 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
 253 {
 254         u32 diff;
 255
 256         smp_mb();
 257
 258         /* The ring uses 256 indices for 255 entries, one of them
 259          * needs to be skipped.
 260          */
 261         diff = txr->tx_prod - txr->tx_cons;
 262         if (unlikely(diff >= TX_DESC_CNT)) {
 263                 diff &= 0xffff;
 264                 if (diff == TX_DESC_CNT)
 265                         diff = MAX_TX_DESC_CNT;
 266         }
 267         return (bp->tx_ring_size - diff);
 268 }
 269
 270 static u32
 271 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 272 {
 273         u32 val;
 274
 275         spin_lock_bh(&bp->indirect_lock);
 276         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 277         val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
 278         spin_unlock_bh(&bp->indirect_lock);
 279         return val;
 280 }
 281
 282 static void
 283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 284 {
 285         spin_lock_bh(&bp->indirect_lock);
 286         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 287         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 288         spin_unlock_bh(&bp->indirect_lock);
 289 }
 290
 291 static void
 292 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
 293 {
 294         bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
 295 }
 296
 297 static u32
 298 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
 299 {
 300         return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
 301 }
 302
 303 static void
 304 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 305 {
 306         offset += cid_addr;
 307         spin_lock_bh(&bp->indirect_lock);
 308         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 309                 int i;
 310
 311                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 312                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 313                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 314                 for (i = 0; i < 5; i++) {
 315                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 316                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 317                                 break;
 318                         udelay(5);
 319                 }
 320         } else {
 321                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 322                 REG_WR(bp, BNX2_CTX_DATA, val);
 323         }
 324         spin_unlock_bh(&bp->indirect_lock);
 325 }
 326
 327 #ifdef BCM_CNIC
 328 static int
 329 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
 330 {
 331         struct bnx2 *bp = netdev_priv(dev);
 332         struct drv_ctl_io *io = &info->data.io;
 333
 334         switch (info->cmd) {
 335         case DRV_CTL_IO_WR_CMD:
 336                 bnx2_reg_wr_ind(bp, io->offset, io->data);
 337                 break;
 338         case DRV_CTL_IO_RD_CMD:
 339                 io->data = bnx2_reg_rd_ind(bp, io->offset);
 340                 break;
 341         case DRV_CTL_CTX_WR_CMD:
 342                 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
 343                 break;
 344         default:
 345                 return -EINVAL;
 346         }
 347         return 0;
 348 }
 349
 350 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
 351 {
 352         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 353         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 354         int sb_id;
 355
 356         if (bp->flags & BNX2_FLAG_USING_MSIX) {
 357                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
 358                 bnapi->cnic_present = 0;
 359                 sb_id = bp->irq_nvecs;
 360                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
 361         } else {
 362                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
 363                 bnapi->cnic_tag = bnapi->last_status_idx;
 364                 bnapi->cnic_present = 1;
 365                 sb_id = 0;
 366                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
 367         }
 368
 369         cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
 370         cp->irq_arr[0].status_blk = (void *)
 371                 ((unsigned long) bnapi->status_blk.msi +
 372                 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
 373         cp->irq_arr[0].status_blk_num = sb_id;
 374         cp->num_irq = 1;
 375 }
 376
 377 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
 378                               void *data)
 379 {
 380         struct bnx2 *bp = netdev_priv(dev);
 381         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 382
 383         if (ops == NULL)
 384                 return -EINVAL;
 385
 386         if (cp->drv_state & CNIC_DRV_STATE_REGD)
 387                 return -EBUSY;
 388
 389         bp->cnic_data = data;
 390         rcu_assign_pointer(bp->cnic_ops, ops);
 391
 392         cp->num_irq = 0;
 393         cp->drv_state = CNIC_DRV_STATE_REGD;
 394
 395         bnx2_setup_cnic_irq_info(bp);
 396
 397         return 0;
 398 }
 399
 400 static int bnx2_unregister_cnic(struct net_device *dev)
 401 {
 402         struct bnx2 *bp = netdev_priv(dev);
 403         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 404         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 405
 406         mutex_lock(&bp->cnic_lock);
 407         cp->drv_state = 0;
 408         bnapi->cnic_present = 0;
 409         rcu_assign_pointer(bp->cnic_ops, NULL);
 410         mutex_unlock(&bp->cnic_lock);
 411         synchronize_rcu();
 412         return 0;
 413 }
 414
 415 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
 416 {
 417         struct bnx2 *bp = netdev_priv(dev);
 418         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
 419
 420         cp->drv_owner = THIS_MODULE;
 421         cp->chip_id = bp->chip_id;
 422         cp->pdev = bp->pdev;
 423         cp->io_base = bp->regview;
 424         cp->drv_ctl = bnx2_drv_ctl;
 425         cp->drv_register_cnic = bnx2_register_cnic;
 426         cp->drv_unregister_cnic = bnx2_unregister_cnic;
 427
 428         return cp;
 429 }
 430 EXPORT_SYMBOL(bnx2_cnic_probe);
 431
 432 static void
 433 bnx2_cnic_stop(struct bnx2 *bp)
 434 {
 435         struct cnic_ops *c_ops;
 436         struct cnic_ctl_info info;
 437
 438         mutex_lock(&bp->cnic_lock);
 439         c_ops = bp->cnic_ops;
 440         if (c_ops) {
 441                 info.cmd = CNIC_CTL_STOP_CMD;
 442                 c_ops->cnic_ctl(bp->cnic_data, &info);
 443         }
 444         mutex_unlock(&bp->cnic_lock);
 445 }
 446
 447 static void
 448 bnx2_cnic_start(struct bnx2 *bp)
 449 {
 450         struct cnic_ops *c_ops;
 451         struct cnic_ctl_info info;
 452
 453         mutex_lock(&bp->cnic_lock);
 454         c_ops = bp->cnic_ops;
 455         if (c_ops) {
 456                 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
 457                         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 458
 459                         bnapi->cnic_tag = bnapi->last_status_idx;
 460                 }
 461                 info.cmd = CNIC_CTL_START_CMD;
 462                 c_ops->cnic_ctl(bp->cnic_data, &info);
 463         }
 464         mutex_unlock(&bp->cnic_lock);
 465 }
 466
 467 #else
 468
 469 static void
 470 bnx2_cnic_stop(struct bnx2 *bp)
 471 {
 472 }
 473
 474 static void
 475 bnx2_cnic_start(struct bnx2 *bp)
 476 {
 477 }
 478
 479 #endif
 480
 481 static int
 482 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 483 {
 484         u32 val1;
 485         int i, ret;
 486
 487         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 488                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 489                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 490
 491                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 492                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 493
 494                 udelay(40);
 495         }
 496
 497         val1 = (bp->phy_addr << 21) | (reg << 16) |
 498                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 499                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 500         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 501
 502         for (i = 0; i < 50; i++) {
 503                 udelay(10);
 504
 505                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 506                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 507                         udelay(5);
 508
 509                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 510                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 511
 512                         break;
 513                 }
 514         }
 515
 516         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 517                 *val = 0x0;
 518                 ret = -EBUSY;
 519         }
 520         else {
 521                 *val = val1;
 522                 ret = 0;
 523         }
 524
 525         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 526                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 527                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 528
 529                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 530                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 531
 532                 udelay(40);
 533         }
 534
 535         return ret;
 536 }
 537
 538 static int
 539 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 540 {
 541         u32 val1;
 542         int i, ret;
 543
 544         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 545                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 546                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 547
 548                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 549                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 550
 551                 udelay(40);
 552         }
 553
 554         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 555                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 556                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 557         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 558
 559         for (i = 0; i < 50; i++) {
 560                 udelay(10);
 561
 562                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 563                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 564                         udelay(5);
 565                         break;
 566                 }
 567         }
 568
 569         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 570                 ret = -EBUSY;
 571         else
 572                 ret = 0;
 573
 574         if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
 575                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 576                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 577
 578                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 579                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 580
 581                 udelay(40);
 582         }
 583
 584         return ret;
 585 }
 586
 587 static void
 588 bnx2_disable_int(struct bnx2 *bp)
 589 {
 590         int i;
 591         struct bnx2_napi *bnapi;
 592
 593         for (i = 0; i < bp->irq_nvecs; i++) {
 594                 bnapi = &bp->bnx2_napi[i];
 595                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 596                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 597         }
 598         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 599 }
 600
 601 static void
 602 bnx2_enable_int(struct bnx2 *bp)
 603 {
 604         int i;
 605         struct bnx2_napi *bnapi;
 606
 607         for (i = 0; i < bp->irq_nvecs; i++) {
 608                 bnapi = &bp->bnx2_napi[i];
 609
 610                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 611                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 612                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
 613                        bnapi->last_status_idx);
 614
 615                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
 616                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 617                        bnapi->last_status_idx);
 618         }
 619         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 620 }
 621
 622 static void
 623 bnx2_disable_int_sync(struct bnx2 *bp)
 624 {
 625         int i;
 626
 627         atomic_inc(&bp->intr_sem);
 628         if (!netif_running(bp->dev))
 629                 return;
 630
 631         bnx2_disable_int(bp);
 632         for (i = 0; i < bp->irq_nvecs; i++)
 633                 synchronize_irq(bp->irq_tbl[i].vector);
 634 }
 635
 636 static void
 637 bnx2_napi_disable(struct bnx2 *bp)
 638 {
 639         int i;
 640
 641         for (i = 0; i < bp->irq_nvecs; i++)
 642                 napi_disable(&bp->bnx2_napi[i].napi);
 643 }
 644
 645 static void
 646 bnx2_napi_enable(struct bnx2 *bp)
 647 {
 648         int i;
 649
 650         for (i = 0; i < bp->irq_nvecs; i++)
 651                 napi_enable(&bp->bnx2_napi[i].napi);
 652 }
 653
 654 static void
 655 bnx2_netif_stop(struct bnx2 *bp, bool stop_cnic)
 656 {
 657         if (stop_cnic)
 658                 bnx2_cnic_stop(bp);
 659         if (netif_running(bp->dev)) {
 660                 bnx2_napi_disable(bp);
 661                 netif_tx_disable(bp->dev);
 662         }
 663         bnx2_disable_int_sync(bp);
 664         netif_carrier_off(bp->dev);     /* prevent tx timeout */
 665 }
 666
 667 static void
 668 bnx2_netif_start(struct bnx2 *bp, bool start_cnic)
 669 {
 670         if (atomic_dec_and_test(&bp->intr_sem)) {
 671                 if (netif_running(bp->dev)) {
 672                         netif_tx_wake_all_queues(bp->dev);
 673                         spin_lock_bh(&bp->phy_lock);
 674                         if (bp->link_up)
 675                                 netif_carrier_on(bp->dev);
 676                         spin_unlock_bh(&bp->phy_lock);
 677                         bnx2_napi_enable(bp);
 678                         bnx2_enable_int(bp);
 679                         if (start_cnic)
 680                                 bnx2_cnic_start(bp);
 681                 }
 682         }
 683 }
 684
 685 static void
 686 bnx2_free_tx_mem(struct bnx2 *bp)
 687 {
 688         int i;
 689
 690         for (i = 0; i < bp->num_tx_rings; i++) {
 691                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 692                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 693
 694                 if (txr->tx_desc_ring) {
 695                         pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
 696                                             txr->tx_desc_ring,
 697                                             txr->tx_desc_mapping);
 698                         txr->tx_desc_ring = NULL;
 699                 }
 700                 kfree(txr->tx_buf_ring);
 701                 txr->tx_buf_ring = NULL;
 702         }
 703 }
 704
 705 static void
 706 bnx2_free_rx_mem(struct bnx2 *bp)
 707 {
 708         int i;
 709
 710         for (i = 0; i < bp->num_rx_rings; i++) {
 711                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 712                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 713                 int j;
 714
 715                 for (j = 0; j < bp->rx_max_ring; j++) {
 716                         if (rxr->rx_desc_ring[j])
 717                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 718                                                     rxr->rx_desc_ring[j],
 719                                                     rxr->rx_desc_mapping[j]);
 720                         rxr->rx_desc_ring[j] = NULL;
 721                 }
 722                 vfree(rxr->rx_buf_ring);
 723                 rxr->rx_buf_ring = NULL;
 724
 725                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 726                         if (rxr->rx_pg_desc_ring[j])
 727                                 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
 728                                                     rxr->rx_pg_desc_ring[j],
 729                                                     rxr->rx_pg_desc_mapping[j]);
 730                         rxr->rx_pg_desc_ring[j] = NULL;
 731                 }
 732                 vfree(rxr->rx_pg_ring);
 733                 rxr->rx_pg_ring = NULL;
 734         }
 735 }
 736
 737 static int
 738 bnx2_alloc_tx_mem(struct bnx2 *bp)
 739 {
 740         int i;
 741
 742         for (i = 0; i < bp->num_tx_rings; i++) {
 743                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 744                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
 745
 746                 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
 747                 if (txr->tx_buf_ring == NULL)
 748                         return -ENOMEM;
 749
 750                 txr->tx_desc_ring =
 751                         pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
 752                                              &txr->tx_desc_mapping);
 753                 if (txr->tx_desc_ring == NULL)
 754                         return -ENOMEM;
 755         }
 756         return 0;
 757 }
 758
 759 static int
 760 bnx2_alloc_rx_mem(struct bnx2 *bp)
 761 {
 762         int i;
 763
 764         for (i = 0; i < bp->num_rx_rings; i++) {
 765                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
 766                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
 767                 int j;
 768
 769                 rxr->rx_buf_ring =
 770                         vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
 771                 if (rxr->rx_buf_ring == NULL)
 772                         return -ENOMEM;
 773
 774                 memset(rxr->rx_buf_ring, 0,
 775                        SW_RXBD_RING_SIZE * bp->rx_max_ring);
 776
 777                 for (j = 0; j < bp->rx_max_ring; j++) {
 778                         rxr->rx_desc_ring[j] =
 779                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 780                                                      &rxr->rx_desc_mapping[j]);
 781                         if (rxr->rx_desc_ring[j] == NULL)
 782                                 return -ENOMEM;
 783
 784                 }
 785
 786                 if (bp->rx_pg_ring_size) {
 787                         rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
 788                                                   bp->rx_max_pg_ring);
 789                         if (rxr->rx_pg_ring == NULL)
 790                                 return -ENOMEM;
 791
 792                         memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
 793                                bp->rx_max_pg_ring);
 794                 }
 795
 796                 for (j = 0; j < bp->rx_max_pg_ring; j++) {
 797                         rxr->rx_pg_desc_ring[j] =
 798                                 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
 799                                                 &rxr->rx_pg_desc_mapping[j]);
 800                         if (rxr->rx_pg_desc_ring[j] == NULL)
 801                                 return -ENOMEM;
 802
 803                 }
 804         }
 805         return 0;
 806 }
 807
 808 static void
 809 bnx2_free_mem(struct bnx2 *bp)
 810 {
 811         int i;
 812         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
 813
 814         bnx2_free_tx_mem(bp);
 815         bnx2_free_rx_mem(bp);
 816
 817         for (i = 0; i < bp->ctx_pages; i++) {
 818                 if (bp->ctx_blk[i]) {
 819                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 820                                             bp->ctx_blk[i],
 821                                             bp->ctx_blk_mapping[i]);
 822                         bp->ctx_blk[i] = NULL;
 823                 }
 824         }
 825         if (bnapi->status_blk.msi) {
 826                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 827                                     bnapi->status_blk.msi,
 828                                     bp->status_blk_mapping);
 829                 bnapi->status_blk.msi = NULL;
 830                 bp->stats_blk = NULL;
 831         }
 832 }
 833
 834 static int
 835 bnx2_alloc_mem(struct bnx2 *bp)
 836 {
 837         int i, status_blk_size, err;
 838         struct bnx2_napi *bnapi;
 839         void *status_blk;
 840
 841         /* Combine status and statistics blocks into one allocation. */
 842         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 843         if (bp->flags & BNX2_FLAG_MSIX_CAP)
 844                 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
 845                                                  BNX2_SBLK_MSIX_ALIGN_SIZE);
 846         bp->status_stats_size = status_blk_size +
 847                                 sizeof(struct statistics_block);
 848
 849         status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 850                                           &bp->status_blk_mapping);
 851         if (status_blk == NULL)
 852                 goto alloc_mem_err;
 853
 854         memset(status_blk, 0, bp->status_stats_size);
 855
 856         bnapi = &bp->bnx2_napi[0];
 857         bnapi->status_blk.msi = status_blk;
 858         bnapi->hw_tx_cons_ptr =
 859                 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
 860         bnapi->hw_rx_cons_ptr =
 861                 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
 862         if (bp->flags & BNX2_FLAG_MSIX_CAP) {
 863                 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
 864                         struct status_block_msix *sblk;
 865
 866                         bnapi = &bp->bnx2_napi[i];
 867
 868                         sblk = (void *) (status_blk +
 869                                          BNX2_SBLK_MSIX_ALIGN_SIZE * i);
 870                         bnapi->status_blk.msix = sblk;
 871                         bnapi->hw_tx_cons_ptr =
 872                                 &sblk->status_tx_quick_consumer_index;
 873                         bnapi->hw_rx_cons_ptr =
 874                                 &sblk->status_rx_quick_consumer_index;
 875                         bnapi->int_num = i << 24;
 876                 }
 877         }
 878
 879         bp->stats_blk = status_blk + status_blk_size;
 880
 881         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 882
 883         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 884                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 885                 if (bp->ctx_pages == 0)
 886                         bp->ctx_pages = 1;
 887                 for (i = 0; i < bp->ctx_pages; i++) {
 888                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 889                                                 BCM_PAGE_SIZE,
 890                                                 &bp->ctx_blk_mapping[i]);
 891                         if (bp->ctx_blk[i] == NULL)
 892                                 goto alloc_mem_err;
 893                 }
 894         }
 895
 896         err = bnx2_alloc_rx_mem(bp);
 897         if (err)
 898                 goto alloc_mem_err;
 899
 900         err = bnx2_alloc_tx_mem(bp);
 901         if (err)
 902                 goto alloc_mem_err;
 903
 904         return 0;
 905
 906 alloc_mem_err:
 907         bnx2_free_mem(bp);
 908         return -ENOMEM;
 909 }
 910
 911 static void
 912 bnx2_report_fw_link(struct bnx2 *bp)
 913 {
 914         u32 fw_link_status = 0;
 915
 916         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
 917                 return;
 918
 919         if (bp->link_up) {
 920                 u32 bmsr;
 921
 922                 switch (bp->line_speed) {
 923                 case SPEED_10:
 924                         if (bp->duplex == DUPLEX_HALF)
 925                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 926                         else
 927                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 928                         break;
 929                 case SPEED_100:
 930                         if (bp->duplex == DUPLEX_HALF)
 931                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 932                         else
 933                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 934                         break;
 935                 case SPEED_1000:
 936                         if (bp->duplex == DUPLEX_HALF)
 937                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 938                         else
 939                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 940                         break;
 941                 case SPEED_2500:
 942                         if (bp->duplex == DUPLEX_HALF)
 943                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 944                         else
 945                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 946                         break;
 947                 }
 948
 949                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 950
 951                 if (bp->autoneg) {
 952                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 953
 954                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 955                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
 956
 957                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 958                             bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
 959                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 960                         else
 961                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 962                 }
 963         }
 964         else
 965                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 966
 967         bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
 968 }
 969
 970 static char *
 971 bnx2_xceiver_str(struct bnx2 *bp)
 972 {
 973         return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
 974                 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
 975                  "Copper"));
 976 }
 977
 978 static void
 979 bnx2_report_link(struct bnx2 *bp)
 980 {
 981         if (bp->link_up) {
 982                 netif_carrier_on(bp->dev);
 983                 netdev_info(bp->dev, "NIC %s Link is Up, %d Mbps %s duplex",
 984                             bnx2_xceiver_str(bp),
 985                             bp->line_speed,
 986                             bp->duplex == DUPLEX_FULL ? "full" : "half");
 987
 988                 if (bp->flow_ctrl) {
 989                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 990                                 pr_cont(", receive ");
 991                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 992                                         pr_cont("& transmit ");
 993                         }
 994                         else {
 995                                 pr_cont(", transmit ");
 996                         }
 997                         pr_cont("flow control ON");
 998                 }
 999                 pr_cont("\n");
1000         } else {
1001                 netif_carrier_off(bp->dev);
1002                 netdev_err(bp->dev, "NIC %s Link is Down\n",
1003                            bnx2_xceiver_str(bp));
1004         }
1005
1006         bnx2_report_fw_link(bp);
1007 }
1008
1009 static void
1010 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1011 {
1012         u32 local_adv, remote_adv;
1013
1014         bp->flow_ctrl = 0;
1015         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1016                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1017
1018                 if (bp->duplex == DUPLEX_FULL) {
1019                         bp->flow_ctrl = bp->req_flow_ctrl;
1020                 }
1021                 return;
1022         }
1023
1024         if (bp->duplex != DUPLEX_FULL) {
1025                 return;
1026         }
1027
1028         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1029             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1030                 u32 val;
1031
1032                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1033                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1034                         bp->flow_ctrl |= FLOW_CTRL_TX;
1035                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1036                         bp->flow_ctrl |= FLOW_CTRL_RX;
1037                 return;
1038         }
1039
1040         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1041         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1042
1043         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1044                 u32 new_local_adv = 0;
1045                 u32 new_remote_adv = 0;
1046
1047                 if (local_adv & ADVERTISE_1000XPAUSE)
1048                         new_local_adv |= ADVERTISE_PAUSE_CAP;
1049                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1050                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
1051                 if (remote_adv & ADVERTISE_1000XPAUSE)
1052                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
1053                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1054                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1055
1056                 local_adv = new_local_adv;
1057                 remote_adv = new_remote_adv;
1058         }
1059
1060         /* See Table 28B-3 of 802.3ab-1999 spec. */
1061         if (local_adv & ADVERTISE_PAUSE_CAP) {
1062                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1063                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
1064                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1065                         }
1066                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1067                                 bp->flow_ctrl = FLOW_CTRL_RX;
1068                         }
1069                 }
1070                 else {
1071                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073                         }
1074                 }
1075         }
1076         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1077                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1078                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1079
1080                         bp->flow_ctrl = FLOW_CTRL_TX;
1081                 }
1082         }
1083 }
1084
1085 static int
1086 bnx2_5709s_linkup(struct bnx2 *bp)
1087 {
1088         u32 val, speed;
1089
1090         bp->link_up = 1;
1091
1092         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1093         bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1094         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1095
1096         if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1097                 bp->line_speed = bp->req_line_speed;
1098                 bp->duplex = bp->req_duplex;
1099                 return 0;
1100         }
1101         speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1102         switch (speed) {
1103                 case MII_BNX2_GP_TOP_AN_SPEED_10:
1104                         bp->line_speed = SPEED_10;
1105                         break;
1106                 case MII_BNX2_GP_TOP_AN_SPEED_100:
1107                         bp->line_speed = SPEED_100;
1108                         break;
1109                 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1110                 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1111                         bp->line_speed = SPEED_1000;
1112                         break;
1113                 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1114                         bp->line_speed = SPEED_2500;
1115                         break;
1116         }
1117         if (val & MII_BNX2_GP_TOP_AN_FD)
1118                 bp->duplex = DUPLEX_FULL;
1119         else
1120                 bp->duplex = DUPLEX_HALF;
1121         return 0;
1122 }
1123
1124 static int
1125 bnx2_5708s_linkup(struct bnx2 *bp)
1126 {
1127         u32 val;
1128
1129         bp->link_up = 1;
1130         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1131         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1132                 case BCM5708S_1000X_STAT1_SPEED_10:
1133                         bp->line_speed = SPEED_10;
1134                         break;
1135                 case BCM5708S_1000X_STAT1_SPEED_100:
1136                         bp->line_speed = SPEED_100;
1137                         break;
1138                 case BCM5708S_1000X_STAT1_SPEED_1G:
1139                         bp->line_speed = SPEED_1000;
1140                         break;
1141                 case BCM5708S_1000X_STAT1_SPEED_2G5:
1142                         bp->line_speed = SPEED_2500;
1143                         break;
1144         }
1145         if (val & BCM5708S_1000X_STAT1_FD)
1146                 bp->duplex = DUPLEX_FULL;
1147         else
1148                 bp->duplex = DUPLEX_HALF;
1149
1150         return 0;
1151 }
1152
1153 static int
1154 bnx2_5706s_linkup(struct bnx2 *bp)
1155 {
1156         u32 bmcr, local_adv, remote_adv, common;
1157
1158         bp->link_up = 1;
1159         bp->line_speed = SPEED_1000;
1160
1161         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1162         if (bmcr & BMCR_FULLDPLX) {
1163                 bp->duplex = DUPLEX_FULL;
1164         }
1165         else {
1166                 bp->duplex = DUPLEX_HALF;
1167         }
1168
1169         if (!(bmcr & BMCR_ANENABLE)) {
1170                 return 0;
1171         }
1172
1173         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1174         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1175
1176         common = local_adv & remote_adv;
1177         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1178
1179                 if (common & ADVERTISE_1000XFULL) {
1180                         bp->duplex = DUPLEX_FULL;
1181                 }
1182                 else {
1183                         bp->duplex = DUPLEX_HALF;
1184                 }
1185         }
1186
1187         return 0;
1188 }
1189
1190 static int
1191 bnx2_copper_linkup(struct bnx2 *bp)
1192 {
1193         u32 bmcr;
1194
1195         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1196         if (bmcr & BMCR_ANENABLE) {
1197                 u32 local_adv, remote_adv, common;
1198
1199                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1200                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1201
1202                 common = local_adv & (remote_adv >> 2);
1203                 if (common & ADVERTISE_1000FULL) {
1204                         bp->line_speed = SPEED_1000;
1205                         bp->duplex = DUPLEX_FULL;
1206                 }
1207                 else if (common & ADVERTISE_1000HALF) {
1208                         bp->line_speed = SPEED_1000;
1209                         bp->duplex = DUPLEX_HALF;
1210                 }
1211                 else {
1212                         bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1213                         bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1214
1215                         common = local_adv & remote_adv;
1216                         if (common & ADVERTISE_100FULL) {
1217                                 bp->line_speed = SPEED_100;
1218                                 bp->duplex = DUPLEX_FULL;
1219                         }
1220                         else if (common & ADVERTISE_100HALF) {
1221                                 bp->line_speed = SPEED_100;
1222                                 bp->duplex = DUPLEX_HALF;
1223                         }
1224                         else if (common & ADVERTISE_10FULL) {
1225                                 bp->line_speed = SPEED_10;
1226                                 bp->duplex = DUPLEX_FULL;
1227                         }
1228                         else if (common & ADVERTISE_10HALF) {
1229                                 bp->line_speed = SPEED_10;
1230                                 bp->duplex = DUPLEX_HALF;
1231                         }
1232                         else {
1233                                 bp->line_speed = 0;
1234                                 bp->link_up = 0;
1235                         }
1236                 }
1237         }
1238         else {
1239                 if (bmcr & BMCR_SPEED100) {
1240                         bp->line_speed = SPEED_100;
1241                 }
1242                 else {
1243                         bp->line_speed = SPEED_10;
1244                 }
1245                 if (bmcr & BMCR_FULLDPLX) {
1246                         bp->duplex = DUPLEX_FULL;
1247                 }
1248                 else {
1249                         bp->duplex = DUPLEX_HALF;
1250                 }
1251         }
1252
1253         return 0;
1254 }
1255
1256 static void
1257 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1258 {
1259         u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1260
1261         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1262         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1263         val |= 0x02 << 8;
1264
1265         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1266                 u32 lo_water, hi_water;
1267
1268                 if (bp->flow_ctrl & FLOW_CTRL_TX)
1269                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1270                 else
1271                         lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1272                 if (lo_water >= bp->rx_ring_size)
1273                         lo_water = 0;
1274
1275                 hi_water = min_t(int, bp->rx_ring_size / 4, lo_water + 16);
1276
1277                 if (hi_water <= lo_water)
1278                         lo_water = 0;
1279
1280                 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1281                 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1282
1283                 if (hi_water > 0xf)
1284                         hi_water = 0xf;
1285                 else if (hi_water == 0)
1286                         lo_water = 0;
1287                 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1288         }
1289         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1290 }
1291
1292 static void
1293 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1294 {
1295         int i;
1296         u32 cid;
1297
1298         for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1299                 if (i == 1)
1300                         cid = RX_RSS_CID;
1301                 bnx2_init_rx_context(bp, cid);
1302         }
1303 }
1304
1305 static void
1306 bnx2_set_mac_link(struct bnx2 *bp)
1307 {
1308         u32 val;
1309
1310         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1311         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1312                 (bp->duplex == DUPLEX_HALF)) {
1313                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1314         }
1315
1316         /* Configure the EMAC mode register. */
1317         val = REG_RD(bp, BNX2_EMAC_MODE);
1318
1319         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1320                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1321                 BNX2_EMAC_MODE_25G_MODE);
1322
1323         if (bp->link_up) {
1324                 switch (bp->line_speed) {
1325                         case SPEED_10:
1326                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1327                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
1328                                         break;
1329                                 }
1330                                 /* fall through */
1331                         case SPEED_100:
1332                                 val |= BNX2_EMAC_MODE_PORT_MII;
1333                                 break;
1334                         case SPEED_2500:
1335                                 val |= BNX2_EMAC_MODE_25G_MODE;
1336                                 /* fall through */
1337                         case SPEED_1000:
1338                                 val |= BNX2_EMAC_MODE_PORT_GMII;
1339                                 break;
1340                 }
1341         }
1342         else {
1343                 val |= BNX2_EMAC_MODE_PORT_GMII;
1344         }
1345
1346         /* Set the MAC to operate in the appropriate duplex mode. */
1347         if (bp->duplex == DUPLEX_HALF)
1348                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1349         REG_WR(bp, BNX2_EMAC_MODE, val);
1350
1351         /* Enable/disable rx PAUSE. */
1352         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1353
1354         if (bp->flow_ctrl & FLOW_CTRL_RX)
1355                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1356         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1357
1358         /* Enable/disable tx PAUSE. */
1359         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1360         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1361
1362         if (bp->flow_ctrl & FLOW_CTRL_TX)
1363                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1364         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1365
1366         /* Acknowledge the interrupt. */
1367         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1368
1369         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1370                 bnx2_init_all_rx_contexts(bp);
1371 }
1372
1373 static void
1374 bnx2_enable_bmsr1(struct bnx2 *bp)
1375 {
1376         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1377             (CHIP_NUM(bp) == CHIP_NUM_5709))
1378                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1379                                MII_BNX2_BLK_ADDR_GP_STATUS);
1380 }
1381
1382 static void
1383 bnx2_disable_bmsr1(struct bnx2 *bp)
1384 {
1385         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1386             (CHIP_NUM(bp) == CHIP_NUM_5709))
1387                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1388                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1389 }
1390
1391 static int
1392 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1393 {
1394         u32 up1;
1395         int ret = 1;
1396
1397         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1398                 return 0;
1399
1400         if (bp->autoneg & AUTONEG_SPEED)
1401                 bp->advertising |= ADVERTISED_2500baseX_Full;
1402
1403         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1404                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1405
1406         bnx2_read_phy(bp, bp->mii_up1, &up1);
1407         if (!(up1 & BCM5708S_UP1_2G5)) {
1408                 up1 |= BCM5708S_UP1_2G5;
1409                 bnx2_write_phy(bp, bp->mii_up1, up1);
1410                 ret = 0;
1411         }
1412
1413         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1414                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1415                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1416
1417         return ret;
1418 }
1419
1420 static int
1421 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1422 {
1423         u32 up1;
1424         int ret = 0;
1425
1426         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1427                 return 0;
1428
1429         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1430                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1431
1432         bnx2_read_phy(bp, bp->mii_up1, &up1);
1433         if (up1 & BCM5708S_UP1_2G5) {
1434                 up1 &= ~BCM5708S_UP1_2G5;
1435                 bnx2_write_phy(bp, bp->mii_up1, up1);
1436                 ret = 1;
1437         }
1438
1439         if (CHIP_NUM(bp) == CHIP_NUM_5709)
1440                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1441                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1442
1443         return ret;
1444 }
1445
1446 static void
1447 bnx2_enable_forced_2g5(struct bnx2 *bp)
1448 {
1449         u32 bmcr;
1450
1451         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1452                 return;
1453
1454         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1455                 u32 val;
1456
1457                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1458                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1459                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1460                 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1461                 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1462                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1463
1464                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1465                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1466                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1467
1468         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1469                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1470                 bmcr |= BCM5708S_BMCR_FORCE_2500;
1471         } else {
1472                 return;
1473         }
1474
1475         if (bp->autoneg & AUTONEG_SPEED) {
1476                 bmcr &= ~BMCR_ANENABLE;
1477                 if (bp->req_duplex == DUPLEX_FULL)
1478                         bmcr |= BMCR_FULLDPLX;
1479         }
1480         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1481 }
1482
1483 static void
1484 bnx2_disable_forced_2g5(struct bnx2 *bp)
1485 {
1486         u32 bmcr;
1487
1488         if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1489                 return;
1490
1491         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1492                 u32 val;
1493
1494                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1495                                MII_BNX2_BLK_ADDR_SERDES_DIG);
1496                 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1497                 val &= ~MII_BNX2_SD_MISC1_FORCE;
1498                 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1499
1500                 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1501                                MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1502                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1503
1504         } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1505                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1506                 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1507         } else {
1508                 return;
1509         }
1510
1511         if (bp->autoneg & AUTONEG_SPEED)
1512                 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1513         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1514 }
1515
1516 static void
1517 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1518 {
1519         u32 val;
1520
1521         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1522         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1523         if (start)
1524                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1525         else
1526                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1527 }
1528
1529 static int
1530 bnx2_set_link(struct bnx2 *bp)
1531 {
1532         u32 bmsr;
1533         u8 link_up;
1534
1535         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1536                 bp->link_up = 1;
1537                 return 0;
1538         }
1539
1540         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1541                 return 0;
1542
1543         link_up = bp->link_up;
1544
1545         bnx2_enable_bmsr1(bp);
1546         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1547         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1548         bnx2_disable_bmsr1(bp);
1549
1550         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1551             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1552                 u32 val, an_dbg;
1553
1554                 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1555                         bnx2_5706s_force_link_dn(bp, 0);
1556                         bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1557                 }
1558                 val = REG_RD(bp, BNX2_EMAC_STATUS);
1559
1560                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1561                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1562                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1563
1564                 if ((val & BNX2_EMAC_STATUS_LINK) &&
1565                     !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1566                         bmsr |= BMSR_LSTATUS;
1567                 else
1568                         bmsr &= ~BMSR_LSTATUS;
1569         }
1570
1571         if (bmsr & BMSR_LSTATUS) {
1572                 bp->link_up = 1;
1573
1574                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1575                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1576                                 bnx2_5706s_linkup(bp);
1577                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1578                                 bnx2_5708s_linkup(bp);
1579                         else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1580                                 bnx2_5709s_linkup(bp);
1581                 }
1582                 else {
1583                         bnx2_copper_linkup(bp);
1584                 }
1585                 bnx2_resolve_flow_ctrl(bp);
1586         }
1587         else {
1588                 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1589                     (bp->autoneg & AUTONEG_SPEED))
1590                         bnx2_disable_forced_2g5(bp);
1591
1592                 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1593                         u32 bmcr;
1594
1595                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1596                         bmcr |= BMCR_ANENABLE;
1597                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1598
1599                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1600                 }
1601                 bp->link_up = 0;
1602         }
1603
1604         if (bp->link_up != link_up) {
1605                 bnx2_report_link(bp);
1606         }
1607
1608         bnx2_set_mac_link(bp);
1609
1610         return 0;
1611 }
1612
1613 static int
1614 bnx2_reset_phy(struct bnx2 *bp)
1615 {
1616         int i;
1617         u32 reg;
1618
1619         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1620
1621 #define PHY_RESET_MAX_WAIT 100
1622         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1623                 udelay(10);
1624
1625                 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1626                 if (!(reg & BMCR_RESET)) {
1627                         udelay(20);
1628                         break;
1629                 }
1630         }
1631         if (i == PHY_RESET_MAX_WAIT) {
1632                 return -EBUSY;
1633         }
1634         return 0;
1635 }
1636
1637 static u32
1638 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1639 {
1640         u32 adv = 0;
1641
1642         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1643                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1644
1645                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1646                         adv = ADVERTISE_1000XPAUSE;
1647                 }
1648                 else {
1649                         adv = ADVERTISE_PAUSE_CAP;
1650                 }
1651         }
1652         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1653                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1654                         adv = ADVERTISE_1000XPSE_ASYM;
1655                 }
1656                 else {
1657                         adv = ADVERTISE_PAUSE_ASYM;
1658                 }
1659         }
1660         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1661                 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1662                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1663                 }
1664                 else {
1665                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1666                 }
1667         }
1668         return adv;
1669 }
1670
1671 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1672
1673 static int
1674 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1675 __releases(&bp->phy_lock)
1676 __acquires(&bp->phy_lock)
1677 {
1678         u32 speed_arg = 0, pause_adv;
1679
1680         pause_adv = bnx2_phy_get_pause_adv(bp);
1681
1682         if (bp->autoneg & AUTONEG_SPEED) {
1683                 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1684                 if (bp->advertising & ADVERTISED_10baseT_Half)
1685                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1686                 if (bp->advertising & ADVERTISED_10baseT_Full)
1687                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1688                 if (bp->advertising & ADVERTISED_100baseT_Half)
1689                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1690                 if (bp->advertising & ADVERTISED_100baseT_Full)
1691                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1692                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1693                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1694                 if (bp->advertising & ADVERTISED_2500baseX_Full)
1695                         speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1696         } else {
1697                 if (bp->req_line_speed == SPEED_2500)
1698                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1699                 else if (bp->req_line_speed == SPEED_1000)
1700                         speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1701                 else if (bp->req_line_speed == SPEED_100) {
1702                         if (bp->req_duplex == DUPLEX_FULL)
1703                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1704                         else
1705                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1706                 } else if (bp->req_line_speed == SPEED_10) {
1707                         if (bp->req_duplex == DUPLEX_FULL)
1708                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1709                         else
1710                                 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1711                 }
1712         }
1713
1714         if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1715                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1716         if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1717                 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1718
1719         if (port == PORT_TP)
1720                 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1721                              BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1722
1723         bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1724
1725         spin_unlock_bh(&bp->phy_lock);
1726         bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1727         spin_lock_bh(&bp->phy_lock);
1728
1729         return 0;
1730 }
1731
1732 static int
1733 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1734 __releases(&bp->phy_lock)
1735 __acquires(&bp->phy_lock)
1736 {
1737         u32 adv, bmcr;
1738         u32 new_adv = 0;
1739
1740         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1741                 return (bnx2_setup_remote_phy(bp, port));
1742
1743         if (!(bp->autoneg & AUTONEG_SPEED)) {
1744                 u32 new_bmcr;
1745                 int force_link_down = 0;
1746
1747                 if (bp->req_line_speed == SPEED_2500) {
1748                         if (!bnx2_test_and_enable_2g5(bp))
1749                                 force_link_down = 1;
1750                 } else if (bp->req_line_speed == SPEED_1000) {
1751                         if (bnx2_test_and_disable_2g5(bp))
1752                                 force_link_down = 1;
1753                 }
1754                 bnx2_read_phy(bp, bp->mii_adv, &adv);
1755                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1756
1757                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1758                 new_bmcr = bmcr & ~BMCR_ANENABLE;
1759                 new_bmcr |= BMCR_SPEED1000;
1760
1761                 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1762                         if (bp->req_line_speed == SPEED_2500)
1763                                 bnx2_enable_forced_2g5(bp);
1764                         else if (bp->req_line_speed == SPEED_1000) {
1765                                 bnx2_disable_forced_2g5(bp);
1766                                 new_bmcr &= ~0x2000;
1767                         }
1768
1769                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1770                         if (bp->req_line_speed == SPEED_2500)
1771                                 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1772                         else
1773                                 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1774                 }
1775
1776                 if (bp->req_duplex == DUPLEX_FULL) {
1777                         adv |= ADVERTISE_1000XFULL;
1778                         new_bmcr |= BMCR_FULLDPLX;
1779                 }
1780                 else {
1781                         adv |= ADVERTISE_1000XHALF;
1782                         new_bmcr &= ~BMCR_FULLDPLX;
1783                 }
1784                 if ((new_bmcr != bmcr) || (force_link_down)) {
1785                         /* Force a link down visible on the other side */
1786                         if (bp->link_up) {
1787                                 bnx2_write_phy(bp, bp->mii_adv, adv &
1788                                                ~(ADVERTISE_1000XFULL |
1789                                                  ADVERTISE_1000XHALF));
1790                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1791                                         BMCR_ANRESTART | BMCR_ANENABLE);
1792
1793                                 bp->link_up = 0;
1794                                 netif_carrier_off(bp->dev);
1795                                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1796                                 bnx2_report_link(bp);
1797                         }
1798                         bnx2_write_phy(bp, bp->mii_adv, adv);
1799                         bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1800                 } else {
1801                         bnx2_resolve_flow_ctrl(bp);
1802                         bnx2_set_mac_link(bp);
1803                 }
1804                 return 0;
1805         }
1806
1807         bnx2_test_and_enable_2g5(bp);
1808
1809         if (bp->advertising & ADVERTISED_1000baseT_Full)
1810                 new_adv |= ADVERTISE_1000XFULL;
1811
1812         new_adv |= bnx2_phy_get_pause_adv(bp);
1813
1814         bnx2_read_phy(bp, bp->mii_adv, &adv);
1815         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1816
1817         bp->serdes_an_pending = 0;
1818         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1819                 /* Force a link down visible on the other side */
1820                 if (bp->link_up) {
1821                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1822                         spin_unlock_bh(&bp->phy_lock);
1823                         msleep(20);
1824                         spin_lock_bh(&bp->phy_lock);
1825                 }
1826
1827                 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1828                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1829                         BMCR_ANENABLE);
1830                 /* Speed up link-up time when the link partner
1831                  * does not autonegotiate which is very common
1832                  * in blade servers. Some blade servers use
1833                  * IPMI for kerboard input and it's important
1834                  * to minimize link disruptions. Autoneg. involves
1835                  * exchanging base pages plus 3 next pages and
1836                  * normally completes in about 120 msec.
1837                  */
1838                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1839                 bp->serdes_an_pending = 1;
1840                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1841         } else {
1842                 bnx2_resolve_flow_ctrl(bp);
1843                 bnx2_set_mac_link(bp);
1844         }
1845
1846         return 0;
1847 }
1848
1849 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1850         (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ?                  \
1851                 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1852                 (ADVERTISED_1000baseT_Full)
1853
1854 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1855         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1856         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1857         ADVERTISED_1000baseT_Full)
1858
1859 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1860         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1861
1862 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1863
1864 static void
1865 bnx2_set_default_remote_link(struct bnx2 *bp)
1866 {
1867         u32 link;
1868
1869         if (bp->phy_port == PORT_TP)
1870                 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1871         else
1872                 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1873
1874         if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1875                 bp->req_line_speed = 0;
1876                 bp->autoneg |= AUTONEG_SPEED;
1877                 bp->advertising = ADVERTISED_Autoneg;
1878                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1879                         bp->advertising |= ADVERTISED_10baseT_Half;
1880                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1881                         bp->advertising |= ADVERTISED_10baseT_Full;
1882                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1883                         bp->advertising |= ADVERTISED_100baseT_Half;
1884                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1885                         bp->advertising |= ADVERTISED_100baseT_Full;
1886                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1887                         bp->advertising |= ADVERTISED_1000baseT_Full;
1888                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1889                         bp->advertising |= ADVERTISED_2500baseX_Full;
1890         } else {
1891                 bp->autoneg = 0;
1892                 bp->advertising = 0;
1893                 bp->req_duplex = DUPLEX_FULL;
1894                 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1895                         bp->req_line_speed = SPEED_10;
1896                         if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1897                                 bp->req_duplex = DUPLEX_HALF;
1898                 }
1899                 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1900                         bp->req_line_speed = SPEED_100;
1901                         if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1902                                 bp->req_duplex = DUPLEX_HALF;
1903                 }
1904                 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1905                         bp->req_line_speed = SPEED_1000;
1906                 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1907                         bp->req_line_speed = SPEED_2500;
1908         }
1909 }
1910
1911 static void
1912 bnx2_set_default_link(struct bnx2 *bp)
1913 {
1914         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1915                 bnx2_set_default_remote_link(bp);
1916                 return;
1917         }
1918
1919         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1920         bp->req_line_speed = 0;
1921         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1922                 u32 reg;
1923
1924                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1925
1926                 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1927                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1928                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1929                         bp->autoneg = 0;
1930                         bp->req_line_speed = bp->line_speed = SPEED_1000;
1931                         bp->req_duplex = DUPLEX_FULL;
1932                 }
1933         } else
1934                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1935 }
1936
1937 static void
1938 bnx2_send_heart_beat(struct bnx2 *bp)
1939 {
1940         u32 msg;
1941         u32 addr;
1942
1943         spin_lock(&bp->indirect_lock);
1944         msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1945         addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1946         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1947         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1948         spin_unlock(&bp->indirect_lock);
1949 }
1950
1951 static void
1952 bnx2_remote_phy_event(struct bnx2 *bp)
1953 {
1954         u32 msg;
1955         u8 link_up = bp->link_up;
1956         u8 old_port;
1957
1958         msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1959
1960         if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1961                 bnx2_send_heart_beat(bp);
1962
1963         msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1964
1965         if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1966                 bp->link_up = 0;
1967         else {
1968                 u32 speed;
1969
1970                 bp->link_up = 1;
1971                 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1972                 bp->duplex = DUPLEX_FULL;
1973                 switch (speed) {
1974                         case BNX2_LINK_STATUS_10HALF:
1975                                 bp->duplex = DUPLEX_HALF;
1976                         case BNX2_LINK_STATUS_10FULL:
1977                                 bp->line_speed = SPEED_10;
1978                                 break;
1979                         case BNX2_LINK_STATUS_100HALF:
1980                                 bp->duplex = DUPLEX_HALF;
1981                         case BNX2_LINK_STATUS_100BASE_T4:
1982                         case BNX2_LINK_STATUS_100FULL:
1983                                 bp->line_speed = SPEED_100;
1984                                 break;
1985                         case BNX2_LINK_STATUS_1000HALF:
1986                                 bp->duplex = DUPLEX_HALF;
1987                         case BNX2_LINK_STATUS_1000FULL:
1988                                 bp->line_speed = SPEED_1000;
1989                                 break;
1990                         case BNX2_LINK_STATUS_2500HALF:
1991                                 bp->duplex = DUPLEX_HALF;
1992                         case BNX2_LINK_STATUS_2500FULL:
1993                                 bp->line_speed = SPEED_2500;
1994                                 break;
1995                         default:
1996                                 bp->line_speed = 0;
1997                                 break;
1998                 }
1999
2000                 bp->flow_ctrl = 0;
2001                 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2002                     (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2003                         if (bp->duplex == DUPLEX_FULL)
2004                                 bp->flow_ctrl = bp->req_flow_ctrl;
2005                 } else {
2006                         if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2007                                 bp->flow_ctrl |= FLOW_CTRL_TX;
2008                         if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2009                                 bp->flow_ctrl |= FLOW_CTRL_RX;
2010                 }
2011
2012                 old_port = bp->phy_port;
2013                 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2014                         bp->phy_port = PORT_FIBRE;
2015                 else
2016                         bp->phy_port = PORT_TP;
2017
2018                 if (old_port != bp->phy_port)
2019                         bnx2_set_default_link(bp);
2020
2021         }
2022         if (bp->link_up != link_up)
2023                 bnx2_report_link(bp);
2024
2025         bnx2_set_mac_link(bp);
2026 }
2027
2028 static int
2029 bnx2_set_remote_link(struct bnx2 *bp)
2030 {
2031         u32 evt_code;
2032
2033         evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2034         switch (evt_code) {
2035                 case BNX2_FW_EVT_CODE_LINK_EVENT:
2036                         bnx2_remote_phy_event(bp);
2037                         break;
2038                 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2039                 default:
2040                         bnx2_send_heart_beat(bp);
2041                         break;
2042         }
2043         return 0;
2044 }
2045
2046 static int
2047 bnx2_setup_copper_phy(struct bnx2 *bp)
2048 __releases(&bp->phy_lock)
2049 __acquires(&bp->phy_lock)
2050 {
2051         u32 bmcr;
2052         u32 new_bmcr;
2053
2054         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2055
2056         if (bp->autoneg & AUTONEG_SPEED) {
2057                 u32 adv_reg, adv1000_reg;
2058                 u32 new_adv_reg = 0;
2059                 u32 new_adv1000_reg = 0;
2060
2061                 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2062                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2063                         ADVERTISE_PAUSE_ASYM);
2064
2065                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2066                 adv1000_reg &= PHY_ALL_1000_SPEED;
2067
2068                 if (bp->advertising & ADVERTISED_10baseT_Half)
2069                         new_adv_reg |= ADVERTISE_10HALF;
2070                 if (bp->advertising & ADVERTISED_10baseT_Full)
2071                         new_adv_reg |= ADVERTISE_10FULL;
2072                 if (bp->advertising & ADVERTISED_100baseT_Half)
2073                         new_adv_reg |= ADVERTISE_100HALF;
2074                 if (bp->advertising & ADVERTISED_100baseT_Full)
2075                         new_adv_reg |= ADVERTISE_100FULL;
2076                 if (bp->advertising & ADVERTISED_1000baseT_Full)
2077                         new_adv1000_reg |= ADVERTISE_1000FULL;
2078
2079                 new_adv_reg |= ADVERTISE_CSMA;
2080
2081                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2082
2083                 if ((adv1000_reg != new_adv1000_reg) ||
2084                         (adv_reg != new_adv_reg) ||
2085                         ((bmcr & BMCR_ANENABLE) == 0)) {
2086
2087                         bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2088                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2089                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2090                                 BMCR_ANENABLE);
2091                 }
2092                 else if (bp->link_up) {
2093                         /* Flow ctrl may have changed from auto to forced */
2094                         /* or vice-versa. */
2095
2096                         bnx2_resolve_flow_ctrl(bp);
2097                         bnx2_set_mac_link(bp);
2098                 }
2099                 return 0;
2100         }
2101
2102         new_bmcr = 0;
2103         if (bp->req_line_speed == SPEED_100) {
2104                 new_bmcr |= BMCR_SPEED100;
2105         }
2106         if (bp->req_duplex == DUPLEX_FULL) {
2107                 new_bmcr |= BMCR_FULLDPLX;
2108         }
2109         if (new_bmcr != bmcr) {
2110                 u32 bmsr;
2111
2112                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2113                 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2114
2115                 if (bmsr & BMSR_LSTATUS) {
2116                         /* Force link down */
2117                         bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2118                         spin_unlock_bh(&bp->phy_lock);
2119                         msleep(50);
2120                         spin_lock_bh(&bp->phy_lock);
2121
2122                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2123                         bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2124                 }
2125
2126                 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2127
2128                 /* Normally, the new speed is setup after the link has
2129                  * gone down and up again. In some cases, link will not go
2130                  * down so we need to set up the new speed here.
2131                  */
2132                 if (bmsr & BMSR_LSTATUS) {
2133                         bp->line_speed = bp->req_line_speed;
2134                         bp->duplex = bp->req_duplex;
2135                         bnx2_resolve_flow_ctrl(bp);
2136                         bnx2_set_mac_link(bp);
2137                 }
2138         } else {
2139                 bnx2_resolve_flow_ctrl(bp);
2140                 bnx2_set_mac_link(bp);
2141         }
2142         return 0;
2143 }
2144
2145 static int
2146 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2147 __releases(&bp->phy_lock)
2148 __acquires(&bp->phy_lock)
2149 {
2150         if (bp->loopback == MAC_LOOPBACK)
2151                 return 0;
2152
2153         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2154                 return (bnx2_setup_serdes_phy(bp, port));
2155         }
2156         else {
2157                 return (bnx2_setup_copper_phy(bp));
2158         }
2159 }
2160
2161 static int
2162 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2163 {
2164         u32 val;
2165
2166         bp->mii_bmcr = MII_BMCR + 0x10;
2167         bp->mii_bmsr = MII_BMSR + 0x10;
2168         bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2169         bp->mii_adv = MII_ADVERTISE + 0x10;
2170         bp->mii_lpa = MII_LPA + 0x10;
2171         bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2172
2173         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2174         bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2175
2176         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2177         if (reset_phy)
2178                 bnx2_reset_phy(bp);
2179
2180         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2181
2182         bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2183         val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2184         val |= MII_BNX2_SD_1000XCTL1_FIBER;
2185         bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2186
2187         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2188         bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2189         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2190                 val |= BCM5708S_UP1_2G5;
2191         else
2192                 val &= ~BCM5708S_UP1_2G5;
2193         bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2194
2195         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2196         bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2197         val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2198         bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2199
2200         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2201
2202         val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2203               MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2204         bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2205
2206         bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2207
2208         return 0;
2209 }
2210
2211 static int
2212 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2213 {
2214         u32 val;
2215
2216         if (reset_phy)
2217                 bnx2_reset_phy(bp);
2218
2219         bp->mii_up1 = BCM5708S_UP1;
2220
2221         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2222         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2223         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2224
2225         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2226         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2227         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2228
2229         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2230         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2231         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2232
2233         if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2234                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2235                 val |= BCM5708S_UP1_2G5;
2236                 bnx2_write_phy(bp, BCM5708S_UP1, val);
2237         }
2238
2239         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2240             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2241             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2242                 /* increase tx signal amplitude */
2243                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2244                                BCM5708S_BLK_ADDR_TX_MISC);
2245                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2246                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2247                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2248                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2249         }
2250
2251         val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2252               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2253
2254         if (val) {
2255                 u32 is_backplane;
2256
2257                 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2258                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2259                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2260                                        BCM5708S_BLK_ADDR_TX_MISC);
2261                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2262                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2263                                        BCM5708S_BLK_ADDR_DIG);
2264                 }
2265         }
2266         return 0;
2267 }
2268
2269 static int
2270 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2271 {
2272         if (reset_phy)
2273                 bnx2_reset_phy(bp);
2274
2275         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2276
2277         if (CHIP_NUM(bp) == CHIP_NUM_5706)
2278                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2279
2280         if (bp->dev->mtu > 1500) {
2281                 u32 val;
2282
2283                 /* Set extended packet length bit */
2284                 bnx2_write_phy(bp, 0x18, 0x7);
2285                 bnx2_read_phy(bp, 0x18, &val);
2286                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2287
2288                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2289                 bnx2_read_phy(bp, 0x1c, &val);
2290                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2291         }
2292         else {
2293                 u32 val;
2294
2295                 bnx2_write_phy(bp, 0x18, 0x7);
2296                 bnx2_read_phy(bp, 0x18, &val);
2297                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2298
2299                 bnx2_write_phy(bp, 0x1c, 0x6c00);
2300                 bnx2_read_phy(bp, 0x1c, &val);
2301                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2302         }
2303
2304         return 0;
2305 }
2306
2307 static int
2308 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2309 {
2310         u32 val;
2311
2312         if (reset_phy)
2313                 bnx2_reset_phy(bp);
2314
2315         if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2316                 bnx2_write_phy(bp, 0x18, 0x0c00);
2317                 bnx2_write_phy(bp, 0x17, 0x000a);
2318                 bnx2_write_phy(bp, 0x15, 0x310b);
2319                 bnx2_write_phy(bp, 0x17, 0x201f);
2320                 bnx2_write_phy(bp, 0x15, 0x9506);
2321                 bnx2_write_phy(bp, 0x17, 0x401f);
2322                 bnx2_write_phy(bp, 0x15, 0x14e2);
2323                 bnx2_write_phy(bp, 0x18, 0x0400);
2324         }
2325
2326         if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2327                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2328                                MII_BNX2_DSP_EXPAND_REG | 0x8);
2329                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2330                 val &= ~(1 << 8);
2331                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2332         }
2333
2334         if (bp->dev->mtu > 1500) {
2335                 /* Set extended packet length bit */
2336                 bnx2_write_phy(bp, 0x18, 0x7);
2337                 bnx2_read_phy(bp, 0x18, &val);
2338                 bnx2_write_phy(bp, 0x18, val | 0x4000);
2339
2340                 bnx2_read_phy(bp, 0x10, &val);
2341                 bnx2_write_phy(bp, 0x10, val | 0x1);
2342         }
2343         else {
2344                 bnx2_write_phy(bp, 0x18, 0x7);
2345                 bnx2_read_phy(bp, 0x18, &val);
2346                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2347
2348                 bnx2_read_phy(bp, 0x10, &val);
2349                 bnx2_write_phy(bp, 0x10, val & ~0x1);
2350         }
2351
2352         /* ethernet@wirespeed */
2353         bnx2_write_phy(bp, 0x18, 0x7007);
2354         bnx2_read_phy(bp, 0x18, &val);
2355         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2356         return 0;
2357 }
2358
2359
2360 static int
2361 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2362 __releases(&bp->phy_lock)
2363 __acquires(&bp->phy_lock)
2364 {
2365         u32 val;
2366         int rc = 0;
2367
2368         bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2369         bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2370
2371         bp->mii_bmcr = MII_BMCR;
2372         bp->mii_bmsr = MII_BMSR;
2373         bp->mii_bmsr1 = MII_BMSR;
2374         bp->mii_adv = MII_ADVERTISE;
2375         bp->mii_lpa = MII_LPA;
2376
2377         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2378
2379         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2380                 goto setup_phy;
2381
2382         bnx2_read_phy(bp, MII_PHYSID1, &val);
2383         bp->phy_id = val << 16;
2384         bnx2_read_phy(bp, MII_PHYSID2, &val);
2385         bp->phy_id |= val & 0xffff;
2386
2387         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2388                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2389                         rc = bnx2_init_5706s_phy(bp, reset_phy);
2390                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2391                         rc = bnx2_init_5708s_phy(bp, reset_phy);
2392                 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2393                         rc = bnx2_init_5709s_phy(bp, reset_phy);
2394         }
2395         else {
2396                 rc = bnx2_init_copper_phy(bp, reset_phy);
2397         }
2398
2399 setup_phy:
2400         if (!rc)
2401                 rc = bnx2_setup_phy(bp, bp->phy_port);
2402
2403         return rc;
2404 }
2405
2406 static int
2407 bnx2_set_mac_loopback(struct bnx2 *bp)
2408 {
2409         u32 mac_mode;
2410
2411         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2412         mac_mode &= ~BNX2_EMAC_MODE_PORT;
2413         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2414         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2415         bp->link_up = 1;
2416         return 0;
2417 }
2418
2419 static int bnx2_test_link(struct bnx2 *);
2420
2421 static int
2422 bnx2_set_phy_loopback(struct bnx2 *bp)
2423 {
2424         u32 mac_mode;
2425         int rc, i;
2426
2427         spin_lock_bh(&bp->phy_lock);
2428         rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2429                             BMCR_SPEED1000);
2430         spin_unlock_bh(&bp->phy_lock);
2431         if (rc)
2432                 return rc;
2433
2434         for (i = 0; i < 10; i++) {
2435                 if (bnx2_test_link(bp) == 0)
2436                         break;
2437                 msleep(100);
2438         }
2439
2440         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2441         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2442                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2443                       BNX2_EMAC_MODE_25G_MODE);
2444
2445         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2446         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2447         bp->link_up = 1;
2448         return 0;
2449 }
2450
2451 static int
2452 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2453 {
2454         int i;
2455         u32 val;
2456
2457         bp->fw_wr_seq++;
2458         msg_data |= bp->fw_wr_seq;
2459
2460         bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2461
2462         if (!ack)
2463                 return 0;
2464
2465         /* wait for an acknowledgement. */
2466         for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2467                 msleep(10);
2468
2469                 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2470
2471                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2472                         break;
2473         }
2474         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2475                 return 0;
2476
2477         /* If we timed out, inform the firmware that this is the case. */
2478         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2479                 if (!silent)
2480                         pr_err("fw sync timeout, reset code = %x\n", msg_data);
2481
2482                 msg_data &= ~BNX2_DRV_MSG_CODE;
2483                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2484
2485                 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2486
2487                 return -EBUSY;
2488         }
2489
2490         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2491                 return -EIO;
2492
2493         return 0;
2494 }
2495
2496 static int
2497 bnx2_init_5709_context(struct bnx2 *bp)
2498 {
2499         int i, ret = 0;
2500         u32 val;
2501
2502         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2503         val |= (BCM_PAGE_BITS - 8) << 16;
2504         REG_WR(bp, BNX2_CTX_COMMAND, val);
2505         for (i = 0; i < 10; i++) {
2506                 val = REG_RD(bp, BNX2_CTX_COMMAND);
2507                 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2508                         break;
2509                 udelay(2);
2510         }
2511         if (val & BNX2_CTX_COMMAND_MEM_INIT)
2512                 return -EBUSY;
2513
2514         for (i = 0; i < bp->ctx_pages; i++) {
2515                 int j;
2516
2517                 if (bp->ctx_blk[i])
2518                         memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2519                 else
2520                         return -ENOMEM;
2521
2522                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2523                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
2524                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2525                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2526                        (u64) bp->ctx_blk_mapping[i] >> 32);
2527                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2528                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2529                 for (j = 0; j < 10; j++) {
2530
2531                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2532                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2533                                 break;
2534                         udelay(5);
2535                 }
2536                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2537                         ret = -EBUSY;
2538                         break;
2539                 }
2540         }
2541         return ret;
2542 }
2543
2544 static void
2545 bnx2_init_context(struct bnx2 *bp)
2546 {
2547         u32 vcid;
2548
2549         vcid = 96;
2550         while (vcid) {
2551                 u32 vcid_addr, pcid_addr, offset;
2552                 int i;
2553
2554                 vcid--;
2555
2556                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2557                         u32 new_vcid;
2558
2559                         vcid_addr = GET_PCID_ADDR(vcid);
2560                         if (vcid & 0x8) {
2561                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2562                         }
2563                         else {
2564                                 new_vcid = vcid;
2565                         }
2566                         pcid_addr = GET_PCID_ADDR(new_vcid);
2567                 }
2568                 else {
2569                         vcid_addr = GET_CID_ADDR(vcid);
2570                         pcid_addr = vcid_addr;
2571                 }
2572
2573                 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2574                         vcid_addr += (i << PHY_CTX_SHIFT);
2575                         pcid_addr += (i << PHY_CTX_SHIFT);
2576
2577                         REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2578                         REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2579
2580                         /* Zero out the context. */
2581                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2582                                 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2583                 }
2584         }
2585 }
2586
2587 static int
2588 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2589 {
2590         u16 *good_mbuf;
2591         u32 good_mbuf_cnt;
2592         u32 val;
2593
2594         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2595         if (good_mbuf == NULL) {
2596                 pr_err("Failed to allocate memory in %s\n", __func__);
2597                 return -ENOMEM;
2598         }
2599
2600         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2601                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2602
2603         good_mbuf_cnt = 0;
2604
2605         /* Allocate a bunch of mbufs and save the good ones in an array. */
2606         val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2607         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2608                 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2609                                 BNX2_RBUF_COMMAND_ALLOC_REQ);
2610
2611                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2612
2613                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2614
2615                 /* The addresses with Bit 9 set are bad memory blocks. */
2616                 if (!(val & (1 << 9))) {
2617                         good_mbuf[good_mbuf_cnt] = (u16) val;
2618                         good_mbuf_cnt++;
2619                 }
2620
2621                 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2622         }
2623
2624         /* Free the good ones back to the mbuf pool thus discarding
2625          * all the bad ones. */
2626         while (good_mbuf_cnt) {
2627                 good_mbuf_cnt--;
2628
2629                 val = good_mbuf[good_mbuf_cnt];
2630                 val = (val << 9) | val | 1;
2631
2632                 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2633         }
2634         kfree(good_mbuf);
2635         return 0;
2636 }
2637
2638 static void
2639 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2640 {
2641         u32 val;
2642
2643         val = (mac_addr[0] << 8) | mac_addr[1];
2644
2645         REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2646
2647         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2648                 (mac_addr[4] << 8) | mac_addr[5];
2649
2650         REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2651 }
2652
2653 static inline int
2654 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2655 {
2656         dma_addr_t mapping;
2657         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2658         struct rx_bd *rxbd =
2659                 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2660         struct page *page = alloc_page(GFP_ATOMIC);
2661
2662         if (!page)
2663                 return -ENOMEM;
2664         mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2665                                PCI_DMA_FROMDEVICE);
2666         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2667                 __free_page(page);
2668                 return -EIO;
2669         }
2670
2671         rx_pg->page = page;
2672         dma_unmap_addr_set(rx_pg, mapping, mapping);
2673         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2674         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2675         return 0;
2676 }
2677
2678 static void
2679 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2680 {
2681         struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2682         struct page *page = rx_pg->page;
2683
2684         if (!page)
2685                 return;
2686
2687         pci_unmap_page(bp->pdev, dma_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2688                        PCI_DMA_FROMDEVICE);
2689
2690         __free_page(page);
2691         rx_pg->page = NULL;
2692 }
2693
2694 static inline int
2695 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2696 {
2697         struct sk_buff *skb;
2698         struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2699         dma_addr_t mapping;
2700         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2701         unsigned long align;
2702
2703         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2704         if (skb == NULL) {
2705                 return -ENOMEM;
2706         }
2707
2708         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2709                 skb_reserve(skb, BNX2_RX_ALIGN - align);
2710
2711         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2712                 PCI_DMA_FROMDEVICE);
2713         if (pci_dma_mapping_error(bp->pdev, mapping)) {
2714                 dev_kfree_skb(skb);
2715                 return -EIO;
2716         }
2717
2718         rx_buf->skb = skb;
2719         rx_buf->desc = (struct l2_fhdr *) skb->data;
2720         dma_unmap_addr_set(rx_buf, mapping, mapping);
2721
2722         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2723         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2724
2725         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2726
2727         return 0;
2728 }
2729
2730 static int
2731 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2732 {
2733         struct status_block *sblk = bnapi->status_blk.msi;
2734         u32 new_link_state, old_link_state;
2735         int is_set = 1;
2736
2737         new_link_state = sblk->status_attn_bits & event;
2738         old_link_state = sblk->status_attn_bits_ack & event;
2739         if (new_link_state != old_link_state) {
2740                 if (new_link_state)
2741                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2742                 else
2743                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2744         } else
2745                 is_set = 0;
2746
2747         return is_set;
2748 }
2749
2750 static void
2751 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2752 {
2753         spin_lock(&bp->phy_lock);
2754
2755         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2756                 bnx2_set_link(bp);
2757         if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2758                 bnx2_set_remote_link(bp);
2759
2760         spin_unlock(&bp->phy_lock);
2761
2762 }
2763
2764 static inline u16
2765 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2766 {
2767         u16 cons;
2768
2769         /* Tell compiler that status block fields can change. */
2770         barrier();
2771         cons = *bnapi->hw_tx_cons_ptr;
2772         barrier();
2773         if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2774                 cons++;
2775         return cons;
2776 }
2777
2778 static int
2779 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2780 {
2781         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2782         u16 hw_cons, sw_cons, sw_ring_cons;
2783         int tx_pkt = 0, index;
2784         struct netdev_queue *txq;
2785
2786         index = (bnapi - bp->bnx2_napi);
2787         txq = netdev_get_tx_queue(bp->dev, index);
2788
2789         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2790         sw_cons = txr->tx_cons;
2791
2792         while (sw_cons != hw_cons) {
2793                 struct sw_tx_bd *tx_buf;
2794                 struct sk_buff *skb;
2795                 int i, last;
2796
2797                 sw_ring_cons = TX_RING_IDX(sw_cons);
2798
2799                 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2800                 skb = tx_buf->skb;
2801
2802                 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2803                 prefetch(&skb->end);
2804
2805                 /* partial BD completions possible with TSO packets */
2806                 if (tx_buf->is_gso) {
2807                         u16 last_idx, last_ring_idx;
2808
2809                         last_idx = sw_cons + tx_buf->nr_frags + 1;
2810                         last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2811                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2812                                 last_idx++;
2813                         }
2814                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2815                                 break;
2816                         }
2817                 }
2818
2819                 pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
2820                         skb_headlen(skb), PCI_DMA_TODEVICE);
2821
2822                 tx_buf->skb = NULL;
2823                 last = tx_buf->nr_frags;
2824
2825                 for (i = 0; i < last; i++) {
2826                         sw_cons = NEXT_TX_BD(sw_cons);
2827
2828                         pci_unmap_page(bp->pdev,
2829                                 dma_unmap_addr(
2830                                         &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2831                                         mapping),
2832                                 skb_shinfo(skb)->frags[i].size,
2833                                 PCI_DMA_TODEVICE);
2834                 }
2835
2836                 sw_cons = NEXT_TX_BD(sw_cons);
2837
2838                 dev_kfree_skb(skb);
2839                 tx_pkt++;
2840                 if (tx_pkt == budget)
2841                         break;
2842
2843                 if (hw_cons == sw_cons)
2844                         hw_cons = bnx2_get_hw_tx_cons(bnapi);
2845         }
2846
2847         txr->hw_tx_cons = hw_cons;
2848         txr->tx_cons = sw_cons;
2849
2850         /* Need to make the tx_cons update visible to bnx2_start_xmit()
2851          * before checking for netif_tx_queue_stopped().  Without the
2852          * memory barrier, there is a small possibility that bnx2_start_xmit()
2853          * will miss it and cause the queue to be stopped forever.
2854          */
2855         smp_mb();
2856
2857         if (unlikely(netif_tx_queue_stopped(txq)) &&
2858                      (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2859                 __netif_tx_lock(txq, smp_processor_id());
2860                 if ((netif_tx_queue_stopped(txq)) &&
2861                     (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2862                         netif_tx_wake_queue(txq);
2863                 __netif_tx_unlock(txq);
2864         }
2865
2866         return tx_pkt;
2867 }
2868
2869 static void
2870 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2871                         struct sk_buff *skb, int count)
2872 {
2873         struct sw_pg *cons_rx_pg, *prod_rx_pg;
2874         struct rx_bd *cons_bd, *prod_bd;
2875         int i;
2876         u16 hw_prod, prod;
2877         u16 cons = rxr->rx_pg_cons;
2878
2879         cons_rx_pg = &rxr->rx_pg_ring[cons];
2880
2881         /* The caller was unable to allocate a new page to replace the
2882          * last one in the frags array, so we need to recycle that page
2883          * and then free the skb.
2884          */
2885         if (skb) {
2886                 struct page *page;
2887                 struct skb_shared_info *shinfo;
2888
2889                 shinfo = skb_shinfo(skb);
2890                 shinfo->nr_frags--;
2891                 page = shinfo->frags[shinfo->nr_frags].page;
2892                 shinfo->frags[shinfo->nr_frags].page = NULL;
2893
2894                 cons_rx_pg->page = page;
2895                 dev_kfree_skb(skb);
2896         }
2897
2898         hw_prod = rxr->rx_pg_prod;
2899
2900         for (i = 0; i < count; i++) {
2901                 prod = RX_PG_RING_IDX(hw_prod);
2902
2903                 prod_rx_pg = &rxr->rx_pg_ring[prod];
2904                 cons_rx_pg = &rxr->rx_pg_ring[cons];
2905                 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2906                 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2907
2908                 if (prod != cons) {
2909                         prod_rx_pg->page = cons_rx_pg->page;
2910                         cons_rx_pg->page = NULL;
2911                         dma_unmap_addr_set(prod_rx_pg, mapping,
2912                                 dma_unmap_addr(cons_rx_pg, mapping));
2913
2914                         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2915                         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2916
2917                 }
2918                 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2919                 hw_prod = NEXT_RX_BD(hw_prod);
2920         }
2921         rxr->rx_pg_prod = hw_prod;
2922         rxr->rx_pg_cons = cons;
2923 }
2924
2925 static inline void
2926 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2927                   struct sk_buff *skb, u16 cons, u16 prod)
2928 {
2929         struct sw_bd *cons_rx_buf, *prod_rx_buf;
2930         struct rx_bd *cons_bd, *prod_bd;
2931
2932         cons_rx_buf = &rxr->rx_buf_ring[cons];
2933         prod_rx_buf = &rxr->rx_buf_ring[prod];
2934
2935         pci_dma_sync_single_for_device(bp->pdev,
2936                 dma_unmap_addr(cons_rx_buf, mapping),
2937                 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2938
2939         rxr->rx_prod_bseq += bp->rx_buf_use_size;
2940
2941         prod_rx_buf->skb = skb;
2942         prod_rx_buf->desc = (struct l2_fhdr *) skb->data;
2943
2944         if (cons == prod)
2945                 return;
2946
2947         dma_unmap_addr_set(prod_rx_buf, mapping,
2948                         dma_unmap_addr(cons_rx_buf, mapping));
2949
2950         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2951         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2952         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2953         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2954 }
2955
2956 static int
2957 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2958             unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2959             u32 ring_idx)
2960 {
2961         int err;
2962         u16 prod = ring_idx & 0xffff;
2963
2964         err = bnx2_alloc_rx_skb(bp, rxr, prod);
2965         if (unlikely(err)) {
2966                 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2967                 if (hdr_len) {
2968                         unsigned int raw_len = len + 4;
2969                         int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2970
2971                         bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2972                 }
2973                 return err;
2974         }
2975
2976         skb_reserve(skb, BNX2_RX_OFFSET);
2977         pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2978                          PCI_DMA_FROMDEVICE);
2979
2980         if (hdr_len == 0) {
2981                 skb_put(skb, len);
2982                 return 0;
2983         } else {
2984                 unsigned int i, frag_len, frag_size, pages;
2985                 struct sw_pg *rx_pg;
2986                 u16 pg_cons = rxr->rx_pg_cons;
2987                 u16 pg_prod = rxr->rx_pg_prod;
2988
2989                 frag_size = len + 4 - hdr_len;
2990                 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2991                 skb_put(skb, hdr_len);
2992
2993                 for (i = 0; i < pages; i++) {
2994                         dma_addr_t mapping_old;
2995
2996                         frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2997                         if (unlikely(frag_len <= 4)) {
2998                                 unsigned int tail = 4 - frag_len;
2999
3000                                 rxr->rx_pg_cons = pg_cons;
3001                                 rxr->rx_pg_prod = pg_prod;
3002                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3003                                                         pages - i);
3004                                 skb->len -= tail;
3005                                 if (i == 0) {
3006                                         skb->tail -= tail;
3007                                 } else {
3008                                         skb_frag_t *frag =
3009                                                 &skb_shinfo(skb)->frags[i - 1];
3010                                         frag->size -= tail;
3011                                         skb->data_len -= tail;
3012                                         skb->truesize -= tail;
3013                                 }
3014                                 return 0;
3015                         }
3016                         rx_pg = &rxr->rx_pg_ring[pg_cons];
3017
3018                         /* Don't unmap yet.  If we're unable to allocate a new
3019                          * page, we need to recycle the page and the DMA addr.
3020                          */
3021                         mapping_old = dma_unmap_addr(rx_pg, mapping);
3022                         if (i == pages - 1)
3023                                 frag_len -= 4;
3024
3025                         skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3026                         rx_pg->page = NULL;
3027
3028                         err = bnx2_alloc_rx_page(bp, rxr,
3029                                                  RX_PG_RING_IDX(pg_prod));
3030                         if (unlikely(err)) {
3031                                 rxr->rx_pg_cons = pg_cons;
3032                                 rxr->rx_pg_prod = pg_prod;
3033                                 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3034                                                         pages - i);
3035                                 return err;
3036                         }
3037
3038                         pci_unmap_page(bp->pdev, mapping_old,
3039                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
3040
3041                         frag_size -= frag_len;
3042                         skb->data_len += frag_len;
3043                         skb->truesize += frag_len;
3044                         skb->len += frag_len;
3045
3046                         pg_prod = NEXT_RX_BD(pg_prod);
3047                         pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3048                 }
3049                 rxr->rx_pg_prod = pg_prod;
3050                 rxr->rx_pg_cons = pg_cons;
3051         }
3052         return 0;
3053 }
3054
3055 static inline u16
3056 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3057 {
3058         u16 cons;
3059
3060         /* Tell compiler that status block fields can change. */
3061         barrier();
3062         cons = *bnapi->hw_rx_cons_ptr;
3063         barrier();
3064         if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3065                 cons++;
3066         return cons;
3067 }
3068
3069 static int
3070 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3071 {
3072         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3073         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3074         struct l2_fhdr *rx_hdr;
3075         int rx_pkt = 0, pg_ring_used = 0;
3076
3077         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3078         sw_cons = rxr->rx_cons;
3079         sw_prod = rxr->rx_prod;
3080
3081         /* Memory barrier necessary as speculative reads of the rx
3082          * buffer can be ahead of the index in the status block
3083          */
3084         rmb();
3085         while (sw_cons != hw_cons) {
3086                 unsigned int len, hdr_len;
3087                 u32 status;
3088                 struct sw_bd *rx_buf, *next_rx_buf;
3089                 struct sk_buff *skb;
3090                 dma_addr_t dma_addr;
3091                 u16 vtag = 0;
3092                 int hw_vlan __maybe_unused = 0;
3093
3094                 sw_ring_cons = RX_RING_IDX(sw_cons);
3095                 sw_ring_prod = RX_RING_IDX(sw_prod);
3096
3097                 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3098                 skb = rx_buf->skb;
3099                 prefetchw(skb);
3100
3101                 next_rx_buf =
3102                         &rxr->rx_buf_ring[RX_RING_IDX(NEXT_RX_BD(sw_cons))];
3103                 prefetch(next_rx_buf->desc);
3104
3105                 rx_buf->skb = NULL;
3106
3107                 dma_addr = dma_unmap_addr(rx_buf, mapping);
3108
3109                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3110                         BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3111                         PCI_DMA_FROMDEVICE);
3112
3113                 rx_hdr = rx_buf->desc;
3114                 len = rx_hdr->l2_fhdr_pkt_len;
3115                 status = rx_hdr->l2_fhdr_status;
3116
3117                 hdr_len = 0;
3118                 if (status & L2_FHDR_STATUS_SPLIT) {
3119                         hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3120                         pg_ring_used = 1;
3121                 } else if (len > bp->rx_jumbo_thresh) {
3122                         hdr_len = bp->rx_jumbo_thresh;
3123                         pg_ring_used = 1;
3124                 }
3125
3126                 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3127                                        L2_FHDR_ERRORS_PHY_DECODE |
3128                                        L2_FHDR_ERRORS_ALIGNMENT |
3129                                        L2_FHDR_ERRORS_TOO_SHORT |
3130                                        L2_FHDR_ERRORS_GIANT_FRAME))) {
3131
3132                         bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3133                                           sw_ring_prod);
3134                         if (pg_ring_used) {
3135                                 int pages;
3136
3137                                 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3138
3139                                 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3140                         }
3141                         goto next_rx;
3142                 }
3143
3144                 len -= 4;
3145
3146                 if (len <= bp->rx_copy_thresh) {
3147                         struct sk_buff *new_skb;
3148
3149                         new_skb = netdev_alloc_skb(bp->dev, len + 6);
3150                         if (new_skb == NULL) {
3151                                 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3152                                                   sw_ring_prod);
3153                                 goto next_rx;
3154                         }
3155
3156                         /* aligned copy */
3157                         skb_copy_from_linear_data_offset(skb,
3158                                                          BNX2_RX_OFFSET - 6,
3159                                       new_skb->data, len + 6);
3160                         skb_reserve(new_skb, 6);
3161                         skb_put(new_skb, len);
3162
3163                         bnx2_reuse_rx_skb(bp, rxr, skb,
3164                                 sw_ring_cons, sw_ring_prod);
3165
3166                         skb = new_skb;
3167                 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3168                            dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3169                         goto next_rx;
3170
3171                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3172                     !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3173                         vtag = rx_hdr->l2_fhdr_vlan_tag;
3174 #ifdef BCM_VLAN
3175                         if (bp->vlgrp)
3176                                 hw_vlan = 1;
3177                         else
3178 #endif
3179                         {
3180                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3181                                         __skb_push(skb, 4);
3182
3183                                 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3184                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
3185                                 ve->h_vlan_TCI = htons(vtag);
3186                                 len += 4;
3187                         }
3188                 }
3189
3190                 skb->protocol = eth_type_trans(skb, bp->dev);
3191
3192                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3193                         (ntohs(skb->protocol) != 0x8100)) {
3194
3195                         dev_kfree_skb(skb);
3196                         goto next_rx;
3197
3198                 }
3199
3200                 skb->ip_summed = CHECKSUM_NONE;
3201                 if (bp->rx_csum &&
3202                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3203                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
3204
3205                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3206                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3207                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3208                 }
3209
3210                 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3211
3212 #ifdef BCM_VLAN
3213                 if (hw_vlan)
3214                         vlan_gro_receive(&bnapi->napi, bp->vlgrp, vtag, skb);
3215                 else
3216 #endif
3217                         napi_gro_receive(&bnapi->napi, skb);
3218
3219                 rx_pkt++;
3220
3221 next_rx:
3222                 sw_cons = NEXT_RX_BD(sw_cons);
3223                 sw_prod = NEXT_RX_BD(sw_prod);
3224
3225                 if ((rx_pkt == budget))
3226                         break;
3227
3228                 /* Refresh hw_cons to see if there is new work */
3229                 if (sw_cons == hw_cons) {
3230                         hw_cons = bnx2_get_hw_rx_cons(bnapi);
3231                         rmb();
3232                 }
3233         }
3234         rxr->rx_cons = sw_cons;
3235         rxr->rx_prod = sw_prod;
3236
3237         if (pg_ring_used)
3238                 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3239
3240         REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3241
3242         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3243
3244         mmiowb();
3245
3246         return rx_pkt;
3247
3248 }
3249
3250 /* MSI ISR - The only difference between this and the INTx ISR
3251  * is that the MSI interrupt is always serviced.
3252  */
3253 static irqreturn_t
3254 bnx2_msi(int irq, void *dev_instance)
3255 {
3256         struct bnx2_napi *bnapi = dev_instance;
3257         struct bnx2 *bp = bnapi->bp;
3258
3259         prefetch(bnapi->status_blk.msi);
3260         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3261                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3262                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3263
3264         /* Return here if interrupt is disabled. */
3265         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3266                 return IRQ_HANDLED;
3267
3268         napi_schedule(&bnapi->napi);
3269
3270         return IRQ_HANDLED;
3271 }
3272
3273 static irqreturn_t
3274 bnx2_msi_1shot(int irq, void *dev_instance)
3275 {
3276         struct bnx2_napi *bnapi = dev_instance;
3277         struct bnx2 *bp = bnapi->bp;
3278
3279         prefetch(bnapi->status_blk.msi);
3280
3281         /* Return here if interrupt is disabled. */
3282         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3283                 return IRQ_HANDLED;
3284
3285         napi_schedule(&bnapi->napi);
3286
3287         return IRQ_HANDLED;
3288 }
3289
3290 static irqreturn_t
3291 bnx2_interrupt(int irq, void *dev_instance)
3292 {
3293         struct bnx2_napi *bnapi = dev_instance;
3294         struct bnx2 *bp = bnapi->bp;
3295         struct status_block *sblk = bnapi->status_blk.msi;
3296
3297         /* When using INTx, it is possible for the interrupt to arrive
3298          * at the CPU before the status block posted prior to the
3299          * interrupt. Reading a register will flush the status block.
3300          * When using MSI, the MSI message will always complete after
3301          * the status block write.
3302          */
3303         if ((sblk->status_idx == bnapi->last_status_idx) &&
3304             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3305              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3306                 return IRQ_NONE;
3307
3308         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3309                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3310                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3311
3312         /* Read back to deassert IRQ immediately to avoid too many
3313          * spurious interrupts.
3314          */
3315         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3316
3317         /* Return here if interrupt is shared and is disabled. */
3318         if (unlikely(atomic_read(&bp->intr_sem) != 0))
3319                 return IRQ_HANDLED;
3320
3321         if (napi_schedule_prep(&bnapi->napi)) {
3322                 bnapi->last_status_idx = sblk->status_idx;
3323                 __napi_schedule(&bnapi->napi);
3324         }
3325
3326         return IRQ_HANDLED;
3327 }
3328
3329 static inline int
3330 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3331 {
3332         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3333         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3334
3335         if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3336             (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3337                 return 1;
3338         return 0;
3339 }
3340
3341 #define STATUS_ATTN_EVENTS      (STATUS_ATTN_BITS_LINK_STATE | \
3342                                  STATUS_ATTN_BITS_TIMER_ABORT)
3343
3344 static inline int
3345 bnx2_has_work(struct bnx2_napi *bnapi)
3346 {
3347         struct status_block *sblk = bnapi->status_blk.msi;
3348
3349         if (bnx2_has_fast_work(bnapi))
3350                 return 1;
3351
3352 #ifdef BCM_CNIC
3353         if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3354                 return 1;
3355 #endif
3356
3357         if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3358             (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3359                 return 1;
3360
3361         return 0;
3362 }
3363
3364 static void
3365 bnx2_chk_missed_msi(struct bnx2 *bp)
3366 {
3367         struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3368         u32 msi_ctrl;
3369
3370         if (bnx2_has_work(bnapi)) {
3371                 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3372                 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3373                         return;
3374
3375                 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3376                         REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3377                                ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3378                         REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3379                         bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3380                 }
3381         }
3382
3383         bp->idle_chk_status_idx = bnapi->last_status_idx;
3384 }
3385
3386 #ifdef BCM_CNIC
3387 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3388 {
3389         struct cnic_ops *c_ops;
3390
3391         if (!bnapi->cnic_present)
3392                 return;
3393
3394         rcu_read_lock();
3395         c_ops = rcu_dereference(bp->cnic_ops);
3396         if (c_ops)
3397                 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3398                                                       bnapi->status_blk.msi);
3399         rcu_read_unlock();
3400 }
3401 #endif
3402
3403 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3404 {
3405         struct status_block *sblk = bnapi->status_blk.msi;
3406         u32 status_attn_bits = sblk->status_attn_bits;
3407         u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3408
3409         if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3410             (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3411
3412                 bnx2_phy_int(bp, bnapi);
3413
3414                 /* This is needed to take care of transient status
3415                  * during link changes.
3416                  */
3417                 REG_WR(bp, BNX2_HC_COMMAND,
3418                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3419                 REG_RD(bp, BNX2_HC_COMMAND);
3420         }
3421 }
3422
3423 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3424                           int work_done, int budget)
3425 {
3426         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3427         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3428
3429         if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3430                 bnx2_tx_int(bp, bnapi, 0);
3431
3432         if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3433                 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3434
3435         return work_done;
3436 }
3437
3438 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3439 {
3440         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3441         struct bnx2 *bp = bnapi->bp;
3442         int work_done = 0;
3443         struct status_block_msix *sblk = bnapi->status_blk.msix;
3444
3445         while (1) {
3446                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3447                 if (unlikely(work_done >= budget))
3448                         break;
3449
3450                 bnapi->last_status_idx = sblk->status_idx;
3451                 /* status idx must be read before checking for more work. */
3452                 rmb();
3453                 if (likely(!bnx2_has_fast_work(bnapi))) {
3454
3455                         napi_complete(napi);
3456                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3457                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3458                                bnapi->last_status_idx);
3459                         break;
3460                 }
3461         }
3462         return work_done;
3463 }
3464
3465 static int bnx2_poll(struct napi_struct *napi, int budget)
3466 {
3467         struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3468         struct bnx2 *bp = bnapi->bp;
3469         int work_done = 0;
3470         struct status_block *sblk = bnapi->status_blk.msi;
3471
3472         while (1) {
3473                 bnx2_poll_link(bp, bnapi);
3474
3475                 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3476
3477 #ifdef BCM_CNIC
3478                 bnx2_poll_cnic(bp, bnapi);
3479 #endif
3480
3481                 /* bnapi->last_status_idx is used below to tell the hw how
3482                  * much work has been processed, so we must read it before
3483                  * checking for more work.
3484                  */
3485                 bnapi->last_status_idx = sblk->status_idx;
3486
3487                 if (unlikely(work_done >= budget))
3488                         break;
3489
3490                 rmb();
3491                 if (likely(!bnx2_has_work(bnapi))) {
3492                         napi_complete(napi);
3493                         if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3494                                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3495                                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3496                                        bnapi->last_status_idx);
3497                                 break;
3498                         }
3499                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3500                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3501                                BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3502                                bnapi->last_status_idx);
3503
3504                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3505                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3506                                bnapi->last_status_idx);
3507                         break;
3508                 }
3509         }
3510
3511         return work_done;
3512 }
3513
3514 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3515  * from set_multicast.
3516  */
3517 static void
3518 bnx2_set_rx_mode(struct net_device *dev)
3519 {
3520         struct bnx2 *bp = netdev_priv(dev);
3521         u32 rx_mode, sort_mode;
3522         struct netdev_hw_addr *ha;
3523         int i;
3524
3525         if (!netif_running(dev))
3526                 return;
3527
3528         spin_lock_bh(&bp->phy_lock);
3529
3530         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3531                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3532         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3533 #ifdef BCM_VLAN
3534         if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3535                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3536 #else
3537         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3538                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3539 #endif
3540         if (dev->flags & IFF_PROMISC) {
3541                 /* Promiscuous mode. */
3542                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3543                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3544                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3545         }
3546         else if (dev->flags & IFF_ALLMULTI) {
3547                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3548                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3549                                0xffffffff);
3550                 }
3551                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3552         }
3553         else {
3554                 /* Accept one or more multicast(s). */
3555                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3556                 u32 regidx;
3557                 u32 bit;
3558                 u32 crc;
3559
3560                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3561
3562                 netdev_for_each_mc_addr(ha, dev) {
3563                         crc = ether_crc_le(ETH_ALEN, ha->addr);
3564                         bit = crc & 0xff;
3565                         regidx = (bit & 0xe0) >> 5;
3566                         bit &= 0x1f;
3567                         mc_filter[regidx] |= (1 << bit);
3568                 }
3569
3570                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3571                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3572                                mc_filter[i]);
3573                 }
3574
3575                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3576         }
3577
3578         if (netdev_uc_count(dev) > BNX2_MAX_UNICAST_ADDRESSES) {
3579                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3580                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3581                              BNX2_RPM_SORT_USER0_PROM_VLAN;
3582         } else if (!(dev->flags & IFF_PROMISC)) {
3583                 /* Add all entries into to the match filter list */
3584                 i = 0;
3585                 netdev_for_each_uc_addr(ha, dev) {
3586                         bnx2_set_mac_addr(bp, ha->addr,
3587                                           i + BNX2_START_UNICAST_ADDRESS_INDEX);
3588                         sort_mode |= (1 <<
3589                                       (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3590                         i++;
3591                 }
3592
3593         }
3594
3595         if (rx_mode != bp->rx_mode) {
3596                 bp->rx_mode = rx_mode;
3597                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3598         }
3599
3600         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3601         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3602         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3603
3604         spin_unlock_bh(&bp->phy_lock);
3605 }
3606
3607 static int __devinit
3608 check_fw_section(const struct firmware *fw,
3609                  const struct bnx2_fw_file_section *section,
3610                  u32 alignment, bool non_empty)
3611 {
3612         u32 offset = be32_to_cpu(section->offset);
3613         u32 len = be32_to_cpu(section->len);
3614
3615         if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3616                 return -EINVAL;
3617         if ((non_empty && len == 0) || len > fw->size - offset ||
3618             len & (alignment - 1))
3619                 return -EINVAL;
3620         return 0;
3621 }
3622
3623 static int __devinit
3624 check_mips_fw_entry(const struct firmware *fw,
3625                     const struct bnx2_mips_fw_file_entry *entry)
3626 {
3627         if (check_fw_section(fw, &entry->text, 4, true) ||
3628             check_fw_section(fw, &entry->data, 4, false) ||
3629             check_fw_section(fw, &entry->rodata, 4, false))
3630                 return -EINVAL;
3631         return 0;
3632 }
3633
3634 static int __devinit
3635 bnx2_request_firmware(struct bnx2 *bp)
3636 {
3637         const char *mips_fw_file, *rv2p_fw_file;
3638         const struct bnx2_mips_fw_file *mips_fw;
3639         const struct bnx2_rv2p_fw_file *rv2p_fw;
3640         int rc;
3641
3642         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3643                 mips_fw_file = FW_MIPS_FILE_09;
3644                 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3645                     (CHIP_ID(bp) == CHIP_ID_5709_A1))
3646                         rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3647                 else
3648                         rv2p_fw_file = FW_RV2P_FILE_09;
3649         } else {
3650                 mips_fw_file = FW_MIPS_FILE_06;
3651                 rv2p_fw_file = FW_RV2P_FILE_06;
3652         }
3653
3654         rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3655         if (rc) {
3656                 pr_err("Can't load firmware file \"%s\"\n", mips_fw_file);
3657                 return rc;
3658         }
3659
3660         rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3661         if (rc) {
3662                 pr_err("Can't load firmware file \"%s\"\n", rv2p_fw_file);
3663                 return rc;
3664         }
3665         mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3666         rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3667         if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3668             check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3669             check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3670             check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3671             check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3672             check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3673                 pr_err("Firmware file \"%s\" is invalid\n", mips_fw_file);
3674                 return -EINVAL;
3675         }
3676         if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3677             check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3678             check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3679                 pr_err("Firmware file \"%s\" is invalid\n", rv2p_fw_file);
3680                 return -EINVAL;
3681         }
3682
3683         return 0;
3684 }
3685
3686 static u32
3687 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3688 {
3689         switch (idx) {
3690         case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3691                 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3692                 rv2p_code |= RV2P_BD_PAGE_SIZE;
3693                 break;
3694         }
3695         return rv2p_code;
3696 }
3697
3698 static int
3699 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3700              const struct bnx2_rv2p_fw_file_entry *fw_entry)
3701 {
3702         u32 rv2p_code_len, file_offset;
3703         __be32 *rv2p_code;
3704         int i;
3705         u32 val, cmd, addr;
3706
3707         rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3708         file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3709
3710         rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3711
3712         if (rv2p_proc == RV2P_PROC1) {
3713                 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3714                 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3715         } else {
3716                 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3717                 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3718         }
3719
3720         for (i = 0; i < rv2p_code_len; i += 8) {
3721                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3722                 rv2p_code++;
3723                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3724                 rv2p_code++;
3725
3726                 val = (i / 8) | cmd;
3727                 REG_WR(bp, addr, val);
3728         }
3729
3730         rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3731         for (i = 0; i < 8; i++) {
3732                 u32 loc, code;
3733
3734                 loc = be32_to_cpu(fw_entry->fixup[i]);
3735                 if (loc && ((loc * 4) < rv2p_code_len)) {
3736                         code = be32_to_cpu(*(rv2p_code + loc - 1));
3737                         REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3738                         code = be32_to_cpu(*(rv2p_code + loc));
3739                         code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3740                         REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3741
3742                         val = (loc / 2) | cmd;
3743                         REG_WR(bp, addr, val);
3744                 }
3745         }
3746
3747         /* Reset the processor, un-stall is done later. */
3748         if (rv2p_proc == RV2P_PROC1) {
3749                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3750         }
3751         else {
3752                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3753         }
3754
3755         return 0;
3756 }
3757
3758 static int
3759 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3760             const struct bnx2_mips_fw_file_entry *fw_entry)
3761 {
3762         u32 addr, len, file_offset;
3763         __be32 *data;
3764         u32 offset;
3765         u32 val;
3766
3767         /* Halt the CPU. */
3768         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3769         val |= cpu_reg->mode_value_halt;
3770         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3771         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3772
3773         /* Load the Text area. */
3774         addr = be32_to_cpu(fw_entry->text.addr);
3775         len = be32_to_cpu(fw_entry->text.len);
3776         file_offset = be32_to_cpu(fw_entry->text.offset);
3777         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3778
3779         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3780         if (len) {
3781                 int j;
3782
3783                 for (j = 0; j < (len / 4); j++, offset += 4)
3784                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3785         }
3786
3787         /* Load the Data area. */
3788         addr = be32_to_cpu(fw_entry->data.addr);
3789         len = be32_to_cpu(fw_entry->data.len);
3790         file_offset = be32_to_cpu(fw_entry->data.offset);
3791         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3792
3793         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3794         if (len) {
3795                 int j;
3796
3797                 for (j = 0; j < (len / 4); j++, offset += 4)
3798                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3799         }
3800
3801         /* Load the Read-Only area. */
3802         addr = be32_to_cpu(fw_entry->rodata.addr);
3803         len = be32_to_cpu(fw_entry->rodata.len);
3804         file_offset = be32_to_cpu(fw_entry->rodata.offset);
3805         data = (__be32 *)(bp->mips_firmware->data + file_offset);
3806
3807         offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3808         if (len) {
3809                 int j;
3810
3811                 for (j = 0; j < (len / 4); j++, offset += 4)
3812                         bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3813         }
3814
3815         /* Clear the pre-fetch instruction. */
3816         bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3817
3818         val = be32_to_cpu(fw_entry->start_addr);
3819         bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3820
3821         /* Start the CPU. */
3822         val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3823         val &= ~cpu_reg->mode_value_halt;
3824         bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3825         bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3826
3827         return 0;
3828 }
3829
3830 static int
3831 bnx2_init_cpus(struct bnx2 *bp)
3832 {
3833         const struct bnx2_mips_fw_file *mips_fw =
3834                 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3835         const struct bnx2_rv2p_fw_file *rv2p_fw =
3836                 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3837         int rc;
3838
3839         /* Initialize the RV2P processor. */
3840         load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3841         load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3842
3843         /* Initialize the RX Processor. */
3844         rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3845         if (rc)
3846                 goto init_cpu_err;
3847
3848         /* Initialize the TX Processor. */
3849         rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3850         if (rc)
3851                 goto init_cpu_err;
3852
3853         /* Initialize the TX Patch-up Processor. */
3854         rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3855         if (rc)
3856                 goto init_cpu_err;
3857
3858         /* Initialize the Completion Processor. */
3859         rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3860         if (rc)
3861                 goto init_cpu_err;
3862
3863         /* Initialize the Command Processor. */
3864         rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3865
3866 init_cpu_err:
3867         return rc;
3868 }
3869
3870 static int
3871 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3872 {
3873         u16 pmcsr;
3874
3875         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3876
3877         switch (state) {
3878         case PCI_D0: {
3879                 u32 val;
3880
3881                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3882                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3883                         PCI_PM_CTRL_PME_STATUS);
3884
3885                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3886                         /* delay required during transition out of D3hot */
3887                         msleep(20);
3888
3889                 val = REG_RD(bp, BNX2_EMAC_MODE);
3890                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3891                 val &= ~BNX2_EMAC_MODE_MPKT;
3892                 REG_WR(bp, BNX2_EMAC_MODE, val);
3893
3894                 val = REG_RD(bp, BNX2_RPM_CONFIG);
3895                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3896                 REG_WR(bp, BNX2_RPM_CONFIG, val);
3897                 break;
3898         }
3899         case PCI_D3hot: {
3900                 int i;
3901                 u32 val, wol_msg;
3902
3903                 if (bp->wol) {
3904                         u32 advertising;
3905                         u8 autoneg;
3906
3907                         autoneg = bp->autoneg;
3908                         advertising = bp->advertising;
3909
3910                         if (bp->phy_port == PORT_TP) {
3911                                 bp->autoneg = AUTONEG_SPEED;
3912                                 bp->advertising = ADVERTISED_10baseT_Half |
3913                                         ADVERTISED_10baseT_Full |
3914                                         ADVERTISED_100baseT_Half |
3915                                         ADVERTISED_100baseT_Full |
3916                                         ADVERTISED_Autoneg;
3917                         }
3918
3919                         spin_lock_bh(&bp->phy_lock);
3920                         bnx2_setup_phy(bp, bp->phy_port);
3921                         spin_unlock_bh(&bp->phy_lock);
3922
3923                         bp->autoneg = autoneg;
3924                         bp->advertising = advertising;
3925
3926                         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3927
3928                         val = REG_RD(bp, BNX2_EMAC_MODE);
3929
3930                         /* Enable port mode. */
3931                         val &= ~BNX2_EMAC_MODE_PORT;
3932                         val |= BNX2_EMAC_MODE_MPKT_RCVD |
3933                                BNX2_EMAC_MODE_ACPI_RCVD |
3934                                BNX2_EMAC_MODE_MPKT;
3935                         if (bp->phy_port == PORT_TP)
3936                                 val |= BNX2_EMAC_MODE_PORT_MII;
3937                         else {
3938                                 val |= BNX2_EMAC_MODE_PORT_GMII;
3939                                 if (bp->line_speed == SPEED_2500)
3940                                         val |= BNX2_EMAC_MODE_25G_MODE;
3941                         }
3942
3943                         REG_WR(bp, BNX2_EMAC_MODE, val);
3944
3945                         /* receive all multicast */
3946                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3947                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3948                                        0xffffffff);
3949                         }
3950                         REG_WR(bp, BNX2_EMAC_RX_MODE,
3951                                BNX2_EMAC_RX_MODE_SORT_MODE);
3952
3953                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3954                               BNX2_RPM_SORT_USER0_MC_EN;
3955                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3956                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3957                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3958                                BNX2_RPM_SORT_USER0_ENA);
3959
3960                         /* Need to enable EMAC and RPM for WOL. */
3961                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3962                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3963                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3964                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3965
3966                         val = REG_RD(bp, BNX2_RPM_CONFIG);
3967                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3968                         REG_WR(bp, BNX2_RPM_CONFIG, val);
3969
3970                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3971                 }
3972                 else {
3973                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3974                 }
3975
3976                 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3977                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3978                                      1, 0);
3979
3980                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3981                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3982                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3983
3984                         if (bp->wol)
3985                                 pmcsr |= 3;
3986                 }
3987                 else {
3988                         pmcsr |= 3;
3989                 }
3990                 if (bp->wol) {
3991                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3992                 }
3993                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3994                                       pmcsr);
3995
3996                 /* No more memory access after this point until
3997                  * device is brought back to D0.
3998                  */
3999                 udelay(50);
4000                 break;
4001         }
4002         default:
4003                 return -EINVAL;
4004         }
4005         return 0;
4006 }
4007
4008 static int
4009 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4010 {
4011         u32 val;
4012         int j;
4013
4014         /* Request access to the flash interface. */
4015         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4016         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4017                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4018                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4019                         break;
4020
4021                 udelay(5);
4022         }
4023
4024         if (j >= NVRAM_TIMEOUT_COUNT)
4025                 return -EBUSY;
4026
4027         return 0;
4028 }
4029
4030 static int
4031 bnx2_release_nvram_lock(struct bnx2 *bp)
4032 {
4033         int j;
4034         u32 val;
4035
4036         /* Relinquish nvram interface. */
4037         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4038
4039         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4040                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4041                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4042                         break;
4043
4044                 udelay(5);
4045         }
4046
4047         if (j >= NVRAM_TIMEOUT_COUNT)
4048                 return -EBUSY;
4049
4050         return 0;
4051 }
4052
4053
4054 static int
4055 bnx2_enable_nvram_write(struct bnx2 *bp)
4056 {
4057         u32 val;
4058
4059         val = REG_RD(bp, BNX2_MISC_CFG);
4060         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4061
4062         if (bp->flash_info->flags & BNX2_NV_WREN) {
4063                 int j;
4064
4065                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4066                 REG_WR(bp, BNX2_NVM_COMMAND,
4067                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4068
4069                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4070                         udelay(5);
4071
4072                         val = REG_RD(bp, BNX2_NVM_COMMAND);
4073                         if (val & BNX2_NVM_COMMAND_DONE)
4074                                 break;
4075                 }
4076
4077                 if (j >= NVRAM_TIMEOUT_COUNT)
4078                         return -EBUSY;
4079         }
4080         return 0;
4081 }
4082
4083 static void
4084 bnx2_disable_nvram_write(struct bnx2 *bp)
4085 {
4086         u32 val;
4087
4088         val = REG_RD(bp, BNX2_MISC_CFG);
4089         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4090 }
4091
4092
4093 static void
4094 bnx2_enable_nvram_access(struct bnx2 *bp)
4095 {
4096         u32 val;
4097
4098         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4099         /* Enable both bits, even on read. */
4100         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4101                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4102 }
4103
4104 static void
4105 bnx2_disable_nvram_access(struct bnx2 *bp)
4106 {
4107         u32 val;
4108
4109         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4110         /* Disable both bits, even after read. */
4111         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4112                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4113                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
4114 }
4115
4116 static int
4117 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4118 {
4119         u32 cmd;
4120         int j;
4121
4122         if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4123                 /* Buffered flash, no erase needed */
4124                 return 0;
4125
4126         /* Build an erase command */
4127         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4128               BNX2_NVM_COMMAND_DOIT;
4129
4130         /* Need to clear DONE bit separately. */
4131         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4132
4133         /* Address of the NVRAM to read from. */
4134         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4135
4136         /* Issue an erase command. */
4137         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4138
4139         /* Wait for completion. */
4140         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4141                 u32 val;
4142
4143                 udelay(5);
4144
4145                 val = REG_RD(bp, BNX2_NVM_COMMAND);
4146                 if (val & BNX2_NVM_COMMAND_DONE)
4147                         break;
4148         }
4149
4150         if (j >= NVRAM_TIMEOUT_COUNT)
4151                 return -EBUSY;
4152
4153         return 0;
4154 }
4155
4156 static int
4157 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4158 {
4159         u32 cmd;
4160         int j;
4161
4162         /* Build the command word. */
4163         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4164
4165         /* Calculate an offset of a buffered flash, not needed for 5709. */
4166         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4167                 offset = ((offset / bp->flash_info->page_size) <<
4168                            bp->flash_info->page_bits) +
4169                           (offset % bp->flash_info->page_size);
4170         }
4171
4172         /* Need to clear DONE bit separately. */
4173         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4174
4175         /* Address of the NVRAM to read from. */
4176         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4177
4178         /* Issue a read command. */
4179         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4180
4181         /* Wait for completion. */
4182         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4183                 u32 val;
4184
4185                 udelay(5);
4186
4187                 val = REG_RD(bp, BNX2_NVM_COMMAND);
4188                 if (val & BNX2_NVM_COMMAND_DONE) {
4189                         __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4190                         memcpy(ret_val, &v, 4);
4191                         break;
4192                 }
4193         }
4194         if (j >= NVRAM_TIMEOUT_COUNT)
4195                 return -EBUSY;
4196
4197         return 0;
4198 }
4199
4200
4201 static int
4202 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4203 {
4204         u32 cmd;
4205         __be32 val32;
4206         int j;
4207
4208         /* Build the command word. */
4209         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4210
4211         /* Calculate an offset of a buffered flash, not needed for 5709. */
4212         if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4213                 offset = ((offset / bp->flash_info->page_size) <<
4214                           bp->flash_info->page_bits) +
4215                          (offset % bp->flash_info->page_size);
4216         }
4217
4218         /* Need to clear DONE bit separately. */
4219         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4220
4221         memcpy(&val32, val, 4);
4222
4223         /* Write the data. */
4224         REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4225
4226         /* Address of the NVRAM to write to. */
4227         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4228
4229         /* Issue the write command. */
4230         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4231
4232         /* Wait for completion. */
4233         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4234                 udelay(5);
4235
4236                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4237                         break;
4238         }
4239         if (j >= NVRAM_TIMEOUT_COUNT)
4240                 return -EBUSY;
4241
4242         return 0;
4243 }
4244
4245 static int
4246 bnx2_init_nvram(struct bnx2 *bp)
4247 {
4248         u32 val;
4249         int j, entry_count, rc = 0;
4250         const struct flash_spec *flash;
4251
4252         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4253                 bp->flash_info = &flash_5709;
4254                 goto get_flash_size;
4255         }
4256
4257         /* Determine the selected interface. */
4258         val = REG_RD(bp, BNX2_NVM_CFG1);
4259
4260         entry_count = ARRAY_SIZE(flash_table);
4261
4262         if (val & 0x40000000) {
4263
4264                 /* Flash interface has been reconfigured */
4265                 for (j = 0, flash = &flash_table[0]; j < entry_count;
4266                      j++, flash++) {
4267                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
4268                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4269                                 bp->flash_info = flash;
4270                                 break;
4271                         }
4272                 }
4273         }
4274         else {
4275                 u32 mask;
4276                 /* Not yet been reconfigured */
4277
4278                 if (val & (1 << 23))
4279                         mask = FLASH_BACKUP_STRAP_MASK;
4280                 else
4281                         mask = FLASH_STRAP_MASK;
4282
4283                 for (j = 0, flash = &flash_table[0]; j < entry_count;
4284                         j++, flash++) {
4285
4286                         if ((val & mask) == (flash->strapping & mask)) {
4287                                 bp->flash_info = flash;
4288
4289                                 /* Request access to the flash interface. */
4290                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4291                                         return rc;
4292
4293                                 /* Enable access to flash interface */
4294                                 bnx2_enable_nvram_access(bp);
4295
4296                                 /* Reconfigure the flash interface */
4297                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4298                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4299                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4300                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4301
4302                                 /* Disable access to flash interface */
4303                                 bnx2_disable_nvram_access(bp);
4304                                 bnx2_release_nvram_lock(bp);
4305
4306                                 break;
4307                         }
4308                 }
4309         } /* if (val & 0x40000000) */
4310
4311         if (j == entry_count) {
4312                 bp->flash_info = NULL;
4313                 pr_alert("Unknown flash/EEPROM type\n");
4314                 return -ENODEV;
4315         }
4316
4317 get_flash_size:
4318         val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4319         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4320         if (val)
4321                 bp->flash_size = val;
4322         else
4323                 bp->flash_size = bp->flash_info->total_size;
4324
4325         return rc;
4326 }
4327
4328 static int
4329 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4330                 int buf_size)
4331 {
4332         int rc = 0;
4333         u32 cmd_flags, offset32, len32, extra;
4334
4335         if (buf_size == 0)
4336                 return 0;
4337
4338         /* Request access to the flash interface. */
4339         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4340                 return rc;
4341
4342         /* Enable access to flash interface */
4343         bnx2_enable_nvram_access(bp);
4344
4345         len32 = buf_size;
4346         offset32 = offset;
4347         extra = 0;
4348
4349         cmd_flags = 0;
4350
4351         if (offset32 & 3) {
4352                 u8 buf[4];
4353                 u32 pre_len;
4354
4355                 offset32 &= ~3;
4356                 pre_len = 4 - (offset & 3);
4357
4358                 if (pre_len >= len32) {
4359                         pre_len = len32;
4360                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4361                                     BNX2_NVM_COMMAND_LAST;
4362                 }
4363                 else {
4364                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4365                 }
4366
4367                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4368
4369                 if (rc)
4370                         return rc;
4371
4372                 memcpy(ret_buf, buf + (offset & 3), pre_len);
4373
4374                 offset32 += 4;
4375                 ret_buf += pre_len;
4376                 len32 -= pre_len;
4377         }
4378         if (len32 & 3) {
4379                 extra = 4 - (len32 & 3);
4380                 len32 = (len32 + 4) & ~3;
4381         }
4382
4383         if (len32 == 4) {
4384                 u8 buf[4];
4385
4386                 if (cmd_flags)
4387                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4388                 else
4389                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
4390                                     BNX2_NVM_COMMAND_LAST;
4391
4392                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4393
4394                 memcpy(ret_buf, buf, 4 - extra);
4395         }
4396         else if (len32 > 0) {
4397                 u8 buf[4];
4398
4399                 /* Read the first word. */
4400                 if (cmd_flags)
4401                         cmd_flags = 0;
4402                 else
4403                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
4404
4405                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4406
4407                 /* Advance to the next dword. */
4408                 offset32 += 4;
4409                 ret_buf += 4;
4410                 len32 -= 4;
4411
4412                 while (len32 > 4 && rc == 0) {
4413                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4414
4415                         /* Advance to the next dword. */
4416                         offset32 += 4;
4417                         ret_buf += 4;
4418                         len32 -= 4;
4419                 }
4420
4421                 if (rc)
4422                         return rc;
4423
4424                 cmd_flags = BNX2_NVM_COMMAND_LAST;
4425                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4426
4427                 memcpy(ret_buf, buf, 4 - extra);
4428         }
4429
4430         /* Disable access to flash interface */
4431         bnx2_disable_nvram_access(bp);
4432
4433         bnx2_release_nvram_lock(bp);
4434
4435         return rc;
4436 }
4437
4438 static int
4439 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4440                 int buf_size)
4441 {
4442         u32 written, offset32, len32;
4443         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4444         int rc = 0;
4445         int align_start, align_end;
4446
4447         buf = data_buf;
4448         offset32 = offset;
4449         len32 = buf_size;
4450         align_start = align_end = 0;
4451
4452         if ((align_start = (offset32 & 3))) {
4453                 offset32 &= ~3;
4454                 len32 += align_start;
4455                 if (len32 < 4)
4456                         len32 = 4;
4457                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4458                         return rc;
4459         }
4460
4461         if (len32 & 3) {
4462                 align_end = 4 - (len32 & 3);
4463                 len32 += align_end;
4464                 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4465                         return rc;
4466         }
4467
4468         if (align_start || align_end) {
4469                 align_buf = kmalloc(len32, GFP_KERNEL);
4470                 if (align_buf == NULL)
4471                         return -ENOMEM;
4472                 if (align_start) {
4473                         memcpy(align_buf, start, 4);
4474                 }
4475                 if (align_end) {
4476                         memcpy(align_buf + len32 - 4, end, 4);
4477                 }
4478                 memcpy(align_buf + align_start, data_buf, buf_size);
4479                 buf = align_buf;
4480         }
4481
4482         if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4483                 flash_buffer = kmalloc(264, GFP_KERNEL);
4484                 if (flash_buffer == NULL) {
4485                         rc = -ENOMEM;
4486                         goto nvram_write_end;
4487                 }
4488         }
4489
4490         written = 0;
4491         while ((written < len32) && (rc == 0)) {
4492                 u32 page_start, page_end, data_start, data_end;
4493                 u32 addr, cmd_flags;
4494                 int i;
4495
4496                 /* Find the page_start addr */
4497                 page_start = offset32 + written;
4498                 page_start -= (page_start % bp->flash_info->page_size);
4499                 /* Find the page_end addr */
4500                 page_end = page_start + bp->flash_info->page_size;
4501                 /* Find the data_start addr */
4502                 data_start = (written == 0) ? offset32 : page_start;
4503                 /* Find the data_end addr */
4504                 data_end = (page_end > offset32 + len32) ?
4505                         (offset32 + len32) : page_end;
4506
4507                 /* Request access to the flash interface. */
4508                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4509                         goto nvram_write_end;
4510
4511                 /* Enable access to flash interface */
4512                 bnx2_enable_nvram_access(bp);
4513
4514                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4515                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4516                         int j;
4517
4518                         /* Read the whole page into the buffer
4519                          * (non-buffer flash only) */
4520                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
4521                                 if (j == (bp->flash_info->page_size - 4)) {
4522                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
4523                                 }
4524                                 rc = bnx2_nvram_read_dword(bp,
4525                                         page_start + j,
4526                                         &flash_buffer[j],
4527                                         cmd_flags);
4528
4529                                 if (rc)
4530                                         goto nvram_write_end;
4531
4532                                 cmd_flags = 0;
4533                         }
4534                 }
4535
4536                 /* Enable writes to flash interface (unlock write-protect) */
4537                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4538                         goto nvram_write_end;
4539
4540                 /* Loop to write back the buffer data from page_start to
4541                  * data_start */
4542                 i = 0;
4543                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4544                         /* Erase the page */
4545                         if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4546                                 goto nvram_write_end;
4547
4548                         /* Re-enable the write again for the actual write */
4549                         bnx2_enable_nvram_write(bp);
4550
4551                         for (addr = page_start; addr < data_start;
4552                                 addr += 4, i += 4) {
4553
4554                                 rc = bnx2_nvram_write_dword(bp, addr,
4555                                         &flash_buffer[i], cmd_flags);
4556
4557                                 if (rc != 0)
4558                                         goto nvram_write_end;
4559
4560                                 cmd_flags = 0;
4561                         }
4562                 }
4563
4564                 /* Loop to write the new data from data_start to data_end */
4565                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4566                         if ((addr == page_end - 4) ||
4567                                 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4568                                  (addr == data_end - 4))) {
4569
4570                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4571                         }
4572                         rc = bnx2_nvram_write_dword(bp, addr, buf,
4573                                 cmd_flags);
4574
4575                         if (rc != 0)
4576                                 goto nvram_write_end;
4577
4578                         cmd_flags = 0;
4579                         buf += 4;
4580                 }
4581
4582                 /* Loop to write back the buffer data from data_end
4583                  * to page_end */
4584                 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4585                         for (addr = data_end; addr < page_end;
4586                                 addr += 4, i += 4) {
4587
4588                                 if (addr == page_end-4) {
4589                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
4590                                 }
4591                                 rc = bnx2_nvram_write_dword(bp, addr,
4592                                         &flash_buffer[i], cmd_flags);
4593
4594                                 if (rc != 0)
4595                                         goto nvram_write_end;
4596
4597                                 cmd_flags = 0;
4598                         }
4599                 }
4600
4601                 /* Disable writes to flash interface (lock write-protect) */
4602                 bnx2_disable_nvram_write(bp);
4603
4604                 /* Disable access to flash interface */
4605                 bnx2_disable_nvram_access(bp);
4606                 bnx2_release_nvram_lock(bp);
4607
4608                 /* Increment written */
4609                 written += data_end - data_start;
4610         }
4611
4612 nvram_write_end:
4613         kfree(flash_buffer);
4614         kfree(align_buf);
4615         return rc;
4616 }
4617
4618 static void
4619 bnx2_init_fw_cap(struct bnx2 *bp)
4620 {
4621         u32 val, sig = 0;
4622
4623         bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4624         bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4625
4626         if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4627                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4628
4629         val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4630         if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4631                 return;
4632
4633         if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4634                 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4635                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4636         }
4637
4638         if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4639             (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4640                 u32 link;
4641
4642                 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4643
4644                 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4645                 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4646                         bp->phy_port = PORT_FIBRE;
4647                 else
4648                         bp->phy_port = PORT_TP;
4649
4650                 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4651                        BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4652         }
4653
4654         if (netif_running(bp->dev) && sig)
4655                 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4656 }
4657
4658 static void
4659 bnx2_setup_msix_tbl(struct bnx2 *bp)
4660 {
4661         REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4662
4663         REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4664         REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4665 }
4666
4667 static int
4668 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4669 {
4670         u32 val;
4671         int i, rc = 0;
4672         u8 old_port;
4673
4674         /* Wait for the current PCI transaction to complete before
4675          * issuing a reset. */
4676         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4677                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4678                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4679                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4680                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4681         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4682         udelay(5);
4683
4684         /* Wait for the firmware to tell us it is ok to issue a reset. */
4685         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4686
4687         /* Deposit a driver reset signature so the firmware knows that
4688          * this is a soft reset. */
4689         bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4690                       BNX2_DRV_RESET_SIGNATURE_MAGIC);
4691
4692         /* Do a dummy read to force the chip to complete all current transaction
4693          * before we issue a reset. */
4694         val = REG_RD(bp, BNX2_MISC_ID);
4695
4696         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4697                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4698                 REG_RD(bp, BNX2_MISC_COMMAND);
4699                 udelay(5);
4700
4701                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4702                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4703
4704                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4705
4706         } else {
4707                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4708                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4709                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4710
4711                 /* Chip reset. */
4712                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4713
4714                 /* Reading back any register after chip reset will hang the
4715                  * bus on 5706 A0 and A1.  The msleep below provides plenty
4716                  * of margin for write posting.
4717                  */
4718                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4719                     (CHIP_ID(bp) == CHIP_ID_5706_A1))
4720                         msleep(20);
4721
4722                 /* Reset takes approximate 30 usec */
4723                 for (i = 0; i < 10; i++) {
4724                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4725                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4726                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4727                                 break;
4728                         udelay(10);
4729                 }
4730
4731                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4732                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4733                         pr_err("Chip reset did not complete\n");
4734                         return -EBUSY;
4735                 }
4736         }
4737
4738         /* Make sure byte swapping is properly configured. */
4739         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4740         if (val != 0x01020304) {
4741                 pr_err("Chip not in correct endian mode\n");
4742                 return -ENODEV;
4743         }
4744
4745         /* Wait for the firmware to finish its initialization. */
4746         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4747         if (rc)
4748                 return rc;
4749
4750         spin_lock_bh(&bp->phy_lock);
4751         old_port = bp->phy_port;
4752         bnx2_init_fw_cap(bp);
4753         if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4754             old_port != bp->phy_port)
4755                 bnx2_set_default_remote_link(bp);
4756         spin_unlock_bh(&bp->phy_lock);
4757
4758         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4759                 /* Adjust the voltage regular to two steps lower.  The default
4760                  * of this register is 0x0000000e. */
4761                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4762
4763                 /* Remove bad rbuf memory from the free pool. */
4764                 rc = bnx2_alloc_bad_rbuf(bp);
4765         }
4766
4767         if (bp->flags & BNX2_FLAG_USING_MSIX) {
4768                 bnx2_setup_msix_tbl(bp);
4769                 /* Prevent MSIX table reads and write from timing out */
4770                 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4771                         BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4772         }
4773
4774         return rc;
4775 }
4776
4777 static int
4778 bnx2_init_chip(struct bnx2 *bp)
4779 {
4780         u32 val, mtu;
4781         int rc, i;
4782
4783         /* Make sure the interrupt is not active. */
4784         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4785
4786         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4787               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4788 #ifdef __BIG_ENDIAN
4789               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4790 #endif
4791               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4792               DMA_READ_CHANS << 12 |
4793               DMA_WRITE_CHANS << 16;
4794
4795         val |= (0x2 << 20) | (1 << 11);
4796
4797         if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4798                 val |= (1 << 23);
4799
4800         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4801             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4802                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4803
4804         REG_WR(bp, BNX2_DMA_CONFIG, val);
4805
4806         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4807                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4808                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4809                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4810         }
4811
4812         if (bp->flags & BNX2_FLAG_PCIX) {
4813                 u16 val16;
4814
4815                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4816                                      &val16);
4817                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4818                                       val16 & ~PCI_X_CMD_ERO);
4819         }
4820
4821         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4822                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4823                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4824                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4825
4826         /* Initialize context mapping and zero out the quick contexts.  The
4827          * context block must have already been enabled. */
4828         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4829                 rc = bnx2_init_5709_context(bp);
4830                 if (rc)
4831                         return rc;
4832         } else
4833                 bnx2_init_context(bp);
4834
4835         if ((rc = bnx2_init_cpus(bp)) != 0)
4836                 return rc;
4837
4838         bnx2_init_nvram(bp);
4839
4840         bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4841
4842         val = REG_RD(bp, BNX2_MQ_CONFIG);
4843         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4844         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4845         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4846                 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4847                 if (CHIP_REV(bp) == CHIP_REV_Ax)
4848                         val |= BNX2_MQ_CONFIG_HALT_DIS;
4849         }
4850
4851         REG_WR(bp, BNX2_MQ_CONFIG, val);
4852
4853         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4854         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4855         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4856
4857         val = (BCM_PAGE_BITS - 8) << 24;
4858         REG_WR(bp, BNX2_RV2P_CONFIG, val);
4859
4860         /* Configure page size. */
4861         val = REG_RD(bp, BNX2_TBDR_CONFIG);
4862         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4863         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4864         REG_WR(bp, BNX2_TBDR_CONFIG, val);
4865
4866         val = bp->mac_addr[0] +
4867               (bp->mac_addr[1] << 8) +
4868               (bp->mac_addr[2] << 16) +
4869               bp->mac_addr[3] +
4870               (bp->mac_addr[4] << 8) +
4871               (bp->mac_addr[5] << 16);
4872         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4873
4874         /* Program the MTU.  Also include 4 bytes for CRC32. */
4875         mtu = bp->dev->mtu;
4876         val = mtu + ETH_HLEN + ETH_FCS_LEN;
4877         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4878                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4879         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4880
4881         if (mtu < 1500)
4882                 mtu = 1500;
4883
4884         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4885         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4886         bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4887
4888         memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4889         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4890                 bp->bnx2_napi[i].last_status_idx = 0;
4891
4892         bp->idle_chk_status_idx = 0xffff;
4893
4894         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4895
4896         /* Set up how to generate a link change interrupt. */
4897         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4898
4899         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4900                (u64) bp->status_blk_mapping & 0xffffffff);
4901         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4902
4903         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4904                (u64) bp->stats_blk_mapping & 0xffffffff);
4905         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4906                (u64) bp->stats_blk_mapping >> 32);
4907
4908         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4909                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4910
4911         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4912                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4913
4914         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4915                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4916
4917         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4918
4919         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4920
4921         REG_WR(bp, BNX2_HC_COM_TICKS,
4922                (bp->com_ticks_int << 16) | bp->com_ticks);
4923
4924         REG_WR(bp, BNX2_HC_CMD_TICKS,
4925                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4926
4927         if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4928                 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4929         else
4930                 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4931         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4932
4933         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4934                 val = BNX2_HC_CONFIG_COLLECT_STATS;
4935         else {
4936                 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4937                       BNX2_HC_CONFIG_COLLECT_STATS;
4938         }
4939
4940         if (bp->flags & BNX2_FLAG_USING_MSIX) {
4941                 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4942                        BNX2_HC_MSIX_BIT_VECTOR_VAL);
4943
4944                 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4945         }
4946
4947         if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4948                 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4949
4950         REG_WR(bp, BNX2_HC_CONFIG, val);
4951
4952         for (i = 1; i < bp->irq_nvecs; i++) {
4953                 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4954                            BNX2_HC_SB_CONFIG_1;
4955
4956                 REG_WR(bp, base,
4957                         BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4958                         BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4959                         BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4960
4961                 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4962                         (bp->tx_quick_cons_trip_int << 16) |
4963                          bp->tx_quick_cons_trip);
4964
4965                 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4966                         (bp->tx_ticks_int << 16) | bp->tx_ticks);
4967
4968                 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4969                        (bp->rx_quick_cons_trip_int << 16) |
4970                         bp->rx_quick_cons_trip);
4971
4972                 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4973                         (bp->rx_ticks_int << 16) | bp->rx_ticks);
4974         }
4975
4976         /* Clear internal stats counters. */
4977         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4978
4979         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4980
4981         /* Initialize the receive filter. */
4982         bnx2_set_rx_mode(bp->dev);
4983
4984         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4985                 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4986                 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4987                 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4988         }
4989         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4990                           1, 0);
4991
4992         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4993         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4994
4995         udelay(20);
4996
4997         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4998
4999         return rc;
5000 }
5001
5002 static void
5003 bnx2_clear_ring_states(struct bnx2 *bp)
5004 {
5005         struct bnx2_napi *bnapi;
5006         struct bnx2_tx_ring_info *txr;
5007         struct bnx2_rx_ring_info *rxr;
5008         int i;
5009
5010         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5011                 bnapi = &bp->bnx2_napi[i];
5012                 txr = &bnapi->tx_ring;
5013                 rxr = &bnapi->rx_ring;
5014
5015                 txr->tx_cons = 0;
5016                 txr->hw_tx_cons = 0;
5017                 rxr->rx_prod_bseq = 0;
5018                 rxr->rx_prod = 0;
5019                 rxr->rx_cons = 0;
5020                 rxr->rx_pg_prod = 0;
5021                 rxr->rx_pg_cons = 0;
5022         }
5023 }
5024
5025 static void
5026 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5027 {
5028         u32 val, offset0, offset1, offset2, offset3;
5029         u32 cid_addr = GET_CID_ADDR(cid);
5030
5031         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5032                 offset0 = BNX2_L2CTX_TYPE_XI;
5033                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5034                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5035                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5036         } else {
5037                 offset0 = BNX2_L2CTX_TYPE;
5038                 offset1 = BNX2_L2CTX_CMD_TYPE;
5039                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5040                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5041         }
5042         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5043         bnx2_ctx_wr(bp, cid_addr, offset0, val);
5044
5045         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5046         bnx2_ctx_wr(bp, cid_addr, offset1, val);
5047
5048         val = (u64) txr->tx_desc_mapping >> 32;
5049         bnx2_ctx_wr(bp, cid_addr, offset2, val);
5050
5051         val = (u64) txr->tx_desc_mapping & 0xffffffff;
5052         bnx2_ctx_wr(bp, cid_addr, offset3, val);
5053 }
5054
5055 static void
5056 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5057 {
5058         struct tx_bd *txbd;
5059         u32 cid = TX_CID;
5060         struct bnx2_napi *bnapi;
5061         struct bnx2_tx_ring_info *txr;
5062
5063         bnapi = &bp->bnx2_napi[ring_num];
5064         txr = &bnapi->tx_ring;
5065
5066         if (ring_num == 0)
5067                 cid = TX_CID;
5068         else
5069                 cid = TX_TSS_CID + ring_num - 1;
5070
5071         bp->tx_wake_thresh = bp->tx_ring_size / 2;
5072
5073         txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5074
5075         txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5076         txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5077
5078         txr->tx_prod = 0;
5079         txr->tx_prod_bseq = 0;
5080
5081         txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5082         txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5083
5084         bnx2_init_tx_context(bp, cid, txr);
5085 }
5086
5087 static void
5088 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5089                      int num_rings)
5090 {
5091         int i;
5092         struct rx_bd *rxbd;
5093
5094         for (i = 0; i < num_rings; i++) {
5095                 int j;
5096
5097                 rxbd = &rx_ring[i][0];
5098                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5099                         rxbd->rx_bd_len = buf_size;
5100                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5101                 }
5102                 if (i == (num_rings - 1))
5103                         j = 0;
5104                 else
5105                         j = i + 1;
5106                 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5107                 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5108         }
5109 }
5110
5111 static void
5112 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5113 {
5114         int i;
5115         u16 prod, ring_prod;
5116         u32 cid, rx_cid_addr, val;
5117         struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5118         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5119
5120         if (ring_num == 0)
5121                 cid = RX_CID;
5122         else
5123                 cid = RX_RSS_CID + ring_num - 1;
5124
5125         rx_cid_addr = GET_CID_ADDR(cid);
5126
5127         bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5128                              bp->rx_buf_use_size, bp->rx_max_ring);
5129
5130         bnx2_init_rx_context(bp, cid);
5131
5132         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5133                 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5134                 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5135         }
5136
5137         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5138         if (bp->rx_pg_ring_size) {
5139                 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5140                                      rxr->rx_pg_desc_mapping,
5141                                      PAGE_SIZE, bp->rx_max_pg_ring);
5142                 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5143                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5144                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5145                        BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5146
5147                 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5148                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5149
5150                 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5151                 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5152
5153                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5154                         REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5155         }
5156
5157         val = (u64) rxr->rx_desc_mapping[0] >> 32;
5158         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5159
5160         val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5161         bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5162
5163         ring_prod = prod = rxr->rx_pg_prod;
5164         for (i = 0; i < bp->rx_pg_ring_size; i++) {
5165                 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) {
5166                         netdev_warn(bp->dev, "init'ed rx page ring %d with %d/%d pages only\n",
5167                                     ring_num, i, bp->rx_pg_ring_size);
5168                         break;
5169                 }
5170                 prod = NEXT_RX_BD(prod);
5171                 ring_prod = RX_PG_RING_IDX(prod);
5172         }
5173         rxr->rx_pg_prod = prod;
5174
5175         ring_prod = prod = rxr->rx_prod;
5176         for (i = 0; i < bp->rx_ring_size; i++) {
5177                 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) {
5178                         netdev_warn(bp->dev, "init'ed rx ring %d with %d/%d skbs only\n",
5179                                     ring_num, i, bp->rx_ring_size);
5180                         break;
5181                 }
5182                 prod = NEXT_RX_BD(prod);
5183                 ring_prod = RX_RING_IDX(prod);
5184         }
5185         rxr->rx_prod = prod;
5186
5187         rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5188         rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5189         rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5190
5191         REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5192         REG_WR16(bp, rxr->rx_bidx_addr, prod);
5193
5194         REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5195 }
5196
5197 static void
5198 bnx2_init_all_rings(struct bnx2 *bp)
5199 {
5200         int i;
5201         u32 val;
5202
5203         bnx2_clear_ring_states(bp);
5204
5205         REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5206         for (i = 0; i < bp->num_tx_rings; i++)
5207                 bnx2_init_tx_ring(bp, i);
5208
5209         if (bp->num_tx_rings > 1)
5210                 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5211                        (TX_TSS_CID << 7));
5212
5213         REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5214         bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5215
5216         for (i = 0; i < bp->num_rx_rings; i++)
5217                 bnx2_init_rx_ring(bp, i);
5218
5219         if (bp->num_rx_rings > 1) {
5220                 u32 tbl_32;
5221                 u8 *tbl = (u8 *) &tbl_32;
5222
5223                 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5224                                 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5225
5226                 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5227                         tbl[i % 4] = i % (bp->num_rx_rings - 1);
5228                         if ((i % 4) == 3)
5229                                 bnx2_reg_wr_ind(bp,
5230                                                 BNX2_RXP_SCRATCH_RSS_TBL + i,
5231                                                 cpu_to_be32(tbl_32));
5232                 }
5233
5234                 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5235                       BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5236
5237                 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5238
5239         }
5240 }
5241
5242 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5243 {
5244         u32 max, num_rings = 1;
5245
5246         while (ring_size > MAX_RX_DESC_CNT) {
5247                 ring_size -= MAX_RX_DESC_CNT;
5248                 num_rings++;
5249         }
5250         /* round to next power of 2 */
5251         max = max_size;
5252         while ((max & num_rings) == 0)
5253                 max >>= 1;
5254
5255         if (num_rings != max)
5256                 max <<= 1;
5257
5258         return max;
5259 }
5260
5261 static void
5262 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5263 {
5264         u32 rx_size, rx_space, jumbo_size;
5265
5266         /* 8 for CRC and VLAN */
5267         rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5268
5269         rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5270                 sizeof(struct skb_shared_info);
5271
5272         bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5273         bp->rx_pg_ring_size = 0;
5274         bp->rx_max_pg_ring = 0;
5275         bp->rx_max_pg_ring_idx = 0;
5276         if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5277                 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5278
5279                 jumbo_size = size * pages;
5280                 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5281                         jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5282
5283                 bp->rx_pg_ring_size = jumbo_size;
5284                 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5285                                                         MAX_RX_PG_RINGS);
5286                 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5287                 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5288                 bp->rx_copy_thresh = 0;
5289         }
5290
5291         bp->rx_buf_use_size = rx_size;
5292         /* hw alignment */
5293         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5294         bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5295         bp->rx_ring_size = size;
5296         bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5297         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5298 }
5299
5300 static void
5301 bnx2_free_tx_skbs(struct bnx2 *bp)
5302 {
5303         int i;
5304
5305         for (i = 0; i < bp->num_tx_rings; i++) {
5306                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5307                 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5308                 int j;
5309
5310                 if (txr->tx_buf_ring == NULL)
5311                         continue;
5312
5313                 for (j = 0; j < TX_DESC_CNT; ) {
5314                         struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5315                         struct sk_buff *skb = tx_buf->skb;
5316                         int k, last;
5317
5318                         if (skb == NULL) {
5319                                 j++;
5320                                 continue;
5321                         }
5322
5323                         pci_unmap_single(bp->pdev,
5324                                          dma_unmap_addr(tx_buf, mapping),
5325                                          skb_headlen(skb),
5326                                          PCI_DMA_TODEVICE);
5327
5328                         tx_buf->skb = NULL;
5329
5330                         last = tx_buf->nr_frags;
5331                         j++;
5332                         for (k = 0; k < last; k++, j++) {
5333                                 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5334                                 pci_unmap_page(bp->pdev,
5335                                         dma_unmap_addr(tx_buf, mapping),
5336                                         skb_shinfo(skb)->frags[k].size,
5337                                         PCI_DMA_TODEVICE);
5338                         }
5339                         dev_kfree_skb(skb);
5340                 }
5341         }
5342 }
5343
5344 static void
5345 bnx2_free_rx_skbs(struct bnx2 *bp)
5346 {
5347         int i;
5348
5349         for (i = 0; i < bp->num_rx_rings; i++) {
5350                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5351                 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5352                 int j;
5353
5354                 if (rxr->rx_buf_ring == NULL)
5355                         return;
5356
5357                 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5358                         struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5359                         struct sk_buff *skb = rx_buf->skb;
5360
5361                         if (skb == NULL)
5362                                 continue;
5363
5364                         pci_unmap_single(bp->pdev,
5365                                          dma_unmap_addr(rx_buf, mapping),
5366                                          bp->rx_buf_use_size,
5367                                          PCI_DMA_FROMDEVICE);
5368
5369                         rx_buf->skb = NULL;
5370
5371                         dev_kfree_skb(skb);
5372                 }
5373                 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5374                         bnx2_free_rx_page(bp, rxr, j);
5375         }
5376 }
5377
5378 static void
5379 bnx2_free_skbs(struct bnx2 *bp)
5380 {
5381         bnx2_free_tx_skbs(bp);
5382         bnx2_free_rx_skbs(bp);
5383 }
5384
5385 static int
5386 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5387 {
5388         int rc;
5389
5390         rc = bnx2_reset_chip(bp, reset_code);
5391         bnx2_free_skbs(bp);
5392         if (rc)
5393                 return rc;
5394
5395         if ((rc = bnx2_init_chip(bp)) != 0)
5396                 return rc;
5397
5398         bnx2_init_all_rings(bp);
5399         return 0;
5400 }
5401
5402 static int
5403 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5404 {
5405         int rc;
5406
5407         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5408                 return rc;
5409
5410         spin_lock_bh(&bp->phy_lock);
5411         bnx2_init_phy(bp, reset_phy);
5412         bnx2_set_link(bp);
5413         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5414                 bnx2_remote_phy_event(bp);
5415         spin_unlock_bh(&bp->phy_lock);
5416         return 0;
5417 }
5418
5419 static int
5420 bnx2_shutdown_chip(struct bnx2 *bp)
5421 {
5422         u32 reset_code;
5423
5424         if (bp->flags & BNX2_FLAG_NO_WOL)
5425                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5426         else if (bp->wol)
5427                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5428         else
5429                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5430
5431         return bnx2_reset_chip(bp, reset_code);
5432 }
5433
5434 static int
5435 bnx2_test_registers(struct bnx2 *bp)
5436 {
5437         int ret;
5438         int i, is_5709;
5439         static const struct {
5440                 u16   offset;
5441                 u16   flags;
5442 #define BNX2_FL_NOT_5709        1
5443                 u32   rw_mask;
5444                 u32   ro_mask;
5445         } reg_tbl[] = {
5446                 { 0x006c, 0, 0x00000000, 0x0000003f },
5447                 { 0x0090, 0, 0xffffffff, 0x00000000 },
5448                 { 0x0094, 0, 0x00000000, 0x00000000 },
5449
5450                 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5451                 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5452                 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5453                 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5454                 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5455                 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5456                 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5457                 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5458                 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5459
5460                 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5461                 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5462                 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5463                 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5464                 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5465                 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5466
5467                 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5468                 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5469                 { 0x0c08, BNX2_FL_NOT_5709,  0x0f0ff073, 0x00000000 },
5470
5471                 { 0x1000, 0, 0x00000000, 0x00000001 },
5472                 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5473
5474                 { 0x1408, 0, 0x01c00800, 0x00000000 },
5475                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5476                 { 0x14a8, 0, 0x00000000, 0x000001ff },
5477                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5478                 { 0x14b0, 0, 0x00000002, 0x00000001 },
5479                 { 0x14b8, 0, 0x00000000, 0x00000000 },
5480                 { 0x14c0, 0, 0x00000000, 0x00000009 },
5481                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5482                 { 0x14cc, 0, 0x00000000, 0x00000001 },
5483                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5484
5485                 { 0x1800, 0, 0x00000000, 0x00000001 },
5486                 { 0x1804, 0, 0x00000000, 0x00000003 },
5487
5488                 { 0x2800, 0, 0x00000000, 0x00000001 },
5489                 { 0x2804, 0, 0x00000000, 0x00003f01 },
5490                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5491                 { 0x2810, 0, 0xffff0000, 0x00000000 },
5492                 { 0x2814, 0, 0xffff0000, 0x00000000 },
5493                 { 0x2818, 0, 0xffff0000, 0x00000000 },
5494                 { 0x281c, 0, 0xffff0000, 0x00000000 },
5495                 { 0x2834, 0, 0xffffffff, 0x00000000 },
5496                 { 0x2840, 0, 0x00000000, 0xffffffff },
5497                 { 0x2844, 0, 0x00000000, 0xffffffff },
5498                 { 0x2848, 0, 0xffffffff, 0x00000000 },
5499                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5500
5501                 { 0x2c00, 0, 0x00000000, 0x00000011 },
5502                 { 0x2c04, 0, 0x00000000, 0x00030007 },
5503
5504                 { 0x3c00, 0, 0x00000000, 0x00000001 },
5505                 { 0x3c04, 0, 0x00000000, 0x00070000 },
5506                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5507                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5508                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5509                 { 0x3c14, 0, 0x00000000, 0xffffffff },
5510                 { 0x3c18, 0, 0x00000000, 0xffffffff },
5511                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5512                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5513
5514                 { 0x5004, 0, 0x00000000, 0x0000007f },
5515                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5516
5517                 { 0x5c00, 0, 0x00000000, 0x00000001 },
5518                 { 0x5c04, 0, 0x00000000, 0x0003000f },
5519                 { 0x5c08, 0, 0x00000003, 0x00000000 },
5520                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5521                 { 0x5c10, 0, 0x00000000, 0xffffffff },
5522                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5523                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5524                 { 0x5c88, 0, 0x00000000, 0x00077373 },
5525                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5526
5527                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5528                 { 0x680c, 0, 0xffffffff, 0x00000000 },
5529                 { 0x6810, 0, 0xffffffff, 0x00000000 },
5530                 { 0x6814, 0, 0xffffffff, 0x00000000 },
5531                 { 0x6818, 0, 0xffffffff, 0x00000000 },
5532                 { 0x681c, 0, 0xffffffff, 0x00000000 },
5533                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5534                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5535                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5536                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5537                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5538                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5539                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5540                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5541                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5542                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5543                 { 0x684c, 0, 0xffffffff, 0x00000000 },
5544                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5545                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5546                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5547                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5548                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5549                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5550
5551                 { 0xffff, 0, 0x00000000, 0x00000000 },
5552         };
5553
5554         ret = 0;
5555         is_5709 = 0;
5556         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5557                 is_5709 = 1;
5558
5559         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5560                 u32 offset, rw_mask, ro_mask, save_val, val;
5561                 u16 flags = reg_tbl[i].flags;
5562
5563                 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5564                         continue;
5565
5566                 offset = (u32) reg_tbl[i].offset;
5567                 rw_mask = reg_tbl[i].rw_mask;
5568                 ro_mask = reg_tbl[i].ro_mask;
5569
5570                 save_val = readl(bp->regview + offset);
5571
5572                 writel(0, bp->regview + offset);
5573
5574                 val = readl(bp->regview + offset);
5575                 if ((val & rw_mask) != 0) {
5576                         goto reg_test_err;
5577                 }
5578
5579                 if ((val & ro_mask) != (save_val & ro_mask)) {
5580                         goto reg_test_err;
5581                 }
5582
5583                 writel(0xffffffff, bp->regview + offset);
5584
5585                 val = readl(bp->regview + offset);
5586                 if ((val & rw_mask) != rw_mask) {
5587                         goto reg_test_err;
5588                 }
5589
5590                 if ((val & ro_mask) != (save_val & ro_mask)) {
5591                         goto reg_test_err;
5592                 }
5593
5594                 writel(save_val, bp->regview + offset);
5595                 continue;
5596
5597 reg_test_err:
5598                 writel(save_val, bp->regview + offset);
5599                 ret = -ENODEV;
5600                 break;
5601         }
5602         return ret;
5603 }
5604
5605 static int
5606 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5607 {
5608         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5609                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5610         int i;
5611
5612         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5613                 u32 offset;
5614
5615                 for (offset = 0; offset < size; offset += 4) {
5616
5617                         bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5618
5619                         if (bnx2_reg_rd_ind(bp, start + offset) !=
5620                                 test_pattern[i]) {
5621                                 return -ENODEV;
5622                         }
5623                 }
5624         }
5625         return 0;
5626 }
5627
5628 static int
5629 bnx2_test_memory(struct bnx2 *bp)
5630 {
5631         int ret = 0;
5632         int i;
5633         static struct mem_entry {
5634                 u32   offset;
5635                 u32   len;
5636         } mem_tbl_5706[] = {
5637                 { 0x60000,  0x4000 },
5638                 { 0xa0000,  0x3000 },
5639                 { 0xe0000,  0x4000 },
5640                 { 0x120000, 0x4000 },
5641                 { 0x1a0000, 0x4000 },
5642                 { 0x160000, 0x4000 },
5643                 { 0xffffffff, 0    },
5644         },
5645         mem_tbl_5709[] = {
5646                 { 0x60000,  0x4000 },
5647                 { 0xa0000,  0x3000 },
5648                 { 0xe0000,  0x4000 },
5649                 { 0x120000, 0x4000 },
5650                 { 0x1a0000, 0x4000 },
5651                 { 0xffffffff, 0    },
5652         };
5653         struct mem_entry *mem_tbl;
5654
5655         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5656                 mem_tbl = mem_tbl_5709;
5657         else
5658                 mem_tbl = mem_tbl_5706;
5659
5660         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5661                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5662                         mem_tbl[i].len)) != 0) {
5663                         return ret;
5664                 }
5665         }
5666
5667         return ret;
5668 }
5669
5670 #define BNX2_MAC_LOOPBACK       0
5671 #define BNX2_PHY_LOOPBACK       1
5672
5673 static int
5674 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5675 {
5676         unsigned int pkt_size, num_pkts, i;
5677         struct sk_buff *skb, *rx_skb;
5678         unsigned char *packet;
5679         u16 rx_start_idx, rx_idx;
5680         dma_addr_t map;
5681         struct tx_bd *txbd;
5682         struct sw_bd *rx_buf;
5683         struct l2_fhdr *rx_hdr;
5684         int ret = -ENODEV;
5685         struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5686         struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5687         struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5688
5689         tx_napi = bnapi;
5690
5691         txr = &tx_napi->tx_ring;
5692         rxr = &bnapi->rx_ring;
5693         if (loopback_mode == BNX2_MAC_LOOPBACK) {
5694                 bp->loopback = MAC_LOOPBACK;
5695                 bnx2_set_mac_loopback(bp);
5696         }
5697         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5698                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5699                         return 0;
5700
5701                 bp->loopback = PHY_LOOPBACK;
5702                 bnx2_set_phy_loopback(bp);
5703         }
5704         else
5705                 return -EINVAL;
5706
5707         pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5708         skb = netdev_alloc_skb(bp->dev, pkt_size);
5709         if (!skb)
5710                 return -ENOMEM;
5711         packet = skb_put(skb, pkt_size);
5712         memcpy(packet, bp->dev->dev_addr, 6);
5713         memset(packet + 6, 0x0, 8);
5714         for (i = 14; i < pkt_size; i++)
5715                 packet[i] = (unsigned char) (i & 0xff);
5716
5717         map = pci_map_single(bp->pdev, skb->data, pkt_size,
5718                 PCI_DMA_TODEVICE);
5719         if (pci_dma_mapping_error(bp->pdev, map)) {
5720                 dev_kfree_skb(skb);
5721                 return -EIO;
5722         }
5723
5724         REG_WR(bp, BNX2_HC_COMMAND,
5725                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5726
5727         REG_RD(bp, BNX2_HC_COMMAND);
5728
5729         udelay(5);
5730         rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5731
5732         num_pkts = 0;
5733
5734         txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5735
5736         txbd->tx_bd_haddr_hi = (u64) map >> 32;
5737         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5738         txbd->tx_bd_mss_nbytes = pkt_size;
5739         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5740
5741         num_pkts++;
5742         txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5743         txr->tx_prod_bseq += pkt_size;
5744
5745         REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5746         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5747
5748         udelay(100);
5749
5750         REG_WR(bp, BNX2_HC_COMMAND,
5751                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5752
5753         REG_RD(bp, BNX2_HC_COMMAND);
5754
5755         udelay(5);
5756
5757         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5758         dev_kfree_skb(skb);
5759
5760         if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5761                 goto loopback_test_done;
5762
5763         rx_idx = bnx2_get_hw_rx_cons(bnapi);
5764         if (rx_idx != rx_start_idx + num_pkts) {
5765                 goto loopback_test_done;
5766         }
5767
5768         rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5769         rx_skb = rx_buf->skb;
5770
5771         rx_hdr = rx_buf->desc;
5772         skb_reserve(rx_skb, BNX2_RX_OFFSET);
5773
5774         pci_dma_sync_single_for_cpu(bp->pdev,
5775                 dma_unmap_addr(rx_buf, mapping),
5776                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5777
5778         if (rx_hdr->l2_fhdr_status &
5779                 (L2_FHDR_ERRORS_BAD_CRC |
5780                 L2_FHDR_ERRORS_PHY_DECODE |
5781                 L2_FHDR_ERRORS_ALIGNMENT |
5782                 L2_FHDR_ERRORS_TOO_SHORT |
5783                 L2_FHDR_ERRORS_GIANT_FRAME)) {
5784
5785                 goto loopback_test_done;
5786         }
5787
5788         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5789                 goto loopback_test_done;
5790         }
5791
5792         for (i = 14; i < pkt_size; i++) {
5793                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5794                         goto loopback_test_done;
5795                 }
5796         }
5797
5798         ret = 0;
5799
5800 loopback_test_done:
5801         bp->loopback = 0;
5802         return ret;
5803 }
5804
5805 #define BNX2_MAC_LOOPBACK_FAILED        1
5806 #define BNX2_PHY_LOOPBACK_FAILED        2
5807 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
5808                                          BNX2_PHY_LOOPBACK_FAILED)
5809
5810 static int
5811 bnx2_test_loopback(struct bnx2 *bp)
5812 {
5813         int rc = 0;
5814
5815         if (!netif_running(bp->dev))
5816                 return BNX2_LOOPBACK_FAILED;
5817
5818         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5819         spin_lock_bh(&bp->phy_lock);
5820         bnx2_init_phy(bp, 1);
5821         spin_unlock_bh(&bp->phy_lock);
5822         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5823                 rc |= BNX2_MAC_LOOPBACK_FAILED;
5824         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5825                 rc |= BNX2_PHY_LOOPBACK_FAILED;
5826         return rc;
5827 }
5828
5829 #define NVRAM_SIZE 0x200
5830 #define CRC32_RESIDUAL 0xdebb20e3
5831
5832 static int
5833 bnx2_test_nvram(struct bnx2 *bp)
5834 {
5835         __be32 buf[NVRAM_SIZE / 4];
5836         u8 *data = (u8 *) buf;
5837         int rc = 0;
5838         u32 magic, csum;
5839
5840         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5841                 goto test_nvram_done;
5842
5843         magic = be32_to_cpu(buf[0]);
5844         if (magic != 0x669955aa) {
5845                 rc = -ENODEV;
5846                 goto test_nvram_done;
5847         }
5848
5849         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5850                 goto test_nvram_done;
5851
5852         csum = ether_crc_le(0x100, data);
5853         if (csum != CRC32_RESIDUAL) {
5854                 rc = -ENODEV;
5855                 goto test_nvram_done;
5856         }
5857
5858         csum = ether_crc_le(0x100, data + 0x100);
5859         if (csum != CRC32_RESIDUAL) {
5860                 rc = -ENODEV;
5861         }
5862
5863 test_nvram_done:
5864         return rc;
5865 }
5866
5867 static int
5868 bnx2_test_link(struct bnx2 *bp)
5869 {
5870         u32 bmsr;
5871
5872         if (!netif_running(bp->dev))
5873                 return -ENODEV;
5874
5875         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5876                 if (bp->link_up)
5877                         return 0;
5878                 return -ENODEV;
5879         }
5880         spin_lock_bh(&bp->phy_lock);
5881         bnx2_enable_bmsr1(bp);
5882         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5883         bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5884         bnx2_disable_bmsr1(bp);
5885         spin_unlock_bh(&bp->phy_lock);
5886
5887         if (bmsr & BMSR_LSTATUS) {
5888                 return 0;
5889         }
5890         return -ENODEV;
5891 }
5892
5893 static int
5894 bnx2_test_intr(struct bnx2 *bp)
5895 {
5896         int i;
5897         u16 status_idx;
5898
5899         if (!netif_running(bp->dev))
5900                 return -ENODEV;
5901
5902         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5903
5904         /* This register is not touched during run-time. */
5905         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5906         REG_RD(bp, BNX2_HC_COMMAND);
5907
5908         for (i = 0; i < 10; i++) {
5909                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5910                         status_idx) {
5911
5912                         break;
5913                 }
5914
5915                 msleep_interruptible(10);
5916         }
5917         if (i < 10)
5918                 return 0;
5919
5920         return -ENODEV;
5921 }
5922
5923 /* Determining link for parallel detection. */
5924 static int
5925 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5926 {
5927         u32 mode_ctl, an_dbg, exp;
5928
5929         if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5930                 return 0;
5931
5932         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5933         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5934
5935         if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5936                 return 0;
5937
5938         bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5939         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5940         bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5941
5942         if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5943                 return 0;
5944
5945         bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5946         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5947         bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5948
5949         if (exp & MII_EXPAND_REG1_RUDI_C)       /* receiving CONFIG */
5950                 return 0;
5951
5952         return 1;
5953 }
5954
5955 static void
5956 bnx2_5706_serdes_timer(struct bnx2 *bp)
5957 {
5958         int check_link = 1;
5959
5960         spin_lock(&bp->phy_lock);
5961         if (bp->serdes_an_pending) {
5962                 bp->serdes_an_pending--;
5963                 check_link = 0;
5964         } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5965                 u32 bmcr;
5966
5967                 bp->current_interval = BNX2_TIMER_INTERVAL;
5968
5969                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5970
5971                 if (bmcr & BMCR_ANENABLE) {
5972                         if (bnx2_5706_serdes_has_link(bp)) {
5973                                 bmcr &= ~BMCR_ANENABLE;
5974                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5975                                 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5976                                 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5977                         }
5978                 }
5979         }
5980         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5981                  (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5982                 u32 phy2;
5983
5984                 bnx2_write_phy(bp, 0x17, 0x0f01);
5985                 bnx2_read_phy(bp, 0x15, &phy2);
5986                 if (phy2 & 0x20) {
5987                         u32 bmcr;
5988
5989                         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5990                         bmcr |= BMCR_ANENABLE;
5991                         bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5992
5993                         bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5994                 }
5995         } else
5996                 bp->current_interval = BNX2_TIMER_INTERVAL;
5997
5998         if (check_link) {
5999                 u32 val;
6000
6001                 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6002                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6003                 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6004
6005                 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6006                         if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6007                                 bnx2_5706s_force_link_dn(bp, 1);
6008                                 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6009                         } else
6010                                 bnx2_set_link(bp);
6011                 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6012                         bnx2_set_link(bp);
6013         }
6014         spin_unlock(&bp->phy_lock);
6015 }
6016
6017 static void
6018 bnx2_5708_serdes_timer(struct bnx2 *bp)
6019 {
6020         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6021                 return;
6022
6023         if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6024                 bp->serdes_an_pending = 0;
6025                 return;
6026         }
6027
6028         spin_lock(&bp->phy_lock);
6029         if (bp->serdes_an_pending)
6030                 bp->serdes_an_pending--;
6031         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6032                 u32 bmcr;
6033
6034                 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6035                 if (bmcr & BMCR_ANENABLE) {
6036                         bnx2_enable_forced_2g5(bp);
6037                         bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6038                 } else {
6039                         bnx2_disable_forced_2g5(bp);
6040                         bp->serdes_an_pending = 2;
6041                         bp->current_interval = BNX2_TIMER_INTERVAL;
6042                 }
6043
6044         } else
6045                 bp->current_interval = BNX2_TIMER_INTERVAL;
6046
6047         spin_unlock(&bp->phy_lock);
6048 }
6049
6050 static void
6051 bnx2_timer(unsigned long data)
6052 {
6053         struct bnx2 *bp = (struct bnx2 *) data;
6054
6055         if (!netif_running(bp->dev))
6056                 return;
6057
6058         if (atomic_read(&bp->intr_sem) != 0)
6059                 goto bnx2_restart_timer;
6060
6061         if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6062              BNX2_FLAG_USING_MSI)
6063                 bnx2_chk_missed_msi(bp);
6064
6065         bnx2_send_heart_beat(bp);
6066
6067         bp->stats_blk->stat_FwRxDrop =
6068                 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6069
6070         /* workaround occasional corrupted counters */
6071         if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6072                 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6073                                             BNX2_HC_COMMAND_STATS_NOW);
6074
6075         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6076                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6077                         bnx2_5706_serdes_timer(bp);
6078                 else
6079                         bnx2_5708_serdes_timer(bp);
6080         }
6081
6082 bnx2_restart_timer:
6083         mod_timer(&bp->timer, jiffies + bp->current_interval);
6084 }
6085
6086 static int
6087 bnx2_request_irq(struct bnx2 *bp)
6088 {
6089         unsigned long flags;
6090         struct bnx2_irq *irq;
6091         int rc = 0, i;
6092
6093         if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6094                 flags = 0;
6095         else
6096                 flags = IRQF_SHARED;
6097
6098         for (i = 0; i < bp->irq_nvecs; i++) {
6099                 irq = &bp->irq_tbl[i];
6100                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6101                                  &bp->bnx2_napi[i]);
6102                 if (rc)
6103                         break;
6104                 irq->requested = 1;
6105         }
6106         return rc;
6107 }
6108
6109 static void
6110 bnx2_free_irq(struct bnx2 *bp)
6111 {
6112         struct bnx2_irq *irq;
6113         int i;
6114
6115         for (i = 0; i < bp->irq_nvecs; i++) {
6116                 irq = &bp->irq_tbl[i];
6117                 if (irq->requested)
6118                         free_irq(irq->vector, &bp->bnx2_napi[i]);
6119                 irq->requested = 0;
6120         }
6121         if (bp->flags & BNX2_FLAG_USING_MSI)
6122                 pci_disable_msi(bp->pdev);
6123         else if (bp->flags & BNX2_FLAG_USING_MSIX)
6124                 pci_disable_msix(bp->pdev);
6125
6126         bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6127 }
6128
6129 static void
6130 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6131 {
6132         int i, rc;
6133         struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6134         struct net_device *dev = bp->dev;
6135         const int len = sizeof(bp->irq_tbl[0].name);
6136
6137         bnx2_setup_msix_tbl(bp);
6138         REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6139         REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6140         REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6141
6142         /*  Need to flush the previous three writes to ensure MSI-X
6143          *  is setup properly */
6144         REG_RD(bp, BNX2_PCI_MSIX_CONTROL);
6145
6146         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6147                 msix_ent[i].entry = i;
6148                 msix_ent[i].vector = 0;
6149         }
6150
6151         rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6152         if (rc != 0)
6153                 return;
6154
6155         bp->irq_nvecs = msix_vecs;
6156         bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6157         for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6158                 bp->irq_tbl[i].vector = msix_ent[i].vector;
6159                 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6160                 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6161         }
6162 }
6163
6164 static void
6165 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6166 {
6167         int cpus = num_online_cpus();
6168         int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6169
6170         bp->irq_tbl[0].handler = bnx2_interrupt;
6171         strcpy(bp->irq_tbl[0].name, bp->dev->name);
6172         bp->irq_nvecs = 1;
6173         bp->irq_tbl[0].vector = bp->pdev->irq;
6174
6175         if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6176                 bnx2_enable_msix(bp, msix_vecs);
6177
6178         if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6179             !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6180                 if (pci_enable_msi(bp->pdev) == 0) {
6181                         bp->flags |= BNX2_FLAG_USING_MSI;
6182                         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6183                                 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6184                                 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6185                         } else
6186                                 bp->irq_tbl[0].handler = bnx2_msi;
6187
6188                         bp->irq_tbl[0].vector = bp->pdev->irq;
6189                 }
6190         }
6191
6192         bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6193         bp->dev->real_num_tx_queues = bp->num_tx_rings;
6194
6195         bp->num_rx_rings = bp->irq_nvecs;
6196 }
6197
6198 /* Called with rtnl_lock */
6199 static int
6200 bnx2_open(struct net_device *dev)
6201 {
6202         struct bnx2 *bp = netdev_priv(dev);
6203         int rc;
6204
6205         netif_carrier_off(dev);
6206
6207         bnx2_set_power_state(bp, PCI_D0);
6208         bnx2_disable_int(bp);
6209
6210         bnx2_setup_int_mode(bp, disable_msi);
6211         bnx2_init_napi(bp);
6212         bnx2_napi_enable(bp);
6213         rc = bnx2_alloc_mem(bp);
6214         if (rc)
6215                 goto open_err;
6216
6217         rc = bnx2_request_irq(bp);
6218         if (rc)
6219                 goto open_err;
6220
6221         rc = bnx2_init_nic(bp, 1);
6222         if (rc)
6223                 goto open_err;
6224
6225         mod_timer(&bp->timer, jiffies + bp->current_interval);
6226
6227         atomic_set(&bp->intr_sem, 0);
6228
6229         memset(bp->temp_stats_blk, 0, sizeof(struct statistics_block));
6230
6231         bnx2_enable_int(bp);
6232
6233         if (bp->flags & BNX2_FLAG_USING_MSI) {
6234                 /* Test MSI to make sure it is working
6235                  * If MSI test fails, go back to INTx mode
6236                  */
6237                 if (bnx2_test_intr(bp) != 0) {
6238                         netdev_warn(bp->dev, "No interrupt was generated using MSI, switching to INTx mode. Please report this failure to the PCI maintainer and include system chipset information.\n");
6239
6240                         bnx2_disable_int(bp);
6241                         bnx2_free_irq(bp);
6242
6243                         bnx2_setup_int_mode(bp, 1);
6244
6245                         rc = bnx2_init_nic(bp, 0);
6246
6247                         if (!rc)
6248                                 rc = bnx2_request_irq(bp);
6249
6250                         if (rc) {
6251                                 del_timer_sync(&bp->timer);
6252                                 goto open_err;
6253                         }
6254                         bnx2_enable_int(bp);
6255                 }
6256         }
6257         if (bp->flags & BNX2_FLAG_USING_MSI)
6258                 netdev_info(dev, "using MSI\n");
6259         else if (bp->flags & BNX2_FLAG_USING_MSIX)
6260                 netdev_info(dev, "using MSIX\n");
6261
6262         netif_tx_start_all_queues(dev);
6263
6264         return 0;
6265
6266 open_err:
6267         bnx2_napi_disable(bp);
6268         bnx2_free_skbs(bp);
6269         bnx2_free_irq(bp);
6270         bnx2_free_mem(bp);
6271         bnx2_del_napi(bp);
6272         return rc;
6273 }
6274
6275 static void
6276 bnx2_reset_task(struct work_struct *work)
6277 {
6278         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6279
6280         rtnl_lock();
6281         if (!netif_running(bp->dev)) {
6282                 rtnl_unlock();
6283                 return;
6284         }
6285
6286         bnx2_netif_stop(bp, true);
6287
6288         bnx2_init_nic(bp, 1);
6289
6290         atomic_set(&bp->intr_sem, 1);
6291         bnx2_netif_start(bp, true);
6292         rtnl_unlock();
6293 }
6294
6295 static void
6296 bnx2_dump_state(struct bnx2 *bp)
6297 {
6298         struct net_device *dev = bp->dev;
6299         u32 mcp_p0, mcp_p1;
6300
6301         netdev_err(dev, "DEBUG: intr_sem[%x]\n", atomic_read(&bp->intr_sem));
6302         netdev_err(dev, "DEBUG: EMAC_TX_STATUS[%08x] EMAC_RX_STATUS[%08x]\n",
6303                    REG_RD(bp, BNX2_EMAC_TX_STATUS),
6304                    REG_RD(bp, BNX2_EMAC_RX_STATUS));
6305         netdev_err(dev, "DEBUG: RPM_MGMT_PKT_CTRL[%08x]\n",
6306                    REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6307         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6308                 mcp_p0 = BNX2_MCP_STATE_P0;
6309                 mcp_p1 = BNX2_MCP_STATE_P1;
6310         } else {
6311                 mcp_p0 = BNX2_MCP_STATE_P0_5708;
6312                 mcp_p1 = BNX2_MCP_STATE_P1_5708;
6313         }
6314         netdev_err(dev, "DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
6315                    bnx2_reg_rd_ind(bp, mcp_p0), bnx2_reg_rd_ind(bp, mcp_p1));
6316         netdev_err(dev, "DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6317                    REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6318         if (bp->flags & BNX2_FLAG_USING_MSIX)
6319                 netdev_err(dev, "DEBUG: PBA[%08x]\n",
6320                            REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6321 }
6322
6323 static void
6324 bnx2_tx_timeout(struct net_device *dev)
6325 {
6326         struct bnx2 *bp = netdev_priv(dev);
6327
6328         bnx2_dump_state(bp);
6329
6330         /* This allows the netif to be shutdown gracefully before resetting */
6331         schedule_work(&bp->reset_task);
6332 }
6333
6334 #ifdef BCM_VLAN
6335 /* Called with rtnl_lock */
6336 static void
6337 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6338 {
6339         struct bnx2 *bp = netdev_priv(dev);
6340
6341         if (netif_running(dev))
6342                 bnx2_netif_stop(bp, false);
6343
6344         bp->vlgrp = vlgrp;
6345
6346         if (!netif_running(dev))
6347                 return;
6348
6349         bnx2_set_rx_mode(dev);
6350         if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6351                 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6352
6353         bnx2_netif_start(bp, false);
6354 }
6355 #endif
6356
6357 /* Called with netif_tx_lock.
6358  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6359  * netif_wake_queue().
6360  */
6361 static netdev_tx_t
6362 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6363 {
6364         struct bnx2 *bp = netdev_priv(dev);
6365         dma_addr_t mapping;
6366         struct tx_bd *txbd;
6367         struct sw_tx_bd *tx_buf;
6368         u32 len, vlan_tag_flags, last_frag, mss;
6369         u16 prod, ring_prod;
6370         int i;
6371         struct bnx2_napi *bnapi;
6372         struct bnx2_tx_ring_info *txr;
6373         struct netdev_queue *txq;
6374
6375         /*  Determine which tx ring we will be placed on */
6376         i = skb_get_queue_mapping(skb);
6377         bnapi = &bp->bnx2_napi[i];
6378         txr = &bnapi->tx_ring;
6379         txq = netdev_get_tx_queue(dev, i);
6380
6381         if (unlikely(bnx2_tx_avail(bp, txr) <
6382             (skb_shinfo(skb)->nr_frags + 1))) {
6383                 netif_tx_stop_queue(txq);
6384                 netdev_err(dev, "BUG! Tx ring full when queue awake!\n");
6385
6386                 return NETDEV_TX_BUSY;
6387         }
6388         len = skb_headlen(skb);
6389         prod = txr->tx_prod;
6390         ring_prod = TX_RING_IDX(prod);
6391
6392         vlan_tag_flags = 0;
6393         if (skb->ip_summed == CHECKSUM_PARTIAL) {
6394                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6395         }
6396
6397 #ifdef BCM_VLAN
6398         if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6399                 vlan_tag_flags |=
6400                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6401         }
6402 #endif
6403         if ((mss = skb_shinfo(skb)->gso_size)) {
6404                 u32 tcp_opt_len;
6405                 struct iphdr *iph;
6406
6407                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6408
6409                 tcp_opt_len = tcp_optlen(skb);
6410
6411                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6412                         u32 tcp_off = skb_transport_offset(skb) -
6413                                       sizeof(struct ipv6hdr) - ETH_HLEN;
6414
6415                         vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6416                                           TX_BD_FLAGS_SW_FLAGS;
6417                         if (likely(tcp_off == 0))
6418                                 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6419                         else {
6420                                 tcp_off >>= 3;
6421                                 vlan_tag_flags |= ((tcp_off & 0x3) <<
6422                                                    TX_BD_FLAGS_TCP6_OFF0_SHL) |
6423                                                   ((tcp_off & 0x10) <<
6424                                                    TX_BD_FLAGS_TCP6_OFF4_SHL);
6425                                 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6426                         }
6427                 } else {
6428                         iph = ip_hdr(skb);
6429                         if (tcp_opt_len || (iph->ihl > 5)) {
6430                                 vlan_tag_flags |= ((iph->ihl - 5) +
6431                                                    (tcp_opt_len >> 2)) << 8;
6432                         }
6433                 }
6434         } else
6435                 mss = 0;
6436
6437         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6438         if (pci_dma_mapping_error(bp->pdev, mapping)) {
6439                 dev_kfree_skb(skb);
6440                 return NETDEV_TX_OK;
6441         }
6442
6443         tx_buf = &txr->tx_buf_ring[ring_prod];
6444         tx_buf->skb = skb;
6445         dma_unmap_addr_set(tx_buf, mapping, mapping);
6446
6447         txbd = &txr->tx_desc_ring[ring_prod];
6448
6449         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6450         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6451         txbd->tx_bd_mss_nbytes = len | (mss << 16);
6452         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6453
6454         last_frag = skb_shinfo(skb)->nr_frags;
6455         tx_buf->nr_frags = last_frag;
6456         tx_buf->is_gso = skb_is_gso(skb);
6457
6458         for (i = 0; i < last_frag; i++) {
6459                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6460
6461                 prod = NEXT_TX_BD(prod);
6462                 ring_prod = TX_RING_IDX(prod);
6463                 txbd = &txr->tx_desc_ring[ring_prod];
6464
6465                 len = frag->size;
6466                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6467                         len, PCI_DMA_TODEVICE);
6468                 if (pci_dma_mapping_error(bp->pdev, mapping))
6469                         goto dma_error;
6470                 dma_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6471                                    mapping);
6472
6473                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6474                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6475                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6476                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6477
6478         }
6479         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6480
6481         prod = NEXT_TX_BD(prod);
6482         txr->tx_prod_bseq += skb->len;
6483
6484         REG_WR16(bp, txr->tx_bidx_addr, prod);
6485         REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6486
6487         mmiowb();
6488
6489         txr->tx_prod = prod;
6490
6491         if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6492                 netif_tx_stop_queue(txq);
6493                 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6494                         netif_tx_wake_queue(txq);
6495         }
6496
6497         return NETDEV_TX_OK;
6498 dma_error:
6499         /* save value of frag that failed */
6500         last_frag = i;
6501
6502         /* start back at beginning and unmap skb */
6503         prod = txr->tx_prod;
6504         ring_prod = TX_RING_IDX(prod);
6505         tx_buf = &txr->tx_buf_ring[ring_prod];
6506         tx_buf->skb = NULL;
6507         pci_unmap_single(bp->pdev, dma_unmap_addr(tx_buf, mapping),
6508                          skb_headlen(skb), PCI_DMA_TODEVICE);
6509
6510         /* unmap remaining mapped pages */
6511         for (i = 0; i < last_frag; i++) {
6512                 prod = NEXT_TX_BD(prod);
6513                 ring_prod = TX_RING_IDX(prod);
6514                 tx_buf = &txr->tx_buf_ring[ring_prod];
6515                 pci_unmap_page(bp->pdev, dma_unmap_addr(tx_buf, mapping),
6516                                skb_shinfo(skb)->frags[i].size,
6517                                PCI_DMA_TODEVICE);
6518         }
6519
6520         dev_kfree_skb(skb);
6521         return NETDEV_TX_OK;
6522 }
6523
6524 /* Called with rtnl_lock */
6525 static int
6526 bnx2_close(struct net_device *dev)
6527 {
6528         struct bnx2 *bp = netdev_priv(dev);
6529
6530         cancel_work_sync(&bp->reset_task);
6531
6532         bnx2_disable_int_sync(bp);
6533         bnx2_napi_disable(bp);
6534         del_timer_sync(&bp->timer);
6535         bnx2_shutdown_chip(bp);
6536         bnx2_free_irq(bp);
6537         bnx2_free_skbs(bp);
6538         bnx2_free_mem(bp);
6539         bnx2_del_napi(bp);
6540         bp->link_up = 0;
6541         netif_carrier_off(bp->dev);
6542         bnx2_set_power_state(bp, PCI_D3hot);
6543         return 0;
6544 }
6545
6546 static void
6547 bnx2_save_stats(struct bnx2 *bp)
6548 {
6549         u32 *hw_stats = (u32 *) bp->stats_blk;
6550         u32 *temp_stats = (u32 *) bp->temp_stats_blk;
6551         int i;
6552
6553         /* The 1st 10 counters are 64-bit counters */
6554         for (i = 0; i < 20; i += 2) {
6555                 u32 hi;
6556                 u64 lo;
6557
6558                 hi = temp_stats[i] + hw_stats[i];
6559                 lo = (u64) temp_stats[i + 1] + (u64) hw_stats[i + 1];
6560                 if (lo > 0xffffffff)
6561                         hi++;
6562                 temp_stats[i] = hi;
6563                 temp_stats[i + 1] = lo & 0xffffffff;
6564         }
6565
6566         for ( ; i < sizeof(struct statistics_block) / 4; i++)
6567                 temp_stats[i] += hw_stats[i];
6568 }
6569
6570 #define GET_64BIT_NET_STATS64(ctr)                              \
6571         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
6572         (unsigned long) (ctr##_lo)
6573
6574 #define GET_64BIT_NET_STATS32(ctr)                              \
6575         (ctr##_lo)
6576
6577 #if (BITS_PER_LONG == 64)
6578 #define GET_64BIT_NET_STATS(ctr)                                \
6579         GET_64BIT_NET_STATS64(bp->stats_blk->ctr) +             \
6580         GET_64BIT_NET_STATS64(bp->temp_stats_blk->ctr)
6581 #else
6582 #define GET_64BIT_NET_STATS(ctr)                                \
6583         GET_64BIT_NET_STATS32(bp->stats_blk->ctr) +             \
6584         GET_64BIT_NET_STATS32(bp->temp_stats_blk->ctr)
6585 #endif
6586
6587 #define GET_32BIT_NET_STATS(ctr)                                \
6588         (unsigned long) (bp->stats_blk->ctr +                   \
6589                          bp->temp_stats_blk->ctr)
6590
6591 static struct net_device_stats *
6592 bnx2_get_stats(struct net_device *dev)
6593 {
6594         struct bnx2 *bp = netdev_priv(dev);
6595         struct net_device_stats *net_stats = &dev->stats;
6596
6597         if (bp->stats_blk == NULL) {
6598                 return net_stats;
6599         }
6600         net_stats->rx_packets =
6601                 GET_64BIT_NET_STATS(stat_IfHCInUcastPkts) +
6602                 GET_64BIT_NET_STATS(stat_IfHCInMulticastPkts) +
6603                 GET_64BIT_NET_STATS(stat_IfHCInBroadcastPkts);
6604
6605         net_stats->tx_packets =
6606                 GET_64BIT_NET_STATS(stat_IfHCOutUcastPkts) +
6607                 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts) +
6608                 GET_64BIT_NET_STATS(stat_IfHCOutBroadcastPkts);
6609
6610         net_stats->rx_bytes =
6611                 GET_64BIT_NET_STATS(stat_IfHCInOctets);
6612
6613         net_stats->tx_bytes =
6614                 GET_64BIT_NET_STATS(stat_IfHCOutOctets);
6615
6616         net_stats->multicast =
6617                 GET_64BIT_NET_STATS(stat_IfHCOutMulticastPkts);
6618
6619         net_stats->collisions =
6620                 GET_32BIT_NET_STATS(stat_EtherStatsCollisions);
6621
6622         net_stats->rx_length_errors =
6623                 GET_32BIT_NET_STATS(stat_EtherStatsUndersizePkts) +
6624                 GET_32BIT_NET_STATS(stat_EtherStatsOverrsizePkts);
6625
6626         net_stats->rx_over_errors =
6627                 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6628                 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards);
6629
6630         net_stats->rx_frame_errors =
6631                 GET_32BIT_NET_STATS(stat_Dot3StatsAlignmentErrors);
6632
6633         net_stats->rx_crc_errors =
6634                 GET_32BIT_NET_STATS(stat_Dot3StatsFCSErrors);
6635
6636         net_stats->rx_errors = net_stats->rx_length_errors +
6637                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6638                 net_stats->rx_crc_errors;
6639
6640         net_stats->tx_aborted_errors =
6641                 GET_32BIT_NET_STATS(stat_Dot3StatsExcessiveCollisions) +
6642                 GET_32BIT_NET_STATS(stat_Dot3StatsLateCollisions);
6643
6644         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6645             (CHIP_ID(bp) == CHIP_ID_5708_A0))
6646                 net_stats->tx_carrier_errors = 0;
6647         else {
6648                 net_stats->tx_carrier_errors =
6649                         GET_32BIT_NET_STATS(stat_Dot3StatsCarrierSenseErrors);
6650         }
6651
6652         net_stats->tx_errors =
6653                 GET_32BIT_NET_STATS(stat_emac_tx_stat_dot3statsinternalmactransmiterrors) +
6654                 net_stats->tx_aborted_errors +
6655                 net_stats->tx_carrier_errors;
6656
6657         net_stats->rx_missed_errors =
6658                 GET_32BIT_NET_STATS(stat_IfInFTQDiscards) +
6659                 GET_32BIT_NET_STATS(stat_IfInMBUFDiscards) +
6660                 GET_32BIT_NET_STATS(stat_FwRxDrop);
6661
6662         return net_stats;
6663 }
6664
6665 /* All ethtool functions called with rtnl_lock */
6666
6667 static int
6668 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6669 {
6670         struct bnx2 *bp = netdev_priv(dev);
6671         int support_serdes = 0, support_copper = 0;
6672
6673         cmd->supported = SUPPORTED_Autoneg;
6674         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6675                 support_serdes = 1;
6676                 support_copper = 1;
6677         } else if (bp->phy_port == PORT_FIBRE)
6678                 support_serdes = 1;
6679         else
6680                 support_copper = 1;
6681
6682         if (support_serdes) {
6683                 cmd->supported |= SUPPORTED_1000baseT_Full |
6684                         SUPPORTED_FIBRE;
6685                 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6686                         cmd->supported |= SUPPORTED_2500baseX_Full;
6687
6688         }
6689         if (support_copper) {
6690                 cmd->supported |= SUPPORTED_10baseT_Half |
6691                         SUPPORTED_10baseT_Full |
6692                         SUPPORTED_100baseT_Half |
6693                         SUPPORTED_100baseT_Full |
6694                         SUPPORTED_1000baseT_Full |
6695                         SUPPORTED_TP;
6696
6697         }
6698
6699         spin_lock_bh(&bp->phy_lock);
6700         cmd->port = bp->phy_port;
6701         cmd->advertising = bp->advertising;
6702
6703         if (bp->autoneg & AUTONEG_SPEED) {
6704                 cmd->autoneg = AUTONEG_ENABLE;
6705         }
6706         else {
6707                 cmd->autoneg = AUTONEG_DISABLE;
6708         }
6709
6710         if (netif_carrier_ok(dev)) {
6711                 cmd->speed = bp->line_speed;
6712                 cmd->duplex = bp->duplex;
6713         }
6714         else {
6715                 cmd->speed = -1;
6716                 cmd->duplex = -1;
6717         }
6718         spin_unlock_bh(&bp->phy_lock);
6719
6720         cmd->transceiver = XCVR_INTERNAL;
6721         cmd->phy_address = bp->phy_addr;
6722
6723         return 0;
6724 }
6725
6726 static int
6727 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6728 {
6729         struct bnx2 *bp = netdev_priv(dev);
6730         u8 autoneg = bp->autoneg;
6731         u8 req_duplex = bp->req_duplex;
6732         u16 req_line_speed = bp->req_line_speed;
6733         u32 advertising = bp->advertising;
6734         int err = -EINVAL;
6735
6736         spin_lock_bh(&bp->phy_lock);
6737
6738         if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6739                 goto err_out_unlock;
6740
6741         if (cmd->port != bp->phy_port &&
6742             !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6743                 goto err_out_unlock;
6744
6745         /* If device is down, we can store the settings only if the user
6746          * is setting the currently active port.
6747          */
6748         if (!netif_running(dev) && cmd->port != bp->phy_port)
6749                 goto err_out_unlock;
6750
6751         if (cmd->autoneg == AUTONEG_ENABLE) {
6752                 autoneg |= AUTONEG_SPEED;
6753
6754                 advertising = cmd->advertising;
6755                 if (cmd->port == PORT_TP) {
6756                         advertising &= ETHTOOL_ALL_COPPER_SPEED;
6757                         if (!advertising)
6758                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
6759                 } else {
6760                         advertising &= ETHTOOL_ALL_FIBRE_SPEED;
6761                         if (!advertising)
6762                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6763                 }
6764                 advertising |= ADVERTISED_Autoneg;
6765         }
6766         else {
6767                 if (cmd->port == PORT_FIBRE) {
6768                         if ((cmd->speed != SPEED_1000 &&
6769                              cmd->speed != SPEED_2500) ||
6770                             (cmd->duplex != DUPLEX_FULL))
6771                                 goto err_out_unlock;
6772
6773                         if (cmd->speed == SPEED_2500 &&
6774                             !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6775                                 goto err_out_unlock;
6776                 }
6777                 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6778                         goto err_out_unlock;
6779
6780                 autoneg &= ~AUTONEG_SPEED;
6781                 req_line_speed = cmd->speed;
6782                 req_duplex = cmd->duplex;
6783                 advertising = 0;
6784         }
6785
6786         bp->autoneg = autoneg;
6787         bp->advertising = advertising;
6788         bp->req_line_speed = req_line_speed;
6789         bp->req_duplex = req_duplex;
6790
6791         err = 0;
6792         /* If device is down, the new settings will be picked up when it is
6793          * brought up.
6794          */
6795         if (netif_running(dev))
6796                 err = bnx2_setup_phy(bp, cmd->port);
6797
6798 err_out_unlock:
6799         spin_unlock_bh(&bp->phy_lock);
6800
6801         return err;
6802 }
6803
6804 static void
6805 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6806 {
6807         struct bnx2 *bp = netdev_priv(dev);
6808
6809         strcpy(info->driver, DRV_MODULE_NAME);
6810         strcpy(info->version, DRV_MODULE_VERSION);
6811         strcpy(info->bus_info, pci_name(bp->pdev));
6812         strcpy(info->fw_version, bp->fw_version);
6813 }
6814
6815 #define BNX2_REGDUMP_LEN                (32 * 1024)
6816
6817 static int
6818 bnx2_get_regs_len(struct net_device *dev)
6819 {
6820         return BNX2_REGDUMP_LEN;
6821 }
6822
6823 static void
6824 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6825 {
6826         u32 *p = _p, i, offset;
6827         u8 *orig_p = _p;
6828         struct bnx2 *bp = netdev_priv(dev);
6829         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6830                                  0x0800, 0x0880, 0x0c00, 0x0c10,
6831                                  0x0c30, 0x0d08, 0x1000, 0x101c,
6832                                  0x1040, 0x1048, 0x1080, 0x10a4,
6833                                  0x1400, 0x1490, 0x1498, 0x14f0,
6834                                  0x1500, 0x155c, 0x1580, 0x15dc,
6835                                  0x1600, 0x1658, 0x1680, 0x16d8,
6836                                  0x1800, 0x1820, 0x1840, 0x1854,
6837                                  0x1880, 0x1894, 0x1900, 0x1984,
6838                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6839                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
6840                                  0x2000, 0x2030, 0x23c0, 0x2400,
6841                                  0x2800, 0x2820, 0x2830, 0x2850,
6842                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
6843                                  0x3c00, 0x3c94, 0x4000, 0x4010,
6844                                  0x4080, 0x4090, 0x43c0, 0x4458,
6845                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
6846                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
6847                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
6848                                  0x5fc0, 0x6000, 0x6400, 0x6428,
6849                                  0x6800, 0x6848, 0x684c, 0x6860,
6850                                  0x6888, 0x6910, 0x8000 };
6851
6852         regs->version = 0;
6853
6854         memset(p, 0, BNX2_REGDUMP_LEN);
6855
6856         if (!netif_running(bp->dev))
6857                 return;
6858
6859         i = 0;
6860         offset = reg_boundaries[0];
6861         p += offset;
6862         while (offset < BNX2_REGDUMP_LEN) {
6863                 *p++ = REG_RD(bp, offset);
6864                 offset += 4;
6865                 if (offset == reg_boundaries[i + 1]) {
6866                         offset = reg_boundaries[i + 2];
6867                         p = (u32 *) (orig_p + offset);
6868                         i += 2;
6869                 }
6870         }
6871 }
6872
6873 static void
6874 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6875 {
6876         struct bnx2 *bp = netdev_priv(dev);
6877
6878         if (bp->flags & BNX2_FLAG_NO_WOL) {
6879                 wol->supported = 0;
6880                 wol->wolopts = 0;
6881         }
6882         else {
6883                 wol->supported = WAKE_MAGIC;
6884                 if (bp->wol)
6885                         wol->wolopts = WAKE_MAGIC;
6886                 else
6887                         wol->wolopts = 0;
6888         }
6889         memset(&wol->sopass, 0, sizeof(wol->sopass));
6890 }
6891
6892 static int
6893 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6894 {
6895         struct bnx2 *bp = netdev_priv(dev);
6896
6897         if (wol->wolopts & ~WAKE_MAGIC)
6898                 return -EINVAL;
6899
6900         if (wol->wolopts & WAKE_MAGIC) {
6901                 if (bp->flags & BNX2_FLAG_NO_WOL)
6902                         return -EINVAL;
6903
6904                 bp->wol = 1;
6905         }
6906         else {
6907                 bp->wol = 0;
6908         }
6909         return 0;
6910 }
6911
6912 static int
6913 bnx2_nway_reset(struct net_device *dev)
6914 {
6915         struct bnx2 *bp = netdev_priv(dev);
6916         u32 bmcr;
6917
6918         if (!netif_running(dev))
6919                 return -EAGAIN;
6920
6921         if (!(bp->autoneg & AUTONEG_SPEED)) {
6922                 return -EINVAL;
6923         }
6924
6925         spin_lock_bh(&bp->phy_lock);
6926
6927         if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6928                 int rc;
6929
6930                 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6931                 spin_unlock_bh(&bp->phy_lock);
6932                 return rc;
6933         }
6934
6935         /* Force a link down visible on the other side */
6936         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6937                 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6938                 spin_unlock_bh(&bp->phy_lock);
6939
6940                 msleep(20);
6941
6942                 spin_lock_bh(&bp->phy_lock);
6943
6944                 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6945                 bp->serdes_an_pending = 1;
6946                 mod_timer(&bp->timer, jiffies + bp->current_interval);
6947         }
6948
6949         bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6950         bmcr &= ~BMCR_LOOPBACK;
6951         bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6952
6953         spin_unlock_bh(&bp->phy_lock);
6954
6955         return 0;
6956 }
6957
6958 static u32
6959 bnx2_get_link(struct net_device *dev)
6960 {
6961         struct bnx2 *bp = netdev_priv(dev);
6962
6963         return bp->link_up;
6964 }
6965
6966 static int
6967 bnx2_get_eeprom_len(struct net_device *dev)
6968 {
6969         struct bnx2 *bp = netdev_priv(dev);
6970
6971         if (bp->flash_info == NULL)
6972                 return 0;
6973
6974         return (int) bp->flash_size;
6975 }
6976
6977 static int
6978 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6979                 u8 *eebuf)
6980 {
6981         struct bnx2 *bp = netdev_priv(dev);
6982         int rc;
6983
6984         if (!netif_running(dev))
6985                 return -EAGAIN;
6986
6987         /* parameters already validated in ethtool_get_eeprom */
6988
6989         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6990
6991         return rc;
6992 }
6993
6994 static int
6995 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6996                 u8 *eebuf)
6997 {
6998         struct bnx2 *bp = netdev_priv(dev);
6999         int rc;
7000
7001         if (!netif_running(dev))
7002                 return -EAGAIN;
7003
7004         /* parameters already validated in ethtool_set_eeprom */
7005
7006         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
7007
7008         return rc;
7009 }
7010
7011 static int
7012 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7013 {
7014         struct bnx2 *bp = netdev_priv(dev);
7015
7016         memset(coal, 0, sizeof(struct ethtool_coalesce));
7017
7018         coal->rx_coalesce_usecs = bp->rx_ticks;
7019         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7020         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7021         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7022
7023         coal->tx_coalesce_usecs = bp->tx_ticks;
7024         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7025         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7026         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7027
7028         coal->stats_block_coalesce_usecs = bp->stats_ticks;
7029
7030         return 0;
7031 }
7032
7033 static int
7034 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7035 {
7036         struct bnx2 *bp = netdev_priv(dev);
7037
7038         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7039         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7040
7041         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7042         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7043
7044         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7045         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7046
7047         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7048         if (bp->rx_quick_cons_trip_int > 0xff)
7049                 bp->rx_quick_cons_trip_int = 0xff;
7050
7051         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7052         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7053
7054         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7055         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7056
7057         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7058         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7059
7060         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7061         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7062                 0xff;
7063
7064         bp->stats_ticks = coal->stats_block_coalesce_usecs;
7065         if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7066                 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7067                         bp->stats_ticks = USEC_PER_SEC;
7068         }
7069         if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7070                 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7071         bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7072
7073         if (netif_running(bp->dev)) {
7074                 bnx2_netif_stop(bp, true);
7075                 bnx2_init_nic(bp, 0);
7076                 bnx2_netif_start(bp, true);
7077         }
7078
7079         return 0;
7080 }
7081
7082 static void
7083 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7084 {
7085         struct bnx2 *bp = netdev_priv(dev);
7086
7087         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7088         ering->rx_mini_max_pending = 0;
7089         ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7090
7091         ering->rx_pending = bp->rx_ring_size;
7092         ering->rx_mini_pending = 0;
7093         ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7094
7095         ering->tx_max_pending = MAX_TX_DESC_CNT;
7096         ering->tx_pending = bp->tx_ring_size;
7097 }
7098
7099 static int
7100 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7101 {
7102         if (netif_running(bp->dev)) {
7103                 /* Reset will erase chipset stats; save them */
7104                 bnx2_save_stats(bp);
7105
7106                 bnx2_netif_stop(bp, true);
7107                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7108                 bnx2_free_skbs(bp);
7109                 bnx2_free_mem(bp);
7110         }
7111
7112         bnx2_set_rx_ring_size(bp, rx);
7113         bp->tx_ring_size = tx;
7114
7115         if (netif_running(bp->dev)) {
7116                 int rc;
7117
7118                 rc = bnx2_alloc_mem(bp);
7119                 if (!rc)
7120                         rc = bnx2_init_nic(bp, 0);
7121
7122                 if (rc) {
7123                         bnx2_napi_enable(bp);
7124                         dev_close(bp->dev);
7125                         return rc;
7126                 }
7127 #ifdef BCM_CNIC
7128                 mutex_lock(&bp->cnic_lock);
7129                 /* Let cnic know about the new status block. */
7130                 if (bp->cnic_eth_dev.drv_state & CNIC_DRV_STATE_REGD)
7131                         bnx2_setup_cnic_irq_info(bp);
7132                 mutex_unlock(&bp->cnic_lock);
7133 #endif
7134                 bnx2_netif_start(bp, true);
7135         }
7136         return 0;
7137 }
7138
7139 static int
7140 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7141 {
7142         struct bnx2 *bp = netdev_priv(dev);
7143         int rc;
7144
7145         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7146                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7147                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7148
7149                 return -EINVAL;
7150         }
7151         rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7152         return rc;
7153 }
7154
7155 static void
7156 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7157 {
7158         struct bnx2 *bp = netdev_priv(dev);
7159
7160         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7161         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7162         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7163 }
7164
7165 static int
7166 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7167 {
7168         struct bnx2 *bp = netdev_priv(dev);
7169
7170         bp->req_flow_ctrl = 0;
7171         if (epause->rx_pause)
7172                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7173         if (epause->tx_pause)
7174                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7175
7176         if (epause->autoneg) {
7177                 bp->autoneg |= AUTONEG_FLOW_CTRL;
7178         }
7179         else {
7180                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7181         }
7182
7183         if (netif_running(dev)) {
7184                 spin_lock_bh(&bp->phy_lock);
7185                 bnx2_setup_phy(bp, bp->phy_port);
7186                 spin_unlock_bh(&bp->phy_lock);
7187         }
7188
7189         return 0;
7190 }
7191
7192 static u32
7193 bnx2_get_rx_csum(struct net_device *dev)
7194 {
7195         struct bnx2 *bp = netdev_priv(dev);
7196
7197         return bp->rx_csum;
7198 }
7199
7200 static int
7201 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7202 {
7203         struct bnx2 *bp = netdev_priv(dev);
7204
7205         bp->rx_csum = data;
7206         return 0;
7207 }
7208
7209 static int
7210 bnx2_set_tso(struct net_device *dev, u32 data)
7211 {
7212         struct bnx2 *bp = netdev_priv(dev);
7213
7214         if (data) {
7215                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7216                 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7217                         dev->features |= NETIF_F_TSO6;
7218         } else
7219                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7220                                    NETIF_F_TSO_ECN);
7221         return 0;
7222 }
7223
7224 static struct {
7225         char string[ETH_GSTRING_LEN];
7226 } bnx2_stats_str_arr[] = {
7227         { "rx_bytes" },
7228         { "rx_error_bytes" },
7229         { "tx_bytes" },
7230         { "tx_error_bytes" },
7231         { "rx_ucast_packets" },
7232         { "rx_mcast_packets" },
7233         { "rx_bcast_packets" },
7234         { "tx_ucast_packets" },
7235         { "tx_mcast_packets" },
7236         { "tx_bcast_packets" },
7237         { "tx_mac_errors" },
7238         { "tx_carrier_errors" },
7239         { "rx_crc_errors" },
7240         { "rx_align_errors" },
7241         { "tx_single_collisions" },
7242         { "tx_multi_collisions" },
7243         { "tx_deferred" },
7244         { "tx_excess_collisions" },
7245         { "tx_late_collisions" },
7246         { "tx_total_collisions" },
7247         { "rx_fragments" },
7248         { "rx_jabbers" },
7249         { "rx_undersize_packets" },
7250         { "rx_oversize_packets" },
7251         { "rx_64_byte_packets" },
7252         { "rx_65_to_127_byte_packets" },
7253         { "rx_128_to_255_byte_packets" },
7254         { "rx_256_to_511_byte_packets" },
7255         { "rx_512_to_1023_byte_packets" },
7256         { "rx_1024_to_1522_byte_packets" },
7257         { "rx_1523_to_9022_byte_packets" },
7258         { "tx_64_byte_packets" },
7259         { "tx_65_to_127_byte_packets" },
7260         { "tx_128_to_255_byte_packets" },
7261         { "tx_256_to_511_byte_packets" },
7262         { "tx_512_to_1023_byte_packets" },
7263         { "tx_1024_to_1522_byte_packets" },
7264         { "tx_1523_to_9022_byte_packets" },
7265         { "rx_xon_frames" },
7266         { "rx_xoff_frames" },
7267         { "tx_xon_frames" },
7268         { "tx_xoff_frames" },
7269         { "rx_mac_ctrl_frames" },
7270         { "rx_filtered_packets" },
7271         { "rx_ftq_discards" },
7272         { "rx_discards" },
7273         { "rx_fw_discards" },
7274 };
7275
7276 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7277                         sizeof(bnx2_stats_str_arr[0]))
7278
7279 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7280
7281 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7282     STATS_OFFSET32(stat_IfHCInOctets_hi),
7283     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7284     STATS_OFFSET32(stat_IfHCOutOctets_hi),
7285     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7286     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7287     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7288     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7289     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7290     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7291     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7292     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7293     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7294     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7295     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7296     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7297     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7298     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7299     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7300     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7301     STATS_OFFSET32(stat_EtherStatsCollisions),
7302     STATS_OFFSET32(stat_EtherStatsFragments),
7303     STATS_OFFSET32(stat_EtherStatsJabbers),
7304     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7305     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7306     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7307     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7308     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7309     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7310     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7311     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7312     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7313     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7314     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7315     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7316     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7317     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7318     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7319     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7320     STATS_OFFSET32(stat_XonPauseFramesReceived),
7321     STATS_OFFSET32(stat_XoffPauseFramesReceived),
7322     STATS_OFFSET32(stat_OutXonSent),
7323     STATS_OFFSET32(stat_OutXoffSent),
7324     STATS_OFFSET32(stat_MacControlFramesReceived),
7325     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7326     STATS_OFFSET32(stat_IfInFTQDiscards),
7327     STATS_OFFSET32(stat_IfInMBUFDiscards),
7328     STATS_OFFSET32(stat_FwRxDrop),
7329 };
7330
7331 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7332  * skipped because of errata.
7333  */
7334 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7335         8,0,8,8,8,8,8,8,8,8,
7336         4,0,4,4,4,4,4,4,4,4,
7337         4,4,4,4,4,4,4,4,4,4,
7338         4,4,4,4,4,4,4,4,4,4,
7339         4,4,4,4,4,4,4,
7340 };
7341
7342 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7343         8,0,8,8,8,8,8,8,8,8,
7344         4,4,4,4,4,4,4,4,4,4,
7345         4,4,4,4,4,4,4,4,4,4,
7346         4,4,4,4,4,4,4,4,4,4,
7347         4,4,4,4,4,4,4,
7348 };
7349
7350 #define BNX2_NUM_TESTS 6
7351
7352 static struct {
7353         char string[ETH_GSTRING_LEN];
7354 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7355         { "register_test (offline)" },
7356         { "memory_test (offline)" },
7357         { "loopback_test (offline)" },
7358         { "nvram_test (online)" },
7359         { "interrupt_test (online)" },
7360         { "link_test (online)" },
7361 };
7362
7363 static int
7364 bnx2_get_sset_count(struct net_device *dev, int sset)
7365 {
7366         switch (sset) {
7367         case ETH_SS_TEST:
7368                 return BNX2_NUM_TESTS;
7369         case ETH_SS_STATS:
7370                 return BNX2_NUM_STATS;
7371         default:
7372                 return -EOPNOTSUPP;
7373         }
7374 }
7375
7376 static void
7377 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7378 {
7379         struct bnx2 *bp = netdev_priv(dev);
7380
7381         bnx2_set_power_state(bp, PCI_D0);
7382
7383         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7384         if (etest->flags & ETH_TEST_FL_OFFLINE) {
7385                 int i;
7386
7387                 bnx2_netif_stop(bp, true);
7388                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7389                 bnx2_free_skbs(bp);
7390
7391                 if (bnx2_test_registers(bp) != 0) {
7392                         buf[0] = 1;
7393                         etest->flags |= ETH_TEST_FL_FAILED;
7394                 }
7395                 if (bnx2_test_memory(bp) != 0) {
7396                         buf[1] = 1;
7397                         etest->flags |= ETH_TEST_FL_FAILED;
7398                 }
7399                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7400                         etest->flags |= ETH_TEST_FL_FAILED;
7401
7402                 if (!netif_running(bp->dev))
7403                         bnx2_shutdown_chip(bp);
7404                 else {
7405                         bnx2_init_nic(bp, 1);
7406                         bnx2_netif_start(bp, true);
7407                 }
7408
7409                 /* wait for link up */
7410                 for (i = 0; i < 7; i++) {
7411                         if (bp->link_up)
7412                                 break;
7413                         msleep_interruptible(1000);
7414                 }
7415         }
7416
7417         if (bnx2_test_nvram(bp) != 0) {
7418                 buf[3] = 1;
7419                 etest->flags |= ETH_TEST_FL_FAILED;
7420         }
7421         if (bnx2_test_intr(bp) != 0) {
7422                 buf[4] = 1;
7423                 etest->flags |= ETH_TEST_FL_FAILED;
7424         }
7425
7426         if (bnx2_test_link(bp) != 0) {
7427                 buf[5] = 1;
7428                 etest->flags |= ETH_TEST_FL_FAILED;
7429
7430         }
7431         if (!netif_running(bp->dev))
7432                 bnx2_set_power_state(bp, PCI_D3hot);
7433 }
7434
7435 static void
7436 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7437 {
7438         switch (stringset) {
7439         case ETH_SS_STATS:
7440                 memcpy(buf, bnx2_stats_str_arr,
7441                         sizeof(bnx2_stats_str_arr));
7442                 break;
7443         case ETH_SS_TEST:
7444                 memcpy(buf, bnx2_tests_str_arr,
7445                         sizeof(bnx2_tests_str_arr));
7446                 break;
7447         }
7448 }
7449
7450 static void
7451 bnx2_get_ethtool_stats(struct net_device *dev,
7452                 struct ethtool_stats *stats, u64 *buf)
7453 {
7454         struct bnx2 *bp = netdev_priv(dev);
7455         int i;
7456         u32 *hw_stats = (u32 *) bp->stats_blk;
7457         u32 *temp_stats = (u32 *) bp->temp_stats_blk;
7458         u8 *stats_len_arr = NULL;
7459
7460         if (hw_stats == NULL) {
7461                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7462                 return;
7463         }
7464
7465         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7466             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7467             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7468             (CHIP_ID(bp) == CHIP_ID_5708_A0))
7469                 stats_len_arr = bnx2_5706_stats_len_arr;
7470         else
7471                 stats_len_arr = bnx2_5708_stats_len_arr;
7472
7473         for (i = 0; i < BNX2_NUM_STATS; i++) {
7474                 unsigned long offset;
7475
7476                 if (stats_len_arr[i] == 0) {
7477                         /* skip this counter */
7478                         buf[i] = 0;
7479                         continue;
7480                 }
7481
7482                 offset = bnx2_stats_offset_arr[i];
7483                 if (stats_len_arr[i] == 4) {
7484                         /* 4-byte counter */
7485                         buf[i] = (u64) *(hw_stats + offset) +
7486                                  *(temp_stats + offset);
7487                         continue;
7488                 }
7489                 /* 8-byte counter */
7490                 buf[i] = (((u64) *(hw_stats + offset)) << 32) +
7491                          *(hw_stats + offset + 1) +
7492                          (((u64) *(temp_stats + offset)) << 32) +
7493                          *(temp_stats + offset + 1);
7494         }
7495 }
7496
7497 static int
7498 bnx2_phys_id(struct net_device *dev, u32 data)
7499 {
7500         struct bnx2 *bp = netdev_priv(dev);
7501         int i;
7502         u32 save;
7503
7504         bnx2_set_power_state(bp, PCI_D0);
7505
7506         if (data == 0)
7507                 data = 2;
7508
7509         save = REG_RD(bp, BNX2_MISC_CFG);
7510         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7511
7512         for (i = 0; i < (data * 2); i++) {
7513                 if ((i % 2) == 0) {
7514                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7515                 }
7516                 else {
7517                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7518                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
7519                                 BNX2_EMAC_LED_100MB_OVERRIDE |
7520                                 BNX2_EMAC_LED_10MB_OVERRIDE |
7521                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7522                                 BNX2_EMAC_LED_TRAFFIC);
7523                 }
7524                 msleep_interruptible(500);
7525                 if (signal_pending(current))
7526                         break;
7527         }
7528         REG_WR(bp, BNX2_EMAC_LED, 0);
7529         REG_WR(bp, BNX2_MISC_CFG, save);
7530
7531         if (!netif_running(dev))
7532                 bnx2_set_power_state(bp, PCI_D3hot);
7533
7534         return 0;
7535 }
7536
7537 static int
7538 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7539 {
7540         struct bnx2 *bp = netdev_priv(dev);
7541
7542         if (CHIP_NUM(bp) == CHIP_NUM_5709)
7543                 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7544         else
7545                 return (ethtool_op_set_tx_csum(dev, data));
7546 }
7547
7548 static const struct ethtool_ops bnx2_ethtool_ops = {
7549         .get_settings           = bnx2_get_settings,
7550         .set_settings           = bnx2_set_settings,
7551         .get_drvinfo            = bnx2_get_drvinfo,
7552         .get_regs_len           = bnx2_get_regs_len,
7553         .get_regs               = bnx2_get_regs,
7554         .get_wol                = bnx2_get_wol,
7555         .set_wol                = bnx2_set_wol,
7556         .nway_reset             = bnx2_nway_reset,
7557         .get_link               = bnx2_get_link,
7558         .get_eeprom_len         = bnx2_get_eeprom_len,
7559         .get_eeprom             = bnx2_get_eeprom,
7560         .set_eeprom             = bnx2_set_eeprom,
7561         .get_coalesce           = bnx2_get_coalesce,
7562         .set_coalesce           = bnx2_set_coalesce,
7563         .get_ringparam          = bnx2_get_ringparam,
7564         .set_ringparam          = bnx2_set_ringparam,
7565         .get_pauseparam         = bnx2_get_pauseparam,
7566         .set_pauseparam         = bnx2_set_pauseparam,
7567         .get_rx_csum            = bnx2_get_rx_csum,
7568         .set_rx_csum            = bnx2_set_rx_csum,
7569         .set_tx_csum            = bnx2_set_tx_csum,
7570         .set_sg                 = ethtool_op_set_sg,
7571         .set_tso                = bnx2_set_tso,
7572         .self_test              = bnx2_self_test,
7573         .get_strings            = bnx2_get_strings,
7574         .phys_id                = bnx2_phys_id,
7575         .get_ethtool_stats      = bnx2_get_ethtool_stats,
7576         .get_sset_count         = bnx2_get_sset_count,
7577 };
7578
7579 /* Called with rtnl_lock */
7580 static int
7581 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7582 {
7583         struct mii_ioctl_data *data = if_mii(ifr);
7584         struct bnx2 *bp = netdev_priv(dev);
7585         int err;
7586
7587         switch(cmd) {
7588         case SIOCGMIIPHY:
7589                 data->phy_id = bp->phy_addr;
7590
7591                 /* fallthru */
7592         case SIOCGMIIREG: {
7593                 u32 mii_regval;
7594
7595                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7596                         return -EOPNOTSUPP;
7597
7598                 if (!netif_running(dev))
7599                         return -EAGAIN;
7600
7601                 spin_lock_bh(&bp->phy_lock);
7602                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7603                 spin_unlock_bh(&bp->phy_lock);
7604
7605                 data->val_out = mii_regval;
7606
7607                 return err;
7608         }
7609
7610         case SIOCSMIIREG:
7611                 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7612                         return -EOPNOTSUPP;
7613
7614                 if (!netif_running(dev))
7615                         return -EAGAIN;
7616
7617                 spin_lock_bh(&bp->phy_lock);
7618                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7619                 spin_unlock_bh(&bp->phy_lock);
7620
7621                 return err;
7622
7623         default:
7624                 /* do nothing */
7625                 break;
7626         }
7627         return -EOPNOTSUPP;
7628 }
7629
7630 /* Called with rtnl_lock */
7631 static int
7632 bnx2_change_mac_addr(struct net_device *dev, void *p)
7633 {
7634         struct sockaddr *addr = p;
7635         struct bnx2 *bp = netdev_priv(dev);
7636
7637         if (!is_valid_ether_addr(addr->sa_data))
7638                 return -EINVAL;
7639
7640         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7641         if (netif_running(dev))
7642                 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7643
7644         return 0;
7645 }
7646
7647 /* Called with rtnl_lock */
7648 static int
7649 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7650 {
7651         struct bnx2 *bp = netdev_priv(dev);
7652
7653         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7654                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7655                 return -EINVAL;
7656
7657         dev->mtu = new_mtu;
7658         return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7659 }
7660
7661 #ifdef CONFIG_NET_POLL_CONTROLLER
7662 static void
7663 poll_bnx2(struct net_device *dev)
7664 {
7665         struct bnx2 *bp = netdev_priv(dev);
7666         int i;
7667
7668         for (i = 0; i < bp->irq_nvecs; i++) {
7669                 struct bnx2_irq *irq = &bp->irq_tbl[i];
7670
7671                 disable_irq(irq->vector);
7672                 irq->handler(irq->vector, &bp->bnx2_napi[i]);
7673                 enable_irq(irq->vector);
7674         }
7675 }
7676 #endif
7677
7678 static void __devinit
7679 bnx2_get_5709_media(struct bnx2 *bp)
7680 {
7681         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7682         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7683         u32 strap;
7684
7685         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7686                 return;
7687         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7688                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7689                 return;
7690         }
7691
7692         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7693                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7694         else
7695                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7696
7697         if (PCI_FUNC(bp->pdev->devfn) == 0) {
7698                 switch (strap) {
7699                 case 0x4:
7700                 case 0x5:
7701                 case 0x6:
7702                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7703                         return;
7704                 }
7705         } else {
7706                 switch (strap) {
7707                 case 0x1:
7708                 case 0x2:
7709                 case 0x4:
7710                         bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7711                         return;
7712                 }
7713         }
7714 }
7715
7716 static void __devinit
7717 bnx2_get_pci_speed(struct bnx2 *bp)
7718 {
7719         u32 reg;
7720
7721         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7722         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7723                 u32 clkreg;
7724
7725                 bp->flags |= BNX2_FLAG_PCIX;
7726
7727                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7728
7729                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7730                 switch (clkreg) {
7731                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7732                         bp->bus_speed_mhz = 133;
7733                         break;
7734
7735                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7736                         bp->bus_speed_mhz = 100;
7737                         break;
7738
7739                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7740                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7741                         bp->bus_speed_mhz = 66;
7742                         break;
7743
7744                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7745                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7746                         bp->bus_speed_mhz = 50;
7747                         break;
7748
7749                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7750                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7751                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7752                         bp->bus_speed_mhz = 33;
7753                         break;
7754                 }
7755         }
7756         else {
7757                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7758                         bp->bus_speed_mhz = 66;
7759                 else
7760                         bp->bus_speed_mhz = 33;
7761         }
7762
7763         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7764                 bp->flags |= BNX2_FLAG_PCI_32BIT;
7765
7766 }
7767
7768 static void __devinit
7769 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7770 {
7771         int rc, i, j;
7772         u8 *data;
7773         unsigned int block_end, rosize, len;
7774
7775 #define BNX2_VPD_NVRAM_OFFSET   0x300
7776 #define BNX2_VPD_LEN            128
7777 #define BNX2_MAX_VER_SLEN       30
7778
7779         data = kmalloc(256, GFP_KERNEL);
7780         if (!data)
7781                 return;
7782
7783         rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7784                              BNX2_VPD_LEN);
7785         if (rc)
7786                 goto vpd_done;
7787
7788         for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7789                 data[i] = data[i + BNX2_VPD_LEN + 3];
7790                 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7791                 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7792                 data[i + 3] = data[i + BNX2_VPD_LEN];
7793         }
7794
7795         i = pci_vpd_find_tag(data, 0, BNX2_VPD_LEN, PCI_VPD_LRDT_RO_DATA);
7796         if (i < 0)
7797                 goto vpd_done;
7798
7799         rosize = pci_vpd_lrdt_size(&data[i]);
7800         i += PCI_VPD_LRDT_TAG_SIZE;
7801         block_end = i + rosize;
7802
7803         if (block_end > BNX2_VPD_LEN)
7804                 goto vpd_done;
7805
7806         j = pci_vpd_find_info_keyword(data, i, rosize,
7807                                       PCI_VPD_RO_KEYWORD_MFR_ID);
7808         if (j < 0)
7809                 goto vpd_done;
7810
7811         len = pci_vpd_info_field_size(&data[j]);
7812
7813         j += PCI_VPD_INFO_FLD_HDR_SIZE;
7814         if (j + len > block_end || len != 4 ||
7815             memcmp(&data[j], "1028", 4))
7816                 goto vpd_done;
7817
7818         j = pci_vpd_find_info_keyword(data, i, rosize,
7819                                       PCI_VPD_RO_KEYWORD_VENDOR0);
7820         if (j < 0)
7821                 goto vpd_done;
7822
7823         len = pci_vpd_info_field_size(&data[j]);
7824
7825         j += PCI_VPD_INFO_FLD_HDR_SIZE;
7826         if (j + len > block_end || len > BNX2_MAX_VER_SLEN)
7827                 goto vpd_done;
7828
7829         memcpy(bp->fw_version, &data[j], len);
7830         bp->fw_version[len] = ' ';
7831
7832 vpd_done:
7833         kfree(data);
7834 }
7835
7836 static int __devinit
7837 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7838 {
7839         struct bnx2 *bp;
7840         unsigned long mem_len;
7841         int rc, i, j;
7842         u32 reg;
7843         u64 dma_mask, persist_dma_mask;
7844
7845         SET_NETDEV_DEV(dev, &pdev->dev);
7846         bp = netdev_priv(dev);
7847
7848         bp->flags = 0;
7849         bp->phy_flags = 0;
7850
7851         bp->temp_stats_blk =
7852                 kzalloc(sizeof(struct statistics_block), GFP_KERNEL);
7853
7854         if (bp->temp_stats_blk == NULL) {
7855                 rc = -ENOMEM;
7856                 goto err_out;
7857         }
7858
7859         /* enable device (incl. PCI PM wakeup), and bus-mastering */
7860         rc = pci_enable_device(pdev);
7861         if (rc) {
7862                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
7863                 goto err_out;
7864         }
7865
7866         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7867                 dev_err(&pdev->dev,
7868                         "Cannot find PCI device base address, aborting\n");
7869                 rc = -ENODEV;
7870                 goto err_out_disable;
7871         }
7872
7873         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7874         if (rc) {
7875                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
7876                 goto err_out_disable;
7877         }
7878
7879         pci_set_master(pdev);
7880         pci_save_state(pdev);
7881
7882         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7883         if (bp->pm_cap == 0) {
7884                 dev_err(&pdev->dev,
7885                         "Cannot find power management capability, aborting\n");
7886                 rc = -EIO;
7887                 goto err_out_release;
7888         }
7889
7890         bp->dev = dev;
7891         bp->pdev = pdev;
7892
7893         spin_lock_init(&bp->phy_lock);
7894         spin_lock_init(&bp->indirect_lock);
7895 #ifdef BCM_CNIC
7896         mutex_init(&bp->cnic_lock);
7897 #endif
7898         INIT_WORK(&bp->reset_task, bnx2_reset_task);
7899
7900         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7901         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7902         dev->mem_end = dev->mem_start + mem_len;
7903         dev->irq = pdev->irq;
7904
7905         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7906
7907         if (!bp->regview) {
7908                 dev_err(&pdev->dev, "Cannot map register space, aborting\n");
7909                 rc = -ENOMEM;
7910                 goto err_out_release;
7911         }
7912
7913         /* Configure byte swap and enable write to the reg_window registers.
7914          * Rely on CPU to do target byte swapping on big endian systems
7915          * The chip's target access swapping will not swap all accesses
7916          */
7917         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7918                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7919                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7920
7921         bnx2_set_power_state(bp, PCI_D0);
7922
7923         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7924
7925         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7926                 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7927                         dev_err(&pdev->dev,
7928                                 "Cannot find PCIE capability, aborting\n");
7929                         rc = -EIO;
7930                         goto err_out_unmap;
7931                 }
7932                 bp->flags |= BNX2_FLAG_PCIE;
7933                 if (CHIP_REV(bp) == CHIP_REV_Ax)
7934                         bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7935         } else {
7936                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7937                 if (bp->pcix_cap == 0) {
7938                         dev_err(&pdev->dev,
7939                                 "Cannot find PCIX capability, aborting\n");
7940                         rc = -EIO;
7941                         goto err_out_unmap;
7942                 }
7943                 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7944         }
7945
7946         if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7947                 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7948                         bp->flags |= BNX2_FLAG_MSIX_CAP;
7949         }
7950
7951         if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7952                 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7953                         bp->flags |= BNX2_FLAG_MSI_CAP;
7954         }
7955
7956         /* 5708 cannot support DMA addresses > 40-bit.  */
7957         if (CHIP_NUM(bp) == CHIP_NUM_5708)
7958                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7959         else
7960                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7961
7962         /* Configure DMA attributes. */
7963         if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7964                 dev->features |= NETIF_F_HIGHDMA;
7965                 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7966                 if (rc) {
7967                         dev_err(&pdev->dev,
7968                                 "pci_set_consistent_dma_mask failed, aborting\n");
7969                         goto err_out_unmap;
7970                 }
7971         } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7972                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
7973                 goto err_out_unmap;
7974         }
7975
7976         if (!(bp->flags & BNX2_FLAG_PCIE))
7977                 bnx2_get_pci_speed(bp);
7978
7979         /* 5706A0 may falsely detect SERR and PERR. */
7980         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7981                 reg = REG_RD(bp, PCI_COMMAND);
7982                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7983                 REG_WR(bp, PCI_COMMAND, reg);
7984         }
7985         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7986                 !(bp->flags & BNX2_FLAG_PCIX)) {
7987
7988                 dev_err(&pdev->dev,
7989                         "5706 A1 can only be used in a PCIX bus, aborting\n");
7990                 goto err_out_unmap;
7991         }
7992
7993         bnx2_init_nvram(bp);
7994
7995         reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7996
7997         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7998             BNX2_SHM_HDR_SIGNATURE_SIG) {
7999                 u32 off = PCI_FUNC(pdev->devfn) << 2;
8000
8001                 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
8002         } else
8003                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
8004
8005         /* Get the permanent MAC address.  First we need to make sure the
8006          * firmware is actually running.
8007          */
8008         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
8009
8010         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
8011             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
8012                 dev_err(&pdev->dev, "Firmware not running, aborting\n");
8013                 rc = -ENODEV;
8014                 goto err_out_unmap;
8015         }
8016
8017         bnx2_read_vpd_fw_ver(bp);
8018
8019         j = strlen(bp->fw_version);
8020         reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
8021         for (i = 0; i < 3 && j < 24; i++) {
8022                 u8 num, k, skip0;
8023
8024                 if (i == 0) {
8025                         bp->fw_version[j++] = 'b';
8026                         bp->fw_version[j++] = 'c';
8027                         bp->fw_version[j++] = ' ';
8028                 }
8029                 num = (u8) (reg >> (24 - (i * 8)));
8030                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8031                         if (num >= k || !skip0 || k == 1) {
8032                                 bp->fw_version[j++] = (num / k) + '0';
8033                                 skip0 = 0;
8034                         }
8035                 }
8036                 if (i != 2)
8037                         bp->fw_version[j++] = '.';
8038         }
8039         reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8040         if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8041                 bp->wol = 1;
8042
8043         if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8044                 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8045
8046                 for (i = 0; i < 30; i++) {
8047                         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8048                         if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8049                                 break;
8050                         msleep(10);
8051                 }
8052         }
8053         reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8054         reg &= BNX2_CONDITION_MFW_RUN_MASK;
8055         if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8056             reg != BNX2_CONDITION_MFW_RUN_NONE) {
8057                 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8058
8059                 if (j < 32)
8060                         bp->fw_version[j++] = ' ';
8061                 for (i = 0; i < 3 && j < 28; i++) {
8062                         reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8063                         reg = swab32(reg);
8064                         memcpy(&bp->fw_version[j], &reg, 4);
8065                         j += 4;
8066                 }
8067         }
8068
8069         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8070         bp->mac_addr[0] = (u8) (reg >> 8);
8071         bp->mac_addr[1] = (u8) reg;
8072
8073         reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8074         bp->mac_addr[2] = (u8) (reg >> 24);
8075         bp->mac_addr[3] = (u8) (reg >> 16);
8076         bp->mac_addr[4] = (u8) (reg >> 8);
8077         bp->mac_addr[5] = (u8) reg;
8078
8079         bp->tx_ring_size = MAX_TX_DESC_CNT;
8080         bnx2_set_rx_ring_size(bp, 255);
8081
8082         bp->rx_csum = 1;
8083
8084         bp->tx_quick_cons_trip_int = 2;
8085         bp->tx_quick_cons_trip = 20;
8086         bp->tx_ticks_int = 18;
8087         bp->tx_ticks = 80;
8088
8089         bp->rx_quick_cons_trip_int = 2;
8090         bp->rx_quick_cons_trip = 12;
8091         bp->rx_ticks_int = 18;
8092         bp->rx_ticks = 18;
8093
8094         bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8095
8096         bp->current_interval = BNX2_TIMER_INTERVAL;
8097
8098         bp->phy_addr = 1;
8099
8100         /* Disable WOL support if we are running on a SERDES chip. */
8101         if (CHIP_NUM(bp) == CHIP_NUM_5709)
8102                 bnx2_get_5709_media(bp);
8103         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8104                 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8105
8106         bp->phy_port = PORT_TP;
8107         if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8108                 bp->phy_port = PORT_FIBRE;
8109                 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8110                 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8111                         bp->flags |= BNX2_FLAG_NO_WOL;
8112                         bp->wol = 0;
8113                 }
8114                 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8115                         /* Don't do parallel detect on this board because of
8116                          * some board problems.  The link will not go down
8117                          * if we do parallel detect.
8118                          */
8119                         if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8120                             pdev->subsystem_device == 0x310c)
8121                                 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8122                 } else {
8123                         bp->phy_addr = 2;
8124                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8125                                 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8126                 }
8127         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8128                    CHIP_NUM(bp) == CHIP_NUM_5708)
8129                 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8130         else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8131                  (CHIP_REV(bp) == CHIP_REV_Ax ||
8132                   CHIP_REV(bp) == CHIP_REV_Bx))
8133                 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8134
8135         bnx2_init_fw_cap(bp);
8136
8137         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8138             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8139             (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8140             !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8141                 bp->flags |= BNX2_FLAG_NO_WOL;
8142                 bp->wol = 0;
8143         }
8144
8145         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8146                 bp->tx_quick_cons_trip_int =
8147                         bp->tx_quick_cons_trip;
8148                 bp->tx_ticks_int = bp->tx_ticks;
8149                 bp->rx_quick_cons_trip_int =
8150                         bp->rx_quick_cons_trip;
8151                 bp->rx_ticks_int = bp->rx_ticks;
8152                 bp->comp_prod_trip_int = bp->comp_prod_trip;
8153                 bp->com_ticks_int = bp->com_ticks;
8154                 bp->cmd_ticks_int = bp->cmd_ticks;
8155         }
8156
8157         /* Disable MSI on 5706 if AMD 8132 bridge is found.
8158          *
8159          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
8160          * with byte enables disabled on the unused 32-bit word.  This is legal
8161          * but causes problems on the AMD 8132 which will eventually stop
8162          * responding after a while.
8163          *
8164          * AMD believes this incompatibility is unique to the 5706, and
8165          * prefers to locally disable MSI rather than globally disabling it.
8166          */
8167         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8168                 struct pci_dev *amd_8132 = NULL;
8169
8170                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8171                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
8172                                                   amd_8132))) {
8173
8174                         if (amd_8132->revision >= 0x10 &&
8175                             amd_8132->revision <= 0x13) {
8176                                 disable_msi = 1;
8177                                 pci_dev_put(amd_8132);
8178                                 break;
8179                         }
8180                 }
8181         }
8182
8183         bnx2_set_default_link(bp);
8184         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8185
8186         init_timer(&bp->timer);
8187         bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8188         bp->timer.data = (unsigned long) bp;
8189         bp->timer.function = bnx2_timer;
8190
8191         return 0;
8192
8193 err_out_unmap:
8194         if (bp->regview) {
8195                 iounmap(bp->regview);
8196                 bp->regview = NULL;
8197         }
8198
8199 err_out_release:
8200         pci_release_regions(pdev);
8201
8202 err_out_disable:
8203         pci_disable_device(pdev);
8204         pci_set_drvdata(pdev, NULL);
8205
8206 err_out:
8207         return rc;
8208 }
8209
8210 static char * __devinit
8211 bnx2_bus_string(struct bnx2 *bp, char *str)
8212 {
8213         char *s = str;
8214
8215         if (bp->flags & BNX2_FLAG_PCIE) {
8216                 s += sprintf(s, "PCI Express");
8217         } else {
8218                 s += sprintf(s, "PCI");
8219                 if (bp->flags & BNX2_FLAG_PCIX)
8220                         s += sprintf(s, "-X");
8221                 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8222                         s += sprintf(s, " 32-bit");
8223                 else
8224                         s += sprintf(s, " 64-bit");
8225                 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8226         }
8227         return str;
8228 }
8229
8230 static void
8231 bnx2_del_napi(struct bnx2 *bp)
8232 {
8233         int i;
8234
8235         for (i = 0; i < bp->irq_nvecs; i++)
8236                 netif_napi_del(&bp->bnx2_napi[i].napi);
8237 }
8238
8239 static void
8240 bnx2_init_napi(struct bnx2 *bp)
8241 {
8242         int i;
8243
8244         for (i = 0; i < bp->irq_nvecs; i++) {
8245                 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8246                 int (*poll)(struct napi_struct *, int);
8247
8248                 if (i == 0)
8249                         poll = bnx2_poll;
8250                 else
8251                         poll = bnx2_poll_msix;
8252
8253                 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8254                 bnapi->bp = bp;
8255         }
8256 }
8257
8258 static const struct net_device_ops bnx2_netdev_ops = {
8259         .ndo_open               = bnx2_open,
8260         .ndo_start_xmit         = bnx2_start_xmit,
8261         .ndo_stop               = bnx2_close,
8262         .ndo_get_stats          = bnx2_get_stats,
8263         .ndo_set_rx_mode        = bnx2_set_rx_mode,
8264         .ndo_do_ioctl           = bnx2_ioctl,
8265         .ndo_validate_addr      = eth_validate_addr,
8266         .ndo_set_mac_address    = bnx2_change_mac_addr,
8267         .ndo_change_mtu         = bnx2_change_mtu,
8268         .ndo_tx_timeout         = bnx2_tx_timeout,
8269 #ifdef BCM_VLAN
8270         .ndo_vlan_rx_register   = bnx2_vlan_rx_register,
8271 #endif
8272 #ifdef CONFIG_NET_POLL_CONTROLLER
8273         .ndo_poll_controller    = poll_bnx2,
8274 #endif
8275 };
8276
8277 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8278 {
8279 #ifdef BCM_VLAN
8280         dev->vlan_features |= flags;
8281 #endif
8282 }
8283
8284 static int __devinit
8285 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8286 {
8287         static int version_printed = 0;
8288         struct net_device *dev = NULL;
8289         struct bnx2 *bp;
8290         int rc;
8291         char str[40];
8292
8293         if (version_printed++ == 0)
8294                 pr_info("%s", version);
8295
8296         /* dev zeroed in init_etherdev */
8297         dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8298
8299         if (!dev)
8300                 return -ENOMEM;
8301
8302         rc = bnx2_init_board(pdev, dev);
8303         if (rc < 0) {
8304                 free_netdev(dev);
8305                 return rc;
8306         }
8307
8308         dev->netdev_ops = &bnx2_netdev_ops;
8309         dev->watchdog_timeo = TX_TIMEOUT;
8310         dev->ethtool_ops = &bnx2_ethtool_ops;
8311
8312         bp = netdev_priv(dev);
8313
8314         pci_set_drvdata(pdev, dev);
8315
8316         rc = bnx2_request_firmware(bp);
8317         if (rc)
8318                 goto error;
8319
8320         memcpy(dev->dev_addr, bp->mac_addr, 6);
8321         memcpy(dev->perm_addr, bp->mac_addr, 6);
8322
8323         dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
8324         vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8325         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8326                 dev->features |= NETIF_F_IPV6_CSUM;
8327                 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8328         }
8329 #ifdef BCM_VLAN
8330         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8331 #endif
8332         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8333         vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8334         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8335                 dev->features |= NETIF_F_TSO6;
8336                 vlan_features_add(dev, NETIF_F_TSO6);
8337         }
8338         if ((rc = register_netdev(dev))) {
8339                 dev_err(&pdev->dev, "Cannot register net device\n");
8340                 goto error;
8341         }
8342
8343         netdev_info(dev, "%s (%c%d) %s found at mem %lx, IRQ %d, node addr %pM\n",
8344                     board_info[ent->driver_data].name,
8345                     ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8346                     ((CHIP_ID(bp) & 0x0ff0) >> 4),
8347                     bnx2_bus_string(bp, str),
8348                     dev->base_addr,
8349                     bp->pdev->irq, dev->dev_addr);
8350
8351         return 0;
8352
8353 error:
8354         if (bp->mips_firmware)
8355                 release_firmware(bp->mips_firmware);
8356         if (bp->rv2p_firmware)
8357                 release_firmware(bp->rv2p_firmware);
8358
8359         if (bp->regview)
8360                 iounmap(bp->regview);
8361         pci_release_regions(pdev);
8362         pci_disable_device(pdev);
8363         pci_set_drvdata(pdev, NULL);
8364         free_netdev(dev);
8365         return rc;
8366 }
8367
8368 static void __devexit
8369 bnx2_remove_one(struct pci_dev *pdev)
8370 {
8371         struct net_device *dev = pci_get_drvdata(pdev);
8372         struct bnx2 *bp = netdev_priv(dev);
8373
8374         flush_scheduled_work();
8375
8376         unregister_netdev(dev);
8377
8378         if (bp->mips_firmware)
8379                 release_firmware(bp->mips_firmware);
8380         if (bp->rv2p_firmware)
8381                 release_firmware(bp->rv2p_firmware);
8382
8383         if (bp->regview)
8384                 iounmap(bp->regview);
8385
8386         kfree(bp->temp_stats_blk);
8387
8388         free_netdev(dev);
8389         pci_release_regions(pdev);
8390         pci_disable_device(pdev);
8391         pci_set_drvdata(pdev, NULL);
8392 }
8393
8394 static int
8395 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8396 {
8397         struct net_device *dev = pci_get_drvdata(pdev);
8398         struct bnx2 *bp = netdev_priv(dev);
8399
8400         /* PCI register 4 needs to be saved whether netif_running() or not.
8401          * MSI address and data need to be saved if using MSI and
8402          * netif_running().
8403          */
8404         pci_save_state(pdev);
8405         if (!netif_running(dev))
8406                 return 0;
8407
8408         flush_scheduled_work();
8409         bnx2_netif_stop(bp, true);
8410         netif_device_detach(dev);
8411         del_timer_sync(&bp->timer);
8412         bnx2_shutdown_chip(bp);
8413         bnx2_free_skbs(bp);
8414         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8415         return 0;
8416 }
8417
8418 static int
8419 bnx2_resume(struct pci_dev *pdev)
8420 {
8421         struct net_device *dev = pci_get_drvdata(pdev);
8422         struct bnx2 *bp = netdev_priv(dev);
8423
8424         pci_restore_state(pdev);
8425         if (!netif_running(dev))
8426                 return 0;
8427
8428         bnx2_set_power_state(bp, PCI_D0);
8429         netif_device_attach(dev);
8430         bnx2_init_nic(bp, 1);
8431         bnx2_netif_start(bp, true);
8432         return 0;
8433 }
8434
8435 /**
8436  * bnx2_io_error_detected - called when PCI error is detected
8437  * @pdev: Pointer to PCI device
8438  * @state: The current pci connection state
8439  *
8440  * This function is called after a PCI bus error affecting
8441  * this device has been detected.
8442  */
8443 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8444                                                pci_channel_state_t state)
8445 {
8446         struct net_device *dev = pci_get_drvdata(pdev);
8447         struct bnx2 *bp = netdev_priv(dev);
8448
8449         rtnl_lock();
8450         netif_device_detach(dev);
8451
8452         if (state == pci_channel_io_perm_failure) {
8453                 rtnl_unlock();
8454                 return PCI_ERS_RESULT_DISCONNECT;
8455         }
8456
8457         if (netif_running(dev)) {
8458                 bnx2_netif_stop(bp, true);
8459                 del_timer_sync(&bp->timer);
8460                 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8461         }
8462
8463         pci_disable_device(pdev);
8464         rtnl_unlock();
8465
8466         /* Request a slot slot reset. */
8467         return PCI_ERS_RESULT_NEED_RESET;
8468 }
8469
8470 /**
8471  * bnx2_io_slot_reset - called after the pci bus has been reset.
8472  * @pdev: Pointer to PCI device
8473  *
8474  * Restart the card from scratch, as if from a cold-boot.
8475  */
8476 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8477 {
8478         struct net_device *dev = pci_get_drvdata(pdev);
8479         struct bnx2 *bp = netdev_priv(dev);
8480
8481         rtnl_lock();
8482         if (pci_enable_device(pdev)) {
8483                 dev_err(&pdev->dev,
8484                         "Cannot re-enable PCI device after reset\n");
8485                 rtnl_unlock();
8486                 return PCI_ERS_RESULT_DISCONNECT;
8487         }
8488         pci_set_master(pdev);
8489         pci_restore_state(pdev);
8490         pci_save_state(pdev);
8491
8492         if (netif_running(dev)) {
8493                 bnx2_set_power_state(bp, PCI_D0);
8494                 bnx2_init_nic(bp, 1);
8495         }
8496
8497         rtnl_unlock();
8498         return PCI_ERS_RESULT_RECOVERED;
8499 }
8500
8501 /**
8502  * bnx2_io_resume - called when traffic can start flowing again.
8503  * @pdev: Pointer to PCI device
8504  *
8505  * This callback is called when the error recovery driver tells us that
8506  * its OK to resume normal operation.
8507  */
8508 static void bnx2_io_resume(struct pci_dev *pdev)
8509 {
8510         struct net_device *dev = pci_get_drvdata(pdev);
8511         struct bnx2 *bp = netdev_priv(dev);
8512
8513         rtnl_lock();
8514         if (netif_running(dev))
8515                 bnx2_netif_start(bp, true);
8516
8517         netif_device_attach(dev);
8518         rtnl_unlock();
8519 }
8520
8521 static struct pci_error_handlers bnx2_err_handler = {
8522         .error_detected = bnx2_io_error_detected,
8523         .slot_reset     = bnx2_io_slot_reset,
8524         .resume         = bnx2_io_resume,
8525 };
8526
8527 static struct pci_driver bnx2_pci_driver = {
8528         .name           = DRV_MODULE_NAME,
8529         .id_table       = bnx2_pci_tbl,
8530         .probe          = bnx2_init_one,
8531         .remove         = __devexit_p(bnx2_remove_one),
8532         .suspend        = bnx2_suspend,
8533         .resume         = bnx2_resume,
8534         .err_handler    = &bnx2_err_handler,
8535 };
8536
8537 static int __init bnx2_init(void)
8538 {
8539         return pci_register_driver(&bnx2_pci_driver);
8540 }
8541
8542 static void __exit bnx2_cleanup(void)
8543 {
8544         pci_unregister_driver(&bnx2_pci_driver);
8545 }
8546
8547 module_init(bnx2_init);
8548 module_exit(bnx2_cleanup);
8549
8550
8551