2 * Linux network driver for Brocade Converged Network Adapter.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
22 static void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status);
25 bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
31 port->llport.link_status = BNA_LINK_UP;
33 port->llport.link_status = BNA_CEE_UP;
35 /* Compute the priority */
36 prio_map = aen->prio_map;
38 for (i = 0; i < 8; i++) {
39 if ((prio_map >> i) & 0x1)
47 bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup);
48 bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority);
49 port->link_cbfn(port->bna->bnad, port->llport.link_status);
53 bna_port_cb_link_down(struct bna_port *port, int status)
55 port->llport.link_status = BNA_LINK_DOWN;
58 bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN);
59 port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
68 return msg_id == BFI_LL_I2H_LINK_DOWN_AEN ||
69 msg_id == BFI_LL_I2H_LINK_UP_AEN;
73 bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
75 struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg);
77 switch (aen->mh.msg_id) {
78 case BFI_LL_I2H_LINK_UP_AEN:
79 bna_port_cb_link_up(&bna->port, aen, aen->reason);
81 case BFI_LL_I2H_LINK_DOWN_AEN:
82 bna_port_cb_link_down(&bna->port, aen->reason);
90 bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
92 struct bna *bna = (struct bna *)(llarg);
93 struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg);
94 struct bfi_mhdr *cmd_h, *rsp_h;
95 struct bna_mbox_qe *mb_qe = NULL;
98 char message[BNA_MESSAGE_SIZE];
100 aen = bna_is_aen(mb_rsp->mh.msg_id);
103 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
104 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
105 rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh);
107 if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) &&
108 (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) {
109 /* Remove the request from posted_q, update state */
110 list_del(&mb_qe->qe);
111 bna->mbox_mod.msg_pending--;
112 if (list_empty(&bna->mbox_mod.posted_q))
113 bna->mbox_mod.state = BNA_MBOX_FREE;
117 /* Dispatch the cbfn */
119 mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error);
121 /* Post the next entry, if needed */
123 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
124 bfa_nw_ioc_mbox_queue(&bna->device.ioc,
128 snprintf(message, BNA_MESSAGE_SIZE,
129 "No matching rsp for [%d:%d:%d]\n",
130 mb_rsp->mh.msg_class, mb_rsp->mh.msg_id,
131 mb_rsp->mh.mtag.i2htok);
132 pr_info("%s", message);
136 bna_mbox_aen_callback(bna, msg);
140 bna_err_handler(struct bna *bna, u32 intr_status)
144 if (intr_status & __HALT_STATUS_BITS) {
145 init_halt = readl(bna->device.ioc.ioc_regs.ll_halt);
146 init_halt &= ~__FW_INIT_HALT_P;
147 writel(init_halt, bna->device.ioc.ioc_regs.ll_halt);
150 bfa_nw_ioc_error_isr(&bna->device.ioc);
154 bna_mbox_handler(struct bna *bna, u32 intr_status)
156 if (BNA_IS_ERR_INTR(intr_status)) {
157 bna_err_handler(bna, intr_status);
160 if (BNA_IS_MBOX_INTR(intr_status))
161 bfa_nw_ioc_mbox_isr(&bna->device.ioc);
165 bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe)
169 mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]);
171 mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr);
172 bna->mbox_mod.msg_ctr++;
173 bna->mbox_mod.msg_pending++;
174 if (bna->mbox_mod.state == BNA_MBOX_FREE) {
175 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
176 bfa_nw_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd);
177 bna->mbox_mod.state = BNA_MBOX_POSTED;
179 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
184 bna_mbox_flush_q(struct bna *bna, struct list_head *q)
186 struct bna_mbox_qe *mb_qe = NULL;
187 struct bfi_mhdr *cmd_h;
188 struct list_head *mb_q;
189 void (*cbfn)(void *arg, int status);
192 mb_q = &bna->mbox_mod.posted_q;
194 while (!list_empty(mb_q)) {
195 bfa_q_deq(mb_q, &mb_qe);
197 cbarg = mb_qe->cbarg;
198 bfa_q_qe_init(mb_qe);
199 bna->mbox_mod.msg_pending--;
201 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
203 cbfn(cbarg, BNA_CB_NOT_EXEC);
206 bna->mbox_mod.state = BNA_MBOX_FREE;
210 bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod)
215 bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod)
217 bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q);
221 bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna)
223 bfa_nw_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna);
224 mbox_mod->state = BNA_MBOX_FREE;
225 mbox_mod->msg_ctr = mbox_mod->msg_pending = 0;
226 INIT_LIST_HEAD(&mbox_mod->posted_q);
231 bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod)
233 mbox_mod->bna = NULL;
239 #define call_llport_stop_cbfn(llport, status)\
241 if ((llport)->stop_cbfn)\
242 (llport)->stop_cbfn(&(llport)->bna->port, status);\
243 (llport)->stop_cbfn = NULL;\
246 static void bna_fw_llport_up(struct bna_llport *llport);
247 static void bna_fw_cb_llport_up(void *arg, int status);
248 static void bna_fw_llport_down(struct bna_llport *llport);
249 static void bna_fw_cb_llport_down(void *arg, int status);
250 static void bna_llport_start(struct bna_llport *llport);
251 static void bna_llport_stop(struct bna_llport *llport);
252 static void bna_llport_fail(struct bna_llport *llport);
254 enum bna_llport_event {
260 LLPORT_E_FWRESP_UP = 6,
261 LLPORT_E_FWRESP_DOWN = 7
264 enum bna_llport_state {
265 BNA_LLPORT_STOPPED = 1,
267 BNA_LLPORT_UP_RESP_WAIT = 3,
268 BNA_LLPORT_DOWN_RESP_WAIT = 4,
270 BNA_LLPORT_LAST_RESP_WAIT = 6
273 bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport,
274 enum bna_llport_event);
275 bfa_fsm_state_decl(bna_llport, down, struct bna_llport,
276 enum bna_llport_event);
277 bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport,
278 enum bna_llport_event);
279 bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport,
280 enum bna_llport_event);
281 bfa_fsm_state_decl(bna_llport, up, struct bna_llport,
282 enum bna_llport_event);
283 bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport,
284 enum bna_llport_event);
286 static struct bfa_sm_table llport_sm_table[] = {
287 {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED},
288 {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN},
289 {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT},
290 {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT},
291 {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP},
292 {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT}
296 bna_llport_sm_stopped_entry(struct bna_llport *llport)
298 llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN);
299 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
303 bna_llport_sm_stopped(struct bna_llport *llport,
304 enum bna_llport_event event)
308 bfa_fsm_set_state(llport, bna_llport_sm_down);
312 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
319 /* This event is received due to Rx objects failing */
323 case LLPORT_E_FWRESP_UP:
324 case LLPORT_E_FWRESP_DOWN:
326 * These events are received due to flushing of mbox when
333 bfa_sm_fault(llport->bna, event);
338 bna_llport_sm_down_entry(struct bna_llport *llport)
340 bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN);
344 bna_llport_sm_down(struct bna_llport *llport,
345 enum bna_llport_event event)
349 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
353 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
357 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
358 bna_fw_llport_up(llport);
362 bfa_sm_fault(llport->bna, event);
367 bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
370 * NOTE: Do not call bna_fw_llport_up() here. That will over step
371 * mbox due to down_resp_wait -> up_resp_wait transition on event
377 bna_llport_sm_up_resp_wait(struct bna_llport *llport,
378 enum bna_llport_event event)
382 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
386 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
390 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
393 case LLPORT_E_FWRESP_UP:
394 bfa_fsm_set_state(llport, bna_llport_sm_up);
397 case LLPORT_E_FWRESP_DOWN:
398 /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
399 bna_fw_llport_up(llport);
403 bfa_sm_fault(llport->bna, event);
408 bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport)
411 * NOTE: Do not call bna_fw_llport_down() here. That will over step
412 * mbox due to up_resp_wait -> down_resp_wait transition on event
418 bna_llport_sm_down_resp_wait(struct bna_llport *llport,
419 enum bna_llport_event event)
423 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
427 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
431 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
434 case LLPORT_E_FWRESP_UP:
435 /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
436 bna_fw_llport_down(llport);
439 case LLPORT_E_FWRESP_DOWN:
440 bfa_fsm_set_state(llport, bna_llport_sm_down);
444 bfa_sm_fault(llport->bna, event);
449 bna_llport_sm_up_entry(struct bna_llport *llport)
454 bna_llport_sm_up(struct bna_llport *llport,
455 enum bna_llport_event event)
459 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
460 bna_fw_llport_down(llport);
464 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
468 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
469 bna_fw_llport_down(llport);
473 bfa_sm_fault(llport->bna, event);
478 bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport)
483 bna_llport_sm_last_resp_wait(struct bna_llport *llport,
484 enum bna_llport_event event)
488 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
493 * This event is received due to Rx objects stopping in
499 case LLPORT_E_FWRESP_UP:
500 /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
501 bna_fw_llport_down(llport);
504 case LLPORT_E_FWRESP_DOWN:
505 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
509 bfa_sm_fault(llport->bna, event);
514 bna_fw_llport_admin_up(struct bna_llport *llport)
516 struct bfi_ll_port_admin_req ll_req;
518 memset(&ll_req, 0, sizeof(ll_req));
519 ll_req.mh.msg_class = BFI_MC_LL;
520 ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
521 ll_req.mh.mtag.h2i.lpu_id = 0;
523 ll_req.up = BNA_STATUS_T_ENABLED;
525 bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
526 bna_fw_cb_llport_up, llport);
528 bna_mbox_send(llport->bna, &llport->mbox_qe);
532 bna_fw_llport_up(struct bna_llport *llport)
534 if (llport->type == BNA_PORT_T_REGULAR)
535 bna_fw_llport_admin_up(llport);
539 bna_fw_cb_llport_up(void *arg, int status)
541 struct bna_llport *llport = (struct bna_llport *)arg;
543 bfa_q_qe_init(&llport->mbox_qe.qe);
544 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP);
548 bna_fw_llport_admin_down(struct bna_llport *llport)
550 struct bfi_ll_port_admin_req ll_req;
552 memset(&ll_req, 0, sizeof(ll_req));
553 ll_req.mh.msg_class = BFI_MC_LL;
554 ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
555 ll_req.mh.mtag.h2i.lpu_id = 0;
557 ll_req.up = BNA_STATUS_T_DISABLED;
559 bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
560 bna_fw_cb_llport_down, llport);
562 bna_mbox_send(llport->bna, &llport->mbox_qe);
566 bna_fw_llport_down(struct bna_llport *llport)
568 if (llport->type == BNA_PORT_T_REGULAR)
569 bna_fw_llport_admin_down(llport);
573 bna_fw_cb_llport_down(void *arg, int status)
575 struct bna_llport *llport = (struct bna_llport *)arg;
577 bfa_q_qe_init(&llport->mbox_qe.qe);
578 bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN);
582 bna_port_cb_llport_stopped(struct bna_port *port,
583 enum bna_cb_status status)
585 bfa_wc_down(&port->chld_stop_wc);
589 bna_llport_init(struct bna_llport *llport, struct bna *bna)
591 llport->flags |= BNA_LLPORT_F_ENABLED;
592 llport->type = BNA_PORT_T_REGULAR;
595 llport->link_status = BNA_LINK_DOWN;
597 llport->admin_up_count = 0;
599 llport->stop_cbfn = NULL;
601 bfa_q_qe_init(&llport->mbox_qe.qe);
603 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
607 bna_llport_uninit(struct bna_llport *llport)
609 llport->flags &= ~BNA_LLPORT_F_ENABLED;
615 bna_llport_start(struct bna_llport *llport)
617 bfa_fsm_send_event(llport, LLPORT_E_START);
621 bna_llport_stop(struct bna_llport *llport)
623 llport->stop_cbfn = bna_port_cb_llport_stopped;
625 bfa_fsm_send_event(llport, LLPORT_E_STOP);
629 bna_llport_fail(struct bna_llport *llport)
631 bfa_fsm_send_event(llport, LLPORT_E_FAIL);
635 bna_llport_state_get(struct bna_llport *llport)
637 return bfa_sm_to_state(llport_sm_table, llport->fsm);
641 bna_llport_admin_up(struct bna_llport *llport)
643 llport->admin_up_count++;
645 if (llport->admin_up_count == 1) {
646 llport->flags |= BNA_LLPORT_F_RX_ENABLED;
647 if (llport->flags & BNA_LLPORT_F_ENABLED)
648 bfa_fsm_send_event(llport, LLPORT_E_UP);
653 bna_llport_admin_down(struct bna_llport *llport)
655 llport->admin_up_count--;
657 if (llport->admin_up_count == 0) {
658 llport->flags &= ~BNA_LLPORT_F_RX_ENABLED;
659 if (llport->flags & BNA_LLPORT_F_ENABLED)
660 bfa_fsm_send_event(llport, LLPORT_E_DOWN);
667 #define bna_port_chld_start(port)\
669 enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
670 BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
671 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
672 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
673 bna_llport_start(&(port)->llport);\
674 bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\
675 bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
678 #define bna_port_chld_stop(port)\
680 enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
681 BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
682 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
683 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
684 bfa_wc_up(&(port)->chld_stop_wc);\
685 bfa_wc_up(&(port)->chld_stop_wc);\
686 bfa_wc_up(&(port)->chld_stop_wc);\
687 bna_llport_stop(&(port)->llport);\
688 bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\
689 bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
692 #define bna_port_chld_fail(port)\
694 bna_llport_fail(&(port)->llport);\
695 bna_tx_mod_fail(&(port)->bna->tx_mod);\
696 bna_rx_mod_fail(&(port)->bna->rx_mod);\
699 #define bna_port_rx_start(port)\
701 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
702 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
703 bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
706 #define bna_port_rx_stop(port)\
708 enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
709 BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
710 bfa_wc_up(&(port)->chld_stop_wc);\
711 bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
714 #define call_port_stop_cbfn(port, status)\
716 if ((port)->stop_cbfn)\
717 (port)->stop_cbfn((port)->stop_cbarg, status);\
718 (port)->stop_cbfn = NULL;\
719 (port)->stop_cbarg = NULL;\
722 #define call_port_pause_cbfn(port, status)\
724 if ((port)->pause_cbfn)\
725 (port)->pause_cbfn((port)->bna->bnad, status);\
726 (port)->pause_cbfn = NULL;\
729 #define call_port_mtu_cbfn(port, status)\
731 if ((port)->mtu_cbfn)\
732 (port)->mtu_cbfn((port)->bna->bnad, status);\
733 (port)->mtu_cbfn = NULL;\
736 static void bna_fw_pause_set(struct bna_port *port);
737 static void bna_fw_cb_pause_set(void *arg, int status);
738 static void bna_fw_mtu_set(struct bna_port *port);
739 static void bna_fw_cb_mtu_set(void *arg, int status);
741 enum bna_port_event {
745 PORT_E_PAUSE_CFG = 4,
747 PORT_E_CHLD_STOPPED = 6,
748 PORT_E_FWRESP_PAUSE = 7,
749 PORT_E_FWRESP_MTU = 8
752 enum bna_port_state {
753 BNA_PORT_STOPPED = 1,
754 BNA_PORT_MTU_INIT_WAIT = 2,
755 BNA_PORT_PAUSE_INIT_WAIT = 3,
756 BNA_PORT_LAST_RESP_WAIT = 4,
757 BNA_PORT_STARTED = 5,
758 BNA_PORT_PAUSE_CFG_WAIT = 6,
759 BNA_PORT_RX_STOP_WAIT = 7,
760 BNA_PORT_MTU_CFG_WAIT = 8,
761 BNA_PORT_CHLD_STOP_WAIT = 9
764 bfa_fsm_state_decl(bna_port, stopped, struct bna_port,
765 enum bna_port_event);
766 bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port,
767 enum bna_port_event);
768 bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port,
769 enum bna_port_event);
770 bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port,
771 enum bna_port_event);
772 bfa_fsm_state_decl(bna_port, started, struct bna_port,
773 enum bna_port_event);
774 bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port,
775 enum bna_port_event);
776 bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port,
777 enum bna_port_event);
778 bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port,
779 enum bna_port_event);
780 bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port,
781 enum bna_port_event);
783 static struct bfa_sm_table port_sm_table[] = {
784 {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED},
785 {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT},
786 {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT},
787 {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT},
788 {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED},
789 {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT},
790 {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT},
791 {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT},
792 {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT}
796 bna_port_sm_stopped_entry(struct bna_port *port)
798 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
799 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
800 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
804 bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event)
808 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
812 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
819 case PORT_E_PAUSE_CFG:
820 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
824 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
827 case PORT_E_CHLD_STOPPED:
829 * This event is received due to LLPort, Tx and Rx objects
835 case PORT_E_FWRESP_PAUSE:
836 case PORT_E_FWRESP_MTU:
838 * These events are received due to flushing of mbox when
845 bfa_sm_fault(port->bna, event);
850 bna_port_sm_mtu_init_wait_entry(struct bna_port *port)
852 bna_fw_mtu_set(port);
856 bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event)
860 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
864 bfa_fsm_set_state(port, bna_port_sm_stopped);
867 case PORT_E_PAUSE_CFG:
872 port->flags |= BNA_PORT_F_MTU_CHANGED;
875 case PORT_E_FWRESP_MTU:
876 if (port->flags & BNA_PORT_F_MTU_CHANGED) {
877 port->flags &= ~BNA_PORT_F_MTU_CHANGED;
878 bna_fw_mtu_set(port);
880 bfa_fsm_set_state(port, bna_port_sm_pause_init_wait);
885 bfa_sm_fault(port->bna, event);
890 bna_port_sm_pause_init_wait_entry(struct bna_port *port)
892 bna_fw_pause_set(port);
896 bna_port_sm_pause_init_wait(struct bna_port *port,
897 enum bna_port_event event)
901 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
905 bfa_fsm_set_state(port, bna_port_sm_stopped);
908 case PORT_E_PAUSE_CFG:
909 port->flags |= BNA_PORT_F_PAUSE_CHANGED;
913 port->flags |= BNA_PORT_F_MTU_CHANGED;
916 case PORT_E_FWRESP_PAUSE:
917 if (port->flags & BNA_PORT_F_PAUSE_CHANGED) {
918 port->flags &= ~BNA_PORT_F_PAUSE_CHANGED;
919 bna_fw_pause_set(port);
920 } else if (port->flags & BNA_PORT_F_MTU_CHANGED) {
921 port->flags &= ~BNA_PORT_F_MTU_CHANGED;
922 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
924 bfa_fsm_set_state(port, bna_port_sm_started);
925 bna_port_chld_start(port);
930 bfa_sm_fault(port->bna, event);
935 bna_port_sm_last_resp_wait_entry(struct bna_port *port)
940 bna_port_sm_last_resp_wait(struct bna_port *port,
941 enum bna_port_event event)
945 case PORT_E_FWRESP_PAUSE:
946 case PORT_E_FWRESP_MTU:
947 bfa_fsm_set_state(port, bna_port_sm_stopped);
951 bfa_sm_fault(port->bna, event);
956 bna_port_sm_started_entry(struct bna_port *port)
959 * NOTE: Do not call bna_port_chld_start() here, since it will be
960 * inadvertently called during pause_cfg_wait->started transition
963 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
964 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
968 bna_port_sm_started(struct bna_port *port,
969 enum bna_port_event event)
973 bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait);
977 bfa_fsm_set_state(port, bna_port_sm_stopped);
978 bna_port_chld_fail(port);
981 case PORT_E_PAUSE_CFG:
982 bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait);
986 bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait);
990 bfa_sm_fault(port->bna, event);
995 bna_port_sm_pause_cfg_wait_entry(struct bna_port *port)
997 bna_fw_pause_set(port);
1001 bna_port_sm_pause_cfg_wait(struct bna_port *port,
1002 enum bna_port_event event)
1006 bfa_fsm_set_state(port, bna_port_sm_stopped);
1007 bna_port_chld_fail(port);
1010 case PORT_E_FWRESP_PAUSE:
1011 bfa_fsm_set_state(port, bna_port_sm_started);
1015 bfa_sm_fault(port->bna, event);
1020 bna_port_sm_rx_stop_wait_entry(struct bna_port *port)
1022 bna_port_rx_stop(port);
1026 bna_port_sm_rx_stop_wait(struct bna_port *port,
1027 enum bna_port_event event)
1031 bfa_fsm_set_state(port, bna_port_sm_stopped);
1032 bna_port_chld_fail(port);
1035 case PORT_E_CHLD_STOPPED:
1036 bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait);
1040 bfa_sm_fault(port->bna, event);
1045 bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port)
1047 bna_fw_mtu_set(port);
1051 bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event)
1055 bfa_fsm_set_state(port, bna_port_sm_stopped);
1056 bna_port_chld_fail(port);
1059 case PORT_E_FWRESP_MTU:
1060 bfa_fsm_set_state(port, bna_port_sm_started);
1061 bna_port_rx_start(port);
1065 bfa_sm_fault(port->bna, event);
1070 bna_port_sm_chld_stop_wait_entry(struct bna_port *port)
1072 bna_port_chld_stop(port);
1076 bna_port_sm_chld_stop_wait(struct bna_port *port,
1077 enum bna_port_event event)
1081 bfa_fsm_set_state(port, bna_port_sm_stopped);
1082 bna_port_chld_fail(port);
1085 case PORT_E_CHLD_STOPPED:
1086 bfa_fsm_set_state(port, bna_port_sm_stopped);
1090 bfa_sm_fault(port->bna, event);
1095 bna_fw_pause_set(struct bna_port *port)
1097 struct bfi_ll_set_pause_req ll_req;
1099 memset(&ll_req, 0, sizeof(ll_req));
1100 ll_req.mh.msg_class = BFI_MC_LL;
1101 ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ;
1102 ll_req.mh.mtag.h2i.lpu_id = 0;
1104 ll_req.tx_pause = port->pause_config.tx_pause;
1105 ll_req.rx_pause = port->pause_config.rx_pause;
1107 bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1108 bna_fw_cb_pause_set, port);
1110 bna_mbox_send(port->bna, &port->mbox_qe);
1114 bna_fw_cb_pause_set(void *arg, int status)
1116 struct bna_port *port = (struct bna_port *)arg;
1118 bfa_q_qe_init(&port->mbox_qe.qe);
1119 bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE);
1123 bna_fw_mtu_set(struct bna_port *port)
1125 struct bfi_ll_mtu_info_req ll_req;
1127 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
1128 ll_req.mtu = htons((u16)port->mtu);
1130 bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1131 bna_fw_cb_mtu_set, port);
1132 bna_mbox_send(port->bna, &port->mbox_qe);
1136 bna_fw_cb_mtu_set(void *arg, int status)
1138 struct bna_port *port = (struct bna_port *)arg;
1140 bfa_q_qe_init(&port->mbox_qe.qe);
1141 bfa_fsm_send_event(port, PORT_E_FWRESP_MTU);
1145 bna_port_cb_chld_stopped(void *arg)
1147 struct bna_port *port = (struct bna_port *)arg;
1149 bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED);
1153 bna_port_init(struct bna_port *port, struct bna *bna)
1158 port->type = BNA_PORT_T_REGULAR;
1160 port->link_cbfn = bnad_cb_port_link_status;
1162 port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped;
1163 port->chld_stop_wc.wc_cbarg = port;
1164 port->chld_stop_wc.wc_count = 0;
1166 port->stop_cbfn = NULL;
1167 port->stop_cbarg = NULL;
1169 port->pause_cbfn = NULL;
1171 port->mtu_cbfn = NULL;
1173 bfa_q_qe_init(&port->mbox_qe.qe);
1175 bfa_fsm_set_state(port, bna_port_sm_stopped);
1177 bna_llport_init(&port->llport, bna);
1181 bna_port_uninit(struct bna_port *port)
1183 bna_llport_uninit(&port->llport);
1191 bna_port_state_get(struct bna_port *port)
1193 return bfa_sm_to_state(port_sm_table, port->fsm);
1197 bna_port_start(struct bna_port *port)
1199 port->flags |= BNA_PORT_F_DEVICE_READY;
1200 if (port->flags & BNA_PORT_F_ENABLED)
1201 bfa_fsm_send_event(port, PORT_E_START);
1205 bna_port_stop(struct bna_port *port)
1207 port->stop_cbfn = bna_device_cb_port_stopped;
1208 port->stop_cbarg = &port->bna->device;
1210 port->flags &= ~BNA_PORT_F_DEVICE_READY;
1211 bfa_fsm_send_event(port, PORT_E_STOP);
1215 bna_port_fail(struct bna_port *port)
1217 port->flags &= ~BNA_PORT_F_DEVICE_READY;
1218 bfa_fsm_send_event(port, PORT_E_FAIL);
1222 bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status)
1224 bfa_wc_down(&port->chld_stop_wc);
1228 bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status)
1230 bfa_wc_down(&port->chld_stop_wc);
1234 bna_port_mtu_get(struct bna_port *port)
1240 bna_port_enable(struct bna_port *port)
1242 if (port->fsm != (bfa_sm_t)bna_port_sm_stopped)
1245 port->flags |= BNA_PORT_F_ENABLED;
1247 if (port->flags & BNA_PORT_F_DEVICE_READY)
1248 bfa_fsm_send_event(port, PORT_E_START);
1252 bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
1253 void (*cbfn)(void *, enum bna_cb_status))
1255 if (type == BNA_SOFT_CLEANUP) {
1256 (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS);
1260 port->stop_cbfn = cbfn;
1261 port->stop_cbarg = port->bna->bnad;
1263 port->flags &= ~BNA_PORT_F_ENABLED;
1265 bfa_fsm_send_event(port, PORT_E_STOP);
1269 bna_port_pause_config(struct bna_port *port,
1270 struct bna_pause_config *pause_config,
1271 void (*cbfn)(struct bnad *, enum bna_cb_status))
1273 port->pause_config = *pause_config;
1275 port->pause_cbfn = cbfn;
1277 bfa_fsm_send_event(port, PORT_E_PAUSE_CFG);
1281 bna_port_mtu_set(struct bna_port *port, int mtu,
1282 void (*cbfn)(struct bnad *, enum bna_cb_status))
1286 port->mtu_cbfn = cbfn;
1288 bfa_fsm_send_event(port, PORT_E_MTU_CFG);
1292 bna_port_mac_get(struct bna_port *port, mac_t *mac)
1294 *mac = bfa_nw_ioc_get_mac(&port->bna->device.ioc);
1300 #define enable_mbox_intr(_device)\
1303 bna_intr_status_get((_device)->bna, intr_status);\
1304 bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\
1305 bna_mbox_intr_enable((_device)->bna);\
1308 #define disable_mbox_intr(_device)\
1310 bna_mbox_intr_disable((_device)->bna);\
1311 bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\
1314 static const struct bna_chip_regs_offset reg_offset[] =
1315 {{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
1316 HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
1317 {HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
1318 HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
1319 {HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
1320 HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
1321 {HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
1322 HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
1325 enum bna_device_event {
1326 DEVICE_E_ENABLE = 1,
1327 DEVICE_E_DISABLE = 2,
1328 DEVICE_E_IOC_READY = 3,
1329 DEVICE_E_IOC_FAILED = 4,
1330 DEVICE_E_IOC_DISABLED = 5,
1331 DEVICE_E_IOC_RESET = 6,
1332 DEVICE_E_PORT_STOPPED = 7,
1335 enum bna_device_state {
1336 BNA_DEVICE_STOPPED = 1,
1337 BNA_DEVICE_IOC_READY_WAIT = 2,
1338 BNA_DEVICE_READY = 3,
1339 BNA_DEVICE_PORT_STOP_WAIT = 4,
1340 BNA_DEVICE_IOC_DISABLE_WAIT = 5,
1341 BNA_DEVICE_FAILED = 6
1344 bfa_fsm_state_decl(bna_device, stopped, struct bna_device,
1345 enum bna_device_event);
1346 bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device,
1347 enum bna_device_event);
1348 bfa_fsm_state_decl(bna_device, ready, struct bna_device,
1349 enum bna_device_event);
1350 bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device,
1351 enum bna_device_event);
1352 bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device,
1353 enum bna_device_event);
1354 bfa_fsm_state_decl(bna_device, failed, struct bna_device,
1355 enum bna_device_event);
1357 static struct bfa_sm_table device_sm_table[] = {
1358 {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED},
1359 {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT},
1360 {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY},
1361 {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT},
1362 {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT},
1363 {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED},
1367 bna_device_sm_stopped_entry(struct bna_device *device)
1369 if (device->stop_cbfn)
1370 device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS);
1372 device->stop_cbfn = NULL;
1373 device->stop_cbarg = NULL;
1377 bna_device_sm_stopped(struct bna_device *device,
1378 enum bna_device_event event)
1381 case DEVICE_E_ENABLE:
1382 if (device->intr_type == BNA_INTR_T_MSIX)
1383 bna_mbox_msix_idx_set(device);
1384 bfa_nw_ioc_enable(&device->ioc);
1385 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1388 case DEVICE_E_DISABLE:
1389 bfa_fsm_set_state(device, bna_device_sm_stopped);
1392 case DEVICE_E_IOC_RESET:
1393 enable_mbox_intr(device);
1396 case DEVICE_E_IOC_FAILED:
1397 bfa_fsm_set_state(device, bna_device_sm_failed);
1401 bfa_sm_fault(device->bna, event);
1406 bna_device_sm_ioc_ready_wait_entry(struct bna_device *device)
1409 * Do not call bfa_ioc_enable() here. It must be called in the
1410 * previous state due to failed -> ioc_ready_wait transition.
1415 bna_device_sm_ioc_ready_wait(struct bna_device *device,
1416 enum bna_device_event event)
1419 case DEVICE_E_DISABLE:
1420 if (device->ready_cbfn)
1421 device->ready_cbfn(device->ready_cbarg,
1423 device->ready_cbfn = NULL;
1424 device->ready_cbarg = NULL;
1425 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1428 case DEVICE_E_IOC_READY:
1429 bfa_fsm_set_state(device, bna_device_sm_ready);
1432 case DEVICE_E_IOC_FAILED:
1433 bfa_fsm_set_state(device, bna_device_sm_failed);
1436 case DEVICE_E_IOC_RESET:
1437 enable_mbox_intr(device);
1441 bfa_sm_fault(device->bna, event);
1446 bna_device_sm_ready_entry(struct bna_device *device)
1448 bna_mbox_mod_start(&device->bna->mbox_mod);
1449 bna_port_start(&device->bna->port);
1451 if (device->ready_cbfn)
1452 device->ready_cbfn(device->ready_cbarg,
1454 device->ready_cbfn = NULL;
1455 device->ready_cbarg = NULL;
1459 bna_device_sm_ready(struct bna_device *device, enum bna_device_event event)
1462 case DEVICE_E_DISABLE:
1463 bfa_fsm_set_state(device, bna_device_sm_port_stop_wait);
1466 case DEVICE_E_IOC_FAILED:
1467 bfa_fsm_set_state(device, bna_device_sm_failed);
1471 bfa_sm_fault(device->bna, event);
1476 bna_device_sm_port_stop_wait_entry(struct bna_device *device)
1478 bna_port_stop(&device->bna->port);
1482 bna_device_sm_port_stop_wait(struct bna_device *device,
1483 enum bna_device_event event)
1486 case DEVICE_E_PORT_STOPPED:
1487 bna_mbox_mod_stop(&device->bna->mbox_mod);
1488 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1491 case DEVICE_E_IOC_FAILED:
1492 disable_mbox_intr(device);
1493 bna_port_fail(&device->bna->port);
1497 bfa_sm_fault(device->bna, event);
1502 bna_device_sm_ioc_disable_wait_entry(struct bna_device *device)
1504 bfa_nw_ioc_disable(&device->ioc);
1508 bna_device_sm_ioc_disable_wait(struct bna_device *device,
1509 enum bna_device_event event)
1512 case DEVICE_E_IOC_DISABLED:
1513 disable_mbox_intr(device);
1514 bfa_fsm_set_state(device, bna_device_sm_stopped);
1518 bfa_sm_fault(device->bna, event);
1523 bna_device_sm_failed_entry(struct bna_device *device)
1525 disable_mbox_intr(device);
1526 bna_port_fail(&device->bna->port);
1527 bna_mbox_mod_stop(&device->bna->mbox_mod);
1529 if (device->ready_cbfn)
1530 device->ready_cbfn(device->ready_cbarg,
1532 device->ready_cbfn = NULL;
1533 device->ready_cbarg = NULL;
1537 bna_device_sm_failed(struct bna_device *device,
1538 enum bna_device_event event)
1541 case DEVICE_E_DISABLE:
1542 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1545 case DEVICE_E_IOC_RESET:
1546 enable_mbox_intr(device);
1547 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1551 bfa_sm_fault(device->bna, event);
1555 /* IOC callback functions */
1558 bna_device_cb_iocll_ready(void *dev, enum bfa_status error)
1560 struct bna_device *device = (struct bna_device *)dev;
1563 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1565 bfa_fsm_send_event(device, DEVICE_E_IOC_READY);
1569 bna_device_cb_iocll_disabled(void *dev)
1571 struct bna_device *device = (struct bna_device *)dev;
1573 bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED);
1577 bna_device_cb_iocll_failed(void *dev)
1579 struct bna_device *device = (struct bna_device *)dev;
1581 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1585 bna_device_cb_iocll_reset(void *dev)
1587 struct bna_device *device = (struct bna_device *)dev;
1589 bfa_fsm_send_event(device, DEVICE_E_IOC_RESET);
1592 static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
1593 bna_device_cb_iocll_ready,
1594 bna_device_cb_iocll_disabled,
1595 bna_device_cb_iocll_failed,
1596 bna_device_cb_iocll_reset
1601 bna_adv_device_init(struct bna_device *device, struct bna *bna,
1602 struct bna_res_info *res_info)
1609 kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva;
1612 * Attach common modules (Diag, SFP, CEE, Port) and claim respective
1616 &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma);
1617 kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva;
1619 bfa_nw_cee_attach(&bna->cee, &device->ioc, bna);
1620 bfa_nw_cee_mem_claim(&bna->cee, kva, dma);
1621 kva += bfa_nw_cee_meminfo();
1622 dma += bfa_nw_cee_meminfo();
1627 bna_device_init(struct bna_device *device, struct bna *bna,
1628 struct bna_res_info *res_info)
1635 * Attach IOC and claim:
1636 * 1. DMA memory for IOC attributes
1637 * 2. Kernel memory for FW trace
1639 bfa_nw_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn);
1640 bfa_nw_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL);
1643 &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma);
1644 bfa_nw_ioc_mem_claim(&device->ioc,
1645 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva,
1648 bna_adv_device_init(device, bna, res_info);
1650 * Initialize mbox_mod only after IOC, so that mbox handler
1651 * registration goes through
1654 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type;
1656 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector;
1657 bna_mbox_mod_init(&bna->mbox_mod, bna);
1659 device->ready_cbfn = device->stop_cbfn = NULL;
1660 device->ready_cbarg = device->stop_cbarg = NULL;
1662 bfa_fsm_set_state(device, bna_device_sm_stopped);
1666 bna_device_uninit(struct bna_device *device)
1668 bna_mbox_mod_uninit(&device->bna->mbox_mod);
1670 bfa_nw_ioc_detach(&device->ioc);
1676 bna_device_cb_port_stopped(void *arg, enum bna_cb_status status)
1678 struct bna_device *device = (struct bna_device *)arg;
1680 bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED);
1684 bna_device_status_get(struct bna_device *device)
1686 return device->fsm == (bfa_fsm_t)bna_device_sm_ready;
1690 bna_device_enable(struct bna_device *device)
1692 if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) {
1693 bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY);
1697 device->ready_cbfn = bnad_cb_device_enabled;
1698 device->ready_cbarg = device->bna->bnad;
1700 bfa_fsm_send_event(device, DEVICE_E_ENABLE);
1704 bna_device_disable(struct bna_device *device, enum bna_cleanup_type type)
1706 if (type == BNA_SOFT_CLEANUP) {
1707 bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS);
1711 device->stop_cbfn = bnad_cb_device_disabled;
1712 device->stop_cbarg = device->bna->bnad;
1714 bfa_fsm_send_event(device, DEVICE_E_DISABLE);
1718 bna_device_state_get(struct bna_device *device)
1720 return bfa_sm_to_state(device_sm_table, device->fsm);
1723 const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
1737 bna_adv_res_req(struct bna_res_info *res_info)
1739 /* DMA memory for COMMON_MODULE */
1740 res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM;
1741 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1742 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1;
1743 res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN(
1744 bfa_nw_cee_meminfo(), PAGE_SIZE);
1746 /* Virtual memory for retreiving fw_trc */
1747 res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM;
1748 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1749 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0;
1750 res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0;
1752 /* DMA memory for retreiving stats */
1753 res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM;
1754 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1755 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1;
1756 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len =
1757 ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE);
1759 /* Virtual memory for soft stats */
1760 res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM;
1761 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1762 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1;
1763 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len =
1764 sizeof(struct bna_sw_stats);
1768 bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats)
1771 struct bna_txq *txq;
1773 struct bna_rxp *rxp;
1774 struct list_head *qe;
1775 struct list_head *txq_qe;
1776 struct list_head *rxp_qe;
1777 struct list_head *mac_qe;
1780 sw_stats->device_state = bna_device_state_get(&bna->device);
1781 sw_stats->port_state = bna_port_state_get(&bna->port);
1782 sw_stats->port_flags = bna->port.flags;
1783 sw_stats->llport_state = bna_llport_state_get(&bna->port.llport);
1784 sw_stats->priority = bna->port.priority;
1787 list_for_each(qe, &bna->tx_mod.tx_active_q) {
1788 tx = (struct bna_tx *)qe;
1789 sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx);
1790 sw_stats->tx_stats[i].tx_flags = tx->flags;
1792 sw_stats->tx_stats[i].num_txqs = 0;
1793 sw_stats->tx_stats[i].txq_bmap[0] = 0;
1794 sw_stats->tx_stats[i].txq_bmap[1] = 0;
1795 list_for_each(txq_qe, &tx->txq_q) {
1796 txq = (struct bna_txq *)txq_qe;
1797 if (txq->txq_id < 32)
1798 sw_stats->tx_stats[i].txq_bmap[0] |=
1799 ((u32)1 << txq->txq_id);
1801 sw_stats->tx_stats[i].txq_bmap[1] |=
1803 1 << (txq->txq_id - 32));
1804 sw_stats->tx_stats[i].num_txqs++;
1807 sw_stats->tx_stats[i].txf_id = tx->txf.txf_id;
1811 sw_stats->num_active_tx = i;
1814 list_for_each(qe, &bna->rx_mod.rx_active_q) {
1815 rx = (struct bna_rx *)qe;
1816 sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx);
1817 sw_stats->rx_stats[i].rx_flags = rx->rx_flags;
1819 sw_stats->rx_stats[i].num_rxps = 0;
1820 sw_stats->rx_stats[i].num_rxqs = 0;
1821 sw_stats->rx_stats[i].rxq_bmap[0] = 0;
1822 sw_stats->rx_stats[i].rxq_bmap[1] = 0;
1823 sw_stats->rx_stats[i].cq_bmap[0] = 0;
1824 sw_stats->rx_stats[i].cq_bmap[1] = 0;
1825 list_for_each(rxp_qe, &rx->rxp_q) {
1826 rxp = (struct bna_rxp *)rxp_qe;
1828 sw_stats->rx_stats[i].num_rxqs += 1;
1830 if (rxp->type == BNA_RXP_SINGLE) {
1831 if (rxp->rxq.single.only->rxq_id < 32) {
1832 sw_stats->rx_stats[i].rxq_bmap[0] |=
1834 rxp->rxq.single.only->rxq_id);
1836 sw_stats->rx_stats[i].rxq_bmap[1] |=
1838 (rxp->rxq.single.only->rxq_id - 32));
1841 if (rxp->rxq.slr.large->rxq_id < 32) {
1842 sw_stats->rx_stats[i].rxq_bmap[0] |=
1844 rxp->rxq.slr.large->rxq_id);
1846 sw_stats->rx_stats[i].rxq_bmap[1] |=
1848 (rxp->rxq.slr.large->rxq_id - 32));
1851 if (rxp->rxq.slr.small->rxq_id < 32) {
1852 sw_stats->rx_stats[i].rxq_bmap[0] |=
1854 rxp->rxq.slr.small->rxq_id);
1856 sw_stats->rx_stats[i].rxq_bmap[1] |=
1858 (rxp->rxq.slr.small->rxq_id - 32));
1860 sw_stats->rx_stats[i].num_rxqs += 1;
1863 if (rxp->cq.cq_id < 32)
1864 sw_stats->rx_stats[i].cq_bmap[0] |=
1865 (1 << rxp->cq.cq_id);
1867 sw_stats->rx_stats[i].cq_bmap[1] |=
1868 (1 << (rxp->cq.cq_id - 32));
1870 sw_stats->rx_stats[i].num_rxps++;
1873 sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id;
1874 sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf);
1875 sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state;
1877 sw_stats->rx_stats[i].num_active_ucast = 0;
1878 if (rx->rxf.ucast_active_mac)
1879 sw_stats->rx_stats[i].num_active_ucast++;
1880 list_for_each(mac_qe, &rx->rxf.ucast_active_q)
1881 sw_stats->rx_stats[i].num_active_ucast++;
1883 sw_stats->rx_stats[i].num_active_mcast = 0;
1884 list_for_each(mac_qe, &rx->rxf.mcast_active_q)
1885 sw_stats->rx_stats[i].num_active_mcast++;
1887 sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active;
1888 sw_stats->rx_stats[i].vlan_filter_status =
1889 rx->rxf.vlan_filter_status;
1890 memcpy(sw_stats->rx_stats[i].vlan_filter_table,
1891 rx->rxf.vlan_filter_table,
1892 sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32));
1894 sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status;
1895 sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status;
1899 sw_stats->num_active_rx = i;
1903 bna_fw_cb_stats_get(void *arg, int status)
1905 struct bna *bna = (struct bna *)arg;
1908 int rxf_count, txf_count;
1909 u64 rxf_bmap, txf_bmap;
1911 bfa_q_qe_init(&bna->mbox_qe.qe);
1914 p_stats = (u64 *)bna->stats.hw_stats;
1915 count = sizeof(struct bfi_ll_stats) / sizeof(u64);
1916 for (i = 0; i < count; i++)
1917 p_stats[i] = cpu_to_be64(p_stats[i]);
1920 rxf_bmap = (u64)bna->stats.rxf_bmap[0] |
1921 ((u64)bna->stats.rxf_bmap[1] << 32);
1922 for (i = 0; i < BFI_LL_RXF_ID_MAX; i++)
1923 if (rxf_bmap & ((u64)1 << i))
1927 txf_bmap = (u64)bna->stats.txf_bmap[0] |
1928 ((u64)bna->stats.txf_bmap[1] << 32);
1929 for (i = 0; i < BFI_LL_TXF_ID_MAX; i++)
1930 if (txf_bmap & ((u64)1 << i))
1933 p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] +
1934 ((rxf_count * sizeof(struct bfi_ll_stats_rxf) +
1935 txf_count * sizeof(struct bfi_ll_stats_txf))/
1938 /* Populate the TXF stats from the firmware DMAed copy */
1939 for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--)
1940 if (txf_bmap & ((u64)1 << i)) {
1941 p_stats -= sizeof(struct bfi_ll_stats_txf)/
1943 memcpy(&bna->stats.hw_stats->txf_stats[i],
1945 sizeof(struct bfi_ll_stats_txf));
1948 /* Populate the RXF stats from the firmware DMAed copy */
1949 for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--)
1950 if (rxf_bmap & ((u64)1 << i)) {
1951 p_stats -= sizeof(struct bfi_ll_stats_rxf)/
1953 memcpy(&bna->stats.hw_stats->rxf_stats[i],
1955 sizeof(struct bfi_ll_stats_rxf));
1958 bna_sw_stats_get(bna, bna->stats.sw_stats);
1959 bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats);
1961 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
1965 bna_fw_stats_get(struct bna *bna)
1967 struct bfi_ll_stats_req ll_req;
1969 bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
1970 ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
1972 ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]);
1973 ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]);
1974 ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]);
1975 ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]);
1977 ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb;
1978 ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb;
1980 bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
1981 bna_fw_cb_stats_get, bna);
1982 bna_mbox_send(bna, &bna->mbox_qe);
1984 bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0];
1985 bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1];
1986 bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0];
1987 bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1];
1991 bna_stats_get(struct bna *bna)
1993 if (bna_device_status_get(&bna->device))
1994 bna_fw_stats_get(bna);
1996 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
2001 bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
2003 ib->ib_config.coalescing_timeo = coalescing_timeo;
2005 if (ib->start_count)
2006 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
2007 (u32)ib->ib_config.coalescing_timeo, 0);
2012 bna_rxf_adv_init(struct bna_rxf *rxf,
2014 struct bna_rx_config *q_config)
2016 switch (q_config->rxp_type) {
2017 case BNA_RXP_SINGLE:
2021 rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ;
2024 rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type;
2025 rxf->hds_cfg.header_size =
2026 q_config->hds_config.header_size;
2027 rxf->forced_offset = 0;
2033 if (q_config->rss_status == BNA_STATUS_T_ENABLED) {
2034 rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
2035 rxf->rss_cfg.hash_type = q_config->rss_config.hash_type;
2036 rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask;
2037 memcpy(&rxf->rss_cfg.toeplitz_hash_key[0],
2038 &q_config->rss_config.toeplitz_hash_key[0],
2039 sizeof(rxf->rss_cfg.toeplitz_hash_key));
2044 rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
2046 struct bfi_ll_rxf_req req;
2048 bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
2050 req.rxf_id = rxf->rxf_id;
2051 req.enable = status;
2053 bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
2054 rxf_cb_cam_fltr_mbox_cmd, rxf);
2056 bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
2060 __rxf_default_function_config(struct bna_rxf *rxf, enum bna_status status)
2062 struct bna_rx_fndb_ram *rx_fndb_ram;
2066 rx_fndb_ram = (struct bna_rx_fndb_ram *)
2067 BNA_GET_MEM_BASE_ADDR(rxf->rx->bna->pcidev.pci_bar_kva,
2068 RX_FNDB_RAM_BASE_OFFSET);
2070 for (i = 0; i < BFI_MAX_RXF; i++) {
2071 if (status == BNA_STATUS_T_ENABLED) {
2072 if (i == rxf->rxf_id)
2076 readl(&rx_fndb_ram[i].control_flags);
2077 ctrl_flags |= BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
2079 &rx_fndb_ram[i].control_flags);
2082 readl(&rx_fndb_ram[i].control_flags);
2083 ctrl_flags &= ~BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
2085 &rx_fndb_ram[i].control_flags);
2091 rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
2093 struct bna_mac *mac = NULL;
2094 struct list_head *qe;
2096 /* Add additional MAC entries */
2097 if (!list_empty(&rxf->ucast_pending_add_q)) {
2098 bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
2100 mac = (struct bna_mac *)qe;
2101 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac);
2102 list_add_tail(&mac->qe, &rxf->ucast_active_q);
2106 /* Delete MAC addresses previousely added */
2107 if (!list_empty(&rxf->ucast_pending_del_q)) {
2108 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2110 mac = (struct bna_mac *)qe;
2111 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2112 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2120 rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
2122 struct bna *bna = rxf->rx->bna;
2124 /* Enable/disable promiscuous mode */
2125 if (is_promisc_enable(rxf->rxmode_pending,
2126 rxf->rxmode_pending_bitmask)) {
2127 /* move promisc configuration from pending -> active */
2128 promisc_inactive(rxf->rxmode_pending,
2129 rxf->rxmode_pending_bitmask);
2130 rxf->rxmode_active |= BNA_RXMODE_PROMISC;
2132 /* Disable VLAN filter to allow all VLANs */
2133 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2134 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2135 BNA_STATUS_T_ENABLED);
2137 } else if (is_promisc_disable(rxf->rxmode_pending,
2138 rxf->rxmode_pending_bitmask)) {
2139 /* move promisc configuration from pending -> active */
2140 promisc_inactive(rxf->rxmode_pending,
2141 rxf->rxmode_pending_bitmask);
2142 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2143 bna->rxf_promisc_id = BFI_MAX_RXF;
2145 /* Revert VLAN filter */
2146 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2147 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2148 BNA_STATUS_T_DISABLED);
2156 rxf_process_packet_filter_default(struct bna_rxf *rxf)
2158 struct bna *bna = rxf->rx->bna;
2160 /* Enable/disable default mode */
2161 if (is_default_enable(rxf->rxmode_pending,
2162 rxf->rxmode_pending_bitmask)) {
2163 /* move default configuration from pending -> active */
2164 default_inactive(rxf->rxmode_pending,
2165 rxf->rxmode_pending_bitmask);
2166 rxf->rxmode_active |= BNA_RXMODE_DEFAULT;
2168 /* Disable VLAN filter to allow all VLANs */
2169 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2170 /* Redirect all other RxF vlan filtering to this one */
2171 __rxf_default_function_config(rxf, BNA_STATUS_T_ENABLED);
2172 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2173 BNA_STATUS_T_ENABLED);
2175 } else if (is_default_disable(rxf->rxmode_pending,
2176 rxf->rxmode_pending_bitmask)) {
2177 /* move default configuration from pending -> active */
2178 default_inactive(rxf->rxmode_pending,
2179 rxf->rxmode_pending_bitmask);
2180 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2181 bna->rxf_default_id = BFI_MAX_RXF;
2183 /* Revert VLAN filter */
2184 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2185 /* Stop RxF vlan filter table redirection */
2186 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2187 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2188 BNA_STATUS_T_DISABLED);
2196 rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
2198 /* Enable/disable allmulti mode */
2199 if (is_allmulti_enable(rxf->rxmode_pending,
2200 rxf->rxmode_pending_bitmask)) {
2201 /* move allmulti configuration from pending -> active */
2202 allmulti_inactive(rxf->rxmode_pending,
2203 rxf->rxmode_pending_bitmask);
2204 rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
2206 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2207 BNA_STATUS_T_ENABLED);
2209 } else if (is_allmulti_disable(rxf->rxmode_pending,
2210 rxf->rxmode_pending_bitmask)) {
2211 /* move allmulti configuration from pending -> active */
2212 allmulti_inactive(rxf->rxmode_pending,
2213 rxf->rxmode_pending_bitmask);
2214 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2216 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2217 BNA_STATUS_T_DISABLED);
2225 rxf_clear_packet_filter_ucast(struct bna_rxf *rxf)
2227 struct bna_mac *mac = NULL;
2228 struct list_head *qe;
2230 /* 1. delete pending ucast entries */
2231 if (!list_empty(&rxf->ucast_pending_del_q)) {
2232 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2234 mac = (struct bna_mac *)qe;
2235 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2236 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2240 /* 2. clear active ucast entries; move them to pending_add_q */
2241 if (!list_empty(&rxf->ucast_active_q)) {
2242 bfa_q_deq(&rxf->ucast_active_q, &qe);
2244 mac = (struct bna_mac *)qe;
2245 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2246 list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
2254 rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
2256 struct bna *bna = rxf->rx->bna;
2258 /* 6. Execute pending promisc mode disable command */
2259 if (is_promisc_disable(rxf->rxmode_pending,
2260 rxf->rxmode_pending_bitmask)) {
2261 /* move promisc configuration from pending -> active */
2262 promisc_inactive(rxf->rxmode_pending,
2263 rxf->rxmode_pending_bitmask);
2264 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2265 bna->rxf_promisc_id = BFI_MAX_RXF;
2267 /* Revert VLAN filter */
2268 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2269 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2270 BNA_STATUS_T_DISABLED);
2274 /* 7. Clear active promisc mode; move it to pending enable */
2275 if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2276 /* move promisc configuration from active -> pending */
2277 promisc_enable(rxf->rxmode_pending,
2278 rxf->rxmode_pending_bitmask);
2279 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2281 /* Revert VLAN filter */
2282 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2283 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2284 BNA_STATUS_T_DISABLED);
2292 rxf_clear_packet_filter_default(struct bna_rxf *rxf)
2294 struct bna *bna = rxf->rx->bna;
2296 /* 8. Execute pending default mode disable command */
2297 if (is_default_disable(rxf->rxmode_pending,
2298 rxf->rxmode_pending_bitmask)) {
2299 /* move default configuration from pending -> active */
2300 default_inactive(rxf->rxmode_pending,
2301 rxf->rxmode_pending_bitmask);
2302 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2303 bna->rxf_default_id = BFI_MAX_RXF;
2305 /* Revert VLAN filter */
2306 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2307 /* Stop RxF vlan filter table redirection */
2308 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2309 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2310 BNA_STATUS_T_DISABLED);
2314 /* 9. Clear active default mode; move it to pending enable */
2315 if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2316 /* move default configuration from active -> pending */
2317 default_enable(rxf->rxmode_pending,
2318 rxf->rxmode_pending_bitmask);
2319 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2321 /* Revert VLAN filter */
2322 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2323 /* Stop RxF vlan filter table redirection */
2324 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2325 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2326 BNA_STATUS_T_DISABLED);
2334 rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
2336 /* 10. Execute pending allmulti mode disable command */
2337 if (is_allmulti_disable(rxf->rxmode_pending,
2338 rxf->rxmode_pending_bitmask)) {
2339 /* move allmulti configuration from pending -> active */
2340 allmulti_inactive(rxf->rxmode_pending,
2341 rxf->rxmode_pending_bitmask);
2342 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2343 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2344 BNA_STATUS_T_DISABLED);
2348 /* 11. Clear active allmulti mode; move it to pending enable */
2349 if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2350 /* move allmulti configuration from active -> pending */
2351 allmulti_enable(rxf->rxmode_pending,
2352 rxf->rxmode_pending_bitmask);
2353 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2354 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2355 BNA_STATUS_T_DISABLED);
2363 rxf_reset_packet_filter_ucast(struct bna_rxf *rxf)
2365 struct list_head *qe;
2366 struct bna_mac *mac;
2368 /* 1. Move active ucast entries to pending_add_q */
2369 while (!list_empty(&rxf->ucast_active_q)) {
2370 bfa_q_deq(&rxf->ucast_active_q, &qe);
2372 list_add_tail(qe, &rxf->ucast_pending_add_q);
2375 /* 2. Throw away delete pending ucast entries */
2376 while (!list_empty(&rxf->ucast_pending_del_q)) {
2377 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2379 mac = (struct bna_mac *)qe;
2380 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2385 rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
2387 struct bna *bna = rxf->rx->bna;
2389 /* 6. Clear pending promisc mode disable */
2390 if (is_promisc_disable(rxf->rxmode_pending,
2391 rxf->rxmode_pending_bitmask)) {
2392 promisc_inactive(rxf->rxmode_pending,
2393 rxf->rxmode_pending_bitmask);
2394 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2395 bna->rxf_promisc_id = BFI_MAX_RXF;
2398 /* 7. Move promisc mode config from active -> pending */
2399 if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2400 promisc_enable(rxf->rxmode_pending,
2401 rxf->rxmode_pending_bitmask);
2402 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2408 rxf_reset_packet_filter_default(struct bna_rxf *rxf)
2410 struct bna *bna = rxf->rx->bna;
2412 /* 8. Clear pending default mode disable */
2413 if (is_default_disable(rxf->rxmode_pending,
2414 rxf->rxmode_pending_bitmask)) {
2415 default_inactive(rxf->rxmode_pending,
2416 rxf->rxmode_pending_bitmask);
2417 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2418 bna->rxf_default_id = BFI_MAX_RXF;
2421 /* 9. Move default mode config from active -> pending */
2422 if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2423 default_enable(rxf->rxmode_pending,
2424 rxf->rxmode_pending_bitmask);
2425 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2430 rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
2432 /* 10. Clear pending allmulti mode disable */
2433 if (is_allmulti_disable(rxf->rxmode_pending,
2434 rxf->rxmode_pending_bitmask)) {
2435 allmulti_inactive(rxf->rxmode_pending,
2436 rxf->rxmode_pending_bitmask);
2437 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2440 /* 11. Move allmulti mode config from active -> pending */
2441 if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2442 allmulti_enable(rxf->rxmode_pending,
2443 rxf->rxmode_pending_bitmask);
2444 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2449 * Should only be called by bna_rxf_mode_set.
2450 * Helps deciding if h/w configuration is needed or not.
2453 * 1 = need h/w change
2456 rxf_promisc_enable(struct bna_rxf *rxf)
2458 struct bna *bna = rxf->rx->bna;
2461 /* There can not be any pending disable command */
2463 /* Do nothing if pending enable or already enabled */
2464 if (is_promisc_enable(rxf->rxmode_pending,
2465 rxf->rxmode_pending_bitmask) ||
2466 (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
2467 /* Schedule enable */
2469 /* Promisc mode should not be active in the system */
2470 promisc_enable(rxf->rxmode_pending,
2471 rxf->rxmode_pending_bitmask);
2472 bna->rxf_promisc_id = rxf->rxf_id;
2480 * Should only be called by bna_rxf_mode_set.
2481 * Helps deciding if h/w configuration is needed or not.
2484 * 1 = need h/w change
2487 rxf_promisc_disable(struct bna_rxf *rxf)
2489 struct bna *bna = rxf->rx->bna;
2492 /* There can not be any pending disable */
2494 /* Turn off pending enable command , if any */
2495 if (is_promisc_enable(rxf->rxmode_pending,
2496 rxf->rxmode_pending_bitmask)) {
2497 /* Promisc mode should not be active */
2498 /* system promisc state should be pending */
2499 promisc_inactive(rxf->rxmode_pending,
2500 rxf->rxmode_pending_bitmask);
2501 /* Remove the promisc state from the system */
2502 bna->rxf_promisc_id = BFI_MAX_RXF;
2504 /* Schedule disable */
2505 } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2506 /* Promisc mode should be active in the system */
2507 promisc_disable(rxf->rxmode_pending,
2508 rxf->rxmode_pending_bitmask);
2511 /* Do nothing if already disabled */
2519 * Should only be called by bna_rxf_mode_set.
2520 * Helps deciding if h/w configuration is needed or not.
2523 * 1 = need h/w change
2526 rxf_default_enable(struct bna_rxf *rxf)
2528 struct bna *bna = rxf->rx->bna;
2531 /* There can not be any pending disable command */
2533 /* Do nothing if pending enable or already enabled */
2534 if (is_default_enable(rxf->rxmode_pending,
2535 rxf->rxmode_pending_bitmask) ||
2536 (rxf->rxmode_active & BNA_RXMODE_DEFAULT)) {
2537 /* Schedule enable */
2539 /* Default mode should not be active in the system */
2540 default_enable(rxf->rxmode_pending,
2541 rxf->rxmode_pending_bitmask);
2542 bna->rxf_default_id = rxf->rxf_id;
2550 * Should only be called by bna_rxf_mode_set.
2551 * Helps deciding if h/w configuration is needed or not.
2554 * 1 = need h/w change
2557 rxf_default_disable(struct bna_rxf *rxf)
2559 struct bna *bna = rxf->rx->bna;
2562 /* There can not be any pending disable */
2564 /* Turn off pending enable command , if any */
2565 if (is_default_enable(rxf->rxmode_pending,
2566 rxf->rxmode_pending_bitmask)) {
2567 /* Promisc mode should not be active */
2568 /* system default state should be pending */
2569 default_inactive(rxf->rxmode_pending,
2570 rxf->rxmode_pending_bitmask);
2571 /* Remove the default state from the system */
2572 bna->rxf_default_id = BFI_MAX_RXF;
2574 /* Schedule disable */
2575 } else if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2576 /* Default mode should be active in the system */
2577 default_disable(rxf->rxmode_pending,
2578 rxf->rxmode_pending_bitmask);
2581 /* Do nothing if already disabled */
2589 * Should only be called by bna_rxf_mode_set.
2590 * Helps deciding if h/w configuration is needed or not.
2593 * 1 = need h/w change
2596 rxf_allmulti_enable(struct bna_rxf *rxf)
2600 /* There can not be any pending disable command */
2602 /* Do nothing if pending enable or already enabled */
2603 if (is_allmulti_enable(rxf->rxmode_pending,
2604 rxf->rxmode_pending_bitmask) ||
2605 (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
2606 /* Schedule enable */
2608 allmulti_enable(rxf->rxmode_pending,
2609 rxf->rxmode_pending_bitmask);
2617 * Should only be called by bna_rxf_mode_set.
2618 * Helps deciding if h/w configuration is needed or not.
2621 * 1 = need h/w change
2624 rxf_allmulti_disable(struct bna_rxf *rxf)
2628 /* There can not be any pending disable */
2630 /* Turn off pending enable command , if any */
2631 if (is_allmulti_enable(rxf->rxmode_pending,
2632 rxf->rxmode_pending_bitmask)) {
2633 /* Allmulti mode should not be active */
2634 allmulti_inactive(rxf->rxmode_pending,
2635 rxf->rxmode_pending_bitmask);
2637 /* Schedule disable */
2638 } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2639 allmulti_disable(rxf->rxmode_pending,
2640 rxf->rxmode_pending_bitmask);
2649 bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
2650 enum bna_rxmode bitmask,
2651 void (*cbfn)(struct bnad *, struct bna_rx *,
2652 enum bna_cb_status))
2654 struct bna_rxf *rxf = &rx->rxf;
2655 int need_hw_config = 0;
2659 if (is_promisc_enable(new_mode, bitmask)) {
2660 /* If promisc mode is already enabled elsewhere in the system */
2661 if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
2662 (rx->bna->rxf_promisc_id != rxf->rxf_id))
2665 /* If default mode is already enabled in the system */
2666 if (rx->bna->rxf_default_id != BFI_MAX_RXF)
2669 /* Trying to enable promiscuous and default mode together */
2670 if (is_default_enable(new_mode, bitmask))
2674 if (is_default_enable(new_mode, bitmask)) {
2675 /* If default mode is already enabled elsewhere in the system */
2676 if ((rx->bna->rxf_default_id != BFI_MAX_RXF) &&
2677 (rx->bna->rxf_default_id != rxf->rxf_id)) {
2681 /* If promiscuous mode is already enabled in the system */
2682 if (rx->bna->rxf_promisc_id != BFI_MAX_RXF)
2686 /* Process the commands */
2688 if (is_promisc_enable(new_mode, bitmask)) {
2689 if (rxf_promisc_enable(rxf))
2691 } else if (is_promisc_disable(new_mode, bitmask)) {
2692 if (rxf_promisc_disable(rxf))
2696 if (is_default_enable(new_mode, bitmask)) {
2697 if (rxf_default_enable(rxf))
2699 } else if (is_default_disable(new_mode, bitmask)) {
2700 if (rxf_default_disable(rxf))
2704 if (is_allmulti_enable(new_mode, bitmask)) {
2705 if (rxf_allmulti_enable(rxf))
2707 } else if (is_allmulti_disable(new_mode, bitmask)) {
2708 if (rxf_allmulti_disable(rxf))
2712 /* Trigger h/w if needed */
2714 if (need_hw_config) {
2715 rxf->cam_fltr_cbfn = cbfn;
2716 rxf->cam_fltr_cbarg = rx->bna->bnad;
2717 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2719 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2721 return BNA_CB_SUCCESS;
2729 bna_rx_vlanfilter_enable(struct bna_rx *rx)
2731 struct bna_rxf *rxf = &rx->rxf;
2733 if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
2734 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
2735 rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
2736 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2744 bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
2746 struct bna_rxp *rxp;
2747 struct list_head *qe;
2749 list_for_each(qe, &rx->rxp_q) {
2750 rxp = (struct bna_rxp *)qe;
2751 rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
2752 bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo);
2758 bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
2762 for (i = 0; i < BNA_LOAD_T_MAX; i++)
2763 for (j = 0; j < BNA_BIAS_T_MAX; j++)
2764 bna->rx_mod.dim_vector[i][j] = vector[i][j];
2769 bna_rx_dim_update(struct bna_ccb *ccb)
2771 struct bna *bna = ccb->cq->rx->bna;
2773 u32 pkt_rt, small_rt, large_rt;
2774 u8 coalescing_timeo;
2776 if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
2777 (ccb->pkt_rate.large_pkt_cnt == 0))
2780 /* Arrive at preconfigured coalescing timeo value based on pkt rate */
2782 small_rt = ccb->pkt_rate.small_pkt_cnt;
2783 large_rt = ccb->pkt_rate.large_pkt_cnt;
2785 pkt_rt = small_rt + large_rt;
2787 if (pkt_rt < BNA_PKT_RATE_10K)
2788 load = BNA_LOAD_T_LOW_4;
2789 else if (pkt_rt < BNA_PKT_RATE_20K)
2790 load = BNA_LOAD_T_LOW_3;
2791 else if (pkt_rt < BNA_PKT_RATE_30K)
2792 load = BNA_LOAD_T_LOW_2;
2793 else if (pkt_rt < BNA_PKT_RATE_40K)
2794 load = BNA_LOAD_T_LOW_1;
2795 else if (pkt_rt < BNA_PKT_RATE_50K)
2796 load = BNA_LOAD_T_HIGH_1;
2797 else if (pkt_rt < BNA_PKT_RATE_60K)
2798 load = BNA_LOAD_T_HIGH_2;
2799 else if (pkt_rt < BNA_PKT_RATE_80K)
2800 load = BNA_LOAD_T_HIGH_3;
2802 load = BNA_LOAD_T_HIGH_4;
2804 if (small_rt > (large_rt << 1))
2809 ccb->pkt_rate.small_pkt_cnt = 0;
2810 ccb->pkt_rate.large_pkt_cnt = 0;
2812 coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
2813 ccb->rx_coalescing_timeo = coalescing_timeo;
2816 bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo);
2822 bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
2824 struct bna_txq *txq;
2825 struct list_head *qe;
2827 list_for_each(qe, &tx->txq_q) {
2828 txq = (struct bna_txq *)qe;
2829 bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo);
2837 struct bna_ritseg_pool_cfg {
2839 u32 pool_entry_size;
2841 init_ritseg_pool(ritseg_pool_cfg);
2847 bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
2848 struct bna_res_info *res_info)
2852 ucam_mod->ucmac = (struct bna_mac *)
2853 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
2855 INIT_LIST_HEAD(&ucam_mod->free_q);
2856 for (i = 0; i < BFI_MAX_UCMAC; i++) {
2857 bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
2858 list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
2861 ucam_mod->bna = bna;
2865 bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
2867 struct list_head *qe;
2870 list_for_each(qe, &ucam_mod->free_q)
2873 ucam_mod->bna = NULL;
2877 bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
2878 struct bna_res_info *res_info)
2882 mcam_mod->mcmac = (struct bna_mac *)
2883 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
2885 INIT_LIST_HEAD(&mcam_mod->free_q);
2886 for (i = 0; i < BFI_MAX_MCMAC; i++) {
2887 bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
2888 list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
2891 mcam_mod->bna = bna;
2895 bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
2897 struct list_head *qe;
2900 list_for_each(qe, &mcam_mod->free_q)
2903 mcam_mod->bna = NULL;
2907 bna_rit_mod_init(struct bna_rit_mod *rit_mod,
2908 struct bna_res_info *res_info)
2915 rit_mod->rit = (struct bna_rit_entry *)
2916 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva;
2917 rit_mod->rit_segment = (struct bna_rit_segment *)
2918 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva;
2922 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
2923 INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]);
2924 for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) {
2925 bfa_q_qe_init(&rit_mod->rit_segment[count].qe);
2926 rit_mod->rit_segment[count].max_rit_size =
2927 ritseg_pool_cfg[i].pool_entry_size;
2928 rit_mod->rit_segment[count].rit_offset = offset;
2929 rit_mod->rit_segment[count].rit =
2930 &rit_mod->rit[offset];
2931 list_add_tail(&rit_mod->rit_segment[count].qe,
2932 &rit_mod->rit_seg_pool[i]);
2934 offset += ritseg_pool_cfg[i].pool_entry_size;
2940 bna_rit_mod_uninit(struct bna_rit_mod *rit_mod)
2942 struct bna_rit_segment *rit_segment;
2943 struct list_head *qe;
2947 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
2949 list_for_each(qe, &rit_mod->rit_seg_pool[i]) {
2950 rit_segment = (struct bna_rit_segment *)qe;
2960 /* Called during probe(), before calling bna_init() */
2962 bna_res_req(struct bna_res_info *res_info)
2964 bna_adv_res_req(res_info);
2966 /* DMA memory for retrieving IOC attributes */
2967 res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM;
2968 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
2969 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1;
2970 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len =
2971 ALIGN(bfa_nw_ioc_meminfo(), PAGE_SIZE);
2973 /* DMA memory for index segment of an IB */
2974 res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
2975 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
2976 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len =
2977 BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE;
2978 res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB;
2980 /* Virtual memory for IB objects - stored by IB module */
2981 res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM;
2982 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type =
2984 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1;
2985 res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len =
2986 BFI_MAX_IB * sizeof(struct bna_ib);
2988 /* Virtual memory for intr objects - stored by IB module */
2989 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM;
2990 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type =
2992 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1;
2993 res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len =
2994 BFI_MAX_IB * sizeof(struct bna_intr);
2996 /* Virtual memory for idx_seg objects - stored by IB module */
2997 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM;
2998 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type =
3000 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1;
3001 res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len =
3002 BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg);
3004 /* Virtual memory for Tx objects - stored by Tx module */
3005 res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM;
3006 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type =
3008 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1;
3009 res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len =
3010 BFI_MAX_TXQ * sizeof(struct bna_tx);
3012 /* Virtual memory for TxQ - stored by Tx module */
3013 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM;
3014 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type =
3016 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1;
3017 res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len =
3018 BFI_MAX_TXQ * sizeof(struct bna_txq);
3020 /* Virtual memory for Rx objects - stored by Rx module */
3021 res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM;
3022 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type =
3024 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1;
3025 res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len =
3026 BFI_MAX_RXQ * sizeof(struct bna_rx);
3028 /* Virtual memory for RxPath - stored by Rx module */
3029 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM;
3030 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type =
3032 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1;
3033 res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len =
3034 BFI_MAX_RXQ * sizeof(struct bna_rxp);
3036 /* Virtual memory for RxQ - stored by Rx module */
3037 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM;
3038 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type =
3040 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1;
3041 res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len =
3042 BFI_MAX_RXQ * sizeof(struct bna_rxq);
3044 /* Virtual memory for Unicast MAC address - stored by ucam module */
3045 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM;
3046 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type =
3048 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1;
3049 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len =
3050 BFI_MAX_UCMAC * sizeof(struct bna_mac);
3052 /* Virtual memory for Multicast MAC address - stored by mcam module */
3053 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM;
3054 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type =
3056 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1;
3057 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len =
3058 BFI_MAX_MCMAC * sizeof(struct bna_mac);
3060 /* Virtual memory for RIT entries */
3061 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM;
3062 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type =
3064 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1;
3065 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len =
3066 BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry);
3068 /* Virtual memory for RIT segment table */
3069 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM;
3070 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type =
3072 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1;
3073 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len =
3074 BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment);
3076 /* Interrupt resource for mailbox interrupt */
3077 res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR;
3078 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type =
3080 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1;
3083 /* Called during probe() */
3085 bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
3086 struct bna_res_info *res_info)
3089 bna->pcidev = *pcidev;
3091 bna->stats.hw_stats = (struct bfi_ll_stats *)
3092 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva;
3093 bna->hw_stats_dma.msb =
3094 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb;
3095 bna->hw_stats_dma.lsb =
3096 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb;
3097 bna->stats.sw_stats = (struct bna_sw_stats *)
3098 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva;
3100 bna->regs.page_addr = bna->pcidev.pci_bar_kva +
3101 reg_offset[bna->pcidev.pci_func].page_addr;
3102 bna->regs.fn_int_status = bna->pcidev.pci_bar_kva +
3103 reg_offset[bna->pcidev.pci_func].fn_int_status;
3104 bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva +
3105 reg_offset[bna->pcidev.pci_func].fn_int_mask;
3107 if (bna->pcidev.pci_func < 3)
3112 /* Also initializes diag, cee, sfp, phy_port and mbox_mod */
3113 bna_device_init(&bna->device, bna, res_info);
3115 bna_port_init(&bna->port, bna);
3117 bna_tx_mod_init(&bna->tx_mod, bna, res_info);
3119 bna_rx_mod_init(&bna->rx_mod, bna, res_info);
3121 bna_ib_mod_init(&bna->ib_mod, bna, res_info);
3123 bna_rit_mod_init(&bna->rit_mod, res_info);
3125 bna_ucam_mod_init(&bna->ucam_mod, bna, res_info);
3127 bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
3129 bna->rxf_default_id = BFI_MAX_RXF;
3130 bna->rxf_promisc_id = BFI_MAX_RXF;
3132 /* Mbox q element for posting stat request to f/w */
3133 bfa_q_qe_init(&bna->mbox_qe.qe);
3137 bna_uninit(struct bna *bna)
3139 bna_mcam_mod_uninit(&bna->mcam_mod);
3141 bna_ucam_mod_uninit(&bna->ucam_mod);
3143 bna_rit_mod_uninit(&bna->rit_mod);
3145 bna_ib_mod_uninit(&bna->ib_mod);
3147 bna_rx_mod_uninit(&bna->rx_mod);
3149 bna_tx_mod_uninit(&bna->tx_mod);
3151 bna_port_uninit(&bna->port);
3153 bna_device_uninit(&bna->device);
3159 bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod)
3161 struct list_head *qe;
3163 if (list_empty(&ucam_mod->free_q))
3166 bfa_q_deq(&ucam_mod->free_q, &qe);
3168 return (struct bna_mac *)qe;
3172 bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac)
3174 list_add_tail(&mac->qe, &ucam_mod->free_q);
3178 bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod)
3180 struct list_head *qe;
3182 if (list_empty(&mcam_mod->free_q))
3185 bfa_q_deq(&mcam_mod->free_q, &qe);
3187 return (struct bna_mac *)qe;
3191 bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac)
3193 list_add_tail(&mac->qe, &mcam_mod->free_q);
3197 * Note: This should be called in the same locking context as the call to
3198 * bna_rit_mod_seg_get()
3201 bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size)
3205 /* Select the pool for seg_size */
3206 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3207 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3211 if (i == BFI_RIT_SEG_TOTAL_POOLS)
3214 if (list_empty(&rit_mod->rit_seg_pool[i]))
3220 struct bna_rit_segment *
3221 bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size)
3223 struct bna_rit_segment *seg;
3224 struct list_head *qe;
3227 /* Select the pool for seg_size */
3228 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3229 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3233 if (i == BFI_RIT_SEG_TOTAL_POOLS)
3236 if (list_empty(&rit_mod->rit_seg_pool[i]))
3239 bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe);
3240 seg = (struct bna_rit_segment *)qe;
3241 bfa_q_qe_init(&seg->qe);
3242 seg->rit_size = seg_size;
3248 bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
3249 struct bna_rit_segment *seg)
3253 /* Select the pool for seg->max_rit_size */
3254 for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3255 if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size)
3260 list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]);