drivers/net/bna/bna_ctrl.c

   1 /*
   2  * Linux network driver for Brocade Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  15  * All rights reserved
  16  * www.brocade.com
  17  */
  18 #include "bna.h"
  19 #include "bfa_sm.h"
  20 #include "bfa_wc.h"
  21
  22 static void bna_device_cb_port_stopped(void *arg, enum bna_cb_status status);
  23
  24 static void
  25 bna_port_cb_link_up(struct bna_port *port, struct bfi_ll_aen *aen,
  26                         int status)
  27 {
  28         int i;
  29         u8 prio_map;
  30
  31         port->llport.link_status = BNA_LINK_UP;
  32         if (aen->cee_linkup)
  33                 port->llport.link_status = BNA_CEE_UP;
  34
  35         /* Compute the priority */
  36         prio_map = aen->prio_map;
  37         if (prio_map) {
  38                 for (i = 0; i < 8; i++) {
  39                         if ((prio_map >> i) & 0x1)
  40                                 break;
  41                 }
  42                 port->priority = i;
  43         } else
  44                 port->priority = 0;
  45
  46         /* Dispatch events */
  47         bna_tx_mod_cee_link_status(&port->bna->tx_mod, aen->cee_linkup);
  48         bna_tx_mod_prio_changed(&port->bna->tx_mod, port->priority);
  49         port->link_cbfn(port->bna->bnad, port->llport.link_status);
  50 }
  51
  52 static void
  53 bna_port_cb_link_down(struct bna_port *port, int status)
  54 {
  55         port->llport.link_status = BNA_LINK_DOWN;
  56
  57         /* Dispatch events */
  58         bna_tx_mod_cee_link_status(&port->bna->tx_mod, BNA_LINK_DOWN);
  59         port->link_cbfn(port->bna->bnad, BNA_LINK_DOWN);
  60 }
  61
  62 /**
  63  * MBOX
  64  */
  65 static int
  66 bna_is_aen(u8 msg_id)
  67 {
  68         return msg_id == BFI_LL_I2H_LINK_DOWN_AEN ||
  69                msg_id == BFI_LL_I2H_LINK_UP_AEN;
  70 }
  71
  72 static void
  73 bna_mbox_aen_callback(struct bna *bna, struct bfi_mbmsg *msg)
  74 {
  75         struct bfi_ll_aen *aen = (struct bfi_ll_aen *)(msg);
  76
  77         switch (aen->mh.msg_id) {
  78         case BFI_LL_I2H_LINK_UP_AEN:
  79                 bna_port_cb_link_up(&bna->port, aen, aen->reason);
  80                 break;
  81         case BFI_LL_I2H_LINK_DOWN_AEN:
  82                 bna_port_cb_link_down(&bna->port, aen->reason);
  83                 break;
  84         default:
  85                 break;
  86         }
  87 }
  88
  89 static void
  90 bna_ll_isr(void *llarg, struct bfi_mbmsg *msg)
  91 {
  92         struct bna *bna = (struct bna *)(llarg);
  93         struct bfi_ll_rsp *mb_rsp = (struct bfi_ll_rsp *)(msg);
  94         struct bfi_mhdr *cmd_h, *rsp_h;
  95         struct bna_mbox_qe *mb_qe = NULL;
  96         int to_post = 0;
  97         u8 aen = 0;
  98         char message[BNA_MESSAGE_SIZE];
  99
 100         aen = bna_is_aen(mb_rsp->mh.msg_id);
 101
 102         if (!aen) {
 103                 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
 104                 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
 105                 rsp_h = (struct bfi_mhdr *)(&mb_rsp->mh);
 106
 107                 if ((BFA_I2HM(cmd_h->msg_id) == rsp_h->msg_id) &&
 108                     (cmd_h->mtag.i2htok == rsp_h->mtag.i2htok)) {
 109                         /* Remove the request from posted_q, update state  */
 110                         list_del(&mb_qe->qe);
 111                         bna->mbox_mod.msg_pending--;
 112                         if (list_empty(&bna->mbox_mod.posted_q))
 113                                 bna->mbox_mod.state = BNA_MBOX_FREE;
 114                         else
 115                                 to_post = 1;
 116
 117                         /* Dispatch the cbfn */
 118                         if (mb_qe->cbfn)
 119                                 mb_qe->cbfn(mb_qe->cbarg, mb_rsp->error);
 120
 121                         /* Post the next entry, if needed */
 122                         if (to_post) {
 123                                 mb_qe = bfa_q_first(&bna->mbox_mod.posted_q);
 124                                 bfa_nw_ioc_mbox_queue(&bna->device.ioc,
 125                                                         &mb_qe->cmd);
 126                         }
 127                 } else {
 128                         snprintf(message, BNA_MESSAGE_SIZE,
 129                                        "No matching rsp for [%d:%d:%d]\n",
 130                                        mb_rsp->mh.msg_class, mb_rsp->mh.msg_id,
 131                                        mb_rsp->mh.mtag.i2htok);
 132                 pr_info("%s", message);
 133                 }
 134
 135         } else
 136                 bna_mbox_aen_callback(bna, msg);
 137 }
 138
 139 static void
 140 bna_err_handler(struct bna *bna, u32 intr_status)
 141 {
 142         u32 init_halt;
 143
 144         if (intr_status & __HALT_STATUS_BITS) {
 145                 init_halt = readl(bna->device.ioc.ioc_regs.ll_halt);
 146                 init_halt &= ~__FW_INIT_HALT_P;
 147                 writel(init_halt, bna->device.ioc.ioc_regs.ll_halt);
 148         }
 149
 150         bfa_nw_ioc_error_isr(&bna->device.ioc);
 151 }
 152
 153 void
 154 bna_mbox_handler(struct bna *bna, u32 intr_status)
 155 {
 156         if (BNA_IS_ERR_INTR(intr_status)) {
 157                 bna_err_handler(bna, intr_status);
 158                 return;
 159         }
 160         if (BNA_IS_MBOX_INTR(intr_status))
 161                 bfa_nw_ioc_mbox_isr(&bna->device.ioc);
 162 }
 163
 164 void
 165 bna_mbox_send(struct bna *bna, struct bna_mbox_qe *mbox_qe)
 166 {
 167         struct bfi_mhdr *mh;
 168
 169         mh = (struct bfi_mhdr *)(&mbox_qe->cmd.msg[0]);
 170
 171         mh->mtag.i2htok = htons(bna->mbox_mod.msg_ctr);
 172         bna->mbox_mod.msg_ctr++;
 173         bna->mbox_mod.msg_pending++;
 174         if (bna->mbox_mod.state == BNA_MBOX_FREE) {
 175                 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
 176                 bfa_nw_ioc_mbox_queue(&bna->device.ioc, &mbox_qe->cmd);
 177                 bna->mbox_mod.state = BNA_MBOX_POSTED;
 178         } else {
 179                 list_add_tail(&mbox_qe->qe, &bna->mbox_mod.posted_q);
 180         }
 181 }
 182
 183 static void
 184 bna_mbox_flush_q(struct bna *bna, struct list_head *q)
 185 {
 186         struct bna_mbox_qe *mb_qe = NULL;
 187         struct bfi_mhdr *cmd_h;
 188         struct list_head                        *mb_q;
 189         void                    (*cbfn)(void *arg, int status);
 190         void                    *cbarg;
 191
 192         mb_q = &bna->mbox_mod.posted_q;
 193
 194         while (!list_empty(mb_q)) {
 195                 bfa_q_deq(mb_q, &mb_qe);
 196                 cbfn = mb_qe->cbfn;
 197                 cbarg = mb_qe->cbarg;
 198                 bfa_q_qe_init(mb_qe);
 199                 bna->mbox_mod.msg_pending--;
 200
 201                 cmd_h = (struct bfi_mhdr *)(&mb_qe->cmd.msg[0]);
 202                 if (cbfn)
 203                         cbfn(cbarg, BNA_CB_NOT_EXEC);
 204         }
 205
 206         bna->mbox_mod.state = BNA_MBOX_FREE;
 207 }
 208
 209 static void
 210 bna_mbox_mod_start(struct bna_mbox_mod *mbox_mod)
 211 {
 212 }
 213
 214 static void
 215 bna_mbox_mod_stop(struct bna_mbox_mod *mbox_mod)
 216 {
 217         bna_mbox_flush_q(mbox_mod->bna, &mbox_mod->posted_q);
 218 }
 219
 220 static void
 221 bna_mbox_mod_init(struct bna_mbox_mod *mbox_mod, struct bna *bna)
 222 {
 223         bfa_nw_ioc_mbox_regisr(&bna->device.ioc, BFI_MC_LL, bna_ll_isr, bna);
 224         mbox_mod->state = BNA_MBOX_FREE;
 225         mbox_mod->msg_ctr = mbox_mod->msg_pending = 0;
 226         INIT_LIST_HEAD(&mbox_mod->posted_q);
 227         mbox_mod->bna = bna;
 228 }
 229
 230 static void
 231 bna_mbox_mod_uninit(struct bna_mbox_mod *mbox_mod)
 232 {
 233         mbox_mod->bna = NULL;
 234 }
 235
 236 /**
 237  * LLPORT
 238  */
 239 #define call_llport_stop_cbfn(llport, status)\
 240 do {\
 241         if ((llport)->stop_cbfn)\
 242                 (llport)->stop_cbfn(&(llport)->bna->port, status);\
 243         (llport)->stop_cbfn = NULL;\
 244 } while (0)
 245
 246 static void bna_fw_llport_up(struct bna_llport *llport);
 247 static void bna_fw_cb_llport_up(void *arg, int status);
 248 static void bna_fw_llport_down(struct bna_llport *llport);
 249 static void bna_fw_cb_llport_down(void *arg, int status);
 250 static void bna_llport_start(struct bna_llport *llport);
 251 static void bna_llport_stop(struct bna_llport *llport);
 252 static void bna_llport_fail(struct bna_llport *llport);
 253
 254 enum bna_llport_event {
 255         LLPORT_E_START                  = 1,
 256         LLPORT_E_STOP                   = 2,
 257         LLPORT_E_FAIL                   = 3,
 258         LLPORT_E_UP                     = 4,
 259         LLPORT_E_DOWN                   = 5,
 260         LLPORT_E_FWRESP_UP              = 6,
 261         LLPORT_E_FWRESP_DOWN            = 7
 262 };
 263
 264 enum bna_llport_state {
 265         BNA_LLPORT_STOPPED              = 1,
 266         BNA_LLPORT_DOWN                 = 2,
 267         BNA_LLPORT_UP_RESP_WAIT         = 3,
 268         BNA_LLPORT_DOWN_RESP_WAIT       = 4,
 269         BNA_LLPORT_UP                   = 5,
 270         BNA_LLPORT_LAST_RESP_WAIT       = 6
 271 };
 272
 273 bfa_fsm_state_decl(bna_llport, stopped, struct bna_llport,
 274                         enum bna_llport_event);
 275 bfa_fsm_state_decl(bna_llport, down, struct bna_llport,
 276                         enum bna_llport_event);
 277 bfa_fsm_state_decl(bna_llport, up_resp_wait, struct bna_llport,
 278                         enum bna_llport_event);
 279 bfa_fsm_state_decl(bna_llport, down_resp_wait, struct bna_llport,
 280                         enum bna_llport_event);
 281 bfa_fsm_state_decl(bna_llport, up, struct bna_llport,
 282                         enum bna_llport_event);
 283 bfa_fsm_state_decl(bna_llport, last_resp_wait, struct bna_llport,
 284                         enum bna_llport_event);
 285
 286 static struct bfa_sm_table llport_sm_table[] = {
 287         {BFA_SM(bna_llport_sm_stopped), BNA_LLPORT_STOPPED},
 288         {BFA_SM(bna_llport_sm_down), BNA_LLPORT_DOWN},
 289         {BFA_SM(bna_llport_sm_up_resp_wait), BNA_LLPORT_UP_RESP_WAIT},
 290         {BFA_SM(bna_llport_sm_down_resp_wait), BNA_LLPORT_DOWN_RESP_WAIT},
 291         {BFA_SM(bna_llport_sm_up), BNA_LLPORT_UP},
 292         {BFA_SM(bna_llport_sm_last_resp_wait), BNA_LLPORT_LAST_RESP_WAIT}
 293 };
 294
 295 static void
 296 bna_llport_sm_stopped_entry(struct bna_llport *llport)
 297 {
 298         llport->bna->port.link_cbfn((llport)->bna->bnad, BNA_LINK_DOWN);
 299         call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
 300 }
 301
 302 static void
 303 bna_llport_sm_stopped(struct bna_llport *llport,
 304                         enum bna_llport_event event)
 305 {
 306         switch (event) {
 307         case LLPORT_E_START:
 308                 bfa_fsm_set_state(llport, bna_llport_sm_down);
 309                 break;
 310
 311         case LLPORT_E_STOP:
 312                 call_llport_stop_cbfn(llport, BNA_CB_SUCCESS);
 313                 break;
 314
 315         case LLPORT_E_FAIL:
 316                 break;
 317
 318         case LLPORT_E_DOWN:
 319                 /* This event is received due to Rx objects failing */
 320                 /* No-op */
 321                 break;
 322
 323         case LLPORT_E_FWRESP_UP:
 324         case LLPORT_E_FWRESP_DOWN:
 325                 /**
 326                  * These events are received due to flushing of mbox when
 327                  * device fails
 328                  */
 329                 /* No-op */
 330                 break;
 331
 332         default:
 333                 bfa_sm_fault(llport->bna, event);
 334         }
 335 }
 336
 337 static void
 338 bna_llport_sm_down_entry(struct bna_llport *llport)
 339 {
 340         bnad_cb_port_link_status((llport)->bna->bnad, BNA_LINK_DOWN);
 341 }
 342
 343 static void
 344 bna_llport_sm_down(struct bna_llport *llport,
 345                         enum bna_llport_event event)
 346 {
 347         switch (event) {
 348         case LLPORT_E_STOP:
 349                 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
 350                 break;
 351
 352         case LLPORT_E_FAIL:
 353                 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
 354                 break;
 355
 356         case LLPORT_E_UP:
 357                 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
 358                 bna_fw_llport_up(llport);
 359                 break;
 360
 361         default:
 362                 bfa_sm_fault(llport->bna, event);
 363         }
 364 }
 365
 366 static void
 367 bna_llport_sm_up_resp_wait_entry(struct bna_llport *llport)
 368 {
 369         /**
 370          * NOTE: Do not call bna_fw_llport_up() here. That will over step
 371          * mbox due to down_resp_wait -> up_resp_wait transition on event
 372          * LLPORT_E_UP
 373          */
 374 }
 375
 376 static void
 377 bna_llport_sm_up_resp_wait(struct bna_llport *llport,
 378                         enum bna_llport_event event)
 379 {
 380         switch (event) {
 381         case LLPORT_E_STOP:
 382                 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
 383                 break;
 384
 385         case LLPORT_E_FAIL:
 386                 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
 387                 break;
 388
 389         case LLPORT_E_DOWN:
 390                 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
 391                 break;
 392
 393         case LLPORT_E_FWRESP_UP:
 394                 bfa_fsm_set_state(llport, bna_llport_sm_up);
 395                 break;
 396
 397         case LLPORT_E_FWRESP_DOWN:
 398                 /* down_resp_wait -> up_resp_wait transition on LLPORT_E_UP */
 399                 bna_fw_llport_up(llport);
 400                 break;
 401
 402         default:
 403                 bfa_sm_fault(llport->bna, event);
 404         }
 405 }
 406
 407 static void
 408 bna_llport_sm_down_resp_wait_entry(struct bna_llport *llport)
 409 {
 410         /**
 411          * NOTE: Do not call bna_fw_llport_down() here. That will over step
 412          * mbox due to up_resp_wait -> down_resp_wait transition on event
 413          * LLPORT_E_DOWN
 414          */
 415 }
 416
 417 static void
 418 bna_llport_sm_down_resp_wait(struct bna_llport *llport,
 419                         enum bna_llport_event event)
 420 {
 421         switch (event) {
 422         case LLPORT_E_STOP:
 423                 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
 424                 break;
 425
 426         case LLPORT_E_FAIL:
 427                 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
 428                 break;
 429
 430         case LLPORT_E_UP:
 431                 bfa_fsm_set_state(llport, bna_llport_sm_up_resp_wait);
 432                 break;
 433
 434         case LLPORT_E_FWRESP_UP:
 435                 /* up_resp_wait->down_resp_wait transition on LLPORT_E_DOWN */
 436                 bna_fw_llport_down(llport);
 437                 break;
 438
 439         case LLPORT_E_FWRESP_DOWN:
 440                 bfa_fsm_set_state(llport, bna_llport_sm_down);
 441                 break;
 442
 443         default:
 444                 bfa_sm_fault(llport->bna, event);
 445         }
 446 }
 447
 448 static void
 449 bna_llport_sm_up_entry(struct bna_llport *llport)
 450 {
 451 }
 452
 453 static void
 454 bna_llport_sm_up(struct bna_llport *llport,
 455                         enum bna_llport_event event)
 456 {
 457         switch (event) {
 458         case LLPORT_E_STOP:
 459                 bfa_fsm_set_state(llport, bna_llport_sm_last_resp_wait);
 460                 bna_fw_llport_down(llport);
 461                 break;
 462
 463         case LLPORT_E_FAIL:
 464                 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
 465                 break;
 466
 467         case LLPORT_E_DOWN:
 468                 bfa_fsm_set_state(llport, bna_llport_sm_down_resp_wait);
 469                 bna_fw_llport_down(llport);
 470                 break;
 471
 472         default:
 473                 bfa_sm_fault(llport->bna, event);
 474         }
 475 }
 476
 477 static void
 478 bna_llport_sm_last_resp_wait_entry(struct bna_llport *llport)
 479 {
 480 }
 481
 482 static void
 483 bna_llport_sm_last_resp_wait(struct bna_llport *llport,
 484                         enum bna_llport_event event)
 485 {
 486         switch (event) {
 487         case LLPORT_E_FAIL:
 488                 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
 489                 break;
 490
 491         case LLPORT_E_DOWN:
 492                 /**
 493                  * This event is received due to Rx objects stopping in
 494                  * parallel to llport
 495                  */
 496                 /* No-op */
 497                 break;
 498
 499         case LLPORT_E_FWRESP_UP:
 500                 /* up_resp_wait->last_resp_wait transition on LLPORT_T_STOP */
 501                 bna_fw_llport_down(llport);
 502                 break;
 503
 504         case LLPORT_E_FWRESP_DOWN:
 505                 bfa_fsm_set_state(llport, bna_llport_sm_stopped);
 506                 break;
 507
 508         default:
 509                 bfa_sm_fault(llport->bna, event);
 510         }
 511 }
 512
 513 static void
 514 bna_fw_llport_admin_up(struct bna_llport *llport)
 515 {
 516         struct bfi_ll_port_admin_req ll_req;
 517
 518         memset(&ll_req, 0, sizeof(ll_req));
 519         ll_req.mh.msg_class = BFI_MC_LL;
 520         ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
 521         ll_req.mh.mtag.h2i.lpu_id = 0;
 522
 523         ll_req.up = BNA_STATUS_T_ENABLED;
 524
 525         bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
 526                         bna_fw_cb_llport_up, llport);
 527
 528         bna_mbox_send(llport->bna, &llport->mbox_qe);
 529 }
 530
 531 static void
 532 bna_fw_llport_up(struct bna_llport *llport)
 533 {
 534         if (llport->type == BNA_PORT_T_REGULAR)
 535                 bna_fw_llport_admin_up(llport);
 536 }
 537
 538 static void
 539 bna_fw_cb_llport_up(void *arg, int status)
 540 {
 541         struct bna_llport *llport = (struct bna_llport *)arg;
 542
 543         bfa_q_qe_init(&llport->mbox_qe.qe);
 544         bfa_fsm_send_event(llport, LLPORT_E_FWRESP_UP);
 545 }
 546
 547 static void
 548 bna_fw_llport_admin_down(struct bna_llport *llport)
 549 {
 550         struct bfi_ll_port_admin_req ll_req;
 551
 552         memset(&ll_req, 0, sizeof(ll_req));
 553         ll_req.mh.msg_class = BFI_MC_LL;
 554         ll_req.mh.msg_id = BFI_LL_H2I_PORT_ADMIN_REQ;
 555         ll_req.mh.mtag.h2i.lpu_id = 0;
 556
 557         ll_req.up = BNA_STATUS_T_DISABLED;
 558
 559         bna_mbox_qe_fill(&llport->mbox_qe, &ll_req, sizeof(ll_req),
 560                         bna_fw_cb_llport_down, llport);
 561
 562         bna_mbox_send(llport->bna, &llport->mbox_qe);
 563 }
 564
 565 static void
 566 bna_fw_llport_down(struct bna_llport *llport)
 567 {
 568         if (llport->type == BNA_PORT_T_REGULAR)
 569                 bna_fw_llport_admin_down(llport);
 570 }
 571
 572 static void
 573 bna_fw_cb_llport_down(void *arg, int status)
 574 {
 575         struct bna_llport *llport = (struct bna_llport *)arg;
 576
 577         bfa_q_qe_init(&llport->mbox_qe.qe);
 578         bfa_fsm_send_event(llport, LLPORT_E_FWRESP_DOWN);
 579 }
 580
 581 static void
 582 bna_port_cb_llport_stopped(struct bna_port *port,
 583                                 enum bna_cb_status status)
 584 {
 585         bfa_wc_down(&port->chld_stop_wc);
 586 }
 587
 588 static void
 589 bna_llport_init(struct bna_llport *llport, struct bna *bna)
 590 {
 591         llport->flags |= BNA_LLPORT_F_ENABLED;
 592         llport->type = BNA_PORT_T_REGULAR;
 593         llport->bna = bna;
 594
 595         llport->link_status = BNA_LINK_DOWN;
 596
 597         llport->admin_up_count = 0;
 598
 599         llport->stop_cbfn = NULL;
 600
 601         bfa_q_qe_init(&llport->mbox_qe.qe);
 602
 603         bfa_fsm_set_state(llport, bna_llport_sm_stopped);
 604 }
 605
 606 static void
 607 bna_llport_uninit(struct bna_llport *llport)
 608 {
 609         llport->flags &= ~BNA_LLPORT_F_ENABLED;
 610
 611         llport->bna = NULL;
 612 }
 613
 614 static void
 615 bna_llport_start(struct bna_llport *llport)
 616 {
 617         bfa_fsm_send_event(llport, LLPORT_E_START);
 618 }
 619
 620 static void
 621 bna_llport_stop(struct bna_llport *llport)
 622 {
 623         llport->stop_cbfn = bna_port_cb_llport_stopped;
 624
 625         bfa_fsm_send_event(llport, LLPORT_E_STOP);
 626 }
 627
 628 static void
 629 bna_llport_fail(struct bna_llport *llport)
 630 {
 631         bfa_fsm_send_event(llport, LLPORT_E_FAIL);
 632 }
 633
 634 static int
 635 bna_llport_state_get(struct bna_llport *llport)
 636 {
 637         return bfa_sm_to_state(llport_sm_table, llport->fsm);
 638 }
 639
 640 void
 641 bna_llport_admin_up(struct bna_llport *llport)
 642 {
 643         llport->admin_up_count++;
 644
 645         if (llport->admin_up_count == 1) {
 646                 llport->flags |= BNA_LLPORT_F_RX_ENABLED;
 647                 if (llport->flags & BNA_LLPORT_F_ENABLED)
 648                         bfa_fsm_send_event(llport, LLPORT_E_UP);
 649         }
 650 }
 651
 652 void
 653 bna_llport_admin_down(struct bna_llport *llport)
 654 {
 655         llport->admin_up_count--;
 656
 657         if (llport->admin_up_count == 0) {
 658                 llport->flags &= ~BNA_LLPORT_F_RX_ENABLED;
 659                 if (llport->flags & BNA_LLPORT_F_ENABLED)
 660                         bfa_fsm_send_event(llport, LLPORT_E_DOWN);
 661         }
 662 }
 663
 664 /**
 665  * PORT
 666  */
 667 #define bna_port_chld_start(port)\
 668 do {\
 669         enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
 670                                         BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
 671         enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
 672                                         BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
 673         bna_llport_start(&(port)->llport);\
 674         bna_tx_mod_start(&(port)->bna->tx_mod, tx_type);\
 675         bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
 676 } while (0)
 677
 678 #define bna_port_chld_stop(port)\
 679 do {\
 680         enum bna_tx_type tx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
 681                                         BNA_TX_T_REGULAR : BNA_TX_T_LOOPBACK;\
 682         enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
 683                                         BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
 684         bfa_wc_up(&(port)->chld_stop_wc);\
 685         bfa_wc_up(&(port)->chld_stop_wc);\
 686         bfa_wc_up(&(port)->chld_stop_wc);\
 687         bna_llport_stop(&(port)->llport);\
 688         bna_tx_mod_stop(&(port)->bna->tx_mod, tx_type);\
 689         bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
 690 } while (0)
 691
 692 #define bna_port_chld_fail(port)\
 693 do {\
 694         bna_llport_fail(&(port)->llport);\
 695         bna_tx_mod_fail(&(port)->bna->tx_mod);\
 696         bna_rx_mod_fail(&(port)->bna->rx_mod);\
 697 } while (0)
 698
 699 #define bna_port_rx_start(port)\
 700 do {\
 701         enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
 702                                         BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
 703         bna_rx_mod_start(&(port)->bna->rx_mod, rx_type);\
 704 } while (0)
 705
 706 #define bna_port_rx_stop(port)\
 707 do {\
 708         enum bna_rx_type rx_type = ((port)->type == BNA_PORT_T_REGULAR) ?\
 709                                         BNA_RX_T_REGULAR : BNA_RX_T_LOOPBACK;\
 710         bfa_wc_up(&(port)->chld_stop_wc);\
 711         bna_rx_mod_stop(&(port)->bna->rx_mod, rx_type);\
 712 } while (0)
 713
 714 #define call_port_stop_cbfn(port, status)\
 715 do {\
 716         if ((port)->stop_cbfn)\
 717                 (port)->stop_cbfn((port)->stop_cbarg, status);\
 718         (port)->stop_cbfn = NULL;\
 719         (port)->stop_cbarg = NULL;\
 720 } while (0)
 721
 722 #define call_port_pause_cbfn(port, status)\
 723 do {\
 724         if ((port)->pause_cbfn)\
 725                 (port)->pause_cbfn((port)->bna->bnad, status);\
 726         (port)->pause_cbfn = NULL;\
 727 } while (0)
 728
 729 #define call_port_mtu_cbfn(port, status)\
 730 do {\
 731         if ((port)->mtu_cbfn)\
 732                 (port)->mtu_cbfn((port)->bna->bnad, status);\
 733         (port)->mtu_cbfn = NULL;\
 734 } while (0)
 735
 736 static void bna_fw_pause_set(struct bna_port *port);
 737 static void bna_fw_cb_pause_set(void *arg, int status);
 738 static void bna_fw_mtu_set(struct bna_port *port);
 739 static void bna_fw_cb_mtu_set(void *arg, int status);
 740
 741 enum bna_port_event {
 742         PORT_E_START                    = 1,
 743         PORT_E_STOP                     = 2,
 744         PORT_E_FAIL                     = 3,
 745         PORT_E_PAUSE_CFG                = 4,
 746         PORT_E_MTU_CFG                  = 5,
 747         PORT_E_CHLD_STOPPED             = 6,
 748         PORT_E_FWRESP_PAUSE             = 7,
 749         PORT_E_FWRESP_MTU               = 8
 750 };
 751
 752 enum bna_port_state {
 753         BNA_PORT_STOPPED                = 1,
 754         BNA_PORT_MTU_INIT_WAIT          = 2,
 755         BNA_PORT_PAUSE_INIT_WAIT        = 3,
 756         BNA_PORT_LAST_RESP_WAIT         = 4,
 757         BNA_PORT_STARTED                = 5,
 758         BNA_PORT_PAUSE_CFG_WAIT         = 6,
 759         BNA_PORT_RX_STOP_WAIT           = 7,
 760         BNA_PORT_MTU_CFG_WAIT           = 8,
 761         BNA_PORT_CHLD_STOP_WAIT         = 9
 762 };
 763
 764 bfa_fsm_state_decl(bna_port, stopped, struct bna_port,
 765                         enum bna_port_event);
 766 bfa_fsm_state_decl(bna_port, mtu_init_wait, struct bna_port,
 767                         enum bna_port_event);
 768 bfa_fsm_state_decl(bna_port, pause_init_wait, struct bna_port,
 769                         enum bna_port_event);
 770 bfa_fsm_state_decl(bna_port, last_resp_wait, struct bna_port,
 771                         enum bna_port_event);
 772 bfa_fsm_state_decl(bna_port, started, struct bna_port,
 773                         enum bna_port_event);
 774 bfa_fsm_state_decl(bna_port, pause_cfg_wait, struct bna_port,
 775                         enum bna_port_event);
 776 bfa_fsm_state_decl(bna_port, rx_stop_wait, struct bna_port,
 777                         enum bna_port_event);
 778 bfa_fsm_state_decl(bna_port, mtu_cfg_wait, struct bna_port,
 779                         enum bna_port_event);
 780 bfa_fsm_state_decl(bna_port, chld_stop_wait, struct bna_port,
 781                         enum bna_port_event);
 782
 783 static struct bfa_sm_table port_sm_table[] = {
 784         {BFA_SM(bna_port_sm_stopped), BNA_PORT_STOPPED},
 785         {BFA_SM(bna_port_sm_mtu_init_wait), BNA_PORT_MTU_INIT_WAIT},
 786         {BFA_SM(bna_port_sm_pause_init_wait), BNA_PORT_PAUSE_INIT_WAIT},
 787         {BFA_SM(bna_port_sm_last_resp_wait), BNA_PORT_LAST_RESP_WAIT},
 788         {BFA_SM(bna_port_sm_started), BNA_PORT_STARTED},
 789         {BFA_SM(bna_port_sm_pause_cfg_wait), BNA_PORT_PAUSE_CFG_WAIT},
 790         {BFA_SM(bna_port_sm_rx_stop_wait), BNA_PORT_RX_STOP_WAIT},
 791         {BFA_SM(bna_port_sm_mtu_cfg_wait), BNA_PORT_MTU_CFG_WAIT},
 792         {BFA_SM(bna_port_sm_chld_stop_wait), BNA_PORT_CHLD_STOP_WAIT}
 793 };
 794
 795 static void
 796 bna_port_sm_stopped_entry(struct bna_port *port)
 797 {
 798         call_port_pause_cbfn(port, BNA_CB_SUCCESS);
 799         call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
 800         call_port_stop_cbfn(port, BNA_CB_SUCCESS);
 801 }
 802
 803 static void
 804 bna_port_sm_stopped(struct bna_port *port, enum bna_port_event event)
 805 {
 806         switch (event) {
 807         case PORT_E_START:
 808                 bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
 809                 break;
 810
 811         case PORT_E_STOP:
 812                 call_port_stop_cbfn(port, BNA_CB_SUCCESS);
 813                 break;
 814
 815         case PORT_E_FAIL:
 816                 /* No-op */
 817                 break;
 818
 819         case PORT_E_PAUSE_CFG:
 820                 call_port_pause_cbfn(port, BNA_CB_SUCCESS);
 821                 break;
 822
 823         case PORT_E_MTU_CFG:
 824                 call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
 825                 break;
 826
 827         case PORT_E_CHLD_STOPPED:
 828                 /**
 829                  * This event is received due to LLPort, Tx and Rx objects
 830                  * failing
 831                  */
 832                 /* No-op */
 833                 break;
 834
 835         case PORT_E_FWRESP_PAUSE:
 836         case PORT_E_FWRESP_MTU:
 837                 /**
 838                  * These events are received due to flushing of mbox when
 839                  * device fails
 840                  */
 841                 /* No-op */
 842                 break;
 843
 844         default:
 845                 bfa_sm_fault(port->bna, event);
 846         }
 847 }
 848
 849 static void
 850 bna_port_sm_mtu_init_wait_entry(struct bna_port *port)
 851 {
 852         bna_fw_mtu_set(port);
 853 }
 854
 855 static void
 856 bna_port_sm_mtu_init_wait(struct bna_port *port, enum bna_port_event event)
 857 {
 858         switch (event) {
 859         case PORT_E_STOP:
 860                 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
 861                 break;
 862
 863         case PORT_E_FAIL:
 864                 bfa_fsm_set_state(port, bna_port_sm_stopped);
 865                 break;
 866
 867         case PORT_E_PAUSE_CFG:
 868                 /* No-op */
 869                 break;
 870
 871         case PORT_E_MTU_CFG:
 872                 port->flags |= BNA_PORT_F_MTU_CHANGED;
 873                 break;
 874
 875         case PORT_E_FWRESP_MTU:
 876                 if (port->flags & BNA_PORT_F_MTU_CHANGED) {
 877                         port->flags &= ~BNA_PORT_F_MTU_CHANGED;
 878                         bna_fw_mtu_set(port);
 879                 } else {
 880                         bfa_fsm_set_state(port, bna_port_sm_pause_init_wait);
 881                 }
 882                 break;
 883
 884         default:
 885                 bfa_sm_fault(port->bna, event);
 886         }
 887 }
 888
 889 static void
 890 bna_port_sm_pause_init_wait_entry(struct bna_port *port)
 891 {
 892         bna_fw_pause_set(port);
 893 }
 894
 895 static void
 896 bna_port_sm_pause_init_wait(struct bna_port *port,
 897                                 enum bna_port_event event)
 898 {
 899         switch (event) {
 900         case PORT_E_STOP:
 901                 bfa_fsm_set_state(port, bna_port_sm_last_resp_wait);
 902                 break;
 903
 904         case PORT_E_FAIL:
 905                 bfa_fsm_set_state(port, bna_port_sm_stopped);
 906                 break;
 907
 908         case PORT_E_PAUSE_CFG:
 909                 port->flags |= BNA_PORT_F_PAUSE_CHANGED;
 910                 break;
 911
 912         case PORT_E_MTU_CFG:
 913                 port->flags |= BNA_PORT_F_MTU_CHANGED;
 914                 break;
 915
 916         case PORT_E_FWRESP_PAUSE:
 917                 if (port->flags & BNA_PORT_F_PAUSE_CHANGED) {
 918                         port->flags &= ~BNA_PORT_F_PAUSE_CHANGED;
 919                         bna_fw_pause_set(port);
 920                 } else if (port->flags & BNA_PORT_F_MTU_CHANGED) {
 921                         port->flags &= ~BNA_PORT_F_MTU_CHANGED;
 922                         bfa_fsm_set_state(port, bna_port_sm_mtu_init_wait);
 923                 } else {
 924                         bfa_fsm_set_state(port, bna_port_sm_started);
 925                         bna_port_chld_start(port);
 926                 }
 927                 break;
 928
 929         default:
 930                 bfa_sm_fault(port->bna, event);
 931         }
 932 }
 933
 934 static void
 935 bna_port_sm_last_resp_wait_entry(struct bna_port *port)
 936 {
 937 }
 938
 939 static void
 940 bna_port_sm_last_resp_wait(struct bna_port *port,
 941                                 enum bna_port_event event)
 942 {
 943         switch (event) {
 944         case PORT_E_FAIL:
 945         case PORT_E_FWRESP_PAUSE:
 946         case PORT_E_FWRESP_MTU:
 947                 bfa_fsm_set_state(port, bna_port_sm_stopped);
 948                 break;
 949
 950         default:
 951                 bfa_sm_fault(port->bna, event);
 952         }
 953 }
 954
 955 static void
 956 bna_port_sm_started_entry(struct bna_port *port)
 957 {
 958         /**
 959          * NOTE: Do not call bna_port_chld_start() here, since it will be
 960          * inadvertently called during pause_cfg_wait->started transition
 961          * as well
 962          */
 963         call_port_pause_cbfn(port, BNA_CB_SUCCESS);
 964         call_port_mtu_cbfn(port, BNA_CB_SUCCESS);
 965 }
 966
 967 static void
 968 bna_port_sm_started(struct bna_port *port,
 969                         enum bna_port_event event)
 970 {
 971         switch (event) {
 972         case PORT_E_STOP:
 973                 bfa_fsm_set_state(port, bna_port_sm_chld_stop_wait);
 974                 break;
 975
 976         case PORT_E_FAIL:
 977                 bfa_fsm_set_state(port, bna_port_sm_stopped);
 978                 bna_port_chld_fail(port);
 979                 break;
 980
 981         case PORT_E_PAUSE_CFG:
 982                 bfa_fsm_set_state(port, bna_port_sm_pause_cfg_wait);
 983                 break;
 984
 985         case PORT_E_MTU_CFG:
 986                 bfa_fsm_set_state(port, bna_port_sm_rx_stop_wait);
 987                 break;
 988
 989         default:
 990                 bfa_sm_fault(port->bna, event);
 991         }
 992 }
 993
 994 static void
 995 bna_port_sm_pause_cfg_wait_entry(struct bna_port *port)
 996 {
 997         bna_fw_pause_set(port);
 998 }
 999
1000 static void
1001 bna_port_sm_pause_cfg_wait(struct bna_port *port,
1002                                 enum bna_port_event event)
1003 {
1004         switch (event) {
1005         case PORT_E_FAIL:
1006                 bfa_fsm_set_state(port, bna_port_sm_stopped);
1007                 bna_port_chld_fail(port);
1008                 break;
1009
1010         case PORT_E_FWRESP_PAUSE:
1011                 bfa_fsm_set_state(port, bna_port_sm_started);
1012                 break;
1013
1014         default:
1015                 bfa_sm_fault(port->bna, event);
1016         }
1017 }
1018
1019 static void
1020 bna_port_sm_rx_stop_wait_entry(struct bna_port *port)
1021 {
1022         bna_port_rx_stop(port);
1023 }
1024
1025 static void
1026 bna_port_sm_rx_stop_wait(struct bna_port *port,
1027                                 enum bna_port_event event)
1028 {
1029         switch (event) {
1030         case PORT_E_FAIL:
1031                 bfa_fsm_set_state(port, bna_port_sm_stopped);
1032                 bna_port_chld_fail(port);
1033                 break;
1034
1035         case PORT_E_CHLD_STOPPED:
1036                 bfa_fsm_set_state(port, bna_port_sm_mtu_cfg_wait);
1037                 break;
1038
1039         default:
1040                 bfa_sm_fault(port->bna, event);
1041         }
1042 }
1043
1044 static void
1045 bna_port_sm_mtu_cfg_wait_entry(struct bna_port *port)
1046 {
1047         bna_fw_mtu_set(port);
1048 }
1049
1050 static void
1051 bna_port_sm_mtu_cfg_wait(struct bna_port *port, enum bna_port_event event)
1052 {
1053         switch (event) {
1054         case PORT_E_FAIL:
1055                 bfa_fsm_set_state(port, bna_port_sm_stopped);
1056                 bna_port_chld_fail(port);
1057                 break;
1058
1059         case PORT_E_FWRESP_MTU:
1060                 bfa_fsm_set_state(port, bna_port_sm_started);
1061                 bna_port_rx_start(port);
1062                 break;
1063
1064         default:
1065                 bfa_sm_fault(port->bna, event);
1066         }
1067 }
1068
1069 static void
1070 bna_port_sm_chld_stop_wait_entry(struct bna_port *port)
1071 {
1072         bna_port_chld_stop(port);
1073 }
1074
1075 static void
1076 bna_port_sm_chld_stop_wait(struct bna_port *port,
1077                                 enum bna_port_event event)
1078 {
1079         switch (event) {
1080         case PORT_E_FAIL:
1081                 bfa_fsm_set_state(port, bna_port_sm_stopped);
1082                 bna_port_chld_fail(port);
1083                 break;
1084
1085         case PORT_E_CHLD_STOPPED:
1086                 bfa_fsm_set_state(port, bna_port_sm_stopped);
1087                 break;
1088
1089         default:
1090                 bfa_sm_fault(port->bna, event);
1091         }
1092 }
1093
1094 static void
1095 bna_fw_pause_set(struct bna_port *port)
1096 {
1097         struct bfi_ll_set_pause_req ll_req;
1098
1099         memset(&ll_req, 0, sizeof(ll_req));
1100         ll_req.mh.msg_class = BFI_MC_LL;
1101         ll_req.mh.msg_id = BFI_LL_H2I_SET_PAUSE_REQ;
1102         ll_req.mh.mtag.h2i.lpu_id = 0;
1103
1104         ll_req.tx_pause = port->pause_config.tx_pause;
1105         ll_req.rx_pause = port->pause_config.rx_pause;
1106
1107         bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1108                         bna_fw_cb_pause_set, port);
1109
1110         bna_mbox_send(port->bna, &port->mbox_qe);
1111 }
1112
1113 static void
1114 bna_fw_cb_pause_set(void *arg, int status)
1115 {
1116         struct bna_port *port = (struct bna_port *)arg;
1117
1118         bfa_q_qe_init(&port->mbox_qe.qe);
1119         bfa_fsm_send_event(port, PORT_E_FWRESP_PAUSE);
1120 }
1121
1122 void
1123 bna_fw_mtu_set(struct bna_port *port)
1124 {
1125         struct bfi_ll_mtu_info_req ll_req;
1126
1127         bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_MTU_INFO_REQ, 0);
1128         ll_req.mtu = htons((u16)port->mtu);
1129
1130         bna_mbox_qe_fill(&port->mbox_qe, &ll_req, sizeof(ll_req),
1131                                 bna_fw_cb_mtu_set, port);
1132         bna_mbox_send(port->bna, &port->mbox_qe);
1133 }
1134
1135 void
1136 bna_fw_cb_mtu_set(void *arg, int status)
1137 {
1138         struct bna_port *port = (struct bna_port *)arg;
1139
1140         bfa_q_qe_init(&port->mbox_qe.qe);
1141         bfa_fsm_send_event(port, PORT_E_FWRESP_MTU);
1142 }
1143
1144 static void
1145 bna_port_cb_chld_stopped(void *arg)
1146 {
1147         struct bna_port *port = (struct bna_port *)arg;
1148
1149         bfa_fsm_send_event(port, PORT_E_CHLD_STOPPED);
1150 }
1151
1152 static void
1153 bna_port_init(struct bna_port *port, struct bna *bna)
1154 {
1155         port->bna = bna;
1156         port->flags = 0;
1157         port->mtu = 0;
1158         port->type = BNA_PORT_T_REGULAR;
1159
1160         port->link_cbfn = bnad_cb_port_link_status;
1161
1162         port->chld_stop_wc.wc_resume = bna_port_cb_chld_stopped;
1163         port->chld_stop_wc.wc_cbarg = port;
1164         port->chld_stop_wc.wc_count = 0;
1165
1166         port->stop_cbfn = NULL;
1167         port->stop_cbarg = NULL;
1168
1169         port->pause_cbfn = NULL;
1170
1171         port->mtu_cbfn = NULL;
1172
1173         bfa_q_qe_init(&port->mbox_qe.qe);
1174
1175         bfa_fsm_set_state(port, bna_port_sm_stopped);
1176
1177         bna_llport_init(&port->llport, bna);
1178 }
1179
1180 static void
1181 bna_port_uninit(struct bna_port *port)
1182 {
1183         bna_llport_uninit(&port->llport);
1184
1185         port->flags = 0;
1186
1187         port->bna = NULL;
1188 }
1189
1190 static int
1191 bna_port_state_get(struct bna_port *port)
1192 {
1193         return bfa_sm_to_state(port_sm_table, port->fsm);
1194 }
1195
1196 static void
1197 bna_port_start(struct bna_port *port)
1198 {
1199         port->flags |= BNA_PORT_F_DEVICE_READY;
1200         if (port->flags & BNA_PORT_F_ENABLED)
1201                 bfa_fsm_send_event(port, PORT_E_START);
1202 }
1203
1204 static void
1205 bna_port_stop(struct bna_port *port)
1206 {
1207         port->stop_cbfn = bna_device_cb_port_stopped;
1208         port->stop_cbarg = &port->bna->device;
1209
1210         port->flags &= ~BNA_PORT_F_DEVICE_READY;
1211         bfa_fsm_send_event(port, PORT_E_STOP);
1212 }
1213
1214 static void
1215 bna_port_fail(struct bna_port *port)
1216 {
1217         port->flags &= ~BNA_PORT_F_DEVICE_READY;
1218         bfa_fsm_send_event(port, PORT_E_FAIL);
1219 }
1220
1221 void
1222 bna_port_cb_tx_stopped(struct bna_port *port, enum bna_cb_status status)
1223 {
1224         bfa_wc_down(&port->chld_stop_wc);
1225 }
1226
1227 void
1228 bna_port_cb_rx_stopped(struct bna_port *port, enum bna_cb_status status)
1229 {
1230         bfa_wc_down(&port->chld_stop_wc);
1231 }
1232
1233 int
1234 bna_port_mtu_get(struct bna_port *port)
1235 {
1236         return port->mtu;
1237 }
1238
1239 void
1240 bna_port_enable(struct bna_port *port)
1241 {
1242         if (port->fsm != (bfa_sm_t)bna_port_sm_stopped)
1243                 return;
1244
1245         port->flags |= BNA_PORT_F_ENABLED;
1246
1247         if (port->flags & BNA_PORT_F_DEVICE_READY)
1248                 bfa_fsm_send_event(port, PORT_E_START);
1249 }
1250
1251 void
1252 bna_port_disable(struct bna_port *port, enum bna_cleanup_type type,
1253                  void (*cbfn)(void *, enum bna_cb_status))
1254 {
1255         if (type == BNA_SOFT_CLEANUP) {
1256                 (*cbfn)(port->bna->bnad, BNA_CB_SUCCESS);
1257                 return;
1258         }
1259
1260         port->stop_cbfn = cbfn;
1261         port->stop_cbarg = port->bna->bnad;
1262
1263         port->flags &= ~BNA_PORT_F_ENABLED;
1264
1265         bfa_fsm_send_event(port, PORT_E_STOP);
1266 }
1267
1268 void
1269 bna_port_pause_config(struct bna_port *port,
1270                       struct bna_pause_config *pause_config,
1271                       void (*cbfn)(struct bnad *, enum bna_cb_status))
1272 {
1273         port->pause_config = *pause_config;
1274
1275         port->pause_cbfn = cbfn;
1276
1277         bfa_fsm_send_event(port, PORT_E_PAUSE_CFG);
1278 }
1279
1280 void
1281 bna_port_mtu_set(struct bna_port *port, int mtu,
1282                  void (*cbfn)(struct bnad *, enum bna_cb_status))
1283 {
1284         port->mtu = mtu;
1285
1286         port->mtu_cbfn = cbfn;
1287
1288         bfa_fsm_send_event(port, PORT_E_MTU_CFG);
1289 }
1290
1291 void
1292 bna_port_mac_get(struct bna_port *port, mac_t *mac)
1293 {
1294         *mac = bfa_nw_ioc_get_mac(&port->bna->device.ioc);
1295 }
1296
1297 /**
1298  * DEVICE
1299  */
1300 #define enable_mbox_intr(_device)\
1301 do {\
1302         u32 intr_status;\
1303         bna_intr_status_get((_device)->bna, intr_status);\
1304         bnad_cb_device_enable_mbox_intr((_device)->bna->bnad);\
1305         bna_mbox_intr_enable((_device)->bna);\
1306 } while (0)
1307
1308 #define disable_mbox_intr(_device)\
1309 do {\
1310         bna_mbox_intr_disable((_device)->bna);\
1311         bnad_cb_device_disable_mbox_intr((_device)->bna->bnad);\
1312 } while (0)
1313
1314 static const struct bna_chip_regs_offset reg_offset[] =
1315 {{HOST_PAGE_NUM_FN0, HOSTFN0_INT_STATUS,
1316         HOSTFN0_INT_MASK, HOST_MSIX_ERR_INDEX_FN0},
1317 {HOST_PAGE_NUM_FN1, HOSTFN1_INT_STATUS,
1318         HOSTFN1_INT_MASK, HOST_MSIX_ERR_INDEX_FN1},
1319 {HOST_PAGE_NUM_FN2, HOSTFN2_INT_STATUS,
1320         HOSTFN2_INT_MASK, HOST_MSIX_ERR_INDEX_FN2},
1321 {HOST_PAGE_NUM_FN3, HOSTFN3_INT_STATUS,
1322         HOSTFN3_INT_MASK, HOST_MSIX_ERR_INDEX_FN3},
1323 };
1324
1325 enum bna_device_event {
1326         DEVICE_E_ENABLE                 = 1,
1327         DEVICE_E_DISABLE                = 2,
1328         DEVICE_E_IOC_READY              = 3,
1329         DEVICE_E_IOC_FAILED             = 4,
1330         DEVICE_E_IOC_DISABLED           = 5,
1331         DEVICE_E_IOC_RESET              = 6,
1332         DEVICE_E_PORT_STOPPED           = 7,
1333 };
1334
1335 enum bna_device_state {
1336         BNA_DEVICE_STOPPED              = 1,
1337         BNA_DEVICE_IOC_READY_WAIT       = 2,
1338         BNA_DEVICE_READY                = 3,
1339         BNA_DEVICE_PORT_STOP_WAIT       = 4,
1340         BNA_DEVICE_IOC_DISABLE_WAIT     = 5,
1341         BNA_DEVICE_FAILED               = 6
1342 };
1343
1344 bfa_fsm_state_decl(bna_device, stopped, struct bna_device,
1345                         enum bna_device_event);
1346 bfa_fsm_state_decl(bna_device, ioc_ready_wait, struct bna_device,
1347                         enum bna_device_event);
1348 bfa_fsm_state_decl(bna_device, ready, struct bna_device,
1349                         enum bna_device_event);
1350 bfa_fsm_state_decl(bna_device, port_stop_wait, struct bna_device,
1351                         enum bna_device_event);
1352 bfa_fsm_state_decl(bna_device, ioc_disable_wait, struct bna_device,
1353                         enum bna_device_event);
1354 bfa_fsm_state_decl(bna_device, failed, struct bna_device,
1355                         enum bna_device_event);
1356
1357 static struct bfa_sm_table device_sm_table[] = {
1358         {BFA_SM(bna_device_sm_stopped), BNA_DEVICE_STOPPED},
1359         {BFA_SM(bna_device_sm_ioc_ready_wait), BNA_DEVICE_IOC_READY_WAIT},
1360         {BFA_SM(bna_device_sm_ready), BNA_DEVICE_READY},
1361         {BFA_SM(bna_device_sm_port_stop_wait), BNA_DEVICE_PORT_STOP_WAIT},
1362         {BFA_SM(bna_device_sm_ioc_disable_wait), BNA_DEVICE_IOC_DISABLE_WAIT},
1363         {BFA_SM(bna_device_sm_failed), BNA_DEVICE_FAILED},
1364 };
1365
1366 static void
1367 bna_device_sm_stopped_entry(struct bna_device *device)
1368 {
1369         if (device->stop_cbfn)
1370                 device->stop_cbfn(device->stop_cbarg, BNA_CB_SUCCESS);
1371
1372         device->stop_cbfn = NULL;
1373         device->stop_cbarg = NULL;
1374 }
1375
1376 static void
1377 bna_device_sm_stopped(struct bna_device *device,
1378                         enum bna_device_event event)
1379 {
1380         switch (event) {
1381         case DEVICE_E_ENABLE:
1382                 if (device->intr_type == BNA_INTR_T_MSIX)
1383                         bna_mbox_msix_idx_set(device);
1384                 bfa_nw_ioc_enable(&device->ioc);
1385                 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1386                 break;
1387
1388         case DEVICE_E_DISABLE:
1389                 bfa_fsm_set_state(device, bna_device_sm_stopped);
1390                 break;
1391
1392         case DEVICE_E_IOC_RESET:
1393                 enable_mbox_intr(device);
1394                 break;
1395
1396         case DEVICE_E_IOC_FAILED:
1397                 bfa_fsm_set_state(device, bna_device_sm_failed);
1398                 break;
1399
1400         default:
1401                 bfa_sm_fault(device->bna, event);
1402         }
1403 }
1404
1405 static void
1406 bna_device_sm_ioc_ready_wait_entry(struct bna_device *device)
1407 {
1408         /**
1409          * Do not call bfa_ioc_enable() here. It must be called in the
1410          * previous state due to failed -> ioc_ready_wait transition.
1411          */
1412 }
1413
1414 static void
1415 bna_device_sm_ioc_ready_wait(struct bna_device *device,
1416                                 enum bna_device_event event)
1417 {
1418         switch (event) {
1419         case DEVICE_E_DISABLE:
1420                 if (device->ready_cbfn)
1421                         device->ready_cbfn(device->ready_cbarg,
1422                                                 BNA_CB_INTERRUPT);
1423                 device->ready_cbfn = NULL;
1424                 device->ready_cbarg = NULL;
1425                 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1426                 break;
1427
1428         case DEVICE_E_IOC_READY:
1429                 bfa_fsm_set_state(device, bna_device_sm_ready);
1430                 break;
1431
1432         case DEVICE_E_IOC_FAILED:
1433                 bfa_fsm_set_state(device, bna_device_sm_failed);
1434                 break;
1435
1436         case DEVICE_E_IOC_RESET:
1437                 enable_mbox_intr(device);
1438                 break;
1439
1440         default:
1441                 bfa_sm_fault(device->bna, event);
1442         }
1443 }
1444
1445 static void
1446 bna_device_sm_ready_entry(struct bna_device *device)
1447 {
1448         bna_mbox_mod_start(&device->bna->mbox_mod);
1449         bna_port_start(&device->bna->port);
1450
1451         if (device->ready_cbfn)
1452                 device->ready_cbfn(device->ready_cbarg,
1453                                         BNA_CB_SUCCESS);
1454         device->ready_cbfn = NULL;
1455         device->ready_cbarg = NULL;
1456 }
1457
1458 static void
1459 bna_device_sm_ready(struct bna_device *device, enum bna_device_event event)
1460 {
1461         switch (event) {
1462         case DEVICE_E_DISABLE:
1463                 bfa_fsm_set_state(device, bna_device_sm_port_stop_wait);
1464                 break;
1465
1466         case DEVICE_E_IOC_FAILED:
1467                 bfa_fsm_set_state(device, bna_device_sm_failed);
1468                 break;
1469
1470         default:
1471                 bfa_sm_fault(device->bna, event);
1472         }
1473 }
1474
1475 static void
1476 bna_device_sm_port_stop_wait_entry(struct bna_device *device)
1477 {
1478         bna_port_stop(&device->bna->port);
1479 }
1480
1481 static void
1482 bna_device_sm_port_stop_wait(struct bna_device *device,
1483                                 enum bna_device_event event)
1484 {
1485         switch (event) {
1486         case DEVICE_E_PORT_STOPPED:
1487                 bna_mbox_mod_stop(&device->bna->mbox_mod);
1488                 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1489                 break;
1490
1491         case DEVICE_E_IOC_FAILED:
1492                 disable_mbox_intr(device);
1493                 bna_port_fail(&device->bna->port);
1494                 break;
1495
1496         default:
1497                 bfa_sm_fault(device->bna, event);
1498         }
1499 }
1500
1501 static void
1502 bna_device_sm_ioc_disable_wait_entry(struct bna_device *device)
1503 {
1504         bfa_nw_ioc_disable(&device->ioc);
1505 }
1506
1507 static void
1508 bna_device_sm_ioc_disable_wait(struct bna_device *device,
1509                                 enum bna_device_event event)
1510 {
1511         switch (event) {
1512         case DEVICE_E_IOC_DISABLED:
1513                 disable_mbox_intr(device);
1514                 bfa_fsm_set_state(device, bna_device_sm_stopped);
1515                 break;
1516
1517         default:
1518                 bfa_sm_fault(device->bna, event);
1519         }
1520 }
1521
1522 static void
1523 bna_device_sm_failed_entry(struct bna_device *device)
1524 {
1525         disable_mbox_intr(device);
1526         bna_port_fail(&device->bna->port);
1527         bna_mbox_mod_stop(&device->bna->mbox_mod);
1528
1529         if (device->ready_cbfn)
1530                 device->ready_cbfn(device->ready_cbarg,
1531                                         BNA_CB_FAIL);
1532         device->ready_cbfn = NULL;
1533         device->ready_cbarg = NULL;
1534 }
1535
1536 static void
1537 bna_device_sm_failed(struct bna_device *device,
1538                         enum bna_device_event event)
1539 {
1540         switch (event) {
1541         case DEVICE_E_DISABLE:
1542                 bfa_fsm_set_state(device, bna_device_sm_ioc_disable_wait);
1543                 break;
1544
1545         case DEVICE_E_IOC_RESET:
1546                 enable_mbox_intr(device);
1547                 bfa_fsm_set_state(device, bna_device_sm_ioc_ready_wait);
1548                 break;
1549
1550         default:
1551                 bfa_sm_fault(device->bna, event);
1552         }
1553 }
1554
1555 /* IOC callback functions */
1556
1557 static void
1558 bna_device_cb_iocll_ready(void *dev, enum bfa_status error)
1559 {
1560         struct bna_device *device = (struct bna_device *)dev;
1561
1562         if (error)
1563                 bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1564         else
1565                 bfa_fsm_send_event(device, DEVICE_E_IOC_READY);
1566 }
1567
1568 static void
1569 bna_device_cb_iocll_disabled(void *dev)
1570 {
1571         struct bna_device *device = (struct bna_device *)dev;
1572
1573         bfa_fsm_send_event(device, DEVICE_E_IOC_DISABLED);
1574 }
1575
1576 static void
1577 bna_device_cb_iocll_failed(void *dev)
1578 {
1579         struct bna_device *device = (struct bna_device *)dev;
1580
1581         bfa_fsm_send_event(device, DEVICE_E_IOC_FAILED);
1582 }
1583
1584 static void
1585 bna_device_cb_iocll_reset(void *dev)
1586 {
1587         struct bna_device *device = (struct bna_device *)dev;
1588
1589         bfa_fsm_send_event(device, DEVICE_E_IOC_RESET);
1590 }
1591
1592 static struct bfa_ioc_cbfn bfa_iocll_cbfn = {
1593         bna_device_cb_iocll_ready,
1594         bna_device_cb_iocll_disabled,
1595         bna_device_cb_iocll_failed,
1596         bna_device_cb_iocll_reset
1597 };
1598
1599 /* device */
1600 static void
1601 bna_adv_device_init(struct bna_device *device, struct bna *bna,
1602                 struct bna_res_info *res_info)
1603 {
1604         u8 *kva;
1605         u64 dma;
1606
1607         device->bna = bna;
1608
1609         kva = res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mdl[0].kva;
1610
1611         /**
1612          * Attach common modules (Diag, SFP, CEE, Port) and claim respective
1613          * DMA memory.
1614          */
1615         BNA_GET_DMA_ADDR(
1616                 &res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].dma, dma);
1617         kva = res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mdl[0].kva;
1618
1619         bfa_nw_cee_attach(&bna->cee, &device->ioc, bna);
1620         bfa_nw_cee_mem_claim(&bna->cee, kva, dma);
1621         kva += bfa_nw_cee_meminfo();
1622         dma += bfa_nw_cee_meminfo();
1623
1624 }
1625
1626 static void
1627 bna_device_init(struct bna_device *device, struct bna *bna,
1628                 struct bna_res_info *res_info)
1629 {
1630         u64 dma;
1631
1632         device->bna = bna;
1633
1634         /**
1635          * Attach IOC and claim:
1636          *      1. DMA memory for IOC attributes
1637          *      2. Kernel memory for FW trace
1638          */
1639         bfa_nw_ioc_attach(&device->ioc, device, &bfa_iocll_cbfn);
1640         bfa_nw_ioc_pci_init(&device->ioc, &bna->pcidev, BFI_MC_LL);
1641
1642         BNA_GET_DMA_ADDR(
1643                 &res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].dma, dma);
1644         bfa_nw_ioc_mem_claim(&device->ioc,
1645                 res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mdl[0].kva,
1646                           dma);
1647
1648         bna_adv_device_init(device, bna, res_info);
1649         /*
1650          * Initialize mbox_mod only after IOC, so that mbox handler
1651          * registration goes through
1652          */
1653         device->intr_type =
1654                 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type;
1655         device->vector =
1656                 res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.idl[0].vector;
1657         bna_mbox_mod_init(&bna->mbox_mod, bna);
1658
1659         device->ready_cbfn = device->stop_cbfn = NULL;
1660         device->ready_cbarg = device->stop_cbarg = NULL;
1661
1662         bfa_fsm_set_state(device, bna_device_sm_stopped);
1663 }
1664
1665 static void
1666 bna_device_uninit(struct bna_device *device)
1667 {
1668         bna_mbox_mod_uninit(&device->bna->mbox_mod);
1669
1670         bfa_nw_ioc_detach(&device->ioc);
1671
1672         device->bna = NULL;
1673 }
1674
1675 static void
1676 bna_device_cb_port_stopped(void *arg, enum bna_cb_status status)
1677 {
1678         struct bna_device *device = (struct bna_device *)arg;
1679
1680         bfa_fsm_send_event(device, DEVICE_E_PORT_STOPPED);
1681 }
1682
1683 static int
1684 bna_device_status_get(struct bna_device *device)
1685 {
1686         return device->fsm == (bfa_fsm_t)bna_device_sm_ready;
1687 }
1688
1689 void
1690 bna_device_enable(struct bna_device *device)
1691 {
1692         if (device->fsm != (bfa_fsm_t)bna_device_sm_stopped) {
1693                 bnad_cb_device_enabled(device->bna->bnad, BNA_CB_BUSY);
1694                 return;
1695         }
1696
1697         device->ready_cbfn = bnad_cb_device_enabled;
1698         device->ready_cbarg = device->bna->bnad;
1699
1700         bfa_fsm_send_event(device, DEVICE_E_ENABLE);
1701 }
1702
1703 void
1704 bna_device_disable(struct bna_device *device, enum bna_cleanup_type type)
1705 {
1706         if (type == BNA_SOFT_CLEANUP) {
1707                 bnad_cb_device_disabled(device->bna->bnad, BNA_CB_SUCCESS);
1708                 return;
1709         }
1710
1711         device->stop_cbfn = bnad_cb_device_disabled;
1712         device->stop_cbarg = device->bna->bnad;
1713
1714         bfa_fsm_send_event(device, DEVICE_E_DISABLE);
1715 }
1716
1717 static int
1718 bna_device_state_get(struct bna_device *device)
1719 {
1720         return bfa_sm_to_state(device_sm_table, device->fsm);
1721 }
1722
1723 const u32 bna_napi_dim_vector[BNA_LOAD_T_MAX][BNA_BIAS_T_MAX] = {
1724         {12, 12},
1725         {6, 10},
1726         {5, 10},
1727         {4, 8},
1728         {3, 6},
1729         {3, 6},
1730         {2, 4},
1731         {1, 2},
1732 };
1733
1734 /* utils */
1735
1736 static void
1737 bna_adv_res_req(struct bna_res_info *res_info)
1738 {
1739         /* DMA memory for COMMON_MODULE */
1740         res_info[BNA_RES_MEM_T_COM].res_type = BNA_RES_T_MEM;
1741         res_info[BNA_RES_MEM_T_COM].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1742         res_info[BNA_RES_MEM_T_COM].res_u.mem_info.num = 1;
1743         res_info[BNA_RES_MEM_T_COM].res_u.mem_info.len = ALIGN(
1744                                 bfa_nw_cee_meminfo(), PAGE_SIZE);
1745
1746         /* Virtual memory for retreiving fw_trc */
1747         res_info[BNA_RES_MEM_T_FWTRC].res_type = BNA_RES_T_MEM;
1748         res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1749         res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.num = 0;
1750         res_info[BNA_RES_MEM_T_FWTRC].res_u.mem_info.len = 0;
1751
1752         /* DMA memory for retreiving stats */
1753         res_info[BNA_RES_MEM_T_STATS].res_type = BNA_RES_T_MEM;
1754         res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
1755         res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.num = 1;
1756         res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.len =
1757                                 ALIGN(BFI_HW_STATS_SIZE, PAGE_SIZE);
1758
1759         /* Virtual memory for soft stats */
1760         res_info[BNA_RES_MEM_T_SWSTATS].res_type = BNA_RES_T_MEM;
1761         res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mem_type = BNA_MEM_T_KVA;
1762         res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.num = 1;
1763         res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.len =
1764                                 sizeof(struct bna_sw_stats);
1765 }
1766
1767 static void
1768 bna_sw_stats_get(struct bna *bna, struct bna_sw_stats *sw_stats)
1769 {
1770         struct bna_tx *tx;
1771         struct bna_txq *txq;
1772         struct bna_rx *rx;
1773         struct bna_rxp *rxp;
1774         struct list_head *qe;
1775         struct list_head *txq_qe;
1776         struct list_head *rxp_qe;
1777         struct list_head *mac_qe;
1778         int i;
1779
1780         sw_stats->device_state = bna_device_state_get(&bna->device);
1781         sw_stats->port_state = bna_port_state_get(&bna->port);
1782         sw_stats->port_flags = bna->port.flags;
1783         sw_stats->llport_state = bna_llport_state_get(&bna->port.llport);
1784         sw_stats->priority = bna->port.priority;
1785
1786         i = 0;
1787         list_for_each(qe, &bna->tx_mod.tx_active_q) {
1788                 tx = (struct bna_tx *)qe;
1789                 sw_stats->tx_stats[i].tx_state = bna_tx_state_get(tx);
1790                 sw_stats->tx_stats[i].tx_flags = tx->flags;
1791
1792                 sw_stats->tx_stats[i].num_txqs = 0;
1793                 sw_stats->tx_stats[i].txq_bmap[0] = 0;
1794                 sw_stats->tx_stats[i].txq_bmap[1] = 0;
1795                 list_for_each(txq_qe, &tx->txq_q) {
1796                         txq = (struct bna_txq *)txq_qe;
1797                         if (txq->txq_id < 32)
1798                                 sw_stats->tx_stats[i].txq_bmap[0] |=
1799                                                 ((u32)1 << txq->txq_id);
1800                         else
1801                                 sw_stats->tx_stats[i].txq_bmap[1] |=
1802                                                 ((u32)
1803                                                  1 << (txq->txq_id - 32));
1804                         sw_stats->tx_stats[i].num_txqs++;
1805                 }
1806
1807                 sw_stats->tx_stats[i].txf_id = tx->txf.txf_id;
1808
1809                 i++;
1810         }
1811         sw_stats->num_active_tx = i;
1812
1813         i = 0;
1814         list_for_each(qe, &bna->rx_mod.rx_active_q) {
1815                 rx = (struct bna_rx *)qe;
1816                 sw_stats->rx_stats[i].rx_state = bna_rx_state_get(rx);
1817                 sw_stats->rx_stats[i].rx_flags = rx->rx_flags;
1818
1819                 sw_stats->rx_stats[i].num_rxps = 0;
1820                 sw_stats->rx_stats[i].num_rxqs = 0;
1821                 sw_stats->rx_stats[i].rxq_bmap[0] = 0;
1822                 sw_stats->rx_stats[i].rxq_bmap[1] = 0;
1823                 sw_stats->rx_stats[i].cq_bmap[0] = 0;
1824                 sw_stats->rx_stats[i].cq_bmap[1] = 0;
1825                 list_for_each(rxp_qe, &rx->rxp_q) {
1826                         rxp = (struct bna_rxp *)rxp_qe;
1827
1828                         sw_stats->rx_stats[i].num_rxqs += 1;
1829
1830                         if (rxp->type == BNA_RXP_SINGLE) {
1831                                 if (rxp->rxq.single.only->rxq_id < 32) {
1832                                         sw_stats->rx_stats[i].rxq_bmap[0] |=
1833                                         ((u32)1 <<
1834                                         rxp->rxq.single.only->rxq_id);
1835                                 } else {
1836                                         sw_stats->rx_stats[i].rxq_bmap[1] |=
1837                                         ((u32)1 <<
1838                                         (rxp->rxq.single.only->rxq_id - 32));
1839                                 }
1840                         } else {
1841                                 if (rxp->rxq.slr.large->rxq_id < 32) {
1842                                         sw_stats->rx_stats[i].rxq_bmap[0] |=
1843                                         ((u32)1 <<
1844                                         rxp->rxq.slr.large->rxq_id);
1845                                 } else {
1846                                         sw_stats->rx_stats[i].rxq_bmap[1] |=
1847                                         ((u32)1 <<
1848                                         (rxp->rxq.slr.large->rxq_id - 32));
1849                                 }
1850
1851                                 if (rxp->rxq.slr.small->rxq_id < 32) {
1852                                         sw_stats->rx_stats[i].rxq_bmap[0] |=
1853                                         ((u32)1 <<
1854                                         rxp->rxq.slr.small->rxq_id);
1855                                 } else {
1856                                         sw_stats->rx_stats[i].rxq_bmap[1] |=
1857                                 ((u32)1 <<
1858                                  (rxp->rxq.slr.small->rxq_id - 32));
1859                                 }
1860                                 sw_stats->rx_stats[i].num_rxqs += 1;
1861                         }
1862
1863                         if (rxp->cq.cq_id < 32)
1864                                 sw_stats->rx_stats[i].cq_bmap[0] |=
1865                                         (1 << rxp->cq.cq_id);
1866                         else
1867                                 sw_stats->rx_stats[i].cq_bmap[1] |=
1868                                         (1 << (rxp->cq.cq_id - 32));
1869
1870                         sw_stats->rx_stats[i].num_rxps++;
1871                 }
1872
1873                 sw_stats->rx_stats[i].rxf_id = rx->rxf.rxf_id;
1874                 sw_stats->rx_stats[i].rxf_state = bna_rxf_state_get(&rx->rxf);
1875                 sw_stats->rx_stats[i].rxf_oper_state = rx->rxf.rxf_oper_state;
1876
1877                 sw_stats->rx_stats[i].num_active_ucast = 0;
1878                 if (rx->rxf.ucast_active_mac)
1879                         sw_stats->rx_stats[i].num_active_ucast++;
1880                 list_for_each(mac_qe, &rx->rxf.ucast_active_q)
1881                         sw_stats->rx_stats[i].num_active_ucast++;
1882
1883                 sw_stats->rx_stats[i].num_active_mcast = 0;
1884                 list_for_each(mac_qe, &rx->rxf.mcast_active_q)
1885                         sw_stats->rx_stats[i].num_active_mcast++;
1886
1887                 sw_stats->rx_stats[i].rxmode_active = rx->rxf.rxmode_active;
1888                 sw_stats->rx_stats[i].vlan_filter_status =
1889                                                 rx->rxf.vlan_filter_status;
1890                 memcpy(sw_stats->rx_stats[i].vlan_filter_table,
1891                                 rx->rxf.vlan_filter_table,
1892                                 sizeof(u32) * ((BFI_MAX_VLAN + 1) / 32));
1893
1894                 sw_stats->rx_stats[i].rss_status = rx->rxf.rss_status;
1895                 sw_stats->rx_stats[i].hds_status = rx->rxf.hds_status;
1896
1897                 i++;
1898         }
1899         sw_stats->num_active_rx = i;
1900 }
1901
1902 static void
1903 bna_fw_cb_stats_get(void *arg, int status)
1904 {
1905         struct bna *bna = (struct bna *)arg;
1906         u64 *p_stats;
1907         int i, count;
1908         int rxf_count, txf_count;
1909         u64 rxf_bmap, txf_bmap;
1910
1911         bfa_q_qe_init(&bna->mbox_qe.qe);
1912
1913         if (status == 0) {
1914                 p_stats = (u64 *)bna->stats.hw_stats;
1915                 count = sizeof(struct bfi_ll_stats) / sizeof(u64);
1916                 for (i = 0; i < count; i++)
1917                         p_stats[i] = cpu_to_be64(p_stats[i]);
1918
1919                 rxf_count = 0;
1920                 rxf_bmap = (u64)bna->stats.rxf_bmap[0] |
1921                         ((u64)bna->stats.rxf_bmap[1] << 32);
1922                 for (i = 0; i < BFI_LL_RXF_ID_MAX; i++)
1923                         if (rxf_bmap & ((u64)1 << i))
1924                                 rxf_count++;
1925
1926                 txf_count = 0;
1927                 txf_bmap = (u64)bna->stats.txf_bmap[0] |
1928                         ((u64)bna->stats.txf_bmap[1] << 32);
1929                 for (i = 0; i < BFI_LL_TXF_ID_MAX; i++)
1930                         if (txf_bmap & ((u64)1 << i))
1931                                 txf_count++;
1932
1933                 p_stats = (u64 *)&bna->stats.hw_stats->rxf_stats[0] +
1934                                 ((rxf_count * sizeof(struct bfi_ll_stats_rxf) +
1935                                 txf_count * sizeof(struct bfi_ll_stats_txf))/
1936                                 sizeof(u64));
1937
1938                 /* Populate the TXF stats from the firmware DMAed copy */
1939                 for (i = (BFI_LL_TXF_ID_MAX - 1); i >= 0; i--)
1940                         if (txf_bmap & ((u64)1 << i)) {
1941                                 p_stats -= sizeof(struct bfi_ll_stats_txf)/
1942                                                 sizeof(u64);
1943                                 memcpy(&bna->stats.hw_stats->txf_stats[i],
1944                                         p_stats,
1945                                         sizeof(struct bfi_ll_stats_txf));
1946                         }
1947
1948                 /* Populate the RXF stats from the firmware DMAed copy */
1949                 for (i = (BFI_LL_RXF_ID_MAX - 1); i >= 0; i--)
1950                         if (rxf_bmap & ((u64)1 << i)) {
1951                                 p_stats -= sizeof(struct bfi_ll_stats_rxf)/
1952                                                 sizeof(u64);
1953                                 memcpy(&bna->stats.hw_stats->rxf_stats[i],
1954                                         p_stats,
1955                                         sizeof(struct bfi_ll_stats_rxf));
1956                         }
1957
1958                 bna_sw_stats_get(bna, bna->stats.sw_stats);
1959                 bnad_cb_stats_get(bna->bnad, BNA_CB_SUCCESS, &bna->stats);
1960         } else
1961                 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
1962 }
1963
1964 static void
1965 bna_fw_stats_get(struct bna *bna)
1966 {
1967         struct bfi_ll_stats_req ll_req;
1968
1969         bfi_h2i_set(ll_req.mh, BFI_MC_LL, BFI_LL_H2I_STATS_GET_REQ, 0);
1970         ll_req.stats_mask = htons(BFI_LL_STATS_ALL);
1971
1972         ll_req.rxf_id_mask[0] = htonl(bna->rx_mod.rxf_bmap[0]);
1973         ll_req.rxf_id_mask[1] = htonl(bna->rx_mod.rxf_bmap[1]);
1974         ll_req.txf_id_mask[0] = htonl(bna->tx_mod.txf_bmap[0]);
1975         ll_req.txf_id_mask[1] = htonl(bna->tx_mod.txf_bmap[1]);
1976
1977         ll_req.host_buffer.a32.addr_hi = bna->hw_stats_dma.msb;
1978         ll_req.host_buffer.a32.addr_lo = bna->hw_stats_dma.lsb;
1979
1980         bna_mbox_qe_fill(&bna->mbox_qe, &ll_req, sizeof(ll_req),
1981                                 bna_fw_cb_stats_get, bna);
1982         bna_mbox_send(bna, &bna->mbox_qe);
1983
1984         bna->stats.rxf_bmap[0] = bna->rx_mod.rxf_bmap[0];
1985         bna->stats.rxf_bmap[1] = bna->rx_mod.rxf_bmap[1];
1986         bna->stats.txf_bmap[0] = bna->tx_mod.txf_bmap[0];
1987         bna->stats.txf_bmap[1] = bna->tx_mod.txf_bmap[1];
1988 }
1989
1990 void
1991 bna_stats_get(struct bna *bna)
1992 {
1993         if (bna_device_status_get(&bna->device))
1994                 bna_fw_stats_get(bna);
1995         else
1996                 bnad_cb_stats_get(bna->bnad, BNA_CB_FAIL, &bna->stats);
1997 }
1998
1999 /* IB */
2000 static void
2001 bna_ib_coalescing_timeo_set(struct bna_ib *ib, u8 coalescing_timeo)
2002 {
2003         ib->ib_config.coalescing_timeo = coalescing_timeo;
2004
2005         if (ib->start_count)
2006                 ib->door_bell.doorbell_ack = BNA_DOORBELL_IB_INT_ACK(
2007                                 (u32)ib->ib_config.coalescing_timeo, 0);
2008 }
2009
2010 /* RxF */
2011 void
2012 bna_rxf_adv_init(struct bna_rxf *rxf,
2013                 struct bna_rx *rx,
2014                 struct bna_rx_config *q_config)
2015 {
2016         switch (q_config->rxp_type) {
2017         case BNA_RXP_SINGLE:
2018                 /* No-op */
2019                 break;
2020         case BNA_RXP_SLR:
2021                 rxf->ctrl_flags |= BNA_RXF_CF_SM_LG_RXQ;
2022                 break;
2023         case BNA_RXP_HDS:
2024                 rxf->hds_cfg.hdr_type = q_config->hds_config.hdr_type;
2025                 rxf->hds_cfg.header_size =
2026                                 q_config->hds_config.header_size;
2027                 rxf->forced_offset = 0;
2028                 break;
2029         default:
2030                 break;
2031         }
2032
2033         if (q_config->rss_status == BNA_STATUS_T_ENABLED) {
2034                 rxf->ctrl_flags |= BNA_RXF_CF_RSS_ENABLE;
2035                 rxf->rss_cfg.hash_type = q_config->rss_config.hash_type;
2036                 rxf->rss_cfg.hash_mask = q_config->rss_config.hash_mask;
2037                 memcpy(&rxf->rss_cfg.toeplitz_hash_key[0],
2038                         &q_config->rss_config.toeplitz_hash_key[0],
2039                         sizeof(rxf->rss_cfg.toeplitz_hash_key));
2040         }
2041 }
2042
2043 static void
2044 rxf_fltr_mbox_cmd(struct bna_rxf *rxf, u8 cmd, enum bna_status status)
2045 {
2046         struct bfi_ll_rxf_req req;
2047
2048         bfi_h2i_set(req.mh, BFI_MC_LL, cmd, 0);
2049
2050         req.rxf_id = rxf->rxf_id;
2051         req.enable = status;
2052
2053         bna_mbox_qe_fill(&rxf->mbox_qe, &req, sizeof(req),
2054                         rxf_cb_cam_fltr_mbox_cmd, rxf);
2055
2056         bna_mbox_send(rxf->rx->bna, &rxf->mbox_qe);
2057 }
2058
2059 static void
2060 __rxf_default_function_config(struct bna_rxf *rxf, enum bna_status status)
2061 {
2062         struct bna_rx_fndb_ram *rx_fndb_ram;
2063         u32 ctrl_flags;
2064         int i;
2065
2066         rx_fndb_ram = (struct bna_rx_fndb_ram *)
2067                         BNA_GET_MEM_BASE_ADDR(rxf->rx->bna->pcidev.pci_bar_kva,
2068                         RX_FNDB_RAM_BASE_OFFSET);
2069
2070         for (i = 0; i < BFI_MAX_RXF; i++) {
2071                 if (status == BNA_STATUS_T_ENABLED) {
2072                         if (i == rxf->rxf_id)
2073                                 continue;
2074
2075                         ctrl_flags =
2076                                 readl(&rx_fndb_ram[i].control_flags);
2077                         ctrl_flags |= BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
2078                         writel(ctrl_flags,
2079                                                 &rx_fndb_ram[i].control_flags);
2080                 } else {
2081                         ctrl_flags =
2082                                 readl(&rx_fndb_ram[i].control_flags);
2083                         ctrl_flags &= ~BNA_RXF_CF_DEFAULT_FUNCTION_ENABLE;
2084                         writel(ctrl_flags,
2085                                                 &rx_fndb_ram[i].control_flags);
2086                 }
2087         }
2088 }
2089
2090 int
2091 rxf_process_packet_filter_ucast(struct bna_rxf *rxf)
2092 {
2093         struct bna_mac *mac = NULL;
2094         struct list_head *qe;
2095
2096         /* Add additional MAC entries */
2097         if (!list_empty(&rxf->ucast_pending_add_q)) {
2098                 bfa_q_deq(&rxf->ucast_pending_add_q, &qe);
2099                 bfa_q_qe_init(qe);
2100                 mac = (struct bna_mac *)qe;
2101                 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_ADD_REQ, mac);
2102                 list_add_tail(&mac->qe, &rxf->ucast_active_q);
2103                 return 1;
2104         }
2105
2106         /* Delete MAC addresses previousely added */
2107         if (!list_empty(&rxf->ucast_pending_del_q)) {
2108                 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2109                 bfa_q_qe_init(qe);
2110                 mac = (struct bna_mac *)qe;
2111                 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2112                 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2113                 return 1;
2114         }
2115
2116         return 0;
2117 }
2118
2119 int
2120 rxf_process_packet_filter_promisc(struct bna_rxf *rxf)
2121 {
2122         struct bna *bna = rxf->rx->bna;
2123
2124         /* Enable/disable promiscuous mode */
2125         if (is_promisc_enable(rxf->rxmode_pending,
2126                                 rxf->rxmode_pending_bitmask)) {
2127                 /* move promisc configuration from pending -> active */
2128                 promisc_inactive(rxf->rxmode_pending,
2129                                 rxf->rxmode_pending_bitmask);
2130                 rxf->rxmode_active |= BNA_RXMODE_PROMISC;
2131
2132                 /* Disable VLAN filter to allow all VLANs */
2133                 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2134                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2135                                 BNA_STATUS_T_ENABLED);
2136                 return 1;
2137         } else if (is_promisc_disable(rxf->rxmode_pending,
2138                                 rxf->rxmode_pending_bitmask)) {
2139                 /* move promisc configuration from pending -> active */
2140                 promisc_inactive(rxf->rxmode_pending,
2141                                 rxf->rxmode_pending_bitmask);
2142                 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2143                 bna->rxf_promisc_id = BFI_MAX_RXF;
2144
2145                 /* Revert VLAN filter */
2146                 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2147                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2148                                 BNA_STATUS_T_DISABLED);
2149                 return 1;
2150         }
2151
2152         return 0;
2153 }
2154
2155 int
2156 rxf_process_packet_filter_default(struct bna_rxf *rxf)
2157 {
2158         struct bna *bna = rxf->rx->bna;
2159
2160         /* Enable/disable default mode */
2161         if (is_default_enable(rxf->rxmode_pending,
2162                                 rxf->rxmode_pending_bitmask)) {
2163                 /* move default configuration from pending -> active */
2164                 default_inactive(rxf->rxmode_pending,
2165                                 rxf->rxmode_pending_bitmask);
2166                 rxf->rxmode_active |= BNA_RXMODE_DEFAULT;
2167
2168                 /* Disable VLAN filter to allow all VLANs */
2169                 __rxf_vlan_filter_set(rxf, BNA_STATUS_T_DISABLED);
2170                 /* Redirect all other RxF vlan filtering to this one */
2171                 __rxf_default_function_config(rxf, BNA_STATUS_T_ENABLED);
2172                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2173                                 BNA_STATUS_T_ENABLED);
2174                 return 1;
2175         } else if (is_default_disable(rxf->rxmode_pending,
2176                                 rxf->rxmode_pending_bitmask)) {
2177                 /* move default configuration from pending -> active */
2178                 default_inactive(rxf->rxmode_pending,
2179                                 rxf->rxmode_pending_bitmask);
2180                 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2181                 bna->rxf_default_id = BFI_MAX_RXF;
2182
2183                 /* Revert VLAN filter */
2184                 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2185                 /* Stop RxF vlan filter table redirection */
2186                 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2187                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2188                                 BNA_STATUS_T_DISABLED);
2189                 return 1;
2190         }
2191
2192         return 0;
2193 }
2194
2195 int
2196 rxf_process_packet_filter_allmulti(struct bna_rxf *rxf)
2197 {
2198         /* Enable/disable allmulti mode */
2199         if (is_allmulti_enable(rxf->rxmode_pending,
2200                                 rxf->rxmode_pending_bitmask)) {
2201                 /* move allmulti configuration from pending -> active */
2202                 allmulti_inactive(rxf->rxmode_pending,
2203                                 rxf->rxmode_pending_bitmask);
2204                 rxf->rxmode_active |= BNA_RXMODE_ALLMULTI;
2205
2206                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2207                                 BNA_STATUS_T_ENABLED);
2208                 return 1;
2209         } else if (is_allmulti_disable(rxf->rxmode_pending,
2210                                         rxf->rxmode_pending_bitmask)) {
2211                 /* move allmulti configuration from pending -> active */
2212                 allmulti_inactive(rxf->rxmode_pending,
2213                                 rxf->rxmode_pending_bitmask);
2214                 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2215
2216                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2217                                 BNA_STATUS_T_DISABLED);
2218                 return 1;
2219         }
2220
2221         return 0;
2222 }
2223
2224 int
2225 rxf_clear_packet_filter_ucast(struct bna_rxf *rxf)
2226 {
2227         struct bna_mac *mac = NULL;
2228         struct list_head *qe;
2229
2230         /* 1. delete pending ucast entries */
2231         if (!list_empty(&rxf->ucast_pending_del_q)) {
2232                 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2233                 bfa_q_qe_init(qe);
2234                 mac = (struct bna_mac *)qe;
2235                 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2236                 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2237                 return 1;
2238         }
2239
2240         /* 2. clear active ucast entries; move them to pending_add_q */
2241         if (!list_empty(&rxf->ucast_active_q)) {
2242                 bfa_q_deq(&rxf->ucast_active_q, &qe);
2243                 bfa_q_qe_init(qe);
2244                 mac = (struct bna_mac *)qe;
2245                 rxf_cam_mbox_cmd(rxf, BFI_LL_H2I_MAC_UCAST_DEL_REQ, mac);
2246                 list_add_tail(&mac->qe, &rxf->ucast_pending_add_q);
2247                 return 1;
2248         }
2249
2250         return 0;
2251 }
2252
2253 int
2254 rxf_clear_packet_filter_promisc(struct bna_rxf *rxf)
2255 {
2256         struct bna *bna = rxf->rx->bna;
2257
2258         /* 6. Execute pending promisc mode disable command */
2259         if (is_promisc_disable(rxf->rxmode_pending,
2260                                 rxf->rxmode_pending_bitmask)) {
2261                 /* move promisc configuration from pending -> active */
2262                 promisc_inactive(rxf->rxmode_pending,
2263                                 rxf->rxmode_pending_bitmask);
2264                 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2265                 bna->rxf_promisc_id = BFI_MAX_RXF;
2266
2267                 /* Revert VLAN filter */
2268                 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2269                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2270                                 BNA_STATUS_T_DISABLED);
2271                 return 1;
2272         }
2273
2274         /* 7. Clear active promisc mode; move it to pending enable */
2275         if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2276                 /* move promisc configuration from active -> pending */
2277                 promisc_enable(rxf->rxmode_pending,
2278                                 rxf->rxmode_pending_bitmask);
2279                 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2280
2281                 /* Revert VLAN filter */
2282                 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2283                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_PROMISCUOUS_SET_REQ,
2284                                 BNA_STATUS_T_DISABLED);
2285                 return 1;
2286         }
2287
2288         return 0;
2289 }
2290
2291 int
2292 rxf_clear_packet_filter_default(struct bna_rxf *rxf)
2293 {
2294         struct bna *bna = rxf->rx->bna;
2295
2296         /* 8. Execute pending default mode disable command */
2297         if (is_default_disable(rxf->rxmode_pending,
2298                                 rxf->rxmode_pending_bitmask)) {
2299                 /* move default configuration from pending -> active */
2300                 default_inactive(rxf->rxmode_pending,
2301                                 rxf->rxmode_pending_bitmask);
2302                 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2303                 bna->rxf_default_id = BFI_MAX_RXF;
2304
2305                 /* Revert VLAN filter */
2306                 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2307                 /* Stop RxF vlan filter table redirection */
2308                 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2309                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2310                                 BNA_STATUS_T_DISABLED);
2311                 return 1;
2312         }
2313
2314         /* 9. Clear active default mode; move it to pending enable */
2315         if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2316                 /* move default configuration from active -> pending */
2317                 default_enable(rxf->rxmode_pending,
2318                                 rxf->rxmode_pending_bitmask);
2319                 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2320
2321                 /* Revert VLAN filter */
2322                 __rxf_vlan_filter_set(rxf, rxf->vlan_filter_status);
2323                 /* Stop RxF vlan filter table redirection */
2324                 __rxf_default_function_config(rxf, BNA_STATUS_T_DISABLED);
2325                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_RXF_DEFAULT_SET_REQ,
2326                                 BNA_STATUS_T_DISABLED);
2327                 return 1;
2328         }
2329
2330         return 0;
2331 }
2332
2333 int
2334 rxf_clear_packet_filter_allmulti(struct bna_rxf *rxf)
2335 {
2336         /* 10. Execute pending allmulti mode disable command */
2337         if (is_allmulti_disable(rxf->rxmode_pending,
2338                                 rxf->rxmode_pending_bitmask)) {
2339                 /* move allmulti configuration from pending -> active */
2340                 allmulti_inactive(rxf->rxmode_pending,
2341                                 rxf->rxmode_pending_bitmask);
2342                 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2343                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2344                                 BNA_STATUS_T_DISABLED);
2345                 return 1;
2346         }
2347
2348         /* 11. Clear active allmulti mode; move it to pending enable */
2349         if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2350                 /* move allmulti configuration from active -> pending */
2351                 allmulti_enable(rxf->rxmode_pending,
2352                                 rxf->rxmode_pending_bitmask);
2353                 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2354                 rxf_fltr_mbox_cmd(rxf, BFI_LL_H2I_MAC_MCAST_FILTER_REQ,
2355                                 BNA_STATUS_T_DISABLED);
2356                 return 1;
2357         }
2358
2359         return 0;
2360 }
2361
2362 void
2363 rxf_reset_packet_filter_ucast(struct bna_rxf *rxf)
2364 {
2365         struct list_head *qe;
2366         struct bna_mac *mac;
2367
2368         /* 1. Move active ucast entries to pending_add_q */
2369         while (!list_empty(&rxf->ucast_active_q)) {
2370                 bfa_q_deq(&rxf->ucast_active_q, &qe);
2371                 bfa_q_qe_init(qe);
2372                 list_add_tail(qe, &rxf->ucast_pending_add_q);
2373         }
2374
2375         /* 2. Throw away delete pending ucast entries */
2376         while (!list_empty(&rxf->ucast_pending_del_q)) {
2377                 bfa_q_deq(&rxf->ucast_pending_del_q, &qe);
2378                 bfa_q_qe_init(qe);
2379                 mac = (struct bna_mac *)qe;
2380                 bna_ucam_mod_mac_put(&rxf->rx->bna->ucam_mod, mac);
2381         }
2382 }
2383
2384 void
2385 rxf_reset_packet_filter_promisc(struct bna_rxf *rxf)
2386 {
2387         struct bna *bna = rxf->rx->bna;
2388
2389         /* 6. Clear pending promisc mode disable */
2390         if (is_promisc_disable(rxf->rxmode_pending,
2391                                 rxf->rxmode_pending_bitmask)) {
2392                 promisc_inactive(rxf->rxmode_pending,
2393                                 rxf->rxmode_pending_bitmask);
2394                 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2395                 bna->rxf_promisc_id = BFI_MAX_RXF;
2396         }
2397
2398         /* 7. Move promisc mode config from active -> pending */
2399         if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2400                 promisc_enable(rxf->rxmode_pending,
2401                                 rxf->rxmode_pending_bitmask);
2402                 rxf->rxmode_active &= ~BNA_RXMODE_PROMISC;
2403         }
2404
2405 }
2406
2407 void
2408 rxf_reset_packet_filter_default(struct bna_rxf *rxf)
2409 {
2410         struct bna *bna = rxf->rx->bna;
2411
2412         /* 8. Clear pending default mode disable */
2413         if (is_default_disable(rxf->rxmode_pending,
2414                                 rxf->rxmode_pending_bitmask)) {
2415                 default_inactive(rxf->rxmode_pending,
2416                                 rxf->rxmode_pending_bitmask);
2417                 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2418                 bna->rxf_default_id = BFI_MAX_RXF;
2419         }
2420
2421         /* 9. Move default mode config from active -> pending */
2422         if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2423                 default_enable(rxf->rxmode_pending,
2424                                 rxf->rxmode_pending_bitmask);
2425                 rxf->rxmode_active &= ~BNA_RXMODE_DEFAULT;
2426         }
2427 }
2428
2429 void
2430 rxf_reset_packet_filter_allmulti(struct bna_rxf *rxf)
2431 {
2432         /* 10. Clear pending allmulti mode disable */
2433         if (is_allmulti_disable(rxf->rxmode_pending,
2434                                 rxf->rxmode_pending_bitmask)) {
2435                 allmulti_inactive(rxf->rxmode_pending,
2436                                 rxf->rxmode_pending_bitmask);
2437                 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2438         }
2439
2440         /* 11. Move allmulti mode config from active -> pending */
2441         if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2442                 allmulti_enable(rxf->rxmode_pending,
2443                                 rxf->rxmode_pending_bitmask);
2444                 rxf->rxmode_active &= ~BNA_RXMODE_ALLMULTI;
2445         }
2446 }
2447
2448 /**
2449  * Should only be called by bna_rxf_mode_set.
2450  * Helps deciding if h/w configuration is needed or not.
2451  *  Returns:
2452  *      0 = no h/w change
2453  *      1 = need h/w change
2454  */
2455 static int
2456 rxf_promisc_enable(struct bna_rxf *rxf)
2457 {
2458         struct bna *bna = rxf->rx->bna;
2459         int ret = 0;
2460
2461         /* There can not be any pending disable command */
2462
2463         /* Do nothing if pending enable or already enabled */
2464         if (is_promisc_enable(rxf->rxmode_pending,
2465                         rxf->rxmode_pending_bitmask) ||
2466                         (rxf->rxmode_active & BNA_RXMODE_PROMISC)) {
2467                 /* Schedule enable */
2468         } else {
2469                 /* Promisc mode should not be active in the system */
2470                 promisc_enable(rxf->rxmode_pending,
2471                                 rxf->rxmode_pending_bitmask);
2472                 bna->rxf_promisc_id = rxf->rxf_id;
2473                 ret = 1;
2474         }
2475
2476         return ret;
2477 }
2478
2479 /**
2480  * Should only be called by bna_rxf_mode_set.
2481  * Helps deciding if h/w configuration is needed or not.
2482  *  Returns:
2483  *      0 = no h/w change
2484  *      1 = need h/w change
2485  */
2486 static int
2487 rxf_promisc_disable(struct bna_rxf *rxf)
2488 {
2489         struct bna *bna = rxf->rx->bna;
2490         int ret = 0;
2491
2492         /* There can not be any pending disable */
2493
2494         /* Turn off pending enable command , if any */
2495         if (is_promisc_enable(rxf->rxmode_pending,
2496                                 rxf->rxmode_pending_bitmask)) {
2497                 /* Promisc mode should not be active */
2498                 /* system promisc state should be pending */
2499                 promisc_inactive(rxf->rxmode_pending,
2500                                 rxf->rxmode_pending_bitmask);
2501                 /* Remove the promisc state from the system */
2502                 bna->rxf_promisc_id = BFI_MAX_RXF;
2503
2504                 /* Schedule disable */
2505         } else if (rxf->rxmode_active & BNA_RXMODE_PROMISC) {
2506                 /* Promisc mode should be active in the system */
2507                 promisc_disable(rxf->rxmode_pending,
2508                                 rxf->rxmode_pending_bitmask);
2509                 ret = 1;
2510
2511         /* Do nothing if already disabled */
2512         } else {
2513         }
2514
2515         return ret;
2516 }
2517
2518 /**
2519  * Should only be called by bna_rxf_mode_set.
2520  * Helps deciding if h/w configuration is needed or not.
2521  *  Returns:
2522  *      0 = no h/w change
2523  *      1 = need h/w change
2524  */
2525 static int
2526 rxf_default_enable(struct bna_rxf *rxf)
2527 {
2528         struct bna *bna = rxf->rx->bna;
2529         int ret = 0;
2530
2531         /* There can not be any pending disable command */
2532
2533         /* Do nothing if pending enable or already enabled */
2534         if (is_default_enable(rxf->rxmode_pending,
2535                 rxf->rxmode_pending_bitmask) ||
2536                 (rxf->rxmode_active & BNA_RXMODE_DEFAULT)) {
2537                 /* Schedule enable */
2538         } else {
2539                 /* Default mode should not be active in the system */
2540                 default_enable(rxf->rxmode_pending,
2541                                 rxf->rxmode_pending_bitmask);
2542                 bna->rxf_default_id = rxf->rxf_id;
2543                 ret = 1;
2544         }
2545
2546         return ret;
2547 }
2548
2549 /**
2550  * Should only be called by bna_rxf_mode_set.
2551  * Helps deciding if h/w configuration is needed or not.
2552  *  Returns:
2553  *      0 = no h/w change
2554  *      1 = need h/w change
2555  */
2556 static int
2557 rxf_default_disable(struct bna_rxf *rxf)
2558 {
2559         struct bna *bna = rxf->rx->bna;
2560         int ret = 0;
2561
2562         /* There can not be any pending disable */
2563
2564         /* Turn off pending enable command , if any */
2565         if (is_default_enable(rxf->rxmode_pending,
2566                                 rxf->rxmode_pending_bitmask)) {
2567                 /* Promisc mode should not be active */
2568                 /* system default state should be pending */
2569                 default_inactive(rxf->rxmode_pending,
2570                                 rxf->rxmode_pending_bitmask);
2571                 /* Remove the default state from the system */
2572                 bna->rxf_default_id = BFI_MAX_RXF;
2573
2574         /* Schedule disable */
2575         } else if (rxf->rxmode_active & BNA_RXMODE_DEFAULT) {
2576                 /* Default mode should be active in the system */
2577                 default_disable(rxf->rxmode_pending,
2578                                 rxf->rxmode_pending_bitmask);
2579                 ret = 1;
2580
2581         /* Do nothing if already disabled */
2582         } else {
2583         }
2584
2585         return ret;
2586 }
2587
2588 /**
2589  * Should only be called by bna_rxf_mode_set.
2590  * Helps deciding if h/w configuration is needed or not.
2591  *  Returns:
2592  *      0 = no h/w change
2593  *      1 = need h/w change
2594  */
2595 static int
2596 rxf_allmulti_enable(struct bna_rxf *rxf)
2597 {
2598         int ret = 0;
2599
2600         /* There can not be any pending disable command */
2601
2602         /* Do nothing if pending enable or already enabled */
2603         if (is_allmulti_enable(rxf->rxmode_pending,
2604                         rxf->rxmode_pending_bitmask) ||
2605                         (rxf->rxmode_active & BNA_RXMODE_ALLMULTI)) {
2606                 /* Schedule enable */
2607         } else {
2608                 allmulti_enable(rxf->rxmode_pending,
2609                                 rxf->rxmode_pending_bitmask);
2610                 ret = 1;
2611         }
2612
2613         return ret;
2614 }
2615
2616 /**
2617  * Should only be called by bna_rxf_mode_set.
2618  * Helps deciding if h/w configuration is needed or not.
2619  *  Returns:
2620  *      0 = no h/w change
2621  *      1 = need h/w change
2622  */
2623 static int
2624 rxf_allmulti_disable(struct bna_rxf *rxf)
2625 {
2626         int ret = 0;
2627
2628         /* There can not be any pending disable */
2629
2630         /* Turn off pending enable command , if any */
2631         if (is_allmulti_enable(rxf->rxmode_pending,
2632                                 rxf->rxmode_pending_bitmask)) {
2633                 /* Allmulti mode should not be active */
2634                 allmulti_inactive(rxf->rxmode_pending,
2635                                 rxf->rxmode_pending_bitmask);
2636
2637         /* Schedule disable */
2638         } else if (rxf->rxmode_active & BNA_RXMODE_ALLMULTI) {
2639                 allmulti_disable(rxf->rxmode_pending,
2640                                 rxf->rxmode_pending_bitmask);
2641                 ret = 1;
2642         }
2643
2644         return ret;
2645 }
2646
2647 /* RxF <- bnad */
2648 enum bna_cb_status
2649 bna_rx_mode_set(struct bna_rx *rx, enum bna_rxmode new_mode,
2650                 enum bna_rxmode bitmask,
2651                 void (*cbfn)(struct bnad *, struct bna_rx *,
2652                              enum bna_cb_status))
2653 {
2654         struct bna_rxf *rxf = &rx->rxf;
2655         int need_hw_config = 0;
2656
2657         /* Error checks */
2658
2659         if (is_promisc_enable(new_mode, bitmask)) {
2660                 /* If promisc mode is already enabled elsewhere in the system */
2661                 if ((rx->bna->rxf_promisc_id != BFI_MAX_RXF) &&
2662                         (rx->bna->rxf_promisc_id != rxf->rxf_id))
2663                         goto err_return;
2664
2665                 /* If default mode is already enabled in the system */
2666                 if (rx->bna->rxf_default_id != BFI_MAX_RXF)
2667                         goto err_return;
2668
2669                 /* Trying to enable promiscuous and default mode together */
2670                 if (is_default_enable(new_mode, bitmask))
2671                         goto err_return;
2672         }
2673
2674         if (is_default_enable(new_mode, bitmask)) {
2675                 /* If default mode is already enabled elsewhere in the system */
2676                 if ((rx->bna->rxf_default_id != BFI_MAX_RXF) &&
2677                         (rx->bna->rxf_default_id != rxf->rxf_id)) {
2678                                 goto err_return;
2679                 }
2680
2681                 /* If promiscuous mode is already enabled in the system */
2682                 if (rx->bna->rxf_promisc_id != BFI_MAX_RXF)
2683                         goto err_return;
2684         }
2685
2686         /* Process the commands */
2687
2688         if (is_promisc_enable(new_mode, bitmask)) {
2689                 if (rxf_promisc_enable(rxf))
2690                         need_hw_config = 1;
2691         } else if (is_promisc_disable(new_mode, bitmask)) {
2692                 if (rxf_promisc_disable(rxf))
2693                         need_hw_config = 1;
2694         }
2695
2696         if (is_default_enable(new_mode, bitmask)) {
2697                 if (rxf_default_enable(rxf))
2698                         need_hw_config = 1;
2699         } else if (is_default_disable(new_mode, bitmask)) {
2700                 if (rxf_default_disable(rxf))
2701                         need_hw_config = 1;
2702         }
2703
2704         if (is_allmulti_enable(new_mode, bitmask)) {
2705                 if (rxf_allmulti_enable(rxf))
2706                         need_hw_config = 1;
2707         } else if (is_allmulti_disable(new_mode, bitmask)) {
2708                 if (rxf_allmulti_disable(rxf))
2709                         need_hw_config = 1;
2710         }
2711
2712         /* Trigger h/w if needed */
2713
2714         if (need_hw_config) {
2715                 rxf->cam_fltr_cbfn = cbfn;
2716                 rxf->cam_fltr_cbarg = rx->bna->bnad;
2717                 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2718         } else if (cbfn)
2719                 (*cbfn)(rx->bna->bnad, rx, BNA_CB_SUCCESS);
2720
2721         return BNA_CB_SUCCESS;
2722
2723 err_return:
2724         return BNA_CB_FAIL;
2725 }
2726
2727 void
2728 /* RxF <- bnad */
2729 bna_rx_vlanfilter_enable(struct bna_rx *rx)
2730 {
2731         struct bna_rxf *rxf = &rx->rxf;
2732
2733         if (rxf->vlan_filter_status == BNA_STATUS_T_DISABLED) {
2734                 rxf->rxf_flags |= BNA_RXF_FL_VLAN_CONFIG_PENDING;
2735                 rxf->vlan_filter_status = BNA_STATUS_T_ENABLED;
2736                 bfa_fsm_send_event(rxf, RXF_E_CAM_FLTR_MOD);
2737         }
2738 }
2739
2740 /* Rx */
2741
2742 /* Rx <- bnad */
2743 void
2744 bna_rx_coalescing_timeo_set(struct bna_rx *rx, int coalescing_timeo)
2745 {
2746         struct bna_rxp *rxp;
2747         struct list_head *qe;
2748
2749         list_for_each(qe, &rx->rxp_q) {
2750                 rxp = (struct bna_rxp *)qe;
2751                 rxp->cq.ccb->rx_coalescing_timeo = coalescing_timeo;
2752                 bna_ib_coalescing_timeo_set(rxp->cq.ib, coalescing_timeo);
2753         }
2754 }
2755
2756 /* Rx <- bnad */
2757 void
2758 bna_rx_dim_reconfig(struct bna *bna, const u32 vector[][BNA_BIAS_T_MAX])
2759 {
2760         int i, j;
2761
2762         for (i = 0; i < BNA_LOAD_T_MAX; i++)
2763                 for (j = 0; j < BNA_BIAS_T_MAX; j++)
2764                         bna->rx_mod.dim_vector[i][j] = vector[i][j];
2765 }
2766
2767 /* Rx <- bnad */
2768 void
2769 bna_rx_dim_update(struct bna_ccb *ccb)
2770 {
2771         struct bna *bna = ccb->cq->rx->bna;
2772         u32 load, bias;
2773         u32 pkt_rt, small_rt, large_rt;
2774         u8 coalescing_timeo;
2775
2776         if ((ccb->pkt_rate.small_pkt_cnt == 0) &&
2777                 (ccb->pkt_rate.large_pkt_cnt == 0))
2778                 return;
2779
2780         /* Arrive at preconfigured coalescing timeo value based on pkt rate */
2781
2782         small_rt = ccb->pkt_rate.small_pkt_cnt;
2783         large_rt = ccb->pkt_rate.large_pkt_cnt;
2784
2785         pkt_rt = small_rt + large_rt;
2786
2787         if (pkt_rt < BNA_PKT_RATE_10K)
2788                 load = BNA_LOAD_T_LOW_4;
2789         else if (pkt_rt < BNA_PKT_RATE_20K)
2790                 load = BNA_LOAD_T_LOW_3;
2791         else if (pkt_rt < BNA_PKT_RATE_30K)
2792                 load = BNA_LOAD_T_LOW_2;
2793         else if (pkt_rt < BNA_PKT_RATE_40K)
2794                 load = BNA_LOAD_T_LOW_1;
2795         else if (pkt_rt < BNA_PKT_RATE_50K)
2796                 load = BNA_LOAD_T_HIGH_1;
2797         else if (pkt_rt < BNA_PKT_RATE_60K)
2798                 load = BNA_LOAD_T_HIGH_2;
2799         else if (pkt_rt < BNA_PKT_RATE_80K)
2800                 load = BNA_LOAD_T_HIGH_3;
2801         else
2802                 load = BNA_LOAD_T_HIGH_4;
2803
2804         if (small_rt > (large_rt << 1))
2805                 bias = 0;
2806         else
2807                 bias = 1;
2808
2809         ccb->pkt_rate.small_pkt_cnt = 0;
2810         ccb->pkt_rate.large_pkt_cnt = 0;
2811
2812         coalescing_timeo = bna->rx_mod.dim_vector[load][bias];
2813         ccb->rx_coalescing_timeo = coalescing_timeo;
2814
2815         /* Set it to IB */
2816         bna_ib_coalescing_timeo_set(ccb->cq->ib, coalescing_timeo);
2817 }
2818
2819 /* Tx */
2820 /* TX <- bnad */
2821 void
2822 bna_tx_coalescing_timeo_set(struct bna_tx *tx, int coalescing_timeo)
2823 {
2824         struct bna_txq *txq;
2825         struct list_head *qe;
2826
2827         list_for_each(qe, &tx->txq_q) {
2828                 txq = (struct bna_txq *)qe;
2829                 bna_ib_coalescing_timeo_set(txq->ib, coalescing_timeo);
2830         }
2831 }
2832
2833 /*
2834  * Private data
2835  */
2836
2837 struct bna_ritseg_pool_cfg {
2838         u32     pool_size;
2839         u32     pool_entry_size;
2840 };
2841 init_ritseg_pool(ritseg_pool_cfg);
2842
2843 /*
2844  * Private functions
2845  */
2846 static void
2847 bna_ucam_mod_init(struct bna_ucam_mod *ucam_mod, struct bna *bna,
2848                   struct bna_res_info *res_info)
2849 {
2850         int i;
2851
2852         ucam_mod->ucmac = (struct bna_mac *)
2853                 res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
2854
2855         INIT_LIST_HEAD(&ucam_mod->free_q);
2856         for (i = 0; i < BFI_MAX_UCMAC; i++) {
2857                 bfa_q_qe_init(&ucam_mod->ucmac[i].qe);
2858                 list_add_tail(&ucam_mod->ucmac[i].qe, &ucam_mod->free_q);
2859         }
2860
2861         ucam_mod->bna = bna;
2862 }
2863
2864 static void
2865 bna_ucam_mod_uninit(struct bna_ucam_mod *ucam_mod)
2866 {
2867         struct list_head *qe;
2868         int i = 0;
2869
2870         list_for_each(qe, &ucam_mod->free_q)
2871                 i++;
2872
2873         ucam_mod->bna = NULL;
2874 }
2875
2876 static void
2877 bna_mcam_mod_init(struct bna_mcam_mod *mcam_mod, struct bna *bna,
2878                   struct bna_res_info *res_info)
2879 {
2880         int i;
2881
2882         mcam_mod->mcmac = (struct bna_mac *)
2883                 res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mdl[0].kva;
2884
2885         INIT_LIST_HEAD(&mcam_mod->free_q);
2886         for (i = 0; i < BFI_MAX_MCMAC; i++) {
2887                 bfa_q_qe_init(&mcam_mod->mcmac[i].qe);
2888                 list_add_tail(&mcam_mod->mcmac[i].qe, &mcam_mod->free_q);
2889         }
2890
2891         mcam_mod->bna = bna;
2892 }
2893
2894 static void
2895 bna_mcam_mod_uninit(struct bna_mcam_mod *mcam_mod)
2896 {
2897         struct list_head *qe;
2898         int i = 0;
2899
2900         list_for_each(qe, &mcam_mod->free_q)
2901                 i++;
2902
2903         mcam_mod->bna = NULL;
2904 }
2905
2906 static void
2907 bna_rit_mod_init(struct bna_rit_mod *rit_mod,
2908                 struct bna_res_info *res_info)
2909 {
2910         int i;
2911         int j;
2912         int count;
2913         int offset;
2914
2915         rit_mod->rit = (struct bna_rit_entry *)
2916                 res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mdl[0].kva;
2917         rit_mod->rit_segment = (struct bna_rit_segment *)
2918                 res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mdl[0].kva;
2919
2920         count = 0;
2921         offset = 0;
2922         for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
2923                 INIT_LIST_HEAD(&rit_mod->rit_seg_pool[i]);
2924                 for (j = 0; j < ritseg_pool_cfg[i].pool_size; j++) {
2925                         bfa_q_qe_init(&rit_mod->rit_segment[count].qe);
2926                         rit_mod->rit_segment[count].max_rit_size =
2927                                         ritseg_pool_cfg[i].pool_entry_size;
2928                         rit_mod->rit_segment[count].rit_offset = offset;
2929                         rit_mod->rit_segment[count].rit =
2930                                         &rit_mod->rit[offset];
2931                         list_add_tail(&rit_mod->rit_segment[count].qe,
2932                                 &rit_mod->rit_seg_pool[i]);
2933                         count++;
2934                         offset += ritseg_pool_cfg[i].pool_entry_size;
2935                 }
2936         }
2937 }
2938
2939 static void
2940 bna_rit_mod_uninit(struct bna_rit_mod *rit_mod)
2941 {
2942         struct bna_rit_segment *rit_segment;
2943         struct list_head *qe;
2944         int i;
2945         int j;
2946
2947         for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
2948                 j = 0;
2949                 list_for_each(qe, &rit_mod->rit_seg_pool[i]) {
2950                         rit_segment = (struct bna_rit_segment *)qe;
2951                         j++;
2952                 }
2953         }
2954 }
2955
2956 /*
2957  * Public functions
2958  */
2959
2960 /* Called during probe(), before calling bna_init() */
2961 void
2962 bna_res_req(struct bna_res_info *res_info)
2963 {
2964         bna_adv_res_req(res_info);
2965
2966         /* DMA memory for retrieving IOC attributes */
2967         res_info[BNA_RES_MEM_T_ATTR].res_type = BNA_RES_T_MEM;
2968         res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
2969         res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.num = 1;
2970         res_info[BNA_RES_MEM_T_ATTR].res_u.mem_info.len =
2971                                 ALIGN(bfa_nw_ioc_meminfo(), PAGE_SIZE);
2972
2973         /* DMA memory for index segment of an IB */
2974         res_info[BNA_RES_MEM_T_IBIDX].res_type = BNA_RES_T_MEM;
2975         res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.mem_type = BNA_MEM_T_DMA;
2976         res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.len =
2977                                 BFI_IBIDX_SIZE * BFI_IBIDX_MAX_SEGSIZE;
2978         res_info[BNA_RES_MEM_T_IBIDX].res_u.mem_info.num = BFI_MAX_IB;
2979
2980         /* Virtual memory for IB objects - stored by IB module */
2981         res_info[BNA_RES_MEM_T_IB_ARRAY].res_type = BNA_RES_T_MEM;
2982         res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.mem_type =
2983                                                                 BNA_MEM_T_KVA;
2984         res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.num = 1;
2985         res_info[BNA_RES_MEM_T_IB_ARRAY].res_u.mem_info.len =
2986                                 BFI_MAX_IB * sizeof(struct bna_ib);
2987
2988         /* Virtual memory for intr objects - stored by IB module */
2989         res_info[BNA_RES_MEM_T_INTR_ARRAY].res_type = BNA_RES_T_MEM;
2990         res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.mem_type =
2991                                                                 BNA_MEM_T_KVA;
2992         res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.num = 1;
2993         res_info[BNA_RES_MEM_T_INTR_ARRAY].res_u.mem_info.len =
2994                                 BFI_MAX_IB * sizeof(struct bna_intr);
2995
2996         /* Virtual memory for idx_seg objects - stored by IB module */
2997         res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_type = BNA_RES_T_MEM;
2998         res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.mem_type =
2999                                                                 BNA_MEM_T_KVA;
3000         res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.num = 1;
3001         res_info[BNA_RES_MEM_T_IDXSEG_ARRAY].res_u.mem_info.len =
3002                         BFI_IBIDX_TOTAL_SEGS * sizeof(struct bna_ibidx_seg);
3003
3004         /* Virtual memory for Tx objects - stored by Tx module */
3005         res_info[BNA_RES_MEM_T_TX_ARRAY].res_type = BNA_RES_T_MEM;
3006         res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.mem_type =
3007                                                                 BNA_MEM_T_KVA;
3008         res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.num = 1;
3009         res_info[BNA_RES_MEM_T_TX_ARRAY].res_u.mem_info.len =
3010                         BFI_MAX_TXQ * sizeof(struct bna_tx);
3011
3012         /* Virtual memory for TxQ - stored by Tx module */
3013         res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_type = BNA_RES_T_MEM;
3014         res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.mem_type =
3015                                                                 BNA_MEM_T_KVA;
3016         res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.num = 1;
3017         res_info[BNA_RES_MEM_T_TXQ_ARRAY].res_u.mem_info.len =
3018                         BFI_MAX_TXQ * sizeof(struct bna_txq);
3019
3020         /* Virtual memory for Rx objects - stored by Rx module */
3021         res_info[BNA_RES_MEM_T_RX_ARRAY].res_type = BNA_RES_T_MEM;
3022         res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.mem_type =
3023                                                                 BNA_MEM_T_KVA;
3024         res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.num = 1;
3025         res_info[BNA_RES_MEM_T_RX_ARRAY].res_u.mem_info.len =
3026                         BFI_MAX_RXQ * sizeof(struct bna_rx);
3027
3028         /* Virtual memory for RxPath - stored by Rx module */
3029         res_info[BNA_RES_MEM_T_RXP_ARRAY].res_type = BNA_RES_T_MEM;
3030         res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.mem_type =
3031                                                                 BNA_MEM_T_KVA;
3032         res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.num = 1;
3033         res_info[BNA_RES_MEM_T_RXP_ARRAY].res_u.mem_info.len =
3034                         BFI_MAX_RXQ * sizeof(struct bna_rxp);
3035
3036         /* Virtual memory for RxQ - stored by Rx module */
3037         res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_type = BNA_RES_T_MEM;
3038         res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.mem_type =
3039                                                                 BNA_MEM_T_KVA;
3040         res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.num = 1;
3041         res_info[BNA_RES_MEM_T_RXQ_ARRAY].res_u.mem_info.len =
3042                         BFI_MAX_RXQ * sizeof(struct bna_rxq);
3043
3044         /* Virtual memory for Unicast MAC address - stored by ucam module */
3045         res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_type = BNA_RES_T_MEM;
3046         res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.mem_type =
3047                                                                 BNA_MEM_T_KVA;
3048         res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.num = 1;
3049         res_info[BNA_RES_MEM_T_UCMAC_ARRAY].res_u.mem_info.len =
3050                         BFI_MAX_UCMAC * sizeof(struct bna_mac);
3051
3052         /* Virtual memory for Multicast MAC address - stored by mcam module */
3053         res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_type = BNA_RES_T_MEM;
3054         res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.mem_type =
3055                                                                 BNA_MEM_T_KVA;
3056         res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.num = 1;
3057         res_info[BNA_RES_MEM_T_MCMAC_ARRAY].res_u.mem_info.len =
3058                         BFI_MAX_MCMAC * sizeof(struct bna_mac);
3059
3060         /* Virtual memory for RIT entries */
3061         res_info[BNA_RES_MEM_T_RIT_ENTRY].res_type = BNA_RES_T_MEM;
3062         res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.mem_type =
3063                                                                 BNA_MEM_T_KVA;
3064         res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.num = 1;
3065         res_info[BNA_RES_MEM_T_RIT_ENTRY].res_u.mem_info.len =
3066                         BFI_MAX_RIT_SIZE * sizeof(struct bna_rit_entry);
3067
3068         /* Virtual memory for RIT segment table */
3069         res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_type = BNA_RES_T_MEM;
3070         res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.mem_type =
3071                                                                 BNA_MEM_T_KVA;
3072         res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.num = 1;
3073         res_info[BNA_RES_MEM_T_RIT_SEGMENT].res_u.mem_info.len =
3074                         BFI_RIT_TOTAL_SEGS * sizeof(struct bna_rit_segment);
3075
3076         /* Interrupt resource for mailbox interrupt */
3077         res_info[BNA_RES_INTR_T_MBOX].res_type = BNA_RES_T_INTR;
3078         res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.intr_type =
3079                                                         BNA_INTR_T_MSIX;
3080         res_info[BNA_RES_INTR_T_MBOX].res_u.intr_info.num = 1;
3081 }
3082
3083 /* Called during probe() */
3084 void
3085 bna_init(struct bna *bna, struct bnad *bnad, struct bfa_pcidev *pcidev,
3086                 struct bna_res_info *res_info)
3087 {
3088         bna->bnad = bnad;
3089         bna->pcidev = *pcidev;
3090
3091         bna->stats.hw_stats = (struct bfi_ll_stats *)
3092                 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].kva;
3093         bna->hw_stats_dma.msb =
3094                 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.msb;
3095         bna->hw_stats_dma.lsb =
3096                 res_info[BNA_RES_MEM_T_STATS].res_u.mem_info.mdl[0].dma.lsb;
3097         bna->stats.sw_stats = (struct bna_sw_stats *)
3098                 res_info[BNA_RES_MEM_T_SWSTATS].res_u.mem_info.mdl[0].kva;
3099
3100         bna->regs.page_addr = bna->pcidev.pci_bar_kva +
3101                                 reg_offset[bna->pcidev.pci_func].page_addr;
3102         bna->regs.fn_int_status = bna->pcidev.pci_bar_kva +
3103                                 reg_offset[bna->pcidev.pci_func].fn_int_status;
3104         bna->regs.fn_int_mask = bna->pcidev.pci_bar_kva +
3105                                 reg_offset[bna->pcidev.pci_func].fn_int_mask;
3106
3107         if (bna->pcidev.pci_func < 3)
3108                 bna->port_num = 0;
3109         else
3110                 bna->port_num = 1;
3111
3112         /* Also initializes diag, cee, sfp, phy_port and mbox_mod */
3113         bna_device_init(&bna->device, bna, res_info);
3114
3115         bna_port_init(&bna->port, bna);
3116
3117         bna_tx_mod_init(&bna->tx_mod, bna, res_info);
3118
3119         bna_rx_mod_init(&bna->rx_mod, bna, res_info);
3120
3121         bna_ib_mod_init(&bna->ib_mod, bna, res_info);
3122
3123         bna_rit_mod_init(&bna->rit_mod, res_info);
3124
3125         bna_ucam_mod_init(&bna->ucam_mod, bna, res_info);
3126
3127         bna_mcam_mod_init(&bna->mcam_mod, bna, res_info);
3128
3129         bna->rxf_default_id = BFI_MAX_RXF;
3130         bna->rxf_promisc_id = BFI_MAX_RXF;
3131
3132         /* Mbox q element for posting stat request to f/w */
3133         bfa_q_qe_init(&bna->mbox_qe.qe);
3134 }
3135
3136 void
3137 bna_uninit(struct bna *bna)
3138 {
3139         bna_mcam_mod_uninit(&bna->mcam_mod);
3140
3141         bna_ucam_mod_uninit(&bna->ucam_mod);
3142
3143         bna_rit_mod_uninit(&bna->rit_mod);
3144
3145         bna_ib_mod_uninit(&bna->ib_mod);
3146
3147         bna_rx_mod_uninit(&bna->rx_mod);
3148
3149         bna_tx_mod_uninit(&bna->tx_mod);
3150
3151         bna_port_uninit(&bna->port);
3152
3153         bna_device_uninit(&bna->device);
3154
3155         bna->bnad = NULL;
3156 }
3157
3158 struct bna_mac *
3159 bna_ucam_mod_mac_get(struct bna_ucam_mod *ucam_mod)
3160 {
3161         struct list_head *qe;
3162
3163         if (list_empty(&ucam_mod->free_q))
3164                 return NULL;
3165
3166         bfa_q_deq(&ucam_mod->free_q, &qe);
3167
3168         return (struct bna_mac *)qe;
3169 }
3170
3171 void
3172 bna_ucam_mod_mac_put(struct bna_ucam_mod *ucam_mod, struct bna_mac *mac)
3173 {
3174         list_add_tail(&mac->qe, &ucam_mod->free_q);
3175 }
3176
3177 struct bna_mac *
3178 bna_mcam_mod_mac_get(struct bna_mcam_mod *mcam_mod)
3179 {
3180         struct list_head *qe;
3181
3182         if (list_empty(&mcam_mod->free_q))
3183                 return NULL;
3184
3185         bfa_q_deq(&mcam_mod->free_q, &qe);
3186
3187         return (struct bna_mac *)qe;
3188 }
3189
3190 void
3191 bna_mcam_mod_mac_put(struct bna_mcam_mod *mcam_mod, struct bna_mac *mac)
3192 {
3193         list_add_tail(&mac->qe, &mcam_mod->free_q);
3194 }
3195
3196 /**
3197  * Note: This should be called in the same locking context as the call to
3198  * bna_rit_mod_seg_get()
3199  */
3200 int
3201 bna_rit_mod_can_satisfy(struct bna_rit_mod *rit_mod, int seg_size)
3202 {
3203         int i;
3204
3205         /* Select the pool for seg_size */
3206         for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3207                 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3208                         break;
3209         }
3210
3211         if (i == BFI_RIT_SEG_TOTAL_POOLS)
3212                 return 0;
3213
3214         if (list_empty(&rit_mod->rit_seg_pool[i]))
3215                 return 0;
3216
3217         return 1;
3218 }
3219
3220 struct bna_rit_segment *
3221 bna_rit_mod_seg_get(struct bna_rit_mod *rit_mod, int seg_size)
3222 {
3223         struct bna_rit_segment *seg;
3224         struct list_head *qe;
3225         int i;
3226
3227         /* Select the pool for seg_size */
3228         for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3229                 if (seg_size <= ritseg_pool_cfg[i].pool_entry_size)
3230                         break;
3231         }
3232
3233         if (i == BFI_RIT_SEG_TOTAL_POOLS)
3234                 return NULL;
3235
3236         if (list_empty(&rit_mod->rit_seg_pool[i]))
3237                 return NULL;
3238
3239         bfa_q_deq(&rit_mod->rit_seg_pool[i], &qe);
3240         seg = (struct bna_rit_segment *)qe;
3241         bfa_q_qe_init(&seg->qe);
3242         seg->rit_size = seg_size;
3243
3244         return seg;
3245 }
3246
3247 void
3248 bna_rit_mod_seg_put(struct bna_rit_mod *rit_mod,
3249                         struct bna_rit_segment *seg)
3250 {
3251         int i;
3252
3253         /* Select the pool for seg->max_rit_size */
3254         for (i = 0; i < BFI_RIT_SEG_TOTAL_POOLS; i++) {
3255                 if (seg->max_rit_size == ritseg_pool_cfg[i].pool_entry_size)
3256                         break;
3257         }
3258
3259         seg->rit_size = 0;
3260         list_add_tail(&seg->qe, &rit_mod->rit_seg_pool[i]);
3261 }