drivers/net/bcmgenet.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com>
   4  *
   5  * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4)
   6  * This driver is based on the Linux driver:
   7  *      drivers/net/ethernet/broadcom/genet/bcmgenet.c
   8  *      which is: Copyright (c) 2014-2017 Broadcom
   9  *
  10  * The hardware supports multiple queues (16 priority queues and one
  11  * default queue), both for RX and TX. There are 256 DMA descriptors (both
  12  * for TX and RX), and they live in MMIO registers. The hardware allows
  13  * assigning descriptor ranges to queues, but we choose the most simple setup:
  14  * All 256 descriptors are assigned to the default queue (#16).
  15  * Also the Linux driver supports multiple generations of the MAC, whereas
  16  * we only support v5, as used in the Raspberry Pi 4.
  17  */
  18
  19 #include <log.h>
  20 #include <asm/cache.h>
  21 #include <asm/io.h>
  22 #include <clk.h>
  23 #include <cpu_func.h>
  24 #include <dm.h>
  25 #include <fdt_support.h>
  26 #include <linux/err.h>
  27 #include <malloc.h>
  28 #include <miiphy.h>
  29 #include <net.h>
  30 #include <dm/of_access.h>
  31 #include <dm/ofnode.h>
  32 #include <linux/iopoll.h>
  33 #include <linux/sizes.h>
  34 #include <asm/dma-mapping.h>
  35 #include <wait_bit.h>
  36
  37 /* Register definitions derived from Linux source */
  38 #define SYS_REV_CTRL                    0x00
  39
  40 #define SYS_PORT_CTRL                   0x04
  41 #define PORT_MODE_EXT_GPHY              3
  42
  43 #define GENET_SYS_OFF                   0x0000
  44 #define SYS_RBUF_FLUSH_CTRL             (GENET_SYS_OFF  + 0x08)
  45 #define SYS_TBUF_FLUSH_CTRL             (GENET_SYS_OFF  + 0x0c)
  46
  47 #define GENET_EXT_OFF                   0x0080
  48 #define EXT_RGMII_OOB_CTRL              (GENET_EXT_OFF + 0x0c)
  49 #define RGMII_LINK                      BIT(4)
  50 #define OOB_DISABLE                     BIT(5)
  51 #define RGMII_MODE_EN                   BIT(6)
  52 #define ID_MODE_DIS                     BIT(16)
  53
  54 #define GENET_RBUF_OFF                  0x0300
  55 #define RBUF_TBUF_SIZE_CTRL             (GENET_RBUF_OFF + 0xb4)
  56 #define RBUF_CTRL                       (GENET_RBUF_OFF + 0x00)
  57 #define RBUF_ALIGN_2B                   BIT(1)
  58
  59 #define GENET_UMAC_OFF                  0x0800
  60 #define UMAC_MIB_CTRL                   (GENET_UMAC_OFF + 0x580)
  61 #define UMAC_MAX_FRAME_LEN              (GENET_UMAC_OFF + 0x014)
  62 #define UMAC_MAC0                       (GENET_UMAC_OFF + 0x00c)
  63 #define UMAC_MAC1                       (GENET_UMAC_OFF + 0x010)
  64 #define UMAC_CMD                        (GENET_UMAC_OFF + 0x008)
  65 #define MDIO_CMD                        (GENET_UMAC_OFF + 0x614)
  66 #define UMAC_TX_FLUSH                   (GENET_UMAC_OFF + 0x334)
  67 #define MDIO_START_BUSY                 BIT(29)
  68 #define MDIO_READ_FAIL                  BIT(28)
  69 #define MDIO_RD                         (2 << 26)
  70 #define MDIO_WR                         BIT(26)
  71 #define MDIO_PMD_SHIFT                  21
  72 #define MDIO_PMD_MASK                   0x1f
  73 #define MDIO_REG_SHIFT                  16
  74 #define MDIO_REG_MASK                   0x1f
  75
  76 #define CMD_TX_EN                       BIT(0)
  77 #define CMD_RX_EN                       BIT(1)
  78 #define UMAC_SPEED_10                   0
  79 #define UMAC_SPEED_100                  1
  80 #define UMAC_SPEED_1000                 2
  81 #define UMAC_SPEED_2500                 3
  82 #define CMD_SPEED_SHIFT                 2
  83 #define CMD_SPEED_MASK                  3
  84 #define CMD_SW_RESET                    BIT(13)
  85 #define CMD_LCL_LOOP_EN                 BIT(15)
  86 #define CMD_TX_EN                       BIT(0)
  87 #define CMD_RX_EN                       BIT(1)
  88
  89 #define MIB_RESET_RX                    BIT(0)
  90 #define MIB_RESET_RUNT                  BIT(1)
  91 #define MIB_RESET_TX                    BIT(2)
  92
  93 /* total number of Buffer Descriptors, same for Rx/Tx */
  94 #define TOTAL_DESCS                     256
  95 #define RX_DESCS                        TOTAL_DESCS
  96 #define TX_DESCS                        TOTAL_DESCS
  97
  98 #define DEFAULT_Q                       0x10
  99
 100 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
 101  * 1536 is multiple of 256 bytes
 102  */
 103 #define ENET_BRCM_TAG_LEN               6
 104 #define ENET_PAD                        8
 105 #define ENET_MAX_MTU_SIZE               (ETH_DATA_LEN + ETH_HLEN +       \
 106                                          VLAN_HLEN + ENET_BRCM_TAG_LEN + \
 107                                          ETH_FCS_LEN + ENET_PAD)
 108
 109 /* Tx/Rx Dma Descriptor common bits */
 110 #define DMA_EN                          BIT(0)
 111 #define DMA_RING_BUF_EN_SHIFT           0x01
 112 #define DMA_RING_BUF_EN_MASK            0xffff
 113 #define DMA_BUFLENGTH_MASK              0x0fff
 114 #define DMA_BUFLENGTH_SHIFT             16
 115 #define DMA_RING_SIZE_SHIFT             16
 116 #define DMA_OWN                         0x8000
 117 #define DMA_EOP                         0x4000
 118 #define DMA_SOP                         0x2000
 119 #define DMA_WRAP                        0x1000
 120 #define DMA_MAX_BURST_LENGTH            0x8
 121 /* Tx specific DMA descriptor bits */
 122 #define DMA_TX_UNDERRUN                 0x0200
 123 #define DMA_TX_APPEND_CRC               0x0040
 124 #define DMA_TX_OW_CRC                   0x0020
 125 #define DMA_TX_DO_CSUM                  0x0010
 126 #define DMA_TX_QTAG_SHIFT               7
 127
 128 /* DMA rings size */
 129 #define DMA_RING_SIZE                   0x40
 130 #define DMA_RINGS_SIZE                  (DMA_RING_SIZE * (DEFAULT_Q + 1))
 131
 132 /* DMA descriptor */
 133 #define DMA_DESC_LENGTH_STATUS          0x00
 134 #define DMA_DESC_ADDRESS_LO             0x04
 135 #define DMA_DESC_ADDRESS_HI             0x08
 136 #define DMA_DESC_SIZE                   12
 137
 138 #define GENET_RX_OFF                    0x2000
 139 #define GENET_RDMA_REG_OFF                                      \
 140         (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
 141 #define GENET_TX_OFF                    0x4000
 142 #define GENET_TDMA_REG_OFF                                      \
 143         (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
 144
 145 #define DMA_FC_THRESH_HI                (RX_DESCS >> 4)
 146 #define DMA_FC_THRESH_LO                5
 147 #define DMA_FC_THRESH_VALUE             ((DMA_FC_THRESH_LO << 16) |     \
 148                                           DMA_FC_THRESH_HI)
 149
 150 #define DMA_XOFF_THRESHOLD_SHIFT        16
 151
 152 #define TDMA_RING_REG_BASE                                      \
 153         (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
 154 #define TDMA_READ_PTR                   (TDMA_RING_REG_BASE + 0x00)
 155 #define TDMA_CONS_INDEX                 (TDMA_RING_REG_BASE + 0x08)
 156 #define TDMA_PROD_INDEX                 (TDMA_RING_REG_BASE + 0x0c)
 157 #define DMA_RING_BUF_SIZE               0x10
 158 #define DMA_START_ADDR                  0x14
 159 #define DMA_END_ADDR                    0x1c
 160 #define DMA_MBUF_DONE_THRESH            0x24
 161 #define TDMA_FLOW_PERIOD                (TDMA_RING_REG_BASE + 0x28)
 162 #define TDMA_WRITE_PTR                  (TDMA_RING_REG_BASE + 0x2c)
 163
 164 #define RDMA_RING_REG_BASE                                      \
 165         (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
 166 #define RDMA_WRITE_PTR                  (RDMA_RING_REG_BASE + 0x00)
 167 #define RDMA_PROD_INDEX                 (RDMA_RING_REG_BASE + 0x08)
 168 #define RDMA_CONS_INDEX                 (RDMA_RING_REG_BASE + 0x0c)
 169 #define RDMA_XON_XOFF_THRESH            (RDMA_RING_REG_BASE + 0x28)
 170 #define RDMA_READ_PTR                   (RDMA_RING_REG_BASE + 0x2c)
 171
 172 #define TDMA_REG_BASE                   (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE)
 173 #define RDMA_REG_BASE                   (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE)
 174 #define DMA_RING_CFG                    0x00
 175 #define DMA_CTRL                        0x04
 176 #define DMA_SCB_BURST_SIZE              0x0c
 177
 178 #define RX_BUF_LENGTH                   2048
 179 #define RX_TOTAL_BUFSIZE                (RX_BUF_LENGTH * RX_DESCS)
 180 #define RX_BUF_OFFSET                   2
 181
 182 struct bcmgenet_eth_priv {
 183         char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
 184         void *mac_reg;
 185         void *tx_desc_base;
 186         void *rx_desc_base;
 187         int tx_index;
 188         int rx_index;
 189         int c_index;
 190         int phyaddr;
 191         u32 interface;
 192         u32 speed;
 193         struct phy_device *phydev;
 194         struct mii_dev *bus;
 195 };
 196
 197 static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv)
 198 {
 199         u32 reg;
 200
 201         reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
 202         reg |= BIT(1);
 203         writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
 204         udelay(10);
 205
 206         reg &= ~BIT(1);
 207         writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
 208         udelay(10);
 209
 210         writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
 211         udelay(10);
 212
 213         writel(0, priv->mac_reg + UMAC_CMD);
 214
 215         writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
 216         udelay(2);
 217         writel(0, priv->mac_reg + UMAC_CMD);
 218
 219         /* clear tx/rx counter */
 220         writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
 221                priv->mac_reg + UMAC_MIB_CTRL);
 222         writel(0, priv->mac_reg + UMAC_MIB_CTRL);
 223
 224         writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN);
 225
 226         /* init rx registers, enable ip header optimization */
 227         reg = readl(priv->mac_reg + RBUF_CTRL);
 228         reg |= RBUF_ALIGN_2B;
 229         writel(reg, (priv->mac_reg + RBUF_CTRL));
 230
 231         writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL));
 232 }
 233
 234 static int bcmgenet_gmac_write_hwaddr(struct udevice *dev)
 235 {
 236         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 237         struct eth_pdata *pdata = dev_get_platdata(dev);
 238         uchar *addr = pdata->enetaddr;
 239         u32 reg;
 240
 241         reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
 242         writel_relaxed(reg, priv->mac_reg + UMAC_MAC0);
 243
 244         reg = addr[4] << 8 | addr[5];
 245         writel_relaxed(reg, priv->mac_reg + UMAC_MAC1);
 246
 247         return 0;
 248 }
 249
 250 static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv)
 251 {
 252         clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN);
 253         clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN);
 254
 255         writel(1, priv->mac_reg + UMAC_TX_FLUSH);
 256         udelay(10);
 257         writel(0, priv->mac_reg + UMAC_TX_FLUSH);
 258 }
 259
 260 static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv)
 261 {
 262         u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
 263
 264         writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL);
 265
 266         setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl);
 267 }
 268
 269 static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length)
 270 {
 271         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 272         void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE;
 273         u32 len_stat = length << DMA_BUFLENGTH_SHIFT;
 274         ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN);
 275         u32 prod_index, cons;
 276         u32 tries = 100;
 277
 278         prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX);
 279
 280         /* There is actually no reason for the rounding here, but the ARMv7
 281          * implementation of flush_dcache_range() checks for aligned
 282          * boundaries of the flushed range.
 283          * Adjust them here to pass that check and avoid misleading messages.
 284          */
 285         flush_dcache_range(packet_aligned,
 286                            packet_aligned + roundup(length, ARCH_DMA_MINALIGN));
 287
 288         len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
 289         len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
 290
 291         /* Set-up packet for transmission */
 292         writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO));
 293         writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI));
 294         writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS));
 295
 296         /* Increment index and start transmission */
 297         if (++priv->tx_index >= TX_DESCS)
 298                 priv->tx_index = 0;
 299
 300         prod_index++;
 301
 302         /* Start Transmisson */
 303         writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX);
 304
 305         do {
 306                 cons = readl(priv->mac_reg + TDMA_CONS_INDEX);
 307         } while ((cons & 0xffff) < prod_index && --tries);
 308         if (!tries)
 309                 return -ETIMEDOUT;
 310
 311         return 0;
 312 }
 313
 314 /* Check whether all cache lines affected by an invalidate are within
 315  * the buffer, to make sure we don't accidentally lose unrelated dirty
 316  * data stored nearby.
 317  * Alignment of the buffer start address will be checked in the implementation
 318  * of invalidate_dcache_range().
 319  */
 320 static void invalidate_dcache_check(unsigned long addr, size_t size,
 321                                     size_t buffer_size)
 322 {
 323         size_t inval_size = roundup(size, ARCH_DMA_MINALIGN);
 324
 325         if (unlikely(inval_size > buffer_size))
 326                 printf("WARNING: Cache invalidate area exceeds buffer size\n");
 327
 328         invalidate_dcache_range(addr, addr + inval_size);
 329 }
 330
 331 static int bcmgenet_gmac_eth_recv(struct udevice *dev,
 332                                   int flags, uchar **packetp)
 333 {
 334         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 335         void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE;
 336         u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX);
 337         u32 length, addr;
 338
 339         if (prod_index == priv->c_index)
 340                 return -EAGAIN;
 341
 342         length = readl(desc_base + DMA_DESC_LENGTH_STATUS);
 343         length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
 344         addr = readl(desc_base + DMA_DESC_ADDRESS_LO);
 345
 346         invalidate_dcache_check(addr, length, RX_BUF_LENGTH);
 347
 348         /* To cater for the IP header alignment the hardware does.
 349          * This would actually not be needed if we don't program
 350          * RBUF_ALIGN_2B
 351          */
 352         *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET;
 353
 354         return length - RX_BUF_OFFSET;
 355 }
 356
 357 static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet,
 358                                   int length)
 359 {
 360         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 361
 362         /* Tell the MAC we have consumed that last receive buffer. */
 363         priv->c_index = (priv->c_index + 1) & 0xFFFF;
 364         writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX);
 365
 366         /* Forward our descriptor pointer, wrapping around if needed. */
 367         if (++priv->rx_index >= RX_DESCS)
 368                 priv->rx_index = 0;
 369
 370         return 0;
 371 }
 372
 373 static void rx_descs_init(struct bcmgenet_eth_priv *priv)
 374 {
 375         char *rxbuffs = &priv->rxbuffer[0];
 376         u32 len_stat, i;
 377         void *desc_base = priv->rx_desc_base;
 378
 379         priv->c_index = 0;
 380
 381         len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
 382
 383         for (i = 0; i < RX_DESCS; i++) {
 384                 writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
 385                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO);
 386                 writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
 387                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI);
 388                 writel(len_stat,
 389                        desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS);
 390         }
 391 }
 392
 393 static void rx_ring_init(struct bcmgenet_eth_priv *priv)
 394 {
 395         writel(DMA_MAX_BURST_LENGTH,
 396                priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE);
 397
 398         writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR);
 399         writel(0x0, priv->mac_reg + RDMA_READ_PTR);
 400         writel(0x0, priv->mac_reg + RDMA_WRITE_PTR);
 401         writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1,
 402                priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR);
 403
 404         writel(0x0, priv->mac_reg + RDMA_PROD_INDEX);
 405         writel(0x0, priv->mac_reg + RDMA_CONS_INDEX);
 406         writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
 407                priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
 408         writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH);
 409         writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG);
 410 }
 411
 412 static void tx_ring_init(struct bcmgenet_eth_priv *priv)
 413 {
 414         writel(DMA_MAX_BURST_LENGTH,
 415                priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE);
 416
 417         writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR);
 418         writel(0x0, priv->mac_reg + TDMA_READ_PTR);
 419         writel(0x0, priv->mac_reg + TDMA_WRITE_PTR);
 420         writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1,
 421                priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR);
 422         writel(0x0, priv->mac_reg + TDMA_PROD_INDEX);
 423         writel(0x0, priv->mac_reg + TDMA_CONS_INDEX);
 424         writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH);
 425         writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD);
 426         writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
 427                priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
 428
 429         writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG);
 430 }
 431
 432 static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv)
 433 {
 434         struct phy_device *phy_dev = priv->phydev;
 435         u32 speed;
 436
 437         switch (phy_dev->speed) {
 438         case SPEED_1000:
 439                 speed = UMAC_SPEED_1000;
 440                 break;
 441         case SPEED_100:
 442                 speed = UMAC_SPEED_100;
 443                 break;
 444         case SPEED_10:
 445                 speed = UMAC_SPEED_10;
 446                 break;
 447         default:
 448                 printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed);
 449                 return -EINVAL;
 450         }
 451
 452         clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
 453                         RGMII_LINK | RGMII_MODE_EN);
 454
 455         if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII)
 456                 setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS);
 457
 458         writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
 459
 460         return 0;
 461 }
 462
 463 static int bcmgenet_gmac_eth_start(struct udevice *dev)
 464 {
 465         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 466         int ret;
 467
 468         priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF;
 469         priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF;
 470         priv->tx_index = 0x0;
 471         priv->rx_index = 0x0;
 472
 473         bcmgenet_umac_reset(priv);
 474
 475         bcmgenet_gmac_write_hwaddr(dev);
 476
 477         /* Disable RX/TX DMA and flush TX queues */
 478         bcmgenet_disable_dma(priv);
 479
 480         rx_ring_init(priv);
 481         rx_descs_init(priv);
 482
 483         tx_ring_init(priv);
 484
 485         /* Enable RX/TX DMA */
 486         bcmgenet_enable_dma(priv);
 487
 488         /* read PHY properties over the wire from generic PHY set-up */
 489         ret = phy_startup(priv->phydev);
 490         if (ret) {
 491                 printf("bcmgenet: PHY startup failed: %d\n", ret);
 492                 return ret;
 493         }
 494
 495         /* Update MAC registers based on PHY property */
 496         ret = bcmgenet_adjust_link(priv);
 497         if (ret) {
 498                 printf("bcmgenet: adjust PHY link failed: %d\n", ret);
 499                 return ret;
 500         }
 501
 502         /* Enable Rx/Tx */
 503         setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
 504
 505         return 0;
 506 }
 507
 508 static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev)
 509 {
 510         struct phy_device *phydev;
 511         int ret;
 512
 513         phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
 514         if (!phydev)
 515                 return -ENODEV;
 516
 517         phydev->supported &= PHY_GBIT_FEATURES;
 518         if (priv->speed) {
 519                 ret = phy_set_supported(priv->phydev, priv->speed);
 520                 if (ret)
 521                         return ret;
 522         }
 523         phydev->advertising = phydev->supported;
 524
 525         phy_connect_dev(phydev, dev);
 526
 527         priv->phydev = phydev;
 528         phy_config(priv->phydev);
 529
 530         return 0;
 531 }
 532
 533 static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv)
 534 {
 535         setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY);
 536 }
 537
 538 static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad,
 539                                int reg, u16 value)
 540 {
 541         struct udevice *dev = bus->priv;
 542         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 543         u32 val;
 544
 545         /* Prepare the read operation */
 546         val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |
 547                 (reg << MDIO_REG_SHIFT) | (0xffff & value);
 548         writel_relaxed(val,  priv->mac_reg + MDIO_CMD);
 549
 550         /* Start MDIO transaction */
 551         bcmgenet_mdio_start(priv);
 552
 553         return wait_for_bit_32(priv->mac_reg + MDIO_CMD,
 554                                MDIO_START_BUSY, false, 20, true);
 555 }
 556
 557 static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
 558 {
 559         struct udevice *dev = bus->priv;
 560         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 561         u32 val;
 562         int ret;
 563
 564         /* Prepare the read operation */
 565         val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
 566         writel_relaxed(val, priv->mac_reg + MDIO_CMD);
 567
 568         /* Start MDIO transaction */
 569         bcmgenet_mdio_start(priv);
 570
 571         ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD,
 572                               MDIO_START_BUSY, false, 20, true);
 573         if (ret)
 574                 return ret;
 575
 576         val = readl_relaxed(priv->mac_reg + MDIO_CMD);
 577
 578         return val & 0xffff;
 579 }
 580
 581 static int bcmgenet_mdio_init(const char *name, struct udevice *priv)
 582 {
 583         struct mii_dev *bus = mdio_alloc();
 584
 585         if (!bus) {
 586                 debug("Failed to allocate MDIO bus\n");
 587                 return -ENOMEM;
 588         }
 589
 590         bus->read = bcmgenet_mdio_read;
 591         bus->write = bcmgenet_mdio_write;
 592         snprintf(bus->name, sizeof(bus->name), name);
 593         bus->priv = (void *)priv;
 594
 595         return mdio_register(bus);
 596 }
 597
 598 /* We only support RGMII (as used on the RPi4). */
 599 static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv)
 600 {
 601         phy_interface_t phy_mode = priv->interface;
 602
 603         switch (phy_mode) {
 604         case PHY_INTERFACE_MODE_RGMII:
 605         case PHY_INTERFACE_MODE_RGMII_RXID:
 606                 writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL);
 607                 break;
 608         default:
 609                 printf("unknown phy mode: %d\n", priv->interface);
 610                 return -EINVAL;
 611         }
 612
 613         return 0;
 614 }
 615
 616 static int bcmgenet_eth_probe(struct udevice *dev)
 617 {
 618         struct eth_pdata *pdata = dev_get_platdata(dev);
 619         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 620         ofnode mdio_node;
 621         const char *name;
 622         u32 reg;
 623         int ret;
 624         u8 major;
 625
 626         priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE);
 627         priv->interface = pdata->phy_interface;
 628         priv->speed = pdata->max_speed;
 629
 630         /* Read GENET HW version */
 631         reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL);
 632         major = (reg >> 24) & 0x0f;
 633         if (major != 6) {
 634                 if (major == 5)
 635                         major = 4;
 636                 else if (major == 0)
 637                         major = 1;
 638
 639                 printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f);
 640                 return -ENODEV;
 641         }
 642
 643         ret = bcmgenet_interface_set(priv);
 644         if (ret)
 645                 return ret;
 646
 647         writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
 648         udelay(10);
 649         /* disable MAC while updating its registers */
 650         writel(0, priv->mac_reg + UMAC_CMD);
 651         /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
 652         writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
 653
 654         mdio_node = dev_read_first_subnode(dev);
 655         name = ofnode_get_name(mdio_node);
 656
 657         ret = bcmgenet_mdio_init(name, dev);
 658         if (ret)
 659                 return ret;
 660
 661         priv->bus = miiphy_get_dev_by_name(name);
 662
 663         return bcmgenet_phy_init(priv, dev);
 664 }
 665
 666 static void bcmgenet_gmac_eth_stop(struct udevice *dev)
 667 {
 668         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 669
 670         clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
 671
 672         bcmgenet_disable_dma(priv);
 673 }
 674
 675 static const struct eth_ops bcmgenet_gmac_eth_ops = {
 676         .start                  = bcmgenet_gmac_eth_start,
 677         .write_hwaddr           = bcmgenet_gmac_write_hwaddr,
 678         .send                   = bcmgenet_gmac_eth_send,
 679         .recv                   = bcmgenet_gmac_eth_recv,
 680         .free_pkt               = bcmgenet_gmac_free_pkt,
 681         .stop                   = bcmgenet_gmac_eth_stop,
 682 };
 683
 684 static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev)
 685 {
 686         struct eth_pdata *pdata = dev_get_platdata(dev);
 687         struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
 688         struct ofnode_phandle_args phy_node;
 689         const char *phy_mode;
 690         int ret;
 691
 692         pdata->iobase = dev_read_addr(dev);
 693
 694         /* Get phy mode from DT */
 695         pdata->phy_interface = -1;
 696         phy_mode = dev_read_string(dev, "phy-mode");
 697         if (phy_mode)
 698                 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
 699         if (pdata->phy_interface == -1) {
 700                 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
 701                 return -EINVAL;
 702         }
 703
 704         ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
 705                                          &phy_node);
 706         if (!ret) {
 707                 ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr);
 708                 ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed);
 709         }
 710
 711         return 0;
 712 }
 713
 714 /* The BCM2711 implementation has a limited burst length compared to a generic
 715  * GENETv5 version, but we go with that shorter value (8) in both cases, for
 716  * the sake of simplicity.
 717  */
 718 static const struct udevice_id bcmgenet_eth_ids[] = {
 719         {.compatible = "brcm,genet-v5"},
 720         {.compatible = "brcm,bcm2711-genet-v5"},
 721         {}
 722 };
 723
 724 U_BOOT_DRIVER(eth_bcmgenet) = {
 725         .name   = "eth_bcmgenet",
 726         .id     = UCLASS_ETH,
 727         .of_match = bcmgenet_eth_ids,
 728         .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata,
 729         .probe  = bcmgenet_eth_probe,
 730         .ops    = &bcmgenet_gmac_eth_ops,
 731         .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv),
 732         .platdata_auto_alloc_size = sizeof(struct eth_pdata),
 733         .flags = DM_FLAG_ALLOC_PRIV_DMA,
 734 };