drivers/net/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/module.h>
  22 #include <linux/clk.h>
  23 #include <linux/etherdevice.h>
  24 #include <linux/delay.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/crc32.h>
  27 #include <linux/err.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/if_vlan.h>
  31
  32 #include <bcm63xx_dev_enet.h>
  33 #include "bcm63xx_enet.h"
  34
  35 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  36 static char bcm_enet_driver_version[] = "1.0";
  37
  38 static int copybreak __read_mostly = 128;
  39 module_param(copybreak, int, 0);
  40 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  41
  42 /* io memory shared between all devices */
  43 static void __iomem *bcm_enet_shared_base;
  44
  45 /*
  46  * io helpers to access mac registers
  47  */
  48 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  49 {
  50         return bcm_readl(priv->base + off);
  51 }
  52
  53 static inline void enet_writel(struct bcm_enet_priv *priv,
  54                                u32 val, u32 off)
  55 {
  56         bcm_writel(val, priv->base + off);
  57 }
  58
  59 /*
  60  * io helpers to access shared registers
  61  */
  62 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
  63 {
  64         return bcm_readl(bcm_enet_shared_base + off);
  65 }
  66
  67 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
  68                                        u32 val, u32 off)
  69 {
  70         bcm_writel(val, bcm_enet_shared_base + off);
  71 }
  72
  73 /*
  74  * write given data into mii register and wait for transfer to end
  75  * with timeout (average measured transfer time is 25us)
  76  */
  77 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
  78 {
  79         int limit;
  80
  81         /* make sure mii interrupt status is cleared */
  82         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
  83
  84         enet_writel(priv, data, ENET_MIIDATA_REG);
  85         wmb();
  86
  87         /* busy wait on mii interrupt bit, with timeout */
  88         limit = 1000;
  89         do {
  90                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
  91                         break;
  92                 udelay(1);
  93         } while (limit-- > 0);
  94
  95         return (limit < 0) ? 1 : 0;
  96 }
  97
  98 /*
  99  * MII internal read callback
 100  */
 101 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 102                               int regnum)
 103 {
 104         u32 tmp, val;
 105
 106         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 107         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 108         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 109         tmp |= ENET_MIIDATA_OP_READ_MASK;
 110
 111         if (do_mdio_op(priv, tmp))
 112                 return -1;
 113
 114         val = enet_readl(priv, ENET_MIIDATA_REG);
 115         val &= 0xffff;
 116         return val;
 117 }
 118
 119 /*
 120  * MII internal write callback
 121  */
 122 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 123                                int regnum, u16 value)
 124 {
 125         u32 tmp;
 126
 127         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 128         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 129         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 130         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 131         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 132
 133         (void)do_mdio_op(priv, tmp);
 134         return 0;
 135 }
 136
 137 /*
 138  * MII read callback from phylib
 139  */
 140 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 141                                      int regnum)
 142 {
 143         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 144 }
 145
 146 /*
 147  * MII write callback from phylib
 148  */
 149 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 150                                       int regnum, u16 value)
 151 {
 152         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 153 }
 154
 155 /*
 156  * MII read callback from mii core
 157  */
 158 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 159                                   int regnum)
 160 {
 161         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 162 }
 163
 164 /*
 165  * MII write callback from mii core
 166  */
 167 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 168                                     int regnum, int value)
 169 {
 170         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 171 }
 172
 173 /*
 174  * refill rx queue
 175  */
 176 static int bcm_enet_refill_rx(struct net_device *dev)
 177 {
 178         struct bcm_enet_priv *priv;
 179
 180         priv = netdev_priv(dev);
 181
 182         while (priv->rx_desc_count < priv->rx_ring_size) {
 183                 struct bcm_enet_desc *desc;
 184                 struct sk_buff *skb;
 185                 dma_addr_t p;
 186                 int desc_idx;
 187                 u32 len_stat;
 188
 189                 desc_idx = priv->rx_dirty_desc;
 190                 desc = &priv->rx_desc_cpu[desc_idx];
 191
 192                 if (!priv->rx_skb[desc_idx]) {
 193                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 194                         if (!skb)
 195                                 break;
 196                         priv->rx_skb[desc_idx] = skb;
 197
 198                         p = dma_map_single(&priv->pdev->dev, skb->data,
 199                                            priv->rx_skb_size,
 200                                            DMA_FROM_DEVICE);
 201                         desc->address = p;
 202                 }
 203
 204                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 205                 len_stat |= DMADESC_OWNER_MASK;
 206                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 207                         len_stat |= DMADESC_WRAP_MASK;
 208                         priv->rx_dirty_desc = 0;
 209                 } else {
 210                         priv->rx_dirty_desc++;
 211                 }
 212                 wmb();
 213                 desc->len_stat = len_stat;
 214
 215                 priv->rx_desc_count++;
 216
 217                 /* tell dma engine we allocated one buffer */
 218                 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 219         }
 220
 221         /* If rx ring is still empty, set a timer to try allocating
 222          * again at a later time. */
 223         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 224                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 225                 priv->rx_timeout.expires = jiffies + HZ;
 226                 add_timer(&priv->rx_timeout);
 227         }
 228
 229         return 0;
 230 }
 231
 232 /*
 233  * timer callback to defer refill rx queue in case we're OOM
 234  */
 235 static void bcm_enet_refill_rx_timer(unsigned long data)
 236 {
 237         struct net_device *dev;
 238         struct bcm_enet_priv *priv;
 239
 240         dev = (struct net_device *)data;
 241         priv = netdev_priv(dev);
 242
 243         spin_lock(&priv->rx_lock);
 244         bcm_enet_refill_rx((struct net_device *)data);
 245         spin_unlock(&priv->rx_lock);
 246 }
 247
 248 /*
 249  * extract packet from rx queue
 250  */
 251 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 252 {
 253         struct bcm_enet_priv *priv;
 254         struct device *kdev;
 255         int processed;
 256
 257         priv = netdev_priv(dev);
 258         kdev = &priv->pdev->dev;
 259         processed = 0;
 260
 261         /* don't scan ring further than number of refilled
 262          * descriptor */
 263         if (budget > priv->rx_desc_count)
 264                 budget = priv->rx_desc_count;
 265
 266         do {
 267                 struct bcm_enet_desc *desc;
 268                 struct sk_buff *skb;
 269                 int desc_idx;
 270                 u32 len_stat;
 271                 unsigned int len;
 272
 273                 desc_idx = priv->rx_curr_desc;
 274                 desc = &priv->rx_desc_cpu[desc_idx];
 275
 276                 /* make sure we actually read the descriptor status at
 277                  * each loop */
 278                 rmb();
 279
 280                 len_stat = desc->len_stat;
 281
 282                 /* break if dma ownership belongs to hw */
 283                 if (len_stat & DMADESC_OWNER_MASK)
 284                         break;
 285
 286                 processed++;
 287                 priv->rx_curr_desc++;
 288                 if (priv->rx_curr_desc == priv->rx_ring_size)
 289                         priv->rx_curr_desc = 0;
 290                 priv->rx_desc_count--;
 291
 292                 /* if the packet does not have start of packet _and_
 293                  * end of packet flag set, then just recycle it */
 294                 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 295                         priv->stats.rx_dropped++;
 296                         continue;
 297                 }
 298
 299                 /* recycle packet if it's marked as bad */
 300                 if (unlikely(len_stat & DMADESC_ERR_MASK)) {
 301                         priv->stats.rx_errors++;
 302
 303                         if (len_stat & DMADESC_OVSIZE_MASK)
 304                                 priv->stats.rx_length_errors++;
 305                         if (len_stat & DMADESC_CRC_MASK)
 306                                 priv->stats.rx_crc_errors++;
 307                         if (len_stat & DMADESC_UNDER_MASK)
 308                                 priv->stats.rx_frame_errors++;
 309                         if (len_stat & DMADESC_OV_MASK)
 310                                 priv->stats.rx_fifo_errors++;
 311                         continue;
 312                 }
 313
 314                 /* valid packet */
 315                 skb = priv->rx_skb[desc_idx];
 316                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 317                 /* don't include FCS */
 318                 len -= 4;
 319
 320                 if (len < copybreak) {
 321                         struct sk_buff *nskb;
 322
 323                         nskb = netdev_alloc_skb_ip_align(dev, len);
 324                         if (!nskb) {
 325                                 /* forget packet, just rearm desc */
 326                                 priv->stats.rx_dropped++;
 327                                 continue;
 328                         }
 329
 330                         dma_sync_single_for_cpu(kdev, desc->address,
 331                                                 len, DMA_FROM_DEVICE);
 332                         memcpy(nskb->data, skb->data, len);
 333                         dma_sync_single_for_device(kdev, desc->address,
 334                                                    len, DMA_FROM_DEVICE);
 335                         skb = nskb;
 336                 } else {
 337                         dma_unmap_single(&priv->pdev->dev, desc->address,
 338                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 339                         priv->rx_skb[desc_idx] = NULL;
 340                 }
 341
 342                 skb_put(skb, len);
 343                 skb->protocol = eth_type_trans(skb, dev);
 344                 priv->stats.rx_packets++;
 345                 priv->stats.rx_bytes += len;
 346                 dev->last_rx = jiffies;
 347                 netif_receive_skb(skb);
 348
 349         } while (--budget > 0);
 350
 351         if (processed || !priv->rx_desc_count) {
 352                 bcm_enet_refill_rx(dev);
 353
 354                 /* kick rx dma */
 355                 enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 356                                 ENETDMA_CHANCFG_REG(priv->rx_chan));
 357         }
 358
 359         return processed;
 360 }
 361
 362
 363 /*
 364  * try to or force reclaim of transmitted buffers
 365  */
 366 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 367 {
 368         struct bcm_enet_priv *priv;
 369         int released;
 370
 371         priv = netdev_priv(dev);
 372         released = 0;
 373
 374         while (priv->tx_desc_count < priv->tx_ring_size) {
 375                 struct bcm_enet_desc *desc;
 376                 struct sk_buff *skb;
 377
 378                 /* We run in a bh and fight against start_xmit, which
 379                  * is called with bh disabled  */
 380                 spin_lock(&priv->tx_lock);
 381
 382                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 383
 384                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 385                         spin_unlock(&priv->tx_lock);
 386                         break;
 387                 }
 388
 389                 /* ensure other field of the descriptor were not read
 390                  * before we checked ownership */
 391                 rmb();
 392
 393                 skb = priv->tx_skb[priv->tx_dirty_desc];
 394                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 395                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 396                                  DMA_TO_DEVICE);
 397
 398                 priv->tx_dirty_desc++;
 399                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 400                         priv->tx_dirty_desc = 0;
 401                 priv->tx_desc_count++;
 402
 403                 spin_unlock(&priv->tx_lock);
 404
 405                 if (desc->len_stat & DMADESC_UNDER_MASK)
 406                         priv->stats.tx_errors++;
 407
 408                 dev_kfree_skb(skb);
 409                 released++;
 410         }
 411
 412         if (netif_queue_stopped(dev) && released)
 413                 netif_wake_queue(dev);
 414
 415         return released;
 416 }
 417
 418 /*
 419  * poll func, called by network core
 420  */
 421 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 422 {
 423         struct bcm_enet_priv *priv;
 424         struct net_device *dev;
 425         int tx_work_done, rx_work_done;
 426
 427         priv = container_of(napi, struct bcm_enet_priv, napi);
 428         dev = priv->net_dev;
 429
 430         /* ack interrupts */
 431         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 432                         ENETDMA_IR_REG(priv->rx_chan));
 433         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 434                         ENETDMA_IR_REG(priv->tx_chan));
 435
 436         /* reclaim sent skb */
 437         tx_work_done = bcm_enet_tx_reclaim(dev, 0);
 438
 439         spin_lock(&priv->rx_lock);
 440         rx_work_done = bcm_enet_receive_queue(dev, budget);
 441         spin_unlock(&priv->rx_lock);
 442
 443         if (rx_work_done >= budget || tx_work_done > 0) {
 444                 /* rx/tx queue is not yet empty/clean */
 445                 return rx_work_done;
 446         }
 447
 448         /* no more packet in rx/tx queue, remove device from poll
 449          * queue */
 450         napi_complete(napi);
 451
 452         /* restore rx/tx interrupt */
 453         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 454                         ENETDMA_IRMASK_REG(priv->rx_chan));
 455         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 456                         ENETDMA_IRMASK_REG(priv->tx_chan));
 457
 458         return rx_work_done;
 459 }
 460
 461 /*
 462  * mac interrupt handler
 463  */
 464 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 465 {
 466         struct net_device *dev;
 467         struct bcm_enet_priv *priv;
 468         u32 stat;
 469
 470         dev = dev_id;
 471         priv = netdev_priv(dev);
 472
 473         stat = enet_readl(priv, ENET_IR_REG);
 474         if (!(stat & ENET_IR_MIB))
 475                 return IRQ_NONE;
 476
 477         /* clear & mask interrupt */
 478         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 479         enet_writel(priv, 0, ENET_IRMASK_REG);
 480
 481         /* read mib registers in workqueue */
 482         schedule_work(&priv->mib_update_task);
 483
 484         return IRQ_HANDLED;
 485 }
 486
 487 /*
 488  * rx/tx dma interrupt handler
 489  */
 490 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 491 {
 492         struct net_device *dev;
 493         struct bcm_enet_priv *priv;
 494
 495         dev = dev_id;
 496         priv = netdev_priv(dev);
 497
 498         /* mask rx/tx interrupts */
 499         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
 500         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 501
 502         napi_schedule(&priv->napi);
 503
 504         return IRQ_HANDLED;
 505 }
 506
 507 /*
 508  * tx request callback
 509  */
 510 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 511 {
 512         struct bcm_enet_priv *priv;
 513         struct bcm_enet_desc *desc;
 514         u32 len_stat;
 515         int ret;
 516
 517         priv = netdev_priv(dev);
 518
 519         /* lock against tx reclaim */
 520         spin_lock(&priv->tx_lock);
 521
 522         /* make sure  the tx hw queue  is not full,  should not happen
 523          * since we stop queue before it's the case */
 524         if (unlikely(!priv->tx_desc_count)) {
 525                 netif_stop_queue(dev);
 526                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 527                         "available?\n");
 528                 ret = NETDEV_TX_BUSY;
 529                 goto out_unlock;
 530         }
 531
 532         /* point to the next available desc */
 533         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 534         priv->tx_skb[priv->tx_curr_desc] = skb;
 535
 536         /* fill descriptor */
 537         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 538                                        DMA_TO_DEVICE);
 539
 540         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 541         len_stat |= DMADESC_ESOP_MASK |
 542                 DMADESC_APPEND_CRC |
 543                 DMADESC_OWNER_MASK;
 544
 545         priv->tx_curr_desc++;
 546         if (priv->tx_curr_desc == priv->tx_ring_size) {
 547                 priv->tx_curr_desc = 0;
 548                 len_stat |= DMADESC_WRAP_MASK;
 549         }
 550         priv->tx_desc_count--;
 551
 552         /* dma might be already polling, make sure we update desc
 553          * fields in correct order */
 554         wmb();
 555         desc->len_stat = len_stat;
 556         wmb();
 557
 558         /* kick tx dma */
 559         enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 560                         ENETDMA_CHANCFG_REG(priv->tx_chan));
 561
 562         /* stop queue if no more desc available */
 563         if (!priv->tx_desc_count)
 564                 netif_stop_queue(dev);
 565
 566         priv->stats.tx_bytes += skb->len;
 567         priv->stats.tx_packets++;
 568         dev->trans_start = jiffies;
 569         ret = NETDEV_TX_OK;
 570
 571 out_unlock:
 572         spin_unlock(&priv->tx_lock);
 573         return ret;
 574 }
 575
 576 /*
 577  * Change the interface's mac address.
 578  */
 579 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 580 {
 581         struct bcm_enet_priv *priv;
 582         struct sockaddr *addr = p;
 583         u32 val;
 584
 585         priv = netdev_priv(dev);
 586         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 587
 588         /* use perfect match register 0 to store my mac address */
 589         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 590                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 591         enet_writel(priv, val, ENET_PML_REG(0));
 592
 593         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 594         val |= ENET_PMH_DATAVALID_MASK;
 595         enet_writel(priv, val, ENET_PMH_REG(0));
 596
 597         return 0;
 598 }
 599
 600 /*
 601  * Change rx mode (promiscous/allmulti) and update multicast list
 602  */
 603 static void bcm_enet_set_multicast_list(struct net_device *dev)
 604 {
 605         struct bcm_enet_priv *priv;
 606         struct netdev_hw_addr *ha;
 607         u32 val;
 608         int i;
 609
 610         priv = netdev_priv(dev);
 611
 612         val = enet_readl(priv, ENET_RXCFG_REG);
 613
 614         if (dev->flags & IFF_PROMISC)
 615                 val |= ENET_RXCFG_PROMISC_MASK;
 616         else
 617                 val &= ~ENET_RXCFG_PROMISC_MASK;
 618
 619         /* only 3 perfect match registers left, first one is used for
 620          * own mac address */
 621         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 622                 val |= ENET_RXCFG_ALLMCAST_MASK;
 623         else
 624                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 625
 626         /* no need to set perfect match registers if we catch all
 627          * multicast */
 628         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 629                 enet_writel(priv, val, ENET_RXCFG_REG);
 630                 return;
 631         }
 632
 633         i = 0;
 634         netdev_for_each_mc_addr(ha, dev) {
 635                 u8 *dmi_addr;
 636                 u32 tmp;
 637
 638                 if (i == 3)
 639                         break;
 640                 /* update perfect match registers */
 641                 dmi_addr = ha->addr;
 642                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 643                         (dmi_addr[4] << 8) | dmi_addr[5];
 644                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 645
 646                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 647                 tmp |= ENET_PMH_DATAVALID_MASK;
 648                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 649         }
 650
 651         for (; i < 3; i++) {
 652                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 653                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 654         }
 655
 656         enet_writel(priv, val, ENET_RXCFG_REG);
 657 }
 658
 659 /*
 660  * set mac duplex parameters
 661  */
 662 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 663 {
 664         u32 val;
 665
 666         val = enet_readl(priv, ENET_TXCTL_REG);
 667         if (fullduplex)
 668                 val |= ENET_TXCTL_FD_MASK;
 669         else
 670                 val &= ~ENET_TXCTL_FD_MASK;
 671         enet_writel(priv, val, ENET_TXCTL_REG);
 672 }
 673
 674 /*
 675  * set mac flow control parameters
 676  */
 677 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 678 {
 679         u32 val;
 680
 681         /* rx flow control (pause frame handling) */
 682         val = enet_readl(priv, ENET_RXCFG_REG);
 683         if (rx_en)
 684                 val |= ENET_RXCFG_ENFLOW_MASK;
 685         else
 686                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 687         enet_writel(priv, val, ENET_RXCFG_REG);
 688
 689         /* tx flow control (pause frame generation) */
 690         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 691         if (tx_en)
 692                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 693         else
 694                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 695         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 696 }
 697
 698 /*
 699  * link changed callback (from phylib)
 700  */
 701 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 702 {
 703         struct bcm_enet_priv *priv;
 704         struct phy_device *phydev;
 705         int status_changed;
 706
 707         priv = netdev_priv(dev);
 708         phydev = priv->phydev;
 709         status_changed = 0;
 710
 711         if (priv->old_link != phydev->link) {
 712                 status_changed = 1;
 713                 priv->old_link = phydev->link;
 714         }
 715
 716         /* reflect duplex change in mac configuration */
 717         if (phydev->link && phydev->duplex != priv->old_duplex) {
 718                 bcm_enet_set_duplex(priv,
 719                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 720                 status_changed = 1;
 721                 priv->old_duplex = phydev->duplex;
 722         }
 723
 724         /* enable flow control if remote advertise it (trust phylib to
 725          * check that duplex is full */
 726         if (phydev->link && phydev->pause != priv->old_pause) {
 727                 int rx_pause_en, tx_pause_en;
 728
 729                 if (phydev->pause) {
 730                         /* pause was advertised by lpa and us */
 731                         rx_pause_en = 1;
 732                         tx_pause_en = 1;
 733                 } else if (!priv->pause_auto) {
 734                         /* pause setting overrided by user */
 735                         rx_pause_en = priv->pause_rx;
 736                         tx_pause_en = priv->pause_tx;
 737                 } else {
 738                         rx_pause_en = 0;
 739                         tx_pause_en = 0;
 740                 }
 741
 742                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 743                 status_changed = 1;
 744                 priv->old_pause = phydev->pause;
 745         }
 746
 747         if (status_changed) {
 748                 pr_info("%s: link %s", dev->name, phydev->link ?
 749                         "UP" : "DOWN");
 750                 if (phydev->link)
 751                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 752                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 753                                phydev->pause == 1 ? "rx&tx" : "off");
 754
 755                 pr_cont("\n");
 756         }
 757 }
 758
 759 /*
 760  * link changed callback (if phylib is not used)
 761  */
 762 static void bcm_enet_adjust_link(struct net_device *dev)
 763 {
 764         struct bcm_enet_priv *priv;
 765
 766         priv = netdev_priv(dev);
 767         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 768         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 769         netif_carrier_on(dev);
 770
 771         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 772                 dev->name,
 773                 priv->force_speed_100 ? 100 : 10,
 774                 priv->force_duplex_full ? "full" : "half",
 775                 priv->pause_rx ? "rx" : "off",
 776                 priv->pause_tx ? "tx" : "off");
 777 }
 778
 779 /*
 780  * open callback, allocate dma rings & buffers and start rx operation
 781  */
 782 static int bcm_enet_open(struct net_device *dev)
 783 {
 784         struct bcm_enet_priv *priv;
 785         struct sockaddr addr;
 786         struct device *kdev;
 787         struct phy_device *phydev;
 788         int i, ret;
 789         unsigned int size;
 790         char phy_id[MII_BUS_ID_SIZE + 3];
 791         void *p;
 792         u32 val;
 793
 794         priv = netdev_priv(dev);
 795         kdev = &priv->pdev->dev;
 796
 797         if (priv->has_phy) {
 798                 /* connect to PHY */
 799                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 800                          priv->mac_id ? "1" : "0", priv->phy_id);
 801
 802                 phydev = phy_connect(dev, phy_id, &bcm_enet_adjust_phy_link, 0,
 803                                      PHY_INTERFACE_MODE_MII);
 804
 805                 if (IS_ERR(phydev)) {
 806                         dev_err(kdev, "could not attach to PHY\n");
 807                         return PTR_ERR(phydev);
 808                 }
 809
 810                 /* mask with MAC supported features */
 811                 phydev->supported &= (SUPPORTED_10baseT_Half |
 812                                       SUPPORTED_10baseT_Full |
 813                                       SUPPORTED_100baseT_Half |
 814                                       SUPPORTED_100baseT_Full |
 815                                       SUPPORTED_Autoneg |
 816                                       SUPPORTED_Pause |
 817                                       SUPPORTED_MII);
 818                 phydev->advertising = phydev->supported;
 819
 820                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 821                         phydev->advertising |= SUPPORTED_Pause;
 822                 else
 823                         phydev->advertising &= ~SUPPORTED_Pause;
 824
 825                 dev_info(kdev, "attached PHY at address %d [%s]\n",
 826                          phydev->addr, phydev->drv->name);
 827
 828                 priv->old_link = 0;
 829                 priv->old_duplex = -1;
 830                 priv->old_pause = -1;
 831                 priv->phydev = phydev;
 832         }
 833
 834         /* mask all interrupts and request them */
 835         enet_writel(priv, 0, ENET_IRMASK_REG);
 836         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
 837         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
 838
 839         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 840         if (ret)
 841                 goto out_phy_disconnect;
 842
 843         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
 844                           IRQF_SAMPLE_RANDOM | IRQF_DISABLED, dev->name, dev);
 845         if (ret)
 846                 goto out_freeirq;
 847
 848         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 849                           IRQF_DISABLED, dev->name, dev);
 850         if (ret)
 851                 goto out_freeirq_rx;
 852
 853         /* initialize perfect match registers */
 854         for (i = 0; i < 4; i++) {
 855                 enet_writel(priv, 0, ENET_PML_REG(i));
 856                 enet_writel(priv, 0, ENET_PMH_REG(i));
 857         }
 858
 859         /* write device mac address */
 860         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 861         bcm_enet_set_mac_address(dev, &addr);
 862
 863         /* allocate rx dma ring */
 864         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 865         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 866         if (!p) {
 867                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
 868                 ret = -ENOMEM;
 869                 goto out_freeirq_tx;
 870         }
 871
 872         memset(p, 0, size);
 873         priv->rx_desc_alloc_size = size;
 874         priv->rx_desc_cpu = p;
 875
 876         /* allocate tx dma ring */
 877         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 878         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 879         if (!p) {
 880                 dev_err(kdev, "cannot allocate tx ring\n");
 881                 ret = -ENOMEM;
 882                 goto out_free_rx_ring;
 883         }
 884
 885         memset(p, 0, size);
 886         priv->tx_desc_alloc_size = size;
 887         priv->tx_desc_cpu = p;
 888
 889         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
 890                                GFP_KERNEL);
 891         if (!priv->tx_skb) {
 892                 dev_err(kdev, "cannot allocate rx skb queue\n");
 893                 ret = -ENOMEM;
 894                 goto out_free_tx_ring;
 895         }
 896
 897         priv->tx_desc_count = priv->tx_ring_size;
 898         priv->tx_dirty_desc = 0;
 899         priv->tx_curr_desc = 0;
 900         spin_lock_init(&priv->tx_lock);
 901
 902         /* init & fill rx ring with skbs */
 903         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
 904                                GFP_KERNEL);
 905         if (!priv->rx_skb) {
 906                 dev_err(kdev, "cannot allocate rx skb queue\n");
 907                 ret = -ENOMEM;
 908                 goto out_free_tx_skb;
 909         }
 910
 911         priv->rx_desc_count = 0;
 912         priv->rx_dirty_desc = 0;
 913         priv->rx_curr_desc = 0;
 914
 915         /* initialize flow control buffer allocation */
 916         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 917                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
 918
 919         if (bcm_enet_refill_rx(dev)) {
 920                 dev_err(kdev, "cannot allocate rx skb queue\n");
 921                 ret = -ENOMEM;
 922                 goto out;
 923         }
 924
 925         /* write rx & tx ring addresses */
 926         enet_dma_writel(priv, priv->rx_desc_dma,
 927                         ENETDMA_RSTART_REG(priv->rx_chan));
 928         enet_dma_writel(priv, priv->tx_desc_dma,
 929                         ENETDMA_RSTART_REG(priv->tx_chan));
 930
 931         /* clear remaining state ram for rx & tx channel */
 932         enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan));
 933         enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan));
 934         enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan));
 935         enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan));
 936         enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan));
 937         enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan));
 938
 939         /* set max rx/tx length */
 940         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
 941         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
 942
 943         /* set dma maximum burst len */
 944         enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
 945                         ENETDMA_MAXBURST_REG(priv->rx_chan));
 946         enet_dma_writel(priv, BCMENET_DMA_MAXBURST,
 947                         ENETDMA_MAXBURST_REG(priv->tx_chan));
 948
 949         /* set correct transmit fifo watermark */
 950         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
 951
 952         /* set flow control low/high threshold to 1/3 / 2/3 */
 953         val = priv->rx_ring_size / 3;
 954         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
 955         val = (priv->rx_ring_size * 2) / 3;
 956         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
 957
 958         /* all set, enable mac and interrupts, start dma engine and
 959          * kick rx dma channel */
 960         wmb();
 961         enet_writel(priv, ENET_CTL_ENABLE_MASK, ENET_CTL_REG);
 962         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
 963         enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK,
 964                         ENETDMA_CHANCFG_REG(priv->rx_chan));
 965
 966         /* watch "mib counters about to overflow" interrupt */
 967         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 968         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
 969
 970         /* watch "packet transferred" interrupt in rx and tx */
 971         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 972                         ENETDMA_IR_REG(priv->rx_chan));
 973         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 974                         ENETDMA_IR_REG(priv->tx_chan));
 975
 976         /* make sure we enable napi before rx interrupt  */
 977         napi_enable(&priv->napi);
 978
 979         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 980                         ENETDMA_IRMASK_REG(priv->rx_chan));
 981         enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK,
 982                         ENETDMA_IRMASK_REG(priv->tx_chan));
 983
 984         if (priv->has_phy)
 985                 phy_start(priv->phydev);
 986         else
 987                 bcm_enet_adjust_link(dev);
 988
 989         netif_start_queue(dev);
 990         return 0;
 991
 992 out:
 993         for (i = 0; i < priv->rx_ring_size; i++) {
 994                 struct bcm_enet_desc *desc;
 995
 996                 if (!priv->rx_skb[i])
 997                         continue;
 998
 999                 desc = &priv->rx_desc_cpu[i];
1000                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1001                                  DMA_FROM_DEVICE);
1002                 kfree_skb(priv->rx_skb[i]);
1003         }
1004         kfree(priv->rx_skb);
1005
1006 out_free_tx_skb:
1007         kfree(priv->tx_skb);
1008
1009 out_free_tx_ring:
1010         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1011                           priv->tx_desc_cpu, priv->tx_desc_dma);
1012
1013 out_free_rx_ring:
1014         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1015                           priv->rx_desc_cpu, priv->rx_desc_dma);
1016
1017 out_freeirq_tx:
1018         free_irq(priv->irq_tx, dev);
1019
1020 out_freeirq_rx:
1021         free_irq(priv->irq_rx, dev);
1022
1023 out_freeirq:
1024         free_irq(dev->irq, dev);
1025
1026 out_phy_disconnect:
1027         phy_disconnect(priv->phydev);
1028
1029         return ret;
1030 }
1031
1032 /*
1033  * disable mac
1034  */
1035 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1036 {
1037         int limit;
1038         u32 val;
1039
1040         val = enet_readl(priv, ENET_CTL_REG);
1041         val |= ENET_CTL_DISABLE_MASK;
1042         enet_writel(priv, val, ENET_CTL_REG);
1043
1044         limit = 1000;
1045         do {
1046                 u32 val;
1047
1048                 val = enet_readl(priv, ENET_CTL_REG);
1049                 if (!(val & ENET_CTL_DISABLE_MASK))
1050                         break;
1051                 udelay(1);
1052         } while (limit--);
1053 }
1054
1055 /*
1056  * disable dma in given channel
1057  */
1058 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1059 {
1060         int limit;
1061
1062         enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan));
1063
1064         limit = 1000;
1065         do {
1066                 u32 val;
1067
1068                 val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan));
1069                 if (!(val & ENETDMA_CHANCFG_EN_MASK))
1070                         break;
1071                 udelay(1);
1072         } while (limit--);
1073 }
1074
1075 /*
1076  * stop callback
1077  */
1078 static int bcm_enet_stop(struct net_device *dev)
1079 {
1080         struct bcm_enet_priv *priv;
1081         struct device *kdev;
1082         int i;
1083
1084         priv = netdev_priv(dev);
1085         kdev = &priv->pdev->dev;
1086
1087         netif_stop_queue(dev);
1088         napi_disable(&priv->napi);
1089         if (priv->has_phy)
1090                 phy_stop(priv->phydev);
1091         del_timer_sync(&priv->rx_timeout);
1092
1093         /* mask all interrupts */
1094         enet_writel(priv, 0, ENET_IRMASK_REG);
1095         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan));
1096         enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan));
1097
1098         /* make sure no mib update is scheduled */
1099         flush_scheduled_work();
1100
1101         /* disable dma & mac */
1102         bcm_enet_disable_dma(priv, priv->tx_chan);
1103         bcm_enet_disable_dma(priv, priv->rx_chan);
1104         bcm_enet_disable_mac(priv);
1105
1106         /* force reclaim of all tx buffers */
1107         bcm_enet_tx_reclaim(dev, 1);
1108
1109         /* free the rx skb ring */
1110         for (i = 0; i < priv->rx_ring_size; i++) {
1111                 struct bcm_enet_desc *desc;
1112
1113                 if (!priv->rx_skb[i])
1114                         continue;
1115
1116                 desc = &priv->rx_desc_cpu[i];
1117                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1118                                  DMA_FROM_DEVICE);
1119                 kfree_skb(priv->rx_skb[i]);
1120         }
1121
1122         /* free remaining allocated memory */
1123         kfree(priv->rx_skb);
1124         kfree(priv->tx_skb);
1125         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1126                           priv->rx_desc_cpu, priv->rx_desc_dma);
1127         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1128                           priv->tx_desc_cpu, priv->tx_desc_dma);
1129         free_irq(priv->irq_tx, dev);
1130         free_irq(priv->irq_rx, dev);
1131         free_irq(dev->irq, dev);
1132
1133         /* release phy */
1134         if (priv->has_phy) {
1135                 phy_disconnect(priv->phydev);
1136                 priv->phydev = NULL;
1137         }
1138
1139         return 0;
1140 }
1141
1142 /*
1143  * core request to return device rx/tx stats
1144  */
1145 static struct net_device_stats *bcm_enet_get_stats(struct net_device *dev)
1146 {
1147         struct bcm_enet_priv *priv;
1148
1149         priv = netdev_priv(dev);
1150         return &priv->stats;
1151 }
1152
1153 /*
1154  * ethtool callbacks
1155  */
1156 struct bcm_enet_stats {
1157         char stat_string[ETH_GSTRING_LEN];
1158         int sizeof_stat;
1159         int stat_offset;
1160         int mib_reg;
1161 };
1162
1163 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1164                      offsetof(struct bcm_enet_priv, m)
1165
1166 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1167         { "rx_packets", GEN_STAT(stats.rx_packets), -1 },
1168         { "tx_packets", GEN_STAT(stats.tx_packets), -1 },
1169         { "rx_bytes", GEN_STAT(stats.rx_bytes), -1 },
1170         { "tx_bytes", GEN_STAT(stats.tx_bytes), -1 },
1171         { "rx_errors", GEN_STAT(stats.rx_errors), -1 },
1172         { "tx_errors", GEN_STAT(stats.tx_errors), -1 },
1173         { "rx_dropped", GEN_STAT(stats.rx_dropped), -1 },
1174         { "tx_dropped", GEN_STAT(stats.tx_dropped), -1 },
1175
1176         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1177         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1178         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1179         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1180         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1181         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1182         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1183         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1184         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1185         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1186         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1187         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1188         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1189         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1190         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1191         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1192         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1193         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1194         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1195         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1196         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1197
1198         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1199         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1200         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1201         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1202         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1203         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1204         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1205         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1206         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1207         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1208         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1209         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1210         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1211         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1212         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1213         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1214         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1215         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1216         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1217         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1218         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1219         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1220
1221 };
1222
1223 #define BCM_ENET_STATS_LEN      \
1224         (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats))
1225
1226 static const u32 unused_mib_regs[] = {
1227         ETH_MIB_TX_ALL_OCTETS,
1228         ETH_MIB_TX_ALL_PKTS,
1229         ETH_MIB_RX_ALL_OCTETS,
1230         ETH_MIB_RX_ALL_PKTS,
1231 };
1232
1233
1234 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1235                                  struct ethtool_drvinfo *drvinfo)
1236 {
1237         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
1238         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
1239         strncpy(drvinfo->fw_version, "N/A", 32);
1240         strncpy(drvinfo->bus_info, "bcm63xx", 32);
1241         drvinfo->n_stats = BCM_ENET_STATS_LEN;
1242 }
1243
1244 static int bcm_enet_get_sset_count(struct net_device *netdev,
1245                                         int string_set)
1246 {
1247         switch (string_set) {
1248         case ETH_SS_STATS:
1249                 return BCM_ENET_STATS_LEN;
1250         default:
1251                 return -EINVAL;
1252         }
1253 }
1254
1255 static void bcm_enet_get_strings(struct net_device *netdev,
1256                                  u32 stringset, u8 *data)
1257 {
1258         int i;
1259
1260         switch (stringset) {
1261         case ETH_SS_STATS:
1262                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1263                         memcpy(data + i * ETH_GSTRING_LEN,
1264                                bcm_enet_gstrings_stats[i].stat_string,
1265                                ETH_GSTRING_LEN);
1266                 }
1267                 break;
1268         }
1269 }
1270
1271 static void update_mib_counters(struct bcm_enet_priv *priv)
1272 {
1273         int i;
1274
1275         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1276                 const struct bcm_enet_stats *s;
1277                 u32 val;
1278                 char *p;
1279
1280                 s = &bcm_enet_gstrings_stats[i];
1281                 if (s->mib_reg == -1)
1282                         continue;
1283
1284                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1285                 p = (char *)priv + s->stat_offset;
1286
1287                 if (s->sizeof_stat == sizeof(u64))
1288                         *(u64 *)p += val;
1289                 else
1290                         *(u32 *)p += val;
1291         }
1292
1293         /* also empty unused mib counters to make sure mib counter
1294          * overflow interrupt is cleared */
1295         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1296                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1297 }
1298
1299 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1300 {
1301         struct bcm_enet_priv *priv;
1302
1303         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1304         mutex_lock(&priv->mib_update_lock);
1305         update_mib_counters(priv);
1306         mutex_unlock(&priv->mib_update_lock);
1307
1308         /* reenable mib interrupt */
1309         if (netif_running(priv->net_dev))
1310                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1311 }
1312
1313 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1314                                        struct ethtool_stats *stats,
1315                                        u64 *data)
1316 {
1317         struct bcm_enet_priv *priv;
1318         int i;
1319
1320         priv = netdev_priv(netdev);
1321
1322         mutex_lock(&priv->mib_update_lock);
1323         update_mib_counters(priv);
1324
1325         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1326                 const struct bcm_enet_stats *s;
1327                 char *p;
1328
1329                 s = &bcm_enet_gstrings_stats[i];
1330                 p = (char *)priv + s->stat_offset;
1331                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1332                         *(u64 *)p : *(u32 *)p;
1333         }
1334         mutex_unlock(&priv->mib_update_lock);
1335 }
1336
1337 static int bcm_enet_get_settings(struct net_device *dev,
1338                                  struct ethtool_cmd *cmd)
1339 {
1340         struct bcm_enet_priv *priv;
1341
1342         priv = netdev_priv(dev);
1343
1344         cmd->maxrxpkt = 0;
1345         cmd->maxtxpkt = 0;
1346
1347         if (priv->has_phy) {
1348                 if (!priv->phydev)
1349                         return -ENODEV;
1350                 return phy_ethtool_gset(priv->phydev, cmd);
1351         } else {
1352                 cmd->autoneg = 0;
1353                 cmd->speed = (priv->force_speed_100) ? SPEED_100 : SPEED_10;
1354                 cmd->duplex = (priv->force_duplex_full) ?
1355                         DUPLEX_FULL : DUPLEX_HALF;
1356                 cmd->supported = ADVERTISED_10baseT_Half  |
1357                         ADVERTISED_10baseT_Full |
1358                         ADVERTISED_100baseT_Half |
1359                         ADVERTISED_100baseT_Full;
1360                 cmd->advertising = 0;
1361                 cmd->port = PORT_MII;
1362                 cmd->transceiver = XCVR_EXTERNAL;
1363         }
1364         return 0;
1365 }
1366
1367 static int bcm_enet_set_settings(struct net_device *dev,
1368                                  struct ethtool_cmd *cmd)
1369 {
1370         struct bcm_enet_priv *priv;
1371
1372         priv = netdev_priv(dev);
1373         if (priv->has_phy) {
1374                 if (!priv->phydev)
1375                         return -ENODEV;
1376                 return phy_ethtool_sset(priv->phydev, cmd);
1377         } else {
1378
1379                 if (cmd->autoneg ||
1380                     (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1381                     cmd->port != PORT_MII)
1382                         return -EINVAL;
1383
1384                 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1385                 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1386
1387                 if (netif_running(dev))
1388                         bcm_enet_adjust_link(dev);
1389                 return 0;
1390         }
1391 }
1392
1393 static void bcm_enet_get_ringparam(struct net_device *dev,
1394                                    struct ethtool_ringparam *ering)
1395 {
1396         struct bcm_enet_priv *priv;
1397
1398         priv = netdev_priv(dev);
1399
1400         /* rx/tx ring is actually only limited by memory */
1401         ering->rx_max_pending = 8192;
1402         ering->tx_max_pending = 8192;
1403         ering->rx_mini_max_pending = 0;
1404         ering->rx_jumbo_max_pending = 0;
1405         ering->rx_pending = priv->rx_ring_size;
1406         ering->tx_pending = priv->tx_ring_size;
1407 }
1408
1409 static int bcm_enet_set_ringparam(struct net_device *dev,
1410                                   struct ethtool_ringparam *ering)
1411 {
1412         struct bcm_enet_priv *priv;
1413         int was_running;
1414
1415         priv = netdev_priv(dev);
1416
1417         was_running = 0;
1418         if (netif_running(dev)) {
1419                 bcm_enet_stop(dev);
1420                 was_running = 1;
1421         }
1422
1423         priv->rx_ring_size = ering->rx_pending;
1424         priv->tx_ring_size = ering->tx_pending;
1425
1426         if (was_running) {
1427                 int err;
1428
1429                 err = bcm_enet_open(dev);
1430                 if (err)
1431                         dev_close(dev);
1432                 else
1433                         bcm_enet_set_multicast_list(dev);
1434         }
1435         return 0;
1436 }
1437
1438 static void bcm_enet_get_pauseparam(struct net_device *dev,
1439                                     struct ethtool_pauseparam *ecmd)
1440 {
1441         struct bcm_enet_priv *priv;
1442
1443         priv = netdev_priv(dev);
1444         ecmd->autoneg = priv->pause_auto;
1445         ecmd->rx_pause = priv->pause_rx;
1446         ecmd->tx_pause = priv->pause_tx;
1447 }
1448
1449 static int bcm_enet_set_pauseparam(struct net_device *dev,
1450                                    struct ethtool_pauseparam *ecmd)
1451 {
1452         struct bcm_enet_priv *priv;
1453
1454         priv = netdev_priv(dev);
1455
1456         if (priv->has_phy) {
1457                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1458                         /* asymetric pause mode not supported,
1459                          * actually possible but integrated PHY has RO
1460                          * asym_pause bit */
1461                         return -EINVAL;
1462                 }
1463         } else {
1464                 /* no pause autoneg on direct mii connection */
1465                 if (ecmd->autoneg)
1466                         return -EINVAL;
1467         }
1468
1469         priv->pause_auto = ecmd->autoneg;
1470         priv->pause_rx = ecmd->rx_pause;
1471         priv->pause_tx = ecmd->tx_pause;
1472
1473         return 0;
1474 }
1475
1476 static struct ethtool_ops bcm_enet_ethtool_ops = {
1477         .get_strings            = bcm_enet_get_strings,
1478         .get_sset_count         = bcm_enet_get_sset_count,
1479         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1480         .get_settings           = bcm_enet_get_settings,
1481         .set_settings           = bcm_enet_set_settings,
1482         .get_drvinfo            = bcm_enet_get_drvinfo,
1483         .get_link               = ethtool_op_get_link,
1484         .get_ringparam          = bcm_enet_get_ringparam,
1485         .set_ringparam          = bcm_enet_set_ringparam,
1486         .get_pauseparam         = bcm_enet_get_pauseparam,
1487         .set_pauseparam         = bcm_enet_set_pauseparam,
1488 };
1489
1490 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1491 {
1492         struct bcm_enet_priv *priv;
1493
1494         priv = netdev_priv(dev);
1495         if (priv->has_phy) {
1496                 if (!priv->phydev)
1497                         return -ENODEV;
1498                 return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1499         } else {
1500                 struct mii_if_info mii;
1501
1502                 mii.dev = dev;
1503                 mii.mdio_read = bcm_enet_mdio_read_mii;
1504                 mii.mdio_write = bcm_enet_mdio_write_mii;
1505                 mii.phy_id = 0;
1506                 mii.phy_id_mask = 0x3f;
1507                 mii.reg_num_mask = 0x1f;
1508                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1509         }
1510 }
1511
1512 /*
1513  * calculate actual hardware mtu
1514  */
1515 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1516 {
1517         int actual_mtu;
1518
1519         actual_mtu = mtu;
1520
1521         /* add ethernet header + vlan tag size */
1522         actual_mtu += VLAN_ETH_HLEN;
1523
1524         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1525                 return -EINVAL;
1526
1527         /*
1528          * setup maximum size before we get overflow mark in
1529          * descriptor, note that this will not prevent reception of
1530          * big frames, they will be split into multiple buffers
1531          * anyway
1532          */
1533         priv->hw_mtu = actual_mtu;
1534
1535         /*
1536          * align rx buffer size to dma burst len, account FCS since
1537          * it's appended
1538          */
1539         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1540                                   BCMENET_DMA_MAXBURST * 4);
1541         return 0;
1542 }
1543
1544 /*
1545  * adjust mtu, can't be called while device is running
1546  */
1547 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1548 {
1549         int ret;
1550
1551         if (netif_running(dev))
1552                 return -EBUSY;
1553
1554         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1555         if (ret)
1556                 return ret;
1557         dev->mtu = new_mtu;
1558         return 0;
1559 }
1560
1561 /*
1562  * preinit hardware to allow mii operation while device is down
1563  */
1564 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1565 {
1566         u32 val;
1567         int limit;
1568
1569         /* make sure mac is disabled */
1570         bcm_enet_disable_mac(priv);
1571
1572         /* soft reset mac */
1573         val = ENET_CTL_SRESET_MASK;
1574         enet_writel(priv, val, ENET_CTL_REG);
1575         wmb();
1576
1577         limit = 1000;
1578         do {
1579                 val = enet_readl(priv, ENET_CTL_REG);
1580                 if (!(val & ENET_CTL_SRESET_MASK))
1581                         break;
1582                 udelay(1);
1583         } while (limit--);
1584
1585         /* select correct mii interface */
1586         val = enet_readl(priv, ENET_CTL_REG);
1587         if (priv->use_external_mii)
1588                 val |= ENET_CTL_EPHYSEL_MASK;
1589         else
1590                 val &= ~ENET_CTL_EPHYSEL_MASK;
1591         enet_writel(priv, val, ENET_CTL_REG);
1592
1593         /* turn on mdc clock */
1594         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1595                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1596
1597         /* set mib counters to self-clear when read */
1598         val = enet_readl(priv, ENET_MIBCTL_REG);
1599         val |= ENET_MIBCTL_RDCLEAR_MASK;
1600         enet_writel(priv, val, ENET_MIBCTL_REG);
1601 }
1602
1603 static const struct net_device_ops bcm_enet_ops = {
1604         .ndo_open               = bcm_enet_open,
1605         .ndo_stop               = bcm_enet_stop,
1606         .ndo_start_xmit         = bcm_enet_start_xmit,
1607         .ndo_get_stats          = bcm_enet_get_stats,
1608         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1609         .ndo_set_multicast_list = bcm_enet_set_multicast_list,
1610         .ndo_do_ioctl           = bcm_enet_ioctl,
1611         .ndo_change_mtu         = bcm_enet_change_mtu,
1612 #ifdef CONFIG_NET_POLL_CONTROLLER
1613         .ndo_poll_controller = bcm_enet_netpoll,
1614 #endif
1615 };
1616
1617 /*
1618  * allocate netdevice, request register memory and register device.
1619  */
1620 static int __devinit bcm_enet_probe(struct platform_device *pdev)
1621 {
1622         struct bcm_enet_priv *priv;
1623         struct net_device *dev;
1624         struct bcm63xx_enet_platform_data *pd;
1625         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1626         struct mii_bus *bus;
1627         const char *clk_name;
1628         unsigned int iomem_size;
1629         int i, ret;
1630
1631         /* stop if shared driver failed, assume driver->probe will be
1632          * called in the same order we register devices (correct ?) */
1633         if (!bcm_enet_shared_base)
1634                 return -ENODEV;
1635
1636         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1637         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1638         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1639         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1640         if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx)
1641                 return -ENODEV;
1642
1643         ret = 0;
1644         dev = alloc_etherdev(sizeof(*priv));
1645         if (!dev)
1646                 return -ENOMEM;
1647         priv = netdev_priv(dev);
1648         memset(priv, 0, sizeof(*priv));
1649
1650         ret = compute_hw_mtu(priv, dev->mtu);
1651         if (ret)
1652                 goto out;
1653
1654         iomem_size = res_mem->end - res_mem->start + 1;
1655         if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) {
1656                 ret = -EBUSY;
1657                 goto out;
1658         }
1659
1660         priv->base = ioremap(res_mem->start, iomem_size);
1661         if (priv->base == NULL) {
1662                 ret = -ENOMEM;
1663                 goto out_release_mem;
1664         }
1665         dev->irq = priv->irq = res_irq->start;
1666         priv->irq_rx = res_irq_rx->start;
1667         priv->irq_tx = res_irq_tx->start;
1668         priv->mac_id = pdev->id;
1669
1670         /* get rx & tx dma channel id for this mac */
1671         if (priv->mac_id == 0) {
1672                 priv->rx_chan = 0;
1673                 priv->tx_chan = 1;
1674                 clk_name = "enet0";
1675         } else {
1676                 priv->rx_chan = 2;
1677                 priv->tx_chan = 3;
1678                 clk_name = "enet1";
1679         }
1680
1681         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1682         if (IS_ERR(priv->mac_clk)) {
1683                 ret = PTR_ERR(priv->mac_clk);
1684                 goto out_unmap;
1685         }
1686         clk_enable(priv->mac_clk);
1687
1688         /* initialize default and fetch platform data */
1689         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1690         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1691
1692         pd = pdev->dev.platform_data;
1693         if (pd) {
1694                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1695                 priv->has_phy = pd->has_phy;
1696                 priv->phy_id = pd->phy_id;
1697                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1698                 priv->phy_interrupt = pd->phy_interrupt;
1699                 priv->use_external_mii = !pd->use_internal_phy;
1700                 priv->pause_auto = pd->pause_auto;
1701                 priv->pause_rx = pd->pause_rx;
1702                 priv->pause_tx = pd->pause_tx;
1703                 priv->force_duplex_full = pd->force_duplex_full;
1704                 priv->force_speed_100 = pd->force_speed_100;
1705         }
1706
1707         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1708                 /* using internal PHY, enable clock */
1709                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1710                 if (IS_ERR(priv->phy_clk)) {
1711                         ret = PTR_ERR(priv->phy_clk);
1712                         priv->phy_clk = NULL;
1713                         goto out_put_clk_mac;
1714                 }
1715                 clk_enable(priv->phy_clk);
1716         }
1717
1718         /* do minimal hardware init to be able to probe mii bus */
1719         bcm_enet_hw_preinit(priv);
1720
1721         /* MII bus registration */
1722         if (priv->has_phy) {
1723
1724                 priv->mii_bus = mdiobus_alloc();
1725                 if (!priv->mii_bus) {
1726                         ret = -ENOMEM;
1727                         goto out_uninit_hw;
1728                 }
1729
1730                 bus = priv->mii_bus;
1731                 bus->name = "bcm63xx_enet MII bus";
1732                 bus->parent = &pdev->dev;
1733                 bus->priv = priv;
1734                 bus->read = bcm_enet_mdio_read_phylib;
1735                 bus->write = bcm_enet_mdio_write_phylib;
1736                 sprintf(bus->id, "%d", priv->mac_id);
1737
1738                 /* only probe bus where we think the PHY is, because
1739                  * the mdio read operation return 0 instead of 0xffff
1740                  * if a slave is not present on hw */
1741                 bus->phy_mask = ~(1 << priv->phy_id);
1742
1743                 bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1744                 if (!bus->irq) {
1745                         ret = -ENOMEM;
1746                         goto out_free_mdio;
1747                 }
1748
1749                 if (priv->has_phy_interrupt)
1750                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1751                 else
1752                         bus->irq[priv->phy_id] = PHY_POLL;
1753
1754                 ret = mdiobus_register(bus);
1755                 if (ret) {
1756                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1757                         goto out_free_mdio;
1758                 }
1759         } else {
1760
1761                 /* run platform code to initialize PHY device */
1762                 if (pd->mii_config &&
1763                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1764                                    bcm_enet_mdio_write_mii)) {
1765                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1766                         goto out_uninit_hw;
1767                 }
1768         }
1769
1770         spin_lock_init(&priv->rx_lock);
1771
1772         /* init rx timeout (used for oom) */
1773         init_timer(&priv->rx_timeout);
1774         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1775         priv->rx_timeout.data = (unsigned long)dev;
1776
1777         /* init the mib update lock&work */
1778         mutex_init(&priv->mib_update_lock);
1779         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1780
1781         /* zero mib counters */
1782         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1783                 enet_writel(priv, 0, ENET_MIB_REG(i));
1784
1785         /* register netdevice */
1786         dev->netdev_ops = &bcm_enet_ops;
1787         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1788
1789         SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops);
1790         SET_NETDEV_DEV(dev, &pdev->dev);
1791
1792         ret = register_netdev(dev);
1793         if (ret)
1794                 goto out_unregister_mdio;
1795
1796         netif_carrier_off(dev);
1797         platform_set_drvdata(pdev, dev);
1798         priv->pdev = pdev;
1799         priv->net_dev = dev;
1800
1801         return 0;
1802
1803 out_unregister_mdio:
1804         if (priv->mii_bus) {
1805                 mdiobus_unregister(priv->mii_bus);
1806                 kfree(priv->mii_bus->irq);
1807         }
1808
1809 out_free_mdio:
1810         if (priv->mii_bus)
1811                 mdiobus_free(priv->mii_bus);
1812
1813 out_uninit_hw:
1814         /* turn off mdc clock */
1815         enet_writel(priv, 0, ENET_MIISC_REG);
1816         if (priv->phy_clk) {
1817                 clk_disable(priv->phy_clk);
1818                 clk_put(priv->phy_clk);
1819         }
1820
1821 out_put_clk_mac:
1822         clk_disable(priv->mac_clk);
1823         clk_put(priv->mac_clk);
1824
1825 out_unmap:
1826         iounmap(priv->base);
1827
1828 out_release_mem:
1829         release_mem_region(res_mem->start, iomem_size);
1830 out:
1831         free_netdev(dev);
1832         return ret;
1833 }
1834
1835
1836 /*
1837  * exit func, stops hardware and unregisters netdevice
1838  */
1839 static int __devexit bcm_enet_remove(struct platform_device *pdev)
1840 {
1841         struct bcm_enet_priv *priv;
1842         struct net_device *dev;
1843         struct resource *res;
1844
1845         /* stop netdevice */
1846         dev = platform_get_drvdata(pdev);
1847         priv = netdev_priv(dev);
1848         unregister_netdev(dev);
1849
1850         /* turn off mdc clock */
1851         enet_writel(priv, 0, ENET_MIISC_REG);
1852
1853         if (priv->has_phy) {
1854                 mdiobus_unregister(priv->mii_bus);
1855                 kfree(priv->mii_bus->irq);
1856                 mdiobus_free(priv->mii_bus);
1857         } else {
1858                 struct bcm63xx_enet_platform_data *pd;
1859
1860                 pd = pdev->dev.platform_data;
1861                 if (pd && pd->mii_config)
1862                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1863                                        bcm_enet_mdio_write_mii);
1864         }
1865
1866         /* release device resources */
1867         iounmap(priv->base);
1868         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1869         release_mem_region(res->start, res->end - res->start + 1);
1870
1871         /* disable hw block clocks */
1872         if (priv->phy_clk) {
1873                 clk_disable(priv->phy_clk);
1874                 clk_put(priv->phy_clk);
1875         }
1876         clk_disable(priv->mac_clk);
1877         clk_put(priv->mac_clk);
1878
1879         platform_set_drvdata(pdev, NULL);
1880         free_netdev(dev);
1881         return 0;
1882 }
1883
1884 struct platform_driver bcm63xx_enet_driver = {
1885         .probe  = bcm_enet_probe,
1886         .remove = __devexit_p(bcm_enet_remove),
1887         .driver = {
1888                 .name   = "bcm63xx_enet",
1889                 .owner  = THIS_MODULE,
1890         },
1891 };
1892
1893 /*
1894  * reserve & remap memory space shared between all macs
1895  */
1896 static int __devinit bcm_enet_shared_probe(struct platform_device *pdev)
1897 {
1898         struct resource *res;
1899         unsigned int iomem_size;
1900
1901         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1902         if (!res)
1903                 return -ENODEV;
1904
1905         iomem_size = res->end - res->start + 1;
1906         if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma"))
1907                 return -EBUSY;
1908
1909         bcm_enet_shared_base = ioremap(res->start, iomem_size);
1910         if (!bcm_enet_shared_base) {
1911                 release_mem_region(res->start, iomem_size);
1912                 return -ENOMEM;
1913         }
1914         return 0;
1915 }
1916
1917 static int __devexit bcm_enet_shared_remove(struct platform_device *pdev)
1918 {
1919         struct resource *res;
1920
1921         iounmap(bcm_enet_shared_base);
1922         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1923         release_mem_region(res->start, res->end - res->start + 1);
1924         return 0;
1925 }
1926
1927 /*
1928  * this "shared" driver is needed because both macs share a single
1929  * address space
1930  */
1931 struct platform_driver bcm63xx_enet_shared_driver = {
1932         .probe  = bcm_enet_shared_probe,
1933         .remove = __devexit_p(bcm_enet_shared_remove),
1934         .driver = {
1935                 .name   = "bcm63xx_enet_shared",
1936                 .owner  = THIS_MODULE,
1937         },
1938 };
1939
1940 /*
1941  * entry point
1942  */
1943 static int __init bcm_enet_init(void)
1944 {
1945         int ret;
1946
1947         ret = platform_driver_register(&bcm63xx_enet_shared_driver);
1948         if (ret)
1949                 return ret;
1950
1951         ret = platform_driver_register(&bcm63xx_enet_driver);
1952         if (ret)
1953                 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1954
1955         return ret;
1956 }
1957
1958 static void __exit bcm_enet_exit(void)
1959 {
1960         platform_driver_unregister(&bcm63xx_enet_driver);
1961         platform_driver_unregister(&bcm63xx_enet_shared_driver);
1962 }
1963
1964
1965 module_init(bcm_enet_init);
1966 module_exit(bcm_enet_exit);
1967
1968 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
1969 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
1970 MODULE_LICENSE("GPL");