1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
32 #define DRV_NAME "3c59x"
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
46 static int rx_copybreak = 200;
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
63 #define tx_interrupt_mitigation 1
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
68 static int vortex_debug = VORTEX_DEBUG;
70 static int vortex_debug = 1;
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
79 #include <linux/ioport.h>
80 #include <linux/interrupt.h>
81 #include <linux/pci.h>
82 #include <linux/mii.h>
83 #include <linux/init.h>
84 #include <linux/netdevice.h>
85 #include <linux/etherdevice.h>
86 #include <linux/skbuff.h>
87 #include <linux/ethtool.h>
88 #include <linux/highmem.h>
89 #include <linux/eisa.h>
90 #include <linux/bitops.h>
91 #include <linux/jiffies.h>
92 #include <linux/gfp.h>
93 #include <asm/irq.h> /* For nr_irqs only. */
95 #include <asm/uaccess.h>
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
100 #define RUN_AT(x) (jiffies + (x))
102 #include <linux/delay.h>
105 static const char version[] __devinitconst =
106 DRV_NAME ": Donald Becker and others.\n";
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
113 /* Operational parameter that usually are not changed. */
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
127 #define PFX DRV_NAME ": "
134 I. Board Compatibility
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
145 II. Board-specific settings
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
155 III. Driver operation
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
271 /* note: this array directly indexed by above enums, and MUST
272 * be kept in sync with both the enums above, and the PCI device
275 static struct vortex_chip_info {
280 } vortex_info_tbl[] __devinitdata = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
303 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
374 {NULL,}, /* NULL terminated list. */
378 static DEFINE_PCI_DEVICE_TABLE(vortex_pci_tbl) = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
426 {0,} /* 0 terminated list. */
428 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
431 /* Operational definitions.
432 These are not used by other compilation units and thus are not
433 exported in a ".h" file.
435 First the windows. There are eight register windows, with the command
436 and status registers available in each.
439 #define EL3_STATUS 0x0e
441 /* The top five bits written to EL3_CMD are a command, the lower
442 11 bits are the parameter, if applicable.
443 Note that 11 parameters bits was fine for ethernet, but the new chip
444 can handle FDDI length frames (~4500 octets) and now parameters count
445 32-bit 'Dwords' rather than octets. */
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
459 /* The SetRxFilter command accepts the following classes: */
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
463 /* Bits in the general status register. */
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
470 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
473 /* Register window 1 offsets, the window used in normal operation.
474 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
481 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
482 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
483 IntrStatus=0x0E, /* Valid in all windows. */
485 enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
488 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
490 /* EEPROM locations. */
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
497 enum Window2 { /* Window 2. */
500 enum Window3 { /* Window 3: MAC/config bits. */
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
504 #define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
507 #define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
511 #define RAM_SIZE(v) BFEXT(v, 0, 3)
512 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
513 #define RAM_SPEED(v) BFEXT(v, 4, 2)
514 #define ROM_SIZE(v) BFEXT(v, 6, 2)
515 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
516 #define XCVR(v) BFEXT(v, 20, 4)
517 #define AUTOSELECT(v) BFEXT(v, 24, 1)
519 enum Window4 { /* Window 4: Xcvr/media bits. */
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
522 enum Win4_Media_bits {
523 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
524 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
525 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
526 Media_LnkBeat = 0x0800,
528 enum Window7 { /* Window 7: Bus Master control. */
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
532 /* Boomerang bus master control registers. */
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
538 /* The Rx and Tx descriptor lists.
539 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
540 alignment contraint on tx_ring[] and rx_ring[]. */
541 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
542 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
543 struct boom_rx_desc {
544 __le32 next; /* Last entry points to 0. */
546 __le32 addr; /* Up to 63 addr/len pairs possible. */
547 __le32 length; /* Set LAST_FRAG to indicate last pair. */
549 /* Values for the Rx status entry. */
550 enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552 /* See boomerang_rx() for actual error bits */
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
558 #define DO_ZEROCOPY 1
560 #define DO_ZEROCOPY 0
563 struct boom_tx_desc {
564 __le32 next; /* Last entry points to 0. */
565 __le32 status; /* bits 0:12 length, others see below. */
570 } frag[1+MAX_SKB_FRAGS];
577 /* Values for the Tx status entry. */
578 enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
584 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
585 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
587 struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
595 struct vortex_private {
596 /* The Rx and Tx rings should be quad-word-aligned. */
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601 /* The addresses of transmit- and receive-in-place skbuffs. */
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx; /* The next free ring entry */
605 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
606 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
607 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
608 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
610 /* PCI configuration space information. */
611 struct device *gendev;
612 void __iomem *ioaddr; /* IO address space */
613 void __iomem *cb_fn_base; /* CardBus function status addr space. */
615 /* Some values here only for performance evaluation and path-coverage */
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
619 /* The remainder are related to chip state, mostly media selection. */
620 struct timer_list timer; /* Media selection timer. */
621 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
622 int options; /* User-settable misc. driver options. */
623 unsigned int media_override:4, /* Passed-in media type. */
624 default_media:4, /* Read from the EEPROM/Wn3_Config. */
625 full_duplex:1, autoselect:1,
626 bus_master:1, /* Vortex can only do a fragment bus-m. */
627 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
628 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
629 partner_flow_ctrl:1, /* Partner supports flow control */
631 enable_wol:1, /* Wake-on-LAN is enabled */
632 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
635 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
636 large_frames:1, /* accept large frames */
637 handling_irq:1; /* private in_irq indicator */
641 u16 available_media; /* From Wn3_Options. */
642 u16 capabilities, info1, info2; /* Various, from EEPROM. */
643 u16 advertising; /* NWay media advertisement */
644 unsigned char phys[2]; /* MII device addresses. */
645 u16 deferred; /* Resend these interrupts when we
646 * bale from the ISR */
647 u16 io_size; /* Size of PCI region (for release_region) */
649 /* Serialises access to hardware other than MII and variables below.
650 * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
653 spinlock_t mii_lock; /* Serialises access to MII */
654 struct mii_if_info mii; /* MII lib hooks/info */
655 spinlock_t window_lock; /* Serialises access to windowed regs */
656 int window; /* Register window */
659 static void window_set(struct vortex_private *vp, int window)
661 if (window != vp->window) {
662 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
667 #define DEFINE_WINDOW_IO(size) \
669 window_read ## size(struct vortex_private *vp, int window, int addr) \
671 unsigned long flags; \
673 spin_lock_irqsave(&vp->window_lock, flags); \
674 window_set(vp, window); \
675 ret = ioread ## size(vp->ioaddr + addr); \
676 spin_unlock_irqrestore(&vp->window_lock, flags); \
680 window_write ## size(struct vortex_private *vp, u ## size value, \
681 int window, int addr) \
683 unsigned long flags; \
684 spin_lock_irqsave(&vp->window_lock, flags); \
685 window_set(vp, window); \
686 iowrite ## size(value, vp->ioaddr + addr); \
687 spin_unlock_irqrestore(&vp->window_lock, flags); \
694 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
696 #define DEVICE_PCI(dev) NULL
699 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
702 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
704 #define DEVICE_EISA(dev) NULL
707 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
709 /* The action to take with a media selection timer tick.
710 Note that we deviate from the 3Com order by checking 10base2 before AUI.
713 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
714 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
717 static const struct media_table {
719 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
720 mask:8, /* The transceiver-present bit in Wn3_Config.*/
721 next:8; /* The media type to try next. */
722 int wait; /* Time before we check media status. */
724 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
725 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
726 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
727 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
728 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
729 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
730 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
731 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
732 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
733 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
734 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
738 const char str[ETH_GSTRING_LEN];
739 } ethtool_stats_keys[] = {
741 { "tx_max_collisions" },
742 { "tx_multiple_collisions" },
743 { "tx_single_collisions" },
747 /* number of ETHTOOL_GSTATS u64's */
748 #define VORTEX_NUM_STATS 5
750 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
751 int chip_idx, int card_idx);
752 static int vortex_up(struct net_device *dev);
753 static void vortex_down(struct net_device *dev, int final);
754 static int vortex_open(struct net_device *dev);
755 static void mdio_sync(struct vortex_private *vp, int bits);
756 static int mdio_read(struct net_device *dev, int phy_id, int location);
757 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
758 static void vortex_timer(unsigned long arg);
759 static void rx_oom_timer(unsigned long arg);
760 static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
761 struct net_device *dev);
762 static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
763 struct net_device *dev);
764 static int vortex_rx(struct net_device *dev);
765 static int boomerang_rx(struct net_device *dev);
766 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
767 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
768 static int vortex_close(struct net_device *dev);
769 static void dump_tx_ring(struct net_device *dev);
770 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
771 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
772 static void set_rx_mode(struct net_device *dev);
774 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
776 static void vortex_tx_timeout(struct net_device *dev);
777 static void acpi_set_WOL(struct net_device *dev);
778 static const struct ethtool_ops vortex_ethtool_ops;
779 static void set_8021q_mode(struct net_device *dev, int enable);
781 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
782 /* Option count limit only -- unlimited interfaces are supported. */
784 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
785 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
786 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
787 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
788 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
789 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790 static int global_options = -1;
791 static int global_full_duplex = -1;
792 static int global_enable_wol = -1;
793 static int global_use_mmio = -1;
795 /* Variables to work-around the Compaq PCI BIOS32 problem. */
796 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
797 static struct net_device *compaq_net_device;
799 static int vortex_cards_found;
801 module_param(debug, int, 0);
802 module_param(global_options, int, 0);
803 module_param_array(options, int, NULL, 0);
804 module_param(global_full_duplex, int, 0);
805 module_param_array(full_duplex, int, NULL, 0);
806 module_param_array(hw_checksums, int, NULL, 0);
807 module_param_array(flow_ctrl, int, NULL, 0);
808 module_param(global_enable_wol, int, 0);
809 module_param_array(enable_wol, int, NULL, 0);
810 module_param(rx_copybreak, int, 0);
811 module_param(max_interrupt_work, int, 0);
812 module_param(compaq_ioaddr, int, 0);
813 module_param(compaq_irq, int, 0);
814 module_param(compaq_device_id, int, 0);
815 module_param(watchdog, int, 0);
816 module_param(global_use_mmio, int, 0);
817 module_param_array(use_mmio, int, NULL, 0);
818 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
819 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
820 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
821 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
822 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
823 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
824 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
825 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
826 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
827 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
828 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
829 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
830 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
831 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
832 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
833 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
834 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
836 #ifdef CONFIG_NET_POLL_CONTROLLER
837 static void poll_vortex(struct net_device *dev)
839 struct vortex_private *vp = netdev_priv(dev);
841 local_irq_save(flags);
842 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
843 local_irq_restore(flags);
849 static int vortex_suspend(struct device *dev)
851 struct pci_dev *pdev = to_pci_dev(dev);
852 struct net_device *ndev = pci_get_drvdata(pdev);
854 if (!ndev || !netif_running(ndev))
857 netif_device_detach(ndev);
858 vortex_down(ndev, 1);
863 static int vortex_resume(struct device *dev)
865 struct pci_dev *pdev = to_pci_dev(dev);
866 struct net_device *ndev = pci_get_drvdata(pdev);
869 if (!ndev || !netif_running(ndev))
872 err = vortex_up(ndev);
876 netif_device_attach(ndev);
881 static const struct dev_pm_ops vortex_pm_ops = {
882 .suspend = vortex_suspend,
883 .resume = vortex_resume,
884 .freeze = vortex_suspend,
885 .thaw = vortex_resume,
886 .poweroff = vortex_suspend,
887 .restore = vortex_resume,
890 #define VORTEX_PM_OPS (&vortex_pm_ops)
892 #else /* !CONFIG_PM */
894 #define VORTEX_PM_OPS NULL
896 #endif /* !CONFIG_PM */
899 static struct eisa_device_id vortex_eisa_ids[] = {
900 { "TCM5920", CH_3C592 },
901 { "TCM5970", CH_3C597 },
904 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
906 static int __init vortex_eisa_probe(struct device *device)
908 void __iomem *ioaddr;
909 struct eisa_device *edev;
911 edev = to_eisa_device(device);
913 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
916 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
918 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
919 edev->id.driver_data, vortex_cards_found)) {
920 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
924 vortex_cards_found++;
929 static int __devexit vortex_eisa_remove(struct device *device)
931 struct eisa_device *edev;
932 struct net_device *dev;
933 struct vortex_private *vp;
934 void __iomem *ioaddr;
936 edev = to_eisa_device(device);
937 dev = eisa_get_drvdata(edev);
940 pr_err("vortex_eisa_remove called for Compaq device!\n");
944 vp = netdev_priv(dev);
947 unregister_netdev(dev);
948 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
949 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
955 static struct eisa_driver vortex_eisa_driver = {
956 .id_table = vortex_eisa_ids,
959 .probe = vortex_eisa_probe,
960 .remove = __devexit_p(vortex_eisa_remove)
964 #endif /* CONFIG_EISA */
966 /* returns count found (>= 0), or negative on error */
967 static int __init vortex_eisa_init(void)
970 int orig_cards_found = vortex_cards_found;
975 err = eisa_driver_register (&vortex_eisa_driver);
978 * Because of the way EISA bus is probed, we cannot assume
979 * any device have been found when we exit from
980 * eisa_driver_register (the bus root driver may not be
981 * initialized yet). So we blindly assume something was
982 * found, and let the sysfs magic happend...
988 /* Special code to work-around the Compaq PCI BIOS32 problem. */
990 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
991 compaq_irq, compaq_device_id, vortex_cards_found++);
994 return vortex_cards_found - orig_cards_found + eisa_found;
997 /* returns count (>= 0), or negative on error */
998 static int __devinit vortex_init_one(struct pci_dev *pdev,
999 const struct pci_device_id *ent)
1001 int rc, unit, pci_bar;
1002 struct vortex_chip_info *vci;
1003 void __iomem *ioaddr;
1005 /* wake up and enable device */
1006 rc = pci_enable_device(pdev);
1010 unit = vortex_cards_found;
1012 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1013 /* Determine the default if the user didn't override us */
1014 vci = &vortex_info_tbl[ent->driver_data];
1015 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1016 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1017 pci_bar = use_mmio[unit] ? 1 : 0;
1019 pci_bar = global_use_mmio ? 1 : 0;
1021 ioaddr = pci_iomap(pdev, pci_bar, 0);
1022 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
1023 ioaddr = pci_iomap(pdev, 0, 0);
1025 pci_disable_device(pdev);
1030 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1031 ent->driver_data, unit);
1033 pci_iounmap(pdev, ioaddr);
1034 pci_disable_device(pdev);
1038 vortex_cards_found++;
1044 static const struct net_device_ops boomrang_netdev_ops = {
1045 .ndo_open = vortex_open,
1046 .ndo_stop = vortex_close,
1047 .ndo_start_xmit = boomerang_start_xmit,
1048 .ndo_tx_timeout = vortex_tx_timeout,
1049 .ndo_get_stats = vortex_get_stats,
1051 .ndo_do_ioctl = vortex_ioctl,
1053 .ndo_set_multicast_list = set_rx_mode,
1054 .ndo_change_mtu = eth_change_mtu,
1055 .ndo_set_mac_address = eth_mac_addr,
1056 .ndo_validate_addr = eth_validate_addr,
1057 #ifdef CONFIG_NET_POLL_CONTROLLER
1058 .ndo_poll_controller = poll_vortex,
1062 static const struct net_device_ops vortex_netdev_ops = {
1063 .ndo_open = vortex_open,
1064 .ndo_stop = vortex_close,
1065 .ndo_start_xmit = vortex_start_xmit,
1066 .ndo_tx_timeout = vortex_tx_timeout,
1067 .ndo_get_stats = vortex_get_stats,
1069 .ndo_do_ioctl = vortex_ioctl,
1071 .ndo_set_multicast_list = set_rx_mode,
1072 .ndo_change_mtu = eth_change_mtu,
1073 .ndo_set_mac_address = eth_mac_addr,
1074 .ndo_validate_addr = eth_validate_addr,
1075 #ifdef CONFIG_NET_POLL_CONTROLLER
1076 .ndo_poll_controller = poll_vortex,
1081 * Start up the PCI/EISA device which is described by *gendev.
1082 * Return 0 on success.
1084 * NOTE: pdev can be NULL, for the case of a Compaq device
1086 static int __devinit vortex_probe1(struct device *gendev,
1087 void __iomem *ioaddr, int irq,
1088 int chip_idx, int card_idx)
1090 struct vortex_private *vp;
1092 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1094 struct net_device *dev;
1095 static int printed_version;
1096 int retval, print_info;
1097 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1098 const char *print_name = "3c59x";
1099 struct pci_dev *pdev = NULL;
1100 struct eisa_device *edev = NULL;
1102 if (!printed_version) {
1103 pr_info("%s", version);
1104 printed_version = 1;
1108 if ((pdev = DEVICE_PCI(gendev))) {
1109 print_name = pci_name(pdev);
1112 if ((edev = DEVICE_EISA(gendev))) {
1113 print_name = dev_name(&edev->dev);
1117 dev = alloc_etherdev(sizeof(*vp));
1120 pr_err(PFX "unable to allocate etherdev, aborting\n");
1123 SET_NETDEV_DEV(dev, gendev);
1124 vp = netdev_priv(dev);
1126 option = global_options;
1128 /* The lower four bits are the media type. */
1129 if (dev->mem_start) {
1131 * The 'options' param is passed in as the third arg to the
1132 * LILO 'ether=' argument for non-modular use
1134 option = dev->mem_start;
1136 else if (card_idx < MAX_UNITS) {
1137 if (options[card_idx] >= 0)
1138 option = options[card_idx];
1142 if (option & 0x8000)
1144 if (option & 0x4000)
1146 if (option & 0x0400)
1150 print_info = (vortex_debug > 1);
1152 pr_info("See Documentation/networking/vortex.txt\n");
1154 pr_info("%s: 3Com %s %s at %p.\n",
1156 pdev ? "PCI" : "EISA",
1160 dev->base_addr = (unsigned long)ioaddr;
1163 vp->ioaddr = ioaddr;
1164 vp->large_frames = mtu > 1500;
1165 vp->drv_flags = vci->drv_flags;
1166 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1167 vp->io_size = vci->io_size;
1168 vp->card_idx = card_idx;
1171 /* module list only for Compaq device */
1172 if (gendev == NULL) {
1173 compaq_net_device = dev;
1176 /* PCI-only startup logic */
1178 /* EISA resources already marked, so only PCI needs to do this here */
1179 /* Ignore return value, because Cardbus drivers already allocate for us */
1180 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1181 vp->must_free_region = 1;
1183 /* enable bus-mastering if necessary */
1184 if (vci->flags & PCI_USES_MASTER)
1185 pci_set_master(pdev);
1187 if (vci->drv_flags & IS_VORTEX) {
1189 u8 new_latency = 248;
1191 /* Check the PCI latency value. On the 3c590 series the latency timer
1192 must be set to the maximum value to avoid data corruption that occurs
1193 when the timer expires during a transfer. This bug exists the Vortex
1195 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1196 if (pci_latency < new_latency) {
1197 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1198 print_name, pci_latency, new_latency);
1199 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1204 spin_lock_init(&vp->lock);
1205 spin_lock_init(&vp->mii_lock);
1206 spin_lock_init(&vp->window_lock);
1207 vp->gendev = gendev;
1209 vp->mii.mdio_read = mdio_read;
1210 vp->mii.mdio_write = mdio_write;
1211 vp->mii.phy_id_mask = 0x1f;
1212 vp->mii.reg_num_mask = 0x1f;
1214 /* Makes sure rings are at least 16 byte aligned. */
1215 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1216 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1222 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1223 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1225 /* if we are a PCI driver, we store info in pdev->driver_data
1226 * instead of a module list */
1228 pci_set_drvdata(pdev, dev);
1230 eisa_set_drvdata(edev, dev);
1232 vp->media_override = 7;
1234 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1235 if (vp->media_override != 7)
1237 vp->full_duplex = (option & 0x200) ? 1 : 0;
1238 vp->bus_master = (option & 16) ? 1 : 0;
1241 if (global_full_duplex > 0)
1242 vp->full_duplex = 1;
1243 if (global_enable_wol > 0)
1246 if (card_idx < MAX_UNITS) {
1247 if (full_duplex[card_idx] > 0)
1248 vp->full_duplex = 1;
1249 if (flow_ctrl[card_idx] > 0)
1251 if (enable_wol[card_idx] > 0)
1255 vp->mii.force_media = vp->full_duplex;
1256 vp->options = option;
1257 /* Read the station address from the EEPROM. */
1261 if (vci->drv_flags & EEPROM_8BIT)
1263 else if (vci->drv_flags & EEPROM_OFFSET)
1264 base = EEPROM_Read + 0x30;
1268 for (i = 0; i < 0x40; i++) {
1270 window_write16(vp, base + i, 0, Wn0EepromCmd);
1271 /* Pause for at least 162 us. for the read to take place. */
1272 for (timer = 10; timer >= 0; timer--) {
1274 if ((window_read16(vp, 0, Wn0EepromCmd) &
1278 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1281 for (i = 0; i < 0x18; i++)
1282 checksum ^= eeprom[i];
1283 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1284 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1286 checksum ^= eeprom[i++];
1287 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1289 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1290 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1291 for (i = 0; i < 3; i++)
1292 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1293 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1295 pr_cont(" %pM", dev->dev_addr);
1296 /* Unfortunately an all zero eeprom passes the checksum and this
1297 gets found in the wild in failure cases. Crypto is hard 8) */
1298 if (!is_valid_ether_addr(dev->dev_addr)) {
1300 pr_err("*** EEPROM MAC address is invalid.\n");
1301 goto free_ring; /* With every pack */
1303 for (i = 0; i < 6; i++)
1304 window_write8(vp, dev->dev_addr[i], 2, i);
1307 pr_cont(", IRQ %d\n", dev->irq);
1308 /* Tell them about an invalid IRQ. */
1309 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1310 pr_warning(" *** Warning: IRQ %d is unlikely to work! ***\n",
1313 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1315 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1316 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1317 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1321 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1324 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1325 if (!vp->cb_fn_base) {
1331 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1333 (unsigned long long)pci_resource_start(pdev, 2),
1337 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1338 if (vp->drv_flags & INVERT_LED_PWR)
1340 if (vp->drv_flags & INVERT_MII_PWR)
1342 window_write16(vp, n, 2, Wn2_ResetOptions);
1343 if (vp->drv_flags & WNO_XCVR_PWR) {
1344 window_write16(vp, 0x0800, 0, 0);
1348 /* Extract our information from the EEPROM data. */
1349 vp->info1 = eeprom[13];
1350 vp->info2 = eeprom[15];
1351 vp->capabilities = eeprom[16];
1353 if (vp->info1 & 0x8000) {
1354 vp->full_duplex = 1;
1356 pr_info("Full duplex capable\n");
1360 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1361 unsigned int config;
1362 vp->available_media = window_read16(vp, 3, Wn3_Options);
1363 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1364 vp->available_media = 0x40;
1365 config = window_read32(vp, 3, Wn3_Config);
1367 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1368 config, window_read16(vp, 3, Wn3_Options));
1369 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1370 8 << RAM_SIZE(config),
1371 RAM_WIDTH(config) ? "word" : "byte",
1372 ram_split[RAM_SPLIT(config)],
1373 AUTOSELECT(config) ? "autoselect/" : "",
1374 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1375 media_tbl[XCVR(config)].name);
1377 vp->default_media = XCVR(config);
1378 if (vp->default_media == XCVR_NWAY)
1380 vp->autoselect = AUTOSELECT(config);
1383 if (vp->media_override != 7) {
1384 pr_info("%s: Media override to transceiver type %d (%s).\n",
1385 print_name, vp->media_override,
1386 media_tbl[vp->media_override].name);
1387 dev->if_port = vp->media_override;
1389 dev->if_port = vp->default_media;
1391 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1392 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1393 int phy, phy_idx = 0;
1394 mii_preamble_required++;
1395 if (vp->drv_flags & EXTRA_PREAMBLE)
1396 mii_preamble_required++;
1398 mdio_read(dev, 24, MII_BMSR);
1399 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1400 int mii_status, phyx;
1403 * For the 3c905CX we look at index 24 first, because it bogusly
1404 * reports an external PHY at all indices
1412 mii_status = mdio_read(dev, phyx, MII_BMSR);
1413 if (mii_status && mii_status != 0xffff) {
1414 vp->phys[phy_idx++] = phyx;
1416 pr_info(" MII transceiver found at address %d, status %4x.\n",
1419 if ((mii_status & 0x0040) == 0)
1420 mii_preamble_required++;
1423 mii_preamble_required--;
1425 pr_warning(" ***WARNING*** No MII transceivers found!\n");
1428 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1429 if (vp->full_duplex) {
1430 /* Only advertise the FD media types. */
1431 vp->advertising &= ~0x02A0;
1432 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1435 vp->mii.phy_id = vp->phys[0];
1438 if (vp->capabilities & CapBusMaster) {
1439 vp->full_bus_master_tx = 1;
1441 pr_info(" Enabling bus-master transmits and %s receives.\n",
1442 (vp->info2 & 1) ? "early" : "whole-frame" );
1444 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1445 vp->bus_master = 0; /* AKPM: vortex only */
1448 /* The 3c59x-specific entries in the device structure. */
1449 if (vp->full_bus_master_tx) {
1450 dev->netdev_ops = &boomrang_netdev_ops;
1451 /* Actually, it still should work with iommu. */
1452 if (card_idx < MAX_UNITS &&
1453 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1454 hw_checksums[card_idx] == 1)) {
1455 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1458 dev->netdev_ops = &vortex_netdev_ops;
1461 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1463 (dev->features & NETIF_F_SG) ? "en":"dis",
1464 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1467 dev->ethtool_ops = &vortex_ethtool_ops;
1468 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1471 vp->pm_state_valid = 1;
1472 pci_save_state(VORTEX_PCI(vp));
1475 retval = register_netdev(dev);
1480 pci_free_consistent(pdev,
1481 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1482 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1486 if (vp->must_free_region)
1487 release_region(dev->base_addr, vci->io_size);
1489 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1495 issue_and_wait(struct net_device *dev, int cmd)
1497 struct vortex_private *vp = netdev_priv(dev);
1498 void __iomem *ioaddr = vp->ioaddr;
1501 iowrite16(cmd, ioaddr + EL3_CMD);
1502 for (i = 0; i < 2000; i++) {
1503 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1507 /* OK, that didn't work. Do it the slow way. One second */
1508 for (i = 0; i < 100000; i++) {
1509 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1510 if (vortex_debug > 1)
1511 pr_info("%s: command 0x%04x took %d usecs\n",
1512 dev->name, cmd, i * 10);
1517 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1518 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1522 vortex_set_duplex(struct net_device *dev)
1524 struct vortex_private *vp = netdev_priv(dev);
1526 pr_info("%s: setting %s-duplex.\n",
1527 dev->name, (vp->full_duplex) ? "full" : "half");
1529 /* Set the full-duplex bit. */
1531 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1532 (vp->large_frames ? 0x40 : 0) |
1533 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1538 static void vortex_check_media(struct net_device *dev, unsigned int init)
1540 struct vortex_private *vp = netdev_priv(dev);
1541 unsigned int ok_to_print = 0;
1543 if (vortex_debug > 3)
1546 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1547 vp->full_duplex = vp->mii.full_duplex;
1548 vortex_set_duplex(dev);
1550 vortex_set_duplex(dev);
1555 vortex_up(struct net_device *dev)
1557 struct vortex_private *vp = netdev_priv(dev);
1558 void __iomem *ioaddr = vp->ioaddr;
1559 unsigned int config;
1560 int i, mii_reg1, mii_reg5, err = 0;
1562 if (VORTEX_PCI(vp)) {
1563 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1564 if (vp->pm_state_valid)
1565 pci_restore_state(VORTEX_PCI(vp));
1566 err = pci_enable_device(VORTEX_PCI(vp));
1568 pr_warning("%s: Could not enable device\n",
1574 /* Before initializing select the active media port. */
1575 config = window_read32(vp, 3, Wn3_Config);
1577 if (vp->media_override != 7) {
1578 pr_info("%s: Media override to transceiver %d (%s).\n",
1579 dev->name, vp->media_override,
1580 media_tbl[vp->media_override].name);
1581 dev->if_port = vp->media_override;
1582 } else if (vp->autoselect) {
1584 if (vortex_debug > 1)
1585 pr_info("%s: using NWAY device table, not %d\n",
1586 dev->name, dev->if_port);
1587 dev->if_port = XCVR_NWAY;
1589 /* Find first available media type, starting with 100baseTx. */
1590 dev->if_port = XCVR_100baseTx;
1591 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1592 dev->if_port = media_tbl[dev->if_port].next;
1593 if (vortex_debug > 1)
1594 pr_info("%s: first available media type: %s\n",
1595 dev->name, media_tbl[dev->if_port].name);
1598 dev->if_port = vp->default_media;
1599 if (vortex_debug > 1)
1600 pr_info("%s: using default media %s\n",
1601 dev->name, media_tbl[dev->if_port].name);
1604 init_timer(&vp->timer);
1605 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1606 vp->timer.data = (unsigned long)dev;
1607 vp->timer.function = vortex_timer; /* timer handler */
1608 add_timer(&vp->timer);
1610 init_timer(&vp->rx_oom_timer);
1611 vp->rx_oom_timer.data = (unsigned long)dev;
1612 vp->rx_oom_timer.function = rx_oom_timer;
1614 if (vortex_debug > 1)
1615 pr_debug("%s: Initial media type %s.\n",
1616 dev->name, media_tbl[dev->if_port].name);
1618 vp->full_duplex = vp->mii.force_media;
1619 config = BFINS(config, dev->if_port, 20, 4);
1620 if (vortex_debug > 6)
1621 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1622 window_write32(vp, config, 3, Wn3_Config);
1624 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1625 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1626 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1627 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1628 vp->mii.full_duplex = vp->full_duplex;
1630 vortex_check_media(dev, 1);
1633 vortex_set_duplex(dev);
1635 issue_and_wait(dev, TxReset);
1637 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1639 issue_and_wait(dev, RxReset|0x04);
1642 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1644 if (vortex_debug > 1) {
1645 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1646 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1649 /* Set the station address and mask in window 2 each time opened. */
1650 for (i = 0; i < 6; i++)
1651 window_write8(vp, dev->dev_addr[i], 2, i);
1652 for (; i < 12; i+=2)
1653 window_write16(vp, 0, 2, i);
1655 if (vp->cb_fn_base) {
1656 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1657 if (vp->drv_flags & INVERT_LED_PWR)
1659 if (vp->drv_flags & INVERT_MII_PWR)
1661 window_write16(vp, n, 2, Wn2_ResetOptions);
1664 if (dev->if_port == XCVR_10base2)
1665 /* Start the thinnet transceiver. We should really wait 50ms...*/
1666 iowrite16(StartCoax, ioaddr + EL3_CMD);
1667 if (dev->if_port != XCVR_NWAY) {
1669 (window_read16(vp, 4, Wn4_Media) &
1670 ~(Media_10TP|Media_SQE)) |
1671 media_tbl[dev->if_port].media_bits,
1675 /* Switch to the stats window, and clear all stats by reading. */
1676 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1677 for (i = 0; i < 10; i++)
1678 window_read8(vp, 6, i);
1679 window_read16(vp, 6, 10);
1680 window_read16(vp, 6, 12);
1681 /* New: On the Vortex we must also clear the BadSSD counter. */
1682 window_read8(vp, 4, 12);
1683 /* ..and on the Boomerang we enable the extra statistics bits. */
1684 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1686 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1687 vp->cur_rx = vp->dirty_rx = 0;
1688 /* Initialize the RxEarly register as recommended. */
1689 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1690 iowrite32(0x0020, ioaddr + PktStatus);
1691 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1693 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1694 vp->cur_tx = vp->dirty_tx = 0;
1695 if (vp->drv_flags & IS_BOOMERANG)
1696 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1697 /* Clear the Rx, Tx rings. */
1698 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1699 vp->rx_ring[i].status = 0;
1700 for (i = 0; i < TX_RING_SIZE; i++)
1701 vp->tx_skbuff[i] = NULL;
1702 iowrite32(0, ioaddr + DownListPtr);
1704 /* Set receiver mode: presumably accept b-case and phys addr only. */
1706 /* enable 802.1q tagged frames */
1707 set_8021q_mode(dev, 1);
1708 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1710 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1711 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1712 /* Allow status bits to be seen. */
1713 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1714 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1715 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1716 (vp->bus_master ? DMADone : 0);
1717 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1718 (vp->full_bus_master_rx ? 0 : RxComplete) |
1719 StatsFull | HostError | TxComplete | IntReq
1720 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1721 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1722 /* Ack all pending events, and set active indicator mask. */
1723 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1725 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1726 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1727 iowrite32(0x8000, vp->cb_fn_base + 4);
1728 netif_start_queue (dev);
1734 vortex_open(struct net_device *dev)
1736 struct vortex_private *vp = netdev_priv(dev);
1740 /* Use the now-standard shared IRQ implementation. */
1741 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1742 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1743 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1747 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1748 if (vortex_debug > 2)
1749 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1750 for (i = 0; i < RX_RING_SIZE; i++) {
1751 struct sk_buff *skb;
1752 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1753 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1754 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1756 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1758 vp->rx_skbuff[i] = skb;
1760 break; /* Bad news! */
1762 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1763 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1765 if (i != RX_RING_SIZE) {
1767 pr_emerg("%s: no memory for rx ring\n", dev->name);
1768 for (j = 0; j < i; j++) {
1769 if (vp->rx_skbuff[j]) {
1770 dev_kfree_skb(vp->rx_skbuff[j]);
1771 vp->rx_skbuff[j] = NULL;
1777 /* Wrap the ring. */
1778 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1781 retval = vortex_up(dev);
1786 free_irq(dev->irq, dev);
1788 if (vortex_debug > 1)
1789 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1795 vortex_timer(unsigned long data)
1797 struct net_device *dev = (struct net_device *)data;
1798 struct vortex_private *vp = netdev_priv(dev);
1799 void __iomem *ioaddr = vp->ioaddr;
1800 int next_tick = 60*HZ;
1804 if (vortex_debug > 2) {
1805 pr_debug("%s: Media selection timer tick happened, %s.\n",
1806 dev->name, media_tbl[dev->if_port].name);
1807 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1810 media_status = window_read16(vp, 4, Wn4_Media);
1811 switch (dev->if_port) {
1812 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1813 if (media_status & Media_LnkBeat) {
1814 netif_carrier_on(dev);
1816 if (vortex_debug > 1)
1817 pr_debug("%s: Media %s has link beat, %x.\n",
1818 dev->name, media_tbl[dev->if_port].name, media_status);
1820 netif_carrier_off(dev);
1821 if (vortex_debug > 1) {
1822 pr_debug("%s: Media %s has no link beat, %x.\n",
1823 dev->name, media_tbl[dev->if_port].name, media_status);
1827 case XCVR_MII: case XCVR_NWAY:
1830 vortex_check_media(dev, 0);
1833 default: /* Other media types handled by Tx timeouts. */
1834 if (vortex_debug > 1)
1835 pr_debug("%s: Media %s has no indication, %x.\n",
1836 dev->name, media_tbl[dev->if_port].name, media_status);
1840 if (!netif_carrier_ok(dev))
1844 goto leave_media_alone;
1847 unsigned int config;
1849 spin_lock_irq(&vp->lock);
1852 dev->if_port = media_tbl[dev->if_port].next;
1853 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1854 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1855 dev->if_port = vp->default_media;
1856 if (vortex_debug > 1)
1857 pr_debug("%s: Media selection failing, using default %s port.\n",
1858 dev->name, media_tbl[dev->if_port].name);
1860 if (vortex_debug > 1)
1861 pr_debug("%s: Media selection failed, now trying %s port.\n",
1862 dev->name, media_tbl[dev->if_port].name);
1863 next_tick = media_tbl[dev->if_port].wait;
1866 (media_status & ~(Media_10TP|Media_SQE)) |
1867 media_tbl[dev->if_port].media_bits,
1870 config = window_read32(vp, 3, Wn3_Config);
1871 config = BFINS(config, dev->if_port, 20, 4);
1872 window_write32(vp, config, 3, Wn3_Config);
1874 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1876 if (vortex_debug > 1)
1877 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1878 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1880 spin_unlock_irq(&vp->lock);
1884 if (vortex_debug > 2)
1885 pr_debug("%s: Media selection timer finished, %s.\n",
1886 dev->name, media_tbl[dev->if_port].name);
1888 mod_timer(&vp->timer, RUN_AT(next_tick));
1890 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1893 static void vortex_tx_timeout(struct net_device *dev)
1895 struct vortex_private *vp = netdev_priv(dev);
1896 void __iomem *ioaddr = vp->ioaddr;
1898 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1899 dev->name, ioread8(ioaddr + TxStatus),
1900 ioread16(ioaddr + EL3_STATUS));
1901 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1902 window_read16(vp, 4, Wn4_NetDiag),
1903 window_read16(vp, 4, Wn4_Media),
1904 ioread32(ioaddr + PktStatus),
1905 window_read16(vp, 4, Wn4_FIFODiag));
1906 /* Slight code bloat to be user friendly. */
1907 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1908 pr_err("%s: Transmitter encountered 16 collisions --"
1909 " network cable problem?\n", dev->name);
1910 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1911 pr_err("%s: Interrupt posted but not delivered --"
1912 " IRQ blocked by another device?\n", dev->name);
1913 /* Bad idea here.. but we might as well handle a few events. */
1916 * Block interrupts because vortex_interrupt does a bare spin_lock()
1918 unsigned long flags;
1919 local_irq_save(flags);
1920 if (vp->full_bus_master_tx)
1921 boomerang_interrupt(dev->irq, dev);
1923 vortex_interrupt(dev->irq, dev);
1924 local_irq_restore(flags);
1928 if (vortex_debug > 0)
1931 issue_and_wait(dev, TxReset);
1933 dev->stats.tx_errors++;
1934 if (vp->full_bus_master_tx) {
1935 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1936 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1937 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1938 ioaddr + DownListPtr);
1939 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1940 netif_wake_queue (dev);
1941 if (vp->drv_flags & IS_BOOMERANG)
1942 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1943 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1945 dev->stats.tx_dropped++;
1946 netif_wake_queue(dev);
1949 /* Issue Tx Enable */
1950 iowrite16(TxEnable, ioaddr + EL3_CMD);
1951 dev->trans_start = jiffies; /* prevent tx timeout */
1955 * Handle uncommon interrupt sources. This is a separate routine to minimize
1959 vortex_error(struct net_device *dev, int status)
1961 struct vortex_private *vp = netdev_priv(dev);
1962 void __iomem *ioaddr = vp->ioaddr;
1963 int do_tx_reset = 0, reset_mask = 0;
1964 unsigned char tx_status = 0;
1966 if (vortex_debug > 2) {
1967 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1970 if (status & TxComplete) { /* Really "TxError" for us. */
1971 tx_status = ioread8(ioaddr + TxStatus);
1972 /* Presumably a tx-timeout. We must merely re-enable. */
1973 if (vortex_debug > 2 ||
1974 (tx_status != 0x88 && vortex_debug > 0)) {
1975 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1976 dev->name, tx_status);
1977 if (tx_status == 0x82) {
1978 pr_err("Probably a duplex mismatch. See "
1979 "Documentation/networking/vortex.txt\n");
1983 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1984 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1985 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1986 iowrite8(0, ioaddr + TxStatus);
1987 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1989 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1991 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1992 } else { /* Merely re-enable the transmitter. */
1993 iowrite16(TxEnable, ioaddr + EL3_CMD);
1997 if (status & RxEarly) { /* Rx early is unused. */
1999 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
2001 if (status & StatsFull) { /* Empty statistics. */
2002 static int DoneDidThat;
2003 if (vortex_debug > 4)
2004 pr_debug("%s: Updating stats.\n", dev->name);
2005 update_stats(ioaddr, dev);
2006 /* HACK: Disable statistics as an interrupt source. */
2007 /* This occurs when we have the wrong media type! */
2008 if (DoneDidThat == 0 &&
2009 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2010 pr_warning("%s: Updating statistics failed, disabling "
2011 "stats as an interrupt source.\n", dev->name);
2012 iowrite16(SetIntrEnb |
2013 (window_read16(vp, 5, 10) & ~StatsFull),
2015 vp->intr_enable &= ~StatsFull;
2019 if (status & IntReq) { /* Restore all interrupt sources. */
2020 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2021 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2023 if (status & HostError) {
2025 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2026 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2027 dev->name, fifo_diag);
2028 /* Adapter failure requires Tx/Rx reset and reinit. */
2029 if (vp->full_bus_master_tx) {
2030 int bus_status = ioread32(ioaddr + PktStatus);
2031 /* 0x80000000 PCI master abort. */
2032 /* 0x40000000 PCI target abort. */
2034 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2036 /* In this case, blow the card away */
2037 /* Must not enter D3 or we can't legally issue the reset! */
2038 vortex_down(dev, 0);
2039 issue_and_wait(dev, TotalReset | 0xff);
2040 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
2041 } else if (fifo_diag & 0x0400)
2043 if (fifo_diag & 0x3000) {
2044 /* Reset Rx fifo and upload logic */
2045 issue_and_wait(dev, RxReset|0x07);
2046 /* Set the Rx filter to the current state. */
2048 /* enable 802.1q VLAN tagged frames */
2049 set_8021q_mode(dev, 1);
2050 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2051 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2056 issue_and_wait(dev, TxReset|reset_mask);
2057 iowrite16(TxEnable, ioaddr + EL3_CMD);
2058 if (!vp->full_bus_master_tx)
2059 netif_wake_queue(dev);
2064 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2066 struct vortex_private *vp = netdev_priv(dev);
2067 void __iomem *ioaddr = vp->ioaddr;
2069 /* Put out the doubleword header... */
2070 iowrite32(skb->len, ioaddr + TX_FIFO);
2071 if (vp->bus_master) {
2072 /* Set the bus-master controller to transfer the packet. */
2073 int len = (skb->len + 3) & ~3;
2074 vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len,
2076 spin_lock_irq(&vp->window_lock);
2078 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2079 iowrite16(len, ioaddr + Wn7_MasterLen);
2080 spin_unlock_irq(&vp->window_lock);
2082 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2083 /* netif_wake_queue() will be called at the DMADone interrupt. */
2085 /* ... and the packet rounded to a doubleword. */
2086 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2087 dev_kfree_skb (skb);
2088 if (ioread16(ioaddr + TxFree) > 1536) {
2089 netif_start_queue (dev); /* AKPM: redundant? */
2091 /* Interrupt us when the FIFO has room for max-sized packet. */
2092 netif_stop_queue(dev);
2093 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2098 /* Clear the Tx status stack. */
2103 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2104 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2105 if (vortex_debug > 2)
2106 pr_debug("%s: Tx error, status %2.2x.\n",
2107 dev->name, tx_status);
2108 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2109 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2110 if (tx_status & 0x30) {
2111 issue_and_wait(dev, TxReset);
2113 iowrite16(TxEnable, ioaddr + EL3_CMD);
2115 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2118 return NETDEV_TX_OK;
2122 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2124 struct vortex_private *vp = netdev_priv(dev);
2125 void __iomem *ioaddr = vp->ioaddr;
2126 /* Calculate the next Tx descriptor entry. */
2127 int entry = vp->cur_tx % TX_RING_SIZE;
2128 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2129 unsigned long flags;
2131 if (vortex_debug > 6) {
2132 pr_debug("boomerang_start_xmit()\n");
2133 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2134 dev->name, vp->cur_tx);
2138 * We can't allow a recursion from our interrupt handler back into the
2139 * tx routine, as they take the same spin lock, and that causes
2140 * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
2143 if (vp->handling_irq)
2144 return NETDEV_TX_BUSY;
2146 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2147 if (vortex_debug > 0)
2148 pr_warning("%s: BUG! Tx Ring full, refusing to send buffer.\n",
2150 netif_stop_queue(dev);
2151 return NETDEV_TX_BUSY;
2154 vp->tx_skbuff[entry] = skb;
2156 vp->tx_ring[entry].next = 0;
2158 if (skb->ip_summed != CHECKSUM_PARTIAL)
2159 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2161 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2163 if (!skb_shinfo(skb)->nr_frags) {
2164 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2165 skb->len, PCI_DMA_TODEVICE));
2166 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2170 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2171 skb_headlen(skb), PCI_DMA_TODEVICE));
2172 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2174 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2175 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2177 vp->tx_ring[entry].frag[i+1].addr =
2178 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2179 (void*)page_address(frag->page) + frag->page_offset,
2180 frag->size, PCI_DMA_TODEVICE));
2182 if (i == skb_shinfo(skb)->nr_frags-1)
2183 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2185 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2189 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2190 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2191 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2194 spin_lock_irqsave(&vp->lock, flags);
2195 /* Wait for the stall to complete. */
2196 issue_and_wait(dev, DownStall);
2197 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2198 if (ioread32(ioaddr + DownListPtr) == 0) {
2199 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2200 vp->queued_packet++;
2204 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2205 netif_stop_queue (dev);
2206 } else { /* Clear previous interrupt enable. */
2207 #if defined(tx_interrupt_mitigation)
2208 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2209 * were selected, this would corrupt DN_COMPLETE. No?
2211 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2214 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2215 spin_unlock_irqrestore(&vp->lock, flags);
2216 return NETDEV_TX_OK;
2219 /* The interrupt handler does all of the Rx thread work and cleans up
2220 after the Tx thread. */
2223 * This is the ISR for the vortex series chips.
2224 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2228 vortex_interrupt(int irq, void *dev_id)
2230 struct net_device *dev = dev_id;
2231 struct vortex_private *vp = netdev_priv(dev);
2232 void __iomem *ioaddr;
2234 int work_done = max_interrupt_work;
2237 ioaddr = vp->ioaddr;
2238 spin_lock(&vp->lock);
2240 status = ioread16(ioaddr + EL3_STATUS);
2242 if (vortex_debug > 6)
2243 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2245 if ((status & IntLatch) == 0)
2246 goto handler_exit; /* No interrupt: shared IRQs cause this */
2249 if (status & IntReq) {
2250 status |= vp->deferred;
2254 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2257 if (vortex_debug > 4)
2258 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2259 dev->name, status, ioread8(ioaddr + Timer));
2261 spin_lock(&vp->window_lock);
2265 if (vortex_debug > 5)
2266 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2268 if (status & RxComplete)
2271 if (status & TxAvailable) {
2272 if (vortex_debug > 5)
2273 pr_debug(" TX room bit was handled.\n");
2274 /* There's room in the FIFO for a full-sized packet. */
2275 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2276 netif_wake_queue (dev);
2279 if (status & DMADone) {
2280 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2281 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2282 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2283 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2284 if (ioread16(ioaddr + TxFree) > 1536) {
2286 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2287 * insufficient FIFO room, the TxAvailable test will succeed and call
2288 * netif_wake_queue()
2290 netif_wake_queue(dev);
2291 } else { /* Interrupt when FIFO has room for max-sized packet. */
2292 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2293 netif_stop_queue(dev);
2297 /* Check for all uncommon interrupts at once. */
2298 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2299 if (status == 0xffff)
2301 vortex_error(dev, status);
2304 if (--work_done < 0) {
2305 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2307 /* Disable all pending interrupts. */
2309 vp->deferred |= status;
2310 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2312 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2313 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2314 /* The timer will reenable interrupts. */
2315 mod_timer(&vp->timer, jiffies + 1*HZ);
2318 /* Acknowledge the IRQ. */
2319 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2320 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2322 spin_unlock(&vp->window_lock);
2324 if (vortex_debug > 4)
2325 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2328 spin_unlock(&vp->lock);
2329 return IRQ_RETVAL(handled);
2333 * This is the ISR for the boomerang series chips.
2334 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2338 boomerang_interrupt(int irq, void *dev_id)
2340 struct net_device *dev = dev_id;
2341 struct vortex_private *vp = netdev_priv(dev);
2342 void __iomem *ioaddr;
2344 int work_done = max_interrupt_work;
2346 ioaddr = vp->ioaddr;
2350 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2351 * and boomerang_start_xmit
2353 spin_lock(&vp->lock);
2354 vp->handling_irq = 1;
2356 status = ioread16(ioaddr + EL3_STATUS);
2358 if (vortex_debug > 6)
2359 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2361 if ((status & IntLatch) == 0)
2362 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2364 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2365 if (vortex_debug > 1)
2366 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2370 if (status & IntReq) {
2371 status |= vp->deferred;
2375 if (vortex_debug > 4)
2376 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2377 dev->name, status, ioread8(ioaddr + Timer));
2379 if (vortex_debug > 5)
2380 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2382 if (status & UpComplete) {
2383 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2384 if (vortex_debug > 5)
2385 pr_debug("boomerang_interrupt->boomerang_rx\n");
2389 if (status & DownComplete) {
2390 unsigned int dirty_tx = vp->dirty_tx;
2392 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2393 while (vp->cur_tx - dirty_tx > 0) {
2394 int entry = dirty_tx % TX_RING_SIZE;
2395 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2396 if (ioread32(ioaddr + DownListPtr) ==
2397 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2398 break; /* It still hasn't been processed. */
2400 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2401 break; /* It still hasn't been processed. */
2404 if (vp->tx_skbuff[entry]) {
2405 struct sk_buff *skb = vp->tx_skbuff[entry];
2408 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2409 pci_unmap_single(VORTEX_PCI(vp),
2410 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2411 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2414 pci_unmap_single(VORTEX_PCI(vp),
2415 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2417 dev_kfree_skb_irq(skb);
2418 vp->tx_skbuff[entry] = NULL;
2420 pr_debug("boomerang_interrupt: no skb!\n");
2422 /* dev->stats.tx_packets++; Counted below. */
2425 vp->dirty_tx = dirty_tx;
2426 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2427 if (vortex_debug > 6)
2428 pr_debug("boomerang_interrupt: wake queue\n");
2429 netif_wake_queue (dev);
2433 /* Check for all uncommon interrupts at once. */
2434 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2435 vortex_error(dev, status);
2437 if (--work_done < 0) {
2438 pr_warning("%s: Too much work in interrupt, status %4.4x.\n",
2440 /* Disable all pending interrupts. */
2442 vp->deferred |= status;
2443 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2445 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2446 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2447 /* The timer will reenable interrupts. */
2448 mod_timer(&vp->timer, jiffies + 1*HZ);
2451 /* Acknowledge the IRQ. */
2452 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2453 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2454 iowrite32(0x8000, vp->cb_fn_base + 4);
2456 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2458 if (vortex_debug > 4)
2459 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2462 vp->handling_irq = 0;
2463 spin_unlock(&vp->lock);
2467 static int vortex_rx(struct net_device *dev)
2469 struct vortex_private *vp = netdev_priv(dev);
2470 void __iomem *ioaddr = vp->ioaddr;
2474 if (vortex_debug > 5)
2475 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2476 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2477 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2478 if (rx_status & 0x4000) { /* Error, update stats. */
2479 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2480 if (vortex_debug > 2)
2481 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2482 dev->stats.rx_errors++;
2483 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2484 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2485 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2486 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2487 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2489 /* The packet length: up to 4.5K!. */
2490 int pkt_len = rx_status & 0x1fff;
2491 struct sk_buff *skb;
2493 skb = dev_alloc_skb(pkt_len + 5);
2494 if (vortex_debug > 4)
2495 pr_debug("Receiving packet size %d status %4.4x.\n",
2496 pkt_len, rx_status);
2498 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2499 /* 'skb_put()' points to the start of sk_buff data area. */
2500 if (vp->bus_master &&
2501 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2502 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2503 pkt_len, PCI_DMA_FROMDEVICE);
2504 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2505 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2506 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2507 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2509 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2511 ioread32_rep(ioaddr + RX_FIFO,
2512 skb_put(skb, pkt_len),
2513 (pkt_len + 3) >> 2);
2515 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2516 skb->protocol = eth_type_trans(skb, dev);
2518 dev->stats.rx_packets++;
2519 /* Wait a limited time to go to next packet. */
2520 for (i = 200; i >= 0; i--)
2521 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2524 } else if (vortex_debug > 0)
2525 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2526 dev->name, pkt_len);
2527 dev->stats.rx_dropped++;
2529 issue_and_wait(dev, RxDiscard);
2536 boomerang_rx(struct net_device *dev)
2538 struct vortex_private *vp = netdev_priv(dev);
2539 int entry = vp->cur_rx % RX_RING_SIZE;
2540 void __iomem *ioaddr = vp->ioaddr;
2542 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2544 if (vortex_debug > 5)
2545 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2547 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2548 if (--rx_work_limit < 0)
2550 if (rx_status & RxDError) { /* Error, update stats. */
2551 unsigned char rx_error = rx_status >> 16;
2552 if (vortex_debug > 2)
2553 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2554 dev->stats.rx_errors++;
2555 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2556 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2557 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2558 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2559 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2561 /* The packet length: up to 4.5K!. */
2562 int pkt_len = rx_status & 0x1fff;
2563 struct sk_buff *skb;
2564 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2566 if (vortex_debug > 4)
2567 pr_debug("Receiving packet size %d status %4.4x.\n",
2568 pkt_len, rx_status);
2570 /* Check if the packet is long enough to just accept without
2571 copying to a properly sized skbuff. */
2572 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
2573 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2574 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2575 /* 'skb_put()' points to the start of sk_buff data area. */
2576 memcpy(skb_put(skb, pkt_len),
2577 vp->rx_skbuff[entry]->data,
2579 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2582 /* Pass up the skbuff already on the Rx ring. */
2583 skb = vp->rx_skbuff[entry];
2584 vp->rx_skbuff[entry] = NULL;
2585 skb_put(skb, pkt_len);
2586 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2589 skb->protocol = eth_type_trans(skb, dev);
2590 { /* Use hardware checksum info. */
2591 int csum_bits = rx_status & 0xee000000;
2593 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2594 csum_bits == (IPChksumValid | UDPChksumValid))) {
2595 skb->ip_summed = CHECKSUM_UNNECESSARY;
2600 dev->stats.rx_packets++;
2602 entry = (++vp->cur_rx) % RX_RING_SIZE;
2604 /* Refill the Rx ring buffers. */
2605 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2606 struct sk_buff *skb;
2607 entry = vp->dirty_rx % RX_RING_SIZE;
2608 if (vp->rx_skbuff[entry] == NULL) {
2609 skb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2611 static unsigned long last_jif;
2612 if (time_after(jiffies, last_jif + 10 * HZ)) {
2613 pr_warning("%s: memory shortage\n", dev->name);
2616 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2617 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2618 break; /* Bad news! */
2621 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2622 vp->rx_skbuff[entry] = skb;
2624 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2625 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2631 * If we've hit a total OOM refilling the Rx ring we poll once a second
2632 * for some memory. Otherwise there is no way to restart the rx process.
2635 rx_oom_timer(unsigned long arg)
2637 struct net_device *dev = (struct net_device *)arg;
2638 struct vortex_private *vp = netdev_priv(dev);
2640 spin_lock_irq(&vp->lock);
2641 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2643 if (vortex_debug > 1) {
2644 pr_debug("%s: rx_oom_timer %s\n", dev->name,
2645 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2647 spin_unlock_irq(&vp->lock);
2651 vortex_down(struct net_device *dev, int final_down)
2653 struct vortex_private *vp = netdev_priv(dev);
2654 void __iomem *ioaddr = vp->ioaddr;
2656 netif_stop_queue (dev);
2658 del_timer_sync(&vp->rx_oom_timer);
2659 del_timer_sync(&vp->timer);
2661 /* Turn off statistics ASAP. We update dev->stats below. */
2662 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2664 /* Disable the receiver and transmitter. */
2665 iowrite16(RxDisable, ioaddr + EL3_CMD);
2666 iowrite16(TxDisable, ioaddr + EL3_CMD);
2668 /* Disable receiving 802.1q tagged frames */
2669 set_8021q_mode(dev, 0);
2671 if (dev->if_port == XCVR_10base2)
2672 /* Turn off thinnet power. Green! */
2673 iowrite16(StopCoax, ioaddr + EL3_CMD);
2675 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2677 update_stats(ioaddr, dev);
2678 if (vp->full_bus_master_rx)
2679 iowrite32(0, ioaddr + UpListPtr);
2680 if (vp->full_bus_master_tx)
2681 iowrite32(0, ioaddr + DownListPtr);
2683 if (final_down && VORTEX_PCI(vp)) {
2684 vp->pm_state_valid = 1;
2685 pci_save_state(VORTEX_PCI(vp));
2691 vortex_close(struct net_device *dev)
2693 struct vortex_private *vp = netdev_priv(dev);
2694 void __iomem *ioaddr = vp->ioaddr;
2697 if (netif_device_present(dev))
2698 vortex_down(dev, 1);
2700 if (vortex_debug > 1) {
2701 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2702 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2703 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2704 " tx_queued %d Rx pre-checksummed %d.\n",
2705 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2709 if (vp->rx_csumhits &&
2710 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2711 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2712 pr_warning("%s supports hardware checksums, and we're not using them!\n", dev->name);
2716 free_irq(dev->irq, dev);
2718 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2719 for (i = 0; i < RX_RING_SIZE; i++)
2720 if (vp->rx_skbuff[i]) {
2721 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2722 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2723 dev_kfree_skb(vp->rx_skbuff[i]);
2724 vp->rx_skbuff[i] = NULL;
2727 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2728 for (i = 0; i < TX_RING_SIZE; i++) {
2729 if (vp->tx_skbuff[i]) {
2730 struct sk_buff *skb = vp->tx_skbuff[i];
2734 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2735 pci_unmap_single(VORTEX_PCI(vp),
2736 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2737 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2740 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2743 vp->tx_skbuff[i] = NULL;
2752 dump_tx_ring(struct net_device *dev)
2754 if (vortex_debug > 0) {
2755 struct vortex_private *vp = netdev_priv(dev);
2756 void __iomem *ioaddr = vp->ioaddr;
2758 if (vp->full_bus_master_tx) {
2760 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2762 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2763 vp->full_bus_master_tx,
2764 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2765 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2766 pr_err(" Transmit list %8.8x vs. %p.\n",
2767 ioread32(ioaddr + DownListPtr),
2768 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2769 issue_and_wait(dev, DownStall);
2770 for (i = 0; i < TX_RING_SIZE; i++) {
2771 unsigned int length;
2774 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2776 length = le32_to_cpu(vp->tx_ring[i].length);
2778 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2779 i, &vp->tx_ring[i], length,
2780 le32_to_cpu(vp->tx_ring[i].status));
2783 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2788 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2790 struct vortex_private *vp = netdev_priv(dev);
2791 void __iomem *ioaddr = vp->ioaddr;
2792 unsigned long flags;
2794 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2795 spin_lock_irqsave (&vp->lock, flags);
2796 update_stats(ioaddr, dev);
2797 spin_unlock_irqrestore (&vp->lock, flags);
2802 /* Update statistics.
2803 Unlike with the EL3 we need not worry about interrupts changing
2804 the window setting from underneath us, but we must still guard
2805 against a race condition with a StatsUpdate interrupt updating the
2806 table. This is done by checking that the ASM (!) code generated uses
2807 atomic updates with '+='.
2809 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2811 struct vortex_private *vp = netdev_priv(dev);
2813 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2814 /* Switch to the stats window, and read everything. */
2815 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2816 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2817 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2818 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2819 dev->stats.tx_packets += window_read8(vp, 6, 6);
2820 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2822 /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
2823 /* Don't bother with register 9, an extension of registers 6&7.
2824 If we do use the 6&7 values the atomic update assumption above
2826 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2827 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2828 /* Extra stats for get_ethtool_stats() */
2829 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2830 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2831 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2832 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2834 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2835 + vp->xstats.tx_single_collisions
2836 + vp->xstats.tx_max_collisions;
2839 u8 up = window_read8(vp, 4, 13);
2840 dev->stats.rx_bytes += (up & 0x0f) << 16;
2841 dev->stats.tx_bytes += (up & 0xf0) << 12;
2845 static int vortex_nway_reset(struct net_device *dev)
2847 struct vortex_private *vp = netdev_priv(dev);
2849 return mii_nway_restart(&vp->mii);
2852 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2854 struct vortex_private *vp = netdev_priv(dev);
2856 return mii_ethtool_gset(&vp->mii, cmd);
2859 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2861 struct vortex_private *vp = netdev_priv(dev);
2863 return mii_ethtool_sset(&vp->mii, cmd);
2866 static u32 vortex_get_msglevel(struct net_device *dev)
2868 return vortex_debug;
2871 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2876 static int vortex_get_sset_count(struct net_device *dev, int sset)
2880 return VORTEX_NUM_STATS;
2886 static void vortex_get_ethtool_stats(struct net_device *dev,
2887 struct ethtool_stats *stats, u64 *data)
2889 struct vortex_private *vp = netdev_priv(dev);
2890 void __iomem *ioaddr = vp->ioaddr;
2891 unsigned long flags;
2893 spin_lock_irqsave(&vp->lock, flags);
2894 update_stats(ioaddr, dev);
2895 spin_unlock_irqrestore(&vp->lock, flags);
2897 data[0] = vp->xstats.tx_deferred;
2898 data[1] = vp->xstats.tx_max_collisions;
2899 data[2] = vp->xstats.tx_multiple_collisions;
2900 data[3] = vp->xstats.tx_single_collisions;
2901 data[4] = vp->xstats.rx_bad_ssd;
2905 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2907 switch (stringset) {
2909 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2917 static void vortex_get_drvinfo(struct net_device *dev,
2918 struct ethtool_drvinfo *info)
2920 struct vortex_private *vp = netdev_priv(dev);
2922 strcpy(info->driver, DRV_NAME);
2923 if (VORTEX_PCI(vp)) {
2924 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2926 if (VORTEX_EISA(vp))
2927 strcpy(info->bus_info, dev_name(vp->gendev));
2929 sprintf(info->bus_info, "EISA 0x%lx %d",
2930 dev->base_addr, dev->irq);
2934 static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2936 struct vortex_private *vp = netdev_priv(dev);
2938 spin_lock_irq(&vp->lock);
2939 wol->supported = WAKE_MAGIC;
2943 wol->wolopts |= WAKE_MAGIC;
2944 spin_unlock_irq(&vp->lock);
2947 static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2949 struct vortex_private *vp = netdev_priv(dev);
2950 if (wol->wolopts & ~WAKE_MAGIC)
2953 spin_lock_irq(&vp->lock);
2954 if (wol->wolopts & WAKE_MAGIC)
2959 spin_unlock_irq(&vp->lock);
2964 static const struct ethtool_ops vortex_ethtool_ops = {
2965 .get_drvinfo = vortex_get_drvinfo,
2966 .get_strings = vortex_get_strings,
2967 .get_msglevel = vortex_get_msglevel,
2968 .set_msglevel = vortex_set_msglevel,
2969 .get_ethtool_stats = vortex_get_ethtool_stats,
2970 .get_sset_count = vortex_get_sset_count,
2971 .get_settings = vortex_get_settings,
2972 .set_settings = vortex_set_settings,
2973 .get_link = ethtool_op_get_link,
2974 .nway_reset = vortex_nway_reset,
2975 .get_wol = vortex_get_wol,
2976 .set_wol = vortex_set_wol,
2981 * Must power the device up to do MDIO operations
2983 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2986 struct vortex_private *vp = netdev_priv(dev);
2987 pci_power_t state = 0;
2990 state = VORTEX_PCI(vp)->current_state;
2992 /* The kernel core really should have pci_get_power_state() */
2995 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2996 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2998 pci_set_power_state(VORTEX_PCI(vp), state);
3005 /* Pre-Cyclone chips have no documented multicast filter, so the only
3006 multicast setting is to receive all multicast frames. At least
3007 the chip has a very clean way to set the mode, unlike many others. */
3008 static void set_rx_mode(struct net_device *dev)
3010 struct vortex_private *vp = netdev_priv(dev);
3011 void __iomem *ioaddr = vp->ioaddr;
3014 if (dev->flags & IFF_PROMISC) {
3015 if (vortex_debug > 3)
3016 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3017 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3018 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3019 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3021 new_mode = SetRxFilter | RxStation | RxBroadcast;
3023 iowrite16(new_mode, ioaddr + EL3_CMD);
3026 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
3027 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
3028 Note that this must be done after each RxReset due to some backwards
3029 compatibility logic in the Cyclone and Tornado ASICs */
3031 /* The Ethernet Type used for 802.1q tagged frames */
3032 #define VLAN_ETHER_TYPE 0x8100
3034 static void set_8021q_mode(struct net_device *dev, int enable)
3036 struct vortex_private *vp = netdev_priv(dev);
3039 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3040 /* cyclone and tornado chipsets can recognize 802.1q
3041 * tagged frames and treat them correctly */
3043 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
3045 max_pkt_size += 4; /* 802.1Q VLAN tag */
3047 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3049 /* set VlanEtherType to let the hardware checksumming
3050 treat tagged frames correctly */
3051 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3053 /* on older cards we have to enable large frames */
3055 vp->large_frames = dev->mtu > 1500 || enable;
3057 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3058 if (vp->large_frames)
3062 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3067 static void set_8021q_mode(struct net_device *dev, int enable)
3074 /* MII transceiver control section.
3075 Read and write the MII registers using software-generated serial
3076 MDIO protocol. See the MII specifications or DP83840A data sheet
3079 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3080 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3081 "overclocking" issues. */
3082 static void mdio_delay(struct vortex_private *vp)
3084 window_read32(vp, 4, Wn4_PhysicalMgmt);
3087 #define MDIO_SHIFT_CLK 0x01
3088 #define MDIO_DIR_WRITE 0x04
3089 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3090 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3091 #define MDIO_DATA_READ 0x02
3092 #define MDIO_ENB_IN 0x00
3094 /* Generate the preamble required for initial synchronization and
3095 a few older transceivers. */
3096 static void mdio_sync(struct vortex_private *vp, int bits)
3098 /* Establish sync by sending at least 32 logic ones. */
3099 while (-- bits >= 0) {
3100 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3102 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3103 4, Wn4_PhysicalMgmt);
3108 static int mdio_read(struct net_device *dev, int phy_id, int location)
3111 struct vortex_private *vp = netdev_priv(dev);
3112 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3113 unsigned int retval = 0;
3115 spin_lock_bh(&vp->mii_lock);
3117 if (mii_preamble_required)
3120 /* Shift the read command bits out. */
3121 for (i = 14; i >= 0; i--) {
3122 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3123 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3125 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3126 4, Wn4_PhysicalMgmt);
3129 /* Read the two transition, 16 data, and wire-idle bits. */
3130 for (i = 19; i > 0; i--) {
3131 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3133 retval = (retval << 1) |
3134 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3135 MDIO_DATA_READ) ? 1 : 0);
3136 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3137 4, Wn4_PhysicalMgmt);
3141 spin_unlock_bh(&vp->mii_lock);
3143 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3146 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3148 struct vortex_private *vp = netdev_priv(dev);
3149 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3152 spin_lock_bh(&vp->mii_lock);
3154 if (mii_preamble_required)
3157 /* Shift the command bits out. */
3158 for (i = 31; i >= 0; i--) {
3159 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3160 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3162 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3163 4, Wn4_PhysicalMgmt);
3166 /* Leave the interface idle. */
3167 for (i = 1; i >= 0; i--) {
3168 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3170 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3171 4, Wn4_PhysicalMgmt);
3175 spin_unlock_bh(&vp->mii_lock);
3178 /* ACPI: Advanced Configuration and Power Interface. */
3179 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3180 static void acpi_set_WOL(struct net_device *dev)
3182 struct vortex_private *vp = netdev_priv(dev);
3183 void __iomem *ioaddr = vp->ioaddr;
3185 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3187 if (vp->enable_wol) {
3188 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3189 window_write16(vp, 2, 7, 0x0c);
3190 /* The RxFilter must accept the WOL frames. */
3191 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3192 iowrite16(RxEnable, ioaddr + EL3_CMD);
3194 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3195 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3201 /* Change the power state to D3; RxEnable doesn't take effect. */
3202 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3207 static void __devexit vortex_remove_one(struct pci_dev *pdev)
3209 struct net_device *dev = pci_get_drvdata(pdev);
3210 struct vortex_private *vp;
3213 pr_err("vortex_remove_one called for Compaq device!\n");
3217 vp = netdev_priv(dev);
3220 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3222 unregister_netdev(dev);
3224 if (VORTEX_PCI(vp)) {
3225 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3226 if (vp->pm_state_valid)
3227 pci_restore_state(VORTEX_PCI(vp));
3228 pci_disable_device(VORTEX_PCI(vp));
3230 /* Should really use issue_and_wait() here */
3231 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3232 vp->ioaddr + EL3_CMD);
3234 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3236 pci_free_consistent(pdev,
3237 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3238 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3241 if (vp->must_free_region)
3242 release_region(dev->base_addr, vp->io_size);
3247 static struct pci_driver vortex_driver = {
3249 .probe = vortex_init_one,
3250 .remove = __devexit_p(vortex_remove_one),
3251 .id_table = vortex_pci_tbl,
3252 .driver.pm = VORTEX_PM_OPS,
3256 static int vortex_have_pci;
3257 static int vortex_have_eisa;
3260 static int __init vortex_init(void)
3262 int pci_rc, eisa_rc;
3264 pci_rc = pci_register_driver(&vortex_driver);
3265 eisa_rc = vortex_eisa_init();
3268 vortex_have_pci = 1;
3270 vortex_have_eisa = 1;
3272 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3276 static void __exit vortex_eisa_cleanup(void)
3278 struct vortex_private *vp;
3279 void __iomem *ioaddr;
3282 /* Take care of the EISA devices */
3283 eisa_driver_unregister(&vortex_eisa_driver);
3286 if (compaq_net_device) {
3287 vp = netdev_priv(compaq_net_device);
3288 ioaddr = ioport_map(compaq_net_device->base_addr,
3291 unregister_netdev(compaq_net_device);
3292 iowrite16(TotalReset, ioaddr + EL3_CMD);
3293 release_region(compaq_net_device->base_addr,
3296 free_netdev(compaq_net_device);
3301 static void __exit vortex_cleanup(void)
3303 if (vortex_have_pci)
3304 pci_unregister_driver(&vortex_driver);
3305 if (vortex_have_eisa)
3306 vortex_eisa_cleanup();
3310 module_init(vortex_init);
3311 module_exit(vortex_cleanup);