1 /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
3 Written 1996-1999 by Donald Becker.
5 This software may be used and distributed according to the terms
6 of the GNU General Public License, incorporated herein by reference.
8 This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
9 Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
10 and the EtherLink XL 3c900 and 3c905 cards.
12 Problem reports and questions should be directed to
15 The author may be reached as becker@scyld.com, or C/O
16 Scyld Computing Corporation
17 410 Severn Ave., Suite 210
23 * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
24 * as well as other drivers
26 * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
27 * due to dead code elimination. There will be some performance benefits from this due to
28 * elimination of all the tests and reduced cache footprint.
32 #define DRV_NAME "3c59x"
36 /* A few values that may be tweaked. */
37 /* Keep the ring sizes a power of two for efficiency. */
38 #define TX_RING_SIZE 16
39 #define RX_RING_SIZE 32
40 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
42 /* "Knobs" that adjust features and parameters. */
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1512 effectively disables this feature. */
46 static int rx_copybreak = 200;
48 /* ARM systems perform better by disregarding the bus-master
49 transfer capability of these cards. -- rmk */
50 static int rx_copybreak = 1513;
52 /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
53 static const int mtu = 1500;
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static int max_interrupt_work = 32;
56 /* Tx timeout interval (millisecs) */
57 static int watchdog = 5000;
59 /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
60 * of possible Tx stalls if the system is blocking interrupts
61 * somewhere else. Undefine this to disable.
63 #define tx_interrupt_mitigation 1
65 /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
66 #define vortex_debug debug
68 static int vortex_debug = VORTEX_DEBUG;
70 static int vortex_debug = 1;
73 #include <linux/module.h>
74 #include <linux/kernel.h>
75 #include <linux/string.h>
76 #include <linux/timer.h>
77 #include <linux/errno.h>
79 #include <linux/ioport.h>
80 #include <linux/slab.h>
81 #include <linux/interrupt.h>
82 #include <linux/pci.h>
83 #include <linux/mii.h>
84 #include <linux/init.h>
85 #include <linux/netdevice.h>
86 #include <linux/etherdevice.h>
87 #include <linux/skbuff.h>
88 #include <linux/ethtool.h>
89 #include <linux/highmem.h>
90 #include <linux/eisa.h>
91 #include <linux/bitops.h>
92 #include <linux/jiffies.h>
93 #include <asm/irq.h> /* For NR_IRQS only. */
95 #include <asm/uaccess.h>
97 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
98 This is only in the support-all-kernels source code. */
100 #define RUN_AT(x) (jiffies + (x))
102 #include <linux/delay.h>
105 static char version[] __devinitdata =
106 DRV_NAME ": Donald Becker and others.\n";
108 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109 MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110 MODULE_LICENSE("GPL");
113 /* Operational parameter that usually are not changed. */
115 /* The Vortex size is twice that of the original EtherLinkIII series: the
116 runtime register window, window 1, is now always mapped in.
117 The Boomerang size is twice as large as the Vortex -- it has additional
118 bus master control registers. */
119 #define VORTEX_TOTAL_SIZE 0x20
120 #define BOOMERANG_TOTAL_SIZE 0x40
122 /* Set iff a MII transceiver on any interface requires mdio preamble.
123 This only set with the original DP83840 on older 3c905 boards, so the extra
124 code size of a per-interface flag is not worthwhile. */
125 static char mii_preamble_required;
127 #define PFX DRV_NAME ": "
134 I. Board Compatibility
136 This device driver is designed for the 3Com FastEtherLink and FastEtherLink
137 XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
138 versions of the FastEtherLink cards. The supported product IDs are
139 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
141 The related ISA 3c515 is supported with a separate driver, 3c515.c, included
142 with the kernel source or available from
143 cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
145 II. Board-specific settings
147 PCI bus devices are configured by the system at boot time, so no jumpers
148 need to be set on the board. The system BIOS should be set to assign the
149 PCI INTA signal to an otherwise unused system IRQ line.
151 The EEPROM settings for media type and forced-full-duplex are observed.
152 The EEPROM media type should be left at the default "autoselect" unless using
153 10base2 or AUI connections which cannot be reliably detected.
155 III. Driver operation
157 The 3c59x series use an interface that's very similar to the previous 3c5x9
158 series. The primary interface is two programmed-I/O FIFOs, with an
159 alternate single-contiguous-region bus-master transfer (see next).
161 The 3c900 "Boomerang" series uses a full-bus-master interface with separate
162 lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
163 DEC Tulip and Intel Speedo3. The first chip version retains a compatible
164 programmed-I/O interface that has been removed in 'B' and subsequent board
167 One extension that is advertised in a very large font is that the adapters
168 are capable of being bus masters. On the Vortex chip this capability was
169 only for a single contiguous region making it far less useful than the full
170 bus master capability. There is a significant performance impact of taking
171 an extra interrupt or polling for the completion of each transfer, as well
172 as difficulty sharing the single transfer engine between the transmit and
173 receive threads. Using DMA transfers is a win only with large blocks or
174 with the flawed versions of the Intel Orion motherboard PCI controller.
176 The Boomerang chip's full-bus-master interface is useful, and has the
177 currently-unused advantages over other similar chips that queued transmit
178 packets may be reordered and receive buffer groups are associated with a
181 With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
182 Rather than a fixed intermediate receive buffer, this scheme allocates
183 full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
184 the copying breakpoint: it is chosen to trade-off the memory wasted by
185 passing the full-sized skbuff to the queue layer for all frames vs. the
186 copying cost of copying a frame to a correctly-sized skbuff.
188 IIIC. Synchronization
189 The driver runs as two independent, single-threaded flows of control. One
190 is the send-packet routine, which enforces single-threaded use by the
191 dev->tbusy flag. The other thread is the interrupt handler, which is single
192 threaded by the hardware and other software.
196 Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
197 3c590, 3c595, and 3c900 boards.
198 The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
199 the EISA version is called "Demon". According to Terry these names come
200 from rides at the local amusement park.
202 The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
203 This driver only supports ethernet packets because of the skbuff allocation
207 /* This table drives the PCI probe routines. It's mostly boilerplate in all
208 of the drivers, and will likely be provided by some future kernel.
214 enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
270 /* note: this array directly indexed by above enums, and MUST
271 * be kept in sync with both the enums above, and the PCI device
274 static struct vortex_chip_info {
279 } vortex_info_tbl[] __devinitdata = {
280 {"3c590 Vortex 10Mbps",
281 PCI_USES_MASTER, IS_VORTEX, 32, },
282 {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
283 PCI_USES_MASTER, IS_VORTEX, 32, },
284 {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
285 PCI_USES_MASTER, IS_VORTEX, 32, },
286 {"3c595 Vortex 100baseTx",
287 PCI_USES_MASTER, IS_VORTEX, 32, },
288 {"3c595 Vortex 100baseT4",
289 PCI_USES_MASTER, IS_VORTEX, 32, },
291 {"3c595 Vortex 100base-MII",
292 PCI_USES_MASTER, IS_VORTEX, 32, },
293 {"3c900 Boomerang 10baseT",
294 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
295 {"3c900 Boomerang 10Mbps Combo",
296 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
297 {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
298 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
299 {"3c900 Cyclone 10Mbps Combo",
300 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302 {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
303 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
304 {"3c900B-FL Cyclone 10base-FL",
305 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
306 {"3c905 Boomerang 100baseTx",
307 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
308 {"3c905 Boomerang 100baseT4",
309 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
310 {"3c905B Cyclone 100baseTx",
311 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 10/100/BNC",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
315 {"3c905B-FX Cyclone 100baseFx",
316 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
318 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
319 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
320 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
322 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
325 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
326 {"3cSOHO100-TX Hurricane",
327 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
328 {"3c555 Laptop Hurricane",
329 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
330 {"3c556 Laptop Tornado",
331 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
333 {"3c556B Laptop Hurricane",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
335 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
337 {"3c575 [Megahertz] 10/100 LAN CardBus",
338 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
339 {"3c575 Boomerang CardBus",
340 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
341 {"3CCFE575BT Cyclone CardBus",
342 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
343 INVERT_LED_PWR|HAS_HWCKSM, 128, },
344 {"3CCFE575CT Tornado CardBus",
345 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
346 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
347 {"3CCFE656 Cyclone CardBus",
348 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 INVERT_LED_PWR|HAS_HWCKSM, 128, },
351 {"3CCFEM656B Cyclone+Winmodem CardBus",
352 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
353 INVERT_LED_PWR|HAS_HWCKSM, 128, },
354 {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
355 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
357 {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
360 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
361 {"3c982 Hydra Dual Port A",
362 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
364 {"3c982 Hydra Dual Port B",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
367 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
368 {"3c920B-EMB-WNM Tornado",
369 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
371 {NULL,}, /* NULL terminated list. */
375 static struct pci_device_id vortex_pci_tbl[] = {
376 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
377 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
378 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
379 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
380 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
382 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
383 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
384 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
385 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
386 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
388 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
389 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
390 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
391 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
392 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
394 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
395 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
396 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
397 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
398 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
399 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
401 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
402 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
403 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
404 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
405 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
407 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
408 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
409 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
410 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
411 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
413 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
414 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
415 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
416 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
417 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
419 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
420 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
422 {0,} /* 0 terminated list. */
424 MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
427 /* Operational definitions.
428 These are not used by other compilation units and thus are not
429 exported in a ".h" file.
431 First the windows. There are eight register windows, with the command
432 and status registers available in each.
434 #define EL3WINDOW(win_num) iowrite16(SelectWindow + (win_num), ioaddr + EL3_CMD)
436 #define EL3_STATUS 0x0e
438 /* The top five bits written to EL3_CMD are a command, the lower
439 11 bits are the parameter, if applicable.
440 Note that 11 parameters bits was fine for ethernet, but the new chip
441 can handle FDDI length frames (~4500 octets) and now parameters count
442 32-bit 'Dwords' rather than octets. */
445 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
446 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
447 UpStall = 6<<11, UpUnstall = (6<<11)+1,
448 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
449 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
450 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
451 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
452 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
453 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
454 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
456 /* The SetRxFilter command accepts the following classes: */
458 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
460 /* Bits in the general status register. */
462 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
463 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
464 IntReq = 0x0040, StatsFull = 0x0080,
465 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
466 DMAInProgress = 1<<11, /* DMA controller is still busy.*/
467 CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
470 /* Register window 1 offsets, the window used in normal operation.
471 On the Vortex this window is always mapped at offsets 0x10-0x1f. */
473 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
474 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
475 TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
478 Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
479 Wn0EepromData = 12, /* Window 0: EEPROM results register. */
480 IntrStatus=0x0E, /* Valid in all windows. */
482 enum Win0_EEPROM_bits {
483 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
484 EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
485 EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
487 /* EEPROM locations. */
489 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
490 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
491 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
492 DriverTune=13, Checksum=15};
494 enum Window2 { /* Window 2. */
497 enum Window3 { /* Window 3: MAC/config bits. */
498 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
501 #define BFEXT(value, offset, bitcount) \
502 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
504 #define BFINS(lhs, rhs, offset, bitcount) \
505 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
506 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
508 #define RAM_SIZE(v) BFEXT(v, 0, 3)
509 #define RAM_WIDTH(v) BFEXT(v, 3, 1)
510 #define RAM_SPEED(v) BFEXT(v, 4, 2)
511 #define ROM_SIZE(v) BFEXT(v, 6, 2)
512 #define RAM_SPLIT(v) BFEXT(v, 16, 2)
513 #define XCVR(v) BFEXT(v, 20, 4)
514 #define AUTOSELECT(v) BFEXT(v, 24, 1)
516 enum Window4 { /* Window 4: Xcvr/media bits. */
517 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
519 enum Win4_Media_bits {
520 Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
521 Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
522 Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
523 Media_LnkBeat = 0x0800,
525 enum Window7 { /* Window 7: Bus Master control. */
526 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
527 Wn7_MasterStatus = 12,
529 /* Boomerang bus master control registers. */
531 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
532 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
535 /* The Rx and Tx descriptor lists.
536 Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
537 alignment contraint on tx_ring[] and rx_ring[]. */
538 #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
539 #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
540 struct boom_rx_desc {
541 __le32 next; /* Last entry points to 0. */
543 __le32 addr; /* Up to 63 addr/len pairs possible. */
544 __le32 length; /* Set LAST_FRAG to indicate last pair. */
546 /* Values for the Rx status entry. */
547 enum rx_desc_status {
548 RxDComplete=0x00008000, RxDError=0x4000,
549 /* See boomerang_rx() for actual error bits */
550 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
551 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555 #define DO_ZEROCOPY 1
557 #define DO_ZEROCOPY 0
560 struct boom_tx_desc {
561 __le32 next; /* Last entry points to 0. */
562 __le32 status; /* bits 0:12 length, others see below. */
567 } frag[1+MAX_SKB_FRAGS];
574 /* Values for the Tx status entry. */
575 enum tx_desc_status {
576 CRCDisable=0x2000, TxDComplete=0x8000,
577 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
578 TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
581 /* Chip features we care about in vp->capabilities, read from the EEPROM. */
582 enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
584 struct vortex_extra_stats {
585 unsigned long tx_deferred;
586 unsigned long tx_max_collisions;
587 unsigned long tx_multiple_collisions;
588 unsigned long tx_single_collisions;
589 unsigned long rx_bad_ssd;
592 struct vortex_private {
593 /* The Rx and Tx rings should be quad-word-aligned. */
594 struct boom_rx_desc* rx_ring;
595 struct boom_tx_desc* tx_ring;
596 dma_addr_t rx_ring_dma;
597 dma_addr_t tx_ring_dma;
598 /* The addresses of transmit- and receive-in-place skbuffs. */
599 struct sk_buff* rx_skbuff[RX_RING_SIZE];
600 struct sk_buff* tx_skbuff[TX_RING_SIZE];
601 unsigned int cur_rx, cur_tx; /* The next free ring entry */
602 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
603 struct vortex_extra_stats xstats; /* NIC-specific extra stats */
604 struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
605 dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
607 /* PCI configuration space information. */
608 struct device *gendev;
609 void __iomem *ioaddr; /* IO address space */
610 void __iomem *cb_fn_base; /* CardBus function status addr space. */
612 /* Some values here only for performance evaluation and path-coverage */
613 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
616 /* The remainder are related to chip state, mostly media selection. */
617 struct timer_list timer; /* Media selection timer. */
618 struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */
619 int options; /* User-settable misc. driver options. */
620 unsigned int media_override:4, /* Passed-in media type. */
621 default_media:4, /* Read from the EEPROM/Wn3_Config. */
622 full_duplex:1, autoselect:1,
623 bus_master:1, /* Vortex can only do a fragment bus-m. */
624 full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
625 flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
626 partner_flow_ctrl:1, /* Partner supports flow control */
628 enable_wol:1, /* Wake-on-LAN is enabled */
629 pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
632 must_free_region:1, /* Flag: if zero, Cardbus owns the I/O region */
633 large_frames:1; /* accept large frames */
637 u16 available_media; /* From Wn3_Options. */
638 u16 capabilities, info1, info2; /* Various, from EEPROM. */
639 u16 advertising; /* NWay media advertisement */
640 unsigned char phys[2]; /* MII device addresses. */
641 u16 deferred; /* Resend these interrupts when we
642 * bale from the ISR */
643 u16 io_size; /* Size of PCI region (for release_region) */
644 spinlock_t lock; /* Serialise access to device & its vortex_private */
645 struct mii_if_info mii; /* MII lib hooks/info */
649 #define DEVICE_PCI(dev) (((dev)->bus == &pci_bus_type) ? to_pci_dev((dev)) : NULL)
651 #define DEVICE_PCI(dev) NULL
654 #define VORTEX_PCI(vp) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)
657 #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
659 #define DEVICE_EISA(dev) NULL
662 #define VORTEX_EISA(vp) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)
664 /* The action to take with a media selection timer tick.
665 Note that we deviate from the 3Com order by checking 10base2 before AUI.
668 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
669 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
672 static const struct media_table {
674 unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
675 mask:8, /* The transceiver-present bit in Wn3_Config.*/
676 next:8; /* The media type to try next. */
677 int wait; /* Time before we check media status. */
679 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
680 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
681 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
682 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
683 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
684 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
685 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
686 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
687 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
688 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
689 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
693 const char str[ETH_GSTRING_LEN];
694 } ethtool_stats_keys[] = {
696 { "tx_max_collisions" },
697 { "tx_multiple_collisions" },
698 { "tx_single_collisions" },
702 /* number of ETHTOOL_GSTATS u64's */
703 #define VORTEX_NUM_STATS 5
705 static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
706 int chip_idx, int card_idx);
707 static int vortex_up(struct net_device *dev);
708 static void vortex_down(struct net_device *dev, int final);
709 static int vortex_open(struct net_device *dev);
710 static void mdio_sync(void __iomem *ioaddr, int bits);
711 static int mdio_read(struct net_device *dev, int phy_id, int location);
712 static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
713 static void vortex_timer(unsigned long arg);
714 static void rx_oom_timer(unsigned long arg);
715 static int vortex_start_xmit(struct sk_buff *skb, struct net_device *dev);
716 static int boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev);
717 static int vortex_rx(struct net_device *dev);
718 static int boomerang_rx(struct net_device *dev);
719 static irqreturn_t vortex_interrupt(int irq, void *dev_id);
720 static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
721 static int vortex_close(struct net_device *dev);
722 static void dump_tx_ring(struct net_device *dev);
723 static void update_stats(void __iomem *ioaddr, struct net_device *dev);
724 static struct net_device_stats *vortex_get_stats(struct net_device *dev);
725 static void set_rx_mode(struct net_device *dev);
727 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
729 static void vortex_tx_timeout(struct net_device *dev);
730 static void acpi_set_WOL(struct net_device *dev);
731 static const struct ethtool_ops vortex_ethtool_ops;
732 static void set_8021q_mode(struct net_device *dev, int enable);
734 /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
735 /* Option count limit only -- unlimited interfaces are supported. */
737 static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
738 static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
739 static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
740 static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
741 static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
742 static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
743 static int global_options = -1;
744 static int global_full_duplex = -1;
745 static int global_enable_wol = -1;
746 static int global_use_mmio = -1;
748 /* Variables to work-around the Compaq PCI BIOS32 problem. */
749 static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
750 static struct net_device *compaq_net_device;
752 static int vortex_cards_found;
754 module_param(debug, int, 0);
755 module_param(global_options, int, 0);
756 module_param_array(options, int, NULL, 0);
757 module_param(global_full_duplex, int, 0);
758 module_param_array(full_duplex, int, NULL, 0);
759 module_param_array(hw_checksums, int, NULL, 0);
760 module_param_array(flow_ctrl, int, NULL, 0);
761 module_param(global_enable_wol, int, 0);
762 module_param_array(enable_wol, int, NULL, 0);
763 module_param(rx_copybreak, int, 0);
764 module_param(max_interrupt_work, int, 0);
765 module_param(compaq_ioaddr, int, 0);
766 module_param(compaq_irq, int, 0);
767 module_param(compaq_device_id, int, 0);
768 module_param(watchdog, int, 0);
769 module_param(global_use_mmio, int, 0);
770 module_param_array(use_mmio, int, NULL, 0);
771 MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
772 MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
773 MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
774 MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
775 MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
776 MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
777 MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
778 MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
779 MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
780 MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
781 MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
782 MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
783 MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
784 MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
785 MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
786 MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
787 MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
789 #ifdef CONFIG_NET_POLL_CONTROLLER
790 static void poll_vortex(struct net_device *dev)
792 struct vortex_private *vp = netdev_priv(dev);
794 local_irq_save(flags);
795 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
796 local_irq_restore(flags);
802 static int vortex_suspend(struct pci_dev *pdev, pm_message_t state)
804 struct net_device *dev = pci_get_drvdata(pdev);
806 if (dev && dev->priv) {
807 if (netif_running(dev)) {
808 netif_device_detach(dev);
811 pci_save_state(pdev);
812 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
813 free_irq(dev->irq, dev);
814 pci_disable_device(pdev);
815 pci_set_power_state(pdev, pci_choose_state(pdev, state));
820 static int vortex_resume(struct pci_dev *pdev)
822 struct net_device *dev = pci_get_drvdata(pdev);
823 struct vortex_private *vp = netdev_priv(dev);
827 pci_set_power_state(pdev, PCI_D0);
828 pci_restore_state(pdev);
829 err = pci_enable_device(pdev);
831 printk(KERN_WARNING "%s: Could not enable device \n",
835 pci_set_master(pdev);
836 if (request_irq(dev->irq, vp->full_bus_master_rx ?
837 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev)) {
838 printk(KERN_WARNING "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
839 pci_disable_device(pdev);
842 if (netif_running(dev)) {
843 err = vortex_up(dev);
847 netif_device_attach(dev);
853 #endif /* CONFIG_PM */
856 static struct eisa_device_id vortex_eisa_ids[] = {
857 { "TCM5920", CH_3C592 },
858 { "TCM5970", CH_3C597 },
861 MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
863 static int __init vortex_eisa_probe(struct device *device)
865 void __iomem *ioaddr;
866 struct eisa_device *edev;
868 edev = to_eisa_device(device);
870 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
873 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
875 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
876 edev->id.driver_data, vortex_cards_found)) {
877 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
881 vortex_cards_found++;
886 static int __devexit vortex_eisa_remove(struct device *device)
888 struct eisa_device *edev;
889 struct net_device *dev;
890 struct vortex_private *vp;
891 void __iomem *ioaddr;
893 edev = to_eisa_device(device);
894 dev = eisa_get_drvdata(edev);
897 printk("vortex_eisa_remove called for Compaq device!\n");
901 vp = netdev_priv(dev);
904 unregister_netdev(dev);
905 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
906 release_region(dev->base_addr, VORTEX_TOTAL_SIZE);
912 static struct eisa_driver vortex_eisa_driver = {
913 .id_table = vortex_eisa_ids,
916 .probe = vortex_eisa_probe,
917 .remove = __devexit_p(vortex_eisa_remove)
921 #endif /* CONFIG_EISA */
923 /* returns count found (>= 0), or negative on error */
924 static int __init vortex_eisa_init(void)
927 int orig_cards_found = vortex_cards_found;
932 err = eisa_driver_register (&vortex_eisa_driver);
935 * Because of the way EISA bus is probed, we cannot assume
936 * any device have been found when we exit from
937 * eisa_driver_register (the bus root driver may not be
938 * initialized yet). So we blindly assume something was
939 * found, and let the sysfs magic happend...
945 /* Special code to work-around the Compaq PCI BIOS32 problem. */
947 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
948 compaq_irq, compaq_device_id, vortex_cards_found++);
951 return vortex_cards_found - orig_cards_found + eisa_found;
954 /* returns count (>= 0), or negative on error */
955 static int __devinit vortex_init_one(struct pci_dev *pdev,
956 const struct pci_device_id *ent)
958 int rc, unit, pci_bar;
959 struct vortex_chip_info *vci;
960 void __iomem *ioaddr;
962 /* wake up and enable device */
963 rc = pci_enable_device(pdev);
967 unit = vortex_cards_found;
969 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
970 /* Determine the default if the user didn't override us */
971 vci = &vortex_info_tbl[ent->driver_data];
972 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
973 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
974 pci_bar = use_mmio[unit] ? 1 : 0;
976 pci_bar = global_use_mmio ? 1 : 0;
978 ioaddr = pci_iomap(pdev, pci_bar, 0);
979 if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
980 ioaddr = pci_iomap(pdev, 0, 0);
982 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
983 ent->driver_data, unit);
985 pci_disable_device(pdev);
989 vortex_cards_found++;
996 * Start up the PCI/EISA device which is described by *gendev.
997 * Return 0 on success.
999 * NOTE: pdev can be NULL, for the case of a Compaq device
1001 static int __devinit vortex_probe1(struct device *gendev,
1002 void __iomem *ioaddr, int irq,
1003 int chip_idx, int card_idx)
1005 struct vortex_private *vp;
1007 unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
1009 struct net_device *dev;
1010 static int printed_version;
1011 int retval, print_info;
1012 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1013 const char *print_name = "3c59x";
1014 struct pci_dev *pdev = NULL;
1015 struct eisa_device *edev = NULL;
1016 DECLARE_MAC_BUF(mac);
1018 if (!printed_version) {
1020 printed_version = 1;
1024 if ((pdev = DEVICE_PCI(gendev))) {
1025 print_name = pci_name(pdev);
1028 if ((edev = DEVICE_EISA(gendev))) {
1029 print_name = edev->dev.bus_id;
1033 dev = alloc_etherdev(sizeof(*vp));
1036 printk (KERN_ERR PFX "unable to allocate etherdev, aborting\n");
1039 SET_NETDEV_DEV(dev, gendev);
1040 vp = netdev_priv(dev);
1042 option = global_options;
1044 /* The lower four bits are the media type. */
1045 if (dev->mem_start) {
1047 * The 'options' param is passed in as the third arg to the
1048 * LILO 'ether=' argument for non-modular use
1050 option = dev->mem_start;
1052 else if (card_idx < MAX_UNITS) {
1053 if (options[card_idx] >= 0)
1054 option = options[card_idx];
1058 if (option & 0x8000)
1060 if (option & 0x4000)
1062 if (option & 0x0400)
1066 print_info = (vortex_debug > 1);
1068 printk (KERN_INFO "See Documentation/networking/vortex.txt\n");
1070 printk(KERN_INFO "%s: 3Com %s %s at %p.\n",
1072 pdev ? "PCI" : "EISA",
1076 dev->base_addr = (unsigned long)ioaddr;
1079 vp->ioaddr = ioaddr;
1080 vp->large_frames = mtu > 1500;
1081 vp->drv_flags = vci->drv_flags;
1082 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1083 vp->io_size = vci->io_size;
1084 vp->card_idx = card_idx;
1086 /* module list only for Compaq device */
1087 if (gendev == NULL) {
1088 compaq_net_device = dev;
1091 /* PCI-only startup logic */
1093 /* EISA resources already marked, so only PCI needs to do this here */
1094 /* Ignore return value, because Cardbus drivers already allocate for us */
1095 if (request_region(dev->base_addr, vci->io_size, print_name) != NULL)
1096 vp->must_free_region = 1;
1098 /* enable bus-mastering if necessary */
1099 if (vci->flags & PCI_USES_MASTER)
1100 pci_set_master(pdev);
1102 if (vci->drv_flags & IS_VORTEX) {
1104 u8 new_latency = 248;
1106 /* Check the PCI latency value. On the 3c590 series the latency timer
1107 must be set to the maximum value to avoid data corruption that occurs
1108 when the timer expires during a transfer. This bug exists the Vortex
1110 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1111 if (pci_latency < new_latency) {
1112 printk(KERN_INFO "%s: Overriding PCI latency"
1113 " timer (CFLT) setting of %d, new value is %d.\n",
1114 print_name, pci_latency, new_latency);
1115 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1120 spin_lock_init(&vp->lock);
1121 vp->gendev = gendev;
1123 vp->mii.mdio_read = mdio_read;
1124 vp->mii.mdio_write = mdio_write;
1125 vp->mii.phy_id_mask = 0x1f;
1126 vp->mii.reg_num_mask = 0x1f;
1128 /* Makes sure rings are at least 16 byte aligned. */
1129 vp->rx_ring = pci_alloc_consistent(pdev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1130 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1136 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1137 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1139 /* if we are a PCI driver, we store info in pdev->driver_data
1140 * instead of a module list */
1142 pci_set_drvdata(pdev, dev);
1144 eisa_set_drvdata(edev, dev);
1146 vp->media_override = 7;
1148 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1149 if (vp->media_override != 7)
1151 vp->full_duplex = (option & 0x200) ? 1 : 0;
1152 vp->bus_master = (option & 16) ? 1 : 0;
1155 if (global_full_duplex > 0)
1156 vp->full_duplex = 1;
1157 if (global_enable_wol > 0)
1160 if (card_idx < MAX_UNITS) {
1161 if (full_duplex[card_idx] > 0)
1162 vp->full_duplex = 1;
1163 if (flow_ctrl[card_idx] > 0)
1165 if (enable_wol[card_idx] > 0)
1169 vp->mii.force_media = vp->full_duplex;
1170 vp->options = option;
1171 /* Read the station address from the EEPROM. */
1176 if (vci->drv_flags & EEPROM_8BIT)
1178 else if (vci->drv_flags & EEPROM_OFFSET)
1179 base = EEPROM_Read + 0x30;
1183 for (i = 0; i < 0x40; i++) {
1185 iowrite16(base + i, ioaddr + Wn0EepromCmd);
1186 /* Pause for at least 162 us. for the read to take place. */
1187 for (timer = 10; timer >= 0; timer--) {
1189 if ((ioread16(ioaddr + Wn0EepromCmd) & 0x8000) == 0)
1192 eeprom[i] = ioread16(ioaddr + Wn0EepromData);
1195 for (i = 0; i < 0x18; i++)
1196 checksum ^= eeprom[i];
1197 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1198 if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
1200 checksum ^= eeprom[i++];
1201 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1203 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1204 printk(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1205 for (i = 0; i < 3; i++)
1206 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1207 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1209 printk(" %s", print_mac(mac, dev->dev_addr));
1210 /* Unfortunately an all zero eeprom passes the checksum and this
1211 gets found in the wild in failure cases. Crypto is hard 8) */
1212 if (!is_valid_ether_addr(dev->dev_addr)) {
1214 printk(KERN_ERR "*** EEPROM MAC address is invalid.\n");
1215 goto free_ring; /* With every pack */
1218 for (i = 0; i < 6; i++)
1219 iowrite8(dev->dev_addr[i], ioaddr + i);
1222 printk(", IRQ %d\n", dev->irq);
1223 /* Tell them about an invalid IRQ. */
1224 if (dev->irq <= 0 || dev->irq >= NR_IRQS)
1225 printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n",
1229 step = (ioread8(ioaddr + Wn4_NetDiag) & 0x1e) >> 1;
1231 printk(KERN_INFO " product code %02x%02x rev %02x.%d date %02d-"
1232 "%02d-%02d\n", eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1233 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1237 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1240 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1241 if (!vp->cb_fn_base) {
1247 printk(KERN_INFO "%s: CardBus functions mapped "
1250 (unsigned long long)pci_resource_start(pdev, 2),
1255 n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1256 if (vp->drv_flags & INVERT_LED_PWR)
1258 if (vp->drv_flags & INVERT_MII_PWR)
1260 iowrite16(n, ioaddr + Wn2_ResetOptions);
1261 if (vp->drv_flags & WNO_XCVR_PWR) {
1263 iowrite16(0x0800, ioaddr);
1267 /* Extract our information from the EEPROM data. */
1268 vp->info1 = eeprom[13];
1269 vp->info2 = eeprom[15];
1270 vp->capabilities = eeprom[16];
1272 if (vp->info1 & 0x8000) {
1273 vp->full_duplex = 1;
1275 printk(KERN_INFO "Full duplex capable\n");
1279 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1280 unsigned int config;
1282 vp->available_media = ioread16(ioaddr + Wn3_Options);
1283 if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
1284 vp->available_media = 0x40;
1285 config = ioread32(ioaddr + Wn3_Config);
1287 printk(KERN_DEBUG " Internal config register is %4.4x, "
1288 "transceivers %#x.\n", config, ioread16(ioaddr + Wn3_Options));
1289 printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1290 8 << RAM_SIZE(config),
1291 RAM_WIDTH(config) ? "word" : "byte",
1292 ram_split[RAM_SPLIT(config)],
1293 AUTOSELECT(config) ? "autoselect/" : "",
1294 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1295 media_tbl[XCVR(config)].name);
1297 vp->default_media = XCVR(config);
1298 if (vp->default_media == XCVR_NWAY)
1300 vp->autoselect = AUTOSELECT(config);
1303 if (vp->media_override != 7) {
1304 printk(KERN_INFO "%s: Media override to transceiver type %d (%s).\n",
1305 print_name, vp->media_override,
1306 media_tbl[vp->media_override].name);
1307 dev->if_port = vp->media_override;
1309 dev->if_port = vp->default_media;
1311 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1312 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1313 int phy, phy_idx = 0;
1315 mii_preamble_required++;
1316 if (vp->drv_flags & EXTRA_PREAMBLE)
1317 mii_preamble_required++;
1318 mdio_sync(ioaddr, 32);
1319 mdio_read(dev, 24, MII_BMSR);
1320 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1321 int mii_status, phyx;
1324 * For the 3c905CX we look at index 24 first, because it bogusly
1325 * reports an external PHY at all indices
1333 mii_status = mdio_read(dev, phyx, MII_BMSR);
1334 if (mii_status && mii_status != 0xffff) {
1335 vp->phys[phy_idx++] = phyx;
1337 printk(KERN_INFO " MII transceiver found at address %d,"
1338 " status %4x.\n", phyx, mii_status);
1340 if ((mii_status & 0x0040) == 0)
1341 mii_preamble_required++;
1344 mii_preamble_required--;
1346 printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n");
1349 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1350 if (vp->full_duplex) {
1351 /* Only advertise the FD media types. */
1352 vp->advertising &= ~0x02A0;
1353 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1356 vp->mii.phy_id = vp->phys[0];
1359 if (vp->capabilities & CapBusMaster) {
1360 vp->full_bus_master_tx = 1;
1362 printk(KERN_INFO " Enabling bus-master transmits and %s receives.\n",
1363 (vp->info2 & 1) ? "early" : "whole-frame" );
1365 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1366 vp->bus_master = 0; /* AKPM: vortex only */
1369 /* The 3c59x-specific entries in the device structure. */
1370 dev->open = vortex_open;
1371 if (vp->full_bus_master_tx) {
1372 dev->hard_start_xmit = boomerang_start_xmit;
1373 /* Actually, it still should work with iommu. */
1374 if (card_idx < MAX_UNITS &&
1375 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1376 hw_checksums[card_idx] == 1)) {
1377 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1380 dev->hard_start_xmit = vortex_start_xmit;
1384 printk(KERN_INFO "%s: scatter/gather %sabled. h/w checksums %sabled\n",
1386 (dev->features & NETIF_F_SG) ? "en":"dis",
1387 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1390 dev->stop = vortex_close;
1391 dev->get_stats = vortex_get_stats;
1393 dev->do_ioctl = vortex_ioctl;
1395 dev->ethtool_ops = &vortex_ethtool_ops;
1396 dev->set_multicast_list = set_rx_mode;
1397 dev->tx_timeout = vortex_tx_timeout;
1398 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1399 #ifdef CONFIG_NET_POLL_CONTROLLER
1400 dev->poll_controller = poll_vortex;
1403 vp->pm_state_valid = 1;
1404 pci_save_state(VORTEX_PCI(vp));
1407 retval = register_netdev(dev);
1412 pci_free_consistent(pdev,
1413 sizeof(struct boom_rx_desc) * RX_RING_SIZE
1414 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1418 if (vp->must_free_region)
1419 release_region(dev->base_addr, vci->io_size);
1421 printk(KERN_ERR PFX "vortex_probe1 fails. Returns %d\n", retval);
1427 issue_and_wait(struct net_device *dev, int cmd)
1429 struct vortex_private *vp = netdev_priv(dev);
1430 void __iomem *ioaddr = vp->ioaddr;
1433 iowrite16(cmd, ioaddr + EL3_CMD);
1434 for (i = 0; i < 2000; i++) {
1435 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1439 /* OK, that didn't work. Do it the slow way. One second */
1440 for (i = 0; i < 100000; i++) {
1441 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1442 if (vortex_debug > 1)
1443 printk(KERN_INFO "%s: command 0x%04x took %d usecs\n",
1444 dev->name, cmd, i * 10);
1449 printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n",
1450 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1454 vortex_set_duplex(struct net_device *dev)
1456 struct vortex_private *vp = netdev_priv(dev);
1457 void __iomem *ioaddr = vp->ioaddr;
1459 printk(KERN_INFO "%s: setting %s-duplex.\n",
1460 dev->name, (vp->full_duplex) ? "full" : "half");
1463 /* Set the full-duplex bit. */
1464 iowrite16(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1465 (vp->large_frames ? 0x40 : 0) |
1466 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1468 ioaddr + Wn3_MAC_Ctrl);
1471 static void vortex_check_media(struct net_device *dev, unsigned int init)
1473 struct vortex_private *vp = netdev_priv(dev);
1474 unsigned int ok_to_print = 0;
1476 if (vortex_debug > 3)
1479 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1480 vp->full_duplex = vp->mii.full_duplex;
1481 vortex_set_duplex(dev);
1483 vortex_set_duplex(dev);
1488 vortex_up(struct net_device *dev)
1490 struct vortex_private *vp = netdev_priv(dev);
1491 void __iomem *ioaddr = vp->ioaddr;
1492 unsigned int config;
1493 int i, mii_reg1, mii_reg5, err = 0;
1495 if (VORTEX_PCI(vp)) {
1496 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
1497 if (vp->pm_state_valid)
1498 pci_restore_state(VORTEX_PCI(vp));
1499 err = pci_enable_device(VORTEX_PCI(vp));
1501 printk(KERN_WARNING "%s: Could not enable device \n",
1507 /* Before initializing select the active media port. */
1509 config = ioread32(ioaddr + Wn3_Config);
1511 if (vp->media_override != 7) {
1512 printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n",
1513 dev->name, vp->media_override,
1514 media_tbl[vp->media_override].name);
1515 dev->if_port = vp->media_override;
1516 } else if (vp->autoselect) {
1518 if (vortex_debug > 1)
1519 printk(KERN_INFO "%s: using NWAY device table, not %d\n",
1520 dev->name, dev->if_port);
1521 dev->if_port = XCVR_NWAY;
1523 /* Find first available media type, starting with 100baseTx. */
1524 dev->if_port = XCVR_100baseTx;
1525 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1526 dev->if_port = media_tbl[dev->if_port].next;
1527 if (vortex_debug > 1)
1528 printk(KERN_INFO "%s: first available media type: %s\n",
1529 dev->name, media_tbl[dev->if_port].name);
1532 dev->if_port = vp->default_media;
1533 if (vortex_debug > 1)
1534 printk(KERN_INFO "%s: using default media %s\n",
1535 dev->name, media_tbl[dev->if_port].name);
1538 init_timer(&vp->timer);
1539 vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait);
1540 vp->timer.data = (unsigned long)dev;
1541 vp->timer.function = vortex_timer; /* timer handler */
1542 add_timer(&vp->timer);
1544 init_timer(&vp->rx_oom_timer);
1545 vp->rx_oom_timer.data = (unsigned long)dev;
1546 vp->rx_oom_timer.function = rx_oom_timer;
1548 if (vortex_debug > 1)
1549 printk(KERN_DEBUG "%s: Initial media type %s.\n",
1550 dev->name, media_tbl[dev->if_port].name);
1552 vp->full_duplex = vp->mii.force_media;
1553 config = BFINS(config, dev->if_port, 20, 4);
1554 if (vortex_debug > 6)
1555 printk(KERN_DEBUG "vortex_up(): writing 0x%x to InternalConfig\n", config);
1556 iowrite32(config, ioaddr + Wn3_Config);
1558 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1560 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1561 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1562 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1563 vp->mii.full_duplex = vp->full_duplex;
1565 vortex_check_media(dev, 1);
1568 vortex_set_duplex(dev);
1570 issue_and_wait(dev, TxReset);
1572 * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
1574 issue_and_wait(dev, RxReset|0x04);
1577 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1579 if (vortex_debug > 1) {
1581 printk(KERN_DEBUG "%s: vortex_up() irq %d media status %4.4x.\n",
1582 dev->name, dev->irq, ioread16(ioaddr + Wn4_Media));
1585 /* Set the station address and mask in window 2 each time opened. */
1587 for (i = 0; i < 6; i++)
1588 iowrite8(dev->dev_addr[i], ioaddr + i);
1589 for (; i < 12; i+=2)
1590 iowrite16(0, ioaddr + i);
1592 if (vp->cb_fn_base) {
1593 unsigned short n = ioread16(ioaddr + Wn2_ResetOptions) & ~0x4010;
1594 if (vp->drv_flags & INVERT_LED_PWR)
1596 if (vp->drv_flags & INVERT_MII_PWR)
1598 iowrite16(n, ioaddr + Wn2_ResetOptions);
1601 if (dev->if_port == XCVR_10base2)
1602 /* Start the thinnet transceiver. We should really wait 50ms...*/
1603 iowrite16(StartCoax, ioaddr + EL3_CMD);
1604 if (dev->if_port != XCVR_NWAY) {
1606 iowrite16((ioread16(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) |
1607 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1610 /* Switch to the stats window, and clear all stats by reading. */
1611 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1613 for (i = 0; i < 10; i++)
1614 ioread8(ioaddr + i);
1615 ioread16(ioaddr + 10);
1616 ioread16(ioaddr + 12);
1617 /* New: On the Vortex we must also clear the BadSSD counter. */
1619 ioread8(ioaddr + 12);
1620 /* ..and on the Boomerang we enable the extra statistics bits. */
1621 iowrite16(0x0040, ioaddr + Wn4_NetDiag);
1623 /* Switch to register set 7 for normal use. */
1626 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1627 vp->cur_rx = vp->dirty_rx = 0;
1628 /* Initialize the RxEarly register as recommended. */
1629 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1630 iowrite32(0x0020, ioaddr + PktStatus);
1631 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1633 if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
1634 vp->cur_tx = vp->dirty_tx = 0;
1635 if (vp->drv_flags & IS_BOOMERANG)
1636 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
1637 /* Clear the Rx, Tx rings. */
1638 for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
1639 vp->rx_ring[i].status = 0;
1640 for (i = 0; i < TX_RING_SIZE; i++)
1641 vp->tx_skbuff[i] = NULL;
1642 iowrite32(0, ioaddr + DownListPtr);
1644 /* Set receiver mode: presumably accept b-case and phys addr only. */
1646 /* enable 802.1q tagged frames */
1647 set_8021q_mode(dev, 1);
1648 iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
1650 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
1651 iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
1652 /* Allow status bits to be seen. */
1653 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1654 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1655 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1656 (vp->bus_master ? DMADone : 0);
1657 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1658 (vp->full_bus_master_rx ? 0 : RxComplete) |
1659 StatsFull | HostError | TxComplete | IntReq
1660 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1661 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1662 /* Ack all pending events, and set active indicator mask. */
1663 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1665 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1666 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
1667 iowrite32(0x8000, vp->cb_fn_base + 4);
1668 netif_start_queue (dev);
1674 vortex_open(struct net_device *dev)
1676 struct vortex_private *vp = netdev_priv(dev);
1680 /* Use the now-standard shared IRQ implementation. */
1681 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1682 &boomerang_interrupt : &vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1683 printk(KERN_ERR "%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1687 if (vp->full_bus_master_rx) { /* Boomerang bus master. */
1688 if (vortex_debug > 2)
1689 printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name);
1690 for (i = 0; i < RX_RING_SIZE; i++) {
1691 struct sk_buff *skb;
1692 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1693 vp->rx_ring[i].status = 0; /* Clear complete bit. */
1694 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1696 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1698 vp->rx_skbuff[i] = skb;
1700 break; /* Bad news! */
1702 skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
1703 vp->rx_ring[i].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
1705 if (i != RX_RING_SIZE) {
1707 printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name);
1708 for (j = 0; j < i; j++) {
1709 if (vp->rx_skbuff[j]) {
1710 dev_kfree_skb(vp->rx_skbuff[j]);
1711 vp->rx_skbuff[j] = NULL;
1717 /* Wrap the ring. */
1718 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1721 retval = vortex_up(dev);
1726 free_irq(dev->irq, dev);
1728 if (vortex_debug > 1)
1729 printk(KERN_ERR "%s: vortex_open() fails: returning %d\n", dev->name, retval);
1735 vortex_timer(unsigned long data)
1737 struct net_device *dev = (struct net_device *)data;
1738 struct vortex_private *vp = netdev_priv(dev);
1739 void __iomem *ioaddr = vp->ioaddr;
1740 int next_tick = 60*HZ;
1742 int media_status, old_window;
1744 if (vortex_debug > 2) {
1745 printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n",
1746 dev->name, media_tbl[dev->if_port].name);
1747 printk(KERN_DEBUG "dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1750 disable_irq_lockdep(dev->irq);
1751 old_window = ioread16(ioaddr + EL3_CMD) >> 13;
1753 media_status = ioread16(ioaddr + Wn4_Media);
1754 switch (dev->if_port) {
1755 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1756 if (media_status & Media_LnkBeat) {
1757 netif_carrier_on(dev);
1759 if (vortex_debug > 1)
1760 printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n",
1761 dev->name, media_tbl[dev->if_port].name, media_status);
1763 netif_carrier_off(dev);
1764 if (vortex_debug > 1) {
1765 printk(KERN_DEBUG "%s: Media %s has no link beat, %x.\n",
1766 dev->name, media_tbl[dev->if_port].name, media_status);
1770 case XCVR_MII: case XCVR_NWAY:
1773 /* Interrupts are already disabled */
1774 spin_lock(&vp->lock);
1775 vortex_check_media(dev, 0);
1776 spin_unlock(&vp->lock);
1779 default: /* Other media types handled by Tx timeouts. */
1780 if (vortex_debug > 1)
1781 printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n",
1782 dev->name, media_tbl[dev->if_port].name, media_status);
1786 if (!netif_carrier_ok(dev))
1790 goto leave_media_alone;
1793 unsigned int config;
1796 dev->if_port = media_tbl[dev->if_port].next;
1797 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1798 if (dev->if_port == XCVR_Default) { /* Go back to default. */
1799 dev->if_port = vp->default_media;
1800 if (vortex_debug > 1)
1801 printk(KERN_DEBUG "%s: Media selection failing, using default "
1803 dev->name, media_tbl[dev->if_port].name);
1805 if (vortex_debug > 1)
1806 printk(KERN_DEBUG "%s: Media selection failed, now trying "
1808 dev->name, media_tbl[dev->if_port].name);
1809 next_tick = media_tbl[dev->if_port].wait;
1811 iowrite16((media_status & ~(Media_10TP|Media_SQE)) |
1812 media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
1815 config = ioread32(ioaddr + Wn3_Config);
1816 config = BFINS(config, dev->if_port, 20, 4);
1817 iowrite32(config, ioaddr + Wn3_Config);
1819 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1821 if (vortex_debug > 1)
1822 printk(KERN_DEBUG "wrote 0x%08x to Wn3_Config\n", config);
1823 /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
1827 if (vortex_debug > 2)
1828 printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n",
1829 dev->name, media_tbl[dev->if_port].name);
1831 EL3WINDOW(old_window);
1832 enable_irq_lockdep(dev->irq);
1833 mod_timer(&vp->timer, RUN_AT(next_tick));
1835 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1839 static void vortex_tx_timeout(struct net_device *dev)
1841 struct vortex_private *vp = netdev_priv(dev);
1842 void __iomem *ioaddr = vp->ioaddr;
1844 printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1845 dev->name, ioread8(ioaddr + TxStatus),
1846 ioread16(ioaddr + EL3_STATUS));
1848 printk(KERN_ERR " diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1849 ioread16(ioaddr + Wn4_NetDiag),
1850 ioread16(ioaddr + Wn4_Media),
1851 ioread32(ioaddr + PktStatus),
1852 ioread16(ioaddr + Wn4_FIFODiag));
1853 /* Slight code bloat to be user friendly. */
1854 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1855 printk(KERN_ERR "%s: Transmitter encountered 16 collisions --"
1856 " network cable problem?\n", dev->name);
1857 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1858 printk(KERN_ERR "%s: Interrupt posted but not delivered --"
1859 " IRQ blocked by another device?\n", dev->name);
1860 /* Bad idea here.. but we might as well handle a few events. */
1863 * Block interrupts because vortex_interrupt does a bare spin_lock()
1865 unsigned long flags;
1866 local_irq_save(flags);
1867 if (vp->full_bus_master_tx)
1868 boomerang_interrupt(dev->irq, dev);
1870 vortex_interrupt(dev->irq, dev);
1871 local_irq_restore(flags);
1875 if (vortex_debug > 0)
1878 issue_and_wait(dev, TxReset);
1880 dev->stats.tx_errors++;
1881 if (vp->full_bus_master_tx) {
1882 printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", dev->name);
1883 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1884 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1885 ioaddr + DownListPtr);
1886 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE)
1887 netif_wake_queue (dev);
1888 if (vp->drv_flags & IS_BOOMERANG)
1889 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1890 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1892 dev->stats.tx_dropped++;
1893 netif_wake_queue(dev);
1896 /* Issue Tx Enable */
1897 iowrite16(TxEnable, ioaddr + EL3_CMD);
1898 dev->trans_start = jiffies;
1900 /* Switch to register set 7 for normal use. */
1905 * Handle uncommon interrupt sources. This is a separate routine to minimize
1909 vortex_error(struct net_device *dev, int status)
1911 struct vortex_private *vp = netdev_priv(dev);
1912 void __iomem *ioaddr = vp->ioaddr;
1913 int do_tx_reset = 0, reset_mask = 0;
1914 unsigned char tx_status = 0;
1916 if (vortex_debug > 2) {
1917 printk(KERN_ERR "%s: vortex_error(), status=0x%x\n", dev->name, status);
1920 if (status & TxComplete) { /* Really "TxError" for us. */
1921 tx_status = ioread8(ioaddr + TxStatus);
1922 /* Presumably a tx-timeout. We must merely re-enable. */
1923 if (vortex_debug > 2
1924 || (tx_status != 0x88 && vortex_debug > 0)) {
1925 printk(KERN_ERR "%s: Transmit error, Tx status register %2.2x.\n",
1926 dev->name, tx_status);
1927 if (tx_status == 0x82) {
1928 printk(KERN_ERR "Probably a duplex mismatch. See "
1929 "Documentation/networking/vortex.txt\n");
1933 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1934 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1935 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1936 iowrite8(0, ioaddr + TxStatus);
1937 if (tx_status & 0x30) { /* txJabber or txUnderrun */
1939 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
1941 reset_mask = 0x0108; /* Reset interface logic, but not download logic */
1942 } else { /* Merely re-enable the transmitter. */
1943 iowrite16(TxEnable, ioaddr + EL3_CMD);
1947 if (status & RxEarly) { /* Rx early is unused. */
1949 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1951 if (status & StatsFull) { /* Empty statistics. */
1952 static int DoneDidThat;
1953 if (vortex_debug > 4)
1954 printk(KERN_DEBUG "%s: Updating stats.\n", dev->name);
1955 update_stats(ioaddr, dev);
1956 /* HACK: Disable statistics as an interrupt source. */
1957 /* This occurs when we have the wrong media type! */
1958 if (DoneDidThat == 0 &&
1959 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
1960 printk(KERN_WARNING "%s: Updating statistics failed, disabling "
1961 "stats as an interrupt source.\n", dev->name);
1963 iowrite16(SetIntrEnb | (ioread16(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
1964 vp->intr_enable &= ~StatsFull;
1969 if (status & IntReq) { /* Restore all interrupt sources. */
1970 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1971 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1973 if (status & HostError) {
1976 fifo_diag = ioread16(ioaddr + Wn4_FIFODiag);
1977 printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n",
1978 dev->name, fifo_diag);
1979 /* Adapter failure requires Tx/Rx reset and reinit. */
1980 if (vp->full_bus_master_tx) {
1981 int bus_status = ioread32(ioaddr + PktStatus);
1982 /* 0x80000000 PCI master abort. */
1983 /* 0x40000000 PCI target abort. */
1985 printk(KERN_ERR "%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
1987 /* In this case, blow the card away */
1988 /* Must not enter D3 or we can't legally issue the reset! */
1989 vortex_down(dev, 0);
1990 issue_and_wait(dev, TotalReset | 0xff);
1991 vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
1992 } else if (fifo_diag & 0x0400)
1994 if (fifo_diag & 0x3000) {
1995 /* Reset Rx fifo and upload logic */
1996 issue_and_wait(dev, RxReset|0x07);
1997 /* Set the Rx filter to the current state. */
1999 /* enable 802.1q VLAN tagged frames */
2000 set_8021q_mode(dev, 1);
2001 iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
2002 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2007 issue_and_wait(dev, TxReset|reset_mask);
2008 iowrite16(TxEnable, ioaddr + EL3_CMD);
2009 if (!vp->full_bus_master_tx)
2010 netif_wake_queue(dev);
2015 vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2017 struct vortex_private *vp = netdev_priv(dev);
2018 void __iomem *ioaddr = vp->ioaddr;
2020 /* Put out the doubleword header... */
2021 iowrite32(skb->len, ioaddr + TX_FIFO);
2022 if (vp->bus_master) {
2023 /* Set the bus-master controller to transfer the packet. */
2024 int len = (skb->len + 3) & ~3;
2025 iowrite32(vp->tx_skb_dma = pci_map_single(VORTEX_PCI(vp), skb->data, len, PCI_DMA_TODEVICE),
2026 ioaddr + Wn7_MasterAddr);
2027 iowrite16(len, ioaddr + Wn7_MasterLen);
2029 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2030 /* netif_wake_queue() will be called at the DMADone interrupt. */
2032 /* ... and the packet rounded to a doubleword. */
2033 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2034 dev_kfree_skb (skb);
2035 if (ioread16(ioaddr + TxFree) > 1536) {
2036 netif_start_queue (dev); /* AKPM: redundant? */
2038 /* Interrupt us when the FIFO has room for max-sized packet. */
2039 netif_stop_queue(dev);
2040 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2044 dev->trans_start = jiffies;
2046 /* Clear the Tx status stack. */
2051 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2052 if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
2053 if (vortex_debug > 2)
2054 printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n",
2055 dev->name, tx_status);
2056 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2057 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2058 if (tx_status & 0x30) {
2059 issue_and_wait(dev, TxReset);
2061 iowrite16(TxEnable, ioaddr + EL3_CMD);
2063 iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
2070 boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2072 struct vortex_private *vp = netdev_priv(dev);
2073 void __iomem *ioaddr = vp->ioaddr;
2074 /* Calculate the next Tx descriptor entry. */
2075 int entry = vp->cur_tx % TX_RING_SIZE;
2076 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2077 unsigned long flags;
2079 if (vortex_debug > 6) {
2080 printk(KERN_DEBUG "boomerang_start_xmit()\n");
2081 printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n",
2082 dev->name, vp->cur_tx);
2085 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2086 if (vortex_debug > 0)
2087 printk(KERN_WARNING "%s: BUG! Tx Ring full, refusing to send buffer.\n",
2089 netif_stop_queue(dev);
2093 vp->tx_skbuff[entry] = skb;
2095 vp->tx_ring[entry].next = 0;
2097 if (skb->ip_summed != CHECKSUM_PARTIAL)
2098 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2100 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2102 if (!skb_shinfo(skb)->nr_frags) {
2103 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2104 skb->len, PCI_DMA_TODEVICE));
2105 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2109 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data,
2110 skb->len-skb->data_len, PCI_DMA_TODEVICE));
2111 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len-skb->data_len);
2113 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2114 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2116 vp->tx_ring[entry].frag[i+1].addr =
2117 cpu_to_le32(pci_map_single(VORTEX_PCI(vp),
2118 (void*)page_address(frag->page) + frag->page_offset,
2119 frag->size, PCI_DMA_TODEVICE));
2121 if (i == skb_shinfo(skb)->nr_frags-1)
2122 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size|LAST_FRAG);
2124 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(frag->size);
2128 vp->tx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, skb->len, PCI_DMA_TODEVICE));
2129 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2130 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2133 spin_lock_irqsave(&vp->lock, flags);
2134 /* Wait for the stall to complete. */
2135 issue_and_wait(dev, DownStall);
2136 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2137 if (ioread32(ioaddr + DownListPtr) == 0) {
2138 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2139 vp->queued_packet++;
2143 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2144 netif_stop_queue (dev);
2145 } else { /* Clear previous interrupt enable. */
2146 #if defined(tx_interrupt_mitigation)
2147 /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
2148 * were selected, this would corrupt DN_COMPLETE. No?
2150 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2153 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2154 spin_unlock_irqrestore(&vp->lock, flags);
2155 dev->trans_start = jiffies;
2159 /* The interrupt handler does all of the Rx thread work and cleans up
2160 after the Tx thread. */
2163 * This is the ISR for the vortex series chips.
2164 * full_bus_master_tx == 0 && full_bus_master_rx == 0
2168 vortex_interrupt(int irq, void *dev_id)
2170 struct net_device *dev = dev_id;
2171 struct vortex_private *vp = netdev_priv(dev);
2172 void __iomem *ioaddr;
2174 int work_done = max_interrupt_work;
2177 ioaddr = vp->ioaddr;
2178 spin_lock(&vp->lock);
2180 status = ioread16(ioaddr + EL3_STATUS);
2182 if (vortex_debug > 6)
2183 printk("vortex_interrupt(). status=0x%4x\n", status);
2185 if ((status & IntLatch) == 0)
2186 goto handler_exit; /* No interrupt: shared IRQs cause this */
2189 if (status & IntReq) {
2190 status |= vp->deferred;
2194 if (status == 0xffff) /* h/w no longer present (hotplug)? */
2197 if (vortex_debug > 4)
2198 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2199 dev->name, status, ioread8(ioaddr + Timer));
2202 if (vortex_debug > 5)
2203 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2205 if (status & RxComplete)
2208 if (status & TxAvailable) {
2209 if (vortex_debug > 5)
2210 printk(KERN_DEBUG " TX room bit was handled.\n");
2211 /* There's room in the FIFO for a full-sized packet. */
2212 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2213 netif_wake_queue (dev);
2216 if (status & DMADone) {
2217 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2218 iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
2219 pci_unmap_single(VORTEX_PCI(vp), vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, PCI_DMA_TODEVICE);
2220 dev_kfree_skb_irq(vp->tx_skb); /* Release the transferred buffer */
2221 if (ioread16(ioaddr + TxFree) > 1536) {
2223 * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
2224 * insufficient FIFO room, the TxAvailable test will succeed and call
2225 * netif_wake_queue()
2227 netif_wake_queue(dev);
2228 } else { /* Interrupt when FIFO has room for max-sized packet. */
2229 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2230 netif_stop_queue(dev);
2234 /* Check for all uncommon interrupts at once. */
2235 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2236 if (status == 0xffff)
2238 vortex_error(dev, status);
2241 if (--work_done < 0) {
2242 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2243 "%4.4x.\n", dev->name, status);
2244 /* Disable all pending interrupts. */
2246 vp->deferred |= status;
2247 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2249 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2250 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2251 /* The timer will reenable interrupts. */
2252 mod_timer(&vp->timer, jiffies + 1*HZ);
2255 /* Acknowledge the IRQ. */
2256 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2257 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2259 if (vortex_debug > 4)
2260 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2263 spin_unlock(&vp->lock);
2264 return IRQ_RETVAL(handled);
2268 * This is the ISR for the boomerang series chips.
2269 * full_bus_master_tx == 1 && full_bus_master_rx == 1
2273 boomerang_interrupt(int irq, void *dev_id)
2275 struct net_device *dev = dev_id;
2276 struct vortex_private *vp = netdev_priv(dev);
2277 void __iomem *ioaddr;
2279 int work_done = max_interrupt_work;
2281 ioaddr = vp->ioaddr;
2284 * It seems dopey to put the spinlock this early, but we could race against vortex_tx_timeout
2285 * and boomerang_start_xmit
2287 spin_lock(&vp->lock);
2289 status = ioread16(ioaddr + EL3_STATUS);
2291 if (vortex_debug > 6)
2292 printk(KERN_DEBUG "boomerang_interrupt. status=0x%4x\n", status);
2294 if ((status & IntLatch) == 0)
2295 goto handler_exit; /* No interrupt: shared IRQs can cause this */
2297 if (status == 0xffff) { /* h/w no longer present (hotplug)? */
2298 if (vortex_debug > 1)
2299 printk(KERN_DEBUG "boomerang_interrupt(1): status = 0xffff\n");
2303 if (status & IntReq) {
2304 status |= vp->deferred;
2308 if (vortex_debug > 4)
2309 printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n",
2310 dev->name, status, ioread8(ioaddr + Timer));
2312 if (vortex_debug > 5)
2313 printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n",
2315 if (status & UpComplete) {
2316 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2317 if (vortex_debug > 5)
2318 printk(KERN_DEBUG "boomerang_interrupt->boomerang_rx\n");
2322 if (status & DownComplete) {
2323 unsigned int dirty_tx = vp->dirty_tx;
2325 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2326 while (vp->cur_tx - dirty_tx > 0) {
2327 int entry = dirty_tx % TX_RING_SIZE;
2328 #if 1 /* AKPM: the latter is faster, but cyclone-only */
2329 if (ioread32(ioaddr + DownListPtr) ==
2330 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2331 break; /* It still hasn't been processed. */
2333 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2334 break; /* It still hasn't been processed. */
2337 if (vp->tx_skbuff[entry]) {
2338 struct sk_buff *skb = vp->tx_skbuff[entry];
2341 for (i=0; i<=skb_shinfo(skb)->nr_frags; i++)
2342 pci_unmap_single(VORTEX_PCI(vp),
2343 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2344 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2347 pci_unmap_single(VORTEX_PCI(vp),
2348 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, PCI_DMA_TODEVICE);
2350 dev_kfree_skb_irq(skb);
2351 vp->tx_skbuff[entry] = NULL;
2353 printk(KERN_DEBUG "boomerang_interrupt: no skb!\n");
2355 /* dev->stats.tx_packets++; Counted below. */
2358 vp->dirty_tx = dirty_tx;
2359 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2360 if (vortex_debug > 6)
2361 printk(KERN_DEBUG "boomerang_interrupt: wake queue\n");
2362 netif_wake_queue (dev);
2366 /* Check for all uncommon interrupts at once. */
2367 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2368 vortex_error(dev, status);
2370 if (--work_done < 0) {
2371 printk(KERN_WARNING "%s: Too much work in interrupt, status "
2372 "%4.4x.\n", dev->name, status);
2373 /* Disable all pending interrupts. */
2375 vp->deferred |= status;
2376 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2378 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2379 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2380 /* The timer will reenable interrupts. */
2381 mod_timer(&vp->timer, jiffies + 1*HZ);
2384 /* Acknowledge the IRQ. */
2385 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2386 if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
2387 iowrite32(0x8000, vp->cb_fn_base + 4);
2389 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2391 if (vortex_debug > 4)
2392 printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n",
2395 spin_unlock(&vp->lock);
2399 static int vortex_rx(struct net_device *dev)
2401 struct vortex_private *vp = netdev_priv(dev);
2402 void __iomem *ioaddr = vp->ioaddr;
2406 if (vortex_debug > 5)
2407 printk(KERN_DEBUG "vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2408 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2409 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2410 if (rx_status & 0x4000) { /* Error, update stats. */
2411 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2412 if (vortex_debug > 2)
2413 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2414 dev->stats.rx_errors++;
2415 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2416 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2417 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2418 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2419 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2421 /* The packet length: up to 4.5K!. */
2422 int pkt_len = rx_status & 0x1fff;
2423 struct sk_buff *skb;
2425 skb = dev_alloc_skb(pkt_len + 5);
2426 if (vortex_debug > 4)
2427 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2428 pkt_len, rx_status);
2430 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2431 /* 'skb_put()' points to the start of sk_buff data area. */
2432 if (vp->bus_master &&
2433 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2434 dma_addr_t dma = pci_map_single(VORTEX_PCI(vp), skb_put(skb, pkt_len),
2435 pkt_len, PCI_DMA_FROMDEVICE);
2436 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2437 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2438 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2439 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2441 pci_unmap_single(VORTEX_PCI(vp), dma, pkt_len, PCI_DMA_FROMDEVICE);
2443 ioread32_rep(ioaddr + RX_FIFO,
2444 skb_put(skb, pkt_len),
2445 (pkt_len + 3) >> 2);
2447 iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
2448 skb->protocol = eth_type_trans(skb, dev);
2450 dev->last_rx = jiffies;
2451 dev->stats.rx_packets++;
2452 /* Wait a limited time to go to next packet. */
2453 for (i = 200; i >= 0; i--)
2454 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2457 } else if (vortex_debug > 0)
2458 printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of "
2459 "size %d.\n", dev->name, pkt_len);
2460 dev->stats.rx_dropped++;
2462 issue_and_wait(dev, RxDiscard);
2469 boomerang_rx(struct net_device *dev)
2471 struct vortex_private *vp = netdev_priv(dev);
2472 int entry = vp->cur_rx % RX_RING_SIZE;
2473 void __iomem *ioaddr = vp->ioaddr;
2475 int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx;
2477 if (vortex_debug > 5)
2478 printk(KERN_DEBUG "boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2480 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2481 if (--rx_work_limit < 0)
2483 if (rx_status & RxDError) { /* Error, update stats. */
2484 unsigned char rx_error = rx_status >> 16;
2485 if (vortex_debug > 2)
2486 printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error);
2487 dev->stats.rx_errors++;
2488 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2489 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2490 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2491 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2492 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2494 /* The packet length: up to 4.5K!. */
2495 int pkt_len = rx_status & 0x1fff;
2496 struct sk_buff *skb;
2497 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2499 if (vortex_debug > 4)
2500 printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n",
2501 pkt_len, rx_status);
2503 /* Check if the packet is long enough to just accept without
2504 copying to a properly sized skbuff. */
2505 if (pkt_len < rx_copybreak && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
2506 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
2507 pci_dma_sync_single_for_cpu(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2508 /* 'skb_put()' points to the start of sk_buff data area. */
2509 memcpy(skb_put(skb, pkt_len),
2510 vp->rx_skbuff[entry]->data,
2512 pci_dma_sync_single_for_device(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2515 /* Pass up the skbuff already on the Rx ring. */
2516 skb = vp->rx_skbuff[entry];
2517 vp->rx_skbuff[entry] = NULL;
2518 skb_put(skb, pkt_len);
2519 pci_unmap_single(VORTEX_PCI(vp), dma, PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2522 skb->protocol = eth_type_trans(skb, dev);
2523 { /* Use hardware checksum info. */
2524 int csum_bits = rx_status & 0xee000000;
2526 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2527 csum_bits == (IPChksumValid | UDPChksumValid))) {
2528 skb->ip_summed = CHECKSUM_UNNECESSARY;
2533 dev->last_rx = jiffies;
2534 dev->stats.rx_packets++;
2536 entry = (++vp->cur_rx) % RX_RING_SIZE;
2538 /* Refill the Rx ring buffers. */
2539 for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
2540 struct sk_buff *skb;
2541 entry = vp->dirty_rx % RX_RING_SIZE;
2542 if (vp->rx_skbuff[entry] == NULL) {
2543 skb = netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN);
2545 static unsigned long last_jif;
2546 if (time_after(jiffies, last_jif + 10 * HZ)) {
2547 printk(KERN_WARNING "%s: memory shortage\n", dev->name);
2550 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE)
2551 mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1));
2552 break; /* Bad news! */
2555 skb_reserve(skb, NET_IP_ALIGN);
2556 vp->rx_ring[entry].addr = cpu_to_le32(pci_map_single(VORTEX_PCI(vp), skb->data, PKT_BUF_SZ, PCI_DMA_FROMDEVICE));
2557 vp->rx_skbuff[entry] = skb;
2559 vp->rx_ring[entry].status = 0; /* Clear complete bit. */
2560 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2566 * If we've hit a total OOM refilling the Rx ring we poll once a second
2567 * for some memory. Otherwise there is no way to restart the rx process.
2570 rx_oom_timer(unsigned long arg)
2572 struct net_device *dev = (struct net_device *)arg;
2573 struct vortex_private *vp = netdev_priv(dev);
2575 spin_lock_irq(&vp->lock);
2576 if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */
2578 if (vortex_debug > 1) {
2579 printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name,
2580 ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying");
2582 spin_unlock_irq(&vp->lock);
2586 vortex_down(struct net_device *dev, int final_down)
2588 struct vortex_private *vp = netdev_priv(dev);
2589 void __iomem *ioaddr = vp->ioaddr;
2591 netif_stop_queue (dev);
2593 del_timer_sync(&vp->rx_oom_timer);
2594 del_timer_sync(&vp->timer);
2596 /* Turn off statistics ASAP. We update dev->stats below. */
2597 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2599 /* Disable the receiver and transmitter. */
2600 iowrite16(RxDisable, ioaddr + EL3_CMD);
2601 iowrite16(TxDisable, ioaddr + EL3_CMD);
2603 /* Disable receiving 802.1q tagged frames */
2604 set_8021q_mode(dev, 0);
2606 if (dev->if_port == XCVR_10base2)
2607 /* Turn off thinnet power. Green! */
2608 iowrite16(StopCoax, ioaddr + EL3_CMD);
2610 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2612 update_stats(ioaddr, dev);
2613 if (vp->full_bus_master_rx)
2614 iowrite32(0, ioaddr + UpListPtr);
2615 if (vp->full_bus_master_tx)
2616 iowrite32(0, ioaddr + DownListPtr);
2618 if (final_down && VORTEX_PCI(vp)) {
2619 vp->pm_state_valid = 1;
2620 pci_save_state(VORTEX_PCI(vp));
2626 vortex_close(struct net_device *dev)
2628 struct vortex_private *vp = netdev_priv(dev);
2629 void __iomem *ioaddr = vp->ioaddr;
2632 if (netif_device_present(dev))
2633 vortex_down(dev, 1);
2635 if (vortex_debug > 1) {
2636 printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2637 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2638 printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d"
2639 " tx_queued %d Rx pre-checksummed %d.\n",
2640 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2644 if (vp->rx_csumhits &&
2645 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2646 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2647 printk(KERN_WARNING "%s supports hardware checksums, and we're "
2648 "not using them!\n", dev->name);
2652 free_irq(dev->irq, dev);
2654 if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
2655 for (i = 0; i < RX_RING_SIZE; i++)
2656 if (vp->rx_skbuff[i]) {
2657 pci_unmap_single( VORTEX_PCI(vp), le32_to_cpu(vp->rx_ring[i].addr),
2658 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
2659 dev_kfree_skb(vp->rx_skbuff[i]);
2660 vp->rx_skbuff[i] = NULL;
2663 if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
2664 for (i = 0; i < TX_RING_SIZE; i++) {
2665 if (vp->tx_skbuff[i]) {
2666 struct sk_buff *skb = vp->tx_skbuff[i];
2670 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2671 pci_unmap_single(VORTEX_PCI(vp),
2672 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2673 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2676 pci_unmap_single(VORTEX_PCI(vp), le32_to_cpu(vp->tx_ring[i].addr), skb->len, PCI_DMA_TODEVICE);
2679 vp->tx_skbuff[i] = NULL;
2688 dump_tx_ring(struct net_device *dev)
2690 if (vortex_debug > 0) {
2691 struct vortex_private *vp = netdev_priv(dev);
2692 void __iomem *ioaddr = vp->ioaddr;
2694 if (vp->full_bus_master_tx) {
2696 int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
2698 printk(KERN_ERR " Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2699 vp->full_bus_master_tx,
2700 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2701 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2702 printk(KERN_ERR " Transmit list %8.8x vs. %p.\n",
2703 ioread32(ioaddr + DownListPtr),
2704 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2705 issue_and_wait(dev, DownStall);
2706 for (i = 0; i < TX_RING_SIZE; i++) {
2707 printk(KERN_ERR " %d: @%p length %8.8x status %8.8x\n", i,
2710 le32_to_cpu(vp->tx_ring[i].frag[0].length),
2712 le32_to_cpu(vp->tx_ring[i].length),
2714 le32_to_cpu(vp->tx_ring[i].status));
2717 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2722 static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2724 struct vortex_private *vp = netdev_priv(dev);
2725 void __iomem *ioaddr = vp->ioaddr;
2726 unsigned long flags;
2728 if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
2729 spin_lock_irqsave (&vp->lock, flags);
2730 update_stats(ioaddr, dev);
2731 spin_unlock_irqrestore (&vp->lock, flags);
2736 /* Update statistics.
2737 Unlike with the EL3 we need not worry about interrupts changing
2738 the window setting from underneath us, but we must still guard
2739 against a race condition with a StatsUpdate interrupt updating the
2740 table. This is done by checking that the ASM (!) code generated uses
2741 atomic updates with '+='.
2743 static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2745 struct vortex_private *vp = netdev_priv(dev);
2746 int old_window = ioread16(ioaddr + EL3_CMD);
2748 if (old_window == 0xffff) /* Chip suspended or ejected. */
2750 /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
2751 /* Switch to the stats window, and read everything. */
2753 dev->stats.tx_carrier_errors += ioread8(ioaddr + 0);
2754 dev->stats.tx_heartbeat_errors += ioread8(ioaddr + 1);
2755 dev->stats.tx_window_errors += ioread8(ioaddr + 4);
2756 dev->stats.rx_fifo_errors += ioread8(ioaddr + 5);
2757 dev->stats.tx_packets += ioread8(ioaddr + 6);
2758 dev->stats.tx_packets += (ioread8(ioaddr + 9)&0x30) << 4;
2759 /* Rx packets */ ioread8(ioaddr + 7); /* Must read to clear */
2760 /* Don't bother with register 9, an extension of registers 6&7.
2761 If we do use the 6&7 values the atomic update assumption above
2763 dev->stats.rx_bytes += ioread16(ioaddr + 10);
2764 dev->stats.tx_bytes += ioread16(ioaddr + 12);
2765 /* Extra stats for get_ethtool_stats() */
2766 vp->xstats.tx_multiple_collisions += ioread8(ioaddr + 2);
2767 vp->xstats.tx_single_collisions += ioread8(ioaddr + 3);
2768 vp->xstats.tx_deferred += ioread8(ioaddr + 8);
2770 vp->xstats.rx_bad_ssd += ioread8(ioaddr + 12);
2772 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2773 + vp->xstats.tx_single_collisions
2774 + vp->xstats.tx_max_collisions;
2777 u8 up = ioread8(ioaddr + 13);
2778 dev->stats.rx_bytes += (up & 0x0f) << 16;
2779 dev->stats.tx_bytes += (up & 0xf0) << 12;
2782 EL3WINDOW(old_window >> 13);
2786 static int vortex_nway_reset(struct net_device *dev)
2788 struct vortex_private *vp = netdev_priv(dev);
2789 void __iomem *ioaddr = vp->ioaddr;
2790 unsigned long flags;
2793 spin_lock_irqsave(&vp->lock, flags);
2795 rc = mii_nway_restart(&vp->mii);
2796 spin_unlock_irqrestore(&vp->lock, flags);
2800 static int vortex_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2802 struct vortex_private *vp = netdev_priv(dev);
2803 void __iomem *ioaddr = vp->ioaddr;
2804 unsigned long flags;
2807 spin_lock_irqsave(&vp->lock, flags);
2809 rc = mii_ethtool_gset(&vp->mii, cmd);
2810 spin_unlock_irqrestore(&vp->lock, flags);
2814 static int vortex_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2816 struct vortex_private *vp = netdev_priv(dev);
2817 void __iomem *ioaddr = vp->ioaddr;
2818 unsigned long flags;
2821 spin_lock_irqsave(&vp->lock, flags);
2823 rc = mii_ethtool_sset(&vp->mii, cmd);
2824 spin_unlock_irqrestore(&vp->lock, flags);
2828 static u32 vortex_get_msglevel(struct net_device *dev)
2830 return vortex_debug;
2833 static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2838 static int vortex_get_sset_count(struct net_device *dev, int sset)
2842 return VORTEX_NUM_STATS;
2848 static void vortex_get_ethtool_stats(struct net_device *dev,
2849 struct ethtool_stats *stats, u64 *data)
2851 struct vortex_private *vp = netdev_priv(dev);
2852 void __iomem *ioaddr = vp->ioaddr;
2853 unsigned long flags;
2855 spin_lock_irqsave(&vp->lock, flags);
2856 update_stats(ioaddr, dev);
2857 spin_unlock_irqrestore(&vp->lock, flags);
2859 data[0] = vp->xstats.tx_deferred;
2860 data[1] = vp->xstats.tx_max_collisions;
2861 data[2] = vp->xstats.tx_multiple_collisions;
2862 data[3] = vp->xstats.tx_single_collisions;
2863 data[4] = vp->xstats.rx_bad_ssd;
2867 static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2869 switch (stringset) {
2871 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2879 static void vortex_get_drvinfo(struct net_device *dev,
2880 struct ethtool_drvinfo *info)
2882 struct vortex_private *vp = netdev_priv(dev);
2884 strcpy(info->driver, DRV_NAME);
2885 if (VORTEX_PCI(vp)) {
2886 strcpy(info->bus_info, pci_name(VORTEX_PCI(vp)));
2888 if (VORTEX_EISA(vp))
2889 sprintf(info->bus_info, vp->gendev->bus_id);
2891 sprintf(info->bus_info, "EISA 0x%lx %d",
2892 dev->base_addr, dev->irq);
2896 static const struct ethtool_ops vortex_ethtool_ops = {
2897 .get_drvinfo = vortex_get_drvinfo,
2898 .get_strings = vortex_get_strings,
2899 .get_msglevel = vortex_get_msglevel,
2900 .set_msglevel = vortex_set_msglevel,
2901 .get_ethtool_stats = vortex_get_ethtool_stats,
2902 .get_sset_count = vortex_get_sset_count,
2903 .get_settings = vortex_get_settings,
2904 .set_settings = vortex_set_settings,
2905 .get_link = ethtool_op_get_link,
2906 .nway_reset = vortex_nway_reset,
2911 * Must power the device up to do MDIO operations
2913 static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2916 struct vortex_private *vp = netdev_priv(dev);
2917 void __iomem *ioaddr = vp->ioaddr;
2918 unsigned long flags;
2919 pci_power_t state = 0;
2922 state = VORTEX_PCI(vp)->current_state;
2924 /* The kernel core really should have pci_get_power_state() */
2927 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
2928 spin_lock_irqsave(&vp->lock, flags);
2930 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
2931 spin_unlock_irqrestore(&vp->lock, flags);
2933 pci_set_power_state(VORTEX_PCI(vp), state);
2940 /* Pre-Cyclone chips have no documented multicast filter, so the only
2941 multicast setting is to receive all multicast frames. At least
2942 the chip has a very clean way to set the mode, unlike many others. */
2943 static void set_rx_mode(struct net_device *dev)
2945 struct vortex_private *vp = netdev_priv(dev);
2946 void __iomem *ioaddr = vp->ioaddr;
2949 if (dev->flags & IFF_PROMISC) {
2950 if (vortex_debug > 3)
2951 printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name);
2952 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
2953 } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) {
2954 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
2956 new_mode = SetRxFilter | RxStation | RxBroadcast;
2958 iowrite16(new_mode, ioaddr + EL3_CMD);
2961 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
2962 /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
2963 Note that this must be done after each RxReset due to some backwards
2964 compatibility logic in the Cyclone and Tornado ASICs */
2966 /* The Ethernet Type used for 802.1q tagged frames */
2967 #define VLAN_ETHER_TYPE 0x8100
2969 static void set_8021q_mode(struct net_device *dev, int enable)
2971 struct vortex_private *vp = netdev_priv(dev);
2972 void __iomem *ioaddr = vp->ioaddr;
2973 int old_window = ioread16(ioaddr + EL3_CMD);
2976 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
2977 /* cyclone and tornado chipsets can recognize 802.1q
2978 * tagged frames and treat them correctly */
2980 int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
2982 max_pkt_size += 4; /* 802.1Q VLAN tag */
2985 iowrite16(max_pkt_size, ioaddr+Wn3_MaxPktSize);
2987 /* set VlanEtherType to let the hardware checksumming
2988 treat tagged frames correctly */
2990 iowrite16(VLAN_ETHER_TYPE, ioaddr+Wn7_VlanEtherType);
2992 /* on older cards we have to enable large frames */
2994 vp->large_frames = dev->mtu > 1500 || enable;
2997 mac_ctrl = ioread16(ioaddr+Wn3_MAC_Ctrl);
2998 if (vp->large_frames)
3002 iowrite16(mac_ctrl, ioaddr+Wn3_MAC_Ctrl);
3005 EL3WINDOW(old_window);
3009 static void set_8021q_mode(struct net_device *dev, int enable)
3016 /* MII transceiver control section.
3017 Read and write the MII registers using software-generated serial
3018 MDIO protocol. See the MII specifications or DP83840A data sheet
3021 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
3022 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
3023 "overclocking" issues. */
3024 #define mdio_delay() ioread32(mdio_addr)
3026 #define MDIO_SHIFT_CLK 0x01
3027 #define MDIO_DIR_WRITE 0x04
3028 #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3029 #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3030 #define MDIO_DATA_READ 0x02
3031 #define MDIO_ENB_IN 0x00
3033 /* Generate the preamble required for initial synchronization and
3034 a few older transceivers. */
3035 static void mdio_sync(void __iomem *ioaddr, int bits)
3037 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3039 /* Establish sync by sending at least 32 logic ones. */
3040 while (-- bits >= 0) {
3041 iowrite16(MDIO_DATA_WRITE1, mdio_addr);
3043 iowrite16(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
3048 static int mdio_read(struct net_device *dev, int phy_id, int location)
3051 struct vortex_private *vp = netdev_priv(dev);
3052 void __iomem *ioaddr = vp->ioaddr;
3053 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3054 unsigned int retval = 0;
3055 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3057 if (mii_preamble_required)
3058 mdio_sync(ioaddr, 32);
3060 /* Shift the read command bits out. */
3061 for (i = 14; i >= 0; i--) {
3062 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3063 iowrite16(dataval, mdio_addr);
3065 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3068 /* Read the two transition, 16 data, and wire-idle bits. */
3069 for (i = 19; i > 0; i--) {
3070 iowrite16(MDIO_ENB_IN, mdio_addr);
3072 retval = (retval << 1) | ((ioread16(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
3073 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3076 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3079 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3081 struct vortex_private *vp = netdev_priv(dev);
3082 void __iomem *ioaddr = vp->ioaddr;
3083 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3084 void __iomem *mdio_addr = ioaddr + Wn4_PhysicalMgmt;
3087 if (mii_preamble_required)
3088 mdio_sync(ioaddr, 32);
3090 /* Shift the command bits out. */
3091 for (i = 31; i >= 0; i--) {
3092 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3093 iowrite16(dataval, mdio_addr);
3095 iowrite16(dataval | MDIO_SHIFT_CLK, mdio_addr);
3098 /* Leave the interface idle. */
3099 for (i = 1; i >= 0; i--) {
3100 iowrite16(MDIO_ENB_IN, mdio_addr);
3102 iowrite16(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
3108 /* ACPI: Advanced Configuration and Power Interface. */
3109 /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
3110 static void acpi_set_WOL(struct net_device *dev)
3112 struct vortex_private *vp = netdev_priv(dev);
3113 void __iomem *ioaddr = vp->ioaddr;
3115 if (vp->enable_wol) {
3116 /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
3118 iowrite16(2, ioaddr + 0x0c);
3119 /* The RxFilter must accept the WOL frames. */
3120 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3121 iowrite16(RxEnable, ioaddr + EL3_CMD);
3123 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3124 printk(KERN_INFO "%s: WOL not supported.\n",
3125 pci_name(VORTEX_PCI(vp)));
3131 /* Change the power state to D3; RxEnable doesn't take effect. */
3132 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3137 static void __devexit vortex_remove_one(struct pci_dev *pdev)
3139 struct net_device *dev = pci_get_drvdata(pdev);
3140 struct vortex_private *vp;
3143 printk("vortex_remove_one called for Compaq device!\n");
3147 vp = netdev_priv(dev);
3150 pci_iounmap(VORTEX_PCI(vp), vp->cb_fn_base);
3152 unregister_netdev(dev);
3154 if (VORTEX_PCI(vp)) {
3155 pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
3156 if (vp->pm_state_valid)
3157 pci_restore_state(VORTEX_PCI(vp));
3158 pci_disable_device(VORTEX_PCI(vp));
3160 /* Should really use issue_and_wait() here */
3161 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3162 vp->ioaddr + EL3_CMD);
3164 pci_iounmap(VORTEX_PCI(vp), vp->ioaddr);
3166 pci_free_consistent(pdev,
3167 sizeof(struct boom_rx_desc) * RX_RING_SIZE
3168 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3171 if (vp->must_free_region)
3172 release_region(dev->base_addr, vp->io_size);
3177 static struct pci_driver vortex_driver = {
3179 .probe = vortex_init_one,
3180 .remove = __devexit_p(vortex_remove_one),
3181 .id_table = vortex_pci_tbl,
3183 .suspend = vortex_suspend,
3184 .resume = vortex_resume,
3189 static int vortex_have_pci;
3190 static int vortex_have_eisa;
3193 static int __init vortex_init(void)
3195 int pci_rc, eisa_rc;
3197 pci_rc = pci_register_driver(&vortex_driver);
3198 eisa_rc = vortex_eisa_init();
3201 vortex_have_pci = 1;
3203 vortex_have_eisa = 1;
3205 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3209 static void __exit vortex_eisa_cleanup(void)
3211 struct vortex_private *vp;
3212 void __iomem *ioaddr;
3215 /* Take care of the EISA devices */
3216 eisa_driver_unregister(&vortex_eisa_driver);
3219 if (compaq_net_device) {
3220 vp = compaq_net_device->priv;
3221 ioaddr = ioport_map(compaq_net_device->base_addr,
3224 unregister_netdev(compaq_net_device);
3225 iowrite16(TotalReset, ioaddr + EL3_CMD);
3226 release_region(compaq_net_device->base_addr,
3229 free_netdev(compaq_net_device);
3234 static void __exit vortex_cleanup(void)
3236 if (vortex_have_pci)
3237 pci_unregister_driver(&vortex_driver);
3238 if (vortex_have_eisa)
3239 vortex_eisa_cleanup();
3243 module_init(vortex_init);
3244 module_exit(vortex_cleanup);