2 * linux/drivers/mtd/onenand/omap2.c
4 * OneNAND driver for OMAP2 / OMAP3
6 * Copyright (C) 2005-2006 Nokia Corporation
8 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
9 * IRQ and DMA support written by Timo Teras
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; see the file COPYING. If not, write to the Free Software
22 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/onenand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
37 #include <asm/mach/flash.h>
38 #include <mach/gpmc.h>
39 #include <mach/onenand.h>
40 #include <mach/gpio.h>
41 #include <mach/gpmc.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/dma-mapping.h>
48 #include <mach/board.h>
50 #define DRIVER_NAME "omap2-onenand"
52 #define ONENAND_IO_SIZE SZ_128K
53 #define ONENAND_BUFRAM_SIZE (1024 * 5)
55 struct omap2_onenand {
56 struct platform_device *pdev;
58 unsigned long phys_base;
61 struct mtd_partition *parts;
62 struct onenand_chip onenand;
63 struct completion irq_done;
64 struct completion dma_done;
67 int (*setup)(void __iomem *base, int freq);
70 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
72 struct omap2_onenand *c = data;
74 complete(&c->dma_done);
77 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
79 struct omap2_onenand *c = dev_id;
81 complete(&c->irq_done);
86 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
88 return readw(c->onenand.base + reg);
91 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
94 writew(value, c->onenand.base + reg);
97 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
99 printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
100 msg, state, ctrl, intr);
103 static void wait_warn(char *msg, int state, unsigned int ctrl,
106 printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
107 "intr 0x%04x\n", msg, state, ctrl, intr);
110 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
112 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
113 unsigned int intr = 0;
115 unsigned long timeout;
118 if (state == FL_RESETING) {
121 for (i = 0; i < 20; i++) {
123 intr = read_reg(c, ONENAND_REG_INTERRUPT);
124 if (intr & ONENAND_INT_MASTER)
127 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
128 if (ctrl & ONENAND_CTRL_ERROR) {
129 wait_err("controller error", state, ctrl, intr);
132 if (!(intr & ONENAND_INT_RESET)) {
133 wait_err("timeout", state, ctrl, intr);
139 if (state != FL_READING) {
142 /* Turn interrupts on */
143 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
144 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
145 syscfg |= ONENAND_SYS_CFG1_IOBE;
146 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
147 if (cpu_is_omap34xx())
148 /* Add a delay to let GPIO settle */
149 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
152 INIT_COMPLETION(c->irq_done);
154 result = omap_get_gpio_datain(c->gpio_irq);
156 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
157 intr = read_reg(c, ONENAND_REG_INTERRUPT);
158 wait_err("gpio error", state, ctrl, intr);
166 result = wait_for_completion_timeout(&c->irq_done,
167 msecs_to_jiffies(20));
169 /* Timeout after 20ms */
170 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
171 if (ctrl & ONENAND_CTRL_ONGO) {
173 * The operation seems to be still going
174 * so give it some more time.
180 ONENAND_REG_INTERRUPT);
181 wait_err("timeout", state, ctrl, intr);
184 intr = read_reg(c, ONENAND_REG_INTERRUPT);
185 if ((intr & ONENAND_INT_MASTER) == 0)
186 wait_warn("timeout", state, ctrl, intr);
190 /* Turn interrupts off */
191 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
192 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
193 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
195 timeout = jiffies + msecs_to_jiffies(20);
196 while (time_before(jiffies, timeout)) {
197 intr = read_reg(c, ONENAND_REG_INTERRUPT);
198 if (intr & ONENAND_INT_MASTER)
203 intr = read_reg(c, ONENAND_REG_INTERRUPT);
204 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
206 if (intr & ONENAND_INT_READ) {
207 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
210 unsigned int addr1, addr8;
212 addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
213 addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
214 if (ecc & ONENAND_ECC_2BIT_ALL) {
215 printk(KERN_ERR "onenand_wait: ECC error = "
216 "0x%04x, addr1 %#x, addr8 %#x\n",
218 mtd->ecc_stats.failed++;
220 } else if (ecc & ONENAND_ECC_1BIT_ALL) {
221 printk(KERN_NOTICE "onenand_wait: correctable "
222 "ECC error = 0x%04x, addr1 %#x, "
223 "addr8 %#x\n", ecc, addr1, addr8);
224 mtd->ecc_stats.corrected++;
227 } else if (state == FL_READING) {
228 wait_err("timeout", state, ctrl, intr);
232 if (ctrl & ONENAND_CTRL_ERROR) {
233 wait_err("controller error", state, ctrl, intr);
234 if (ctrl & ONENAND_CTRL_LOCK)
235 printk(KERN_ERR "onenand_wait: "
236 "Device is write protected!!!\n");
241 wait_warn("unexpected controller status", state, ctrl, intr);
246 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
248 struct onenand_chip *this = mtd->priv;
250 if (ONENAND_CURRENT_BUFFERRAM(this)) {
251 if (area == ONENAND_DATARAM)
252 return mtd->writesize;
253 if (area == ONENAND_SPARERAM)
260 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
262 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
263 unsigned char *buffer, int offset,
266 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
267 struct onenand_chip *this = mtd->priv;
268 dma_addr_t dma_src, dma_dst;
270 unsigned long timeout;
271 void *buf = (void *)buffer;
273 volatile unsigned *done;
275 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
276 if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
279 if (buf >= high_memory) {
282 if (((size_t)buf & PAGE_MASK) !=
283 ((size_t)(buf + count - 1) & PAGE_MASK))
285 p1 = vmalloc_to_page(buf);
288 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
294 memcpy(buf + count, this->base + bram_offset + count, xtra);
297 dma_src = c->phys_base + bram_offset;
298 dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
299 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
300 dev_err(&c->pdev->dev,
301 "Couldn't DMA map a %d byte buffer\n",
306 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
307 count >> 2, 1, 0, 0, 0);
308 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
310 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
313 INIT_COMPLETION(c->dma_done);
314 omap_start_dma(c->dma_channel);
316 timeout = jiffies + msecs_to_jiffies(20);
317 done = &c->dma_done.done;
318 while (time_before(jiffies, timeout))
322 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
325 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
332 memcpy(buf, this->base + bram_offset, count);
336 static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
337 const unsigned char *buffer,
338 int offset, size_t count)
340 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
341 struct onenand_chip *this = mtd->priv;
342 dma_addr_t dma_src, dma_dst;
344 unsigned long timeout;
345 void *buf = (void *)buffer;
346 volatile unsigned *done;
348 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
349 if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
352 /* panic_write() may be in an interrupt context */
356 if (buf >= high_memory) {
359 if (((size_t)buf & PAGE_MASK) !=
360 ((size_t)(buf + count - 1) & PAGE_MASK))
362 p1 = vmalloc_to_page(buf);
365 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
368 dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
369 dma_dst = c->phys_base + bram_offset;
370 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
371 dev_err(&c->pdev->dev,
372 "Couldn't DMA map a %d byte buffer\n",
377 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
378 count >> 2, 1, 0, 0, 0);
379 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
381 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
384 INIT_COMPLETION(c->dma_done);
385 omap_start_dma(c->dma_channel);
387 timeout = jiffies + msecs_to_jiffies(20);
388 done = &c->dma_done.done;
389 while (time_before(jiffies, timeout))
393 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
396 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
403 memcpy(this->base + bram_offset, buf, count);
409 int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
410 unsigned char *buffer, int offset,
413 int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
414 const unsigned char *buffer,
415 int offset, size_t count);
419 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
421 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
422 unsigned char *buffer, int offset,
425 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
426 struct onenand_chip *this = mtd->priv;
427 dma_addr_t dma_src, dma_dst;
430 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
431 /* DMA is not used. Revisit PM requirements before enabling it. */
432 if (1 || (c->dma_channel < 0) ||
433 ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
434 (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
435 memcpy(buffer, (__force void *)(this->base + bram_offset),
440 dma_src = c->phys_base + bram_offset;
441 dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
443 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
444 dev_err(&c->pdev->dev,
445 "Couldn't DMA map a %d byte buffer\n",
450 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
451 count / 4, 1, 0, 0, 0);
452 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
454 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
457 INIT_COMPLETION(c->dma_done);
458 omap_start_dma(c->dma_channel);
459 wait_for_completion(&c->dma_done);
461 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
466 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
467 const unsigned char *buffer,
468 int offset, size_t count)
470 struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
471 struct onenand_chip *this = mtd->priv;
472 dma_addr_t dma_src, dma_dst;
475 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
476 /* DMA is not used. Revisit PM requirements before enabling it. */
477 if (1 || (c->dma_channel < 0) ||
478 ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
479 (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
480 memcpy((__force void *)(this->base + bram_offset), buffer,
485 dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
487 dma_dst = c->phys_base + bram_offset;
488 if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
489 dev_err(&c->pdev->dev,
490 "Couldn't DMA map a %d byte buffer\n",
495 omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
496 count / 2, 1, 0, 0, 0);
497 omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
499 omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
502 INIT_COMPLETION(c->dma_done);
503 omap_start_dma(c->dma_channel);
504 wait_for_completion(&c->dma_done);
506 dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
513 int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
514 unsigned char *buffer, int offset,
517 int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
518 const unsigned char *buffer,
519 int offset, size_t count);
523 static struct platform_driver omap2_onenand_driver;
525 static int __adjust_timing(struct device *dev, void *data)
528 struct omap2_onenand *c;
530 c = dev_get_drvdata(dev);
532 BUG_ON(c->setup == NULL);
534 /* DMA is not in use so this is all that is needed */
535 /* Revisit for OMAP3! */
536 ret = c->setup(c->onenand.base, c->freq);
541 int omap2_onenand_rephase(void)
543 return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
544 NULL, __adjust_timing);
547 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
549 struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
551 /* With certain content in the buffer RAM, the OMAP boot ROM code
552 * can recognize the flash chip incorrectly. Zero it out before
555 memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
558 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
560 struct omap_onenand_platform_data *pdata;
561 struct omap2_onenand *c;
564 pdata = pdev->dev.platform_data;
566 dev_err(&pdev->dev, "platform data missing\n");
570 c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
574 init_completion(&c->irq_done);
575 init_completion(&c->dma_done);
576 c->gpmc_cs = pdata->cs;
577 c->gpio_irq = pdata->gpio_irq;
578 c->dma_channel = pdata->dma_channel;
579 if (c->dma_channel < 0) {
580 /* if -1, don't use DMA */
584 r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
586 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
590 if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
591 pdev->dev.driver->name) == NULL) {
592 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
593 "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
597 c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
598 if (c->onenand.base == NULL) {
600 goto err_release_mem_region;
603 if (pdata->onenand_setup != NULL) {
604 r = pdata->onenand_setup(c->onenand.base, c->freq);
606 dev_err(&pdev->dev, "Onenand platform setup failed: "
610 c->setup = pdata->onenand_setup;
614 if ((r = omap_request_gpio(c->gpio_irq)) < 0) {
615 dev_err(&pdev->dev, "Failed to request GPIO%d for "
616 "OneNAND\n", c->gpio_irq);
619 omap_set_gpio_direction(c->gpio_irq, 1);
621 if ((r = request_irq(OMAP_GPIO_IRQ(c->gpio_irq),
622 omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
623 pdev->dev.driver->name, c)) < 0)
624 goto err_release_gpio;
627 if (c->dma_channel >= 0) {
628 r = omap_request_dma(0, pdev->dev.driver->name,
629 omap2_onenand_dma_cb, (void *) c,
632 omap_set_dma_write_mode(c->dma_channel,
633 OMAP_DMA_WRITE_NON_POSTED);
634 omap_set_dma_src_data_pack(c->dma_channel, 1);
635 omap_set_dma_src_burst_mode(c->dma_channel,
636 OMAP_DMA_DATA_BURST_8);
637 omap_set_dma_dest_data_pack(c->dma_channel, 1);
638 omap_set_dma_dest_burst_mode(c->dma_channel,
639 OMAP_DMA_DATA_BURST_8);
642 "failed to allocate DMA for OneNAND, "
643 "using PIO instead\n");
648 dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
649 "base %p\n", c->gpmc_cs, c->phys_base,
653 c->mtd.name = pdev->dev.bus_id;
654 c->mtd.priv = &c->onenand;
655 c->mtd.owner = THIS_MODULE;
657 if (c->dma_channel >= 0) {
658 struct onenand_chip *this = &c->onenand;
660 this->wait = omap2_onenand_wait;
661 if (cpu_is_omap34xx()) {
662 this->read_bufferram = omap3_onenand_read_bufferram;
663 this->write_bufferram = omap3_onenand_write_bufferram;
665 this->read_bufferram = omap2_onenand_read_bufferram;
666 this->write_bufferram = omap2_onenand_write_bufferram;
670 if ((r = onenand_scan(&c->mtd, 1)) < 0)
671 goto err_release_dma;
673 switch ((c->onenand.version_id >> 4) & 0xf) {
688 #ifdef CONFIG_MTD_PARTITIONS
689 if (pdata->parts != NULL)
690 r = add_mtd_partitions(&c->mtd, pdata->parts,
694 r = add_mtd_device(&c->mtd);
696 goto err_release_onenand;
698 platform_set_drvdata(pdev, c);
703 onenand_release(&c->mtd);
705 if (c->dma_channel != -1)
706 omap_free_dma(c->dma_channel);
708 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
711 omap_free_gpio(c->gpio_irq);
713 iounmap(c->onenand.base);
714 err_release_mem_region:
715 release_mem_region(c->phys_base, ONENAND_IO_SIZE);
717 gpmc_cs_free(c->gpmc_cs);
724 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
726 struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
730 #ifdef CONFIG_MTD_PARTITIONS
732 del_mtd_partitions(&c->mtd);
734 del_mtd_device(&c->mtd);
736 del_mtd_device(&c->mtd);
739 onenand_release(&c->mtd);
740 if (c->dma_channel != -1)
741 omap_free_dma(c->dma_channel);
742 omap2_onenand_shutdown(pdev);
743 platform_set_drvdata(pdev, NULL);
745 free_irq(OMAP_GPIO_IRQ(c->gpio_irq), c);
746 omap_free_gpio(c->gpio_irq);
748 iounmap(c->onenand.base);
749 release_mem_region(c->phys_base, ONENAND_IO_SIZE);
755 static struct platform_driver omap2_onenand_driver = {
756 .probe = omap2_onenand_probe,
757 .remove = omap2_onenand_remove,
758 .shutdown = omap2_onenand_shutdown,
761 .owner = THIS_MODULE,
765 static int __init omap2_onenand_init(void)
767 printk(KERN_INFO "OneNAND driver initializing\n");
768 return platform_driver_register(&omap2_onenand_driver);
771 static void __exit omap2_onenand_exit(void)
773 platform_driver_unregister(&omap2_onenand_driver);
776 module_init(omap2_onenand_init);
777 module_exit(omap2_onenand_exit);
779 MODULE_ALIAS(DRIVER_NAME);
780 MODULE_LICENSE("GPL");
781 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
782 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");