drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2 / OMAP3
   5  *
   6  *  Copyright © 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjölä
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/onenand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/delay.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/regulator/consumer.h>
  39
  40 #include <asm/mach/flash.h>
  41 #include <plat/gpmc.h>
  42 #include <plat/onenand.h>
  43 #include <asm/gpio.h>
  44
  45 #include <plat/dma.h>
  46
  47 #define DRIVER_NAME "omap2-onenand"
  48
  49 #define ONENAND_IO_SIZE         SZ_128K
  50 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  51
  52 struct omap2_onenand {
  53         struct platform_device *pdev;
  54         int gpmc_cs;
  55         unsigned long phys_base;
  56         int gpio_irq;
  57         struct mtd_info mtd;
  58         struct onenand_chip onenand;
  59         struct completion irq_done;
  60         struct completion dma_done;
  61         int dma_channel;
  62         int freq;
  63         int (*setup)(void __iomem *base, int *freq_ptr);
  64         struct regulator *regulator;
  65 };
  66
  67 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  68 {
  69         struct omap2_onenand *c = data;
  70
  71         complete(&c->dma_done);
  72 }
  73
  74 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
  75 {
  76         struct omap2_onenand *c = dev_id;
  77
  78         complete(&c->irq_done);
  79
  80         return IRQ_HANDLED;
  81 }
  82
  83 static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
  84 {
  85         return readw(c->onenand.base + reg);
  86 }
  87
  88 static inline void write_reg(struct omap2_onenand *c, unsigned short value,
  89                              int reg)
  90 {
  91         writew(value, c->onenand.base + reg);
  92 }
  93
  94 static void wait_err(char *msg, int state, unsigned int ctrl, unsigned int intr)
  95 {
  96         printk(KERN_ERR "onenand_wait: %s! state %d ctrl 0x%04x intr 0x%04x\n",
  97                msg, state, ctrl, intr);
  98 }
  99
 100 static void wait_warn(char *msg, int state, unsigned int ctrl,
 101                       unsigned int intr)
 102 {
 103         printk(KERN_WARNING "onenand_wait: %s! state %d ctrl 0x%04x "
 104                "intr 0x%04x\n", msg, state, ctrl, intr);
 105 }
 106
 107 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
 108 {
 109         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 110         struct onenand_chip *this = mtd->priv;
 111         unsigned int intr = 0;
 112         unsigned int ctrl, ctrl_mask;
 113         unsigned long timeout;
 114         u32 syscfg;
 115
 116         if (state == FL_RESETING || state == FL_PREPARING_ERASE ||
 117             state == FL_VERIFYING_ERASE) {
 118                 int i = 21;
 119                 unsigned int intr_flags = ONENAND_INT_MASTER;
 120
 121                 switch (state) {
 122                 case FL_RESETING:
 123                         intr_flags |= ONENAND_INT_RESET;
 124                         break;
 125                 case FL_PREPARING_ERASE:
 126                         intr_flags |= ONENAND_INT_ERASE;
 127                         break;
 128                 case FL_VERIFYING_ERASE:
 129                         i = 101;
 130                         break;
 131                 }
 132
 133                 while (--i) {
 134                         udelay(1);
 135                         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 136                         if (intr & ONENAND_INT_MASTER)
 137                                 break;
 138                 }
 139                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 140                 if (ctrl & ONENAND_CTRL_ERROR) {
 141                         wait_err("controller error", state, ctrl, intr);
 142                         return -EIO;
 143                 }
 144                 if ((intr & intr_flags) == intr_flags)
 145                         return 0;
 146                 /* Continue in wait for interrupt branch */
 147         }
 148
 149         if (state != FL_READING) {
 150                 int result;
 151
 152                 /* Turn interrupts on */
 153                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 154                 if (!(syscfg & ONENAND_SYS_CFG1_IOBE)) {
 155                         syscfg |= ONENAND_SYS_CFG1_IOBE;
 156                         write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 157                         if (cpu_is_omap34xx())
 158                                 /* Add a delay to let GPIO settle */
 159                                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 160                 }
 161
 162                 INIT_COMPLETION(c->irq_done);
 163                 if (c->gpio_irq) {
 164                         result = gpio_get_value(c->gpio_irq);
 165                         if (result == -1) {
 166                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 167                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 168                                 wait_err("gpio error", state, ctrl, intr);
 169                                 return -EIO;
 170                         }
 171                 } else
 172                         result = 0;
 173                 if (result == 0) {
 174                         int retry_cnt = 0;
 175 retry:
 176                         result = wait_for_completion_timeout(&c->irq_done,
 177                                                     msecs_to_jiffies(20));
 178                         if (result == 0) {
 179                                 /* Timeout after 20ms */
 180                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 181                                 if (ctrl & ONENAND_CTRL_ONGO &&
 182                                     !this->ongoing) {
 183                                         /*
 184                                          * The operation seems to be still going
 185                                          * so give it some more time.
 186                                          */
 187                                         retry_cnt += 1;
 188                                         if (retry_cnt < 3)
 189                                                 goto retry;
 190                                         intr = read_reg(c,
 191                                                         ONENAND_REG_INTERRUPT);
 192                                         wait_err("timeout", state, ctrl, intr);
 193                                         return -EIO;
 194                                 }
 195                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 196                                 if ((intr & ONENAND_INT_MASTER) == 0)
 197                                         wait_warn("timeout", state, ctrl, intr);
 198                         }
 199                 }
 200         } else {
 201                 int retry_cnt = 0;
 202
 203                 /* Turn interrupts off */
 204                 syscfg = read_reg(c, ONENAND_REG_SYS_CFG1);
 205                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 206                 write_reg(c, syscfg, ONENAND_REG_SYS_CFG1);
 207
 208                 timeout = jiffies + msecs_to_jiffies(20);
 209                 while (1) {
 210                         if (time_before(jiffies, timeout)) {
 211                                 intr = read_reg(c, ONENAND_REG_INTERRUPT);
 212                                 if (intr & ONENAND_INT_MASTER)
 213                                         break;
 214                         } else {
 215                                 /* Timeout after 20ms */
 216                                 ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 217                                 if (ctrl & ONENAND_CTRL_ONGO) {
 218                                         /*
 219                                          * The operation seems to be still going
 220                                          * so give it some more time.
 221                                          */
 222                                         retry_cnt += 1;
 223                                         if (retry_cnt < 3) {
 224                                                 timeout = jiffies +
 225                                                           msecs_to_jiffies(20);
 226                                                 continue;
 227                                         }
 228                                 }
 229                                 break;
 230                         }
 231                 }
 232         }
 233
 234         intr = read_reg(c, ONENAND_REG_INTERRUPT);
 235         ctrl = read_reg(c, ONENAND_REG_CTRL_STATUS);
 236
 237         if (intr & ONENAND_INT_READ) {
 238                 int ecc = read_reg(c, ONENAND_REG_ECC_STATUS);
 239
 240                 if (ecc) {
 241                         unsigned int addr1, addr8;
 242
 243                         addr1 = read_reg(c, ONENAND_REG_START_ADDRESS1);
 244                         addr8 = read_reg(c, ONENAND_REG_START_ADDRESS8);
 245                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 246                                 printk(KERN_ERR "onenand_wait: ECC error = "
 247                                        "0x%04x, addr1 %#x, addr8 %#x\n",
 248                                        ecc, addr1, addr8);
 249                                 mtd->ecc_stats.failed++;
 250                                 return -EBADMSG;
 251                         } else if (ecc & ONENAND_ECC_1BIT_ALL) {
 252                                 printk(KERN_NOTICE "onenand_wait: correctable "
 253                                        "ECC error = 0x%04x, addr1 %#x, "
 254                                        "addr8 %#x\n", ecc, addr1, addr8);
 255                                 mtd->ecc_stats.corrected++;
 256                         }
 257                 }
 258         } else if (state == FL_READING) {
 259                 wait_err("timeout", state, ctrl, intr);
 260                 return -EIO;
 261         }
 262
 263         if (ctrl & ONENAND_CTRL_ERROR) {
 264                 wait_err("controller error", state, ctrl, intr);
 265                 if (ctrl & ONENAND_CTRL_LOCK)
 266                         printk(KERN_ERR "onenand_wait: "
 267                                         "Device is write protected!!!\n");
 268                 return -EIO;
 269         }
 270
 271         ctrl_mask = 0xFE9F;
 272         if (this->ongoing)
 273                 ctrl_mask &= ~0x8000;
 274
 275         if (ctrl & ctrl_mask)
 276                 wait_warn("unexpected controller status", state, ctrl, intr);
 277
 278         return 0;
 279 }
 280
 281 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 282 {
 283         struct onenand_chip *this = mtd->priv;
 284
 285         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 286                 if (area == ONENAND_DATARAM)
 287                         return this->writesize;
 288                 if (area == ONENAND_SPARERAM)
 289                         return mtd->oobsize;
 290         }
 291
 292         return 0;
 293 }
 294
 295 #if defined(CONFIG_ARCH_OMAP3) || defined(MULTI_OMAP2)
 296
 297 static int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 298                                         unsigned char *buffer, int offset,
 299                                         size_t count)
 300 {
 301         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 302         struct onenand_chip *this = mtd->priv;
 303         dma_addr_t dma_src, dma_dst;
 304         int bram_offset;
 305         unsigned long timeout;
 306         void *buf = (void *)buffer;
 307         size_t xtra;
 308         volatile unsigned *done;
 309
 310         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 311         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 312                 goto out_copy;
 313
 314         /* panic_write() may be in an interrupt context */
 315         if (in_interrupt() || oops_in_progress)
 316                 goto out_copy;
 317
 318         if (buf >= high_memory) {
 319                 struct page *p1;
 320
 321                 if (((size_t)buf & PAGE_MASK) !=
 322                     ((size_t)(buf + count - 1) & PAGE_MASK))
 323                         goto out_copy;
 324                 p1 = vmalloc_to_page(buf);
 325                 if (!p1)
 326                         goto out_copy;
 327                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 328         }
 329
 330         xtra = count & 3;
 331         if (xtra) {
 332                 count -= xtra;
 333                 memcpy(buf + count, this->base + bram_offset + count, xtra);
 334         }
 335
 336         dma_src = c->phys_base + bram_offset;
 337         dma_dst = dma_map_single(&c->pdev->dev, buf, count, DMA_FROM_DEVICE);
 338         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 339                 dev_err(&c->pdev->dev,
 340                         "Couldn't DMA map a %d byte buffer\n",
 341                         count);
 342                 goto out_copy;
 343         }
 344
 345         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 346                                      count >> 2, 1, 0, 0, 0);
 347         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 348                                 dma_src, 0, 0);
 349         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 350                                  dma_dst, 0, 0);
 351
 352         INIT_COMPLETION(c->dma_done);
 353         omap_start_dma(c->dma_channel);
 354
 355         timeout = jiffies + msecs_to_jiffies(20);
 356         done = &c->dma_done.done;
 357         while (time_before(jiffies, timeout))
 358                 if (*done)
 359                         break;
 360
 361         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 362
 363         if (!*done) {
 364                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 365                 goto out_copy;
 366         }
 367
 368         return 0;
 369
 370 out_copy:
 371         memcpy(buf, this->base + bram_offset, count);
 372         return 0;
 373 }
 374
 375 static int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 376                                          const unsigned char *buffer,
 377                                          int offset, size_t count)
 378 {
 379         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 380         struct onenand_chip *this = mtd->priv;
 381         dma_addr_t dma_src, dma_dst;
 382         int bram_offset;
 383         unsigned long timeout;
 384         void *buf = (void *)buffer;
 385         volatile unsigned *done;
 386
 387         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 388         if (bram_offset & 3 || (size_t)buf & 3 || count < 384)
 389                 goto out_copy;
 390
 391         /* panic_write() may be in an interrupt context */
 392         if (in_interrupt() || oops_in_progress)
 393                 goto out_copy;
 394
 395         if (buf >= high_memory) {
 396                 struct page *p1;
 397
 398                 if (((size_t)buf & PAGE_MASK) !=
 399                     ((size_t)(buf + count - 1) & PAGE_MASK))
 400                         goto out_copy;
 401                 p1 = vmalloc_to_page(buf);
 402                 if (!p1)
 403                         goto out_copy;
 404                 buf = page_address(p1) + ((size_t)buf & ~PAGE_MASK);
 405         }
 406
 407         dma_src = dma_map_single(&c->pdev->dev, buf, count, DMA_TO_DEVICE);
 408         dma_dst = c->phys_base + bram_offset;
 409         if (dma_mapping_error(&c->pdev->dev, dma_src)) {
 410                 dev_err(&c->pdev->dev,
 411                         "Couldn't DMA map a %d byte buffer\n",
 412                         count);
 413                 return -1;
 414         }
 415
 416         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 417                                      count >> 2, 1, 0, 0, 0);
 418         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 419                                 dma_src, 0, 0);
 420         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 421                                  dma_dst, 0, 0);
 422
 423         INIT_COMPLETION(c->dma_done);
 424         omap_start_dma(c->dma_channel);
 425
 426         timeout = jiffies + msecs_to_jiffies(20);
 427         done = &c->dma_done.done;
 428         while (time_before(jiffies, timeout))
 429                 if (*done)
 430                         break;
 431
 432         dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 433
 434         if (!*done) {
 435                 dev_err(&c->pdev->dev, "timeout waiting for DMA\n");
 436                 goto out_copy;
 437         }
 438
 439         return 0;
 440
 441 out_copy:
 442         memcpy(this->base + bram_offset, buf, count);
 443         return 0;
 444 }
 445
 446 #else
 447
 448 int omap3_onenand_read_bufferram(struct mtd_info *mtd, int area,
 449                                  unsigned char *buffer, int offset,
 450                                  size_t count);
 451
 452 int omap3_onenand_write_bufferram(struct mtd_info *mtd, int area,
 453                                   const unsigned char *buffer,
 454                                   int offset, size_t count);
 455
 456 #endif
 457
 458 #if defined(CONFIG_ARCH_OMAP2) || defined(MULTI_OMAP2)
 459
 460 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 461                                         unsigned char *buffer, int offset,
 462                                         size_t count)
 463 {
 464         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 465         struct onenand_chip *this = mtd->priv;
 466         dma_addr_t dma_src, dma_dst;
 467         int bram_offset;
 468
 469         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 470         /* DMA is not used.  Revisit PM requirements before enabling it. */
 471         if (1 || (c->dma_channel < 0) ||
 472             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
 473             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
 474                 memcpy(buffer, (__force void *)(this->base + bram_offset),
 475                        count);
 476                 return 0;
 477         }
 478
 479         dma_src = c->phys_base + bram_offset;
 480         dma_dst = dma_map_single(&c->pdev->dev, buffer, count,
 481                                  DMA_FROM_DEVICE);
 482         if (dma_mapping_error(&c->pdev->dev, dma_dst)) {
 483                 dev_err(&c->pdev->dev,
 484                         "Couldn't DMA map a %d byte buffer\n",
 485                         count);
 486                 return -1;
 487         }
 488
 489         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 490                                      count / 4, 1, 0, 0, 0);
 491         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 492                                 dma_src, 0, 0);
 493         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 494                                  dma_dst, 0, 0);
 495
 496         INIT_COMPLETION(c->dma_done);
 497         omap_start_dma(c->dma_channel);
 498         wait_for_completion(&c->dma_done);
 499
 500         dma_unmap_single(&c->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 501
 502         return 0;
 503 }
 504
 505 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 506                                          const unsigned char *buffer,
 507                                          int offset, size_t count)
 508 {
 509         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 510         struct onenand_chip *this = mtd->priv;
 511         dma_addr_t dma_src, dma_dst;
 512         int bram_offset;
 513
 514         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 515         /* DMA is not used.  Revisit PM requirements before enabling it. */
 516         if (1 || (c->dma_channel < 0) ||
 517             ((void *) buffer >= (void *) high_memory) || (bram_offset & 3) ||
 518             (((unsigned int) buffer) & 3) || (count < 1024) || (count & 3)) {
 519                 memcpy((__force void *)(this->base + bram_offset), buffer,
 520                        count);
 521                 return 0;
 522         }
 523
 524         dma_src = dma_map_single(&c->pdev->dev, (void *) buffer, count,
 525                                  DMA_TO_DEVICE);
 526         dma_dst = c->phys_base + bram_offset;
 527         if (dma_mapping_error(&c->pdev->dev, dma_src)) {
 528                 dev_err(&c->pdev->dev,
 529                         "Couldn't DMA map a %d byte buffer\n",
 530                         count);
 531                 return -1;
 532         }
 533
 534         omap_set_dma_transfer_params(c->dma_channel, OMAP_DMA_DATA_TYPE_S16,
 535                                      count / 2, 1, 0, 0, 0);
 536         omap_set_dma_src_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 537                                 dma_src, 0, 0);
 538         omap_set_dma_dest_params(c->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 539                                  dma_dst, 0, 0);
 540
 541         INIT_COMPLETION(c->dma_done);
 542         omap_start_dma(c->dma_channel);
 543         wait_for_completion(&c->dma_done);
 544
 545         dma_unmap_single(&c->pdev->dev, dma_src, count, DMA_TO_DEVICE);
 546
 547         return 0;
 548 }
 549
 550 #else
 551
 552 int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 553                                  unsigned char *buffer, int offset,
 554                                  size_t count);
 555
 556 int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 557                                   const unsigned char *buffer,
 558                                   int offset, size_t count);
 559
 560 #endif
 561
 562 static struct platform_driver omap2_onenand_driver;
 563
 564 static int __adjust_timing(struct device *dev, void *data)
 565 {
 566         int ret = 0;
 567         struct omap2_onenand *c;
 568
 569         c = dev_get_drvdata(dev);
 570
 571         BUG_ON(c->setup == NULL);
 572
 573         /* DMA is not in use so this is all that is needed */
 574         /* Revisit for OMAP3! */
 575         ret = c->setup(c->onenand.base, &c->freq);
 576
 577         return ret;
 578 }
 579
 580 int omap2_onenand_rephase(void)
 581 {
 582         return driver_for_each_device(&omap2_onenand_driver.driver, NULL,
 583                                       NULL, __adjust_timing);
 584 }
 585
 586 static void omap2_onenand_shutdown(struct platform_device *pdev)
 587 {
 588         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 589
 590         /* With certain content in the buffer RAM, the OMAP boot ROM code
 591          * can recognize the flash chip incorrectly. Zero it out before
 592          * soft reset.
 593          */
 594         memset((__force void *)c->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 595 }
 596
 597 static int omap2_onenand_enable(struct mtd_info *mtd)
 598 {
 599         int ret;
 600         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 601
 602         ret = regulator_enable(c->regulator);
 603         if (ret != 0)
 604                 dev_err(&c->pdev->dev, "can't enable regulator\n");
 605
 606         return ret;
 607 }
 608
 609 static int omap2_onenand_disable(struct mtd_info *mtd)
 610 {
 611         int ret;
 612         struct omap2_onenand *c = container_of(mtd, struct omap2_onenand, mtd);
 613
 614         ret = regulator_disable(c->regulator);
 615         if (ret != 0)
 616                 dev_err(&c->pdev->dev, "can't disable regulator\n");
 617
 618         return ret;
 619 }
 620
 621 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
 622 {
 623         struct omap_onenand_platform_data *pdata;
 624         struct omap2_onenand *c;
 625         struct onenand_chip *this;
 626         int r;
 627
 628         pdata = pdev->dev.platform_data;
 629         if (pdata == NULL) {
 630                 dev_err(&pdev->dev, "platform data missing\n");
 631                 return -ENODEV;
 632         }
 633
 634         c = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 635         if (!c)
 636                 return -ENOMEM;
 637
 638         init_completion(&c->irq_done);
 639         init_completion(&c->dma_done);
 640         c->gpmc_cs = pdata->cs;
 641         c->gpio_irq = pdata->gpio_irq;
 642         c->dma_channel = pdata->dma_channel;
 643         if (c->dma_channel < 0) {
 644                 /* if -1, don't use DMA */
 645                 c->gpio_irq = 0;
 646         }
 647
 648         r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base);
 649         if (r < 0) {
 650                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 651                 goto err_kfree;
 652         }
 653
 654         if (request_mem_region(c->phys_base, ONENAND_IO_SIZE,
 655                                pdev->dev.driver->name) == NULL) {
 656                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, "
 657                         "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE);
 658                 r = -EBUSY;
 659                 goto err_free_cs;
 660         }
 661         c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE);
 662         if (c->onenand.base == NULL) {
 663                 r = -ENOMEM;
 664                 goto err_release_mem_region;
 665         }
 666
 667         if (pdata->onenand_setup != NULL) {
 668                 r = pdata->onenand_setup(c->onenand.base, &c->freq);
 669                 if (r < 0) {
 670                         dev_err(&pdev->dev, "Onenand platform setup failed: "
 671                                 "%d\n", r);
 672                         goto err_iounmap;
 673                 }
 674                 c->setup = pdata->onenand_setup;
 675         }
 676
 677         if (c->gpio_irq) {
 678                 if ((r = gpio_request(c->gpio_irq, "OneNAND irq")) < 0) {
 679                         dev_err(&pdev->dev,  "Failed to request GPIO%d for "
 680                                 "OneNAND\n", c->gpio_irq);
 681                         goto err_iounmap;
 682         }
 683         gpio_direction_input(c->gpio_irq);
 684
 685         if ((r = request_irq(gpio_to_irq(c->gpio_irq),
 686                              omap2_onenand_interrupt, IRQF_TRIGGER_RISING,
 687                              pdev->dev.driver->name, c)) < 0)
 688                 goto err_release_gpio;
 689         }
 690
 691         if (c->dma_channel >= 0) {
 692                 r = omap_request_dma(0, pdev->dev.driver->name,
 693                                      omap2_onenand_dma_cb, (void *) c,
 694                                      &c->dma_channel);
 695                 if (r == 0) {
 696                         omap_set_dma_write_mode(c->dma_channel,
 697                                                 OMAP_DMA_WRITE_NON_POSTED);
 698                         omap_set_dma_src_data_pack(c->dma_channel, 1);
 699                         omap_set_dma_src_burst_mode(c->dma_channel,
 700                                                     OMAP_DMA_DATA_BURST_8);
 701                         omap_set_dma_dest_data_pack(c->dma_channel, 1);
 702                         omap_set_dma_dest_burst_mode(c->dma_channel,
 703                                                      OMAP_DMA_DATA_BURST_8);
 704                 } else {
 705                         dev_info(&pdev->dev,
 706                                  "failed to allocate DMA for OneNAND, "
 707                                  "using PIO instead\n");
 708                         c->dma_channel = -1;
 709                 }
 710         }
 711
 712         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual "
 713                  "base %p, freq %d MHz\n", c->gpmc_cs, c->phys_base,
 714                  c->onenand.base, c->freq);
 715
 716         c->pdev = pdev;
 717         c->mtd.name = dev_name(&pdev->dev);
 718         c->mtd.priv = &c->onenand;
 719         c->mtd.owner = THIS_MODULE;
 720
 721         c->mtd.dev.parent = &pdev->dev;
 722
 723         this = &c->onenand;
 724         if (c->dma_channel >= 0) {
 725                 this->wait = omap2_onenand_wait;
 726                 if (cpu_is_omap34xx()) {
 727                         this->read_bufferram = omap3_onenand_read_bufferram;
 728                         this->write_bufferram = omap3_onenand_write_bufferram;
 729                 } else {
 730                         this->read_bufferram = omap2_onenand_read_bufferram;
 731                         this->write_bufferram = omap2_onenand_write_bufferram;
 732                 }
 733         }
 734
 735         if (pdata->regulator_can_sleep) {
 736                 c->regulator = regulator_get(&pdev->dev, "vonenand");
 737                 if (IS_ERR(c->regulator)) {
 738                         dev_err(&pdev->dev,  "Failed to get regulator\n");
 739                         r = PTR_ERR(c->regulator);
 740                         goto err_release_dma;
 741                 }
 742                 c->onenand.enable = omap2_onenand_enable;
 743                 c->onenand.disable = omap2_onenand_disable;
 744         }
 745
 746         if (pdata->skip_initial_unlocking)
 747                 this->options |= ONENAND_SKIP_INITIAL_UNLOCKING;
 748
 749         if ((r = onenand_scan(&c->mtd, 1)) < 0)
 750                 goto err_release_regulator;
 751
 752         r = mtd_device_parse_register(&c->mtd, NULL, NULL,
 753                                       pdata ? pdata->parts : NULL,
 754                                       pdata ? pdata->nr_parts : 0);
 755         if (r)
 756                 goto err_release_onenand;
 757
 758         platform_set_drvdata(pdev, c);
 759
 760         return 0;
 761
 762 err_release_onenand:
 763         onenand_release(&c->mtd);
 764 err_release_regulator:
 765         regulator_put(c->regulator);
 766 err_release_dma:
 767         if (c->dma_channel != -1)
 768                 omap_free_dma(c->dma_channel);
 769         if (c->gpio_irq)
 770                 free_irq(gpio_to_irq(c->gpio_irq), c);
 771 err_release_gpio:
 772         if (c->gpio_irq)
 773                 gpio_free(c->gpio_irq);
 774 err_iounmap:
 775         iounmap(c->onenand.base);
 776 err_release_mem_region:
 777         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
 778 err_free_cs:
 779         gpmc_cs_free(c->gpmc_cs);
 780 err_kfree:
 781         kfree(c);
 782
 783         return r;
 784 }
 785
 786 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
 787 {
 788         struct omap2_onenand *c = dev_get_drvdata(&pdev->dev);
 789
 790         onenand_release(&c->mtd);
 791         regulator_put(c->regulator);
 792         if (c->dma_channel != -1)
 793                 omap_free_dma(c->dma_channel);
 794         omap2_onenand_shutdown(pdev);
 795         platform_set_drvdata(pdev, NULL);
 796         if (c->gpio_irq) {
 797                 free_irq(gpio_to_irq(c->gpio_irq), c);
 798                 gpio_free(c->gpio_irq);
 799         }
 800         iounmap(c->onenand.base);
 801         release_mem_region(c->phys_base, ONENAND_IO_SIZE);
 802         gpmc_cs_free(c->gpmc_cs);
 803         kfree(c);
 804
 805         return 0;
 806 }
 807
 808 static struct platform_driver omap2_onenand_driver = {
 809         .probe          = omap2_onenand_probe,
 810         .remove         = __devexit_p(omap2_onenand_remove),
 811         .shutdown       = omap2_onenand_shutdown,
 812         .driver         = {
 813                 .name   = DRIVER_NAME,
 814                 .owner  = THIS_MODULE,
 815         },
 816 };
 817
 818 static int __init omap2_onenand_init(void)
 819 {
 820         printk(KERN_INFO "OneNAND driver initializing\n");
 821         return platform_driver_register(&omap2_onenand_driver);
 822 }
 823
 824 static void __exit omap2_onenand_exit(void)
 825 {
 826         platform_driver_unregister(&omap2_onenand_driver);
 827 }
 828
 829 module_init(omap2_onenand_init);
 830 module_exit(omap2_onenand_exit);
 831
 832 MODULE_ALIAS("platform:" DRIVER_NAME);
 833 MODULE_LICENSE("GPL");
 834 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 835 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2 / OMAP3");