1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Panasonic Corporation
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
12 #include <asm/cache.h>
13 #include <asm/dma-mapping.h>
14 #include <dm/device_compat.h>
15 #include <dm/devres.h>
16 #include <linux/bitfield.h>
17 #include <linux/delay.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/rawnand.h>
28 #define DENALI_NAND_NAME "denali-nand"
30 /* for Indexed Addressing */
31 #define DENALI_INDEXED_CTRL 0x00
32 #define DENALI_INDEXED_DATA 0x10
34 #define DENALI_MAP00 (0 << 26) /* direct access to buffer */
35 #define DENALI_MAP01 (1 << 26) /* read/write pages in PIO */
36 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
37 #define DENALI_MAP11 (3 << 26) /* direct controller access */
39 /* MAP11 access cycle type */
40 #define DENALI_MAP11_CMD ((DENALI_MAP11) | 0) /* command cycle */
41 #define DENALI_MAP11_ADDR ((DENALI_MAP11) | 1) /* address cycle */
42 #define DENALI_MAP11_DATA ((DENALI_MAP11) | 2) /* data cycle */
45 #define DENALI_ERASE 0x01
47 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
49 #define DENALI_INVALID_BANK -1
50 #define DENALI_NR_BANKS 4
52 static inline struct denali_nand_info *mtd_to_denali(struct mtd_info *mtd)
54 return container_of(mtd_to_nand(mtd), struct denali_nand_info, nand);
58 * Direct Addressing - the slave address forms the control information (command
59 * type, bank, block, and page address). The slave data is the actual data to
60 * be transferred. This mode requires 28 bits of address region allocated.
62 static u32 denali_direct_read(struct denali_nand_info *denali, u32 addr)
64 return ioread32(denali->host + addr);
67 static void denali_direct_write(struct denali_nand_info *denali, u32 addr,
70 iowrite32(data, denali->host + addr);
74 * Indexed Addressing - address translation module intervenes in passing the
75 * control information. This mode reduces the required address range. The
76 * control information and transferred data are latched by the registers in
77 * the translation module.
79 static u32 denali_indexed_read(struct denali_nand_info *denali, u32 addr)
81 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
82 return ioread32(denali->host + DENALI_INDEXED_DATA);
85 static void denali_indexed_write(struct denali_nand_info *denali, u32 addr,
88 iowrite32(addr, denali->host + DENALI_INDEXED_CTRL);
89 iowrite32(data, denali->host + DENALI_INDEXED_DATA);
93 * Use the configuration feature register to determine the maximum number of
94 * banks that the hardware supports.
96 static void denali_detect_max_banks(struct denali_nand_info *denali)
98 uint32_t features = ioread32(denali->reg + FEATURES);
100 denali->max_banks = 1 << FIELD_GET(FEATURES__N_BANKS, features);
102 /* the encoding changed from rev 5.0 to 5.1 */
103 if (denali->revision < 0x0501)
104 denali->max_banks <<= 1;
107 static void __maybe_unused denali_enable_irq(struct denali_nand_info *denali)
111 for (i = 0; i < DENALI_NR_BANKS; i++)
112 iowrite32(U32_MAX, denali->reg + INTR_EN(i));
113 iowrite32(GLOBAL_INT_EN_FLAG, denali->reg + GLOBAL_INT_ENABLE);
116 static void __maybe_unused denali_disable_irq(struct denali_nand_info *denali)
120 for (i = 0; i < DENALI_NR_BANKS; i++)
121 iowrite32(0, denali->reg + INTR_EN(i));
122 iowrite32(0, denali->reg + GLOBAL_INT_ENABLE);
125 static void denali_clear_irq(struct denali_nand_info *denali,
126 int bank, uint32_t irq_status)
128 /* write one to clear bits */
129 iowrite32(irq_status, denali->reg + INTR_STATUS(bank));
132 static void denali_clear_irq_all(struct denali_nand_info *denali)
136 for (i = 0; i < DENALI_NR_BANKS; i++)
137 denali_clear_irq(denali, i, U32_MAX);
140 static void __denali_check_irq(struct denali_nand_info *denali)
145 for (i = 0; i < DENALI_NR_BANKS; i++) {
146 irq_status = ioread32(denali->reg + INTR_STATUS(i));
147 denali_clear_irq(denali, i, irq_status);
149 if (i != denali->active_bank)
152 denali->irq_status |= irq_status;
156 static void denali_reset_irq(struct denali_nand_info *denali)
158 denali->irq_status = 0;
159 denali->irq_mask = 0;
162 static uint32_t denali_wait_for_irq(struct denali_nand_info *denali,
165 unsigned long time_left = 1000000;
168 __denali_check_irq(denali);
170 if (irq_mask & denali->irq_status)
171 return denali->irq_status;
177 dev_err(denali->dev, "timeout while waiting for irq 0x%x\n",
182 return denali->irq_status;
185 static uint32_t denali_check_irq(struct denali_nand_info *denali)
187 __denali_check_irq(denali);
189 return denali->irq_status;
192 static void denali_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
194 struct denali_nand_info *denali = mtd_to_denali(mtd);
195 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
198 for (i = 0; i < len; i++)
199 buf[i] = denali->host_read(denali, addr);
202 static void denali_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
204 struct denali_nand_info *denali = mtd_to_denali(mtd);
205 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
208 for (i = 0; i < len; i++)
209 denali->host_write(denali, addr, buf[i]);
212 static void denali_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
214 struct denali_nand_info *denali = mtd_to_denali(mtd);
215 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
216 uint16_t *buf16 = (uint16_t *)buf;
219 for (i = 0; i < len / 2; i++)
220 buf16[i] = denali->host_read(denali, addr);
223 static void denali_write_buf16(struct mtd_info *mtd, const uint8_t *buf,
226 struct denali_nand_info *denali = mtd_to_denali(mtd);
227 u32 addr = DENALI_MAP11_DATA | DENALI_BANK(denali);
228 const uint16_t *buf16 = (const uint16_t *)buf;
231 for (i = 0; i < len / 2; i++)
232 denali->host_write(denali, addr, buf16[i]);
235 static uint8_t denali_read_byte(struct mtd_info *mtd)
239 denali_read_buf(mtd, &byte, 1);
244 static void denali_write_byte(struct mtd_info *mtd, uint8_t byte)
246 denali_write_buf(mtd, &byte, 1);
249 static uint16_t denali_read_word(struct mtd_info *mtd)
253 denali_read_buf16(mtd, (uint8_t *)&word, 2);
258 static void denali_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
260 struct denali_nand_info *denali = mtd_to_denali(mtd);
264 type = DENALI_MAP11_CMD;
265 else if (ctrl & NAND_ALE)
266 type = DENALI_MAP11_ADDR;
271 * Some commands are followed by chip->dev_ready or chip->waitfunc.
272 * irq_status must be cleared here to catch the R/B# interrupt later.
274 if (ctrl & NAND_CTRL_CHANGE)
275 denali_reset_irq(denali);
277 denali->host_write(denali, DENALI_BANK(denali) | type, dat);
280 static int denali_dev_ready(struct mtd_info *mtd)
282 struct denali_nand_info *denali = mtd_to_denali(mtd);
284 return !!(denali_check_irq(denali) & INTR__INT_ACT);
287 static int denali_check_erased_page(struct mtd_info *mtd,
288 struct nand_chip *chip, uint8_t *buf,
289 unsigned long uncor_ecc_flags,
290 unsigned int max_bitflips)
292 uint8_t *ecc_code = chip->buffers->ecccode;
293 int ecc_steps = chip->ecc.steps;
294 int ecc_size = chip->ecc.size;
295 int ecc_bytes = chip->ecc.bytes;
298 ret = mtd_ooblayout_get_eccbytes(mtd, ecc_code, chip->oob_poi, 0,
303 for (i = 0; i < ecc_steps; i++) {
304 if (!(uncor_ecc_flags & BIT(i)))
307 stat = nand_check_erased_ecc_chunk(buf, ecc_size,
312 mtd->ecc_stats.failed++;
314 mtd->ecc_stats.corrected += stat;
315 max_bitflips = max_t(unsigned int, max_bitflips, stat);
319 ecc_code += ecc_bytes;
325 static int denali_hw_ecc_fixup(struct mtd_info *mtd,
326 struct denali_nand_info *denali,
327 unsigned long *uncor_ecc_flags)
329 struct nand_chip *chip = mtd_to_nand(mtd);
330 int bank = denali->active_bank;
332 unsigned int max_bitflips;
334 ecc_cor = ioread32(denali->reg + ECC_COR_INFO(bank));
335 ecc_cor >>= ECC_COR_INFO__SHIFT(bank);
337 if (ecc_cor & ECC_COR_INFO__UNCOR_ERR) {
339 * This flag is set when uncorrectable error occurs at least in
340 * one ECC sector. We can not know "how many sectors", or
341 * "which sector(s)". We need erase-page check for all sectors.
343 *uncor_ecc_flags = GENMASK(chip->ecc.steps - 1, 0);
347 max_bitflips = FIELD_GET(ECC_COR_INFO__MAX_ERRORS, ecc_cor);
350 * The register holds the maximum of per-sector corrected bitflips.
351 * This is suitable for the return value of the ->read_page() callback.
352 * Unfortunately, we can not know the total number of corrected bits in
353 * the page. Increase the stats by max_bitflips. (compromised solution)
355 mtd->ecc_stats.corrected += max_bitflips;
360 static int denali_sw_ecc_fixup(struct mtd_info *mtd,
361 struct denali_nand_info *denali,
362 unsigned long *uncor_ecc_flags, uint8_t *buf)
364 unsigned int ecc_size = denali->nand.ecc.size;
365 unsigned int bitflips = 0;
366 unsigned int max_bitflips = 0;
367 uint32_t err_addr, err_cor_info;
368 unsigned int err_byte, err_sector, err_device;
369 uint8_t err_cor_value;
370 unsigned int prev_sector = 0;
373 denali_reset_irq(denali);
376 err_addr = ioread32(denali->reg + ECC_ERROR_ADDRESS);
377 err_sector = FIELD_GET(ECC_ERROR_ADDRESS__SECTOR, err_addr);
378 err_byte = FIELD_GET(ECC_ERROR_ADDRESS__OFFSET, err_addr);
380 err_cor_info = ioread32(denali->reg + ERR_CORRECTION_INFO);
381 err_cor_value = FIELD_GET(ERR_CORRECTION_INFO__BYTE,
383 err_device = FIELD_GET(ERR_CORRECTION_INFO__DEVICE,
386 /* reset the bitflip counter when crossing ECC sector */
387 if (err_sector != prev_sector)
390 if (err_cor_info & ERR_CORRECTION_INFO__UNCOR) {
392 * Check later if this is a real ECC error, or
395 *uncor_ecc_flags |= BIT(err_sector);
396 } else if (err_byte < ecc_size) {
398 * If err_byte is larger than ecc_size, means error
399 * happened in OOB, so we ignore it. It's no need for
400 * us to correct it err_device is represented the NAND
401 * error bits are happened in if there are more than
402 * one NAND connected.
405 unsigned int flips_in_byte;
407 offset = (err_sector * ecc_size + err_byte) *
408 denali->devs_per_cs + err_device;
410 /* correct the ECC error */
411 flips_in_byte = hweight8(buf[offset] ^ err_cor_value);
412 buf[offset] ^= err_cor_value;
413 mtd->ecc_stats.corrected += flips_in_byte;
414 bitflips += flips_in_byte;
416 max_bitflips = max(max_bitflips, bitflips);
419 prev_sector = err_sector;
420 } while (!(err_cor_info & ERR_CORRECTION_INFO__LAST_ERR));
423 * Once handle all ECC errors, controller will trigger an
424 * ECC_TRANSACTION_DONE interrupt.
426 irq_status = denali_wait_for_irq(denali, INTR__ECC_TRANSACTION_DONE);
427 if (!(irq_status & INTR__ECC_TRANSACTION_DONE))
433 static void denali_setup_dma64(struct denali_nand_info *denali,
434 dma_addr_t dma_addr, int page, int write)
437 const int page_count = 1;
439 mode = DENALI_MAP10 | DENALI_BANK(denali) | page;
441 /* DMA is a three step process */
444 * 1. setup transfer type, interrupt when complete,
445 * burst len = 64 bytes, the number of pages
447 denali->host_write(denali, mode,
448 0x01002000 | (64 << 16) | (write << 8) | page_count);
450 /* 2. set memory low address */
451 denali->host_write(denali, mode, lower_32_bits(dma_addr));
453 /* 3. set memory high address */
454 denali->host_write(denali, mode, upper_32_bits(dma_addr));
457 static void denali_setup_dma32(struct denali_nand_info *denali,
458 dma_addr_t dma_addr, int page, int write)
461 const int page_count = 1;
463 mode = DENALI_MAP10 | DENALI_BANK(denali);
465 /* DMA is a four step process */
467 /* 1. setup transfer type and # of pages */
468 denali->host_write(denali, mode | page,
469 0x2000 | (write << 8) | page_count);
471 /* 2. set memory high address bits 23:8 */
472 denali->host_write(denali, mode | ((dma_addr >> 16) << 8), 0x2200);
474 /* 3. set memory low address bits 23:8 */
475 denali->host_write(denali, mode | ((dma_addr & 0xffff) << 8), 0x2300);
477 /* 4. interrupt when complete, burst len = 64 bytes */
478 denali->host_write(denali, mode | 0x14000, 0x2400);
481 static int denali_pio_read(struct denali_nand_info *denali, void *buf,
482 size_t size, int page, int raw)
484 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
485 uint32_t *buf32 = (uint32_t *)buf;
486 uint32_t irq_status, ecc_err_mask;
489 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
490 ecc_err_mask = INTR__ECC_UNCOR_ERR;
492 ecc_err_mask = INTR__ECC_ERR;
494 denali_reset_irq(denali);
496 for (i = 0; i < size / 4; i++)
497 *buf32++ = denali->host_read(denali, addr);
499 irq_status = denali_wait_for_irq(denali, INTR__PAGE_XFER_INC);
500 if (!(irq_status & INTR__PAGE_XFER_INC))
503 if (irq_status & INTR__ERASED_PAGE)
504 memset(buf, 0xff, size);
506 return irq_status & ecc_err_mask ? -EBADMSG : 0;
509 static int denali_pio_write(struct denali_nand_info *denali,
510 const void *buf, size_t size, int page, int raw)
512 u32 addr = DENALI_MAP01 | DENALI_BANK(denali) | page;
513 const uint32_t *buf32 = (uint32_t *)buf;
517 denali_reset_irq(denali);
519 for (i = 0; i < size / 4; i++)
520 denali->host_write(denali, addr, *buf32++);
522 irq_status = denali_wait_for_irq(denali,
523 INTR__PROGRAM_COMP | INTR__PROGRAM_FAIL);
524 if (!(irq_status & INTR__PROGRAM_COMP))
530 static int denali_pio_xfer(struct denali_nand_info *denali, void *buf,
531 size_t size, int page, int raw, int write)
534 return denali_pio_write(denali, buf, size, page, raw);
536 return denali_pio_read(denali, buf, size, page, raw);
539 static int denali_dma_xfer(struct denali_nand_info *denali, void *buf,
540 size_t size, int page, int raw, int write)
543 uint32_t irq_mask, irq_status, ecc_err_mask;
544 enum dma_data_direction dir = write ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
547 dma_addr = dma_map_single(buf, size, dir);
548 if (dma_mapping_error(denali->dev, dma_addr)) {
549 dev_dbg(denali->dev, "Failed to DMA-map buffer. Trying PIO.\n");
550 return denali_pio_xfer(denali, buf, size, page, raw, write);
555 * INTR__PROGRAM_COMP is never asserted for the DMA transfer.
556 * We can use INTR__DMA_CMD_COMP instead. This flag is asserted
557 * when the page program is completed.
559 irq_mask = INTR__DMA_CMD_COMP | INTR__PROGRAM_FAIL;
561 } else if (denali->caps & DENALI_CAP_HW_ECC_FIXUP) {
562 irq_mask = INTR__DMA_CMD_COMP;
563 ecc_err_mask = INTR__ECC_UNCOR_ERR;
565 irq_mask = INTR__DMA_CMD_COMP;
566 ecc_err_mask = INTR__ECC_ERR;
569 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
571 * The ->setup_dma() hook kicks DMA by using the data/command
572 * interface, which belongs to a different AXI port from the
573 * register interface. Read back the register to avoid a race.
575 ioread32(denali->reg + DMA_ENABLE);
577 denali_reset_irq(denali);
578 denali->setup_dma(denali, dma_addr, page, write);
580 irq_status = denali_wait_for_irq(denali, irq_mask);
581 if (!(irq_status & INTR__DMA_CMD_COMP))
583 else if (irq_status & ecc_err_mask)
586 iowrite32(0, denali->reg + DMA_ENABLE);
588 dma_unmap_single(dma_addr, size, dir);
590 if (irq_status & INTR__ERASED_PAGE)
591 memset(buf, 0xff, size);
596 static int denali_data_xfer(struct denali_nand_info *denali, void *buf,
597 size_t size, int page, int raw, int write)
599 iowrite32(raw ? 0 : ECC_ENABLE__FLAG, denali->reg + ECC_ENABLE);
600 iowrite32(raw ? TRANSFER_SPARE_REG__FLAG : 0,
601 denali->reg + TRANSFER_SPARE_REG);
603 if (denali->dma_avail)
604 return denali_dma_xfer(denali, buf, size, page, raw, write);
606 return denali_pio_xfer(denali, buf, size, page, raw, write);
609 static void denali_oob_xfer(struct mtd_info *mtd, struct nand_chip *chip,
612 struct denali_nand_info *denali = mtd_to_denali(mtd);
613 unsigned int start_cmd = write ? NAND_CMD_SEQIN : NAND_CMD_READ0;
614 unsigned int rnd_cmd = write ? NAND_CMD_RNDIN : NAND_CMD_RNDOUT;
615 int writesize = mtd->writesize;
616 int oobsize = mtd->oobsize;
617 uint8_t *bufpoi = chip->oob_poi;
618 int ecc_steps = chip->ecc.steps;
619 int ecc_size = chip->ecc.size;
620 int ecc_bytes = chip->ecc.bytes;
621 int oob_skip = denali->oob_skip_bytes;
622 size_t size = writesize + oobsize;
625 /* BBM at the beginning of the OOB area */
626 chip->cmdfunc(mtd, start_cmd, writesize, page);
628 chip->write_buf(mtd, bufpoi, oob_skip);
630 chip->read_buf(mtd, bufpoi, oob_skip);
634 for (i = 0; i < ecc_steps; i++) {
635 pos = ecc_size + i * (ecc_size + ecc_bytes);
638 if (pos >= writesize)
640 else if (pos + len > writesize)
641 len = writesize - pos;
643 chip->cmdfunc(mtd, rnd_cmd, pos, -1);
645 chip->write_buf(mtd, bufpoi, len);
647 chip->read_buf(mtd, bufpoi, len);
649 if (len < ecc_bytes) {
650 len = ecc_bytes - len;
651 chip->cmdfunc(mtd, rnd_cmd, writesize + oob_skip, -1);
653 chip->write_buf(mtd, bufpoi, len);
655 chip->read_buf(mtd, bufpoi, len);
661 len = oobsize - (bufpoi - chip->oob_poi);
662 chip->cmdfunc(mtd, rnd_cmd, size - len, -1);
664 chip->write_buf(mtd, bufpoi, len);
666 chip->read_buf(mtd, bufpoi, len);
669 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
670 uint8_t *buf, int oob_required, int page)
672 struct denali_nand_info *denali = mtd_to_denali(mtd);
673 int writesize = mtd->writesize;
674 int oobsize = mtd->oobsize;
675 int ecc_steps = chip->ecc.steps;
676 int ecc_size = chip->ecc.size;
677 int ecc_bytes = chip->ecc.bytes;
678 void *tmp_buf = denali->buf;
679 int oob_skip = denali->oob_skip_bytes;
680 size_t size = writesize + oobsize;
681 int ret, i, pos, len;
683 ret = denali_data_xfer(denali, tmp_buf, size, page, 1, 0);
687 /* Arrange the buffer for syndrome payload/ecc layout */
689 for (i = 0; i < ecc_steps; i++) {
690 pos = i * (ecc_size + ecc_bytes);
693 if (pos >= writesize)
695 else if (pos + len > writesize)
696 len = writesize - pos;
698 memcpy(buf, tmp_buf + pos, len);
700 if (len < ecc_size) {
701 len = ecc_size - len;
702 memcpy(buf, tmp_buf + writesize + oob_skip,
710 uint8_t *oob = chip->oob_poi;
712 /* BBM at the beginning of the OOB area */
713 memcpy(oob, tmp_buf + writesize, oob_skip);
717 for (i = 0; i < ecc_steps; i++) {
718 pos = ecc_size + i * (ecc_size + ecc_bytes);
721 if (pos >= writesize)
723 else if (pos + len > writesize)
724 len = writesize - pos;
726 memcpy(oob, tmp_buf + pos, len);
728 if (len < ecc_bytes) {
729 len = ecc_bytes - len;
730 memcpy(oob, tmp_buf + writesize + oob_skip,
737 len = oobsize - (oob - chip->oob_poi);
738 memcpy(oob, tmp_buf + size - len, len);
744 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
747 denali_oob_xfer(mtd, chip, page, 0);
752 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
755 struct denali_nand_info *denali = mtd_to_denali(mtd);
758 denali_reset_irq(denali);
760 denali_oob_xfer(mtd, chip, page, 1);
762 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
763 status = chip->waitfunc(mtd, chip);
765 return status & NAND_STATUS_FAIL ? -EIO : 0;
768 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
769 uint8_t *buf, int oob_required, int page)
771 struct denali_nand_info *denali = mtd_to_denali(mtd);
772 unsigned long uncor_ecc_flags = 0;
776 ret = denali_data_xfer(denali, buf, mtd->writesize, page, 0, 0);
777 if (ret && ret != -EBADMSG)
780 if (denali->caps & DENALI_CAP_HW_ECC_FIXUP)
781 stat = denali_hw_ecc_fixup(mtd, denali, &uncor_ecc_flags);
782 else if (ret == -EBADMSG)
783 stat = denali_sw_ecc_fixup(mtd, denali, &uncor_ecc_flags, buf);
788 if (uncor_ecc_flags) {
789 ret = denali_read_oob(mtd, chip, page);
793 stat = denali_check_erased_page(mtd, chip, buf,
794 uncor_ecc_flags, stat);
800 static int denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
801 const uint8_t *buf, int oob_required, int page)
803 struct denali_nand_info *denali = mtd_to_denali(mtd);
804 int writesize = mtd->writesize;
805 int oobsize = mtd->oobsize;
806 int ecc_steps = chip->ecc.steps;
807 int ecc_size = chip->ecc.size;
808 int ecc_bytes = chip->ecc.bytes;
809 void *tmp_buf = denali->buf;
810 int oob_skip = denali->oob_skip_bytes;
811 size_t size = writesize + oobsize;
815 * Fill the buffer with 0xff first except the full page transfer.
816 * This simplifies the logic.
818 if (!buf || !oob_required)
819 memset(tmp_buf, 0xff, size);
821 /* Arrange the buffer for syndrome payload/ecc layout */
823 for (i = 0; i < ecc_steps; i++) {
824 pos = i * (ecc_size + ecc_bytes);
827 if (pos >= writesize)
829 else if (pos + len > writesize)
830 len = writesize - pos;
832 memcpy(tmp_buf + pos, buf, len);
834 if (len < ecc_size) {
835 len = ecc_size - len;
836 memcpy(tmp_buf + writesize + oob_skip, buf,
844 const uint8_t *oob = chip->oob_poi;
846 /* BBM at the beginning of the OOB area */
847 memcpy(tmp_buf + writesize, oob, oob_skip);
851 for (i = 0; i < ecc_steps; i++) {
852 pos = ecc_size + i * (ecc_size + ecc_bytes);
855 if (pos >= writesize)
857 else if (pos + len > writesize)
858 len = writesize - pos;
860 memcpy(tmp_buf + pos, oob, len);
862 if (len < ecc_bytes) {
863 len = ecc_bytes - len;
864 memcpy(tmp_buf + writesize + oob_skip, oob,
871 len = oobsize - (oob - chip->oob_poi);
872 memcpy(tmp_buf + size - len, oob, len);
875 return denali_data_xfer(denali, tmp_buf, size, page, 1, 1);
878 static int denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
879 const uint8_t *buf, int oob_required, int page)
881 struct denali_nand_info *denali = mtd_to_denali(mtd);
883 return denali_data_xfer(denali, (void *)buf, mtd->writesize,
887 static void denali_select_chip(struct mtd_info *mtd, int chip)
889 struct denali_nand_info *denali = mtd_to_denali(mtd);
891 denali->active_bank = chip;
894 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
896 struct denali_nand_info *denali = mtd_to_denali(mtd);
899 /* R/B# pin transitioned from low to high? */
900 irq_status = denali_wait_for_irq(denali, INTR__INT_ACT);
902 return irq_status & INTR__INT_ACT ? 0 : NAND_STATUS_FAIL;
905 static int denali_erase(struct mtd_info *mtd, int page)
907 struct denali_nand_info *denali = mtd_to_denali(mtd);
910 denali_reset_irq(denali);
912 denali->host_write(denali, DENALI_MAP10 | DENALI_BANK(denali) | page,
915 /* wait for erase to complete or failure to occur */
916 irq_status = denali_wait_for_irq(denali,
917 INTR__ERASE_COMP | INTR__ERASE_FAIL);
919 return irq_status & INTR__ERASE_COMP ? 0 : NAND_STATUS_FAIL;
922 static int denali_setup_data_interface(struct mtd_info *mtd, int chipnr,
923 const struct nand_data_interface *conf)
925 struct denali_nand_info *denali = mtd_to_denali(mtd);
926 const struct nand_sdr_timings *timings;
927 unsigned long t_x, mult_x;
928 int acc_clks, re_2_we, re_2_re, we_2_re, addr_2_data;
929 int rdwr_en_lo, rdwr_en_hi, rdwr_en_lo_hi, cs_setup;
930 int addr_2_data_mask;
933 timings = nand_get_sdr_timings(conf);
935 return PTR_ERR(timings);
937 /* clk_x period in picoseconds */
938 t_x = DIV_ROUND_DOWN_ULL(1000000000000ULL, denali->clk_x_rate);
943 * The bus interface clock, clk_x, is phase aligned with the core clock.
944 * The clk_x is an integral multiple N of the core clk. The value N is
945 * configured at IP delivery time, and its available value is 4, 5, 6.
947 mult_x = DIV_ROUND_CLOSEST_ULL(denali->clk_x_rate, denali->clk_rate);
948 if (mult_x < 4 || mult_x > 6)
951 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY)
954 /* tREA -> ACC_CLKS */
955 acc_clks = DIV_ROUND_UP(timings->tREA_max, t_x);
956 acc_clks = min_t(int, acc_clks, ACC_CLKS__VALUE);
958 tmp = ioread32(denali->reg + ACC_CLKS);
959 tmp &= ~ACC_CLKS__VALUE;
960 tmp |= FIELD_PREP(ACC_CLKS__VALUE, acc_clks);
961 iowrite32(tmp, denali->reg + ACC_CLKS);
963 /* tRWH -> RE_2_WE */
964 re_2_we = DIV_ROUND_UP(timings->tRHW_min, t_x);
965 re_2_we = min_t(int, re_2_we, RE_2_WE__VALUE);
967 tmp = ioread32(denali->reg + RE_2_WE);
968 tmp &= ~RE_2_WE__VALUE;
969 tmp |= FIELD_PREP(RE_2_WE__VALUE, re_2_we);
970 iowrite32(tmp, denali->reg + RE_2_WE);
972 /* tRHZ -> RE_2_RE */
973 re_2_re = DIV_ROUND_UP(timings->tRHZ_max, t_x);
974 re_2_re = min_t(int, re_2_re, RE_2_RE__VALUE);
976 tmp = ioread32(denali->reg + RE_2_RE);
977 tmp &= ~RE_2_RE__VALUE;
978 tmp |= FIELD_PREP(RE_2_RE__VALUE, re_2_re);
979 iowrite32(tmp, denali->reg + RE_2_RE);
982 * tCCS, tWHR -> WE_2_RE
984 * With WE_2_RE properly set, the Denali controller automatically takes
985 * care of the delay; the driver need not set NAND_WAIT_TCCS.
987 we_2_re = DIV_ROUND_UP(max(timings->tCCS_min, timings->tWHR_min), t_x);
988 we_2_re = min_t(int, we_2_re, TWHR2_AND_WE_2_RE__WE_2_RE);
990 tmp = ioread32(denali->reg + TWHR2_AND_WE_2_RE);
991 tmp &= ~TWHR2_AND_WE_2_RE__WE_2_RE;
992 tmp |= FIELD_PREP(TWHR2_AND_WE_2_RE__WE_2_RE, we_2_re);
993 iowrite32(tmp, denali->reg + TWHR2_AND_WE_2_RE);
995 /* tADL -> ADDR_2_DATA */
997 /* for older versions, ADDR_2_DATA is only 6 bit wide */
998 addr_2_data_mask = TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
999 if (denali->revision < 0x0501)
1000 addr_2_data_mask >>= 1;
1002 addr_2_data = DIV_ROUND_UP(timings->tADL_min, t_x);
1003 addr_2_data = min_t(int, addr_2_data, addr_2_data_mask);
1005 tmp = ioread32(denali->reg + TCWAW_AND_ADDR_2_DATA);
1006 tmp &= ~TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA;
1007 tmp |= FIELD_PREP(TCWAW_AND_ADDR_2_DATA__ADDR_2_DATA, addr_2_data);
1008 iowrite32(tmp, denali->reg + TCWAW_AND_ADDR_2_DATA);
1010 /* tREH, tWH -> RDWR_EN_HI_CNT */
1011 rdwr_en_hi = DIV_ROUND_UP(max(timings->tREH_min, timings->tWH_min),
1013 rdwr_en_hi = min_t(int, rdwr_en_hi, RDWR_EN_HI_CNT__VALUE);
1015 tmp = ioread32(denali->reg + RDWR_EN_HI_CNT);
1016 tmp &= ~RDWR_EN_HI_CNT__VALUE;
1017 tmp |= FIELD_PREP(RDWR_EN_HI_CNT__VALUE, rdwr_en_hi);
1018 iowrite32(tmp, denali->reg + RDWR_EN_HI_CNT);
1020 /* tRP, tWP -> RDWR_EN_LO_CNT */
1021 rdwr_en_lo = DIV_ROUND_UP(max(timings->tRP_min, timings->tWP_min), t_x);
1022 rdwr_en_lo_hi = DIV_ROUND_UP(max(timings->tRC_min, timings->tWC_min),
1024 rdwr_en_lo_hi = max_t(int, rdwr_en_lo_hi, mult_x);
1025 rdwr_en_lo = max(rdwr_en_lo, rdwr_en_lo_hi - rdwr_en_hi);
1026 rdwr_en_lo = min_t(int, rdwr_en_lo, RDWR_EN_LO_CNT__VALUE);
1028 tmp = ioread32(denali->reg + RDWR_EN_LO_CNT);
1029 tmp &= ~RDWR_EN_LO_CNT__VALUE;
1030 tmp |= FIELD_PREP(RDWR_EN_LO_CNT__VALUE, rdwr_en_lo);
1031 iowrite32(tmp, denali->reg + RDWR_EN_LO_CNT);
1033 /* tCS, tCEA -> CS_SETUP_CNT */
1034 cs_setup = max3((int)DIV_ROUND_UP(timings->tCS_min, t_x) - rdwr_en_lo,
1035 (int)DIV_ROUND_UP(timings->tCEA_max, t_x) - acc_clks,
1037 cs_setup = min_t(int, cs_setup, CS_SETUP_CNT__VALUE);
1039 tmp = ioread32(denali->reg + CS_SETUP_CNT);
1040 tmp &= ~CS_SETUP_CNT__VALUE;
1041 tmp |= FIELD_PREP(CS_SETUP_CNT__VALUE, cs_setup);
1042 iowrite32(tmp, denali->reg + CS_SETUP_CNT);
1047 static void denali_reset_banks(struct denali_nand_info *denali)
1052 for (i = 0; i < denali->max_banks; i++) {
1053 denali->active_bank = i;
1055 denali_reset_irq(denali);
1057 iowrite32(DEVICE_RESET__BANK(i),
1058 denali->reg + DEVICE_RESET);
1060 irq_status = denali_wait_for_irq(denali,
1061 INTR__RST_COMP | INTR__INT_ACT | INTR__TIME_OUT);
1062 if (!(irq_status & INTR__INT_ACT))
1066 dev_dbg(denali->dev, "%d chips connected\n", i);
1067 denali->max_banks = i;
1070 static void denali_hw_init(struct denali_nand_info *denali)
1073 * The REVISION register may not be reliable. Platforms are allowed to
1076 if (!denali->revision)
1077 denali->revision = swab16(ioread32(denali->reg + REVISION));
1080 * Set how many bytes should be skipped before writing data in OOB.
1081 * If a platform requests a non-zero value, set it to the register.
1082 * Otherwise, read the value out, expecting it has already been set up
1085 if (denali->oob_skip_bytes)
1086 iowrite32(denali->oob_skip_bytes,
1087 denali->reg + SPARE_AREA_SKIP_BYTES);
1089 denali->oob_skip_bytes = ioread32(denali->reg +
1090 SPARE_AREA_SKIP_BYTES);
1092 denali_detect_max_banks(denali);
1093 iowrite32(0x0F, denali->reg + RB_PIN_ENABLED);
1094 iowrite32(CHIP_EN_DONT_CARE__FLAG, denali->reg + CHIP_ENABLE_DONT_CARE);
1096 iowrite32(0xffff, denali->reg + SPARE_AREA_MARKER);
1099 int denali_calc_ecc_bytes(int step_size, int strength)
1101 /* BCH code. Denali requires ecc.bytes to be multiple of 2 */
1102 return DIV_ROUND_UP(strength * fls(step_size * 8), 16) * 2;
1104 EXPORT_SYMBOL(denali_calc_ecc_bytes);
1106 static int denali_ecc_setup(struct mtd_info *mtd, struct nand_chip *chip,
1107 struct denali_nand_info *denali)
1109 int oobavail = mtd->oobsize - denali->oob_skip_bytes;
1113 * If .size and .strength are already set (usually by DT),
1114 * check if they are supported by this controller.
1116 if (chip->ecc.size && chip->ecc.strength)
1117 return nand_check_ecc_caps(chip, denali->ecc_caps, oobavail);
1120 * We want .size and .strength closest to the chip's requirement
1121 * unless NAND_ECC_MAXIMIZE is requested.
1123 if (!(chip->ecc.options & NAND_ECC_MAXIMIZE)) {
1124 ret = nand_match_ecc_req(chip, denali->ecc_caps, oobavail);
1129 /* Max ECC strength is the last thing we can do */
1130 return nand_maximize_ecc(chip, denali->ecc_caps, oobavail);
1133 static struct nand_ecclayout nand_oob;
1135 static int denali_ooblayout_ecc(struct mtd_info *mtd, int section,
1136 struct mtd_oob_region *oobregion)
1138 struct denali_nand_info *denali = mtd_to_denali(mtd);
1139 struct nand_chip *chip = mtd_to_nand(mtd);
1144 oobregion->offset = denali->oob_skip_bytes;
1145 oobregion->length = chip->ecc.total;
1150 static int denali_ooblayout_free(struct mtd_info *mtd, int section,
1151 struct mtd_oob_region *oobregion)
1153 struct denali_nand_info *denali = mtd_to_denali(mtd);
1154 struct nand_chip *chip = mtd_to_nand(mtd);
1159 oobregion->offset = chip->ecc.total + denali->oob_skip_bytes;
1160 oobregion->length = mtd->oobsize - oobregion->offset;
1165 static const struct mtd_ooblayout_ops denali_ooblayout_ops = {
1166 .ecc = denali_ooblayout_ecc,
1167 .rfree = denali_ooblayout_free,
1170 static int denali_multidev_fixup(struct denali_nand_info *denali)
1172 struct nand_chip *chip = &denali->nand;
1173 struct mtd_info *mtd = nand_to_mtd(chip);
1176 * Support for multi device:
1177 * When the IP configuration is x16 capable and two x8 chips are
1178 * connected in parallel, DEVICES_CONNECTED should be set to 2.
1179 * In this case, the core framework knows nothing about this fact,
1180 * so we should tell it the _logical_ pagesize and anything necessary.
1182 denali->devs_per_cs = ioread32(denali->reg + DEVICES_CONNECTED);
1185 * On some SoCs, DEVICES_CONNECTED is not auto-detected.
1186 * For those, DEVICES_CONNECTED is left to 0. Set 1 if it is the case.
1188 if (denali->devs_per_cs == 0) {
1189 denali->devs_per_cs = 1;
1190 iowrite32(1, denali->reg + DEVICES_CONNECTED);
1193 if (denali->devs_per_cs == 1)
1196 if (denali->devs_per_cs != 2) {
1197 dev_err(denali->dev, "unsupported number of devices %d\n",
1198 denali->devs_per_cs);
1202 /* 2 chips in parallel */
1204 mtd->erasesize <<= 1;
1205 mtd->writesize <<= 1;
1207 chip->chipsize <<= 1;
1208 chip->page_shift += 1;
1209 chip->phys_erase_shift += 1;
1210 chip->bbt_erase_shift += 1;
1211 chip->chip_shift += 1;
1212 chip->pagemask <<= 1;
1213 chip->ecc.size <<= 1;
1214 chip->ecc.bytes <<= 1;
1215 chip->ecc.strength <<= 1;
1216 denali->oob_skip_bytes <<= 1;
1221 int denali_init(struct denali_nand_info *denali)
1223 struct nand_chip *chip = &denali->nand;
1224 struct mtd_info *mtd = nand_to_mtd(chip);
1225 u32 features = ioread32(denali->reg + FEATURES);
1228 denali_hw_init(denali);
1230 denali_clear_irq_all(denali);
1232 denali_reset_banks(denali);
1234 denali->active_bank = DENALI_INVALID_BANK;
1236 chip->flash_node = dev_of_offset(denali->dev);
1237 /* Fallback to the default name if DT did not give "label" property */
1239 mtd->name = "denali-nand";
1241 chip->select_chip = denali_select_chip;
1242 chip->read_byte = denali_read_byte;
1243 chip->write_byte = denali_write_byte;
1244 chip->read_word = denali_read_word;
1245 chip->cmd_ctrl = denali_cmd_ctrl;
1246 chip->dev_ready = denali_dev_ready;
1247 chip->waitfunc = denali_waitfunc;
1249 if (features & FEATURES__INDEX_ADDR) {
1250 denali->host_read = denali_indexed_read;
1251 denali->host_write = denali_indexed_write;
1253 denali->host_read = denali_direct_read;
1254 denali->host_write = denali_direct_write;
1257 /* clk rate info is needed for setup_data_interface */
1258 if (denali->clk_x_rate)
1259 chip->setup_data_interface = denali_setup_data_interface;
1261 ret = nand_scan_ident(mtd, denali->max_banks, NULL);
1265 if (ioread32(denali->reg + FEATURES) & FEATURES__DMA)
1266 denali->dma_avail = 1;
1268 if (denali->dma_avail) {
1269 chip->buf_align = ARCH_DMA_MINALIGN;
1270 if (denali->caps & DENALI_CAP_DMA_64BIT)
1271 denali->setup_dma = denali_setup_dma64;
1273 denali->setup_dma = denali_setup_dma32;
1275 chip->buf_align = 4;
1278 chip->options |= NAND_USE_BOUNCE_BUFFER;
1279 chip->bbt_options |= NAND_BBT_USE_FLASH;
1280 chip->bbt_options |= NAND_BBT_NO_OOB;
1281 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1283 /* no subpage writes on denali */
1284 chip->options |= NAND_NO_SUBPAGE_WRITE;
1286 ret = denali_ecc_setup(mtd, chip, denali);
1288 dev_err(denali->dev, "Failed to setup ECC settings.\n");
1292 dev_dbg(denali->dev,
1293 "chosen ECC settings: step=%d, strength=%d, bytes=%d\n",
1294 chip->ecc.size, chip->ecc.strength, chip->ecc.bytes);
1296 iowrite32(FIELD_PREP(ECC_CORRECTION__ERASE_THRESHOLD, 1) |
1297 FIELD_PREP(ECC_CORRECTION__VALUE, chip->ecc.strength),
1298 denali->reg + ECC_CORRECTION);
1299 iowrite32(mtd->erasesize / mtd->writesize,
1300 denali->reg + PAGES_PER_BLOCK);
1301 iowrite32(chip->options & NAND_BUSWIDTH_16 ? 1 : 0,
1302 denali->reg + DEVICE_WIDTH);
1303 iowrite32(chip->options & NAND_ROW_ADDR_3 ? 0 : TWO_ROW_ADDR_CYCLES__FLAG,
1304 denali->reg + TWO_ROW_ADDR_CYCLES);
1305 iowrite32(mtd->writesize, denali->reg + DEVICE_MAIN_AREA_SIZE);
1306 iowrite32(mtd->oobsize, denali->reg + DEVICE_SPARE_AREA_SIZE);
1308 iowrite32(chip->ecc.size, denali->reg + CFG_DATA_BLOCK_SIZE);
1309 iowrite32(chip->ecc.size, denali->reg + CFG_LAST_DATA_BLOCK_SIZE);
1310 /* chip->ecc.steps is set by nand_scan_tail(); not available here */
1311 iowrite32(mtd->writesize / chip->ecc.size,
1312 denali->reg + CFG_NUM_DATA_BLOCKS);
1314 mtd_set_ooblayout(mtd, &denali_ooblayout_ops);
1316 nand_oob.eccbytes = denali->nand.ecc.bytes;
1317 denali->nand.ecc.layout = &nand_oob;
1319 if (chip->options & NAND_BUSWIDTH_16) {
1320 chip->read_buf = denali_read_buf16;
1321 chip->write_buf = denali_write_buf16;
1323 chip->read_buf = denali_read_buf;
1324 chip->write_buf = denali_write_buf;
1326 chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1327 chip->ecc.read_page = denali_read_page;
1328 chip->ecc.read_page_raw = denali_read_page_raw;
1329 chip->ecc.write_page = denali_write_page;
1330 chip->ecc.write_page_raw = denali_write_page_raw;
1331 chip->ecc.read_oob = denali_read_oob;
1332 chip->ecc.write_oob = denali_write_oob;
1333 chip->erase = denali_erase;
1335 ret = denali_multidev_fixup(denali);
1340 * This buffer is DMA-mapped by denali_{read,write}_page_raw. Do not
1341 * use devm_kmalloc() because the memory allocated by devm_ does not
1342 * guarantee DMA-safe alignment.
1344 denali->buf = kmalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL);
1348 ret = nand_scan_tail(mtd);
1352 ret = nand_register(0, mtd);
1354 dev_err(denali->dev, "Failed to register MTD: %d\n", ret);