5 * Platform independent driver for NDFC (NanD Flash Controller)
6 * integrated into EP440 cores
8 * Ported to an OF platform driver by Sean MacLennan
10 * The NDFC supports multiple chips, but this driver only supports a
11 * single chip since I do not have access to any boards with
14 * Author: Thomas Gleixner
17 * Copyright 2008 PIKA Technologies
18 * Sean MacLennan <smaclennan@pikatech.com>
20 * This program is free software; you can redistribute it and/or modify it
21 * under the terms of the GNU General Public License as published by the
22 * Free Software Foundation; either version 2 of the License, or (at your
23 * option) any later version.
26 #include <linux/module.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
29 #include <linux/mtd/partitions.h>
30 #include <linux/mtd/ndfc.h>
31 #include <linux/slab.h>
32 #include <linux/mtd/mtd.h>
33 #include <linux/of_platform.h>
38 struct ndfc_controller {
39 struct platform_device *ofdev;
40 void __iomem *ndfcbase;
42 struct nand_chip chip;
44 struct nand_hw_control ndfc_control;
47 static struct ndfc_controller ndfc_ctrl[NDFC_MAX_CS];
49 static void ndfc_select_chip(struct mtd_info *mtd, int chip)
52 struct nand_chip *nchip = mtd->priv;
53 struct ndfc_controller *ndfc = nchip->priv;
55 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
57 ccr &= ~NDFC_CCR_BS_MASK;
58 ccr |= NDFC_CCR_BS(chip + ndfc->chip_select);
60 ccr |= NDFC_CCR_RESET_CE;
61 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
64 static void ndfc_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
66 struct nand_chip *chip = mtd->priv;
67 struct ndfc_controller *ndfc = chip->priv;
69 if (cmd == NAND_CMD_NONE)
73 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_CMD);
75 writel(cmd & 0xFF, ndfc->ndfcbase + NDFC_ALE);
78 static int ndfc_ready(struct mtd_info *mtd)
80 struct nand_chip *chip = mtd->priv;
81 struct ndfc_controller *ndfc = chip->priv;
83 return in_be32(ndfc->ndfcbase + NDFC_STAT) & NDFC_STAT_IS_READY;
86 static void ndfc_enable_hwecc(struct mtd_info *mtd, int mode)
89 struct nand_chip *chip = mtd->priv;
90 struct ndfc_controller *ndfc = chip->priv;
92 ccr = in_be32(ndfc->ndfcbase + NDFC_CCR);
93 ccr |= NDFC_CCR_RESET_ECC;
94 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
98 static int ndfc_calculate_ecc(struct mtd_info *mtd,
99 const u_char *dat, u_char *ecc_code)
101 struct nand_chip *chip = mtd->priv;
102 struct ndfc_controller *ndfc = chip->priv;
104 uint8_t *p = (uint8_t *)&ecc;
107 ecc = in_be32(ndfc->ndfcbase + NDFC_ECC);
108 /* The NDFC uses Smart Media (SMC) bytes order */
117 * Speedups for buffer read/write/verify
119 * NDFC allows 32bit read/write of data. So we can speed up the buffer
120 * functions. No further checking, as nand_base will always read/write
123 static void ndfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
125 struct nand_chip *chip = mtd->priv;
126 struct ndfc_controller *ndfc = chip->priv;
127 uint32_t *p = (uint32_t *) buf;
129 for(;len > 0; len -= 4)
130 *p++ = in_be32(ndfc->ndfcbase + NDFC_DATA);
133 static void ndfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
135 struct nand_chip *chip = mtd->priv;
136 struct ndfc_controller *ndfc = chip->priv;
137 uint32_t *p = (uint32_t *) buf;
139 for(;len > 0; len -= 4)
140 out_be32(ndfc->ndfcbase + NDFC_DATA, *p++);
143 static int ndfc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
145 struct nand_chip *chip = mtd->priv;
146 struct ndfc_controller *ndfc = chip->priv;
147 uint32_t *p = (uint32_t *) buf;
149 for(;len > 0; len -= 4)
150 if (*p++ != in_be32(ndfc->ndfcbase + NDFC_DATA))
156 * Initialize chip structure
158 static int ndfc_chip_init(struct ndfc_controller *ndfc,
159 struct device_node *node)
161 struct device_node *flash_np;
162 struct nand_chip *chip = &ndfc->chip;
163 struct mtd_part_parser_data ppdata;
166 chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
167 chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
168 chip->cmd_ctrl = ndfc_hwcontrol;
169 chip->dev_ready = ndfc_ready;
170 chip->select_chip = ndfc_select_chip;
171 chip->chip_delay = 50;
172 chip->controller = &ndfc->ndfc_control;
173 chip->read_buf = ndfc_read_buf;
174 chip->write_buf = ndfc_write_buf;
175 chip->verify_buf = ndfc_verify_buf;
176 chip->ecc.correct = nand_correct_data;
177 chip->ecc.hwctl = ndfc_enable_hwecc;
178 chip->ecc.calculate = ndfc_calculate_ecc;
179 chip->ecc.mode = NAND_ECC_HW;
180 chip->ecc.size = 256;
184 ndfc->mtd.priv = chip;
185 ndfc->mtd.owner = THIS_MODULE;
187 flash_np = of_get_next_child(node, NULL);
191 ppdata->of_node = flash_np;
192 ndfc->mtd.name = kasprintf(GFP_KERNEL, "%s.%s",
193 dev_name(&ndfc->ofdev->dev), flash_np->name);
194 if (!ndfc->mtd.name) {
199 ret = nand_scan(&ndfc->mtd, 1);
203 ret = mtd_device_parse_register(&ndfc->mtd, NULL, &ppdata, NULL, 0);
206 of_node_put(flash_np);
208 kfree(ndfc->mtd.name);
212 static int __devinit ndfc_probe(struct platform_device *ofdev)
214 struct ndfc_controller *ndfc;
219 /* Read the reg property to get the chip select */
220 reg = of_get_property(ofdev->dev.of_node, "reg", &len);
221 if (reg == NULL || len != 12) {
222 dev_err(&ofdev->dev, "unable read reg property (%d)\n", len);
226 cs = be32_to_cpu(reg[0]);
227 if (cs >= NDFC_MAX_CS) {
228 dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs);
232 ndfc = &ndfc_ctrl[cs];
233 ndfc->chip_select = cs;
235 spin_lock_init(&ndfc->ndfc_control.lock);
236 init_waitqueue_head(&ndfc->ndfc_control.wq);
238 dev_set_drvdata(&ofdev->dev, ndfc);
240 ndfc->ndfcbase = of_iomap(ofdev->dev.of_node, 0);
241 if (!ndfc->ndfcbase) {
242 dev_err(&ofdev->dev, "failed to get memory\n");
246 ccr = NDFC_CCR_BS(ndfc->chip_select);
248 /* It is ok if ccr does not exist - just default to 0 */
249 reg = of_get_property(ofdev->dev.of_node, "ccr", NULL);
251 ccr |= be32_to_cpup(reg);
253 out_be32(ndfc->ndfcbase + NDFC_CCR, ccr);
255 /* Set the bank settings if given */
256 reg = of_get_property(ofdev->dev.of_node, "bank-settings", NULL);
258 int offset = NDFC_BCFG0 + (ndfc->chip_select << 2);
259 out_be32(ndfc->ndfcbase + offset, be32_to_cpup(reg));
262 err = ndfc_chip_init(ndfc, ofdev->dev.of_node);
264 iounmap(ndfc->ndfcbase);
271 static int __devexit ndfc_remove(struct platform_device *ofdev)
273 struct ndfc_controller *ndfc = dev_get_drvdata(&ofdev->dev);
275 nand_release(&ndfc->mtd);
276 kfree(ndfc->mtd.name);
281 static const struct of_device_id ndfc_match[] = {
282 { .compatible = "ibm,ndfc", },
285 MODULE_DEVICE_TABLE(of, ndfc_match);
287 static struct platform_driver ndfc_driver = {
290 .owner = THIS_MODULE,
291 .of_match_table = ndfc_match,
294 .remove = __devexit_p(ndfc_remove),
297 static int __init ndfc_nand_init(void)
299 return platform_driver_register(&ndfc_driver);
302 static void __exit ndfc_nand_exit(void)
304 platform_driver_unregister(&ndfc_driver);
307 module_init(ndfc_nand_init);
308 module_exit(ndfc_nand_exit);
310 MODULE_LICENSE("GPL");
311 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
312 MODULE_DESCRIPTION("OF Platform driver for NDFC");