drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ECC support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 /* Define default oob placement schemes for large and small page devices */
  53 static struct nand_ecclayout nand_oob_8 = {
  54         .eccbytes = 3,
  55         .eccpos = {0, 1, 2},
  56         .oobfree = {
  57                 {.offset = 3,
  58                  .length = 2},
  59                 {.offset = 6,
  60                  .length = 2} }
  61 };
  62
  63 static struct nand_ecclayout nand_oob_16 = {
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {
  67                 {.offset = 8,
  68                  . length = 8} }
  69 };
  70
  71 static struct nand_ecclayout nand_oob_64 = {
  72         .eccbytes = 24,
  73         .eccpos = {
  74                    40, 41, 42, 43, 44, 45, 46, 47,
  75                    48, 49, 50, 51, 52, 53, 54, 55,
  76                    56, 57, 58, 59, 60, 61, 62, 63},
  77         .oobfree = {
  78                 {.offset = 2,
  79                  .length = 38} }
  80 };
  81
  82 static struct nand_ecclayout nand_oob_128 = {
  83         .eccbytes = 48,
  84         .eccpos = {
  85                    80, 81, 82, 83, 84, 85, 86, 87,
  86                    88, 89, 90, 91, 92, 93, 94, 95,
  87                    96, 97, 98, 99, 100, 101, 102, 103,
  88                    104, 105, 106, 107, 108, 109, 110, 111,
  89                    112, 113, 114, 115, 116, 117, 118, 119,
  90                    120, 121, 122, 123, 124, 125, 126, 127},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 78} }
  94 };
  95
  96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  97                            int new_state);
  98
  99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 100                              struct mtd_oob_ops *ops);
 101
 102 /*
 103  * For devices which display every fart in the system on a separate LED. Is
 104  * compiled away when LED support is disabled.
 105  */
 106 DEFINE_LED_TRIGGER(nand_led_trigger);
 107
 108 static int check_offs_len(struct mtd_info *mtd,
 109                                         loff_t ofs, uint64_t len)
 110 {
 111         struct nand_chip *chip = mtd->priv;
 112         int ret = 0;
 113
 114         /* Start address must align on block boundary */
 115         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 116                 pr_debug("%s: unaligned address\n", __func__);
 117                 ret = -EINVAL;
 118         }
 119
 120         /* Length must align on block boundary */
 121         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 122                 pr_debug("%s: length not block aligned\n", __func__);
 123                 ret = -EINVAL;
 124         }
 125
 126         /* Do not allow past end of device */
 127         if (ofs + len > mtd->size) {
 128                 pr_debug("%s: past end of device\n", __func__);
 129                 ret = -EINVAL;
 130         }
 131
 132         return ret;
 133 }
 134
 135 /**
 136  * nand_release_device - [GENERIC] release chip
 137  * @mtd: MTD device structure
 138  *
 139  * Deselect, release chip lock and wake up anyone waiting on the device.
 140  */
 141 static void nand_release_device(struct mtd_info *mtd)
 142 {
 143         struct nand_chip *chip = mtd->priv;
 144
 145         /* De-select the NAND device */
 146         chip->select_chip(mtd, -1);
 147
 148         /* Release the controller and the chip */
 149         spin_lock(&chip->controller->lock);
 150         chip->controller->active = NULL;
 151         chip->state = FL_READY;
 152         wake_up(&chip->controller->wq);
 153         spin_unlock(&chip->controller->lock);
 154 }
 155
 156 /**
 157  * nand_read_byte - [DEFAULT] read one byte from the chip
 158  * @mtd: MTD device structure
 159  *
 160  * Default read function for 8bit buswidth
 161  */
 162 static uint8_t nand_read_byte(struct mtd_info *mtd)
 163 {
 164         struct nand_chip *chip = mtd->priv;
 165         return readb(chip->IO_ADDR_R);
 166 }
 167
 168 /**
 169  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 170  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 171  * @mtd: MTD device structure
 172  *
 173  * Default read function for 16bit buswidth with endianness conversion.
 174  *
 175  */
 176 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 177 {
 178         struct nand_chip *chip = mtd->priv;
 179         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 180 }
 181
 182 /**
 183  * nand_read_word - [DEFAULT] read one word from the chip
 184  * @mtd: MTD device structure
 185  *
 186  * Default read function for 16bit buswidth without endianness conversion.
 187  */
 188 static u16 nand_read_word(struct mtd_info *mtd)
 189 {
 190         struct nand_chip *chip = mtd->priv;
 191         return readw(chip->IO_ADDR_R);
 192 }
 193
 194 /**
 195  * nand_select_chip - [DEFAULT] control CE line
 196  * @mtd: MTD device structure
 197  * @chipnr: chipnumber to select, -1 for deselect
 198  *
 199  * Default select function for 1 chip devices.
 200  */
 201 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 202 {
 203         struct nand_chip *chip = mtd->priv;
 204
 205         switch (chipnr) {
 206         case -1:
 207                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 208                 break;
 209         case 0:
 210                 break;
 211
 212         default:
 213                 BUG();
 214         }
 215 }
 216
 217 /**
 218  * nand_write_buf - [DEFAULT] write buffer to chip
 219  * @mtd: MTD device structure
 220  * @buf: data buffer
 221  * @len: number of bytes to write
 222  *
 223  * Default write function for 8bit buswidth.
 224  */
 225 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 226 {
 227         int i;
 228         struct nand_chip *chip = mtd->priv;
 229
 230         for (i = 0; i < len; i++)
 231                 writeb(buf[i], chip->IO_ADDR_W);
 232 }
 233
 234 /**
 235  * nand_read_buf - [DEFAULT] read chip data into buffer
 236  * @mtd: MTD device structure
 237  * @buf: buffer to store date
 238  * @len: number of bytes to read
 239  *
 240  * Default read function for 8bit buswidth.
 241  */
 242 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 243 {
 244         int i;
 245         struct nand_chip *chip = mtd->priv;
 246
 247         for (i = 0; i < len; i++)
 248                 buf[i] = readb(chip->IO_ADDR_R);
 249 }
 250
 251 /**
 252  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 253  * @mtd: MTD device structure
 254  * @buf: buffer containing the data to compare
 255  * @len: number of bytes to compare
 256  *
 257  * Default verify function for 8bit buswidth.
 258  */
 259 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 260 {
 261         int i;
 262         struct nand_chip *chip = mtd->priv;
 263
 264         for (i = 0; i < len; i++)
 265                 if (buf[i] != readb(chip->IO_ADDR_R))
 266                         return -EFAULT;
 267         return 0;
 268 }
 269
 270 /**
 271  * nand_write_buf16 - [DEFAULT] write buffer to chip
 272  * @mtd: MTD device structure
 273  * @buf: data buffer
 274  * @len: number of bytes to write
 275  *
 276  * Default write function for 16bit buswidth.
 277  */
 278 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 279 {
 280         int i;
 281         struct nand_chip *chip = mtd->priv;
 282         u16 *p = (u16 *) buf;
 283         len >>= 1;
 284
 285         for (i = 0; i < len; i++)
 286                 writew(p[i], chip->IO_ADDR_W);
 287
 288 }
 289
 290 /**
 291  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 292  * @mtd: MTD device structure
 293  * @buf: buffer to store date
 294  * @len: number of bytes to read
 295  *
 296  * Default read function for 16bit buswidth.
 297  */
 298 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 299 {
 300         int i;
 301         struct nand_chip *chip = mtd->priv;
 302         u16 *p = (u16 *) buf;
 303         len >>= 1;
 304
 305         for (i = 0; i < len; i++)
 306                 p[i] = readw(chip->IO_ADDR_R);
 307 }
 308
 309 /**
 310  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 311  * @mtd: MTD device structure
 312  * @buf: buffer containing the data to compare
 313  * @len: number of bytes to compare
 314  *
 315  * Default verify function for 16bit buswidth.
 316  */
 317 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 318 {
 319         int i;
 320         struct nand_chip *chip = mtd->priv;
 321         u16 *p = (u16 *) buf;
 322         len >>= 1;
 323
 324         for (i = 0; i < len; i++)
 325                 if (p[i] != readw(chip->IO_ADDR_R))
 326                         return -EFAULT;
 327
 328         return 0;
 329 }
 330
 331 /**
 332  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 333  * @mtd: MTD device structure
 334  * @ofs: offset from device start
 335  * @getchip: 0, if the chip is already selected
 336  *
 337  * Check, if the block is bad.
 338  */
 339 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 340 {
 341         int page, chipnr, res = 0;
 342         struct nand_chip *chip = mtd->priv;
 343         u16 bad;
 344
 345         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 346                 ofs += mtd->erasesize - mtd->writesize;
 347
 348         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 349
 350         if (getchip) {
 351                 chipnr = (int)(ofs >> chip->chip_shift);
 352
 353                 nand_get_device(chip, mtd, FL_READING);
 354
 355                 /* Select the NAND device */
 356                 chip->select_chip(mtd, chipnr);
 357         }
 358
 359         if (chip->options & NAND_BUSWIDTH_16) {
 360                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 361                               page);
 362                 bad = cpu_to_le16(chip->read_word(mtd));
 363                 if (chip->badblockpos & 0x1)
 364                         bad >>= 8;
 365                 else
 366                         bad &= 0xFF;
 367         } else {
 368                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 369                 bad = chip->read_byte(mtd);
 370         }
 371
 372         if (likely(chip->badblockbits == 8))
 373                 res = bad != 0xFF;
 374         else
 375                 res = hweight8(bad) < chip->badblockbits;
 376
 377         if (getchip)
 378                 nand_release_device(mtd);
 379
 380         return res;
 381 }
 382
 383 /**
 384  * nand_default_block_markbad - [DEFAULT] mark a block bad
 385  * @mtd: MTD device structure
 386  * @ofs: offset from device start
 387  *
 388  * This is the default implementation, which can be overridden by a hardware
 389  * specific driver.
 390 */
 391 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 392 {
 393         struct nand_chip *chip = mtd->priv;
 394         uint8_t buf[2] = { 0, 0 };
 395         int block, ret, i = 0;
 396
 397         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 398                 ofs += mtd->erasesize - mtd->writesize;
 399
 400         /* Get block number */
 401         block = (int)(ofs >> chip->bbt_erase_shift);
 402         if (chip->bbt)
 403                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 404
 405         /* Do we have a flash based bad block table? */
 406         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 407                 ret = nand_update_bbt(mtd, ofs);
 408         else {
 409                 nand_get_device(chip, mtd, FL_WRITING);
 410
 411                 /*
 412                  * Write to first two pages if necessary. If we write to more
 413                  * than one location, the first error encountered quits the
 414                  * procedure. We write two bytes per location, so we dont have
 415                  * to mess with 16 bit access.
 416                  */
 417                 do {
 418                         chip->ops.len = chip->ops.ooblen = 2;
 419                         chip->ops.datbuf = NULL;
 420                         chip->ops.oobbuf = buf;
 421                         chip->ops.ooboffs = chip->badblockpos & ~0x01;
 422
 423                         ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 424
 425                         i++;
 426                         ofs += mtd->writesize;
 427                 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
 428                                 i < 2);
 429
 430                 nand_release_device(mtd);
 431         }
 432         if (!ret)
 433                 mtd->ecc_stats.badblocks++;
 434
 435         return ret;
 436 }
 437
 438 /**
 439  * nand_check_wp - [GENERIC] check if the chip is write protected
 440  * @mtd: MTD device structure
 441  *
 442  * Check, if the device is write protected. The function expects, that the
 443  * device is already selected.
 444  */
 445 static int nand_check_wp(struct mtd_info *mtd)
 446 {
 447         struct nand_chip *chip = mtd->priv;
 448
 449         /* Broken xD cards report WP despite being writable */
 450         if (chip->options & NAND_BROKEN_XD)
 451                 return 0;
 452
 453         /* Check the WP bit */
 454         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 455         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 456 }
 457
 458 /**
 459  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 460  * @mtd: MTD device structure
 461  * @ofs: offset from device start
 462  * @getchip: 0, if the chip is already selected
 463  * @allowbbt: 1, if its allowed to access the bbt area
 464  *
 465  * Check, if the block is bad. Either by reading the bad block table or
 466  * calling of the scan function.
 467  */
 468 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 469                                int allowbbt)
 470 {
 471         struct nand_chip *chip = mtd->priv;
 472
 473         if (!chip->bbt)
 474                 return chip->block_bad(mtd, ofs, getchip);
 475
 476         /* Return info from the table */
 477         return nand_isbad_bbt(mtd, ofs, allowbbt);
 478 }
 479
 480 /**
 481  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 482  * @mtd: MTD device structure
 483  * @timeo: Timeout
 484  *
 485  * Helper function for nand_wait_ready used when needing to wait in interrupt
 486  * context.
 487  */
 488 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 489 {
 490         struct nand_chip *chip = mtd->priv;
 491         int i;
 492
 493         /* Wait for the device to get ready */
 494         for (i = 0; i < timeo; i++) {
 495                 if (chip->dev_ready(mtd))
 496                         break;
 497                 touch_softlockup_watchdog();
 498                 mdelay(1);
 499         }
 500 }
 501
 502 /* Wait for the ready pin, after a command. The timeout is caught later. */
 503 void nand_wait_ready(struct mtd_info *mtd)
 504 {
 505         struct nand_chip *chip = mtd->priv;
 506         unsigned long timeo = jiffies + 2;
 507
 508         /* 400ms timeout */
 509         if (in_interrupt() || oops_in_progress)
 510                 return panic_nand_wait_ready(mtd, 400);
 511
 512         led_trigger_event(nand_led_trigger, LED_FULL);
 513         /* Wait until command is processed or timeout occurs */
 514         do {
 515                 if (chip->dev_ready(mtd))
 516                         break;
 517                 touch_softlockup_watchdog();
 518         } while (time_before(jiffies, timeo));
 519         led_trigger_event(nand_led_trigger, LED_OFF);
 520 }
 521 EXPORT_SYMBOL_GPL(nand_wait_ready);
 522
 523 /**
 524  * nand_command - [DEFAULT] Send command to NAND device
 525  * @mtd: MTD device structure
 526  * @command: the command to be sent
 527  * @column: the column address for this command, -1 if none
 528  * @page_addr: the page address for this command, -1 if none
 529  *
 530  * Send command to NAND device. This function is used for small page devices
 531  * (256/512 Bytes per page).
 532  */
 533 static void nand_command(struct mtd_info *mtd, unsigned int command,
 534                          int column, int page_addr)
 535 {
 536         register struct nand_chip *chip = mtd->priv;
 537         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 538
 539         /* Write out the command to the device */
 540         if (command == NAND_CMD_SEQIN) {
 541                 int readcmd;
 542
 543                 if (column >= mtd->writesize) {
 544                         /* OOB area */
 545                         column -= mtd->writesize;
 546                         readcmd = NAND_CMD_READOOB;
 547                 } else if (column < 256) {
 548                         /* First 256 bytes --> READ0 */
 549                         readcmd = NAND_CMD_READ0;
 550                 } else {
 551                         column -= 256;
 552                         readcmd = NAND_CMD_READ1;
 553                 }
 554                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 555                 ctrl &= ~NAND_CTRL_CHANGE;
 556         }
 557         chip->cmd_ctrl(mtd, command, ctrl);
 558
 559         /* Address cycle, when necessary */
 560         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 561         /* Serially input address */
 562         if (column != -1) {
 563                 /* Adjust columns for 16 bit buswidth */
 564                 if (chip->options & NAND_BUSWIDTH_16)
 565                         column >>= 1;
 566                 chip->cmd_ctrl(mtd, column, ctrl);
 567                 ctrl &= ~NAND_CTRL_CHANGE;
 568         }
 569         if (page_addr != -1) {
 570                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 571                 ctrl &= ~NAND_CTRL_CHANGE;
 572                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 573                 /* One more address cycle for devices > 32MiB */
 574                 if (chip->chipsize > (32 << 20))
 575                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 576         }
 577         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 578
 579         /*
 580          * Program and erase have their own busy handlers status and sequential
 581          * in needs no delay
 582          */
 583         switch (command) {
 584
 585         case NAND_CMD_PAGEPROG:
 586         case NAND_CMD_ERASE1:
 587         case NAND_CMD_ERASE2:
 588         case NAND_CMD_SEQIN:
 589         case NAND_CMD_STATUS:
 590                 return;
 591
 592         case NAND_CMD_RESET:
 593                 if (chip->dev_ready)
 594                         break;
 595                 udelay(chip->chip_delay);
 596                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 597                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 598                 chip->cmd_ctrl(mtd,
 599                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 600                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 601                                 ;
 602                 return;
 603
 604                 /* This applies to read commands */
 605         default:
 606                 /*
 607                  * If we don't have access to the busy pin, we apply the given
 608                  * command delay
 609                  */
 610                 if (!chip->dev_ready) {
 611                         udelay(chip->chip_delay);
 612                         return;
 613                 }
 614         }
 615         /*
 616          * Apply this short delay always to ensure that we do wait tWB in
 617          * any case on any machine.
 618          */
 619         ndelay(100);
 620
 621         nand_wait_ready(mtd);
 622 }
 623
 624 /**
 625  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 626  * @mtd: MTD device structure
 627  * @command: the command to be sent
 628  * @column: the column address for this command, -1 if none
 629  * @page_addr: the page address for this command, -1 if none
 630  *
 631  * Send command to NAND device. This is the version for the new large page
 632  * devices. We don't have the separate regions as we have in the small page
 633  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 634  */
 635 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 636                             int column, int page_addr)
 637 {
 638         register struct nand_chip *chip = mtd->priv;
 639
 640         /* Emulate NAND_CMD_READOOB */
 641         if (command == NAND_CMD_READOOB) {
 642                 column += mtd->writesize;
 643                 command = NAND_CMD_READ0;
 644         }
 645
 646         /* Command latch cycle */
 647         chip->cmd_ctrl(mtd, command & 0xff,
 648                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 649
 650         if (column != -1 || page_addr != -1) {
 651                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 652
 653                 /* Serially input address */
 654                 if (column != -1) {
 655                         /* Adjust columns for 16 bit buswidth */
 656                         if (chip->options & NAND_BUSWIDTH_16)
 657                                 column >>= 1;
 658                         chip->cmd_ctrl(mtd, column, ctrl);
 659                         ctrl &= ~NAND_CTRL_CHANGE;
 660                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 661                 }
 662                 if (page_addr != -1) {
 663                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 664                         chip->cmd_ctrl(mtd, page_addr >> 8,
 665                                        NAND_NCE | NAND_ALE);
 666                         /* One more address cycle for devices > 128MiB */
 667                         if (chip->chipsize > (128 << 20))
 668                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 669                                                NAND_NCE | NAND_ALE);
 670                 }
 671         }
 672         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 673
 674         /*
 675          * Program and erase have their own busy handlers status, sequential
 676          * in, and deplete1 need no delay.
 677          */
 678         switch (command) {
 679
 680         case NAND_CMD_CACHEDPROG:
 681         case NAND_CMD_PAGEPROG:
 682         case NAND_CMD_ERASE1:
 683         case NAND_CMD_ERASE2:
 684         case NAND_CMD_SEQIN:
 685         case NAND_CMD_RNDIN:
 686         case NAND_CMD_STATUS:
 687         case NAND_CMD_DEPLETE1:
 688                 return;
 689
 690         case NAND_CMD_STATUS_ERROR:
 691         case NAND_CMD_STATUS_ERROR0:
 692         case NAND_CMD_STATUS_ERROR1:
 693         case NAND_CMD_STATUS_ERROR2:
 694         case NAND_CMD_STATUS_ERROR3:
 695                 /* Read error status commands require only a short delay */
 696                 udelay(chip->chip_delay);
 697                 return;
 698
 699         case NAND_CMD_RESET:
 700                 if (chip->dev_ready)
 701                         break;
 702                 udelay(chip->chip_delay);
 703                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 704                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 705                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 706                                NAND_NCE | NAND_CTRL_CHANGE);
 707                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 708                                 ;
 709                 return;
 710
 711         case NAND_CMD_RNDOUT:
 712                 /* No ready / busy check necessary */
 713                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 714                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 715                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 716                                NAND_NCE | NAND_CTRL_CHANGE);
 717                 return;
 718
 719         case NAND_CMD_READ0:
 720                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 721                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 722                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 723                                NAND_NCE | NAND_CTRL_CHANGE);
 724
 725                 /* This applies to read commands */
 726         default:
 727                 /*
 728                  * If we don't have access to the busy pin, we apply the given
 729                  * command delay.
 730                  */
 731                 if (!chip->dev_ready) {
 732                         udelay(chip->chip_delay);
 733                         return;
 734                 }
 735         }
 736
 737         /*
 738          * Apply this short delay always to ensure that we do wait tWB in
 739          * any case on any machine.
 740          */
 741         ndelay(100);
 742
 743         nand_wait_ready(mtd);
 744 }
 745
 746 /**
 747  * panic_nand_get_device - [GENERIC] Get chip for selected access
 748  * @chip: the nand chip descriptor
 749  * @mtd: MTD device structure
 750  * @new_state: the state which is requested
 751  *
 752  * Used when in panic, no locks are taken.
 753  */
 754 static void panic_nand_get_device(struct nand_chip *chip,
 755                       struct mtd_info *mtd, int new_state)
 756 {
 757         /* Hardware controller shared among independent devices */
 758         chip->controller->active = chip;
 759         chip->state = new_state;
 760 }
 761
 762 /**
 763  * nand_get_device - [GENERIC] Get chip for selected access
 764  * @chip: the nand chip descriptor
 765  * @mtd: MTD device structure
 766  * @new_state: the state which is requested
 767  *
 768  * Get the device and lock it for exclusive access
 769  */
 770 static int
 771 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 772 {
 773         spinlock_t *lock = &chip->controller->lock;
 774         wait_queue_head_t *wq = &chip->controller->wq;
 775         DECLARE_WAITQUEUE(wait, current);
 776 retry:
 777         spin_lock(lock);
 778
 779         /* Hardware controller shared among independent devices */
 780         if (!chip->controller->active)
 781                 chip->controller->active = chip;
 782
 783         if (chip->controller->active == chip && chip->state == FL_READY) {
 784                 chip->state = new_state;
 785                 spin_unlock(lock);
 786                 return 0;
 787         }
 788         if (new_state == FL_PM_SUSPENDED) {
 789                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 790                         chip->state = FL_PM_SUSPENDED;
 791                         spin_unlock(lock);
 792                         return 0;
 793                 }
 794         }
 795         set_current_state(TASK_UNINTERRUPTIBLE);
 796         add_wait_queue(wq, &wait);
 797         spin_unlock(lock);
 798         schedule();
 799         remove_wait_queue(wq, &wait);
 800         goto retry;
 801 }
 802
 803 /**
 804  * panic_nand_wait - [GENERIC] wait until the command is done
 805  * @mtd: MTD device structure
 806  * @chip: NAND chip structure
 807  * @timeo: timeout
 808  *
 809  * Wait for command done. This is a helper function for nand_wait used when
 810  * we are in interrupt context. May happen when in panic and trying to write
 811  * an oops through mtdoops.
 812  */
 813 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 814                             unsigned long timeo)
 815 {
 816         int i;
 817         for (i = 0; i < timeo; i++) {
 818                 if (chip->dev_ready) {
 819                         if (chip->dev_ready(mtd))
 820                                 break;
 821                 } else {
 822                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 823                                 break;
 824                 }
 825                 mdelay(1);
 826         }
 827 }
 828
 829 /**
 830  * nand_wait - [DEFAULT] wait until the command is done
 831  * @mtd: MTD device structure
 832  * @chip: NAND chip structure
 833  *
 834  * Wait for command done. This applies to erase and program only. Erase can
 835  * take up to 400ms and program up to 20ms according to general NAND and
 836  * SmartMedia specs.
 837  */
 838 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 839 {
 840
 841         unsigned long timeo = jiffies;
 842         int status, state = chip->state;
 843
 844         if (state == FL_ERASING)
 845                 timeo += (HZ * 400) / 1000;
 846         else
 847                 timeo += (HZ * 20) / 1000;
 848
 849         led_trigger_event(nand_led_trigger, LED_FULL);
 850
 851         /*
 852          * Apply this short delay always to ensure that we do wait tWB in any
 853          * case on any machine.
 854          */
 855         ndelay(100);
 856
 857         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 858                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 859         else
 860                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 861
 862         if (in_interrupt() || oops_in_progress)
 863                 panic_nand_wait(mtd, chip, timeo);
 864         else {
 865                 while (time_before(jiffies, timeo)) {
 866                         if (chip->dev_ready) {
 867                                 if (chip->dev_ready(mtd))
 868                                         break;
 869                         } else {
 870                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 871                                         break;
 872                         }
 873                         cond_resched();
 874                 }
 875         }
 876         led_trigger_event(nand_led_trigger, LED_OFF);
 877
 878         status = (int)chip->read_byte(mtd);
 879         return status;
 880 }
 881
 882 /**
 883  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 884  * @mtd: mtd info
 885  * @ofs: offset to start unlock from
 886  * @len: length to unlock
 887  * @invert: when = 0, unlock the range of blocks within the lower and
 888  *                    upper boundary address
 889  *          when = 1, unlock the range of blocks outside the boundaries
 890  *                    of the lower and upper boundary address
 891  *
 892  * Returs unlock status.
 893  */
 894 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 895                                         uint64_t len, int invert)
 896 {
 897         int ret = 0;
 898         int status, page;
 899         struct nand_chip *chip = mtd->priv;
 900
 901         /* Submit address of first page to unlock */
 902         page = ofs >> chip->page_shift;
 903         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 904
 905         /* Submit address of last page to unlock */
 906         page = (ofs + len) >> chip->page_shift;
 907         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 908                                 (page | invert) & chip->pagemask);
 909
 910         /* Call wait ready function */
 911         status = chip->waitfunc(mtd, chip);
 912         /* See if device thinks it succeeded */
 913         if (status & 0x01) {
 914                 pr_debug("%s: error status = 0x%08x\n",
 915                                         __func__, status);
 916                 ret = -EIO;
 917         }
 918
 919         return ret;
 920 }
 921
 922 /**
 923  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 924  * @mtd: mtd info
 925  * @ofs: offset to start unlock from
 926  * @len: length to unlock
 927  *
 928  * Returns unlock status.
 929  */
 930 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 931 {
 932         int ret = 0;
 933         int chipnr;
 934         struct nand_chip *chip = mtd->priv;
 935
 936         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 937                         __func__, (unsigned long long)ofs, len);
 938
 939         if (check_offs_len(mtd, ofs, len))
 940                 ret = -EINVAL;
 941
 942         /* Align to last block address if size addresses end of the device */
 943         if (ofs + len == mtd->size)
 944                 len -= mtd->erasesize;
 945
 946         nand_get_device(chip, mtd, FL_UNLOCKING);
 947
 948         /* Shift to get chip number */
 949         chipnr = ofs >> chip->chip_shift;
 950
 951         chip->select_chip(mtd, chipnr);
 952
 953         /* Check, if it is write protected */
 954         if (nand_check_wp(mtd)) {
 955                 pr_debug("%s: device is write protected!\n",
 956                                         __func__);
 957                 ret = -EIO;
 958                 goto out;
 959         }
 960
 961         ret = __nand_unlock(mtd, ofs, len, 0);
 962
 963 out:
 964         nand_release_device(mtd);
 965
 966         return ret;
 967 }
 968 EXPORT_SYMBOL(nand_unlock);
 969
 970 /**
 971  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 972  * @mtd: mtd info
 973  * @ofs: offset to start unlock from
 974  * @len: length to unlock
 975  *
 976  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 977  * have this feature, but it allows only to lock all blocks, not for specified
 978  * range for block. Implementing 'lock' feature by making use of 'unlock', for
 979  * now.
 980  *
 981  * Returns lock status.
 982  */
 983 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 984 {
 985         int ret = 0;
 986         int chipnr, status, page;
 987         struct nand_chip *chip = mtd->priv;
 988
 989         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 990                         __func__, (unsigned long long)ofs, len);
 991
 992         if (check_offs_len(mtd, ofs, len))
 993                 ret = -EINVAL;
 994
 995         nand_get_device(chip, mtd, FL_LOCKING);
 996
 997         /* Shift to get chip number */
 998         chipnr = ofs >> chip->chip_shift;
 999
1000         chip->select_chip(mtd, chipnr);
1001
1002         /* Check, if it is write protected */
1003         if (nand_check_wp(mtd)) {
1004                 pr_debug("%s: device is write protected!\n",
1005                                         __func__);
1006                 status = MTD_ERASE_FAILED;
1007                 ret = -EIO;
1008                 goto out;
1009         }
1010
1011         /* Submit address of first page to lock */
1012         page = ofs >> chip->page_shift;
1013         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1014
1015         /* Call wait ready function */
1016         status = chip->waitfunc(mtd, chip);
1017         /* See if device thinks it succeeded */
1018         if (status & 0x01) {
1019                 pr_debug("%s: error status = 0x%08x\n",
1020                                         __func__, status);
1021                 ret = -EIO;
1022                 goto out;
1023         }
1024
1025         ret = __nand_unlock(mtd, ofs, len, 0x1);
1026
1027 out:
1028         nand_release_device(mtd);
1029
1030         return ret;
1031 }
1032 EXPORT_SYMBOL(nand_lock);
1033
1034 /**
1035  * nand_read_page_raw - [INTERN] read raw page data without ecc
1036  * @mtd: mtd info structure
1037  * @chip: nand chip info structure
1038  * @buf: buffer to store read data
1039  * @page: page number to read
1040  *
1041  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1042  */
1043 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1044                               uint8_t *buf, int page)
1045 {
1046         chip->read_buf(mtd, buf, mtd->writesize);
1047         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1048         return 0;
1049 }
1050
1051 /**
1052  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1053  * @mtd: mtd info structure
1054  * @chip: nand chip info structure
1055  * @buf: buffer to store read data
1056  * @page: page number to read
1057  *
1058  * We need a special oob layout and handling even when OOB isn't used.
1059  */
1060 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1061                                         struct nand_chip *chip,
1062                                         uint8_t *buf, int page)
1063 {
1064         int eccsize = chip->ecc.size;
1065         int eccbytes = chip->ecc.bytes;
1066         uint8_t *oob = chip->oob_poi;
1067         int steps, size;
1068
1069         for (steps = chip->ecc.steps; steps > 0; steps--) {
1070                 chip->read_buf(mtd, buf, eccsize);
1071                 buf += eccsize;
1072
1073                 if (chip->ecc.prepad) {
1074                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1075                         oob += chip->ecc.prepad;
1076                 }
1077
1078                 chip->read_buf(mtd, oob, eccbytes);
1079                 oob += eccbytes;
1080
1081                 if (chip->ecc.postpad) {
1082                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1083                         oob += chip->ecc.postpad;
1084                 }
1085         }
1086
1087         size = mtd->oobsize - (oob - chip->oob_poi);
1088         if (size)
1089                 chip->read_buf(mtd, oob, size);
1090
1091         return 0;
1092 }
1093
1094 /**
1095  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1096  * @mtd: mtd info structure
1097  * @chip: nand chip info structure
1098  * @buf: buffer to store read data
1099  * @page: page number to read
1100  */
1101 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1102                                 uint8_t *buf, int page)
1103 {
1104         int i, eccsize = chip->ecc.size;
1105         int eccbytes = chip->ecc.bytes;
1106         int eccsteps = chip->ecc.steps;
1107         uint8_t *p = buf;
1108         uint8_t *ecc_calc = chip->buffers->ecccalc;
1109         uint8_t *ecc_code = chip->buffers->ecccode;
1110         uint32_t *eccpos = chip->ecc.layout->eccpos;
1111
1112         chip->ecc.read_page_raw(mtd, chip, buf, page);
1113
1114         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1115                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1116
1117         for (i = 0; i < chip->ecc.total; i++)
1118                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1119
1120         eccsteps = chip->ecc.steps;
1121         p = buf;
1122
1123         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1124                 int stat;
1125
1126                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1127                 if (stat < 0)
1128                         mtd->ecc_stats.failed++;
1129                 else
1130                         mtd->ecc_stats.corrected += stat;
1131         }
1132         return 0;
1133 }
1134
1135 /**
1136  * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1137  * @mtd: mtd info structure
1138  * @chip: nand chip info structure
1139  * @data_offs: offset of requested data within the page
1140  * @readlen: data length
1141  * @bufpoi: buffer to store read data
1142  */
1143 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1144                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1145 {
1146         int start_step, end_step, num_steps;
1147         uint32_t *eccpos = chip->ecc.layout->eccpos;
1148         uint8_t *p;
1149         int data_col_addr, i, gaps = 0;
1150         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1151         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1152         int index = 0;
1153
1154         /* Column address within the page aligned to ECC size (256bytes) */
1155         start_step = data_offs / chip->ecc.size;
1156         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1157         num_steps = end_step - start_step + 1;
1158
1159         /* Data size aligned to ECC ecc.size */
1160         datafrag_len = num_steps * chip->ecc.size;
1161         eccfrag_len = num_steps * chip->ecc.bytes;
1162
1163         data_col_addr = start_step * chip->ecc.size;
1164         /* If we read not a page aligned data */
1165         if (data_col_addr != 0)
1166                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1167
1168         p = bufpoi + data_col_addr;
1169         chip->read_buf(mtd, p, datafrag_len);
1170
1171         /* Calculate ECC */
1172         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1173                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1174
1175         /*
1176          * The performance is faster if we position offsets according to
1177          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1178          */
1179         for (i = 0; i < eccfrag_len - 1; i++) {
1180                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1181                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1182                         gaps = 1;
1183                         break;
1184                 }
1185         }
1186         if (gaps) {
1187                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1188                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1189         } else {
1190                 /*
1191                  * Send the command to read the particular ECC bytes take care
1192                  * about buswidth alignment in read_buf.
1193                  */
1194                 index = start_step * chip->ecc.bytes;
1195
1196                 aligned_pos = eccpos[index] & ~(busw - 1);
1197                 aligned_len = eccfrag_len;
1198                 if (eccpos[index] & (busw - 1))
1199                         aligned_len++;
1200                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1201                         aligned_len++;
1202
1203                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1204                                         mtd->writesize + aligned_pos, -1);
1205                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1206         }
1207
1208         for (i = 0; i < eccfrag_len; i++)
1209                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1210
1211         p = bufpoi + data_col_addr;
1212         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1213                 int stat;
1214
1215                 stat = chip->ecc.correct(mtd, p,
1216                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1217                 if (stat < 0)
1218                         mtd->ecc_stats.failed++;
1219                 else
1220                         mtd->ecc_stats.corrected += stat;
1221         }
1222         return 0;
1223 }
1224
1225 /**
1226  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1227  * @mtd: mtd info structure
1228  * @chip: nand chip info structure
1229  * @buf: buffer to store read data
1230  * @page: page number to read
1231  *
1232  * Not for syndrome calculating ECC controllers which need a special oob layout.
1233  */
1234 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1235                                 uint8_t *buf, int page)
1236 {
1237         int i, eccsize = chip->ecc.size;
1238         int eccbytes = chip->ecc.bytes;
1239         int eccsteps = chip->ecc.steps;
1240         uint8_t *p = buf;
1241         uint8_t *ecc_calc = chip->buffers->ecccalc;
1242         uint8_t *ecc_code = chip->buffers->ecccode;
1243         uint32_t *eccpos = chip->ecc.layout->eccpos;
1244
1245         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1246                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1247                 chip->read_buf(mtd, p, eccsize);
1248                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1249         }
1250         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1251
1252         for (i = 0; i < chip->ecc.total; i++)
1253                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1254
1255         eccsteps = chip->ecc.steps;
1256         p = buf;
1257
1258         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1259                 int stat;
1260
1261                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1262                 if (stat < 0)
1263                         mtd->ecc_stats.failed++;
1264                 else
1265                         mtd->ecc_stats.corrected += stat;
1266         }
1267         return 0;
1268 }
1269
1270 /**
1271  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1272  * @mtd: mtd info structure
1273  * @chip: nand chip info structure
1274  * @buf: buffer to store read data
1275  * @page: page number to read
1276  *
1277  * Hardware ECC for large page chips, require OOB to be read first. For this
1278  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1279  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1280  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1281  * the data area, by overwriting the NAND manufacturer bad block markings.
1282  */
1283 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1284         struct nand_chip *chip, uint8_t *buf, int page)
1285 {
1286         int i, eccsize = chip->ecc.size;
1287         int eccbytes = chip->ecc.bytes;
1288         int eccsteps = chip->ecc.steps;
1289         uint8_t *p = buf;
1290         uint8_t *ecc_code = chip->buffers->ecccode;
1291         uint32_t *eccpos = chip->ecc.layout->eccpos;
1292         uint8_t *ecc_calc = chip->buffers->ecccalc;
1293
1294         /* Read the OOB area first */
1295         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1296         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1297         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1298
1299         for (i = 0; i < chip->ecc.total; i++)
1300                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1301
1302         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1303                 int stat;
1304
1305                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1306                 chip->read_buf(mtd, p, eccsize);
1307                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1308
1309                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1310                 if (stat < 0)
1311                         mtd->ecc_stats.failed++;
1312                 else
1313                         mtd->ecc_stats.corrected += stat;
1314         }
1315         return 0;
1316 }
1317
1318 /**
1319  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1320  * @mtd: mtd info structure
1321  * @chip: nand chip info structure
1322  * @buf: buffer to store read data
1323  * @page: page number to read
1324  *
1325  * The hw generator calculates the error syndrome automatically. Therefore we
1326  * need a special oob layout and handling.
1327  */
1328 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1329                                    uint8_t *buf, int page)
1330 {
1331         int i, eccsize = chip->ecc.size;
1332         int eccbytes = chip->ecc.bytes;
1333         int eccsteps = chip->ecc.steps;
1334         uint8_t *p = buf;
1335         uint8_t *oob = chip->oob_poi;
1336
1337         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1338                 int stat;
1339
1340                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1341                 chip->read_buf(mtd, p, eccsize);
1342
1343                 if (chip->ecc.prepad) {
1344                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1345                         oob += chip->ecc.prepad;
1346                 }
1347
1348                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1349                 chip->read_buf(mtd, oob, eccbytes);
1350                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1351
1352                 if (stat < 0)
1353                         mtd->ecc_stats.failed++;
1354                 else
1355                         mtd->ecc_stats.corrected += stat;
1356
1357                 oob += eccbytes;
1358
1359                 if (chip->ecc.postpad) {
1360                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1361                         oob += chip->ecc.postpad;
1362                 }
1363         }
1364
1365         /* Calculate remaining oob bytes */
1366         i = mtd->oobsize - (oob - chip->oob_poi);
1367         if (i)
1368                 chip->read_buf(mtd, oob, i);
1369
1370         return 0;
1371 }
1372
1373 /**
1374  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1375  * @chip: nand chip structure
1376  * @oob: oob destination address
1377  * @ops: oob ops structure
1378  * @len: size of oob to transfer
1379  */
1380 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1381                                   struct mtd_oob_ops *ops, size_t len)
1382 {
1383         switch (ops->mode) {
1384
1385         case MTD_OOB_PLACE:
1386         case MTD_OOB_RAW:
1387                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1388                 return oob + len;
1389
1390         case MTD_OOB_AUTO: {
1391                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1392                 uint32_t boffs = 0, roffs = ops->ooboffs;
1393                 size_t bytes = 0;
1394
1395                 for (; free->length && len; free++, len -= bytes) {
1396                         /* Read request not from offset 0? */
1397                         if (unlikely(roffs)) {
1398                                 if (roffs >= free->length) {
1399                                         roffs -= free->length;
1400                                         continue;
1401                                 }
1402                                 boffs = free->offset + roffs;
1403                                 bytes = min_t(size_t, len,
1404                                               (free->length - roffs));
1405                                 roffs = 0;
1406                         } else {
1407                                 bytes = min_t(size_t, len, free->length);
1408                                 boffs = free->offset;
1409                         }
1410                         memcpy(oob, chip->oob_poi + boffs, bytes);
1411                         oob += bytes;
1412                 }
1413                 return oob;
1414         }
1415         default:
1416                 BUG();
1417         }
1418         return NULL;
1419 }
1420
1421 /**
1422  * nand_do_read_ops - [INTERN] Read data with ECC
1423  * @mtd: MTD device structure
1424  * @from: offset to read from
1425  * @ops: oob ops structure
1426  *
1427  * Internal function. Called with chip held.
1428  */
1429 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1430                             struct mtd_oob_ops *ops)
1431 {
1432         int chipnr, page, realpage, col, bytes, aligned;
1433         struct nand_chip *chip = mtd->priv;
1434         struct mtd_ecc_stats stats;
1435         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1436         int sndcmd = 1;
1437         int ret = 0;
1438         uint32_t readlen = ops->len;
1439         uint32_t oobreadlen = ops->ooblen;
1440         uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1441                 mtd->oobavail : mtd->oobsize;
1442
1443         uint8_t *bufpoi, *oob, *buf;
1444
1445         stats = mtd->ecc_stats;
1446
1447         chipnr = (int)(from >> chip->chip_shift);
1448         chip->select_chip(mtd, chipnr);
1449
1450         realpage = (int)(from >> chip->page_shift);
1451         page = realpage & chip->pagemask;
1452
1453         col = (int)(from & (mtd->writesize - 1));
1454
1455         buf = ops->datbuf;
1456         oob = ops->oobbuf;
1457
1458         while (1) {
1459                 bytes = min(mtd->writesize - col, readlen);
1460                 aligned = (bytes == mtd->writesize);
1461
1462                 /* Is the current page in the buffer? */
1463                 if (realpage != chip->pagebuf || oob) {
1464                         bufpoi = aligned ? buf : chip->buffers->databuf;
1465
1466                         if (likely(sndcmd)) {
1467                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1468                                 sndcmd = 0;
1469                         }
1470
1471                         /* Now read the page into the buffer */
1472                         if (unlikely(ops->mode == MTD_OOB_RAW))
1473                                 ret = chip->ecc.read_page_raw(mtd, chip,
1474                                                               bufpoi, page);
1475                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1476                                 ret = chip->ecc.read_subpage(mtd, chip,
1477                                                         col, bytes, bufpoi);
1478                         else
1479                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1480                                                           page);
1481                         if (ret < 0)
1482                                 break;
1483
1484                         /* Transfer not aligned data */
1485                         if (!aligned) {
1486                                 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1487                                     !(mtd->ecc_stats.failed - stats.failed))
1488                                         chip->pagebuf = realpage;
1489                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1490                         }
1491
1492                         buf += bytes;
1493
1494                         if (unlikely(oob)) {
1495
1496                                 int toread = min(oobreadlen, max_oobsize);
1497
1498                                 if (toread) {
1499                                         oob = nand_transfer_oob(chip,
1500                                                 oob, ops, toread);
1501                                         oobreadlen -= toread;
1502                                 }
1503                         }
1504
1505                         if (!(chip->options & NAND_NO_READRDY)) {
1506                                 /*
1507                                  * Apply delay or wait for ready/busy pin. Do
1508                                  * this before the AUTOINCR check, so no
1509                                  * problems arise if a chip which does auto
1510                                  * increment is marked as NOAUTOINCR by the
1511                                  * board driver.
1512                                  */
1513                                 if (!chip->dev_ready)
1514                                         udelay(chip->chip_delay);
1515                                 else
1516                                         nand_wait_ready(mtd);
1517                         }
1518                 } else {
1519                         memcpy(buf, chip->buffers->databuf + col, bytes);
1520                         buf += bytes;
1521                 }
1522
1523                 readlen -= bytes;
1524
1525                 if (!readlen)
1526                         break;
1527
1528                 /* For subsequent reads align to page boundary */
1529                 col = 0;
1530                 /* Increment page address */
1531                 realpage++;
1532
1533                 page = realpage & chip->pagemask;
1534                 /* Check, if we cross a chip boundary */
1535                 if (!page) {
1536                         chipnr++;
1537                         chip->select_chip(mtd, -1);
1538                         chip->select_chip(mtd, chipnr);
1539                 }
1540
1541                 /*
1542                  * Check, if the chip supports auto page increment or if we
1543                  * have hit a block boundary.
1544                  */
1545                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1546                         sndcmd = 1;
1547         }
1548
1549         ops->retlen = ops->len - (size_t) readlen;
1550         if (oob)
1551                 ops->oobretlen = ops->ooblen - oobreadlen;
1552
1553         if (ret)
1554                 return ret;
1555
1556         if (mtd->ecc_stats.failed - stats.failed)
1557                 return -EBADMSG;
1558
1559         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1560 }
1561
1562 /**
1563  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1564  * @mtd: MTD device structure
1565  * @from: offset to read from
1566  * @len: number of bytes to read
1567  * @retlen: pointer to variable to store the number of read bytes
1568  * @buf: the databuffer to put data
1569  *
1570  * Get hold of the chip and call nand_do_read.
1571  */
1572 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1573                      size_t *retlen, uint8_t *buf)
1574 {
1575         struct nand_chip *chip = mtd->priv;
1576         int ret;
1577
1578         /* Do not allow reads past end of device */
1579         if ((from + len) > mtd->size)
1580                 return -EINVAL;
1581         if (!len)
1582                 return 0;
1583
1584         nand_get_device(chip, mtd, FL_READING);
1585
1586         chip->ops.len = len;
1587         chip->ops.datbuf = buf;
1588         chip->ops.oobbuf = NULL;
1589
1590         ret = nand_do_read_ops(mtd, from, &chip->ops);
1591
1592         *retlen = chip->ops.retlen;
1593
1594         nand_release_device(mtd);
1595
1596         return ret;
1597 }
1598
1599 /**
1600  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1601  * @mtd: mtd info structure
1602  * @chip: nand chip info structure
1603  * @page: page number to read
1604  * @sndcmd: flag whether to issue read command or not
1605  */
1606 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1607                              int page, int sndcmd)
1608 {
1609         if (sndcmd) {
1610                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1611                 sndcmd = 0;
1612         }
1613         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1614         return sndcmd;
1615 }
1616
1617 /**
1618  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1619  *                          with syndromes
1620  * @mtd: mtd info structure
1621  * @chip: nand chip info structure
1622  * @page: page number to read
1623  * @sndcmd: flag whether to issue read command or not
1624  */
1625 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1626                                   int page, int sndcmd)
1627 {
1628         uint8_t *buf = chip->oob_poi;
1629         int length = mtd->oobsize;
1630         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1631         int eccsize = chip->ecc.size;
1632         uint8_t *bufpoi = buf;
1633         int i, toread, sndrnd = 0, pos;
1634
1635         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1636         for (i = 0; i < chip->ecc.steps; i++) {
1637                 if (sndrnd) {
1638                         pos = eccsize + i * (eccsize + chunk);
1639                         if (mtd->writesize > 512)
1640                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1641                         else
1642                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1643                 } else
1644                         sndrnd = 1;
1645                 toread = min_t(int, length, chunk);
1646                 chip->read_buf(mtd, bufpoi, toread);
1647                 bufpoi += toread;
1648                 length -= toread;
1649         }
1650         if (length > 0)
1651                 chip->read_buf(mtd, bufpoi, length);
1652
1653         return 1;
1654 }
1655
1656 /**
1657  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1658  * @mtd: mtd info structure
1659  * @chip: nand chip info structure
1660  * @page: page number to write
1661  */
1662 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1663                               int page)
1664 {
1665         int status = 0;
1666         const uint8_t *buf = chip->oob_poi;
1667         int length = mtd->oobsize;
1668
1669         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1670         chip->write_buf(mtd, buf, length);
1671         /* Send command to program the OOB data */
1672         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1673
1674         status = chip->waitfunc(mtd, chip);
1675
1676         return status & NAND_STATUS_FAIL ? -EIO : 0;
1677 }
1678
1679 /**
1680  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1681  *                           with syndrome - only for large page flash
1682  * @mtd: mtd info structure
1683  * @chip: nand chip info structure
1684  * @page: page number to write
1685  */
1686 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1687                                    struct nand_chip *chip, int page)
1688 {
1689         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1690         int eccsize = chip->ecc.size, length = mtd->oobsize;
1691         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1692         const uint8_t *bufpoi = chip->oob_poi;
1693
1694         /*
1695          * data-ecc-data-ecc ... ecc-oob
1696          * or
1697          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1698          */
1699         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1700                 pos = steps * (eccsize + chunk);
1701                 steps = 0;
1702         } else
1703                 pos = eccsize;
1704
1705         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1706         for (i = 0; i < steps; i++) {
1707                 if (sndcmd) {
1708                         if (mtd->writesize <= 512) {
1709                                 uint32_t fill = 0xFFFFFFFF;
1710
1711                                 len = eccsize;
1712                                 while (len > 0) {
1713                                         int num = min_t(int, len, 4);
1714                                         chip->write_buf(mtd, (uint8_t *)&fill,
1715                                                         num);
1716                                         len -= num;
1717                                 }
1718                         } else {
1719                                 pos = eccsize + i * (eccsize + chunk);
1720                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1721                         }
1722                 } else
1723                         sndcmd = 1;
1724                 len = min_t(int, length, chunk);
1725                 chip->write_buf(mtd, bufpoi, len);
1726                 bufpoi += len;
1727                 length -= len;
1728         }
1729         if (length > 0)
1730                 chip->write_buf(mtd, bufpoi, length);
1731
1732         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1733         status = chip->waitfunc(mtd, chip);
1734
1735         return status & NAND_STATUS_FAIL ? -EIO : 0;
1736 }
1737
1738 /**
1739  * nand_do_read_oob - [INTERN] NAND read out-of-band
1740  * @mtd: MTD device structure
1741  * @from: offset to read from
1742  * @ops: oob operations description structure
1743  *
1744  * NAND read out-of-band data from the spare area.
1745  */
1746 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1747                             struct mtd_oob_ops *ops)
1748 {
1749         int page, realpage, chipnr, sndcmd = 1;
1750         struct nand_chip *chip = mtd->priv;
1751         struct mtd_ecc_stats stats;
1752         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1753         int readlen = ops->ooblen;
1754         int len;
1755         uint8_t *buf = ops->oobbuf;
1756
1757         pr_debug("%s: from = 0x%08Lx, len = %i\n",
1758                         __func__, (unsigned long long)from, readlen);
1759
1760         stats = mtd->ecc_stats;
1761
1762         if (ops->mode == MTD_OOB_AUTO)
1763                 len = chip->ecc.layout->oobavail;
1764         else
1765                 len = mtd->oobsize;
1766
1767         if (unlikely(ops->ooboffs >= len)) {
1768                 pr_debug("%s: attempt to start read outside oob\n",
1769                                 __func__);
1770                 return -EINVAL;
1771         }
1772
1773         /* Do not allow reads past end of device */
1774         if (unlikely(from >= mtd->size ||
1775                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1776                                         (from >> chip->page_shift)) * len)) {
1777                 pr_debug("%s: attempt to read beyond end of device\n",
1778                                 __func__);
1779                 return -EINVAL;
1780         }
1781
1782         chipnr = (int)(from >> chip->chip_shift);
1783         chip->select_chip(mtd, chipnr);
1784
1785         /* Shift to get page */
1786         realpage = (int)(from >> chip->page_shift);
1787         page = realpage & chip->pagemask;
1788
1789         while (1) {
1790                 if (ops->mode == MTD_OOB_RAW)
1791                         sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd);
1792                 else
1793                         sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1794
1795                 len = min(len, readlen);
1796                 buf = nand_transfer_oob(chip, buf, ops, len);
1797
1798                 if (!(chip->options & NAND_NO_READRDY)) {
1799                         /*
1800                          * Apply delay or wait for ready/busy pin. Do this
1801                          * before the AUTOINCR check, so no problems arise if a
1802                          * chip which does auto increment is marked as
1803                          * NOAUTOINCR by the board driver.
1804                          */
1805                         if (!chip->dev_ready)
1806                                 udelay(chip->chip_delay);
1807                         else
1808                                 nand_wait_ready(mtd);
1809                 }
1810
1811                 readlen -= len;
1812                 if (!readlen)
1813                         break;
1814
1815                 /* Increment page address */
1816                 realpage++;
1817
1818                 page = realpage & chip->pagemask;
1819                 /* Check, if we cross a chip boundary */
1820                 if (!page) {
1821                         chipnr++;
1822                         chip->select_chip(mtd, -1);
1823                         chip->select_chip(mtd, chipnr);
1824                 }
1825
1826                 /*
1827                  * Check, if the chip supports auto page increment or if we
1828                  * have hit a block boundary.
1829                  */
1830                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1831                         sndcmd = 1;
1832         }
1833
1834         ops->oobretlen = ops->ooblen;
1835
1836         if (mtd->ecc_stats.failed - stats.failed)
1837                 return -EBADMSG;
1838
1839         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1840 }
1841
1842 /**
1843  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1844  * @mtd: MTD device structure
1845  * @from: offset to read from
1846  * @ops: oob operation description structure
1847  *
1848  * NAND read data and/or out-of-band data.
1849  */
1850 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1851                          struct mtd_oob_ops *ops)
1852 {
1853         struct nand_chip *chip = mtd->priv;
1854         int ret = -ENOTSUPP;
1855
1856         ops->retlen = 0;
1857
1858         /* Do not allow reads past end of device */
1859         if (ops->datbuf && (from + ops->len) > mtd->size) {
1860                 pr_debug("%s: attempt to read beyond end of device\n",
1861                                 __func__);
1862                 return -EINVAL;
1863         }
1864
1865         nand_get_device(chip, mtd, FL_READING);
1866
1867         switch (ops->mode) {
1868         case MTD_OOB_PLACE:
1869         case MTD_OOB_AUTO:
1870         case MTD_OOB_RAW:
1871                 break;
1872
1873         default:
1874                 goto out;
1875         }
1876
1877         if (!ops->datbuf)
1878                 ret = nand_do_read_oob(mtd, from, ops);
1879         else
1880                 ret = nand_do_read_ops(mtd, from, ops);
1881
1882 out:
1883         nand_release_device(mtd);
1884         return ret;
1885 }
1886
1887
1888 /**
1889  * nand_write_page_raw - [INTERN] raw page write function
1890  * @mtd: mtd info structure
1891  * @chip: nand chip info structure
1892  * @buf: data buffer
1893  *
1894  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1895  */
1896 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1897                                 const uint8_t *buf)
1898 {
1899         chip->write_buf(mtd, buf, mtd->writesize);
1900         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1901 }
1902
1903 /**
1904  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1905  * @mtd: mtd info structure
1906  * @chip: nand chip info structure
1907  * @buf: data buffer
1908  *
1909  * We need a special oob layout and handling even when ECC isn't checked.
1910  */
1911 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1912                                         struct nand_chip *chip,
1913                                         const uint8_t *buf)
1914 {
1915         int eccsize = chip->ecc.size;
1916         int eccbytes = chip->ecc.bytes;
1917         uint8_t *oob = chip->oob_poi;
1918         int steps, size;
1919
1920         for (steps = chip->ecc.steps; steps > 0; steps--) {
1921                 chip->write_buf(mtd, buf, eccsize);
1922                 buf += eccsize;
1923
1924                 if (chip->ecc.prepad) {
1925                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1926                         oob += chip->ecc.prepad;
1927                 }
1928
1929                 chip->read_buf(mtd, oob, eccbytes);
1930                 oob += eccbytes;
1931
1932                 if (chip->ecc.postpad) {
1933                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1934                         oob += chip->ecc.postpad;
1935                 }
1936         }
1937
1938         size = mtd->oobsize - (oob - chip->oob_poi);
1939         if (size)
1940                 chip->write_buf(mtd, oob, size);
1941 }
1942 /**
1943  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1944  * @mtd: mtd info structure
1945  * @chip: nand chip info structure
1946  * @buf: data buffer
1947  */
1948 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1949                                   const uint8_t *buf)
1950 {
1951         int i, eccsize = chip->ecc.size;
1952         int eccbytes = chip->ecc.bytes;
1953         int eccsteps = chip->ecc.steps;
1954         uint8_t *ecc_calc = chip->buffers->ecccalc;
1955         const uint8_t *p = buf;
1956         uint32_t *eccpos = chip->ecc.layout->eccpos;
1957
1958         /* Software ECC calculation */
1959         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1960                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1961
1962         for (i = 0; i < chip->ecc.total; i++)
1963                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1964
1965         chip->ecc.write_page_raw(mtd, chip, buf);
1966 }
1967
1968 /**
1969  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1970  * @mtd: mtd info structure
1971  * @chip: nand chip info structure
1972  * @buf: data buffer
1973  */
1974 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1975                                   const uint8_t *buf)
1976 {
1977         int i, eccsize = chip->ecc.size;
1978         int eccbytes = chip->ecc.bytes;
1979         int eccsteps = chip->ecc.steps;
1980         uint8_t *ecc_calc = chip->buffers->ecccalc;
1981         const uint8_t *p = buf;
1982         uint32_t *eccpos = chip->ecc.layout->eccpos;
1983
1984         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1985                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1986                 chip->write_buf(mtd, p, eccsize);
1987                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1988         }
1989
1990         for (i = 0; i < chip->ecc.total; i++)
1991                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1992
1993         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1994 }
1995
1996 /**
1997  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1998  * @mtd: mtd info structure
1999  * @chip: nand chip info structure
2000  * @buf: data buffer
2001  *
2002  * The hw generator calculates the error syndrome automatically. Therefore we
2003  * need a special oob layout and handling.
2004  */
2005 static void nand_write_page_syndrome(struct mtd_info *mtd,
2006                                     struct nand_chip *chip, const uint8_t *buf)
2007 {
2008         int i, eccsize = chip->ecc.size;
2009         int eccbytes = chip->ecc.bytes;
2010         int eccsteps = chip->ecc.steps;
2011         const uint8_t *p = buf;
2012         uint8_t *oob = chip->oob_poi;
2013
2014         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2015
2016                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2017                 chip->write_buf(mtd, p, eccsize);
2018
2019                 if (chip->ecc.prepad) {
2020                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2021                         oob += chip->ecc.prepad;
2022                 }
2023
2024                 chip->ecc.calculate(mtd, p, oob);
2025                 chip->write_buf(mtd, oob, eccbytes);
2026                 oob += eccbytes;
2027
2028                 if (chip->ecc.postpad) {
2029                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2030                         oob += chip->ecc.postpad;
2031                 }
2032         }
2033
2034         /* Calculate remaining oob bytes */
2035         i = mtd->oobsize - (oob - chip->oob_poi);
2036         if (i)
2037                 chip->write_buf(mtd, oob, i);
2038 }
2039
2040 /**
2041  * nand_write_page - [REPLACEABLE] write one page
2042  * @mtd: MTD device structure
2043  * @chip: NAND chip descriptor
2044  * @buf: the data to write
2045  * @page: page number to write
2046  * @cached: cached programming
2047  * @raw: use _raw version of write_page
2048  */
2049 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2050                            const uint8_t *buf, int page, int cached, int raw)
2051 {
2052         int status;
2053
2054         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2055
2056         if (unlikely(raw))
2057                 chip->ecc.write_page_raw(mtd, chip, buf);
2058         else
2059                 chip->ecc.write_page(mtd, chip, buf);
2060
2061         /*
2062          * Cached progamming disabled for now. Not sure if it's worth the
2063          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2064          */
2065         cached = 0;
2066
2067         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2068
2069                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2070                 status = chip->waitfunc(mtd, chip);
2071                 /*
2072                  * See if operation failed and additional status checks are
2073                  * available.
2074                  */
2075                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2076                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2077                                                page);
2078
2079                 if (status & NAND_STATUS_FAIL)
2080                         return -EIO;
2081         } else {
2082                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2083                 status = chip->waitfunc(mtd, chip);
2084         }
2085
2086 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2087         /* Send command to read back the data */
2088         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2089
2090         if (chip->verify_buf(mtd, buf, mtd->writesize))
2091                 return -EIO;
2092 #endif
2093         return 0;
2094 }
2095
2096 /**
2097  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2098  * @mtd: MTD device structure
2099  * @oob: oob data buffer
2100  * @len: oob data write length
2101  * @ops: oob ops structure
2102  */
2103 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2104                               struct mtd_oob_ops *ops)
2105 {
2106         struct nand_chip *chip = mtd->priv;
2107
2108         /*
2109          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2110          * data from a previous OOB read.
2111          */
2112         memset(chip->oob_poi, 0xff, mtd->oobsize);
2113
2114         switch (ops->mode) {
2115
2116         case MTD_OOB_PLACE:
2117         case MTD_OOB_RAW:
2118                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2119                 return oob + len;
2120
2121         case MTD_OOB_AUTO: {
2122                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2123                 uint32_t boffs = 0, woffs = ops->ooboffs;
2124                 size_t bytes = 0;
2125
2126                 for (; free->length && len; free++, len -= bytes) {
2127                         /* Write request not from offset 0? */
2128                         if (unlikely(woffs)) {
2129                                 if (woffs >= free->length) {
2130                                         woffs -= free->length;
2131                                         continue;
2132                                 }
2133                                 boffs = free->offset + woffs;
2134                                 bytes = min_t(size_t, len,
2135                                               (free->length - woffs));
2136                                 woffs = 0;
2137                         } else {
2138                                 bytes = min_t(size_t, len, free->length);
2139                                 boffs = free->offset;
2140                         }
2141                         memcpy(chip->oob_poi + boffs, oob, bytes);
2142                         oob += bytes;
2143                 }
2144                 return oob;
2145         }
2146         default:
2147                 BUG();
2148         }
2149         return NULL;
2150 }
2151
2152 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2153
2154 /**
2155  * nand_do_write_ops - [INTERN] NAND write with ECC
2156  * @mtd: MTD device structure
2157  * @to: offset to write to
2158  * @ops: oob operations description structure
2159  *
2160  * NAND write with ECC.
2161  */
2162 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2163                              struct mtd_oob_ops *ops)
2164 {
2165         int chipnr, realpage, page, blockmask, column;
2166         struct nand_chip *chip = mtd->priv;
2167         uint32_t writelen = ops->len;
2168
2169         uint32_t oobwritelen = ops->ooblen;
2170         uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2171                                 mtd->oobavail : mtd->oobsize;
2172
2173         uint8_t *oob = ops->oobbuf;
2174         uint8_t *buf = ops->datbuf;
2175         int ret, subpage;
2176
2177         ops->retlen = 0;
2178         if (!writelen)
2179                 return 0;
2180
2181         /* Reject writes, which are not page aligned */
2182         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2183                 pr_notice("%s: attempt to write non page aligned data\n",
2184                            __func__);
2185                 return -EINVAL;
2186         }
2187
2188         column = to & (mtd->writesize - 1);
2189         subpage = column || (writelen & (mtd->writesize - 1));
2190
2191         if (subpage && oob)
2192                 return -EINVAL;
2193
2194         chipnr = (int)(to >> chip->chip_shift);
2195         chip->select_chip(mtd, chipnr);
2196
2197         /* Check, if it is write protected */
2198         if (nand_check_wp(mtd))
2199                 return -EIO;
2200
2201         realpage = (int)(to >> chip->page_shift);
2202         page = realpage & chip->pagemask;
2203         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2204
2205         /* Invalidate the page cache, when we write to the cached page */
2206         if (to <= (chip->pagebuf << chip->page_shift) &&
2207             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2208                 chip->pagebuf = -1;
2209
2210         /* Don't allow multipage oob writes with offset */
2211         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2212                 return -EINVAL;
2213
2214         while (1) {
2215                 int bytes = mtd->writesize;
2216                 int cached = writelen > bytes && page != blockmask;
2217                 uint8_t *wbuf = buf;
2218
2219                 /* Partial page write? */
2220                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2221                         cached = 0;
2222                         bytes = min_t(int, bytes - column, (int) writelen);
2223                         chip->pagebuf = -1;
2224                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2225                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2226                         wbuf = chip->buffers->databuf;
2227                 }
2228
2229                 if (unlikely(oob)) {
2230                         size_t len = min(oobwritelen, oobmaxlen);
2231                         oob = nand_fill_oob(mtd, oob, len, ops);
2232                         oobwritelen -= len;
2233                 } else {
2234                         /* We still need to erase leftover OOB data */
2235                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2236                 }
2237
2238                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2239                                        (ops->mode == MTD_OOB_RAW));
2240                 if (ret)
2241                         break;
2242
2243                 writelen -= bytes;
2244                 if (!writelen)
2245                         break;
2246
2247                 column = 0;
2248                 buf += bytes;
2249                 realpage++;
2250
2251                 page = realpage & chip->pagemask;
2252                 /* Check, if we cross a chip boundary */
2253                 if (!page) {
2254                         chipnr++;
2255                         chip->select_chip(mtd, -1);
2256                         chip->select_chip(mtd, chipnr);
2257                 }
2258         }
2259
2260         ops->retlen = ops->len - writelen;
2261         if (unlikely(oob))
2262                 ops->oobretlen = ops->ooblen;
2263         return ret;
2264 }
2265
2266 /**
2267  * panic_nand_write - [MTD Interface] NAND write with ECC
2268  * @mtd: MTD device structure
2269  * @to: offset to write to
2270  * @len: number of bytes to write
2271  * @retlen: pointer to variable to store the number of written bytes
2272  * @buf: the data to write
2273  *
2274  * NAND write with ECC. Used when performing writes in interrupt context, this
2275  * may for example be called by mtdoops when writing an oops while in panic.
2276  */
2277 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2278                             size_t *retlen, const uint8_t *buf)
2279 {
2280         struct nand_chip *chip = mtd->priv;
2281         int ret;
2282
2283         /* Do not allow reads past end of device */
2284         if ((to + len) > mtd->size)
2285                 return -EINVAL;
2286         if (!len)
2287                 return 0;
2288
2289         /* Wait for the device to get ready */
2290         panic_nand_wait(mtd, chip, 400);
2291
2292         /* Grab the device */
2293         panic_nand_get_device(chip, mtd, FL_WRITING);
2294
2295         chip->ops.len = len;
2296         chip->ops.datbuf = (uint8_t *)buf;
2297         chip->ops.oobbuf = NULL;
2298
2299         ret = nand_do_write_ops(mtd, to, &chip->ops);
2300
2301         *retlen = chip->ops.retlen;
2302         return ret;
2303 }
2304
2305 /**
2306  * nand_write - [MTD Interface] NAND write with ECC
2307  * @mtd: MTD device structure
2308  * @to: offset to write to
2309  * @len: number of bytes to write
2310  * @retlen: pointer to variable to store the number of written bytes
2311  * @buf: the data to write
2312  *
2313  * NAND write with ECC.
2314  */
2315 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2316                           size_t *retlen, const uint8_t *buf)
2317 {
2318         struct nand_chip *chip = mtd->priv;
2319         int ret;
2320
2321         /* Do not allow reads past end of device */
2322         if ((to + len) > mtd->size)
2323                 return -EINVAL;
2324         if (!len)
2325                 return 0;
2326
2327         nand_get_device(chip, mtd, FL_WRITING);
2328
2329         chip->ops.len = len;
2330         chip->ops.datbuf = (uint8_t *)buf;
2331         chip->ops.oobbuf = NULL;
2332
2333         ret = nand_do_write_ops(mtd, to, &chip->ops);
2334
2335         *retlen = chip->ops.retlen;
2336
2337         nand_release_device(mtd);
2338
2339         return ret;
2340 }
2341
2342 /**
2343  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2344  * @mtd: MTD device structure
2345  * @to: offset to write to
2346  * @ops: oob operation description structure
2347  *
2348  * NAND write out-of-band.
2349  */
2350 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2351                              struct mtd_oob_ops *ops)
2352 {
2353         int chipnr, page, status, len;
2354         struct nand_chip *chip = mtd->priv;
2355
2356         pr_debug("%s: to = 0x%08x, len = %i\n",
2357                          __func__, (unsigned int)to, (int)ops->ooblen);
2358
2359         if (ops->mode == MTD_OOB_AUTO)
2360                 len = chip->ecc.layout->oobavail;
2361         else
2362                 len = mtd->oobsize;
2363
2364         /* Do not allow write past end of page */
2365         if ((ops->ooboffs + ops->ooblen) > len) {
2366                 pr_debug("%s: attempt to write past end of page\n",
2367                                 __func__);
2368                 return -EINVAL;
2369         }
2370
2371         if (unlikely(ops->ooboffs >= len)) {
2372                 pr_debug("%s: attempt to start write outside oob\n",
2373                                 __func__);
2374                 return -EINVAL;
2375         }
2376
2377         /* Do not allow write past end of device */
2378         if (unlikely(to >= mtd->size ||
2379                      ops->ooboffs + ops->ooblen >
2380                         ((mtd->size >> chip->page_shift) -
2381                          (to >> chip->page_shift)) * len)) {
2382                 pr_debug("%s: attempt to write beyond end of device\n",
2383                                 __func__);
2384                 return -EINVAL;
2385         }
2386
2387         chipnr = (int)(to >> chip->chip_shift);
2388         chip->select_chip(mtd, chipnr);
2389
2390         /* Shift to get page */
2391         page = (int)(to >> chip->page_shift);
2392
2393         /*
2394          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2395          * of my DiskOnChip 2000 test units) will clear the whole data page too
2396          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2397          * it in the doc2000 driver in August 1999.  dwmw2.
2398          */
2399         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2400
2401         /* Check, if it is write protected */
2402         if (nand_check_wp(mtd))
2403                 return -EROFS;
2404
2405         /* Invalidate the page cache, if we write to the cached page */
2406         if (page == chip->pagebuf)
2407                 chip->pagebuf = -1;
2408
2409         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2410
2411         if (ops->mode == MTD_OOB_RAW)
2412                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2413         else
2414                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2415
2416         if (status)
2417                 return status;
2418
2419         ops->oobretlen = ops->ooblen;
2420
2421         return 0;
2422 }
2423
2424 /**
2425  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2426  * @mtd: MTD device structure
2427  * @to: offset to write to
2428  * @ops: oob operation description structure
2429  */
2430 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2431                           struct mtd_oob_ops *ops)
2432 {
2433         struct nand_chip *chip = mtd->priv;
2434         int ret = -ENOTSUPP;
2435
2436         ops->retlen = 0;
2437
2438         /* Do not allow writes past end of device */
2439         if (ops->datbuf && (to + ops->len) > mtd->size) {
2440                 pr_debug("%s: attempt to write beyond end of device\n",
2441                                 __func__);
2442                 return -EINVAL;
2443         }
2444
2445         nand_get_device(chip, mtd, FL_WRITING);
2446
2447         switch (ops->mode) {
2448         case MTD_OOB_PLACE:
2449         case MTD_OOB_AUTO:
2450         case MTD_OOB_RAW:
2451                 break;
2452
2453         default:
2454                 goto out;
2455         }
2456
2457         if (!ops->datbuf)
2458                 ret = nand_do_write_oob(mtd, to, ops);
2459         else
2460                 ret = nand_do_write_ops(mtd, to, ops);
2461
2462 out:
2463         nand_release_device(mtd);
2464         return ret;
2465 }
2466
2467 /**
2468  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2469  * @mtd: MTD device structure
2470  * @page: the page address of the block which will be erased
2471  *
2472  * Standard erase command for NAND chips.
2473  */
2474 static void single_erase_cmd(struct mtd_info *mtd, int page)
2475 {
2476         struct nand_chip *chip = mtd->priv;
2477         /* Send commands to erase a block */
2478         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2479         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2480 }
2481
2482 /**
2483  * multi_erase_cmd - [GENERIC] AND specific block erase command function
2484  * @mtd: MTD device structure
2485  * @page: the page address of the block which will be erased
2486  *
2487  * AND multi block erase command function. Erase 4 consecutive blocks.
2488  */
2489 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2490 {
2491         struct nand_chip *chip = mtd->priv;
2492         /* Send commands to erase a block */
2493         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2494         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2495         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2496         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2497         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2498 }
2499
2500 /**
2501  * nand_erase - [MTD Interface] erase block(s)
2502  * @mtd: MTD device structure
2503  * @instr: erase instruction
2504  *
2505  * Erase one ore more blocks.
2506  */
2507 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2508 {
2509         return nand_erase_nand(mtd, instr, 0);
2510 }
2511
2512 #define BBT_PAGE_MASK   0xffffff3f
2513 /**
2514  * nand_erase_nand - [INTERN] erase block(s)
2515  * @mtd: MTD device structure
2516  * @instr: erase instruction
2517  * @allowbbt: allow erasing the bbt area
2518  *
2519  * Erase one ore more blocks.
2520  */
2521 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2522                     int allowbbt)
2523 {
2524         int page, status, pages_per_block, ret, chipnr;
2525         struct nand_chip *chip = mtd->priv;
2526         loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2527         unsigned int bbt_masked_page = 0xffffffff;
2528         loff_t len;
2529
2530         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2531                         __func__, (unsigned long long)instr->addr,
2532                         (unsigned long long)instr->len);
2533
2534         if (check_offs_len(mtd, instr->addr, instr->len))
2535                 return -EINVAL;
2536
2537         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2538
2539         /* Grab the lock and see if the device is available */
2540         nand_get_device(chip, mtd, FL_ERASING);
2541
2542         /* Shift to get first page */
2543         page = (int)(instr->addr >> chip->page_shift);
2544         chipnr = (int)(instr->addr >> chip->chip_shift);
2545
2546         /* Calculate pages in each block */
2547         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2548
2549         /* Select the NAND device */
2550         chip->select_chip(mtd, chipnr);
2551
2552         /* Check, if it is write protected */
2553         if (nand_check_wp(mtd)) {
2554                 pr_debug("%s: device is write protected!\n",
2555                                 __func__);
2556                 instr->state = MTD_ERASE_FAILED;
2557                 goto erase_exit;
2558         }
2559
2560         /*
2561          * If BBT requires refresh, set the BBT page mask to see if the BBT
2562          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2563          * can not be matched. This is also done when the bbt is actually
2564          * erased to avoid recursive updates.
2565          */
2566         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2567                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2568
2569         /* Loop through the pages */
2570         len = instr->len;
2571
2572         instr->state = MTD_ERASING;
2573
2574         while (len) {
2575                 /* Heck if we have a bad block, we do not erase bad blocks! */
2576                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2577                                         chip->page_shift, 0, allowbbt)) {
2578                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2579                                     __func__, page);
2580                         instr->state = MTD_ERASE_FAILED;
2581                         goto erase_exit;
2582                 }
2583
2584                 /*
2585                  * Invalidate the page cache, if we erase the block which
2586                  * contains the current cached page.
2587                  */
2588                 if (page <= chip->pagebuf && chip->pagebuf <
2589                     (page + pages_per_block))
2590                         chip->pagebuf = -1;
2591
2592                 chip->erase_cmd(mtd, page & chip->pagemask);
2593
2594                 status = chip->waitfunc(mtd, chip);
2595
2596                 /*
2597                  * See if operation failed and additional status checks are
2598                  * available
2599                  */
2600                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2601                         status = chip->errstat(mtd, chip, FL_ERASING,
2602                                                status, page);
2603
2604                 /* See if block erase succeeded */
2605                 if (status & NAND_STATUS_FAIL) {
2606                         pr_debug("%s: failed erase, page 0x%08x\n",
2607                                         __func__, page);
2608                         instr->state = MTD_ERASE_FAILED;
2609                         instr->fail_addr =
2610                                 ((loff_t)page << chip->page_shift);
2611                         goto erase_exit;
2612                 }
2613
2614                 /*
2615                  * If BBT requires refresh, set the BBT rewrite flag to the
2616                  * page being erased.
2617                  */
2618                 if (bbt_masked_page != 0xffffffff &&
2619                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2620                             rewrite_bbt[chipnr] =
2621                                         ((loff_t)page << chip->page_shift);
2622
2623                 /* Increment page address and decrement length */
2624                 len -= (1 << chip->phys_erase_shift);
2625                 page += pages_per_block;
2626
2627                 /* Check, if we cross a chip boundary */
2628                 if (len && !(page & chip->pagemask)) {
2629                         chipnr++;
2630                         chip->select_chip(mtd, -1);
2631                         chip->select_chip(mtd, chipnr);
2632
2633                         /*
2634                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2635                          * page mask to see if this BBT should be rewritten.
2636                          */
2637                         if (bbt_masked_page != 0xffffffff &&
2638                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2639                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2640                                         BBT_PAGE_MASK;
2641                 }
2642         }
2643         instr->state = MTD_ERASE_DONE;
2644
2645 erase_exit:
2646
2647         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2648
2649         /* Deselect and wake up anyone waiting on the device */
2650         nand_release_device(mtd);
2651
2652         /* Do call back function */
2653         if (!ret)
2654                 mtd_erase_callback(instr);
2655
2656         /*
2657          * If BBT requires refresh and erase was successful, rewrite any
2658          * selected bad block tables.
2659          */
2660         if (bbt_masked_page == 0xffffffff || ret)
2661                 return ret;
2662
2663         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2664                 if (!rewrite_bbt[chipnr])
2665                         continue;
2666                 /* Update the BBT for chip */
2667                 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2668                                 __func__, chipnr, rewrite_bbt[chipnr],
2669                                 chip->bbt_td->pages[chipnr]);
2670                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2671         }
2672
2673         /* Return more or less happy */
2674         return ret;
2675 }
2676
2677 /**
2678  * nand_sync - [MTD Interface] sync
2679  * @mtd: MTD device structure
2680  *
2681  * Sync is actually a wait for chip ready function.
2682  */
2683 static void nand_sync(struct mtd_info *mtd)
2684 {
2685         struct nand_chip *chip = mtd->priv;
2686
2687         pr_debug("%s: called\n", __func__);
2688
2689         /* Grab the lock and see if the device is available */
2690         nand_get_device(chip, mtd, FL_SYNCING);
2691         /* Release it and go back */
2692         nand_release_device(mtd);
2693 }
2694
2695 /**
2696  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2697  * @mtd: MTD device structure
2698  * @offs: offset relative to mtd start
2699  */
2700 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2701 {
2702         /* Check for invalid offset */
2703         if (offs > mtd->size)
2704                 return -EINVAL;
2705
2706         return nand_block_checkbad(mtd, offs, 1, 0);
2707 }
2708
2709 /**
2710  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2711  * @mtd: MTD device structure
2712  * @ofs: offset relative to mtd start
2713  */
2714 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2715 {
2716         struct nand_chip *chip = mtd->priv;
2717         int ret;
2718
2719         ret = nand_block_isbad(mtd, ofs);
2720         if (ret) {
2721                 /* If it was bad already, return success and do nothing */
2722                 if (ret > 0)
2723                         return 0;
2724                 return ret;
2725         }
2726
2727         return chip->block_markbad(mtd, ofs);
2728 }
2729
2730 /**
2731  * nand_suspend - [MTD Interface] Suspend the NAND flash
2732  * @mtd: MTD device structure
2733  */
2734 static int nand_suspend(struct mtd_info *mtd)
2735 {
2736         struct nand_chip *chip = mtd->priv;
2737
2738         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2739 }
2740
2741 /**
2742  * nand_resume - [MTD Interface] Resume the NAND flash
2743  * @mtd: MTD device structure
2744  */
2745 static void nand_resume(struct mtd_info *mtd)
2746 {
2747         struct nand_chip *chip = mtd->priv;
2748
2749         if (chip->state == FL_PM_SUSPENDED)
2750                 nand_release_device(mtd);
2751         else
2752                 pr_err("%s called for a chip which is not in suspended state\n",
2753                         __func__);
2754 }
2755
2756 /* Set default functions */
2757 static void nand_set_defaults(struct nand_chip *chip, int busw)
2758 {
2759         /* check for proper chip_delay setup, set 20us if not */
2760         if (!chip->chip_delay)
2761                 chip->chip_delay = 20;
2762
2763         /* check, if a user supplied command function given */
2764         if (chip->cmdfunc == NULL)
2765                 chip->cmdfunc = nand_command;
2766
2767         /* check, if a user supplied wait function given */
2768         if (chip->waitfunc == NULL)
2769                 chip->waitfunc = nand_wait;
2770
2771         if (!chip->select_chip)
2772                 chip->select_chip = nand_select_chip;
2773         if (!chip->read_byte)
2774                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2775         if (!chip->read_word)
2776                 chip->read_word = nand_read_word;
2777         if (!chip->block_bad)
2778                 chip->block_bad = nand_block_bad;
2779         if (!chip->block_markbad)
2780                 chip->block_markbad = nand_default_block_markbad;
2781         if (!chip->write_buf)
2782                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2783         if (!chip->read_buf)
2784                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2785         if (!chip->verify_buf)
2786                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2787         if (!chip->scan_bbt)
2788                 chip->scan_bbt = nand_default_bbt;
2789
2790         if (!chip->controller) {
2791                 chip->controller = &chip->hwcontrol;
2792                 spin_lock_init(&chip->controller->lock);
2793                 init_waitqueue_head(&chip->controller->wq);
2794         }
2795
2796 }
2797
2798 /* Sanitize ONFI strings so we can safely print them */
2799 static void sanitize_string(uint8_t *s, size_t len)
2800 {
2801         ssize_t i;
2802
2803         /* Null terminate */
2804         s[len - 1] = 0;
2805
2806         /* Remove non printable chars */
2807         for (i = 0; i < len - 1; i++) {
2808                 if (s[i] < ' ' || s[i] > 127)
2809                         s[i] = '?';
2810         }
2811
2812         /* Remove trailing spaces */
2813         strim(s);
2814 }
2815
2816 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2817 {
2818         int i;
2819         while (len--) {
2820                 crc ^= *p++ << 8;
2821                 for (i = 0; i < 8; i++)
2822                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2823         }
2824
2825         return crc;
2826 }
2827
2828 /*
2829  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2830  */
2831 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2832                                         int *busw)
2833 {
2834         struct nand_onfi_params *p = &chip->onfi_params;
2835         int i;
2836         int val;
2837
2838         /* Try ONFI for unknown chip or LP */
2839         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2840         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2841                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2842                 return 0;
2843
2844         pr_info("ONFI flash detected\n");
2845         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2846         for (i = 0; i < 3; i++) {
2847                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2848                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2849                                 le16_to_cpu(p->crc)) {
2850                         pr_info("ONFI param page %d valid\n", i);
2851                         break;
2852                 }
2853         }
2854
2855         if (i == 3)
2856                 return 0;
2857
2858         /* Check version */
2859         val = le16_to_cpu(p->revision);
2860         if (val & (1 << 5))
2861                 chip->onfi_version = 23;
2862         else if (val & (1 << 4))
2863                 chip->onfi_version = 22;
2864         else if (val & (1 << 3))
2865                 chip->onfi_version = 21;
2866         else if (val & (1 << 2))
2867                 chip->onfi_version = 20;
2868         else if (val & (1 << 1))
2869                 chip->onfi_version = 10;
2870         else
2871                 chip->onfi_version = 0;
2872
2873         if (!chip->onfi_version) {
2874                 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2875                 return 0;
2876         }
2877
2878         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2879         sanitize_string(p->model, sizeof(p->model));
2880         if (!mtd->name)
2881                 mtd->name = p->model;
2882         mtd->writesize = le32_to_cpu(p->byte_per_page);
2883         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2884         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2885         chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2886         *busw = 0;
2887         if (le16_to_cpu(p->features) & 1)
2888                 *busw = NAND_BUSWIDTH_16;
2889
2890         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2891         chip->options |= (NAND_NO_READRDY |
2892                         NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2893
2894         return 1;
2895 }
2896
2897 /*
2898  * Get the flash and manufacturer id and lookup if the type is supported.
2899  */
2900 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2901                                                   struct nand_chip *chip,
2902                                                   int busw,
2903                                                   int *maf_id, int *dev_id,
2904                                                   struct nand_flash_dev *type)
2905 {
2906         int i, maf_idx;
2907         u8 id_data[8];
2908         int ret;
2909
2910         /* Select the device */
2911         chip->select_chip(mtd, 0);
2912
2913         /*
2914          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2915          * after power-up.
2916          */
2917         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2918
2919         /* Send the command for reading device ID */
2920         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2921
2922         /* Read manufacturer and device IDs */
2923         *maf_id = chip->read_byte(mtd);
2924         *dev_id = chip->read_byte(mtd);
2925
2926         /*
2927          * Try again to make sure, as some systems the bus-hold or other
2928          * interface concerns can cause random data which looks like a
2929          * possibly credible NAND flash to appear. If the two results do
2930          * not match, ignore the device completely.
2931          */
2932
2933         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2934
2935         for (i = 0; i < 2; i++)
2936                 id_data[i] = chip->read_byte(mtd);
2937
2938         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2939                 pr_info("%s: second ID read did not match "
2940                         "%02x,%02x against %02x,%02x\n", __func__,
2941                         *maf_id, *dev_id, id_data[0], id_data[1]);
2942                 return ERR_PTR(-ENODEV);
2943         }
2944
2945         if (!type)
2946                 type = nand_flash_ids;
2947
2948         for (; type->name != NULL; type++)
2949                 if (*dev_id == type->id)
2950                         break;
2951
2952         chip->onfi_version = 0;
2953         if (!type->name || !type->pagesize) {
2954                 /* Check is chip is ONFI compliant */
2955                 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2956                 if (ret)
2957                         goto ident_done;
2958         }
2959
2960         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2961
2962         /* Read entire ID string */
2963
2964         for (i = 0; i < 8; i++)
2965                 id_data[i] = chip->read_byte(mtd);
2966
2967         if (!type->name)
2968                 return ERR_PTR(-ENODEV);
2969
2970         if (!mtd->name)
2971                 mtd->name = type->name;
2972
2973         chip->chipsize = (uint64_t)type->chipsize << 20;
2974
2975         if (!type->pagesize && chip->init_size) {
2976                 /* Set the pagesize, oobsize, erasesize by the driver */
2977                 busw = chip->init_size(mtd, chip, id_data);
2978         } else if (!type->pagesize) {
2979                 int extid;
2980                 /* The 3rd id byte holds MLC / multichip data */
2981                 chip->cellinfo = id_data[2];
2982                 /* The 4th id byte is the important one */
2983                 extid = id_data[3];
2984
2985                 /*
2986                  * Field definitions are in the following datasheets:
2987                  * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2988                  * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
2989                  *
2990                  * Check for wraparound + Samsung ID + nonzero 6th byte
2991                  * to decide what to do.
2992                  */
2993                 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2994                                 id_data[0] == NAND_MFR_SAMSUNG &&
2995                                 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2996                                 id_data[5] != 0x00) {
2997                         /* Calc pagesize */
2998                         mtd->writesize = 2048 << (extid & 0x03);
2999                         extid >>= 2;
3000                         /* Calc oobsize */
3001                         switch (extid & 0x03) {
3002                         case 1:
3003                                 mtd->oobsize = 128;
3004                                 break;
3005                         case 2:
3006                                 mtd->oobsize = 218;
3007                                 break;
3008                         case 3:
3009                                 mtd->oobsize = 400;
3010                                 break;
3011                         default:
3012                                 mtd->oobsize = 436;
3013                                 break;
3014                         }
3015                         extid >>= 2;
3016                         /* Calc blocksize */
3017                         mtd->erasesize = (128 * 1024) <<
3018                                 (((extid >> 1) & 0x04) | (extid & 0x03));
3019                         busw = 0;
3020                 } else {
3021                         /* Calc pagesize */
3022                         mtd->writesize = 1024 << (extid & 0x03);
3023                         extid >>= 2;
3024                         /* Calc oobsize */
3025                         mtd->oobsize = (8 << (extid & 0x01)) *
3026                                 (mtd->writesize >> 9);
3027                         extid >>= 2;
3028                         /* Calc blocksize. Blocksize is multiples of 64KiB */
3029                         mtd->erasesize = (64 * 1024) << (extid & 0x03);
3030                         extid >>= 2;
3031                         /* Get buswidth information */
3032                         busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3033                 }
3034         } else {
3035                 /*
3036                  * Old devices have chip data hardcoded in the device id table.
3037                  */
3038                 mtd->erasesize = type->erasesize;
3039                 mtd->writesize = type->pagesize;
3040                 mtd->oobsize = mtd->writesize / 32;
3041                 busw = type->options & NAND_BUSWIDTH_16;
3042
3043                 /*
3044                  * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3045                  * some Spansion chips have erasesize that conflicts with size
3046                  * listed in nand_ids table.
3047                  * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3048                  */
3049                 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3050                                 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3051                                 id_data[7] == 0x00 && mtd->writesize == 512) {
3052                         mtd->erasesize = 128 * 1024;
3053                         mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3054                 }
3055         }
3056         /* Get chip options, preserve non chip based options */
3057         chip->options &= ~NAND_CHIPOPTIONS_MSK;
3058         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3059
3060         /*
3061          * Check if chip is not a Samsung device. Do not clear the
3062          * options for chips which do not have an extended id.
3063          */
3064         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3065                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3066 ident_done:
3067
3068         /*
3069          * Set chip as a default. Board drivers can override it, if necessary.
3070          */
3071         chip->options |= NAND_NO_AUTOINCR;
3072
3073         /* Try to identify manufacturer */
3074         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3075                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3076                         break;
3077         }
3078
3079         /*
3080          * Check, if buswidth is correct. Hardware drivers should set
3081          * chip correct!
3082          */
3083         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3084                 pr_info("NAND device: Manufacturer ID:"
3085                         " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3086                         *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3087                 pr_warn("NAND bus width %d instead %d bit\n",
3088                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3089                            busw ? 16 : 8);
3090                 return ERR_PTR(-EINVAL);
3091         }
3092
3093         /* Calculate the address shift from the page size */
3094         chip->page_shift = ffs(mtd->writesize) - 1;
3095         /* Convert chipsize to number of pages per chip -1 */
3096         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3097
3098         chip->bbt_erase_shift = chip->phys_erase_shift =
3099                 ffs(mtd->erasesize) - 1;
3100         if (chip->chipsize & 0xffffffff)
3101                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3102         else {
3103                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3104                 chip->chip_shift += 32 - 1;
3105         }
3106
3107         chip->badblockbits = 8;
3108
3109         /* Set the bad block position */
3110         if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3111                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3112         else
3113                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3114
3115         /*
3116          * Bad block marker is stored in the last page of each block
3117          * on Samsung and Hynix MLC devices; stored in first two pages
3118          * of each block on Micron devices with 2KiB pages and on
3119          * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3120          * only the first page.
3121          */
3122         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3123                         (*maf_id == NAND_MFR_SAMSUNG ||
3124                          *maf_id == NAND_MFR_HYNIX))
3125                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3126         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3127                                 (*maf_id == NAND_MFR_SAMSUNG ||
3128                                  *maf_id == NAND_MFR_HYNIX ||
3129                                  *maf_id == NAND_MFR_TOSHIBA ||
3130                                  *maf_id == NAND_MFR_AMD)) ||
3131                         (mtd->writesize == 2048 &&
3132                          *maf_id == NAND_MFR_MICRON))
3133                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3134
3135         /* Check for AND chips with 4 page planes */
3136         if (chip->options & NAND_4PAGE_ARRAY)
3137                 chip->erase_cmd = multi_erase_cmd;
3138         else
3139                 chip->erase_cmd = single_erase_cmd;
3140
3141         /* Do not replace user supplied command function! */
3142         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3143                 chip->cmdfunc = nand_command_lp;
3144
3145         pr_info("NAND device: Manufacturer ID:"
3146                 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3147                 nand_manuf_ids[maf_idx].name,
3148                 chip->onfi_version ? chip->onfi_params.model : type->name);
3149
3150         return type;
3151 }
3152
3153 /**
3154  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3155  * @mtd: MTD device structure
3156  * @maxchips: number of chips to scan for
3157  * @table: alternative NAND ID table
3158  *
3159  * This is the first phase of the normal nand_scan() function. It reads the
3160  * flash ID and sets up MTD fields accordingly.
3161  *
3162  * The mtd->owner field must be set to the module of the caller.
3163  */
3164 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3165                     struct nand_flash_dev *table)
3166 {
3167         int i, busw, nand_maf_id, nand_dev_id;
3168         struct nand_chip *chip = mtd->priv;
3169         struct nand_flash_dev *type;
3170
3171         /* Get buswidth to select the correct functions */
3172         busw = chip->options & NAND_BUSWIDTH_16;
3173         /* Set the default functions */
3174         nand_set_defaults(chip, busw);
3175
3176         /* Read the flash type */
3177         type = nand_get_flash_type(mtd, chip, busw,
3178                                 &nand_maf_id, &nand_dev_id, table);
3179
3180         if (IS_ERR(type)) {
3181                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3182                         pr_warn("No NAND device found\n");
3183                 chip->select_chip(mtd, -1);
3184                 return PTR_ERR(type);
3185         }
3186
3187         /* Check for a chip array */
3188         for (i = 1; i < maxchips; i++) {
3189                 chip->select_chip(mtd, i);
3190                 /* See comment in nand_get_flash_type for reset */
3191                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3192                 /* Send the command for reading device ID */
3193                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3194                 /* Read manufacturer and device IDs */
3195                 if (nand_maf_id != chip->read_byte(mtd) ||
3196                     nand_dev_id != chip->read_byte(mtd))
3197                         break;
3198         }
3199         if (i > 1)
3200                 pr_info("%d NAND chips detected\n", i);
3201
3202         /* Store the number of chips and calc total size for mtd */
3203         chip->numchips = i;
3204         mtd->size = i * chip->chipsize;
3205
3206         return 0;
3207 }
3208 EXPORT_SYMBOL(nand_scan_ident);
3209
3210
3211 /**
3212  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3213  * @mtd: MTD device structure
3214  *
3215  * This is the second phase of the normal nand_scan() function. It fills out
3216  * all the uninitialized function pointers with the defaults and scans for a
3217  * bad block table if appropriate.
3218  */
3219 int nand_scan_tail(struct mtd_info *mtd)
3220 {
3221         int i;
3222         struct nand_chip *chip = mtd->priv;
3223
3224         if (!(chip->options & NAND_OWN_BUFFERS))
3225                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3226         if (!chip->buffers)
3227                 return -ENOMEM;
3228
3229         /* Set the internal oob buffer location, just after the page data */
3230         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3231
3232         /*
3233          * If no default placement scheme is given, select an appropriate one.
3234          */
3235         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3236                 switch (mtd->oobsize) {
3237                 case 8:
3238                         chip->ecc.layout = &nand_oob_8;
3239                         break;
3240                 case 16:
3241                         chip->ecc.layout = &nand_oob_16;
3242                         break;
3243                 case 64:
3244                         chip->ecc.layout = &nand_oob_64;
3245                         break;
3246                 case 128:
3247                         chip->ecc.layout = &nand_oob_128;
3248                         break;
3249                 default:
3250                         pr_warn("No oob scheme defined for oobsize %d\n",
3251                                    mtd->oobsize);
3252                         BUG();
3253                 }
3254         }
3255
3256         if (!chip->write_page)
3257                 chip->write_page = nand_write_page;
3258
3259         /*
3260          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3261          * selected and we have 256 byte pagesize fallback to software ECC
3262          */
3263
3264         switch (chip->ecc.mode) {
3265         case NAND_ECC_HW_OOB_FIRST:
3266                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3267                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3268                      !chip->ecc.hwctl) {
3269                         pr_warn("No ECC functions supplied; "
3270                                    "hardware ECC not possible\n");
3271                         BUG();
3272                 }
3273                 if (!chip->ecc.read_page)
3274                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3275
3276         case NAND_ECC_HW:
3277                 /* Use standard hwecc read page function? */
3278                 if (!chip->ecc.read_page)
3279                         chip->ecc.read_page = nand_read_page_hwecc;
3280                 if (!chip->ecc.write_page)
3281                         chip->ecc.write_page = nand_write_page_hwecc;
3282                 if (!chip->ecc.read_page_raw)
3283                         chip->ecc.read_page_raw = nand_read_page_raw;
3284                 if (!chip->ecc.write_page_raw)
3285                         chip->ecc.write_page_raw = nand_write_page_raw;
3286                 if (!chip->ecc.read_oob)
3287                         chip->ecc.read_oob = nand_read_oob_std;
3288                 if (!chip->ecc.write_oob)
3289                         chip->ecc.write_oob = nand_write_oob_std;
3290
3291         case NAND_ECC_HW_SYNDROME:
3292                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3293                      !chip->ecc.hwctl) &&
3294                     (!chip->ecc.read_page ||
3295                      chip->ecc.read_page == nand_read_page_hwecc ||
3296                      !chip->ecc.write_page ||
3297                      chip->ecc.write_page == nand_write_page_hwecc)) {
3298                         pr_warn("No ECC functions supplied; "
3299                                    "hardware ECC not possible\n");
3300                         BUG();
3301                 }
3302                 /* Use standard syndrome read/write page function? */
3303                 if (!chip->ecc.read_page)
3304                         chip->ecc.read_page = nand_read_page_syndrome;
3305                 if (!chip->ecc.write_page)
3306                         chip->ecc.write_page = nand_write_page_syndrome;
3307                 if (!chip->ecc.read_page_raw)
3308                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3309                 if (!chip->ecc.write_page_raw)
3310                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3311                 if (!chip->ecc.read_oob)
3312                         chip->ecc.read_oob = nand_read_oob_syndrome;
3313                 if (!chip->ecc.write_oob)
3314                         chip->ecc.write_oob = nand_write_oob_syndrome;
3315
3316                 if (mtd->writesize >= chip->ecc.size)
3317                         break;
3318                 pr_warn("%d byte HW ECC not possible on "
3319                            "%d byte page size, fallback to SW ECC\n",
3320                            chip->ecc.size, mtd->writesize);
3321                 chip->ecc.mode = NAND_ECC_SOFT;
3322
3323         case NAND_ECC_SOFT:
3324                 chip->ecc.calculate = nand_calculate_ecc;
3325                 chip->ecc.correct = nand_correct_data;
3326                 chip->ecc.read_page = nand_read_page_swecc;
3327                 chip->ecc.read_subpage = nand_read_subpage;
3328                 chip->ecc.write_page = nand_write_page_swecc;
3329                 chip->ecc.read_page_raw = nand_read_page_raw;
3330                 chip->ecc.write_page_raw = nand_write_page_raw;
3331                 chip->ecc.read_oob = nand_read_oob_std;
3332                 chip->ecc.write_oob = nand_write_oob_std;
3333                 if (!chip->ecc.size)
3334                         chip->ecc.size = 256;
3335                 chip->ecc.bytes = 3;
3336                 break;
3337
3338         case NAND_ECC_SOFT_BCH:
3339                 if (!mtd_nand_has_bch()) {
3340                         pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3341                         BUG();
3342                 }
3343                 chip->ecc.calculate = nand_bch_calculate_ecc;
3344                 chip->ecc.correct = nand_bch_correct_data;
3345                 chip->ecc.read_page = nand_read_page_swecc;
3346                 chip->ecc.read_subpage = nand_read_subpage;
3347                 chip->ecc.write_page = nand_write_page_swecc;
3348                 chip->ecc.read_page_raw = nand_read_page_raw;
3349                 chip->ecc.write_page_raw = nand_write_page_raw;
3350                 chip->ecc.read_oob = nand_read_oob_std;
3351                 chip->ecc.write_oob = nand_write_oob_std;
3352                 /*
3353                  * Board driver should supply ecc.size and ecc.bytes values to
3354                  * select how many bits are correctable; see nand_bch_init()
3355                  * for details. Otherwise, default to 4 bits for large page
3356                  * devices.
3357                  */
3358                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3359                         chip->ecc.size = 512;
3360                         chip->ecc.bytes = 7;
3361                 }
3362                 chip->ecc.priv = nand_bch_init(mtd,
3363                                                chip->ecc.size,
3364                                                chip->ecc.bytes,
3365                                                &chip->ecc.layout);
3366                 if (!chip->ecc.priv) {
3367                         pr_warn("BCH ECC initialization failed!\n");
3368                         BUG();
3369                 }
3370                 break;
3371
3372         case NAND_ECC_NONE:
3373                 pr_warn("NAND_ECC_NONE selected by board driver. "
3374                            "This is not recommended!\n");
3375                 chip->ecc.read_page = nand_read_page_raw;
3376                 chip->ecc.write_page = nand_write_page_raw;
3377                 chip->ecc.read_oob = nand_read_oob_std;
3378                 chip->ecc.read_page_raw = nand_read_page_raw;
3379                 chip->ecc.write_page_raw = nand_write_page_raw;
3380                 chip->ecc.write_oob = nand_write_oob_std;
3381                 chip->ecc.size = mtd->writesize;
3382                 chip->ecc.bytes = 0;
3383                 break;
3384
3385         default:
3386                 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3387                 BUG();
3388         }
3389
3390         /* For many systems, the standard OOB write also works for raw */
3391         if (!chip->ecc.read_oob_raw)
3392                 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3393         if (!chip->ecc.write_oob_raw)
3394                 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3395
3396         /*
3397          * The number of bytes available for a client to place data into
3398          * the out of band area.
3399          */
3400         chip->ecc.layout->oobavail = 0;
3401         for (i = 0; chip->ecc.layout->oobfree[i].length
3402                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3403                 chip->ecc.layout->oobavail +=
3404                         chip->ecc.layout->oobfree[i].length;
3405         mtd->oobavail = chip->ecc.layout->oobavail;
3406
3407         /*
3408          * Set the number of read / write steps for one page depending on ECC
3409          * mode.
3410          */
3411         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3412         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3413                 pr_warn("Invalid ECC parameters\n");
3414                 BUG();
3415         }
3416         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3417
3418         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3419         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3420             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3421                 switch (chip->ecc.steps) {
3422                 case 2:
3423                         mtd->subpage_sft = 1;
3424                         break;
3425                 case 4:
3426                 case 8:
3427                 case 16:
3428                         mtd->subpage_sft = 2;
3429                         break;
3430                 }
3431         }
3432         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3433
3434         /* Initialize state */
3435         chip->state = FL_READY;
3436
3437         /* De-select the device */
3438         chip->select_chip(mtd, -1);
3439
3440         /* Invalidate the pagebuffer reference */
3441         chip->pagebuf = -1;
3442
3443         /* Fill in remaining MTD driver data */
3444         mtd->type = MTD_NANDFLASH;
3445         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3446                                                 MTD_CAP_NANDFLASH;
3447         mtd->erase = nand_erase;
3448         mtd->point = NULL;
3449         mtd->unpoint = NULL;
3450         mtd->read = nand_read;
3451         mtd->write = nand_write;
3452         mtd->panic_write = panic_nand_write;
3453         mtd->read_oob = nand_read_oob;
3454         mtd->write_oob = nand_write_oob;
3455         mtd->sync = nand_sync;
3456         mtd->lock = NULL;
3457         mtd->unlock = NULL;
3458         mtd->suspend = nand_suspend;
3459         mtd->resume = nand_resume;
3460         mtd->block_isbad = nand_block_isbad;
3461         mtd->block_markbad = nand_block_markbad;
3462         mtd->writebufsize = mtd->writesize;
3463
3464         /* propagate ecc.layout to mtd_info */
3465         mtd->ecclayout = chip->ecc.layout;
3466
3467         /* Check, if we should skip the bad block table scan */
3468         if (chip->options & NAND_SKIP_BBTSCAN)
3469                 return 0;
3470
3471         /* Build bad block table */
3472         return chip->scan_bbt(mtd);
3473 }
3474 EXPORT_SYMBOL(nand_scan_tail);
3475
3476 /*
3477  * is_module_text_address() isn't exported, and it's mostly a pointless
3478  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3479  * to call us from in-kernel code if the core NAND support is modular.
3480  */
3481 #ifdef MODULE
3482 #define caller_is_module() (1)
3483 #else
3484 #define caller_is_module() \
3485         is_module_text_address((unsigned long)__builtin_return_address(0))
3486 #endif
3487
3488 /**
3489  * nand_scan - [NAND Interface] Scan for the NAND device
3490  * @mtd: MTD device structure
3491  * @maxchips: number of chips to scan for
3492  *
3493  * This fills out all the uninitialized function pointers with the defaults.
3494  * The flash ID is read and the mtd/chip structures are filled with the
3495  * appropriate values. The mtd->owner field must be set to the module of the
3496  * caller.
3497  */
3498 int nand_scan(struct mtd_info *mtd, int maxchips)
3499 {
3500         int ret;
3501
3502         /* Many callers got this wrong, so check for it for a while... */
3503         if (!mtd->owner && caller_is_module()) {
3504                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3505                 BUG();
3506         }
3507
3508         ret = nand_scan_ident(mtd, maxchips, NULL);
3509         if (!ret)
3510                 ret = nand_scan_tail(mtd);
3511         return ret;
3512 }
3513 EXPORT_SYMBOL(nand_scan);
3514
3515 /**
3516  * nand_release - [NAND Interface] Free resources held by the NAND device
3517  * @mtd: MTD device structure
3518  */
3519 void nand_release(struct mtd_info *mtd)
3520 {
3521         struct nand_chip *chip = mtd->priv;
3522
3523         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3524                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3525
3526         mtd_device_unregister(mtd);
3527
3528         /* Free bad block table memory */
3529         kfree(chip->bbt);
3530         if (!(chip->options & NAND_OWN_BUFFERS))
3531                 kfree(chip->buffers);
3532
3533         /* Free bad block descriptor memory */
3534         if (chip->badblock_pattern && chip->badblock_pattern->options
3535                         & NAND_BBT_DYNAMICSTRUCT)
3536                 kfree(chip->badblock_pattern);
3537 }
3538 EXPORT_SYMBOL_GPL(nand_release);
3539
3540 static int __init nand_base_init(void)
3541 {
3542         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3543         return 0;
3544 }
3545
3546 static void __exit nand_base_exit(void)
3547 {
3548         led_trigger_unregister_simple(nand_led_trigger);
3549 }
3550
3551 module_init(nand_base_init);
3552 module_exit(nand_base_exit);
3553
3554 MODULE_LICENSE("GPL");
3555 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3556 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3557 MODULE_DESCRIPTION("Generic NAND flash driver code");