drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 /* Define default oob placement schemes for large and small page devices */
  53 static struct nand_ecclayout nand_oob_8 = {
  54         .eccbytes = 3,
  55         .eccpos = {0, 1, 2},
  56         .oobfree = {
  57                 {.offset = 3,
  58                  .length = 2},
  59                 {.offset = 6,
  60                  .length = 2} }
  61 };
  62
  63 static struct nand_ecclayout nand_oob_16 = {
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {
  67                 {.offset = 8,
  68                  . length = 8} }
  69 };
  70
  71 static struct nand_ecclayout nand_oob_64 = {
  72         .eccbytes = 24,
  73         .eccpos = {
  74                    40, 41, 42, 43, 44, 45, 46, 47,
  75                    48, 49, 50, 51, 52, 53, 54, 55,
  76                    56, 57, 58, 59, 60, 61, 62, 63},
  77         .oobfree = {
  78                 {.offset = 2,
  79                  .length = 38} }
  80 };
  81
  82 static struct nand_ecclayout nand_oob_128 = {
  83         .eccbytes = 48,
  84         .eccpos = {
  85                    80, 81, 82, 83, 84, 85, 86, 87,
  86                    88, 89, 90, 91, 92, 93, 94, 95,
  87                    96, 97, 98, 99, 100, 101, 102, 103,
  88                    104, 105, 106, 107, 108, 109, 110, 111,
  89                    112, 113, 114, 115, 116, 117, 118, 119,
  90                    120, 121, 122, 123, 124, 125, 126, 127},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 78} }
  94 };
  95
  96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  97                            int new_state);
  98
  99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 100                              struct mtd_oob_ops *ops);
 101
 102 /*
 103  * For devices which display every fart in the system on a separate LED. Is
 104  * compiled away when LED support is disabled.
 105  */
 106 DEFINE_LED_TRIGGER(nand_led_trigger);
 107
 108 static int check_offs_len(struct mtd_info *mtd,
 109                                         loff_t ofs, uint64_t len)
 110 {
 111         struct nand_chip *chip = mtd->priv;
 112         int ret = 0;
 113
 114         /* Start address must align on block boundary */
 115         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 116                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 117                 ret = -EINVAL;
 118         }
 119
 120         /* Length must align on block boundary */
 121         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 122                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 123                                         __func__);
 124                 ret = -EINVAL;
 125         }
 126
 127         /* Do not allow past end of device */
 128         if (ofs + len > mtd->size) {
 129                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
 130                                         __func__);
 131                 ret = -EINVAL;
 132         }
 133
 134         return ret;
 135 }
 136
 137 /**
 138  * nand_release_device - [GENERIC] release chip
 139  * @mtd:        MTD device structure
 140  *
 141  * Deselect, release chip lock and wake up anyone waiting on the device
 142  */
 143 static void nand_release_device(struct mtd_info *mtd)
 144 {
 145         struct nand_chip *chip = mtd->priv;
 146
 147         /* De-select the NAND device */
 148         chip->select_chip(mtd, -1);
 149
 150         /* Release the controller and the chip */
 151         spin_lock(&chip->controller->lock);
 152         chip->controller->active = NULL;
 153         chip->state = FL_READY;
 154         wake_up(&chip->controller->wq);
 155         spin_unlock(&chip->controller->lock);
 156 }
 157
 158 /**
 159  * nand_read_byte - [DEFAULT] read one byte from the chip
 160  * @mtd:        MTD device structure
 161  *
 162  * Default read function for 8bit buswith
 163  */
 164 static uint8_t nand_read_byte(struct mtd_info *mtd)
 165 {
 166         struct nand_chip *chip = mtd->priv;
 167         return readb(chip->IO_ADDR_R);
 168 }
 169
 170 /**
 171  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 172  * @mtd:        MTD device structure
 173  *
 174  * Default read function for 16bit buswith with
 175  * endianess conversion
 176  */
 177 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 178 {
 179         struct nand_chip *chip = mtd->priv;
 180         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 181 }
 182
 183 /**
 184  * nand_read_word - [DEFAULT] read one word from the chip
 185  * @mtd:        MTD device structure
 186  *
 187  * Default read function for 16bit buswith without
 188  * endianess conversion
 189  */
 190 static u16 nand_read_word(struct mtd_info *mtd)
 191 {
 192         struct nand_chip *chip = mtd->priv;
 193         return readw(chip->IO_ADDR_R);
 194 }
 195
 196 /**
 197  * nand_select_chip - [DEFAULT] control CE line
 198  * @mtd:        MTD device structure
 199  * @chipnr:     chipnumber to select, -1 for deselect
 200  *
 201  * Default select function for 1 chip devices.
 202  */
 203 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 204 {
 205         struct nand_chip *chip = mtd->priv;
 206
 207         switch (chipnr) {
 208         case -1:
 209                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 210                 break;
 211         case 0:
 212                 break;
 213
 214         default:
 215                 BUG();
 216         }
 217 }
 218
 219 /**
 220  * nand_write_buf - [DEFAULT] write buffer to chip
 221  * @mtd:        MTD device structure
 222  * @buf:        data buffer
 223  * @len:        number of bytes to write
 224  *
 225  * Default write function for 8bit buswith
 226  */
 227 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 228 {
 229         int i;
 230         struct nand_chip *chip = mtd->priv;
 231
 232         for (i = 0; i < len; i++)
 233                 writeb(buf[i], chip->IO_ADDR_W);
 234 }
 235
 236 /**
 237  * nand_read_buf - [DEFAULT] read chip data into buffer
 238  * @mtd:        MTD device structure
 239  * @buf:        buffer to store date
 240  * @len:        number of bytes to read
 241  *
 242  * Default read function for 8bit buswith
 243  */
 244 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 245 {
 246         int i;
 247         struct nand_chip *chip = mtd->priv;
 248
 249         for (i = 0; i < len; i++)
 250                 buf[i] = readb(chip->IO_ADDR_R);
 251 }
 252
 253 /**
 254  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 255  * @mtd:        MTD device structure
 256  * @buf:        buffer containing the data to compare
 257  * @len:        number of bytes to compare
 258  *
 259  * Default verify function for 8bit buswith
 260  */
 261 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 262 {
 263         int i;
 264         struct nand_chip *chip = mtd->priv;
 265
 266         for (i = 0; i < len; i++)
 267                 if (buf[i] != readb(chip->IO_ADDR_R))
 268                         return -EFAULT;
 269         return 0;
 270 }
 271
 272 /**
 273  * nand_write_buf16 - [DEFAULT] write buffer to chip
 274  * @mtd:        MTD device structure
 275  * @buf:        data buffer
 276  * @len:        number of bytes to write
 277  *
 278  * Default write function for 16bit buswith
 279  */
 280 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 281 {
 282         int i;
 283         struct nand_chip *chip = mtd->priv;
 284         u16 *p = (u16 *) buf;
 285         len >>= 1;
 286
 287         for (i = 0; i < len; i++)
 288                 writew(p[i], chip->IO_ADDR_W);
 289
 290 }
 291
 292 /**
 293  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 294  * @mtd:        MTD device structure
 295  * @buf:        buffer to store date
 296  * @len:        number of bytes to read
 297  *
 298  * Default read function for 16bit buswith
 299  */
 300 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 301 {
 302         int i;
 303         struct nand_chip *chip = mtd->priv;
 304         u16 *p = (u16 *) buf;
 305         len >>= 1;
 306
 307         for (i = 0; i < len; i++)
 308                 p[i] = readw(chip->IO_ADDR_R);
 309 }
 310
 311 /**
 312  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 313  * @mtd:        MTD device structure
 314  * @buf:        buffer containing the data to compare
 315  * @len:        number of bytes to compare
 316  *
 317  * Default verify function for 16bit buswith
 318  */
 319 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 320 {
 321         int i;
 322         struct nand_chip *chip = mtd->priv;
 323         u16 *p = (u16 *) buf;
 324         len >>= 1;
 325
 326         for (i = 0; i < len; i++)
 327                 if (p[i] != readw(chip->IO_ADDR_R))
 328                         return -EFAULT;
 329
 330         return 0;
 331 }
 332
 333 /**
 334  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 335  * @mtd:        MTD device structure
 336  * @ofs:        offset from device start
 337  * @getchip:    0, if the chip is already selected
 338  *
 339  * Check, if the block is bad.
 340  */
 341 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 342 {
 343         int page, chipnr, res = 0;
 344         struct nand_chip *chip = mtd->priv;
 345         u16 bad;
 346
 347         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 348                 ofs += mtd->erasesize - mtd->writesize;
 349
 350         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 351
 352         if (getchip) {
 353                 chipnr = (int)(ofs >> chip->chip_shift);
 354
 355                 nand_get_device(chip, mtd, FL_READING);
 356
 357                 /* Select the NAND device */
 358                 chip->select_chip(mtd, chipnr);
 359         }
 360
 361         if (chip->options & NAND_BUSWIDTH_16) {
 362                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 363                               page);
 364                 bad = cpu_to_le16(chip->read_word(mtd));
 365                 if (chip->badblockpos & 0x1)
 366                         bad >>= 8;
 367                 else
 368                         bad &= 0xFF;
 369         } else {
 370                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 371                 bad = chip->read_byte(mtd);
 372         }
 373
 374         if (likely(chip->badblockbits == 8))
 375                 res = bad != 0xFF;
 376         else
 377                 res = hweight8(bad) < chip->badblockbits;
 378
 379         if (getchip)
 380                 nand_release_device(mtd);
 381
 382         return res;
 383 }
 384
 385 /**
 386  * nand_default_block_markbad - [DEFAULT] mark a block bad
 387  * @mtd:        MTD device structure
 388  * @ofs:        offset from device start
 389  *
 390  * This is the default implementation, which can be overridden by
 391  * a hardware specific driver.
 392 */
 393 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 394 {
 395         struct nand_chip *chip = mtd->priv;
 396         uint8_t buf[2] = { 0, 0 };
 397         int block, ret, i = 0;
 398
 399         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 400                 ofs += mtd->erasesize - mtd->writesize;
 401
 402         /* Get block number */
 403         block = (int)(ofs >> chip->bbt_erase_shift);
 404         if (chip->bbt)
 405                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 406
 407         /* Do we have a flash based bad block table ? */
 408         if (chip->bbt_options & NAND_USE_FLASH_BBT)
 409                 ret = nand_update_bbt(mtd, ofs);
 410         else {
 411                 nand_get_device(chip, mtd, FL_WRITING);
 412
 413                 /*
 414                  * Write to first two pages if necessary. If we write to more
 415                  * than one location, the first error encountered quits the
 416                  * procedure. We write two bytes per location, so we dont have
 417                  * to mess with 16 bit access.
 418                  */
 419                 do {
 420                         chip->ops.len = chip->ops.ooblen = 2;
 421                         chip->ops.datbuf = NULL;
 422                         chip->ops.oobbuf = buf;
 423                         chip->ops.ooboffs = chip->badblockpos & ~0x01;
 424
 425                         ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 426
 427                         i++;
 428                         ofs += mtd->writesize;
 429                 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
 430                                 i < 2);
 431
 432                 nand_release_device(mtd);
 433         }
 434         if (!ret)
 435                 mtd->ecc_stats.badblocks++;
 436
 437         return ret;
 438 }
 439
 440 /**
 441  * nand_check_wp - [GENERIC] check if the chip is write protected
 442  * @mtd:        MTD device structure
 443  * Check, if the device is write protected
 444  *
 445  * The function expects, that the device is already selected
 446  */
 447 static int nand_check_wp(struct mtd_info *mtd)
 448 {
 449         struct nand_chip *chip = mtd->priv;
 450
 451         /* broken xD cards report WP despite being writable */
 452         if (chip->options & NAND_BROKEN_XD)
 453                 return 0;
 454
 455         /* Check the WP bit */
 456         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 457         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 458 }
 459
 460 /**
 461  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 462  * @mtd:        MTD device structure
 463  * @ofs:        offset from device start
 464  * @getchip:    0, if the chip is already selected
 465  * @allowbbt:   1, if its allowed to access the bbt area
 466  *
 467  * Check, if the block is bad. Either by reading the bad block table or
 468  * calling of the scan function.
 469  */
 470 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 471                                int allowbbt)
 472 {
 473         struct nand_chip *chip = mtd->priv;
 474
 475         if (!chip->bbt)
 476                 return chip->block_bad(mtd, ofs, getchip);
 477
 478         /* Return info from the table */
 479         return nand_isbad_bbt(mtd, ofs, allowbbt);
 480 }
 481
 482 /**
 483  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 484  * @mtd:        MTD device structure
 485  * @timeo:      Timeout
 486  *
 487  * Helper function for nand_wait_ready used when needing to wait in interrupt
 488  * context.
 489  */
 490 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 491 {
 492         struct nand_chip *chip = mtd->priv;
 493         int i;
 494
 495         /* Wait for the device to get ready */
 496         for (i = 0; i < timeo; i++) {
 497                 if (chip->dev_ready(mtd))
 498                         break;
 499                 touch_softlockup_watchdog();
 500                 mdelay(1);
 501         }
 502 }
 503
 504 /*
 505  * Wait for the ready pin, after a command
 506  * The timeout is catched later.
 507  */
 508 void nand_wait_ready(struct mtd_info *mtd)
 509 {
 510         struct nand_chip *chip = mtd->priv;
 511         unsigned long timeo = jiffies + 2;
 512
 513         /* 400ms timeout */
 514         if (in_interrupt() || oops_in_progress)
 515                 return panic_nand_wait_ready(mtd, 400);
 516
 517         led_trigger_event(nand_led_trigger, LED_FULL);
 518         /* wait until command is processed or timeout occures */
 519         do {
 520                 if (chip->dev_ready(mtd))
 521                         break;
 522                 touch_softlockup_watchdog();
 523         } while (time_before(jiffies, timeo));
 524         led_trigger_event(nand_led_trigger, LED_OFF);
 525 }
 526 EXPORT_SYMBOL_GPL(nand_wait_ready);
 527
 528 /**
 529  * nand_command - [DEFAULT] Send command to NAND device
 530  * @mtd:        MTD device structure
 531  * @command:    the command to be sent
 532  * @column:     the column address for this command, -1 if none
 533  * @page_addr:  the page address for this command, -1 if none
 534  *
 535  * Send command to NAND device. This function is used for small page
 536  * devices (256/512 Bytes per page)
 537  */
 538 static void nand_command(struct mtd_info *mtd, unsigned int command,
 539                          int column, int page_addr)
 540 {
 541         register struct nand_chip *chip = mtd->priv;
 542         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 543
 544         /*
 545          * Write out the command to the device.
 546          */
 547         if (command == NAND_CMD_SEQIN) {
 548                 int readcmd;
 549
 550                 if (column >= mtd->writesize) {
 551                         /* OOB area */
 552                         column -= mtd->writesize;
 553                         readcmd = NAND_CMD_READOOB;
 554                 } else if (column < 256) {
 555                         /* First 256 bytes --> READ0 */
 556                         readcmd = NAND_CMD_READ0;
 557                 } else {
 558                         column -= 256;
 559                         readcmd = NAND_CMD_READ1;
 560                 }
 561                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 562                 ctrl &= ~NAND_CTRL_CHANGE;
 563         }
 564         chip->cmd_ctrl(mtd, command, ctrl);
 565
 566         /*
 567          * Address cycle, when necessary
 568          */
 569         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 570         /* Serially input address */
 571         if (column != -1) {
 572                 /* Adjust columns for 16 bit buswidth */
 573                 if (chip->options & NAND_BUSWIDTH_16)
 574                         column >>= 1;
 575                 chip->cmd_ctrl(mtd, column, ctrl);
 576                 ctrl &= ~NAND_CTRL_CHANGE;
 577         }
 578         if (page_addr != -1) {
 579                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 580                 ctrl &= ~NAND_CTRL_CHANGE;
 581                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 582                 /* One more address cycle for devices > 32MiB */
 583                 if (chip->chipsize > (32 << 20))
 584                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 585         }
 586         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 587
 588         /*
 589          * program and erase have their own busy handlers
 590          * status and sequential in needs no delay
 591          */
 592         switch (command) {
 593
 594         case NAND_CMD_PAGEPROG:
 595         case NAND_CMD_ERASE1:
 596         case NAND_CMD_ERASE2:
 597         case NAND_CMD_SEQIN:
 598         case NAND_CMD_STATUS:
 599                 return;
 600
 601         case NAND_CMD_RESET:
 602                 if (chip->dev_ready)
 603                         break;
 604                 udelay(chip->chip_delay);
 605                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 606                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 607                 chip->cmd_ctrl(mtd,
 608                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 609                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 610                                 ;
 611                 return;
 612
 613                 /* This applies to read commands */
 614         default:
 615                 /*
 616                  * If we don't have access to the busy pin, we apply the given
 617                  * command delay
 618                  */
 619                 if (!chip->dev_ready) {
 620                         udelay(chip->chip_delay);
 621                         return;
 622                 }
 623         }
 624         /* Apply this short delay always to ensure that we do wait tWB in
 625          * any case on any machine. */
 626         ndelay(100);
 627
 628         nand_wait_ready(mtd);
 629 }
 630
 631 /**
 632  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 633  * @mtd:        MTD device structure
 634  * @command:    the command to be sent
 635  * @column:     the column address for this command, -1 if none
 636  * @page_addr:  the page address for this command, -1 if none
 637  *
 638  * Send command to NAND device. This is the version for the new large page
 639  * devices We dont have the separate regions as we have in the small page
 640  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 641  */
 642 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 643                             int column, int page_addr)
 644 {
 645         register struct nand_chip *chip = mtd->priv;
 646
 647         /* Emulate NAND_CMD_READOOB */
 648         if (command == NAND_CMD_READOOB) {
 649                 column += mtd->writesize;
 650                 command = NAND_CMD_READ0;
 651         }
 652
 653         /* Command latch cycle */
 654         chip->cmd_ctrl(mtd, command & 0xff,
 655                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 656
 657         if (column != -1 || page_addr != -1) {
 658                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 659
 660                 /* Serially input address */
 661                 if (column != -1) {
 662                         /* Adjust columns for 16 bit buswidth */
 663                         if (chip->options & NAND_BUSWIDTH_16)
 664                                 column >>= 1;
 665                         chip->cmd_ctrl(mtd, column, ctrl);
 666                         ctrl &= ~NAND_CTRL_CHANGE;
 667                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 668                 }
 669                 if (page_addr != -1) {
 670                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 671                         chip->cmd_ctrl(mtd, page_addr >> 8,
 672                                        NAND_NCE | NAND_ALE);
 673                         /* One more address cycle for devices > 128MiB */
 674                         if (chip->chipsize > (128 << 20))
 675                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 676                                                NAND_NCE | NAND_ALE);
 677                 }
 678         }
 679         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 680
 681         /*
 682          * program and erase have their own busy handlers
 683          * status, sequential in, and deplete1 need no delay
 684          */
 685         switch (command) {
 686
 687         case NAND_CMD_CACHEDPROG:
 688         case NAND_CMD_PAGEPROG:
 689         case NAND_CMD_ERASE1:
 690         case NAND_CMD_ERASE2:
 691         case NAND_CMD_SEQIN:
 692         case NAND_CMD_RNDIN:
 693         case NAND_CMD_STATUS:
 694         case NAND_CMD_DEPLETE1:
 695                 return;
 696
 697                 /*
 698                  * read error status commands require only a short delay
 699                  */
 700         case NAND_CMD_STATUS_ERROR:
 701         case NAND_CMD_STATUS_ERROR0:
 702         case NAND_CMD_STATUS_ERROR1:
 703         case NAND_CMD_STATUS_ERROR2:
 704         case NAND_CMD_STATUS_ERROR3:
 705                 udelay(chip->chip_delay);
 706                 return;
 707
 708         case NAND_CMD_RESET:
 709                 if (chip->dev_ready)
 710                         break;
 711                 udelay(chip->chip_delay);
 712                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 713                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 714                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 715                                NAND_NCE | NAND_CTRL_CHANGE);
 716                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 717                                 ;
 718                 return;
 719
 720         case NAND_CMD_RNDOUT:
 721                 /* No ready / busy check necessary */
 722                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 723                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 724                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 725                                NAND_NCE | NAND_CTRL_CHANGE);
 726                 return;
 727
 728         case NAND_CMD_READ0:
 729                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 730                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 731                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 732                                NAND_NCE | NAND_CTRL_CHANGE);
 733
 734                 /* This applies to read commands */
 735         default:
 736                 /*
 737                  * If we don't have access to the busy pin, we apply the given
 738                  * command delay
 739                  */
 740                 if (!chip->dev_ready) {
 741                         udelay(chip->chip_delay);
 742                         return;
 743                 }
 744         }
 745
 746         /* Apply this short delay always to ensure that we do wait tWB in
 747          * any case on any machine. */
 748         ndelay(100);
 749
 750         nand_wait_ready(mtd);
 751 }
 752
 753 /**
 754  * panic_nand_get_device - [GENERIC] Get chip for selected access
 755  * @chip:       the nand chip descriptor
 756  * @mtd:        MTD device structure
 757  * @new_state:  the state which is requested
 758  *
 759  * Used when in panic, no locks are taken.
 760  */
 761 static void panic_nand_get_device(struct nand_chip *chip,
 762                       struct mtd_info *mtd, int new_state)
 763 {
 764         /* Hardware controller shared among independend devices */
 765         chip->controller->active = chip;
 766         chip->state = new_state;
 767 }
 768
 769 /**
 770  * nand_get_device - [GENERIC] Get chip for selected access
 771  * @chip:       the nand chip descriptor
 772  * @mtd:        MTD device structure
 773  * @new_state:  the state which is requested
 774  *
 775  * Get the device and lock it for exclusive access
 776  */
 777 static int
 778 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 779 {
 780         spinlock_t *lock = &chip->controller->lock;
 781         wait_queue_head_t *wq = &chip->controller->wq;
 782         DECLARE_WAITQUEUE(wait, current);
 783 retry:
 784         spin_lock(lock);
 785
 786         /* Hardware controller shared among independent devices */
 787         if (!chip->controller->active)
 788                 chip->controller->active = chip;
 789
 790         if (chip->controller->active == chip && chip->state == FL_READY) {
 791                 chip->state = new_state;
 792                 spin_unlock(lock);
 793                 return 0;
 794         }
 795         if (new_state == FL_PM_SUSPENDED) {
 796                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 797                         chip->state = FL_PM_SUSPENDED;
 798                         spin_unlock(lock);
 799                         return 0;
 800                 }
 801         }
 802         set_current_state(TASK_UNINTERRUPTIBLE);
 803         add_wait_queue(wq, &wait);
 804         spin_unlock(lock);
 805         schedule();
 806         remove_wait_queue(wq, &wait);
 807         goto retry;
 808 }
 809
 810 /**
 811  * panic_nand_wait - [GENERIC]  wait until the command is done
 812  * @mtd:        MTD device structure
 813  * @chip:       NAND chip structure
 814  * @timeo:      Timeout
 815  *
 816  * Wait for command done. This is a helper function for nand_wait used when
 817  * we are in interrupt context. May happen when in panic and trying to write
 818  * an oops through mtdoops.
 819  */
 820 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 821                             unsigned long timeo)
 822 {
 823         int i;
 824         for (i = 0; i < timeo; i++) {
 825                 if (chip->dev_ready) {
 826                         if (chip->dev_ready(mtd))
 827                                 break;
 828                 } else {
 829                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 830                                 break;
 831                 }
 832                 mdelay(1);
 833         }
 834 }
 835
 836 /**
 837  * nand_wait - [DEFAULT]  wait until the command is done
 838  * @mtd:        MTD device structure
 839  * @chip:       NAND chip structure
 840  *
 841  * Wait for command done. This applies to erase and program only
 842  * Erase can take up to 400ms and program up to 20ms according to
 843  * general NAND and SmartMedia specs
 844  */
 845 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 846 {
 847
 848         unsigned long timeo = jiffies;
 849         int status, state = chip->state;
 850
 851         if (state == FL_ERASING)
 852                 timeo += (HZ * 400) / 1000;
 853         else
 854                 timeo += (HZ * 20) / 1000;
 855
 856         led_trigger_event(nand_led_trigger, LED_FULL);
 857
 858         /* Apply this short delay always to ensure that we do wait tWB in
 859          * any case on any machine. */
 860         ndelay(100);
 861
 862         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 863                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 864         else
 865                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 866
 867         if (in_interrupt() || oops_in_progress)
 868                 panic_nand_wait(mtd, chip, timeo);
 869         else {
 870                 while (time_before(jiffies, timeo)) {
 871                         if (chip->dev_ready) {
 872                                 if (chip->dev_ready(mtd))
 873                                         break;
 874                         } else {
 875                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 876                                         break;
 877                         }
 878                         cond_resched();
 879                 }
 880         }
 881         led_trigger_event(nand_led_trigger, LED_OFF);
 882
 883         status = (int)chip->read_byte(mtd);
 884         return status;
 885 }
 886
 887 /**
 888  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 889  *
 890  * @mtd: mtd info
 891  * @ofs: offset to start unlock from
 892  * @len: length to unlock
 893  * @invert:   when = 0, unlock the range of blocks within the lower and
 894  *                      upper boundary address
 895  *            when = 1, unlock the range of blocks outside the boundaries
 896  *                      of the lower and upper boundary address
 897  *
 898  * return - unlock status
 899  */
 900 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 901                                         uint64_t len, int invert)
 902 {
 903         int ret = 0;
 904         int status, page;
 905         struct nand_chip *chip = mtd->priv;
 906
 907         /* Submit address of first page to unlock */
 908         page = ofs >> chip->page_shift;
 909         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 910
 911         /* Submit address of last page to unlock */
 912         page = (ofs + len) >> chip->page_shift;
 913         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 914                                 (page | invert) & chip->pagemask);
 915
 916         /* Call wait ready function */
 917         status = chip->waitfunc(mtd, chip);
 918         udelay(1000);
 919         /* See if device thinks it succeeded */
 920         if (status & 0x01) {
 921                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
 922                                         __func__, status);
 923                 ret = -EIO;
 924         }
 925
 926         return ret;
 927 }
 928
 929 /**
 930  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 931  *
 932  * @mtd: mtd info
 933  * @ofs: offset to start unlock from
 934  * @len: length to unlock
 935  *
 936  * return - unlock status
 937  */
 938 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 939 {
 940         int ret = 0;
 941         int chipnr;
 942         struct nand_chip *chip = mtd->priv;
 943
 944         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 945                         __func__, (unsigned long long)ofs, len);
 946
 947         if (check_offs_len(mtd, ofs, len))
 948                 ret = -EINVAL;
 949
 950         /* Align to last block address if size addresses end of the device */
 951         if (ofs + len == mtd->size)
 952                 len -= mtd->erasesize;
 953
 954         nand_get_device(chip, mtd, FL_UNLOCKING);
 955
 956         /* Shift to get chip number */
 957         chipnr = ofs >> chip->chip_shift;
 958
 959         chip->select_chip(mtd, chipnr);
 960
 961         /* Check, if it is write protected */
 962         if (nand_check_wp(mtd)) {
 963                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 964                                         __func__);
 965                 ret = -EIO;
 966                 goto out;
 967         }
 968
 969         ret = __nand_unlock(mtd, ofs, len, 0);
 970
 971 out:
 972         nand_release_device(mtd);
 973
 974         return ret;
 975 }
 976 EXPORT_SYMBOL(nand_unlock);
 977
 978 /**
 979  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 980  *
 981  * @mtd: mtd info
 982  * @ofs: offset to start unlock from
 983  * @len: length to unlock
 984  *
 985  * return - lock status
 986  *
 987  * This feature is not supported in many NAND parts. 'Micron' NAND parts
 988  * do have this feature, but it allows only to lock all blocks, not for
 989  * specified range for block.
 990  *
 991  * Implementing 'lock' feature by making use of 'unlock', for now.
 992  */
 993 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 994 {
 995         int ret = 0;
 996         int chipnr, status, page;
 997         struct nand_chip *chip = mtd->priv;
 998
 999         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1000                         __func__, (unsigned long long)ofs, len);
1001
1002         if (check_offs_len(mtd, ofs, len))
1003                 ret = -EINVAL;
1004
1005         nand_get_device(chip, mtd, FL_LOCKING);
1006
1007         /* Shift to get chip number */
1008         chipnr = ofs >> chip->chip_shift;
1009
1010         chip->select_chip(mtd, chipnr);
1011
1012         /* Check, if it is write protected */
1013         if (nand_check_wp(mtd)) {
1014                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1015                                         __func__);
1016                 status = MTD_ERASE_FAILED;
1017                 ret = -EIO;
1018                 goto out;
1019         }
1020
1021         /* Submit address of first page to lock */
1022         page = ofs >> chip->page_shift;
1023         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1024
1025         /* Call wait ready function */
1026         status = chip->waitfunc(mtd, chip);
1027         udelay(1000);
1028         /* See if device thinks it succeeded */
1029         if (status & 0x01) {
1030                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1031                                         __func__, status);
1032                 ret = -EIO;
1033                 goto out;
1034         }
1035
1036         ret = __nand_unlock(mtd, ofs, len, 0x1);
1037
1038 out:
1039         nand_release_device(mtd);
1040
1041         return ret;
1042 }
1043 EXPORT_SYMBOL(nand_lock);
1044
1045 /**
1046  * nand_read_page_raw - [Intern] read raw page data without ecc
1047  * @mtd:        mtd info structure
1048  * @chip:       nand chip info structure
1049  * @buf:        buffer to store read data
1050  * @page:       page number to read
1051  *
1052  * Not for syndrome calculating ecc controllers, which use a special oob layout
1053  */
1054 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1055                               uint8_t *buf, int page)
1056 {
1057         chip->read_buf(mtd, buf, mtd->writesize);
1058         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1059         return 0;
1060 }
1061
1062 /**
1063  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1064  * @mtd:        mtd info structure
1065  * @chip:       nand chip info structure
1066  * @buf:        buffer to store read data
1067  * @page:       page number to read
1068  *
1069  * We need a special oob layout and handling even when OOB isn't used.
1070  */
1071 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1072                                         struct nand_chip *chip,
1073                                         uint8_t *buf, int page)
1074 {
1075         int eccsize = chip->ecc.size;
1076         int eccbytes = chip->ecc.bytes;
1077         uint8_t *oob = chip->oob_poi;
1078         int steps, size;
1079
1080         for (steps = chip->ecc.steps; steps > 0; steps--) {
1081                 chip->read_buf(mtd, buf, eccsize);
1082                 buf += eccsize;
1083
1084                 if (chip->ecc.prepad) {
1085                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1086                         oob += chip->ecc.prepad;
1087                 }
1088
1089                 chip->read_buf(mtd, oob, eccbytes);
1090                 oob += eccbytes;
1091
1092                 if (chip->ecc.postpad) {
1093                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1094                         oob += chip->ecc.postpad;
1095                 }
1096         }
1097
1098         size = mtd->oobsize - (oob - chip->oob_poi);
1099         if (size)
1100                 chip->read_buf(mtd, oob, size);
1101
1102         return 0;
1103 }
1104
1105 /**
1106  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1107  * @mtd:        mtd info structure
1108  * @chip:       nand chip info structure
1109  * @buf:        buffer to store read data
1110  * @page:       page number to read
1111  */
1112 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1113                                 uint8_t *buf, int page)
1114 {
1115         int i, eccsize = chip->ecc.size;
1116         int eccbytes = chip->ecc.bytes;
1117         int eccsteps = chip->ecc.steps;
1118         uint8_t *p = buf;
1119         uint8_t *ecc_calc = chip->buffers->ecccalc;
1120         uint8_t *ecc_code = chip->buffers->ecccode;
1121         uint32_t *eccpos = chip->ecc.layout->eccpos;
1122
1123         chip->ecc.read_page_raw(mtd, chip, buf, page);
1124
1125         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1126                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1127
1128         for (i = 0; i < chip->ecc.total; i++)
1129                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1130
1131         eccsteps = chip->ecc.steps;
1132         p = buf;
1133
1134         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1135                 int stat;
1136
1137                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1138                 if (stat < 0)
1139                         mtd->ecc_stats.failed++;
1140                 else
1141                         mtd->ecc_stats.corrected += stat;
1142         }
1143         return 0;
1144 }
1145
1146 /**
1147  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1148  * @mtd:        mtd info structure
1149  * @chip:       nand chip info structure
1150  * @data_offs:  offset of requested data within the page
1151  * @readlen:    data length
1152  * @bufpoi:     buffer to store read data
1153  */
1154 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1155                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1156 {
1157         int start_step, end_step, num_steps;
1158         uint32_t *eccpos = chip->ecc.layout->eccpos;
1159         uint8_t *p;
1160         int data_col_addr, i, gaps = 0;
1161         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1162         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1163         int index = 0;
1164
1165         /* Column address wihin the page aligned to ECC size (256bytes). */
1166         start_step = data_offs / chip->ecc.size;
1167         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1168         num_steps = end_step - start_step + 1;
1169
1170         /* Data size aligned to ECC ecc.size*/
1171         datafrag_len = num_steps * chip->ecc.size;
1172         eccfrag_len = num_steps * chip->ecc.bytes;
1173
1174         data_col_addr = start_step * chip->ecc.size;
1175         /* If we read not a page aligned data */
1176         if (data_col_addr != 0)
1177                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1178
1179         p = bufpoi + data_col_addr;
1180         chip->read_buf(mtd, p, datafrag_len);
1181
1182         /* Calculate  ECC */
1183         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1184                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1185
1186         /* The performance is faster if to position offsets
1187            according to ecc.pos. Let make sure here that
1188            there are no gaps in ecc positions */
1189         for (i = 0; i < eccfrag_len - 1; i++) {
1190                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1191                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1192                         gaps = 1;
1193                         break;
1194                 }
1195         }
1196         if (gaps) {
1197                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1198                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1199         } else {
1200                 /* send the command to read the particular ecc bytes */
1201                 /* take care about buswidth alignment in read_buf */
1202                 index = start_step * chip->ecc.bytes;
1203
1204                 aligned_pos = eccpos[index] & ~(busw - 1);
1205                 aligned_len = eccfrag_len;
1206                 if (eccpos[index] & (busw - 1))
1207                         aligned_len++;
1208                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1209                         aligned_len++;
1210
1211                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1212                                         mtd->writesize + aligned_pos, -1);
1213                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1214         }
1215
1216         for (i = 0; i < eccfrag_len; i++)
1217                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1218
1219         p = bufpoi + data_col_addr;
1220         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1221                 int stat;
1222
1223                 stat = chip->ecc.correct(mtd, p,
1224                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1225                 if (stat < 0)
1226                         mtd->ecc_stats.failed++;
1227                 else
1228                         mtd->ecc_stats.corrected += stat;
1229         }
1230         return 0;
1231 }
1232
1233 /**
1234  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1235  * @mtd:        mtd info structure
1236  * @chip:       nand chip info structure
1237  * @buf:        buffer to store read data
1238  * @page:       page number to read
1239  *
1240  * Not for syndrome calculating ecc controllers which need a special oob layout
1241  */
1242 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1243                                 uint8_t *buf, int page)
1244 {
1245         int i, eccsize = chip->ecc.size;
1246         int eccbytes = chip->ecc.bytes;
1247         int eccsteps = chip->ecc.steps;
1248         uint8_t *p = buf;
1249         uint8_t *ecc_calc = chip->buffers->ecccalc;
1250         uint8_t *ecc_code = chip->buffers->ecccode;
1251         uint32_t *eccpos = chip->ecc.layout->eccpos;
1252
1253         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1254                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1255                 chip->read_buf(mtd, p, eccsize);
1256                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1257         }
1258         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1259
1260         for (i = 0; i < chip->ecc.total; i++)
1261                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1262
1263         eccsteps = chip->ecc.steps;
1264         p = buf;
1265
1266         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1267                 int stat;
1268
1269                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1270                 if (stat < 0)
1271                         mtd->ecc_stats.failed++;
1272                 else
1273                         mtd->ecc_stats.corrected += stat;
1274         }
1275         return 0;
1276 }
1277
1278 /**
1279  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1280  * @mtd:        mtd info structure
1281  * @chip:       nand chip info structure
1282  * @buf:        buffer to store read data
1283  * @page:       page number to read
1284  *
1285  * Hardware ECC for large page chips, require OOB to be read first.
1286  * For this ECC mode, the write_page method is re-used from ECC_HW.
1287  * These methods read/write ECC from the OOB area, unlike the
1288  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1289  * "infix ECC" scheme and reads/writes ECC from the data area, by
1290  * overwriting the NAND manufacturer bad block markings.
1291  */
1292 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1293         struct nand_chip *chip, uint8_t *buf, int page)
1294 {
1295         int i, eccsize = chip->ecc.size;
1296         int eccbytes = chip->ecc.bytes;
1297         int eccsteps = chip->ecc.steps;
1298         uint8_t *p = buf;
1299         uint8_t *ecc_code = chip->buffers->ecccode;
1300         uint32_t *eccpos = chip->ecc.layout->eccpos;
1301         uint8_t *ecc_calc = chip->buffers->ecccalc;
1302
1303         /* Read the OOB area first */
1304         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1305         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1306         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1307
1308         for (i = 0; i < chip->ecc.total; i++)
1309                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1310
1311         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1312                 int stat;
1313
1314                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1315                 chip->read_buf(mtd, p, eccsize);
1316                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1317
1318                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1319                 if (stat < 0)
1320                         mtd->ecc_stats.failed++;
1321                 else
1322                         mtd->ecc_stats.corrected += stat;
1323         }
1324         return 0;
1325 }
1326
1327 /**
1328  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1329  * @mtd:        mtd info structure
1330  * @chip:       nand chip info structure
1331  * @buf:        buffer to store read data
1332  * @page:       page number to read
1333  *
1334  * The hw generator calculates the error syndrome automatically. Therefor
1335  * we need a special oob layout and handling.
1336  */
1337 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1338                                    uint8_t *buf, int page)
1339 {
1340         int i, eccsize = chip->ecc.size;
1341         int eccbytes = chip->ecc.bytes;
1342         int eccsteps = chip->ecc.steps;
1343         uint8_t *p = buf;
1344         uint8_t *oob = chip->oob_poi;
1345
1346         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1347                 int stat;
1348
1349                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1350                 chip->read_buf(mtd, p, eccsize);
1351
1352                 if (chip->ecc.prepad) {
1353                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1354                         oob += chip->ecc.prepad;
1355                 }
1356
1357                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1358                 chip->read_buf(mtd, oob, eccbytes);
1359                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1360
1361                 if (stat < 0)
1362                         mtd->ecc_stats.failed++;
1363                 else
1364                         mtd->ecc_stats.corrected += stat;
1365
1366                 oob += eccbytes;
1367
1368                 if (chip->ecc.postpad) {
1369                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1370                         oob += chip->ecc.postpad;
1371                 }
1372         }
1373
1374         /* Calculate remaining oob bytes */
1375         i = mtd->oobsize - (oob - chip->oob_poi);
1376         if (i)
1377                 chip->read_buf(mtd, oob, i);
1378
1379         return 0;
1380 }
1381
1382 /**
1383  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1384  * @chip:       nand chip structure
1385  * @oob:        oob destination address
1386  * @ops:        oob ops structure
1387  * @len:        size of oob to transfer
1388  */
1389 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1390                                   struct mtd_oob_ops *ops, size_t len)
1391 {
1392         switch (ops->mode) {
1393
1394         case MTD_OOB_PLACE:
1395         case MTD_OOB_RAW:
1396                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1397                 return oob + len;
1398
1399         case MTD_OOB_AUTO: {
1400                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1401                 uint32_t boffs = 0, roffs = ops->ooboffs;
1402                 size_t bytes = 0;
1403
1404                 for (; free->length && len; free++, len -= bytes) {
1405                         /* Read request not from offset 0 ? */
1406                         if (unlikely(roffs)) {
1407                                 if (roffs >= free->length) {
1408                                         roffs -= free->length;
1409                                         continue;
1410                                 }
1411                                 boffs = free->offset + roffs;
1412                                 bytes = min_t(size_t, len,
1413                                               (free->length - roffs));
1414                                 roffs = 0;
1415                         } else {
1416                                 bytes = min_t(size_t, len, free->length);
1417                                 boffs = free->offset;
1418                         }
1419                         memcpy(oob, chip->oob_poi + boffs, bytes);
1420                         oob += bytes;
1421                 }
1422                 return oob;
1423         }
1424         default:
1425                 BUG();
1426         }
1427         return NULL;
1428 }
1429
1430 /**
1431  * nand_do_read_ops - [Internal] Read data with ECC
1432  *
1433  * @mtd:        MTD device structure
1434  * @from:       offset to read from
1435  * @ops:        oob ops structure
1436  *
1437  * Internal function. Called with chip held.
1438  */
1439 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1440                             struct mtd_oob_ops *ops)
1441 {
1442         int chipnr, page, realpage, col, bytes, aligned;
1443         struct nand_chip *chip = mtd->priv;
1444         struct mtd_ecc_stats stats;
1445         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1446         int sndcmd = 1;
1447         int ret = 0;
1448         uint32_t readlen = ops->len;
1449         uint32_t oobreadlen = ops->ooblen;
1450         uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1451                 mtd->oobavail : mtd->oobsize;
1452
1453         uint8_t *bufpoi, *oob, *buf;
1454
1455         stats = mtd->ecc_stats;
1456
1457         chipnr = (int)(from >> chip->chip_shift);
1458         chip->select_chip(mtd, chipnr);
1459
1460         realpage = (int)(from >> chip->page_shift);
1461         page = realpage & chip->pagemask;
1462
1463         col = (int)(from & (mtd->writesize - 1));
1464
1465         buf = ops->datbuf;
1466         oob = ops->oobbuf;
1467
1468         while (1) {
1469                 bytes = min(mtd->writesize - col, readlen);
1470                 aligned = (bytes == mtd->writesize);
1471
1472                 /* Is the current page in the buffer ? */
1473                 if (realpage != chip->pagebuf || oob) {
1474                         bufpoi = aligned ? buf : chip->buffers->databuf;
1475
1476                         if (likely(sndcmd)) {
1477                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1478                                 sndcmd = 0;
1479                         }
1480
1481                         /* Now read the page into the buffer */
1482                         if (unlikely(ops->mode == MTD_OOB_RAW))
1483                                 ret = chip->ecc.read_page_raw(mtd, chip,
1484                                                               bufpoi, page);
1485                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1486                                 ret = chip->ecc.read_subpage(mtd, chip,
1487                                                         col, bytes, bufpoi);
1488                         else
1489                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1490                                                           page);
1491                         if (ret < 0)
1492                                 break;
1493
1494                         /* Transfer not aligned data */
1495                         if (!aligned) {
1496                                 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1497                                     !(mtd->ecc_stats.failed - stats.failed))
1498                                         chip->pagebuf = realpage;
1499                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1500                         }
1501
1502                         buf += bytes;
1503
1504                         if (unlikely(oob)) {
1505
1506                                 int toread = min(oobreadlen, max_oobsize);
1507
1508                                 if (toread) {
1509                                         oob = nand_transfer_oob(chip,
1510                                                 oob, ops, toread);
1511                                         oobreadlen -= toread;
1512                                 }
1513                         }
1514
1515                         if (!(chip->options & NAND_NO_READRDY)) {
1516                                 /*
1517                                  * Apply delay or wait for ready/busy pin. Do
1518                                  * this before the AUTOINCR check, so no
1519                                  * problems arise if a chip which does auto
1520                                  * increment is marked as NOAUTOINCR by the
1521                                  * board driver.
1522                                  */
1523                                 if (!chip->dev_ready)
1524                                         udelay(chip->chip_delay);
1525                                 else
1526                                         nand_wait_ready(mtd);
1527                         }
1528                 } else {
1529                         memcpy(buf, chip->buffers->databuf + col, bytes);
1530                         buf += bytes;
1531                 }
1532
1533                 readlen -= bytes;
1534
1535                 if (!readlen)
1536                         break;
1537
1538                 /* For subsequent reads align to page boundary. */
1539                 col = 0;
1540                 /* Increment page address */
1541                 realpage++;
1542
1543                 page = realpage & chip->pagemask;
1544                 /* Check, if we cross a chip boundary */
1545                 if (!page) {
1546                         chipnr++;
1547                         chip->select_chip(mtd, -1);
1548                         chip->select_chip(mtd, chipnr);
1549                 }
1550
1551                 /* Check, if the chip supports auto page increment
1552                  * or if we have hit a block boundary.
1553                  */
1554                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1555                         sndcmd = 1;
1556         }
1557
1558         ops->retlen = ops->len - (size_t) readlen;
1559         if (oob)
1560                 ops->oobretlen = ops->ooblen - oobreadlen;
1561
1562         if (ret)
1563                 return ret;
1564
1565         if (mtd->ecc_stats.failed - stats.failed)
1566                 return -EBADMSG;
1567
1568         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1569 }
1570
1571 /**
1572  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1573  * @mtd:        MTD device structure
1574  * @from:       offset to read from
1575  * @len:        number of bytes to read
1576  * @retlen:     pointer to variable to store the number of read bytes
1577  * @buf:        the databuffer to put data
1578  *
1579  * Get hold of the chip and call nand_do_read
1580  */
1581 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1582                      size_t *retlen, uint8_t *buf)
1583 {
1584         struct nand_chip *chip = mtd->priv;
1585         int ret;
1586
1587         /* Do not allow reads past end of device */
1588         if ((from + len) > mtd->size)
1589                 return -EINVAL;
1590         if (!len)
1591                 return 0;
1592
1593         nand_get_device(chip, mtd, FL_READING);
1594
1595         chip->ops.len = len;
1596         chip->ops.datbuf = buf;
1597         chip->ops.oobbuf = NULL;
1598
1599         ret = nand_do_read_ops(mtd, from, &chip->ops);
1600
1601         *retlen = chip->ops.retlen;
1602
1603         nand_release_device(mtd);
1604
1605         return ret;
1606 }
1607
1608 /**
1609  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1610  * @mtd:        mtd info structure
1611  * @chip:       nand chip info structure
1612  * @page:       page number to read
1613  * @sndcmd:     flag whether to issue read command or not
1614  */
1615 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1616                              int page, int sndcmd)
1617 {
1618         if (sndcmd) {
1619                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1620                 sndcmd = 0;
1621         }
1622         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1623         return sndcmd;
1624 }
1625
1626 /**
1627  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1628  *                          with syndromes
1629  * @mtd:        mtd info structure
1630  * @chip:       nand chip info structure
1631  * @page:       page number to read
1632  * @sndcmd:     flag whether to issue read command or not
1633  */
1634 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1635                                   int page, int sndcmd)
1636 {
1637         uint8_t *buf = chip->oob_poi;
1638         int length = mtd->oobsize;
1639         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1640         int eccsize = chip->ecc.size;
1641         uint8_t *bufpoi = buf;
1642         int i, toread, sndrnd = 0, pos;
1643
1644         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1645         for (i = 0; i < chip->ecc.steps; i++) {
1646                 if (sndrnd) {
1647                         pos = eccsize + i * (eccsize + chunk);
1648                         if (mtd->writesize > 512)
1649                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1650                         else
1651                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1652                 } else
1653                         sndrnd = 1;
1654                 toread = min_t(int, length, chunk);
1655                 chip->read_buf(mtd, bufpoi, toread);
1656                 bufpoi += toread;
1657                 length -= toread;
1658         }
1659         if (length > 0)
1660                 chip->read_buf(mtd, bufpoi, length);
1661
1662         return 1;
1663 }
1664
1665 /**
1666  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1667  * @mtd:        mtd info structure
1668  * @chip:       nand chip info structure
1669  * @page:       page number to write
1670  */
1671 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1672                               int page)
1673 {
1674         int status = 0;
1675         const uint8_t *buf = chip->oob_poi;
1676         int length = mtd->oobsize;
1677
1678         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1679         chip->write_buf(mtd, buf, length);
1680         /* Send command to program the OOB data */
1681         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1682
1683         status = chip->waitfunc(mtd, chip);
1684
1685         return status & NAND_STATUS_FAIL ? -EIO : 0;
1686 }
1687
1688 /**
1689  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1690  *                           with syndrome - only for large page flash !
1691  * @mtd:        mtd info structure
1692  * @chip:       nand chip info structure
1693  * @page:       page number to write
1694  */
1695 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1696                                    struct nand_chip *chip, int page)
1697 {
1698         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1699         int eccsize = chip->ecc.size, length = mtd->oobsize;
1700         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1701         const uint8_t *bufpoi = chip->oob_poi;
1702
1703         /*
1704          * data-ecc-data-ecc ... ecc-oob
1705          * or
1706          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1707          */
1708         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1709                 pos = steps * (eccsize + chunk);
1710                 steps = 0;
1711         } else
1712                 pos = eccsize;
1713
1714         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1715         for (i = 0; i < steps; i++) {
1716                 if (sndcmd) {
1717                         if (mtd->writesize <= 512) {
1718                                 uint32_t fill = 0xFFFFFFFF;
1719
1720                                 len = eccsize;
1721                                 while (len > 0) {
1722                                         int num = min_t(int, len, 4);
1723                                         chip->write_buf(mtd, (uint8_t *)&fill,
1724                                                         num);
1725                                         len -= num;
1726                                 }
1727                         } else {
1728                                 pos = eccsize + i * (eccsize + chunk);
1729                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1730                         }
1731                 } else
1732                         sndcmd = 1;
1733                 len = min_t(int, length, chunk);
1734                 chip->write_buf(mtd, bufpoi, len);
1735                 bufpoi += len;
1736                 length -= len;
1737         }
1738         if (length > 0)
1739                 chip->write_buf(mtd, bufpoi, length);
1740
1741         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1742         status = chip->waitfunc(mtd, chip);
1743
1744         return status & NAND_STATUS_FAIL ? -EIO : 0;
1745 }
1746
1747 /**
1748  * nand_do_read_oob - [Intern] NAND read out-of-band
1749  * @mtd:        MTD device structure
1750  * @from:       offset to read from
1751  * @ops:        oob operations description structure
1752  *
1753  * NAND read out-of-band data from the spare area
1754  */
1755 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1756                             struct mtd_oob_ops *ops)
1757 {
1758         int page, realpage, chipnr, sndcmd = 1;
1759         struct nand_chip *chip = mtd->priv;
1760         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1761         int readlen = ops->ooblen;
1762         int len;
1763         uint8_t *buf = ops->oobbuf;
1764
1765         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1766                         __func__, (unsigned long long)from, readlen);
1767
1768         if (ops->mode == MTD_OOB_AUTO)
1769                 len = chip->ecc.layout->oobavail;
1770         else
1771                 len = mtd->oobsize;
1772
1773         if (unlikely(ops->ooboffs >= len)) {
1774                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1775                                         "outside oob\n", __func__);
1776                 return -EINVAL;
1777         }
1778
1779         /* Do not allow reads past end of device */
1780         if (unlikely(from >= mtd->size ||
1781                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1782                                         (from >> chip->page_shift)) * len)) {
1783                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1784                                         "of device\n", __func__);
1785                 return -EINVAL;
1786         }
1787
1788         chipnr = (int)(from >> chip->chip_shift);
1789         chip->select_chip(mtd, chipnr);
1790
1791         /* Shift to get page */
1792         realpage = (int)(from >> chip->page_shift);
1793         page = realpage & chip->pagemask;
1794
1795         while (1) {
1796                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1797
1798                 len = min(len, readlen);
1799                 buf = nand_transfer_oob(chip, buf, ops, len);
1800
1801                 if (!(chip->options & NAND_NO_READRDY)) {
1802                         /*
1803                          * Apply delay or wait for ready/busy pin. Do this
1804                          * before the AUTOINCR check, so no problems arise if a
1805                          * chip which does auto increment is marked as
1806                          * NOAUTOINCR by the board driver.
1807                          */
1808                         if (!chip->dev_ready)
1809                                 udelay(chip->chip_delay);
1810                         else
1811                                 nand_wait_ready(mtd);
1812                 }
1813
1814                 readlen -= len;
1815                 if (!readlen)
1816                         break;
1817
1818                 /* Increment page address */
1819                 realpage++;
1820
1821                 page = realpage & chip->pagemask;
1822                 /* Check, if we cross a chip boundary */
1823                 if (!page) {
1824                         chipnr++;
1825                         chip->select_chip(mtd, -1);
1826                         chip->select_chip(mtd, chipnr);
1827                 }
1828
1829                 /* Check, if the chip supports auto page increment
1830                  * or if we have hit a block boundary.
1831                  */
1832                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1833                         sndcmd = 1;
1834         }
1835
1836         ops->oobretlen = ops->ooblen;
1837         return 0;
1838 }
1839
1840 /**
1841  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1842  * @mtd:        MTD device structure
1843  * @from:       offset to read from
1844  * @ops:        oob operation description structure
1845  *
1846  * NAND read data and/or out-of-band data
1847  */
1848 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1849                          struct mtd_oob_ops *ops)
1850 {
1851         struct nand_chip *chip = mtd->priv;
1852         int ret = -ENOTSUPP;
1853
1854         ops->retlen = 0;
1855
1856         /* Do not allow reads past end of device */
1857         if (ops->datbuf && (from + ops->len) > mtd->size) {
1858                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1859                                 "beyond end of device\n", __func__);
1860                 return -EINVAL;
1861         }
1862
1863         nand_get_device(chip, mtd, FL_READING);
1864
1865         switch (ops->mode) {
1866         case MTD_OOB_PLACE:
1867         case MTD_OOB_AUTO:
1868         case MTD_OOB_RAW:
1869                 break;
1870
1871         default:
1872                 goto out;
1873         }
1874
1875         if (!ops->datbuf)
1876                 ret = nand_do_read_oob(mtd, from, ops);
1877         else
1878                 ret = nand_do_read_ops(mtd, from, ops);
1879
1880 out:
1881         nand_release_device(mtd);
1882         return ret;
1883 }
1884
1885
1886 /**
1887  * nand_write_page_raw - [Intern] raw page write function
1888  * @mtd:        mtd info structure
1889  * @chip:       nand chip info structure
1890  * @buf:        data buffer
1891  *
1892  * Not for syndrome calculating ecc controllers, which use a special oob layout
1893  */
1894 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1895                                 const uint8_t *buf)
1896 {
1897         chip->write_buf(mtd, buf, mtd->writesize);
1898         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1899 }
1900
1901 /**
1902  * nand_write_page_raw_syndrome - [Intern] raw page write function
1903  * @mtd:        mtd info structure
1904  * @chip:       nand chip info structure
1905  * @buf:        data buffer
1906  *
1907  * We need a special oob layout and handling even when ECC isn't checked.
1908  */
1909 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1910                                         struct nand_chip *chip,
1911                                         const uint8_t *buf)
1912 {
1913         int eccsize = chip->ecc.size;
1914         int eccbytes = chip->ecc.bytes;
1915         uint8_t *oob = chip->oob_poi;
1916         int steps, size;
1917
1918         for (steps = chip->ecc.steps; steps > 0; steps--) {
1919                 chip->write_buf(mtd, buf, eccsize);
1920                 buf += eccsize;
1921
1922                 if (chip->ecc.prepad) {
1923                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1924                         oob += chip->ecc.prepad;
1925                 }
1926
1927                 chip->read_buf(mtd, oob, eccbytes);
1928                 oob += eccbytes;
1929
1930                 if (chip->ecc.postpad) {
1931                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1932                         oob += chip->ecc.postpad;
1933                 }
1934         }
1935
1936         size = mtd->oobsize - (oob - chip->oob_poi);
1937         if (size)
1938                 chip->write_buf(mtd, oob, size);
1939 }
1940 /**
1941  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1942  * @mtd:        mtd info structure
1943  * @chip:       nand chip info structure
1944  * @buf:        data buffer
1945  */
1946 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1947                                   const uint8_t *buf)
1948 {
1949         int i, eccsize = chip->ecc.size;
1950         int eccbytes = chip->ecc.bytes;
1951         int eccsteps = chip->ecc.steps;
1952         uint8_t *ecc_calc = chip->buffers->ecccalc;
1953         const uint8_t *p = buf;
1954         uint32_t *eccpos = chip->ecc.layout->eccpos;
1955
1956         /* Software ecc calculation */
1957         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1958                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1959
1960         for (i = 0; i < chip->ecc.total; i++)
1961                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1962
1963         chip->ecc.write_page_raw(mtd, chip, buf);
1964 }
1965
1966 /**
1967  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1968  * @mtd:        mtd info structure
1969  * @chip:       nand chip info structure
1970  * @buf:        data buffer
1971  */
1972 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1973                                   const uint8_t *buf)
1974 {
1975         int i, eccsize = chip->ecc.size;
1976         int eccbytes = chip->ecc.bytes;
1977         int eccsteps = chip->ecc.steps;
1978         uint8_t *ecc_calc = chip->buffers->ecccalc;
1979         const uint8_t *p = buf;
1980         uint32_t *eccpos = chip->ecc.layout->eccpos;
1981
1982         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1983                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1984                 chip->write_buf(mtd, p, eccsize);
1985                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1986         }
1987
1988         for (i = 0; i < chip->ecc.total; i++)
1989                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1990
1991         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1992 }
1993
1994 /**
1995  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1996  * @mtd:        mtd info structure
1997  * @chip:       nand chip info structure
1998  * @buf:        data buffer
1999  *
2000  * The hw generator calculates the error syndrome automatically. Therefor
2001  * we need a special oob layout and handling.
2002  */
2003 static void nand_write_page_syndrome(struct mtd_info *mtd,
2004                                     struct nand_chip *chip, const uint8_t *buf)
2005 {
2006         int i, eccsize = chip->ecc.size;
2007         int eccbytes = chip->ecc.bytes;
2008         int eccsteps = chip->ecc.steps;
2009         const uint8_t *p = buf;
2010         uint8_t *oob = chip->oob_poi;
2011
2012         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2013
2014                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2015                 chip->write_buf(mtd, p, eccsize);
2016
2017                 if (chip->ecc.prepad) {
2018                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2019                         oob += chip->ecc.prepad;
2020                 }
2021
2022                 chip->ecc.calculate(mtd, p, oob);
2023                 chip->write_buf(mtd, oob, eccbytes);
2024                 oob += eccbytes;
2025
2026                 if (chip->ecc.postpad) {
2027                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2028                         oob += chip->ecc.postpad;
2029                 }
2030         }
2031
2032         /* Calculate remaining oob bytes */
2033         i = mtd->oobsize - (oob - chip->oob_poi);
2034         if (i)
2035                 chip->write_buf(mtd, oob, i);
2036 }
2037
2038 /**
2039  * nand_write_page - [REPLACEABLE] write one page
2040  * @mtd:        MTD device structure
2041  * @chip:       NAND chip descriptor
2042  * @buf:        the data to write
2043  * @page:       page number to write
2044  * @cached:     cached programming
2045  * @raw:        use _raw version of write_page
2046  */
2047 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2048                            const uint8_t *buf, int page, int cached, int raw)
2049 {
2050         int status;
2051
2052         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2053
2054         if (unlikely(raw))
2055                 chip->ecc.write_page_raw(mtd, chip, buf);
2056         else
2057                 chip->ecc.write_page(mtd, chip, buf);
2058
2059         /*
2060          * Cached progamming disabled for now, Not sure if its worth the
2061          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2062          */
2063         cached = 0;
2064
2065         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2066
2067                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2068                 status = chip->waitfunc(mtd, chip);
2069                 /*
2070                  * See if operation failed and additional status checks are
2071                  * available
2072                  */
2073                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2074                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2075                                                page);
2076
2077                 if (status & NAND_STATUS_FAIL)
2078                         return -EIO;
2079         } else {
2080                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2081                 status = chip->waitfunc(mtd, chip);
2082         }
2083
2084 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2085         /* Send command to read back the data */
2086         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2087
2088         if (chip->verify_buf(mtd, buf, mtd->writesize))
2089                 return -EIO;
2090 #endif
2091         return 0;
2092 }
2093
2094 /**
2095  * nand_fill_oob - [Internal] Transfer client buffer to oob
2096  * @chip:       nand chip structure
2097  * @oob:        oob data buffer
2098  * @len:        oob data write length
2099  * @ops:        oob ops structure
2100  */
2101 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2102                                                 struct mtd_oob_ops *ops)
2103 {
2104         switch (ops->mode) {
2105
2106         case MTD_OOB_PLACE:
2107         case MTD_OOB_RAW:
2108                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2109                 return oob + len;
2110
2111         case MTD_OOB_AUTO: {
2112                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2113                 uint32_t boffs = 0, woffs = ops->ooboffs;
2114                 size_t bytes = 0;
2115
2116                 for (; free->length && len; free++, len -= bytes) {
2117                         /* Write request not from offset 0 ? */
2118                         if (unlikely(woffs)) {
2119                                 if (woffs >= free->length) {
2120                                         woffs -= free->length;
2121                                         continue;
2122                                 }
2123                                 boffs = free->offset + woffs;
2124                                 bytes = min_t(size_t, len,
2125                                               (free->length - woffs));
2126                                 woffs = 0;
2127                         } else {
2128                                 bytes = min_t(size_t, len, free->length);
2129                                 boffs = free->offset;
2130                         }
2131                         memcpy(chip->oob_poi + boffs, oob, bytes);
2132                         oob += bytes;
2133                 }
2134                 return oob;
2135         }
2136         default:
2137                 BUG();
2138         }
2139         return NULL;
2140 }
2141
2142 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2143
2144 /**
2145  * nand_do_write_ops - [Internal] NAND write with ECC
2146  * @mtd:        MTD device structure
2147  * @to:         offset to write to
2148  * @ops:        oob operations description structure
2149  *
2150  * NAND write with ECC
2151  */
2152 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2153                              struct mtd_oob_ops *ops)
2154 {
2155         int chipnr, realpage, page, blockmask, column;
2156         struct nand_chip *chip = mtd->priv;
2157         uint32_t writelen = ops->len;
2158
2159         uint32_t oobwritelen = ops->ooblen;
2160         uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2161                                 mtd->oobavail : mtd->oobsize;
2162
2163         uint8_t *oob = ops->oobbuf;
2164         uint8_t *buf = ops->datbuf;
2165         int ret, subpage;
2166
2167         ops->retlen = 0;
2168         if (!writelen)
2169                 return 0;
2170
2171         /* reject writes, which are not page aligned */
2172         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2173                 printk(KERN_NOTICE "%s: Attempt to write not "
2174                                 "page aligned data\n", __func__);
2175                 return -EINVAL;
2176         }
2177
2178         column = to & (mtd->writesize - 1);
2179         subpage = column || (writelen & (mtd->writesize - 1));
2180
2181         if (subpage && oob)
2182                 return -EINVAL;
2183
2184         chipnr = (int)(to >> chip->chip_shift);
2185         chip->select_chip(mtd, chipnr);
2186
2187         /* Check, if it is write protected */
2188         if (nand_check_wp(mtd))
2189                 return -EIO;
2190
2191         realpage = (int)(to >> chip->page_shift);
2192         page = realpage & chip->pagemask;
2193         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2194
2195         /* Invalidate the page cache, when we write to the cached page */
2196         if (to <= (chip->pagebuf << chip->page_shift) &&
2197             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2198                 chip->pagebuf = -1;
2199
2200         /* If we're not given explicit OOB data, let it be 0xFF */
2201         if (likely(!oob))
2202                 memset(chip->oob_poi, 0xff, mtd->oobsize);
2203
2204         /* Don't allow multipage oob writes with offset */
2205         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2206                 return -EINVAL;
2207
2208         while (1) {
2209                 int bytes = mtd->writesize;
2210                 int cached = writelen > bytes && page != blockmask;
2211                 uint8_t *wbuf = buf;
2212
2213                 /* Partial page write ? */
2214                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2215                         cached = 0;
2216                         bytes = min_t(int, bytes - column, (int) writelen);
2217                         chip->pagebuf = -1;
2218                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2219                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2220                         wbuf = chip->buffers->databuf;
2221                 }
2222
2223                 if (unlikely(oob)) {
2224                         size_t len = min(oobwritelen, oobmaxlen);
2225                         oob = nand_fill_oob(chip, oob, len, ops);
2226                         oobwritelen -= len;
2227                 }
2228
2229                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2230                                        (ops->mode == MTD_OOB_RAW));
2231                 if (ret)
2232                         break;
2233
2234                 writelen -= bytes;
2235                 if (!writelen)
2236                         break;
2237
2238                 column = 0;
2239                 buf += bytes;
2240                 realpage++;
2241
2242                 page = realpage & chip->pagemask;
2243                 /* Check, if we cross a chip boundary */
2244                 if (!page) {
2245                         chipnr++;
2246                         chip->select_chip(mtd, -1);
2247                         chip->select_chip(mtd, chipnr);
2248                 }
2249         }
2250
2251         ops->retlen = ops->len - writelen;
2252         if (unlikely(oob))
2253                 ops->oobretlen = ops->ooblen;
2254         return ret;
2255 }
2256
2257 /**
2258  * panic_nand_write - [MTD Interface] NAND write with ECC
2259  * @mtd:        MTD device structure
2260  * @to:         offset to write to
2261  * @len:        number of bytes to write
2262  * @retlen:     pointer to variable to store the number of written bytes
2263  * @buf:        the data to write
2264  *
2265  * NAND write with ECC. Used when performing writes in interrupt context, this
2266  * may for example be called by mtdoops when writing an oops while in panic.
2267  */
2268 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2269                             size_t *retlen, const uint8_t *buf)
2270 {
2271         struct nand_chip *chip = mtd->priv;
2272         int ret;
2273
2274         /* Do not allow reads past end of device */
2275         if ((to + len) > mtd->size)
2276                 return -EINVAL;
2277         if (!len)
2278                 return 0;
2279
2280         /* Wait for the device to get ready.  */
2281         panic_nand_wait(mtd, chip, 400);
2282
2283         /* Grab the device.  */
2284         panic_nand_get_device(chip, mtd, FL_WRITING);
2285
2286         chip->ops.len = len;
2287         chip->ops.datbuf = (uint8_t *)buf;
2288         chip->ops.oobbuf = NULL;
2289
2290         ret = nand_do_write_ops(mtd, to, &chip->ops);
2291
2292         *retlen = chip->ops.retlen;
2293         return ret;
2294 }
2295
2296 /**
2297  * nand_write - [MTD Interface] NAND write with ECC
2298  * @mtd:        MTD device structure
2299  * @to:         offset to write to
2300  * @len:        number of bytes to write
2301  * @retlen:     pointer to variable to store the number of written bytes
2302  * @buf:        the data to write
2303  *
2304  * NAND write with ECC
2305  */
2306 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2307                           size_t *retlen, const uint8_t *buf)
2308 {
2309         struct nand_chip *chip = mtd->priv;
2310         int ret;
2311
2312         /* Do not allow reads past end of device */
2313         if ((to + len) > mtd->size)
2314                 return -EINVAL;
2315         if (!len)
2316                 return 0;
2317
2318         nand_get_device(chip, mtd, FL_WRITING);
2319
2320         chip->ops.len = len;
2321         chip->ops.datbuf = (uint8_t *)buf;
2322         chip->ops.oobbuf = NULL;
2323
2324         ret = nand_do_write_ops(mtd, to, &chip->ops);
2325
2326         *retlen = chip->ops.retlen;
2327
2328         nand_release_device(mtd);
2329
2330         return ret;
2331 }
2332
2333 /**
2334  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2335  * @mtd:        MTD device structure
2336  * @to:         offset to write to
2337  * @ops:        oob operation description structure
2338  *
2339  * NAND write out-of-band
2340  */
2341 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2342                              struct mtd_oob_ops *ops)
2343 {
2344         int chipnr, page, status, len;
2345         struct nand_chip *chip = mtd->priv;
2346
2347         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2348                          __func__, (unsigned int)to, (int)ops->ooblen);
2349
2350         if (ops->mode == MTD_OOB_AUTO)
2351                 len = chip->ecc.layout->oobavail;
2352         else
2353                 len = mtd->oobsize;
2354
2355         /* Do not allow write past end of page */
2356         if ((ops->ooboffs + ops->ooblen) > len) {
2357                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2358                                 "past end of page\n", __func__);
2359                 return -EINVAL;
2360         }
2361
2362         if (unlikely(ops->ooboffs >= len)) {
2363                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2364                                 "write outside oob\n", __func__);
2365                 return -EINVAL;
2366         }
2367
2368         /* Do not allow write past end of device */
2369         if (unlikely(to >= mtd->size ||
2370                      ops->ooboffs + ops->ooblen >
2371                         ((mtd->size >> chip->page_shift) -
2372                          (to >> chip->page_shift)) * len)) {
2373                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2374                                 "end of device\n", __func__);
2375                 return -EINVAL;
2376         }
2377
2378         chipnr = (int)(to >> chip->chip_shift);
2379         chip->select_chip(mtd, chipnr);
2380
2381         /* Shift to get page */
2382         page = (int)(to >> chip->page_shift);
2383
2384         /*
2385          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2386          * of my DiskOnChip 2000 test units) will clear the whole data page too
2387          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2388          * it in the doc2000 driver in August 1999.  dwmw2.
2389          */
2390         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2391
2392         /* Check, if it is write protected */
2393         if (nand_check_wp(mtd))
2394                 return -EROFS;
2395
2396         /* Invalidate the page cache, if we write to the cached page */
2397         if (page == chip->pagebuf)
2398                 chip->pagebuf = -1;
2399
2400         memset(chip->oob_poi, 0xff, mtd->oobsize);
2401         nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2402         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2403         memset(chip->oob_poi, 0xff, mtd->oobsize);
2404
2405         if (status)
2406                 return status;
2407
2408         ops->oobretlen = ops->ooblen;
2409
2410         return 0;
2411 }
2412
2413 /**
2414  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2415  * @mtd:        MTD device structure
2416  * @to:         offset to write to
2417  * @ops:        oob operation description structure
2418  */
2419 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2420                           struct mtd_oob_ops *ops)
2421 {
2422         struct nand_chip *chip = mtd->priv;
2423         int ret = -ENOTSUPP;
2424
2425         ops->retlen = 0;
2426
2427         /* Do not allow writes past end of device */
2428         if (ops->datbuf && (to + ops->len) > mtd->size) {
2429                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2430                                 "end of device\n", __func__);
2431                 return -EINVAL;
2432         }
2433
2434         nand_get_device(chip, mtd, FL_WRITING);
2435
2436         switch (ops->mode) {
2437         case MTD_OOB_PLACE:
2438         case MTD_OOB_AUTO:
2439         case MTD_OOB_RAW:
2440                 break;
2441
2442         default:
2443                 goto out;
2444         }
2445
2446         if (!ops->datbuf)
2447                 ret = nand_do_write_oob(mtd, to, ops);
2448         else
2449                 ret = nand_do_write_ops(mtd, to, ops);
2450
2451 out:
2452         nand_release_device(mtd);
2453         return ret;
2454 }
2455
2456 /**
2457  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2458  * @mtd:        MTD device structure
2459  * @page:       the page address of the block which will be erased
2460  *
2461  * Standard erase command for NAND chips
2462  */
2463 static void single_erase_cmd(struct mtd_info *mtd, int page)
2464 {
2465         struct nand_chip *chip = mtd->priv;
2466         /* Send commands to erase a block */
2467         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2468         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2469 }
2470
2471 /**
2472  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2473  * @mtd:        MTD device structure
2474  * @page:       the page address of the block which will be erased
2475  *
2476  * AND multi block erase command function
2477  * Erase 4 consecutive blocks
2478  */
2479 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2480 {
2481         struct nand_chip *chip = mtd->priv;
2482         /* Send commands to erase a block */
2483         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2485         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2486         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2487         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2488 }
2489
2490 /**
2491  * nand_erase - [MTD Interface] erase block(s)
2492  * @mtd:        MTD device structure
2493  * @instr:      erase instruction
2494  *
2495  * Erase one ore more blocks
2496  */
2497 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2498 {
2499         return nand_erase_nand(mtd, instr, 0);
2500 }
2501
2502 #define BBT_PAGE_MASK   0xffffff3f
2503 /**
2504  * nand_erase_nand - [Internal] erase block(s)
2505  * @mtd:        MTD device structure
2506  * @instr:      erase instruction
2507  * @allowbbt:   allow erasing the bbt area
2508  *
2509  * Erase one ore more blocks
2510  */
2511 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2512                     int allowbbt)
2513 {
2514         int page, status, pages_per_block, ret, chipnr;
2515         struct nand_chip *chip = mtd->priv;
2516         loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2517         unsigned int bbt_masked_page = 0xffffffff;
2518         loff_t len;
2519
2520         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2521                                 __func__, (unsigned long long)instr->addr,
2522                                 (unsigned long long)instr->len);
2523
2524         if (check_offs_len(mtd, instr->addr, instr->len))
2525                 return -EINVAL;
2526
2527         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2528
2529         /* Grab the lock and see if the device is available */
2530         nand_get_device(chip, mtd, FL_ERASING);
2531
2532         /* Shift to get first page */
2533         page = (int)(instr->addr >> chip->page_shift);
2534         chipnr = (int)(instr->addr >> chip->chip_shift);
2535
2536         /* Calculate pages in each block */
2537         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2538
2539         /* Select the NAND device */
2540         chip->select_chip(mtd, chipnr);
2541
2542         /* Check, if it is write protected */
2543         if (nand_check_wp(mtd)) {
2544                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2545                                         __func__);
2546                 instr->state = MTD_ERASE_FAILED;
2547                 goto erase_exit;
2548         }
2549
2550         /*
2551          * If BBT requires refresh, set the BBT page mask to see if the BBT
2552          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2553          * can not be matched. This is also done when the bbt is actually
2554          * erased to avoid recusrsive updates
2555          */
2556         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2557                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2558
2559         /* Loop through the pages */
2560         len = instr->len;
2561
2562         instr->state = MTD_ERASING;
2563
2564         while (len) {
2565                 /*
2566                  * heck if we have a bad block, we do not erase bad blocks !
2567                  */
2568                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2569                                         chip->page_shift, 0, allowbbt)) {
2570                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2571                                         "at page 0x%08x\n", __func__, page);
2572                         instr->state = MTD_ERASE_FAILED;
2573                         goto erase_exit;
2574                 }
2575
2576                 /*
2577                  * Invalidate the page cache, if we erase the block which
2578                  * contains the current cached page
2579                  */
2580                 if (page <= chip->pagebuf && chip->pagebuf <
2581                     (page + pages_per_block))
2582                         chip->pagebuf = -1;
2583
2584                 chip->erase_cmd(mtd, page & chip->pagemask);
2585
2586                 status = chip->waitfunc(mtd, chip);
2587
2588                 /*
2589                  * See if operation failed and additional status checks are
2590                  * available
2591                  */
2592                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2593                         status = chip->errstat(mtd, chip, FL_ERASING,
2594                                                status, page);
2595
2596                 /* See if block erase succeeded */
2597                 if (status & NAND_STATUS_FAIL) {
2598                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2599                                         "page 0x%08x\n", __func__, page);
2600                         instr->state = MTD_ERASE_FAILED;
2601                         instr->fail_addr =
2602                                 ((loff_t)page << chip->page_shift);
2603                         goto erase_exit;
2604                 }
2605
2606                 /*
2607                  * If BBT requires refresh, set the BBT rewrite flag to the
2608                  * page being erased
2609                  */
2610                 if (bbt_masked_page != 0xffffffff &&
2611                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2612                             rewrite_bbt[chipnr] =
2613                                         ((loff_t)page << chip->page_shift);
2614
2615                 /* Increment page address and decrement length */
2616                 len -= (1 << chip->phys_erase_shift);
2617                 page += pages_per_block;
2618
2619                 /* Check, if we cross a chip boundary */
2620                 if (len && !(page & chip->pagemask)) {
2621                         chipnr++;
2622                         chip->select_chip(mtd, -1);
2623                         chip->select_chip(mtd, chipnr);
2624
2625                         /*
2626                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2627                          * page mask to see if this BBT should be rewritten
2628                          */
2629                         if (bbt_masked_page != 0xffffffff &&
2630                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2631                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2632                                         BBT_PAGE_MASK;
2633                 }
2634         }
2635         instr->state = MTD_ERASE_DONE;
2636
2637 erase_exit:
2638
2639         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2640
2641         /* Deselect and wake up anyone waiting on the device */
2642         nand_release_device(mtd);
2643
2644         /* Do call back function */
2645         if (!ret)
2646                 mtd_erase_callback(instr);
2647
2648         /*
2649          * If BBT requires refresh and erase was successful, rewrite any
2650          * selected bad block tables
2651          */
2652         if (bbt_masked_page == 0xffffffff || ret)
2653                 return ret;
2654
2655         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2656                 if (!rewrite_bbt[chipnr])
2657                         continue;
2658                 /* update the BBT for chip */
2659                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2660                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2661                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2662                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2663         }
2664
2665         /* Return more or less happy */
2666         return ret;
2667 }
2668
2669 /**
2670  * nand_sync - [MTD Interface] sync
2671  * @mtd:        MTD device structure
2672  *
2673  * Sync is actually a wait for chip ready function
2674  */
2675 static void nand_sync(struct mtd_info *mtd)
2676 {
2677         struct nand_chip *chip = mtd->priv;
2678
2679         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2680
2681         /* Grab the lock and see if the device is available */
2682         nand_get_device(chip, mtd, FL_SYNCING);
2683         /* Release it and go back */
2684         nand_release_device(mtd);
2685 }
2686
2687 /**
2688  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2689  * @mtd:        MTD device structure
2690  * @offs:       offset relative to mtd start
2691  */
2692 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2693 {
2694         /* Check for invalid offset */
2695         if (offs > mtd->size)
2696                 return -EINVAL;
2697
2698         return nand_block_checkbad(mtd, offs, 1, 0);
2699 }
2700
2701 /**
2702  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2703  * @mtd:        MTD device structure
2704  * @ofs:        offset relative to mtd start
2705  */
2706 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2707 {
2708         struct nand_chip *chip = mtd->priv;
2709         int ret;
2710
2711         ret = nand_block_isbad(mtd, ofs);
2712         if (ret) {
2713                 /* If it was bad already, return success and do nothing. */
2714                 if (ret > 0)
2715                         return 0;
2716                 return ret;
2717         }
2718
2719         return chip->block_markbad(mtd, ofs);
2720 }
2721
2722 /**
2723  * nand_suspend - [MTD Interface] Suspend the NAND flash
2724  * @mtd:        MTD device structure
2725  */
2726 static int nand_suspend(struct mtd_info *mtd)
2727 {
2728         struct nand_chip *chip = mtd->priv;
2729
2730         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2731 }
2732
2733 /**
2734  * nand_resume - [MTD Interface] Resume the NAND flash
2735  * @mtd:        MTD device structure
2736  */
2737 static void nand_resume(struct mtd_info *mtd)
2738 {
2739         struct nand_chip *chip = mtd->priv;
2740
2741         if (chip->state == FL_PM_SUSPENDED)
2742                 nand_release_device(mtd);
2743         else
2744                 printk(KERN_ERR "%s called for a chip which is not "
2745                        "in suspended state\n", __func__);
2746 }
2747
2748 /*
2749  * Set default functions
2750  */
2751 static void nand_set_defaults(struct nand_chip *chip, int busw)
2752 {
2753         /* check for proper chip_delay setup, set 20us if not */
2754         if (!chip->chip_delay)
2755                 chip->chip_delay = 20;
2756
2757         /* check, if a user supplied command function given */
2758         if (chip->cmdfunc == NULL)
2759                 chip->cmdfunc = nand_command;
2760
2761         /* check, if a user supplied wait function given */
2762         if (chip->waitfunc == NULL)
2763                 chip->waitfunc = nand_wait;
2764
2765         if (!chip->select_chip)
2766                 chip->select_chip = nand_select_chip;
2767         if (!chip->read_byte)
2768                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2769         if (!chip->read_word)
2770                 chip->read_word = nand_read_word;
2771         if (!chip->block_bad)
2772                 chip->block_bad = nand_block_bad;
2773         if (!chip->block_markbad)
2774                 chip->block_markbad = nand_default_block_markbad;
2775         if (!chip->write_buf)
2776                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2777         if (!chip->read_buf)
2778                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2779         if (!chip->verify_buf)
2780                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2781         if (!chip->scan_bbt)
2782                 chip->scan_bbt = nand_default_bbt;
2783
2784         if (!chip->controller) {
2785                 chip->controller = &chip->hwcontrol;
2786                 spin_lock_init(&chip->controller->lock);
2787                 init_waitqueue_head(&chip->controller->wq);
2788         }
2789
2790 }
2791
2792 /*
2793  * sanitize ONFI strings so we can safely print them
2794  */
2795 static void sanitize_string(uint8_t *s, size_t len)
2796 {
2797         ssize_t i;
2798
2799         /* null terminate */
2800         s[len - 1] = 0;
2801
2802         /* remove non printable chars */
2803         for (i = 0; i < len - 1; i++) {
2804                 if (s[i] < ' ' || s[i] > 127)
2805                         s[i] = '?';
2806         }
2807
2808         /* remove trailing spaces */
2809         strim(s);
2810 }
2811
2812 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2813 {
2814         int i;
2815         while (len--) {
2816                 crc ^= *p++ << 8;
2817                 for (i = 0; i < 8; i++)
2818                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2819         }
2820
2821         return crc;
2822 }
2823
2824 /*
2825  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2826  */
2827 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2828                                         int busw)
2829 {
2830         struct nand_onfi_params *p = &chip->onfi_params;
2831         int i;
2832         int val;
2833
2834         /* try ONFI for unknow chip or LP */
2835         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2836         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2837                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2838                 return 0;
2839
2840         printk(KERN_INFO "ONFI flash detected\n");
2841         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2842         for (i = 0; i < 3; i++) {
2843                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2844                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2845                                 le16_to_cpu(p->crc)) {
2846                         printk(KERN_INFO "ONFI param page %d valid\n", i);
2847                         break;
2848                 }
2849         }
2850
2851         if (i == 3)
2852                 return 0;
2853
2854         /* check version */
2855         val = le16_to_cpu(p->revision);
2856         if (val & (1 << 5))
2857                 chip->onfi_version = 23;
2858         else if (val & (1 << 4))
2859                 chip->onfi_version = 22;
2860         else if (val & (1 << 3))
2861                 chip->onfi_version = 21;
2862         else if (val & (1 << 2))
2863                 chip->onfi_version = 20;
2864         else if (val & (1 << 1))
2865                 chip->onfi_version = 10;
2866         else
2867                 chip->onfi_version = 0;
2868
2869         if (!chip->onfi_version) {
2870                 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2871                                                                 __func__, val);
2872                 return 0;
2873         }
2874
2875         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2876         sanitize_string(p->model, sizeof(p->model));
2877         if (!mtd->name)
2878                 mtd->name = p->model;
2879         mtd->writesize = le32_to_cpu(p->byte_per_page);
2880         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2881         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2882         chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2883         busw = 0;
2884         if (le16_to_cpu(p->features) & 1)
2885                 busw = NAND_BUSWIDTH_16;
2886
2887         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2888         chip->options |= (NAND_NO_READRDY |
2889                         NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2890
2891         return 1;
2892 }
2893
2894 /*
2895  * Get the flash and manufacturer id and lookup if the type is supported
2896  */
2897 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2898                                                   struct nand_chip *chip,
2899                                                   int busw,
2900                                                   int *maf_id, int *dev_id,
2901                                                   struct nand_flash_dev *type)
2902 {
2903         int i, maf_idx;
2904         u8 id_data[8];
2905         int ret;
2906
2907         /* Select the device */
2908         chip->select_chip(mtd, 0);
2909
2910         /*
2911          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2912          * after power-up
2913          */
2914         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2915
2916         /* Send the command for reading device ID */
2917         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2918
2919         /* Read manufacturer and device IDs */
2920         *maf_id = chip->read_byte(mtd);
2921         *dev_id = chip->read_byte(mtd);
2922
2923         /* Try again to make sure, as some systems the bus-hold or other
2924          * interface concerns can cause random data which looks like a
2925          * possibly credible NAND flash to appear. If the two results do
2926          * not match, ignore the device completely.
2927          */
2928
2929         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2930
2931         for (i = 0; i < 2; i++)
2932                 id_data[i] = chip->read_byte(mtd);
2933
2934         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2935                 printk(KERN_INFO "%s: second ID read did not match "
2936                        "%02x,%02x against %02x,%02x\n", __func__,
2937                        *maf_id, *dev_id, id_data[0], id_data[1]);
2938                 return ERR_PTR(-ENODEV);
2939         }
2940
2941         if (!type)
2942                 type = nand_flash_ids;
2943
2944         for (; type->name != NULL; type++)
2945                 if (*dev_id == type->id)
2946                         break;
2947
2948         chip->onfi_version = 0;
2949         if (!type->name || !type->pagesize) {
2950                 /* Check is chip is ONFI compliant */
2951                 ret = nand_flash_detect_onfi(mtd, chip, busw);
2952                 if (ret)
2953                         goto ident_done;
2954         }
2955
2956         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2957
2958         /* Read entire ID string */
2959
2960         for (i = 0; i < 8; i++)
2961                 id_data[i] = chip->read_byte(mtd);
2962
2963         if (!type->name)
2964                 return ERR_PTR(-ENODEV);
2965
2966         if (!mtd->name)
2967                 mtd->name = type->name;
2968
2969         chip->chipsize = (uint64_t)type->chipsize << 20;
2970
2971         if (!type->pagesize && chip->init_size) {
2972                 /* set the pagesize, oobsize, erasesize by the driver*/
2973                 busw = chip->init_size(mtd, chip, id_data);
2974         } else if (!type->pagesize) {
2975                 int extid;
2976                 /* The 3rd id byte holds MLC / multichip data */
2977                 chip->cellinfo = id_data[2];
2978                 /* The 4th id byte is the important one */
2979                 extid = id_data[3];
2980
2981                 /*
2982                  * Field definitions are in the following datasheets:
2983                  * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2984                  * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
2985                  *
2986                  * Check for wraparound + Samsung ID + nonzero 6th byte
2987                  * to decide what to do.
2988                  */
2989                 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2990                                 id_data[0] == NAND_MFR_SAMSUNG &&
2991                                 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2992                                 id_data[5] != 0x00) {
2993                         /* Calc pagesize */
2994                         mtd->writesize = 2048 << (extid & 0x03);
2995                         extid >>= 2;
2996                         /* Calc oobsize */
2997                         switch (extid & 0x03) {
2998                         case 1:
2999                                 mtd->oobsize = 128;
3000                                 break;
3001                         case 2:
3002                                 mtd->oobsize = 218;
3003                                 break;
3004                         case 3:
3005                                 mtd->oobsize = 400;
3006                                 break;
3007                         default:
3008                                 mtd->oobsize = 436;
3009                                 break;
3010                         }
3011                         extid >>= 2;
3012                         /* Calc blocksize */
3013                         mtd->erasesize = (128 * 1024) <<
3014                                 (((extid >> 1) & 0x04) | (extid & 0x03));
3015                         busw = 0;
3016                 } else {
3017                         /* Calc pagesize */
3018                         mtd->writesize = 1024 << (extid & 0x03);
3019                         extid >>= 2;
3020                         /* Calc oobsize */
3021                         mtd->oobsize = (8 << (extid & 0x01)) *
3022                                 (mtd->writesize >> 9);
3023                         extid >>= 2;
3024                         /* Calc blocksize. Blocksize is multiples of 64KiB */
3025                         mtd->erasesize = (64 * 1024) << (extid & 0x03);
3026                         extid >>= 2;
3027                         /* Get buswidth information */
3028                         busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3029                 }
3030         } else {
3031                 /*
3032                  * Old devices have chip data hardcoded in the device id table
3033                  */
3034                 mtd->erasesize = type->erasesize;
3035                 mtd->writesize = type->pagesize;
3036                 mtd->oobsize = mtd->writesize / 32;
3037                 busw = type->options & NAND_BUSWIDTH_16;
3038
3039                 /*
3040                  * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3041                  * some Spansion chips have erasesize that conflicts with size
3042                  * listed in nand_ids table
3043                  * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3044                  */
3045                 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3046                                 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3047                                 id_data[7] == 0x00 && mtd->writesize == 512) {
3048                         mtd->erasesize = 128 * 1024;
3049                         mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3050                 }
3051         }
3052         /* Get chip options, preserve non chip based options */
3053         chip->options &= ~NAND_CHIPOPTIONS_MSK;
3054         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3055
3056         /* Check if chip is a not a samsung device. Do not clear the
3057          * options for chips which are not having an extended id.
3058          */
3059         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3060                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3061 ident_done:
3062
3063         /*
3064          * Set chip as a default. Board drivers can override it, if necessary
3065          */
3066         chip->options |= NAND_NO_AUTOINCR;
3067
3068         /* Try to identify manufacturer */
3069         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3070                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3071                         break;
3072         }
3073
3074         /*
3075          * Check, if buswidth is correct. Hardware drivers should set
3076          * chip correct !
3077          */
3078         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3079                 printk(KERN_INFO "NAND device: Manufacturer ID:"
3080                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3081                        *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3082                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
3083                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3084                        busw ? 16 : 8);
3085                 return ERR_PTR(-EINVAL);
3086         }
3087
3088         /* Calculate the address shift from the page size */
3089         chip->page_shift = ffs(mtd->writesize) - 1;
3090         /* Convert chipsize to number of pages per chip -1. */
3091         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3092
3093         chip->bbt_erase_shift = chip->phys_erase_shift =
3094                 ffs(mtd->erasesize) - 1;
3095         if (chip->chipsize & 0xffffffff)
3096                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3097         else {
3098                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3099                 chip->chip_shift += 32 - 1;
3100         }
3101
3102         chip->badblockbits = 8;
3103
3104         /* Set the bad block position */
3105         if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3106                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3107         else
3108                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3109
3110         /*
3111          * Bad block marker is stored in the last page of each block
3112          * on Samsung and Hynix MLC devices; stored in first two pages
3113          * of each block on Micron devices with 2KiB pages and on
3114          * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3115          * only the first page.
3116          */
3117         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3118                         (*maf_id == NAND_MFR_SAMSUNG ||
3119                          *maf_id == NAND_MFR_HYNIX))
3120                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3121         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3122                                 (*maf_id == NAND_MFR_SAMSUNG ||
3123                                  *maf_id == NAND_MFR_HYNIX ||
3124                                  *maf_id == NAND_MFR_TOSHIBA ||
3125                                  *maf_id == NAND_MFR_AMD)) ||
3126                         (mtd->writesize == 2048 &&
3127                          *maf_id == NAND_MFR_MICRON))
3128                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3129
3130         /* Check for AND chips with 4 page planes */
3131         if (chip->options & NAND_4PAGE_ARRAY)
3132                 chip->erase_cmd = multi_erase_cmd;
3133         else
3134                 chip->erase_cmd = single_erase_cmd;
3135
3136         /* Do not replace user supplied command function ! */
3137         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3138                 chip->cmdfunc = nand_command_lp;
3139
3140         /* TODO onfi flash name */
3141         printk(KERN_INFO "NAND device: Manufacturer ID:"
3142                 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3143                 nand_manuf_ids[maf_idx].name,
3144                 chip->onfi_version ? chip->onfi_params.model : type->name);
3145
3146         return type;
3147 }
3148
3149 /**
3150  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3151  * @mtd:             MTD device structure
3152  * @maxchips:        Number of chips to scan for
3153  * @table:           Alternative NAND ID table
3154  *
3155  * This is the first phase of the normal nand_scan() function. It
3156  * reads the flash ID and sets up MTD fields accordingly.
3157  *
3158  * The mtd->owner field must be set to the module of the caller.
3159  */
3160 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3161                     struct nand_flash_dev *table)
3162 {
3163         int i, busw, nand_maf_id, nand_dev_id;
3164         struct nand_chip *chip = mtd->priv;
3165         struct nand_flash_dev *type;
3166
3167         /* Get buswidth to select the correct functions */
3168         busw = chip->options & NAND_BUSWIDTH_16;
3169         /* Set the default functions */
3170         nand_set_defaults(chip, busw);
3171
3172         /* Read the flash type */
3173         type = nand_get_flash_type(mtd, chip, busw,
3174                                 &nand_maf_id, &nand_dev_id, table);
3175
3176         if (IS_ERR(type)) {
3177                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3178                         printk(KERN_WARNING "No NAND device found.\n");
3179                 chip->select_chip(mtd, -1);
3180                 return PTR_ERR(type);
3181         }
3182
3183         /* Check for a chip array */
3184         for (i = 1; i < maxchips; i++) {
3185                 chip->select_chip(mtd, i);
3186                 /* See comment in nand_get_flash_type for reset */
3187                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3188                 /* Send the command for reading device ID */
3189                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3190                 /* Read manufacturer and device IDs */
3191                 if (nand_maf_id != chip->read_byte(mtd) ||
3192                     nand_dev_id != chip->read_byte(mtd))
3193                         break;
3194         }
3195         if (i > 1)
3196                 printk(KERN_INFO "%d NAND chips detected\n", i);
3197
3198         /* Store the number of chips and calc total size for mtd */
3199         chip->numchips = i;
3200         mtd->size = i * chip->chipsize;
3201
3202         return 0;
3203 }
3204 EXPORT_SYMBOL(nand_scan_ident);
3205
3206
3207 /**
3208  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3209  * @mtd:            MTD device structure
3210  *
3211  * This is the second phase of the normal nand_scan() function. It
3212  * fills out all the uninitialized function pointers with the defaults
3213  * and scans for a bad block table if appropriate.
3214  */
3215 int nand_scan_tail(struct mtd_info *mtd)
3216 {
3217         int i;
3218         struct nand_chip *chip = mtd->priv;
3219
3220         if (!(chip->options & NAND_OWN_BUFFERS))
3221                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3222         if (!chip->buffers)
3223                 return -ENOMEM;
3224
3225         /* Set the internal oob buffer location, just after the page data */
3226         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3227
3228         /*
3229          * If no default placement scheme is given, select an appropriate one
3230          */
3231         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3232                 switch (mtd->oobsize) {
3233                 case 8:
3234                         chip->ecc.layout = &nand_oob_8;
3235                         break;
3236                 case 16:
3237                         chip->ecc.layout = &nand_oob_16;
3238                         break;
3239                 case 64:
3240                         chip->ecc.layout = &nand_oob_64;
3241                         break;
3242                 case 128:
3243                         chip->ecc.layout = &nand_oob_128;
3244                         break;
3245                 default:
3246                         printk(KERN_WARNING "No oob scheme defined for "
3247                                "oobsize %d\n", mtd->oobsize);
3248                         BUG();
3249                 }
3250         }
3251
3252         if (!chip->write_page)
3253                 chip->write_page = nand_write_page;
3254
3255         /*
3256          * check ECC mode, default to software if 3byte/512byte hardware ECC is
3257          * selected and we have 256 byte pagesize fallback to software ECC
3258          */
3259
3260         switch (chip->ecc.mode) {
3261         case NAND_ECC_HW_OOB_FIRST:
3262                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3263                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3264                      !chip->ecc.hwctl) {
3265                         printk(KERN_WARNING "No ECC functions supplied; "
3266                                "Hardware ECC not possible\n");
3267                         BUG();
3268                 }
3269                 if (!chip->ecc.read_page)
3270                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3271
3272         case NAND_ECC_HW:
3273                 /* Use standard hwecc read page function ? */
3274                 if (!chip->ecc.read_page)
3275                         chip->ecc.read_page = nand_read_page_hwecc;
3276                 if (!chip->ecc.write_page)
3277                         chip->ecc.write_page = nand_write_page_hwecc;
3278                 if (!chip->ecc.read_page_raw)
3279                         chip->ecc.read_page_raw = nand_read_page_raw;
3280                 if (!chip->ecc.write_page_raw)
3281                         chip->ecc.write_page_raw = nand_write_page_raw;
3282                 if (!chip->ecc.read_oob)
3283                         chip->ecc.read_oob = nand_read_oob_std;
3284                 if (!chip->ecc.write_oob)
3285                         chip->ecc.write_oob = nand_write_oob_std;
3286
3287         case NAND_ECC_HW_SYNDROME:
3288                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3289                      !chip->ecc.hwctl) &&
3290                     (!chip->ecc.read_page ||
3291                      chip->ecc.read_page == nand_read_page_hwecc ||
3292                      !chip->ecc.write_page ||
3293                      chip->ecc.write_page == nand_write_page_hwecc)) {
3294                         printk(KERN_WARNING "No ECC functions supplied; "
3295                                "Hardware ECC not possible\n");
3296                         BUG();
3297                 }
3298                 /* Use standard syndrome read/write page function ? */
3299                 if (!chip->ecc.read_page)
3300                         chip->ecc.read_page = nand_read_page_syndrome;
3301                 if (!chip->ecc.write_page)
3302                         chip->ecc.write_page = nand_write_page_syndrome;
3303                 if (!chip->ecc.read_page_raw)
3304                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3305                 if (!chip->ecc.write_page_raw)
3306                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3307                 if (!chip->ecc.read_oob)
3308                         chip->ecc.read_oob = nand_read_oob_syndrome;
3309                 if (!chip->ecc.write_oob)
3310                         chip->ecc.write_oob = nand_write_oob_syndrome;
3311
3312                 if (mtd->writesize >= chip->ecc.size)
3313                         break;
3314                 printk(KERN_WARNING "%d byte HW ECC not possible on "
3315                        "%d byte page size, fallback to SW ECC\n",
3316                        chip->ecc.size, mtd->writesize);
3317                 chip->ecc.mode = NAND_ECC_SOFT;
3318
3319         case NAND_ECC_SOFT:
3320                 chip->ecc.calculate = nand_calculate_ecc;
3321                 chip->ecc.correct = nand_correct_data;
3322                 chip->ecc.read_page = nand_read_page_swecc;
3323                 chip->ecc.read_subpage = nand_read_subpage;
3324                 chip->ecc.write_page = nand_write_page_swecc;
3325                 chip->ecc.read_page_raw = nand_read_page_raw;
3326                 chip->ecc.write_page_raw = nand_write_page_raw;
3327                 chip->ecc.read_oob = nand_read_oob_std;
3328                 chip->ecc.write_oob = nand_write_oob_std;
3329                 if (!chip->ecc.size)
3330                         chip->ecc.size = 256;
3331                 chip->ecc.bytes = 3;
3332                 break;
3333
3334         case NAND_ECC_SOFT_BCH:
3335                 if (!mtd_nand_has_bch()) {
3336                         printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3337                         BUG();
3338                 }
3339                 chip->ecc.calculate = nand_bch_calculate_ecc;
3340                 chip->ecc.correct = nand_bch_correct_data;
3341                 chip->ecc.read_page = nand_read_page_swecc;
3342                 chip->ecc.read_subpage = nand_read_subpage;
3343                 chip->ecc.write_page = nand_write_page_swecc;
3344                 chip->ecc.read_page_raw = nand_read_page_raw;
3345                 chip->ecc.write_page_raw = nand_write_page_raw;
3346                 chip->ecc.read_oob = nand_read_oob_std;
3347                 chip->ecc.write_oob = nand_write_oob_std;
3348                 /*
3349                  * Board driver should supply ecc.size and ecc.bytes values to
3350                  * select how many bits are correctable; see nand_bch_init()
3351                  * for details.
3352                  * Otherwise, default to 4 bits for large page devices
3353                  */
3354                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3355                         chip->ecc.size = 512;
3356                         chip->ecc.bytes = 7;
3357                 }
3358                 chip->ecc.priv = nand_bch_init(mtd,
3359                                                chip->ecc.size,
3360                                                chip->ecc.bytes,
3361                                                &chip->ecc.layout);
3362                 if (!chip->ecc.priv) {
3363                         printk(KERN_WARNING "BCH ECC initialization failed!\n");
3364                         BUG();
3365                 }
3366                 break;
3367
3368         case NAND_ECC_NONE:
3369                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3370                        "This is not recommended !!\n");
3371                 chip->ecc.read_page = nand_read_page_raw;
3372                 chip->ecc.write_page = nand_write_page_raw;
3373                 chip->ecc.read_oob = nand_read_oob_std;
3374                 chip->ecc.read_page_raw = nand_read_page_raw;
3375                 chip->ecc.write_page_raw = nand_write_page_raw;
3376                 chip->ecc.write_oob = nand_write_oob_std;
3377                 chip->ecc.size = mtd->writesize;
3378                 chip->ecc.bytes = 0;
3379                 break;
3380
3381         default:
3382                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3383                        chip->ecc.mode);
3384                 BUG();
3385         }
3386
3387         /*
3388          * The number of bytes available for a client to place data into
3389          * the out of band area
3390          */
3391         chip->ecc.layout->oobavail = 0;
3392         for (i = 0; chip->ecc.layout->oobfree[i].length
3393                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3394                 chip->ecc.layout->oobavail +=
3395                         chip->ecc.layout->oobfree[i].length;
3396         mtd->oobavail = chip->ecc.layout->oobavail;
3397
3398         /*
3399          * Set the number of read / write steps for one page depending on ECC
3400          * mode
3401          */
3402         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3403         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3404                 printk(KERN_WARNING "Invalid ecc parameters\n");
3405                 BUG();
3406         }
3407         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3408
3409         /*
3410          * Allow subpage writes up to ecc.steps. Not possible for MLC
3411          * FLASH.
3412          */
3413         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3414             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3415                 switch (chip->ecc.steps) {
3416                 case 2:
3417                         mtd->subpage_sft = 1;
3418                         break;
3419                 case 4:
3420                 case 8:
3421                 case 16:
3422                         mtd->subpage_sft = 2;
3423                         break;
3424                 }
3425         }
3426         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3427
3428         /* Initialize state */
3429         chip->state = FL_READY;
3430
3431         /* De-select the device */
3432         chip->select_chip(mtd, -1);
3433
3434         /* Invalidate the pagebuffer reference */
3435         chip->pagebuf = -1;
3436
3437         /* Fill in remaining MTD driver data */
3438         mtd->type = MTD_NANDFLASH;
3439         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3440                                                 MTD_CAP_NANDFLASH;
3441         mtd->erase = nand_erase;
3442         mtd->point = NULL;
3443         mtd->unpoint = NULL;
3444         mtd->read = nand_read;
3445         mtd->write = nand_write;
3446         mtd->panic_write = panic_nand_write;
3447         mtd->read_oob = nand_read_oob;
3448         mtd->write_oob = nand_write_oob;
3449         mtd->sync = nand_sync;
3450         mtd->lock = NULL;
3451         mtd->unlock = NULL;
3452         mtd->suspend = nand_suspend;
3453         mtd->resume = nand_resume;
3454         mtd->block_isbad = nand_block_isbad;
3455         mtd->block_markbad = nand_block_markbad;
3456         mtd->writebufsize = mtd->writesize;
3457
3458         /* propagate ecc.layout to mtd_info */
3459         mtd->ecclayout = chip->ecc.layout;
3460
3461         /* Check, if we should skip the bad block table scan */
3462         if (chip->options & NAND_SKIP_BBTSCAN)
3463                 return 0;
3464
3465         /* Build bad block table */
3466         return chip->scan_bbt(mtd);
3467 }
3468 EXPORT_SYMBOL(nand_scan_tail);
3469
3470 /* is_module_text_address() isn't exported, and it's mostly a pointless
3471  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3472  * to call us from in-kernel code if the core NAND support is modular. */
3473 #ifdef MODULE
3474 #define caller_is_module() (1)
3475 #else
3476 #define caller_is_module() \
3477         is_module_text_address((unsigned long)__builtin_return_address(0))
3478 #endif
3479
3480 /**
3481  * nand_scan - [NAND Interface] Scan for the NAND device
3482  * @mtd:        MTD device structure
3483  * @maxchips:   Number of chips to scan for
3484  *
3485  * This fills out all the uninitialized function pointers
3486  * with the defaults.
3487  * The flash ID is read and the mtd/chip structures are
3488  * filled with the appropriate values.
3489  * The mtd->owner field must be set to the module of the caller
3490  *
3491  */
3492 int nand_scan(struct mtd_info *mtd, int maxchips)
3493 {
3494         int ret;
3495
3496         /* Many callers got this wrong, so check for it for a while... */
3497         if (!mtd->owner && caller_is_module()) {
3498                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3499                                 __func__);
3500                 BUG();
3501         }
3502
3503         ret = nand_scan_ident(mtd, maxchips, NULL);
3504         if (!ret)
3505                 ret = nand_scan_tail(mtd);
3506         return ret;
3507 }
3508 EXPORT_SYMBOL(nand_scan);
3509
3510 /**
3511  * nand_release - [NAND Interface] Free resources held by the NAND device
3512  * @mtd:        MTD device structure
3513 */
3514 void nand_release(struct mtd_info *mtd)
3515 {
3516         struct nand_chip *chip = mtd->priv;
3517
3518         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3519                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3520
3521         mtd_device_unregister(mtd);
3522
3523         /* Free bad block table memory */
3524         kfree(chip->bbt);
3525         if (!(chip->options & NAND_OWN_BUFFERS))
3526                 kfree(chip->buffers);
3527
3528         /* Free bad block descriptor memory */
3529         if (chip->badblock_pattern && chip->badblock_pattern->options
3530                         & NAND_BBT_DYNAMICSTRUCT)
3531                 kfree(chip->badblock_pattern);
3532 }
3533 EXPORT_SYMBOL_GPL(nand_release);
3534
3535 static int __init nand_base_init(void)
3536 {
3537         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3538         return 0;
3539 }
3540
3541 static void __exit nand_base_exit(void)
3542 {
3543         led_trigger_unregister_simple(nand_led_trigger);
3544 }
3545
3546 module_init(nand_base_init);
3547 module_exit(nand_base_exit);
3548
3549 MODULE_LICENSE("GPL");
3550 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3551 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3552 MODULE_DESCRIPTION("Generic NAND flash driver code");