drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/compatmac.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <asm/io.h>
  50
  51 #ifdef CONFIG_MTD_PARTITIONS
  52 #include <linux/mtd/partitions.h>
  53 #endif
  54
  55 /* Define default oob placement schemes for large and small page devices */
  56 static struct nand_ecclayout nand_oob_8 = {
  57         .eccbytes = 3,
  58         .eccpos = {0, 1, 2},
  59         .oobfree = {
  60                 {.offset = 3,
  61                  .length = 2},
  62                 {.offset = 6,
  63                  .length = 2}}
  64 };
  65
  66 static struct nand_ecclayout nand_oob_16 = {
  67         .eccbytes = 6,
  68         .eccpos = {0, 1, 2, 3, 6, 7},
  69         .oobfree = {
  70                 {.offset = 8,
  71                  . length = 8}}
  72 };
  73
  74 static struct nand_ecclayout nand_oob_64 = {
  75         .eccbytes = 24,
  76         .eccpos = {
  77                    40, 41, 42, 43, 44, 45, 46, 47,
  78                    48, 49, 50, 51, 52, 53, 54, 55,
  79                    56, 57, 58, 59, 60, 61, 62, 63},
  80         .oobfree = {
  81                 {.offset = 2,
  82                  .length = 38}}
  83 };
  84
  85 static struct nand_ecclayout nand_oob_128 = {
  86         .eccbytes = 48,
  87         .eccpos = {
  88                    80, 81, 82, 83, 84, 85, 86, 87,
  89                    88, 89, 90, 91, 92, 93, 94, 95,
  90                    96, 97, 98, 99, 100, 101, 102, 103,
  91                    104, 105, 106, 107, 108, 109, 110, 111,
  92                    112, 113, 114, 115, 116, 117, 118, 119,
  93                    120, 121, 122, 123, 124, 125, 126, 127},
  94         .oobfree = {
  95                 {.offset = 2,
  96                  .length = 78}}
  97 };
  98
  99 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
 100                            int new_state);
 101
 102 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 103                              struct mtd_oob_ops *ops);
 104
 105 /*
 106  * For devices which display every fart in the system on a separate LED. Is
 107  * compiled away when LED support is disabled.
 108  */
 109 DEFINE_LED_TRIGGER(nand_led_trigger);
 110
 111 static int check_offs_len(struct mtd_info *mtd,
 112                                         loff_t ofs, uint64_t len)
 113 {
 114         struct nand_chip *chip = mtd->priv;
 115         int ret = 0;
 116
 117         /* Start address must align on block boundary */
 118         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 119                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 120                 ret = -EINVAL;
 121         }
 122
 123         /* Length must align on block boundary */
 124         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 125                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 126                                         __func__);
 127                 ret = -EINVAL;
 128         }
 129
 130         /* Do not allow past end of device */
 131         if (ofs + len > mtd->size) {
 132                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
 133                                         __func__);
 134                 ret = -EINVAL;
 135         }
 136
 137         return ret;
 138 }
 139
 140 /**
 141  * nand_release_device - [GENERIC] release chip
 142  * @mtd:        MTD device structure
 143  *
 144  * Deselect, release chip lock and wake up anyone waiting on the device
 145  */
 146 static void nand_release_device(struct mtd_info *mtd)
 147 {
 148         struct nand_chip *chip = mtd->priv;
 149
 150         /* De-select the NAND device */
 151         chip->select_chip(mtd, -1);
 152
 153         /* Release the controller and the chip */
 154         spin_lock(&chip->controller->lock);
 155         chip->controller->active = NULL;
 156         chip->state = FL_READY;
 157         wake_up(&chip->controller->wq);
 158         spin_unlock(&chip->controller->lock);
 159 }
 160
 161 /**
 162  * nand_read_byte - [DEFAULT] read one byte from the chip
 163  * @mtd:        MTD device structure
 164  *
 165  * Default read function for 8bit buswith
 166  */
 167 static uint8_t nand_read_byte(struct mtd_info *mtd)
 168 {
 169         struct nand_chip *chip = mtd->priv;
 170         return readb(chip->IO_ADDR_R);
 171 }
 172
 173 /**
 174  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 175  * @mtd:        MTD device structure
 176  *
 177  * Default read function for 16bit buswith with
 178  * endianess conversion
 179  */
 180 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 181 {
 182         struct nand_chip *chip = mtd->priv;
 183         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 184 }
 185
 186 /**
 187  * nand_read_word - [DEFAULT] read one word from the chip
 188  * @mtd:        MTD device structure
 189  *
 190  * Default read function for 16bit buswith without
 191  * endianess conversion
 192  */
 193 static u16 nand_read_word(struct mtd_info *mtd)
 194 {
 195         struct nand_chip *chip = mtd->priv;
 196         return readw(chip->IO_ADDR_R);
 197 }
 198
 199 /**
 200  * nand_select_chip - [DEFAULT] control CE line
 201  * @mtd:        MTD device structure
 202  * @chipnr:     chipnumber to select, -1 for deselect
 203  *
 204  * Default select function for 1 chip devices.
 205  */
 206 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 207 {
 208         struct nand_chip *chip = mtd->priv;
 209
 210         switch (chipnr) {
 211         case -1:
 212                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 213                 break;
 214         case 0:
 215                 break;
 216
 217         default:
 218                 BUG();
 219         }
 220 }
 221
 222 /**
 223  * nand_write_buf - [DEFAULT] write buffer to chip
 224  * @mtd:        MTD device structure
 225  * @buf:        data buffer
 226  * @len:        number of bytes to write
 227  *
 228  * Default write function for 8bit buswith
 229  */
 230 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 231 {
 232         int i;
 233         struct nand_chip *chip = mtd->priv;
 234
 235         for (i = 0; i < len; i++)
 236                 writeb(buf[i], chip->IO_ADDR_W);
 237 }
 238
 239 /**
 240  * nand_read_buf - [DEFAULT] read chip data into buffer
 241  * @mtd:        MTD device structure
 242  * @buf:        buffer to store date
 243  * @len:        number of bytes to read
 244  *
 245  * Default read function for 8bit buswith
 246  */
 247 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 248 {
 249         int i;
 250         struct nand_chip *chip = mtd->priv;
 251
 252         for (i = 0; i < len; i++)
 253                 buf[i] = readb(chip->IO_ADDR_R);
 254 }
 255
 256 /**
 257  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 258  * @mtd:        MTD device structure
 259  * @buf:        buffer containing the data to compare
 260  * @len:        number of bytes to compare
 261  *
 262  * Default verify function for 8bit buswith
 263  */
 264 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 265 {
 266         int i;
 267         struct nand_chip *chip = mtd->priv;
 268
 269         for (i = 0; i < len; i++)
 270                 if (buf[i] != readb(chip->IO_ADDR_R))
 271                         return -EFAULT;
 272         return 0;
 273 }
 274
 275 /**
 276  * nand_write_buf16 - [DEFAULT] write buffer to chip
 277  * @mtd:        MTD device structure
 278  * @buf:        data buffer
 279  * @len:        number of bytes to write
 280  *
 281  * Default write function for 16bit buswith
 282  */
 283 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 284 {
 285         int i;
 286         struct nand_chip *chip = mtd->priv;
 287         u16 *p = (u16 *) buf;
 288         len >>= 1;
 289
 290         for (i = 0; i < len; i++)
 291                 writew(p[i], chip->IO_ADDR_W);
 292
 293 }
 294
 295 /**
 296  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 297  * @mtd:        MTD device structure
 298  * @buf:        buffer to store date
 299  * @len:        number of bytes to read
 300  *
 301  * Default read function for 16bit buswith
 302  */
 303 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 304 {
 305         int i;
 306         struct nand_chip *chip = mtd->priv;
 307         u16 *p = (u16 *) buf;
 308         len >>= 1;
 309
 310         for (i = 0; i < len; i++)
 311                 p[i] = readw(chip->IO_ADDR_R);
 312 }
 313
 314 /**
 315  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 316  * @mtd:        MTD device structure
 317  * @buf:        buffer containing the data to compare
 318  * @len:        number of bytes to compare
 319  *
 320  * Default verify function for 16bit buswith
 321  */
 322 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 323 {
 324         int i;
 325         struct nand_chip *chip = mtd->priv;
 326         u16 *p = (u16 *) buf;
 327         len >>= 1;
 328
 329         for (i = 0; i < len; i++)
 330                 if (p[i] != readw(chip->IO_ADDR_R))
 331                         return -EFAULT;
 332
 333         return 0;
 334 }
 335
 336 /**
 337  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 338  * @mtd:        MTD device structure
 339  * @ofs:        offset from device start
 340  * @getchip:    0, if the chip is already selected
 341  *
 342  * Check, if the block is bad.
 343  */
 344 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 345 {
 346         int page, chipnr, res = 0;
 347         struct nand_chip *chip = mtd->priv;
 348         u16 bad;
 349
 350         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 351
 352         if (getchip) {
 353                 chipnr = (int)(ofs >> chip->chip_shift);
 354
 355                 nand_get_device(chip, mtd, FL_READING);
 356
 357                 /* Select the NAND device */
 358                 chip->select_chip(mtd, chipnr);
 359         }
 360
 361         if (chip->options & NAND_BUSWIDTH_16) {
 362                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 363                               page);
 364                 bad = cpu_to_le16(chip->read_word(mtd));
 365                 if (chip->badblockpos & 0x1)
 366                         bad >>= 8;
 367                 if ((bad & 0xFF) != 0xff)
 368                         res = 1;
 369         } else {
 370                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 371                 if (chip->read_byte(mtd) != 0xff)
 372                         res = 1;
 373         }
 374
 375         if (getchip)
 376                 nand_release_device(mtd);
 377
 378         return res;
 379 }
 380
 381 /**
 382  * nand_default_block_markbad - [DEFAULT] mark a block bad
 383  * @mtd:        MTD device structure
 384  * @ofs:        offset from device start
 385  *
 386  * This is the default implementation, which can be overridden by
 387  * a hardware specific driver.
 388 */
 389 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 390 {
 391         struct nand_chip *chip = mtd->priv;
 392         uint8_t buf[2] = { 0, 0 };
 393         int block, ret;
 394
 395         /* Get block number */
 396         block = (int)(ofs >> chip->bbt_erase_shift);
 397         if (chip->bbt)
 398                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 399
 400         /* Do we have a flash based bad block table ? */
 401         if (chip->options & NAND_USE_FLASH_BBT)
 402                 ret = nand_update_bbt(mtd, ofs);
 403         else {
 404                 /* We write two bytes, so we dont have to mess with 16 bit
 405                  * access
 406                  */
 407                 nand_get_device(chip, mtd, FL_WRITING);
 408                 ofs += mtd->oobsize;
 409                 chip->ops.len = chip->ops.ooblen = 2;
 410                 chip->ops.datbuf = NULL;
 411                 chip->ops.oobbuf = buf;
 412                 chip->ops.ooboffs = chip->badblockpos & ~0x01;
 413
 414                 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 415                 nand_release_device(mtd);
 416         }
 417         if (!ret)
 418                 mtd->ecc_stats.badblocks++;
 419
 420         return ret;
 421 }
 422
 423 /**
 424  * nand_check_wp - [GENERIC] check if the chip is write protected
 425  * @mtd:        MTD device structure
 426  * Check, if the device is write protected
 427  *
 428  * The function expects, that the device is already selected
 429  */
 430 static int nand_check_wp(struct mtd_info *mtd)
 431 {
 432         struct nand_chip *chip = mtd->priv;
 433         /* Check the WP bit */
 434         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 435         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 436 }
 437
 438 /**
 439  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 440  * @mtd:        MTD device structure
 441  * @ofs:        offset from device start
 442  * @getchip:    0, if the chip is already selected
 443  * @allowbbt:   1, if its allowed to access the bbt area
 444  *
 445  * Check, if the block is bad. Either by reading the bad block table or
 446  * calling of the scan function.
 447  */
 448 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 449                                int allowbbt)
 450 {
 451         struct nand_chip *chip = mtd->priv;
 452
 453         if (!chip->bbt)
 454                 return chip->block_bad(mtd, ofs, getchip);
 455
 456         /* Return info from the table */
 457         return nand_isbad_bbt(mtd, ofs, allowbbt);
 458 }
 459
 460 /**
 461  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 462  * @mtd:        MTD device structure
 463  * @timeo:      Timeout
 464  *
 465  * Helper function for nand_wait_ready used when needing to wait in interrupt
 466  * context.
 467  */
 468 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 469 {
 470         struct nand_chip *chip = mtd->priv;
 471         int i;
 472
 473         /* Wait for the device to get ready */
 474         for (i = 0; i < timeo; i++) {
 475                 if (chip->dev_ready(mtd))
 476                         break;
 477                 touch_softlockup_watchdog();
 478                 mdelay(1);
 479         }
 480 }
 481
 482 /*
 483  * Wait for the ready pin, after a command
 484  * The timeout is catched later.
 485  */
 486 void nand_wait_ready(struct mtd_info *mtd)
 487 {
 488         struct nand_chip *chip = mtd->priv;
 489         unsigned long timeo = jiffies + 2;
 490
 491         /* 400ms timeout */
 492         if (in_interrupt() || oops_in_progress)
 493                 return panic_nand_wait_ready(mtd, 400);
 494
 495         led_trigger_event(nand_led_trigger, LED_FULL);
 496         /* wait until command is processed or timeout occures */
 497         do {
 498                 if (chip->dev_ready(mtd))
 499                         break;
 500                 touch_softlockup_watchdog();
 501         } while (time_before(jiffies, timeo));
 502         led_trigger_event(nand_led_trigger, LED_OFF);
 503 }
 504 EXPORT_SYMBOL_GPL(nand_wait_ready);
 505
 506 /**
 507  * nand_command - [DEFAULT] Send command to NAND device
 508  * @mtd:        MTD device structure
 509  * @command:    the command to be sent
 510  * @column:     the column address for this command, -1 if none
 511  * @page_addr:  the page address for this command, -1 if none
 512  *
 513  * Send command to NAND device. This function is used for small page
 514  * devices (256/512 Bytes per page)
 515  */
 516 static void nand_command(struct mtd_info *mtd, unsigned int command,
 517                          int column, int page_addr)
 518 {
 519         register struct nand_chip *chip = mtd->priv;
 520         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 521
 522         /*
 523          * Write out the command to the device.
 524          */
 525         if (command == NAND_CMD_SEQIN) {
 526                 int readcmd;
 527
 528                 if (column >= mtd->writesize) {
 529                         /* OOB area */
 530                         column -= mtd->writesize;
 531                         readcmd = NAND_CMD_READOOB;
 532                 } else if (column < 256) {
 533                         /* First 256 bytes --> READ0 */
 534                         readcmd = NAND_CMD_READ0;
 535                 } else {
 536                         column -= 256;
 537                         readcmd = NAND_CMD_READ1;
 538                 }
 539                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 540                 ctrl &= ~NAND_CTRL_CHANGE;
 541         }
 542         chip->cmd_ctrl(mtd, command, ctrl);
 543
 544         /*
 545          * Address cycle, when necessary
 546          */
 547         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 548         /* Serially input address */
 549         if (column != -1) {
 550                 /* Adjust columns for 16 bit buswidth */
 551                 if (chip->options & NAND_BUSWIDTH_16)
 552                         column >>= 1;
 553                 chip->cmd_ctrl(mtd, column, ctrl);
 554                 ctrl &= ~NAND_CTRL_CHANGE;
 555         }
 556         if (page_addr != -1) {
 557                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 558                 ctrl &= ~NAND_CTRL_CHANGE;
 559                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 560                 /* One more address cycle for devices > 32MiB */
 561                 if (chip->chipsize > (32 << 20))
 562                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 563         }
 564         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 565
 566         /*
 567          * program and erase have their own busy handlers
 568          * status and sequential in needs no delay
 569          */
 570         switch (command) {
 571
 572         case NAND_CMD_PAGEPROG:
 573         case NAND_CMD_ERASE1:
 574         case NAND_CMD_ERASE2:
 575         case NAND_CMD_SEQIN:
 576         case NAND_CMD_STATUS:
 577                 return;
 578
 579         case NAND_CMD_RESET:
 580                 if (chip->dev_ready)
 581                         break;
 582                 udelay(chip->chip_delay);
 583                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 584                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 585                 chip->cmd_ctrl(mtd,
 586                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 587                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 588                 return;
 589
 590                 /* This applies to read commands */
 591         default:
 592                 /*
 593                  * If we don't have access to the busy pin, we apply the given
 594                  * command delay
 595                  */
 596                 if (!chip->dev_ready) {
 597                         udelay(chip->chip_delay);
 598                         return;
 599                 }
 600         }
 601         /* Apply this short delay always to ensure that we do wait tWB in
 602          * any case on any machine. */
 603         ndelay(100);
 604
 605         nand_wait_ready(mtd);
 606 }
 607
 608 /**
 609  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 610  * @mtd:        MTD device structure
 611  * @command:    the command to be sent
 612  * @column:     the column address for this command, -1 if none
 613  * @page_addr:  the page address for this command, -1 if none
 614  *
 615  * Send command to NAND device. This is the version for the new large page
 616  * devices We dont have the separate regions as we have in the small page
 617  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 618  */
 619 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 620                             int column, int page_addr)
 621 {
 622         register struct nand_chip *chip = mtd->priv;
 623
 624         /* Emulate NAND_CMD_READOOB */
 625         if (command == NAND_CMD_READOOB) {
 626                 column += mtd->writesize;
 627                 command = NAND_CMD_READ0;
 628         }
 629
 630         /* Command latch cycle */
 631         chip->cmd_ctrl(mtd, command & 0xff,
 632                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 633
 634         if (column != -1 || page_addr != -1) {
 635                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 636
 637                 /* Serially input address */
 638                 if (column != -1) {
 639                         /* Adjust columns for 16 bit buswidth */
 640                         if (chip->options & NAND_BUSWIDTH_16)
 641                                 column >>= 1;
 642                         chip->cmd_ctrl(mtd, column, ctrl);
 643                         ctrl &= ~NAND_CTRL_CHANGE;
 644                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 645                 }
 646                 if (page_addr != -1) {
 647                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 648                         chip->cmd_ctrl(mtd, page_addr >> 8,
 649                                        NAND_NCE | NAND_ALE);
 650                         /* One more address cycle for devices > 128MiB */
 651                         if (chip->chipsize > (128 << 20))
 652                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 653                                                NAND_NCE | NAND_ALE);
 654                 }
 655         }
 656         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 657
 658         /*
 659          * program and erase have their own busy handlers
 660          * status, sequential in, and deplete1 need no delay
 661          */
 662         switch (command) {
 663
 664         case NAND_CMD_CACHEDPROG:
 665         case NAND_CMD_PAGEPROG:
 666         case NAND_CMD_ERASE1:
 667         case NAND_CMD_ERASE2:
 668         case NAND_CMD_SEQIN:
 669         case NAND_CMD_RNDIN:
 670         case NAND_CMD_STATUS:
 671         case NAND_CMD_DEPLETE1:
 672                 return;
 673
 674                 /*
 675                  * read error status commands require only a short delay
 676                  */
 677         case NAND_CMD_STATUS_ERROR:
 678         case NAND_CMD_STATUS_ERROR0:
 679         case NAND_CMD_STATUS_ERROR1:
 680         case NAND_CMD_STATUS_ERROR2:
 681         case NAND_CMD_STATUS_ERROR3:
 682                 udelay(chip->chip_delay);
 683                 return;
 684
 685         case NAND_CMD_RESET:
 686                 if (chip->dev_ready)
 687                         break;
 688                 udelay(chip->chip_delay);
 689                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 690                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 691                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 692                                NAND_NCE | NAND_CTRL_CHANGE);
 693                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
 694                 return;
 695
 696         case NAND_CMD_RNDOUT:
 697                 /* No ready / busy check necessary */
 698                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 699                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 700                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 701                                NAND_NCE | NAND_CTRL_CHANGE);
 702                 return;
 703
 704         case NAND_CMD_READ0:
 705                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 706                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 707                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 708                                NAND_NCE | NAND_CTRL_CHANGE);
 709
 710                 /* This applies to read commands */
 711         default:
 712                 /*
 713                  * If we don't have access to the busy pin, we apply the given
 714                  * command delay
 715                  */
 716                 if (!chip->dev_ready) {
 717                         udelay(chip->chip_delay);
 718                         return;
 719                 }
 720         }
 721
 722         /* Apply this short delay always to ensure that we do wait tWB in
 723          * any case on any machine. */
 724         ndelay(100);
 725
 726         nand_wait_ready(mtd);
 727 }
 728
 729 /**
 730  * panic_nand_get_device - [GENERIC] Get chip for selected access
 731  * @chip:       the nand chip descriptor
 732  * @mtd:        MTD device structure
 733  * @new_state:  the state which is requested
 734  *
 735  * Used when in panic, no locks are taken.
 736  */
 737 static void panic_nand_get_device(struct nand_chip *chip,
 738                       struct mtd_info *mtd, int new_state)
 739 {
 740         /* Hardware controller shared among independend devices */
 741         chip->controller->active = chip;
 742         chip->state = new_state;
 743 }
 744
 745 /**
 746  * nand_get_device - [GENERIC] Get chip for selected access
 747  * @chip:       the nand chip descriptor
 748  * @mtd:        MTD device structure
 749  * @new_state:  the state which is requested
 750  *
 751  * Get the device and lock it for exclusive access
 752  */
 753 static int
 754 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 755 {
 756         spinlock_t *lock = &chip->controller->lock;
 757         wait_queue_head_t *wq = &chip->controller->wq;
 758         DECLARE_WAITQUEUE(wait, current);
 759  retry:
 760         spin_lock(lock);
 761
 762         /* Hardware controller shared among independent devices */
 763         if (!chip->controller->active)
 764                 chip->controller->active = chip;
 765
 766         if (chip->controller->active == chip && chip->state == FL_READY) {
 767                 chip->state = new_state;
 768                 spin_unlock(lock);
 769                 return 0;
 770         }
 771         if (new_state == FL_PM_SUSPENDED) {
 772                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 773                         chip->state = FL_PM_SUSPENDED;
 774                         spin_unlock(lock);
 775                         return 0;
 776                 } else {
 777                         spin_unlock(lock);
 778                         return -EAGAIN;
 779                 }
 780         }
 781         set_current_state(TASK_UNINTERRUPTIBLE);
 782         add_wait_queue(wq, &wait);
 783         spin_unlock(lock);
 784         schedule();
 785         remove_wait_queue(wq, &wait);
 786         goto retry;
 787 }
 788
 789 /**
 790  * panic_nand_wait - [GENERIC]  wait until the command is done
 791  * @mtd:        MTD device structure
 792  * @chip:       NAND chip structure
 793  * @timeo:      Timeout
 794  *
 795  * Wait for command done. This is a helper function for nand_wait used when
 796  * we are in interrupt context. May happen when in panic and trying to write
 797  * an oops trough mtdoops.
 798  */
 799 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 800                             unsigned long timeo)
 801 {
 802         int i;
 803         for (i = 0; i < timeo; i++) {
 804                 if (chip->dev_ready) {
 805                         if (chip->dev_ready(mtd))
 806                                 break;
 807                 } else {
 808                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 809                                 break;
 810                 }
 811                 mdelay(1);
 812         }
 813 }
 814
 815 /**
 816  * nand_wait - [DEFAULT]  wait until the command is done
 817  * @mtd:        MTD device structure
 818  * @chip:       NAND chip structure
 819  *
 820  * Wait for command done. This applies to erase and program only
 821  * Erase can take up to 400ms and program up to 20ms according to
 822  * general NAND and SmartMedia specs
 823  */
 824 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 825 {
 826
 827         unsigned long timeo = jiffies;
 828         int status, state = chip->state;
 829
 830         if (state == FL_ERASING)
 831                 timeo += (HZ * 400) / 1000;
 832         else
 833                 timeo += (HZ * 20) / 1000;
 834
 835         led_trigger_event(nand_led_trigger, LED_FULL);
 836
 837         /* Apply this short delay always to ensure that we do wait tWB in
 838          * any case on any machine. */
 839         ndelay(100);
 840
 841         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 842                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 843         else
 844                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 845
 846         if (in_interrupt() || oops_in_progress)
 847                 panic_nand_wait(mtd, chip, timeo);
 848         else {
 849                 while (time_before(jiffies, timeo)) {
 850                         if (chip->dev_ready) {
 851                                 if (chip->dev_ready(mtd))
 852                                         break;
 853                         } else {
 854                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 855                                         break;
 856                         }
 857                         cond_resched();
 858                 }
 859         }
 860         led_trigger_event(nand_led_trigger, LED_OFF);
 861
 862         status = (int)chip->read_byte(mtd);
 863         return status;
 864 }
 865
 866 /**
 867  * nand_read_page_raw - [Intern] read raw page data without ecc
 868  * @mtd:        mtd info structure
 869  * @chip:       nand chip info structure
 870  * @buf:        buffer to store read data
 871  * @page:       page number to read
 872  *
 873  * Not for syndrome calculating ecc controllers, which use a special oob layout
 874  */
 875 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 876                               uint8_t *buf, int page)
 877 {
 878         chip->read_buf(mtd, buf, mtd->writesize);
 879         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 880         return 0;
 881 }
 882
 883 /**
 884  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
 885  * @mtd:        mtd info structure
 886  * @chip:       nand chip info structure
 887  * @buf:        buffer to store read data
 888  * @page:       page number to read
 889  *
 890  * We need a special oob layout and handling even when OOB isn't used.
 891  */
 892 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
 893                               uint8_t *buf, int page)
 894 {
 895         int eccsize = chip->ecc.size;
 896         int eccbytes = chip->ecc.bytes;
 897         uint8_t *oob = chip->oob_poi;
 898         int steps, size;
 899
 900         for (steps = chip->ecc.steps; steps > 0; steps--) {
 901                 chip->read_buf(mtd, buf, eccsize);
 902                 buf += eccsize;
 903
 904                 if (chip->ecc.prepad) {
 905                         chip->read_buf(mtd, oob, chip->ecc.prepad);
 906                         oob += chip->ecc.prepad;
 907                 }
 908
 909                 chip->read_buf(mtd, oob, eccbytes);
 910                 oob += eccbytes;
 911
 912                 if (chip->ecc.postpad) {
 913                         chip->read_buf(mtd, oob, chip->ecc.postpad);
 914                         oob += chip->ecc.postpad;
 915                 }
 916         }
 917
 918         size = mtd->oobsize - (oob - chip->oob_poi);
 919         if (size)
 920                 chip->read_buf(mtd, oob, size);
 921
 922         return 0;
 923 }
 924
 925 /**
 926  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
 927  * @mtd:        mtd info structure
 928  * @chip:       nand chip info structure
 929  * @buf:        buffer to store read data
 930  * @page:       page number to read
 931  */
 932 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
 933                                 uint8_t *buf, int page)
 934 {
 935         int i, eccsize = chip->ecc.size;
 936         int eccbytes = chip->ecc.bytes;
 937         int eccsteps = chip->ecc.steps;
 938         uint8_t *p = buf;
 939         uint8_t *ecc_calc = chip->buffers->ecccalc;
 940         uint8_t *ecc_code = chip->buffers->ecccode;
 941         uint32_t *eccpos = chip->ecc.layout->eccpos;
 942
 943         chip->ecc.read_page_raw(mtd, chip, buf, page);
 944
 945         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
 946                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 947
 948         for (i = 0; i < chip->ecc.total; i++)
 949                 ecc_code[i] = chip->oob_poi[eccpos[i]];
 950
 951         eccsteps = chip->ecc.steps;
 952         p = buf;
 953
 954         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
 955                 int stat;
 956
 957                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 958                 if (stat < 0)
 959                         mtd->ecc_stats.failed++;
 960                 else
 961                         mtd->ecc_stats.corrected += stat;
 962         }
 963         return 0;
 964 }
 965
 966 /**
 967  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
 968  * @mtd:        mtd info structure
 969  * @chip:       nand chip info structure
 970  * @data_offs:  offset of requested data within the page
 971  * @readlen:    data length
 972  * @bufpoi:     buffer to store read data
 973  */
 974 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
 975 {
 976         int start_step, end_step, num_steps;
 977         uint32_t *eccpos = chip->ecc.layout->eccpos;
 978         uint8_t *p;
 979         int data_col_addr, i, gaps = 0;
 980         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
 981         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
 982
 983         /* Column address wihin the page aligned to ECC size (256bytes). */
 984         start_step = data_offs / chip->ecc.size;
 985         end_step = (data_offs + readlen - 1) / chip->ecc.size;
 986         num_steps = end_step - start_step + 1;
 987
 988         /* Data size aligned to ECC ecc.size*/
 989         datafrag_len = num_steps * chip->ecc.size;
 990         eccfrag_len = num_steps * chip->ecc.bytes;
 991
 992         data_col_addr = start_step * chip->ecc.size;
 993         /* If we read not a page aligned data */
 994         if (data_col_addr != 0)
 995                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
 996
 997         p = bufpoi + data_col_addr;
 998         chip->read_buf(mtd, p, datafrag_len);
 999
1000         /* Calculate  ECC */
1001         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1002                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1003
1004         /* The performance is faster if to position offsets
1005            according to ecc.pos. Let make sure here that
1006            there are no gaps in ecc positions */
1007         for (i = 0; i < eccfrag_len - 1; i++) {
1008                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1009                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1010                         gaps = 1;
1011                         break;
1012                 }
1013         }
1014         if (gaps) {
1015                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1016                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1017         } else {
1018                 /* send the command to read the particular ecc bytes */
1019                 /* take care about buswidth alignment in read_buf */
1020                 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1021                 aligned_len = eccfrag_len;
1022                 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1023                         aligned_len++;
1024                 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1025                         aligned_len++;
1026
1027                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1028                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1029         }
1030
1031         for (i = 0; i < eccfrag_len; i++)
1032                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1033
1034         p = bufpoi + data_col_addr;
1035         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1036                 int stat;
1037
1038                 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1039                 if (stat == -1)
1040                         mtd->ecc_stats.failed++;
1041                 else
1042                         mtd->ecc_stats.corrected += stat;
1043         }
1044         return 0;
1045 }
1046
1047 /**
1048  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1049  * @mtd:        mtd info structure
1050  * @chip:       nand chip info structure
1051  * @buf:        buffer to store read data
1052  * @page:       page number to read
1053  *
1054  * Not for syndrome calculating ecc controllers which need a special oob layout
1055  */
1056 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1057                                 uint8_t *buf, int page)
1058 {
1059         int i, eccsize = chip->ecc.size;
1060         int eccbytes = chip->ecc.bytes;
1061         int eccsteps = chip->ecc.steps;
1062         uint8_t *p = buf;
1063         uint8_t *ecc_calc = chip->buffers->ecccalc;
1064         uint8_t *ecc_code = chip->buffers->ecccode;
1065         uint32_t *eccpos = chip->ecc.layout->eccpos;
1066
1067         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1068                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1069                 chip->read_buf(mtd, p, eccsize);
1070                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1071         }
1072         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1073
1074         for (i = 0; i < chip->ecc.total; i++)
1075                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1076
1077         eccsteps = chip->ecc.steps;
1078         p = buf;
1079
1080         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1081                 int stat;
1082
1083                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1084                 if (stat < 0)
1085                         mtd->ecc_stats.failed++;
1086                 else
1087                         mtd->ecc_stats.corrected += stat;
1088         }
1089         return 0;
1090 }
1091
1092 /**
1093  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1094  * @mtd:        mtd info structure
1095  * @chip:       nand chip info structure
1096  * @buf:        buffer to store read data
1097  * @page:       page number to read
1098  *
1099  * Hardware ECC for large page chips, require OOB to be read first.
1100  * For this ECC mode, the write_page method is re-used from ECC_HW.
1101  * These methods read/write ECC from the OOB area, unlike the
1102  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1103  * "infix ECC" scheme and reads/writes ECC from the data area, by
1104  * overwriting the NAND manufacturer bad block markings.
1105  */
1106 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1107         struct nand_chip *chip, uint8_t *buf, int page)
1108 {
1109         int i, eccsize = chip->ecc.size;
1110         int eccbytes = chip->ecc.bytes;
1111         int eccsteps = chip->ecc.steps;
1112         uint8_t *p = buf;
1113         uint8_t *ecc_code = chip->buffers->ecccode;
1114         uint32_t *eccpos = chip->ecc.layout->eccpos;
1115         uint8_t *ecc_calc = chip->buffers->ecccalc;
1116
1117         /* Read the OOB area first */
1118         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1119         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1120         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1121
1122         for (i = 0; i < chip->ecc.total; i++)
1123                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1124
1125         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1126                 int stat;
1127
1128                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1129                 chip->read_buf(mtd, p, eccsize);
1130                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1131
1132                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1133                 if (stat < 0)
1134                         mtd->ecc_stats.failed++;
1135                 else
1136                         mtd->ecc_stats.corrected += stat;
1137         }
1138         return 0;
1139 }
1140
1141 /**
1142  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1143  * @mtd:        mtd info structure
1144  * @chip:       nand chip info structure
1145  * @buf:        buffer to store read data
1146  * @page:       page number to read
1147  *
1148  * The hw generator calculates the error syndrome automatically. Therefor
1149  * we need a special oob layout and handling.
1150  */
1151 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1152                                    uint8_t *buf, int page)
1153 {
1154         int i, eccsize = chip->ecc.size;
1155         int eccbytes = chip->ecc.bytes;
1156         int eccsteps = chip->ecc.steps;
1157         uint8_t *p = buf;
1158         uint8_t *oob = chip->oob_poi;
1159
1160         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1161                 int stat;
1162
1163                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1164                 chip->read_buf(mtd, p, eccsize);
1165
1166                 if (chip->ecc.prepad) {
1167                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1168                         oob += chip->ecc.prepad;
1169                 }
1170
1171                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1172                 chip->read_buf(mtd, oob, eccbytes);
1173                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1174
1175                 if (stat < 0)
1176                         mtd->ecc_stats.failed++;
1177                 else
1178                         mtd->ecc_stats.corrected += stat;
1179
1180                 oob += eccbytes;
1181
1182                 if (chip->ecc.postpad) {
1183                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1184                         oob += chip->ecc.postpad;
1185                 }
1186         }
1187
1188         /* Calculate remaining oob bytes */
1189         i = mtd->oobsize - (oob - chip->oob_poi);
1190         if (i)
1191                 chip->read_buf(mtd, oob, i);
1192
1193         return 0;
1194 }
1195
1196 /**
1197  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1198  * @chip:       nand chip structure
1199  * @oob:        oob destination address
1200  * @ops:        oob ops structure
1201  * @len:        size of oob to transfer
1202  */
1203 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1204                                   struct mtd_oob_ops *ops, size_t len)
1205 {
1206         switch(ops->mode) {
1207
1208         case MTD_OOB_PLACE:
1209         case MTD_OOB_RAW:
1210                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1211                 return oob + len;
1212
1213         case MTD_OOB_AUTO: {
1214                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1215                 uint32_t boffs = 0, roffs = ops->ooboffs;
1216                 size_t bytes = 0;
1217
1218                 for(; free->length && len; free++, len -= bytes) {
1219                         /* Read request not from offset 0 ? */
1220                         if (unlikely(roffs)) {
1221                                 if (roffs >= free->length) {
1222                                         roffs -= free->length;
1223                                         continue;
1224                                 }
1225                                 boffs = free->offset + roffs;
1226                                 bytes = min_t(size_t, len,
1227                                               (free->length - roffs));
1228                                 roffs = 0;
1229                         } else {
1230                                 bytes = min_t(size_t, len, free->length);
1231                                 boffs = free->offset;
1232                         }
1233                         memcpy(oob, chip->oob_poi + boffs, bytes);
1234                         oob += bytes;
1235                 }
1236                 return oob;
1237         }
1238         default:
1239                 BUG();
1240         }
1241         return NULL;
1242 }
1243
1244 /**
1245  * nand_do_read_ops - [Internal] Read data with ECC
1246  *
1247  * @mtd:        MTD device structure
1248  * @from:       offset to read from
1249  * @ops:        oob ops structure
1250  *
1251  * Internal function. Called with chip held.
1252  */
1253 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1254                             struct mtd_oob_ops *ops)
1255 {
1256         int chipnr, page, realpage, col, bytes, aligned;
1257         struct nand_chip *chip = mtd->priv;
1258         struct mtd_ecc_stats stats;
1259         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1260         int sndcmd = 1;
1261         int ret = 0;
1262         uint32_t readlen = ops->len;
1263         uint32_t oobreadlen = ops->ooblen;
1264         uint8_t *bufpoi, *oob, *buf;
1265
1266         stats = mtd->ecc_stats;
1267
1268         chipnr = (int)(from >> chip->chip_shift);
1269         chip->select_chip(mtd, chipnr);
1270
1271         realpage = (int)(from >> chip->page_shift);
1272         page = realpage & chip->pagemask;
1273
1274         col = (int)(from & (mtd->writesize - 1));
1275
1276         buf = ops->datbuf;
1277         oob = ops->oobbuf;
1278
1279         while(1) {
1280                 bytes = min(mtd->writesize - col, readlen);
1281                 aligned = (bytes == mtd->writesize);
1282
1283                 /* Is the current page in the buffer ? */
1284                 if (realpage != chip->pagebuf || oob) {
1285                         bufpoi = aligned ? buf : chip->buffers->databuf;
1286
1287                         if (likely(sndcmd)) {
1288                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1289                                 sndcmd = 0;
1290                         }
1291
1292                         /* Now read the page into the buffer */
1293                         if (unlikely(ops->mode == MTD_OOB_RAW))
1294                                 ret = chip->ecc.read_page_raw(mtd, chip,
1295                                                               bufpoi, page);
1296                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1297                                 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1298                         else
1299                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1300                                                           page);
1301                         if (ret < 0)
1302                                 break;
1303
1304                         /* Transfer not aligned data */
1305                         if (!aligned) {
1306                                 if (!NAND_SUBPAGE_READ(chip) && !oob)
1307                                         chip->pagebuf = realpage;
1308                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1309                         }
1310
1311                         buf += bytes;
1312
1313                         if (unlikely(oob)) {
1314                                 /* Raw mode does data:oob:data:oob */
1315                                 if (ops->mode != MTD_OOB_RAW) {
1316                                         int toread = min(oobreadlen,
1317                                                 chip->ecc.layout->oobavail);
1318                                         if (toread) {
1319                                                 oob = nand_transfer_oob(chip,
1320                                                         oob, ops, toread);
1321                                                 oobreadlen -= toread;
1322                                         }
1323                                 } else
1324                                         buf = nand_transfer_oob(chip,
1325                                                 buf, ops, mtd->oobsize);
1326                         }
1327
1328                         if (!(chip->options & NAND_NO_READRDY)) {
1329                                 /*
1330                                  * Apply delay or wait for ready/busy pin. Do
1331                                  * this before the AUTOINCR check, so no
1332                                  * problems arise if a chip which does auto
1333                                  * increment is marked as NOAUTOINCR by the
1334                                  * board driver.
1335                                  */
1336                                 if (!chip->dev_ready)
1337                                         udelay(chip->chip_delay);
1338                                 else
1339                                         nand_wait_ready(mtd);
1340                         }
1341                 } else {
1342                         memcpy(buf, chip->buffers->databuf + col, bytes);
1343                         buf += bytes;
1344                 }
1345
1346                 readlen -= bytes;
1347
1348                 if (!readlen)
1349                         break;
1350
1351                 /* For subsequent reads align to page boundary. */
1352                 col = 0;
1353                 /* Increment page address */
1354                 realpage++;
1355
1356                 page = realpage & chip->pagemask;
1357                 /* Check, if we cross a chip boundary */
1358                 if (!page) {
1359                         chipnr++;
1360                         chip->select_chip(mtd, -1);
1361                         chip->select_chip(mtd, chipnr);
1362                 }
1363
1364                 /* Check, if the chip supports auto page increment
1365                  * or if we have hit a block boundary.
1366                  */
1367                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1368                         sndcmd = 1;
1369         }
1370
1371         ops->retlen = ops->len - (size_t) readlen;
1372         if (oob)
1373                 ops->oobretlen = ops->ooblen - oobreadlen;
1374
1375         if (ret)
1376                 return ret;
1377
1378         if (mtd->ecc_stats.failed - stats.failed)
1379                 return -EBADMSG;
1380
1381         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1382 }
1383
1384 /**
1385  * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1386  * @mtd:        MTD device structure
1387  * @from:       offset to read from
1388  * @len:        number of bytes to read
1389  * @retlen:     pointer to variable to store the number of read bytes
1390  * @buf:        the databuffer to put data
1391  *
1392  * Get hold of the chip and call nand_do_read
1393  */
1394 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1395                      size_t *retlen, uint8_t *buf)
1396 {
1397         struct nand_chip *chip = mtd->priv;
1398         int ret;
1399
1400         /* Do not allow reads past end of device */
1401         if ((from + len) > mtd->size)
1402                 return -EINVAL;
1403         if (!len)
1404                 return 0;
1405
1406         nand_get_device(chip, mtd, FL_READING);
1407
1408         chip->ops.len = len;
1409         chip->ops.datbuf = buf;
1410         chip->ops.oobbuf = NULL;
1411
1412         ret = nand_do_read_ops(mtd, from, &chip->ops);
1413
1414         *retlen = chip->ops.retlen;
1415
1416         nand_release_device(mtd);
1417
1418         return ret;
1419 }
1420
1421 /**
1422  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1423  * @mtd:        mtd info structure
1424  * @chip:       nand chip info structure
1425  * @page:       page number to read
1426  * @sndcmd:     flag whether to issue read command or not
1427  */
1428 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1429                              int page, int sndcmd)
1430 {
1431         if (sndcmd) {
1432                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1433                 sndcmd = 0;
1434         }
1435         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1436         return sndcmd;
1437 }
1438
1439 /**
1440  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1441  *                          with syndromes
1442  * @mtd:        mtd info structure
1443  * @chip:       nand chip info structure
1444  * @page:       page number to read
1445  * @sndcmd:     flag whether to issue read command or not
1446  */
1447 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1448                                   int page, int sndcmd)
1449 {
1450         uint8_t *buf = chip->oob_poi;
1451         int length = mtd->oobsize;
1452         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1453         int eccsize = chip->ecc.size;
1454         uint8_t *bufpoi = buf;
1455         int i, toread, sndrnd = 0, pos;
1456
1457         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1458         for (i = 0; i < chip->ecc.steps; i++) {
1459                 if (sndrnd) {
1460                         pos = eccsize + i * (eccsize + chunk);
1461                         if (mtd->writesize > 512)
1462                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1463                         else
1464                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1465                 } else
1466                         sndrnd = 1;
1467                 toread = min_t(int, length, chunk);
1468                 chip->read_buf(mtd, bufpoi, toread);
1469                 bufpoi += toread;
1470                 length -= toread;
1471         }
1472         if (length > 0)
1473                 chip->read_buf(mtd, bufpoi, length);
1474
1475         return 1;
1476 }
1477
1478 /**
1479  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1480  * @mtd:        mtd info structure
1481  * @chip:       nand chip info structure
1482  * @page:       page number to write
1483  */
1484 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1485                               int page)
1486 {
1487         int status = 0;
1488         const uint8_t *buf = chip->oob_poi;
1489         int length = mtd->oobsize;
1490
1491         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1492         chip->write_buf(mtd, buf, length);
1493         /* Send command to program the OOB data */
1494         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1495
1496         status = chip->waitfunc(mtd, chip);
1497
1498         return status & NAND_STATUS_FAIL ? -EIO : 0;
1499 }
1500
1501 /**
1502  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1503  *                           with syndrome - only for large page flash !
1504  * @mtd:        mtd info structure
1505  * @chip:       nand chip info structure
1506  * @page:       page number to write
1507  */
1508 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1509                                    struct nand_chip *chip, int page)
1510 {
1511         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1512         int eccsize = chip->ecc.size, length = mtd->oobsize;
1513         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1514         const uint8_t *bufpoi = chip->oob_poi;
1515
1516         /*
1517          * data-ecc-data-ecc ... ecc-oob
1518          * or
1519          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1520          */
1521         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1522                 pos = steps * (eccsize + chunk);
1523                 steps = 0;
1524         } else
1525                 pos = eccsize;
1526
1527         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1528         for (i = 0; i < steps; i++) {
1529                 if (sndcmd) {
1530                         if (mtd->writesize <= 512) {
1531                                 uint32_t fill = 0xFFFFFFFF;
1532
1533                                 len = eccsize;
1534                                 while (len > 0) {
1535                                         int num = min_t(int, len, 4);
1536                                         chip->write_buf(mtd, (uint8_t *)&fill,
1537                                                         num);
1538                                         len -= num;
1539                                 }
1540                         } else {
1541                                 pos = eccsize + i * (eccsize + chunk);
1542                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1543                         }
1544                 } else
1545                         sndcmd = 1;
1546                 len = min_t(int, length, chunk);
1547                 chip->write_buf(mtd, bufpoi, len);
1548                 bufpoi += len;
1549                 length -= len;
1550         }
1551         if (length > 0)
1552                 chip->write_buf(mtd, bufpoi, length);
1553
1554         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1555         status = chip->waitfunc(mtd, chip);
1556
1557         return status & NAND_STATUS_FAIL ? -EIO : 0;
1558 }
1559
1560 /**
1561  * nand_do_read_oob - [Intern] NAND read out-of-band
1562  * @mtd:        MTD device structure
1563  * @from:       offset to read from
1564  * @ops:        oob operations description structure
1565  *
1566  * NAND read out-of-band data from the spare area
1567  */
1568 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1569                             struct mtd_oob_ops *ops)
1570 {
1571         int page, realpage, chipnr, sndcmd = 1;
1572         struct nand_chip *chip = mtd->priv;
1573         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1574         int readlen = ops->ooblen;
1575         int len;
1576         uint8_t *buf = ops->oobbuf;
1577
1578         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1579                         __func__, (unsigned long long)from, readlen);
1580
1581         if (ops->mode == MTD_OOB_AUTO)
1582                 len = chip->ecc.layout->oobavail;
1583         else
1584                 len = mtd->oobsize;
1585
1586         if (unlikely(ops->ooboffs >= len)) {
1587                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1588                                         "outside oob\n", __func__);
1589                 return -EINVAL;
1590         }
1591
1592         /* Do not allow reads past end of device */
1593         if (unlikely(from >= mtd->size ||
1594                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1595                                         (from >> chip->page_shift)) * len)) {
1596                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1597                                         "of device\n", __func__);
1598                 return -EINVAL;
1599         }
1600
1601         chipnr = (int)(from >> chip->chip_shift);
1602         chip->select_chip(mtd, chipnr);
1603
1604         /* Shift to get page */
1605         realpage = (int)(from >> chip->page_shift);
1606         page = realpage & chip->pagemask;
1607
1608         while(1) {
1609                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1610
1611                 len = min(len, readlen);
1612                 buf = nand_transfer_oob(chip, buf, ops, len);
1613
1614                 if (!(chip->options & NAND_NO_READRDY)) {
1615                         /*
1616                          * Apply delay or wait for ready/busy pin. Do this
1617                          * before the AUTOINCR check, so no problems arise if a
1618                          * chip which does auto increment is marked as
1619                          * NOAUTOINCR by the board driver.
1620                          */
1621                         if (!chip->dev_ready)
1622                                 udelay(chip->chip_delay);
1623                         else
1624                                 nand_wait_ready(mtd);
1625                 }
1626
1627                 readlen -= len;
1628                 if (!readlen)
1629                         break;
1630
1631                 /* Increment page address */
1632                 realpage++;
1633
1634                 page = realpage & chip->pagemask;
1635                 /* Check, if we cross a chip boundary */
1636                 if (!page) {
1637                         chipnr++;
1638                         chip->select_chip(mtd, -1);
1639                         chip->select_chip(mtd, chipnr);
1640                 }
1641
1642                 /* Check, if the chip supports auto page increment
1643                  * or if we have hit a block boundary.
1644                  */
1645                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1646                         sndcmd = 1;
1647         }
1648
1649         ops->oobretlen = ops->ooblen;
1650         return 0;
1651 }
1652
1653 /**
1654  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1655  * @mtd:        MTD device structure
1656  * @from:       offset to read from
1657  * @ops:        oob operation description structure
1658  *
1659  * NAND read data and/or out-of-band data
1660  */
1661 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1662                          struct mtd_oob_ops *ops)
1663 {
1664         struct nand_chip *chip = mtd->priv;
1665         int ret = -ENOTSUPP;
1666
1667         ops->retlen = 0;
1668
1669         /* Do not allow reads past end of device */
1670         if (ops->datbuf && (from + ops->len) > mtd->size) {
1671                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1672                                 "beyond end of device\n", __func__);
1673                 return -EINVAL;
1674         }
1675
1676         nand_get_device(chip, mtd, FL_READING);
1677
1678         switch(ops->mode) {
1679         case MTD_OOB_PLACE:
1680         case MTD_OOB_AUTO:
1681         case MTD_OOB_RAW:
1682                 break;
1683
1684         default:
1685                 goto out;
1686         }
1687
1688         if (!ops->datbuf)
1689                 ret = nand_do_read_oob(mtd, from, ops);
1690         else
1691                 ret = nand_do_read_ops(mtd, from, ops);
1692
1693  out:
1694         nand_release_device(mtd);
1695         return ret;
1696 }
1697
1698
1699 /**
1700  * nand_write_page_raw - [Intern] raw page write function
1701  * @mtd:        mtd info structure
1702  * @chip:       nand chip info structure
1703  * @buf:        data buffer
1704  *
1705  * Not for syndrome calculating ecc controllers, which use a special oob layout
1706  */
1707 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1708                                 const uint8_t *buf)
1709 {
1710         chip->write_buf(mtd, buf, mtd->writesize);
1711         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1712 }
1713
1714 /**
1715  * nand_write_page_raw_syndrome - [Intern] raw page write function
1716  * @mtd:        mtd info structure
1717  * @chip:       nand chip info structure
1718  * @buf:        data buffer
1719  *
1720  * We need a special oob layout and handling even when ECC isn't checked.
1721  */
1722 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1723                                 const uint8_t *buf)
1724 {
1725         int eccsize = chip->ecc.size;
1726         int eccbytes = chip->ecc.bytes;
1727         uint8_t *oob = chip->oob_poi;
1728         int steps, size;
1729
1730         for (steps = chip->ecc.steps; steps > 0; steps--) {
1731                 chip->write_buf(mtd, buf, eccsize);
1732                 buf += eccsize;
1733
1734                 if (chip->ecc.prepad) {
1735                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1736                         oob += chip->ecc.prepad;
1737                 }
1738
1739                 chip->read_buf(mtd, oob, eccbytes);
1740                 oob += eccbytes;
1741
1742                 if (chip->ecc.postpad) {
1743                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1744                         oob += chip->ecc.postpad;
1745                 }
1746         }
1747
1748         size = mtd->oobsize - (oob - chip->oob_poi);
1749         if (size)
1750                 chip->write_buf(mtd, oob, size);
1751 }
1752 /**
1753  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1754  * @mtd:        mtd info structure
1755  * @chip:       nand chip info structure
1756  * @buf:        data buffer
1757  */
1758 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1759                                   const uint8_t *buf)
1760 {
1761         int i, eccsize = chip->ecc.size;
1762         int eccbytes = chip->ecc.bytes;
1763         int eccsteps = chip->ecc.steps;
1764         uint8_t *ecc_calc = chip->buffers->ecccalc;
1765         const uint8_t *p = buf;
1766         uint32_t *eccpos = chip->ecc.layout->eccpos;
1767
1768         /* Software ecc calculation */
1769         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1770                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1771
1772         for (i = 0; i < chip->ecc.total; i++)
1773                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1774
1775         chip->ecc.write_page_raw(mtd, chip, buf);
1776 }
1777
1778 /**
1779  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1780  * @mtd:        mtd info structure
1781  * @chip:       nand chip info structure
1782  * @buf:        data buffer
1783  */
1784 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1785                                   const uint8_t *buf)
1786 {
1787         int i, eccsize = chip->ecc.size;
1788         int eccbytes = chip->ecc.bytes;
1789         int eccsteps = chip->ecc.steps;
1790         uint8_t *ecc_calc = chip->buffers->ecccalc;
1791         const uint8_t *p = buf;
1792         uint32_t *eccpos = chip->ecc.layout->eccpos;
1793
1794         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1795                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1796                 chip->write_buf(mtd, p, eccsize);
1797                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1798         }
1799
1800         for (i = 0; i < chip->ecc.total; i++)
1801                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1802
1803         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1804 }
1805
1806 /**
1807  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1808  * @mtd:        mtd info structure
1809  * @chip:       nand chip info structure
1810  * @buf:        data buffer
1811  *
1812  * The hw generator calculates the error syndrome automatically. Therefor
1813  * we need a special oob layout and handling.
1814  */
1815 static void nand_write_page_syndrome(struct mtd_info *mtd,
1816                                     struct nand_chip *chip, const uint8_t *buf)
1817 {
1818         int i, eccsize = chip->ecc.size;
1819         int eccbytes = chip->ecc.bytes;
1820         int eccsteps = chip->ecc.steps;
1821         const uint8_t *p = buf;
1822         uint8_t *oob = chip->oob_poi;
1823
1824         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1825
1826                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1827                 chip->write_buf(mtd, p, eccsize);
1828
1829                 if (chip->ecc.prepad) {
1830                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1831                         oob += chip->ecc.prepad;
1832                 }
1833
1834                 chip->ecc.calculate(mtd, p, oob);
1835                 chip->write_buf(mtd, oob, eccbytes);
1836                 oob += eccbytes;
1837
1838                 if (chip->ecc.postpad) {
1839                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1840                         oob += chip->ecc.postpad;
1841                 }
1842         }
1843
1844         /* Calculate remaining oob bytes */
1845         i = mtd->oobsize - (oob - chip->oob_poi);
1846         if (i)
1847                 chip->write_buf(mtd, oob, i);
1848 }
1849
1850 /**
1851  * nand_write_page - [REPLACEABLE] write one page
1852  * @mtd:        MTD device structure
1853  * @chip:       NAND chip descriptor
1854  * @buf:        the data to write
1855  * @page:       page number to write
1856  * @cached:     cached programming
1857  * @raw:        use _raw version of write_page
1858  */
1859 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1860                            const uint8_t *buf, int page, int cached, int raw)
1861 {
1862         int status;
1863
1864         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
1865
1866         if (unlikely(raw))
1867                 chip->ecc.write_page_raw(mtd, chip, buf);
1868         else
1869                 chip->ecc.write_page(mtd, chip, buf);
1870
1871         /*
1872          * Cached progamming disabled for now, Not sure if its worth the
1873          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
1874          */
1875         cached = 0;
1876
1877         if (!cached || !(chip->options & NAND_CACHEPRG)) {
1878
1879                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1880                 status = chip->waitfunc(mtd, chip);
1881                 /*
1882                  * See if operation failed and additional status checks are
1883                  * available
1884                  */
1885                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
1886                         status = chip->errstat(mtd, chip, FL_WRITING, status,
1887                                                page);
1888
1889                 if (status & NAND_STATUS_FAIL)
1890                         return -EIO;
1891         } else {
1892                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
1893                 status = chip->waitfunc(mtd, chip);
1894         }
1895
1896 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
1897         /* Send command to read back the data */
1898         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1899
1900         if (chip->verify_buf(mtd, buf, mtd->writesize))
1901                 return -EIO;
1902 #endif
1903         return 0;
1904 }
1905
1906 /**
1907  * nand_fill_oob - [Internal] Transfer client buffer to oob
1908  * @chip:       nand chip structure
1909  * @oob:        oob data buffer
1910  * @ops:        oob ops structure
1911  */
1912 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob,
1913                                   struct mtd_oob_ops *ops)
1914 {
1915         size_t len = ops->ooblen;
1916
1917         switch(ops->mode) {
1918
1919         case MTD_OOB_PLACE:
1920         case MTD_OOB_RAW:
1921                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
1922                 return oob + len;
1923
1924         case MTD_OOB_AUTO: {
1925                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1926                 uint32_t boffs = 0, woffs = ops->ooboffs;
1927                 size_t bytes = 0;
1928
1929                 for(; free->length && len; free++, len -= bytes) {
1930                         /* Write request not from offset 0 ? */
1931                         if (unlikely(woffs)) {
1932                                 if (woffs >= free->length) {
1933                                         woffs -= free->length;
1934                                         continue;
1935                                 }
1936                                 boffs = free->offset + woffs;
1937                                 bytes = min_t(size_t, len,
1938                                               (free->length - woffs));
1939                                 woffs = 0;
1940                         } else {
1941                                 bytes = min_t(size_t, len, free->length);
1942                                 boffs = free->offset;
1943                         }
1944                         memcpy(chip->oob_poi + boffs, oob, bytes);
1945                         oob += bytes;
1946                 }
1947                 return oob;
1948         }
1949         default:
1950                 BUG();
1951         }
1952         return NULL;
1953 }
1954
1955 #define NOTALIGNED(x)   (x & (chip->subpagesize - 1)) != 0
1956
1957 /**
1958  * nand_do_write_ops - [Internal] NAND write with ECC
1959  * @mtd:        MTD device structure
1960  * @to:         offset to write to
1961  * @ops:        oob operations description structure
1962  *
1963  * NAND write with ECC
1964  */
1965 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
1966                              struct mtd_oob_ops *ops)
1967 {
1968         int chipnr, realpage, page, blockmask, column;
1969         struct nand_chip *chip = mtd->priv;
1970         uint32_t writelen = ops->len;
1971         uint8_t *oob = ops->oobbuf;
1972         uint8_t *buf = ops->datbuf;
1973         int ret, subpage;
1974
1975         ops->retlen = 0;
1976         if (!writelen)
1977                 return 0;
1978
1979         /* reject writes, which are not page aligned */
1980         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
1981                 printk(KERN_NOTICE "%s: Attempt to write not "
1982                                 "page aligned data\n", __func__);
1983                 return -EINVAL;
1984         }
1985
1986         column = to & (mtd->writesize - 1);
1987         subpage = column || (writelen & (mtd->writesize - 1));
1988
1989         if (subpage && oob)
1990                 return -EINVAL;
1991
1992         chipnr = (int)(to >> chip->chip_shift);
1993         chip->select_chip(mtd, chipnr);
1994
1995         /* Check, if it is write protected */
1996         if (nand_check_wp(mtd))
1997                 return -EIO;
1998
1999         realpage = (int)(to >> chip->page_shift);
2000         page = realpage & chip->pagemask;
2001         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2002
2003         /* Invalidate the page cache, when we write to the cached page */
2004         if (to <= (chip->pagebuf << chip->page_shift) &&
2005             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2006                 chip->pagebuf = -1;
2007
2008         /* If we're not given explicit OOB data, let it be 0xFF */
2009         if (likely(!oob))
2010                 memset(chip->oob_poi, 0xff, mtd->oobsize);
2011
2012         while(1) {
2013                 int bytes = mtd->writesize;
2014                 int cached = writelen > bytes && page != blockmask;
2015                 uint8_t *wbuf = buf;
2016
2017                 /* Partial page write ? */
2018                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2019                         cached = 0;
2020                         bytes = min_t(int, bytes - column, (int) writelen);
2021                         chip->pagebuf = -1;
2022                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2023                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2024                         wbuf = chip->buffers->databuf;
2025                 }
2026
2027                 if (unlikely(oob))
2028                         oob = nand_fill_oob(chip, oob, ops);
2029
2030                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2031                                        (ops->mode == MTD_OOB_RAW));
2032                 if (ret)
2033                         break;
2034
2035                 writelen -= bytes;
2036                 if (!writelen)
2037                         break;
2038
2039                 column = 0;
2040                 buf += bytes;
2041                 realpage++;
2042
2043                 page = realpage & chip->pagemask;
2044                 /* Check, if we cross a chip boundary */
2045                 if (!page) {
2046                         chipnr++;
2047                         chip->select_chip(mtd, -1);
2048                         chip->select_chip(mtd, chipnr);
2049                 }
2050         }
2051
2052         ops->retlen = ops->len - writelen;
2053         if (unlikely(oob))
2054                 ops->oobretlen = ops->ooblen;
2055         return ret;
2056 }
2057
2058 /**
2059  * panic_nand_write - [MTD Interface] NAND write with ECC
2060  * @mtd:        MTD device structure
2061  * @to:         offset to write to
2062  * @len:        number of bytes to write
2063  * @retlen:     pointer to variable to store the number of written bytes
2064  * @buf:        the data to write
2065  *
2066  * NAND write with ECC. Used when performing writes in interrupt context, this
2067  * may for example be called by mtdoops when writing an oops while in panic.
2068  */
2069 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2070                             size_t *retlen, const uint8_t *buf)
2071 {
2072         struct nand_chip *chip = mtd->priv;
2073         int ret;
2074
2075         /* Do not allow reads past end of device */
2076         if ((to + len) > mtd->size)
2077                 return -EINVAL;
2078         if (!len)
2079                 return 0;
2080
2081         /* Wait for the device to get ready.  */
2082         panic_nand_wait(mtd, chip, 400);
2083
2084         /* Grab the device.  */
2085         panic_nand_get_device(chip, mtd, FL_WRITING);
2086
2087         chip->ops.len = len;
2088         chip->ops.datbuf = (uint8_t *)buf;
2089         chip->ops.oobbuf = NULL;
2090
2091         ret = nand_do_write_ops(mtd, to, &chip->ops);
2092
2093         *retlen = chip->ops.retlen;
2094         return ret;
2095 }
2096
2097 /**
2098  * nand_write - [MTD Interface] NAND write with ECC
2099  * @mtd:        MTD device structure
2100  * @to:         offset to write to
2101  * @len:        number of bytes to write
2102  * @retlen:     pointer to variable to store the number of written bytes
2103  * @buf:        the data to write
2104  *
2105  * NAND write with ECC
2106  */
2107 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2108                           size_t *retlen, const uint8_t *buf)
2109 {
2110         struct nand_chip *chip = mtd->priv;
2111         int ret;
2112
2113         /* Do not allow reads past end of device */
2114         if ((to + len) > mtd->size)
2115                 return -EINVAL;
2116         if (!len)
2117                 return 0;
2118
2119         nand_get_device(chip, mtd, FL_WRITING);
2120
2121         chip->ops.len = len;
2122         chip->ops.datbuf = (uint8_t *)buf;
2123         chip->ops.oobbuf = NULL;
2124
2125         ret = nand_do_write_ops(mtd, to, &chip->ops);
2126
2127         *retlen = chip->ops.retlen;
2128
2129         nand_release_device(mtd);
2130
2131         return ret;
2132 }
2133
2134 /**
2135  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2136  * @mtd:        MTD device structure
2137  * @to:         offset to write to
2138  * @ops:        oob operation description structure
2139  *
2140  * NAND write out-of-band
2141  */
2142 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2143                              struct mtd_oob_ops *ops)
2144 {
2145         int chipnr, page, status, len;
2146         struct nand_chip *chip = mtd->priv;
2147
2148         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2149                          __func__, (unsigned int)to, (int)ops->ooblen);
2150
2151         if (ops->mode == MTD_OOB_AUTO)
2152                 len = chip->ecc.layout->oobavail;
2153         else
2154                 len = mtd->oobsize;
2155
2156         /* Do not allow write past end of page */
2157         if ((ops->ooboffs + ops->ooblen) > len) {
2158                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2159                                 "past end of page\n", __func__);
2160                 return -EINVAL;
2161         }
2162
2163         if (unlikely(ops->ooboffs >= len)) {
2164                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2165                                 "write outside oob\n", __func__);
2166                 return -EINVAL;
2167         }
2168
2169         /* Do not allow reads past end of device */
2170         if (unlikely(to >= mtd->size ||
2171                      ops->ooboffs + ops->ooblen >
2172                         ((mtd->size >> chip->page_shift) -
2173                          (to >> chip->page_shift)) * len)) {
2174                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2175                                 "end of device\n", __func__);
2176                 return -EINVAL;
2177         }
2178
2179         chipnr = (int)(to >> chip->chip_shift);
2180         chip->select_chip(mtd, chipnr);
2181
2182         /* Shift to get page */
2183         page = (int)(to >> chip->page_shift);
2184
2185         /*
2186          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2187          * of my DiskOnChip 2000 test units) will clear the whole data page too
2188          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2189          * it in the doc2000 driver in August 1999.  dwmw2.
2190          */
2191         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2192
2193         /* Check, if it is write protected */
2194         if (nand_check_wp(mtd))
2195                 return -EROFS;
2196
2197         /* Invalidate the page cache, if we write to the cached page */
2198         if (page == chip->pagebuf)
2199                 chip->pagebuf = -1;
2200
2201         memset(chip->oob_poi, 0xff, mtd->oobsize);
2202         nand_fill_oob(chip, ops->oobbuf, ops);
2203         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2204         memset(chip->oob_poi, 0xff, mtd->oobsize);
2205
2206         if (status)
2207                 return status;
2208
2209         ops->oobretlen = ops->ooblen;
2210
2211         return 0;
2212 }
2213
2214 /**
2215  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2216  * @mtd:        MTD device structure
2217  * @to:         offset to write to
2218  * @ops:        oob operation description structure
2219  */
2220 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2221                           struct mtd_oob_ops *ops)
2222 {
2223         struct nand_chip *chip = mtd->priv;
2224         int ret = -ENOTSUPP;
2225
2226         ops->retlen = 0;
2227
2228         /* Do not allow writes past end of device */
2229         if (ops->datbuf && (to + ops->len) > mtd->size) {
2230                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2231                                 "end of device\n", __func__);
2232                 return -EINVAL;
2233         }
2234
2235         nand_get_device(chip, mtd, FL_WRITING);
2236
2237         switch(ops->mode) {
2238         case MTD_OOB_PLACE:
2239         case MTD_OOB_AUTO:
2240         case MTD_OOB_RAW:
2241                 break;
2242
2243         default:
2244                 goto out;
2245         }
2246
2247         if (!ops->datbuf)
2248                 ret = nand_do_write_oob(mtd, to, ops);
2249         else
2250                 ret = nand_do_write_ops(mtd, to, ops);
2251
2252  out:
2253         nand_release_device(mtd);
2254         return ret;
2255 }
2256
2257 /**
2258  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2259  * @mtd:        MTD device structure
2260  * @page:       the page address of the block which will be erased
2261  *
2262  * Standard erase command for NAND chips
2263  */
2264 static void single_erase_cmd(struct mtd_info *mtd, int page)
2265 {
2266         struct nand_chip *chip = mtd->priv;
2267         /* Send commands to erase a block */
2268         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2269         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2270 }
2271
2272 /**
2273  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2274  * @mtd:        MTD device structure
2275  * @page:       the page address of the block which will be erased
2276  *
2277  * AND multi block erase command function
2278  * Erase 4 consecutive blocks
2279  */
2280 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2281 {
2282         struct nand_chip *chip = mtd->priv;
2283         /* Send commands to erase a block */
2284         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2285         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2286         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2287         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2288         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2289 }
2290
2291 /**
2292  * nand_erase - [MTD Interface] erase block(s)
2293  * @mtd:        MTD device structure
2294  * @instr:      erase instruction
2295  *
2296  * Erase one ore more blocks
2297  */
2298 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2299 {
2300         return nand_erase_nand(mtd, instr, 0);
2301 }
2302
2303 #define BBT_PAGE_MASK   0xffffff3f
2304 /**
2305  * nand_erase_nand - [Internal] erase block(s)
2306  * @mtd:        MTD device structure
2307  * @instr:      erase instruction
2308  * @allowbbt:   allow erasing the bbt area
2309  *
2310  * Erase one ore more blocks
2311  */
2312 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2313                     int allowbbt)
2314 {
2315         int page, status, pages_per_block, ret, chipnr;
2316         struct nand_chip *chip = mtd->priv;
2317         loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2318         unsigned int bbt_masked_page = 0xffffffff;
2319         loff_t len;
2320
2321         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2322                                 __func__, (unsigned long long)instr->addr,
2323                                 (unsigned long long)instr->len);
2324
2325         if (check_offs_len(mtd, instr->addr, instr->len))
2326                 return -EINVAL;
2327
2328         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2329
2330         /* Grab the lock and see if the device is available */
2331         nand_get_device(chip, mtd, FL_ERASING);
2332
2333         /* Shift to get first page */
2334         page = (int)(instr->addr >> chip->page_shift);
2335         chipnr = (int)(instr->addr >> chip->chip_shift);
2336
2337         /* Calculate pages in each block */
2338         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2339
2340         /* Select the NAND device */
2341         chip->select_chip(mtd, chipnr);
2342
2343         /* Check, if it is write protected */
2344         if (nand_check_wp(mtd)) {
2345                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2346                                         __func__);
2347                 instr->state = MTD_ERASE_FAILED;
2348                 goto erase_exit;
2349         }
2350
2351         /*
2352          * If BBT requires refresh, set the BBT page mask to see if the BBT
2353          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2354          * can not be matched. This is also done when the bbt is actually
2355          * erased to avoid recusrsive updates
2356          */
2357         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2358                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2359
2360         /* Loop through the pages */
2361         len = instr->len;
2362
2363         instr->state = MTD_ERASING;
2364
2365         while (len) {
2366                 /*
2367                  * heck if we have a bad block, we do not erase bad blocks !
2368                  */
2369                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2370                                         chip->page_shift, 0, allowbbt)) {
2371                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2372                                         "at page 0x%08x\n", __func__, page);
2373                         instr->state = MTD_ERASE_FAILED;
2374                         goto erase_exit;
2375                 }
2376
2377                 /*
2378                  * Invalidate the page cache, if we erase the block which
2379                  * contains the current cached page
2380                  */
2381                 if (page <= chip->pagebuf && chip->pagebuf <
2382                     (page + pages_per_block))
2383                         chip->pagebuf = -1;
2384
2385                 chip->erase_cmd(mtd, page & chip->pagemask);
2386
2387                 status = chip->waitfunc(mtd, chip);
2388
2389                 /*
2390                  * See if operation failed and additional status checks are
2391                  * available
2392                  */
2393                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2394                         status = chip->errstat(mtd, chip, FL_ERASING,
2395                                                status, page);
2396
2397                 /* See if block erase succeeded */
2398                 if (status & NAND_STATUS_FAIL) {
2399                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2400                                         "page 0x%08x\n", __func__, page);
2401                         instr->state = MTD_ERASE_FAILED;
2402                         instr->fail_addr =
2403                                 ((loff_t)page << chip->page_shift);
2404                         goto erase_exit;
2405                 }
2406
2407                 /*
2408                  * If BBT requires refresh, set the BBT rewrite flag to the
2409                  * page being erased
2410                  */
2411                 if (bbt_masked_page != 0xffffffff &&
2412                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2413                             rewrite_bbt[chipnr] =
2414                                         ((loff_t)page << chip->page_shift);
2415
2416                 /* Increment page address and decrement length */
2417                 len -= (1 << chip->phys_erase_shift);
2418                 page += pages_per_block;
2419
2420                 /* Check, if we cross a chip boundary */
2421                 if (len && !(page & chip->pagemask)) {
2422                         chipnr++;
2423                         chip->select_chip(mtd, -1);
2424                         chip->select_chip(mtd, chipnr);
2425
2426                         /*
2427                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2428                          * page mask to see if this BBT should be rewritten
2429                          */
2430                         if (bbt_masked_page != 0xffffffff &&
2431                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2432                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2433                                         BBT_PAGE_MASK;
2434                 }
2435         }
2436         instr->state = MTD_ERASE_DONE;
2437
2438  erase_exit:
2439
2440         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2441
2442         /* Deselect and wake up anyone waiting on the device */
2443         nand_release_device(mtd);
2444
2445         /* Do call back function */
2446         if (!ret)
2447                 mtd_erase_callback(instr);
2448
2449         /*
2450          * If BBT requires refresh and erase was successful, rewrite any
2451          * selected bad block tables
2452          */
2453         if (bbt_masked_page == 0xffffffff || ret)
2454                 return ret;
2455
2456         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2457                 if (!rewrite_bbt[chipnr])
2458                         continue;
2459                 /* update the BBT for chip */
2460                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2461                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2462                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2463                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2464         }
2465
2466         /* Return more or less happy */
2467         return ret;
2468 }
2469
2470 /**
2471  * nand_sync - [MTD Interface] sync
2472  * @mtd:        MTD device structure
2473  *
2474  * Sync is actually a wait for chip ready function
2475  */
2476 static void nand_sync(struct mtd_info *mtd)
2477 {
2478         struct nand_chip *chip = mtd->priv;
2479
2480         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2481
2482         /* Grab the lock and see if the device is available */
2483         nand_get_device(chip, mtd, FL_SYNCING);
2484         /* Release it and go back */
2485         nand_release_device(mtd);
2486 }
2487
2488 /**
2489  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2490  * @mtd:        MTD device structure
2491  * @offs:       offset relative to mtd start
2492  */
2493 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2494 {
2495         /* Check for invalid offset */
2496         if (offs > mtd->size)
2497                 return -EINVAL;
2498
2499         return nand_block_checkbad(mtd, offs, 1, 0);
2500 }
2501
2502 /**
2503  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2504  * @mtd:        MTD device structure
2505  * @ofs:        offset relative to mtd start
2506  */
2507 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2508 {
2509         struct nand_chip *chip = mtd->priv;
2510         int ret;
2511
2512         if ((ret = nand_block_isbad(mtd, ofs))) {
2513                 /* If it was bad already, return success and do nothing. */
2514                 if (ret > 0)
2515                         return 0;
2516                 return ret;
2517         }
2518
2519         return chip->block_markbad(mtd, ofs);
2520 }
2521
2522 /**
2523  * nand_suspend - [MTD Interface] Suspend the NAND flash
2524  * @mtd:        MTD device structure
2525  */
2526 static int nand_suspend(struct mtd_info *mtd)
2527 {
2528         struct nand_chip *chip = mtd->priv;
2529
2530         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2531 }
2532
2533 /**
2534  * nand_resume - [MTD Interface] Resume the NAND flash
2535  * @mtd:        MTD device structure
2536  */
2537 static void nand_resume(struct mtd_info *mtd)
2538 {
2539         struct nand_chip *chip = mtd->priv;
2540
2541         if (chip->state == FL_PM_SUSPENDED)
2542                 nand_release_device(mtd);
2543         else
2544                 printk(KERN_ERR "%s called for a chip which is not "
2545                        "in suspended state\n", __func__);
2546 }
2547
2548 /*
2549  * Set default functions
2550  */
2551 static void nand_set_defaults(struct nand_chip *chip, int busw)
2552 {
2553         /* check for proper chip_delay setup, set 20us if not */
2554         if (!chip->chip_delay)
2555                 chip->chip_delay = 20;
2556
2557         /* check, if a user supplied command function given */
2558         if (chip->cmdfunc == NULL)
2559                 chip->cmdfunc = nand_command;
2560
2561         /* check, if a user supplied wait function given */
2562         if (chip->waitfunc == NULL)
2563                 chip->waitfunc = nand_wait;
2564
2565         if (!chip->select_chip)
2566                 chip->select_chip = nand_select_chip;
2567         if (!chip->read_byte)
2568                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2569         if (!chip->read_word)
2570                 chip->read_word = nand_read_word;
2571         if (!chip->block_bad)
2572                 chip->block_bad = nand_block_bad;
2573         if (!chip->block_markbad)
2574                 chip->block_markbad = nand_default_block_markbad;
2575         if (!chip->write_buf)
2576                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2577         if (!chip->read_buf)
2578                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2579         if (!chip->verify_buf)
2580                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2581         if (!chip->scan_bbt)
2582                 chip->scan_bbt = nand_default_bbt;
2583
2584         if (!chip->controller) {
2585                 chip->controller = &chip->hwcontrol;
2586                 spin_lock_init(&chip->controller->lock);
2587                 init_waitqueue_head(&chip->controller->wq);
2588         }
2589
2590 }
2591
2592 /*
2593  * Get the flash and manufacturer id and lookup if the type is supported
2594  */
2595 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2596                                                   struct nand_chip *chip,
2597                                                   int busw, int *maf_id)
2598 {
2599         struct nand_flash_dev *type = NULL;
2600         int i, dev_id, maf_idx;
2601         int tmp_id, tmp_manf;
2602
2603         /* Select the device */
2604         chip->select_chip(mtd, 0);
2605
2606         /*
2607          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2608          * after power-up
2609          */
2610         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2611
2612         /* Send the command for reading device ID */
2613         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2614
2615         /* Read manufacturer and device IDs */
2616         *maf_id = chip->read_byte(mtd);
2617         dev_id = chip->read_byte(mtd);
2618
2619         /* Try again to make sure, as some systems the bus-hold or other
2620          * interface concerns can cause random data which looks like a
2621          * possibly credible NAND flash to appear. If the two results do
2622          * not match, ignore the device completely.
2623          */
2624
2625         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2626
2627         /* Read manufacturer and device IDs */
2628
2629         tmp_manf = chip->read_byte(mtd);
2630         tmp_id = chip->read_byte(mtd);
2631
2632         if (tmp_manf != *maf_id || tmp_id != dev_id) {
2633                 printk(KERN_INFO "%s: second ID read did not match "
2634                        "%02x,%02x against %02x,%02x\n", __func__,
2635                        *maf_id, dev_id, tmp_manf, tmp_id);
2636                 return ERR_PTR(-ENODEV);
2637         }
2638
2639         /* Lookup the flash id */
2640         for (i = 0; nand_flash_ids[i].name != NULL; i++) {
2641                 if (dev_id == nand_flash_ids[i].id) {
2642                         type =  &nand_flash_ids[i];
2643                         break;
2644                 }
2645         }
2646
2647         if (!type)
2648                 return ERR_PTR(-ENODEV);
2649
2650         if (!mtd->name)
2651                 mtd->name = type->name;
2652
2653         chip->chipsize = (uint64_t)type->chipsize << 20;
2654
2655         /* Newer devices have all the information in additional id bytes */
2656         if (!type->pagesize) {
2657                 int extid;
2658                 /* The 3rd id byte holds MLC / multichip data */
2659                 chip->cellinfo = chip->read_byte(mtd);
2660                 /* The 4th id byte is the important one */
2661                 extid = chip->read_byte(mtd);
2662                 /* Calc pagesize */
2663                 mtd->writesize = 1024 << (extid & 0x3);
2664                 extid >>= 2;
2665                 /* Calc oobsize */
2666                 mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
2667                 extid >>= 2;
2668                 /* Calc blocksize. Blocksize is multiples of 64KiB */
2669                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2670                 extid >>= 2;
2671                 /* Get buswidth information */
2672                 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2673
2674         } else {
2675                 /*
2676                  * Old devices have chip data hardcoded in the device id table
2677                  */
2678                 mtd->erasesize = type->erasesize;
2679                 mtd->writesize = type->pagesize;
2680                 mtd->oobsize = mtd->writesize / 32;
2681                 busw = type->options & NAND_BUSWIDTH_16;
2682         }
2683
2684         /* Try to identify manufacturer */
2685         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2686                 if (nand_manuf_ids[maf_idx].id == *maf_id)
2687                         break;
2688         }
2689
2690         /*
2691          * Check, if buswidth is correct. Hardware drivers should set
2692          * chip correct !
2693          */
2694         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2695                 printk(KERN_INFO "NAND device: Manufacturer ID:"
2696                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2697                        dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2698                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2699                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2700                        busw ? 16 : 8);
2701                 return ERR_PTR(-EINVAL);
2702         }
2703
2704         /* Calculate the address shift from the page size */
2705         chip->page_shift = ffs(mtd->writesize) - 1;
2706         /* Convert chipsize to number of pages per chip -1. */
2707         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2708
2709         chip->bbt_erase_shift = chip->phys_erase_shift =
2710                 ffs(mtd->erasesize) - 1;
2711         if (chip->chipsize & 0xffffffff)
2712                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2713         else
2714                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2715
2716         /* Set the bad block position */
2717         chip->badblockpos = mtd->writesize > 512 ?
2718                 NAND_LARGE_BADBLOCK_POS : NAND_SMALL_BADBLOCK_POS;
2719
2720         /* Get chip options, preserve non chip based options */
2721         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2722         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2723
2724         /*
2725          * Set chip as a default. Board drivers can override it, if necessary
2726          */
2727         chip->options |= NAND_NO_AUTOINCR;
2728
2729         /* Check if chip is a not a samsung device. Do not clear the
2730          * options for chips which are not having an extended id.
2731          */
2732         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2733                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2734
2735         /* Check for AND chips with 4 page planes */
2736         if (chip->options & NAND_4PAGE_ARRAY)
2737                 chip->erase_cmd = multi_erase_cmd;
2738         else
2739                 chip->erase_cmd = single_erase_cmd;
2740
2741         /* Do not replace user supplied command function ! */
2742         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
2743                 chip->cmdfunc = nand_command_lp;
2744
2745         printk(KERN_INFO "NAND device: Manufacturer ID:"
2746                " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
2747                nand_manuf_ids[maf_idx].name, type->name);
2748
2749         return type;
2750 }
2751
2752 /**
2753  * nand_scan_ident - [NAND Interface] Scan for the NAND device
2754  * @mtd:             MTD device structure
2755  * @maxchips:        Number of chips to scan for
2756  *
2757  * This is the first phase of the normal nand_scan() function. It
2758  * reads the flash ID and sets up MTD fields accordingly.
2759  *
2760  * The mtd->owner field must be set to the module of the caller.
2761  */
2762 int nand_scan_ident(struct mtd_info *mtd, int maxchips)
2763 {
2764         int i, busw, nand_maf_id;
2765         struct nand_chip *chip = mtd->priv;
2766         struct nand_flash_dev *type;
2767
2768         /* Get buswidth to select the correct functions */
2769         busw = chip->options & NAND_BUSWIDTH_16;
2770         /* Set the default functions */
2771         nand_set_defaults(chip, busw);
2772
2773         /* Read the flash type */
2774         type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
2775
2776         if (IS_ERR(type)) {
2777                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
2778                         printk(KERN_WARNING "No NAND device found.\n");
2779                 chip->select_chip(mtd, -1);
2780                 return PTR_ERR(type);
2781         }
2782
2783         /* Check for a chip array */
2784         for (i = 1; i < maxchips; i++) {
2785                 chip->select_chip(mtd, i);
2786                 /* See comment in nand_get_flash_type for reset */
2787                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2788                 /* Send the command for reading device ID */
2789                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2790                 /* Read manufacturer and device IDs */
2791                 if (nand_maf_id != chip->read_byte(mtd) ||
2792                     type->id != chip->read_byte(mtd))
2793                         break;
2794         }
2795         if (i > 1)
2796                 printk(KERN_INFO "%d NAND chips detected\n", i);
2797
2798         /* Store the number of chips and calc total size for mtd */
2799         chip->numchips = i;
2800         mtd->size = i * chip->chipsize;
2801
2802         return 0;
2803 }
2804
2805
2806 /**
2807  * nand_scan_tail - [NAND Interface] Scan for the NAND device
2808  * @mtd:            MTD device structure
2809  *
2810  * This is the second phase of the normal nand_scan() function. It
2811  * fills out all the uninitialized function pointers with the defaults
2812  * and scans for a bad block table if appropriate.
2813  */
2814 int nand_scan_tail(struct mtd_info *mtd)
2815 {
2816         int i;
2817         struct nand_chip *chip = mtd->priv;
2818
2819         if (!(chip->options & NAND_OWN_BUFFERS))
2820                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
2821         if (!chip->buffers)
2822                 return -ENOMEM;
2823
2824         /* Set the internal oob buffer location, just after the page data */
2825         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
2826
2827         /*
2828          * If no default placement scheme is given, select an appropriate one
2829          */
2830         if (!chip->ecc.layout) {
2831                 switch (mtd->oobsize) {
2832                 case 8:
2833                         chip->ecc.layout = &nand_oob_8;
2834                         break;
2835                 case 16:
2836                         chip->ecc.layout = &nand_oob_16;
2837                         break;
2838                 case 64:
2839                         chip->ecc.layout = &nand_oob_64;
2840                         break;
2841                 case 128:
2842                         chip->ecc.layout = &nand_oob_128;
2843                         break;
2844                 default:
2845                         printk(KERN_WARNING "No oob scheme defined for "
2846                                "oobsize %d\n", mtd->oobsize);
2847                         BUG();
2848                 }
2849         }
2850
2851         if (!chip->write_page)
2852                 chip->write_page = nand_write_page;
2853
2854         /*
2855          * check ECC mode, default to software if 3byte/512byte hardware ECC is
2856          * selected and we have 256 byte pagesize fallback to software ECC
2857          */
2858
2859         switch (chip->ecc.mode) {
2860         case NAND_ECC_HW_OOB_FIRST:
2861                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
2862                 if (!chip->ecc.calculate || !chip->ecc.correct ||
2863                      !chip->ecc.hwctl) {
2864                         printk(KERN_WARNING "No ECC functions supplied; "
2865                                "Hardware ECC not possible\n");
2866                         BUG();
2867                 }
2868                 if (!chip->ecc.read_page)
2869                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
2870
2871         case NAND_ECC_HW:
2872                 /* Use standard hwecc read page function ? */
2873                 if (!chip->ecc.read_page)
2874                         chip->ecc.read_page = nand_read_page_hwecc;
2875                 if (!chip->ecc.write_page)
2876                         chip->ecc.write_page = nand_write_page_hwecc;
2877                 if (!chip->ecc.read_page_raw)
2878                         chip->ecc.read_page_raw = nand_read_page_raw;
2879                 if (!chip->ecc.write_page_raw)
2880                         chip->ecc.write_page_raw = nand_write_page_raw;
2881                 if (!chip->ecc.read_oob)
2882                         chip->ecc.read_oob = nand_read_oob_std;
2883                 if (!chip->ecc.write_oob)
2884                         chip->ecc.write_oob = nand_write_oob_std;
2885
2886         case NAND_ECC_HW_SYNDROME:
2887                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
2888                      !chip->ecc.hwctl) &&
2889                     (!chip->ecc.read_page ||
2890                      chip->ecc.read_page == nand_read_page_hwecc ||
2891                      !chip->ecc.write_page ||
2892                      chip->ecc.write_page == nand_write_page_hwecc)) {
2893                         printk(KERN_WARNING "No ECC functions supplied; "
2894                                "Hardware ECC not possible\n");
2895                         BUG();
2896                 }
2897                 /* Use standard syndrome read/write page function ? */
2898                 if (!chip->ecc.read_page)
2899                         chip->ecc.read_page = nand_read_page_syndrome;
2900                 if (!chip->ecc.write_page)
2901                         chip->ecc.write_page = nand_write_page_syndrome;
2902                 if (!chip->ecc.read_page_raw)
2903                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
2904                 if (!chip->ecc.write_page_raw)
2905                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
2906                 if (!chip->ecc.read_oob)
2907                         chip->ecc.read_oob = nand_read_oob_syndrome;
2908                 if (!chip->ecc.write_oob)
2909                         chip->ecc.write_oob = nand_write_oob_syndrome;
2910
2911                 if (mtd->writesize >= chip->ecc.size)
2912                         break;
2913                 printk(KERN_WARNING "%d byte HW ECC not possible on "
2914                        "%d byte page size, fallback to SW ECC\n",
2915                        chip->ecc.size, mtd->writesize);
2916                 chip->ecc.mode = NAND_ECC_SOFT;
2917
2918         case NAND_ECC_SOFT:
2919                 chip->ecc.calculate = nand_calculate_ecc;
2920                 chip->ecc.correct = nand_correct_data;
2921                 chip->ecc.read_page = nand_read_page_swecc;
2922                 chip->ecc.read_subpage = nand_read_subpage;
2923                 chip->ecc.write_page = nand_write_page_swecc;
2924                 chip->ecc.read_page_raw = nand_read_page_raw;
2925                 chip->ecc.write_page_raw = nand_write_page_raw;
2926                 chip->ecc.read_oob = nand_read_oob_std;
2927                 chip->ecc.write_oob = nand_write_oob_std;
2928                 if (!chip->ecc.size)
2929                         chip->ecc.size = 256;
2930                 chip->ecc.bytes = 3;
2931                 break;
2932
2933         case NAND_ECC_NONE:
2934                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
2935                        "This is not recommended !!\n");
2936                 chip->ecc.read_page = nand_read_page_raw;
2937                 chip->ecc.write_page = nand_write_page_raw;
2938                 chip->ecc.read_oob = nand_read_oob_std;
2939                 chip->ecc.read_page_raw = nand_read_page_raw;
2940                 chip->ecc.write_page_raw = nand_write_page_raw;
2941                 chip->ecc.write_oob = nand_write_oob_std;
2942                 chip->ecc.size = mtd->writesize;
2943                 chip->ecc.bytes = 0;
2944                 break;
2945
2946         default:
2947                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
2948                        chip->ecc.mode);
2949                 BUG();
2950         }
2951
2952         /*
2953          * The number of bytes available for a client to place data into
2954          * the out of band area
2955          */
2956         chip->ecc.layout->oobavail = 0;
2957         for (i = 0; chip->ecc.layout->oobfree[i].length
2958                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
2959                 chip->ecc.layout->oobavail +=
2960                         chip->ecc.layout->oobfree[i].length;
2961         mtd->oobavail = chip->ecc.layout->oobavail;
2962
2963         /*
2964          * Set the number of read / write steps for one page depending on ECC
2965          * mode
2966          */
2967         chip->ecc.steps = mtd->writesize / chip->ecc.size;
2968         if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
2969                 printk(KERN_WARNING "Invalid ecc parameters\n");
2970                 BUG();
2971         }
2972         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
2973
2974         /*
2975          * Allow subpage writes up to ecc.steps. Not possible for MLC
2976          * FLASH.
2977          */
2978         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
2979             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
2980                 switch(chip->ecc.steps) {
2981                 case 2:
2982                         mtd->subpage_sft = 1;
2983                         break;
2984                 case 4:
2985                 case 8:
2986                 case 16:
2987                         mtd->subpage_sft = 2;
2988                         break;
2989                 }
2990         }
2991         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
2992
2993         /* Initialize state */
2994         chip->state = FL_READY;
2995
2996         /* De-select the device */
2997         chip->select_chip(mtd, -1);
2998
2999         /* Invalidate the pagebuffer reference */
3000         chip->pagebuf = -1;
3001
3002         /* Fill in remaining MTD driver data */
3003         mtd->type = MTD_NANDFLASH;
3004         mtd->flags = MTD_CAP_NANDFLASH;
3005         mtd->erase = nand_erase;
3006         mtd->point = NULL;
3007         mtd->unpoint = NULL;
3008         mtd->read = nand_read;
3009         mtd->write = nand_write;
3010         mtd->panic_write = panic_nand_write;
3011         mtd->read_oob = nand_read_oob;
3012         mtd->write_oob = nand_write_oob;
3013         mtd->sync = nand_sync;
3014         mtd->lock = NULL;
3015         mtd->unlock = NULL;
3016         mtd->suspend = nand_suspend;
3017         mtd->resume = nand_resume;
3018         mtd->block_isbad = nand_block_isbad;
3019         mtd->block_markbad = nand_block_markbad;
3020
3021         /* propagate ecc.layout to mtd_info */
3022         mtd->ecclayout = chip->ecc.layout;
3023
3024         /* Check, if we should skip the bad block table scan */
3025         if (chip->options & NAND_SKIP_BBTSCAN)
3026                 return 0;
3027
3028         /* Build bad block table */
3029         return chip->scan_bbt(mtd);
3030 }
3031
3032 /* is_module_text_address() isn't exported, and it's mostly a pointless
3033    test if this is a module _anyway_ -- they'd have to try _really_ hard
3034    to call us from in-kernel code if the core NAND support is modular. */
3035 #ifdef MODULE
3036 #define caller_is_module() (1)
3037 #else
3038 #define caller_is_module() \
3039         is_module_text_address((unsigned long)__builtin_return_address(0))
3040 #endif
3041
3042 /**
3043  * nand_scan - [NAND Interface] Scan for the NAND device
3044  * @mtd:        MTD device structure
3045  * @maxchips:   Number of chips to scan for
3046  *
3047  * This fills out all the uninitialized function pointers
3048  * with the defaults.
3049  * The flash ID is read and the mtd/chip structures are
3050  * filled with the appropriate values.
3051  * The mtd->owner field must be set to the module of the caller
3052  *
3053  */
3054 int nand_scan(struct mtd_info *mtd, int maxchips)
3055 {
3056         int ret;
3057
3058         /* Many callers got this wrong, so check for it for a while... */
3059         if (!mtd->owner && caller_is_module()) {
3060                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3061                                 __func__);
3062                 BUG();
3063         }
3064
3065         ret = nand_scan_ident(mtd, maxchips);
3066         if (!ret)
3067                 ret = nand_scan_tail(mtd);
3068         return ret;
3069 }
3070
3071 /**
3072  * nand_release - [NAND Interface] Free resources held by the NAND device
3073  * @mtd:        MTD device structure
3074 */
3075 void nand_release(struct mtd_info *mtd)
3076 {
3077         struct nand_chip *chip = mtd->priv;
3078
3079 #ifdef CONFIG_MTD_PARTITIONS
3080         /* Deregister partitions */
3081         del_mtd_partitions(mtd);
3082 #endif
3083         /* Deregister the device */
3084         del_mtd_device(mtd);
3085
3086         /* Free bad block table memory */
3087         kfree(chip->bbt);
3088         if (!(chip->options & NAND_OWN_BUFFERS))
3089                 kfree(chip->buffers);
3090 }
3091
3092 EXPORT_SYMBOL_GPL(nand_scan);
3093 EXPORT_SYMBOL_GPL(nand_scan_ident);
3094 EXPORT_SYMBOL_GPL(nand_scan_tail);
3095 EXPORT_SYMBOL_GPL(nand_release);
3096
3097 static int __init nand_base_init(void)
3098 {
3099         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3100         return 0;
3101 }
3102
3103 static void __exit nand_base_exit(void)
3104 {
3105         led_trigger_unregister_simple(nand_led_trigger);
3106 }
3107
3108 module_init(nand_base_init);
3109 module_exit(nand_base_exit);
3110
3111 MODULE_LICENSE("GPL");
3112 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3113 MODULE_DESCRIPTION("Generic NAND flash driver code");