drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ecc support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 /* Define default oob placement schemes for large and small page devices */
  53 static struct nand_ecclayout nand_oob_8 = {
  54         .eccbytes = 3,
  55         .eccpos = {0, 1, 2},
  56         .oobfree = {
  57                 {.offset = 3,
  58                  .length = 2},
  59                 {.offset = 6,
  60                  .length = 2} }
  61 };
  62
  63 static struct nand_ecclayout nand_oob_16 = {
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {
  67                 {.offset = 8,
  68                  . length = 8} }
  69 };
  70
  71 static struct nand_ecclayout nand_oob_64 = {
  72         .eccbytes = 24,
  73         .eccpos = {
  74                    40, 41, 42, 43, 44, 45, 46, 47,
  75                    48, 49, 50, 51, 52, 53, 54, 55,
  76                    56, 57, 58, 59, 60, 61, 62, 63},
  77         .oobfree = {
  78                 {.offset = 2,
  79                  .length = 38} }
  80 };
  81
  82 static struct nand_ecclayout nand_oob_128 = {
  83         .eccbytes = 48,
  84         .eccpos = {
  85                    80, 81, 82, 83, 84, 85, 86, 87,
  86                    88, 89, 90, 91, 92, 93, 94, 95,
  87                    96, 97, 98, 99, 100, 101, 102, 103,
  88                    104, 105, 106, 107, 108, 109, 110, 111,
  89                    112, 113, 114, 115, 116, 117, 118, 119,
  90                    120, 121, 122, 123, 124, 125, 126, 127},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 78} }
  94 };
  95
  96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  97                            int new_state);
  98
  99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 100                              struct mtd_oob_ops *ops);
 101
 102 /*
 103  * For devices which display every fart in the system on a separate LED. Is
 104  * compiled away when LED support is disabled.
 105  */
 106 DEFINE_LED_TRIGGER(nand_led_trigger);
 107
 108 static int check_offs_len(struct mtd_info *mtd,
 109                                         loff_t ofs, uint64_t len)
 110 {
 111         struct nand_chip *chip = mtd->priv;
 112         int ret = 0;
 113
 114         /* Start address must align on block boundary */
 115         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 116                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 117                 ret = -EINVAL;
 118         }
 119
 120         /* Length must align on block boundary */
 121         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 122                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 123                                         __func__);
 124                 ret = -EINVAL;
 125         }
 126
 127         /* Do not allow past end of device */
 128         if (ofs + len > mtd->size) {
 129                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
 130                                         __func__);
 131                 ret = -EINVAL;
 132         }
 133
 134         return ret;
 135 }
 136
 137 /**
 138  * nand_release_device - [GENERIC] release chip
 139  * @mtd:        MTD device structure
 140  *
 141  * Deselect, release chip lock and wake up anyone waiting on the device
 142  */
 143 static void nand_release_device(struct mtd_info *mtd)
 144 {
 145         struct nand_chip *chip = mtd->priv;
 146
 147         /* De-select the NAND device */
 148         chip->select_chip(mtd, -1);
 149
 150         /* Release the controller and the chip */
 151         spin_lock(&chip->controller->lock);
 152         chip->controller->active = NULL;
 153         chip->state = FL_READY;
 154         wake_up(&chip->controller->wq);
 155         spin_unlock(&chip->controller->lock);
 156 }
 157
 158 /**
 159  * nand_read_byte - [DEFAULT] read one byte from the chip
 160  * @mtd:        MTD device structure
 161  *
 162  * Default read function for 8bit buswith
 163  */
 164 static uint8_t nand_read_byte(struct mtd_info *mtd)
 165 {
 166         struct nand_chip *chip = mtd->priv;
 167         return readb(chip->IO_ADDR_R);
 168 }
 169
 170 /**
 171  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 172  * @mtd:        MTD device structure
 173  *
 174  * Default read function for 16bit buswith with
 175  * endianess conversion
 176  */
 177 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 178 {
 179         struct nand_chip *chip = mtd->priv;
 180         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 181 }
 182
 183 /**
 184  * nand_read_word - [DEFAULT] read one word from the chip
 185  * @mtd:        MTD device structure
 186  *
 187  * Default read function for 16bit buswith without
 188  * endianess conversion
 189  */
 190 static u16 nand_read_word(struct mtd_info *mtd)
 191 {
 192         struct nand_chip *chip = mtd->priv;
 193         return readw(chip->IO_ADDR_R);
 194 }
 195
 196 /**
 197  * nand_select_chip - [DEFAULT] control CE line
 198  * @mtd:        MTD device structure
 199  * @chipnr:     chipnumber to select, -1 for deselect
 200  *
 201  * Default select function for 1 chip devices.
 202  */
 203 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 204 {
 205         struct nand_chip *chip = mtd->priv;
 206
 207         switch (chipnr) {
 208         case -1:
 209                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 210                 break;
 211         case 0:
 212                 break;
 213
 214         default:
 215                 BUG();
 216         }
 217 }
 218
 219 /**
 220  * nand_write_buf - [DEFAULT] write buffer to chip
 221  * @mtd:        MTD device structure
 222  * @buf:        data buffer
 223  * @len:        number of bytes to write
 224  *
 225  * Default write function for 8bit buswith
 226  */
 227 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 228 {
 229         int i;
 230         struct nand_chip *chip = mtd->priv;
 231
 232         for (i = 0; i < len; i++)
 233                 writeb(buf[i], chip->IO_ADDR_W);
 234 }
 235
 236 /**
 237  * nand_read_buf - [DEFAULT] read chip data into buffer
 238  * @mtd:        MTD device structure
 239  * @buf:        buffer to store date
 240  * @len:        number of bytes to read
 241  *
 242  * Default read function for 8bit buswith
 243  */
 244 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 245 {
 246         int i;
 247         struct nand_chip *chip = mtd->priv;
 248
 249         for (i = 0; i < len; i++)
 250                 buf[i] = readb(chip->IO_ADDR_R);
 251 }
 252
 253 /**
 254  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 255  * @mtd:        MTD device structure
 256  * @buf:        buffer containing the data to compare
 257  * @len:        number of bytes to compare
 258  *
 259  * Default verify function for 8bit buswith
 260  */
 261 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 262 {
 263         int i;
 264         struct nand_chip *chip = mtd->priv;
 265
 266         for (i = 0; i < len; i++)
 267                 if (buf[i] != readb(chip->IO_ADDR_R))
 268                         return -EFAULT;
 269         return 0;
 270 }
 271
 272 /**
 273  * nand_write_buf16 - [DEFAULT] write buffer to chip
 274  * @mtd:        MTD device structure
 275  * @buf:        data buffer
 276  * @len:        number of bytes to write
 277  *
 278  * Default write function for 16bit buswith
 279  */
 280 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 281 {
 282         int i;
 283         struct nand_chip *chip = mtd->priv;
 284         u16 *p = (u16 *) buf;
 285         len >>= 1;
 286
 287         for (i = 0; i < len; i++)
 288                 writew(p[i], chip->IO_ADDR_W);
 289
 290 }
 291
 292 /**
 293  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 294  * @mtd:        MTD device structure
 295  * @buf:        buffer to store date
 296  * @len:        number of bytes to read
 297  *
 298  * Default read function for 16bit buswith
 299  */
 300 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 301 {
 302         int i;
 303         struct nand_chip *chip = mtd->priv;
 304         u16 *p = (u16 *) buf;
 305         len >>= 1;
 306
 307         for (i = 0; i < len; i++)
 308                 p[i] = readw(chip->IO_ADDR_R);
 309 }
 310
 311 /**
 312  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 313  * @mtd:        MTD device structure
 314  * @buf:        buffer containing the data to compare
 315  * @len:        number of bytes to compare
 316  *
 317  * Default verify function for 16bit buswith
 318  */
 319 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 320 {
 321         int i;
 322         struct nand_chip *chip = mtd->priv;
 323         u16 *p = (u16 *) buf;
 324         len >>= 1;
 325
 326         for (i = 0; i < len; i++)
 327                 if (p[i] != readw(chip->IO_ADDR_R))
 328                         return -EFAULT;
 329
 330         return 0;
 331 }
 332
 333 /**
 334  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 335  * @mtd:        MTD device structure
 336  * @ofs:        offset from device start
 337  * @getchip:    0, if the chip is already selected
 338  *
 339  * Check, if the block is bad.
 340  */
 341 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 342 {
 343         int page, chipnr, res = 0;
 344         struct nand_chip *chip = mtd->priv;
 345         u16 bad;
 346
 347         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 348                 ofs += mtd->erasesize - mtd->writesize;
 349
 350         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 351
 352         if (getchip) {
 353                 chipnr = (int)(ofs >> chip->chip_shift);
 354
 355                 nand_get_device(chip, mtd, FL_READING);
 356
 357                 /* Select the NAND device */
 358                 chip->select_chip(mtd, chipnr);
 359         }
 360
 361         if (chip->options & NAND_BUSWIDTH_16) {
 362                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 363                               page);
 364                 bad = cpu_to_le16(chip->read_word(mtd));
 365                 if (chip->badblockpos & 0x1)
 366                         bad >>= 8;
 367                 else
 368                         bad &= 0xFF;
 369         } else {
 370                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 371                 bad = chip->read_byte(mtd);
 372         }
 373
 374         if (likely(chip->badblockbits == 8))
 375                 res = bad != 0xFF;
 376         else
 377                 res = hweight8(bad) < chip->badblockbits;
 378
 379         if (getchip)
 380                 nand_release_device(mtd);
 381
 382         return res;
 383 }
 384
 385 /**
 386  * nand_default_block_markbad - [DEFAULT] mark a block bad
 387  * @mtd:        MTD device structure
 388  * @ofs:        offset from device start
 389  *
 390  * This is the default implementation, which can be overridden by
 391  * a hardware specific driver.
 392 */
 393 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 394 {
 395         struct nand_chip *chip = mtd->priv;
 396         uint8_t buf[2] = { 0, 0 };
 397         int block, ret, i = 0;
 398
 399         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 400                 ofs += mtd->erasesize - mtd->writesize;
 401
 402         /* Get block number */
 403         block = (int)(ofs >> chip->bbt_erase_shift);
 404         if (chip->bbt)
 405                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 406
 407         /* Do we have a flash based bad block table ? */
 408         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 409                 ret = nand_update_bbt(mtd, ofs);
 410         else {
 411                 nand_get_device(chip, mtd, FL_WRITING);
 412
 413                 /*
 414                  * Write to first two pages if necessary. If we write to more
 415                  * than one location, the first error encountered quits the
 416                  * procedure. We write two bytes per location, so we dont have
 417                  * to mess with 16 bit access.
 418                  */
 419                 do {
 420                         chip->ops.len = chip->ops.ooblen = 2;
 421                         chip->ops.datbuf = NULL;
 422                         chip->ops.oobbuf = buf;
 423                         chip->ops.ooboffs = chip->badblockpos & ~0x01;
 424
 425                         ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 426
 427                         i++;
 428                         ofs += mtd->writesize;
 429                 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
 430                                 i < 2);
 431
 432                 nand_release_device(mtd);
 433         }
 434         if (!ret)
 435                 mtd->ecc_stats.badblocks++;
 436
 437         return ret;
 438 }
 439
 440 /**
 441  * nand_check_wp - [GENERIC] check if the chip is write protected
 442  * @mtd:        MTD device structure
 443  * Check, if the device is write protected
 444  *
 445  * The function expects, that the device is already selected
 446  */
 447 static int nand_check_wp(struct mtd_info *mtd)
 448 {
 449         struct nand_chip *chip = mtd->priv;
 450
 451         /* broken xD cards report WP despite being writable */
 452         if (chip->options & NAND_BROKEN_XD)
 453                 return 0;
 454
 455         /* Check the WP bit */
 456         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 457         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 458 }
 459
 460 /**
 461  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 462  * @mtd:        MTD device structure
 463  * @ofs:        offset from device start
 464  * @getchip:    0, if the chip is already selected
 465  * @allowbbt:   1, if its allowed to access the bbt area
 466  *
 467  * Check, if the block is bad. Either by reading the bad block table or
 468  * calling of the scan function.
 469  */
 470 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 471                                int allowbbt)
 472 {
 473         struct nand_chip *chip = mtd->priv;
 474
 475         if (!chip->bbt)
 476                 return chip->block_bad(mtd, ofs, getchip);
 477
 478         /* Return info from the table */
 479         return nand_isbad_bbt(mtd, ofs, allowbbt);
 480 }
 481
 482 /**
 483  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 484  * @mtd:        MTD device structure
 485  * @timeo:      Timeout
 486  *
 487  * Helper function for nand_wait_ready used when needing to wait in interrupt
 488  * context.
 489  */
 490 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 491 {
 492         struct nand_chip *chip = mtd->priv;
 493         int i;
 494
 495         /* Wait for the device to get ready */
 496         for (i = 0; i < timeo; i++) {
 497                 if (chip->dev_ready(mtd))
 498                         break;
 499                 touch_softlockup_watchdog();
 500                 mdelay(1);
 501         }
 502 }
 503
 504 /*
 505  * Wait for the ready pin, after a command
 506  * The timeout is catched later.
 507  */
 508 void nand_wait_ready(struct mtd_info *mtd)
 509 {
 510         struct nand_chip *chip = mtd->priv;
 511         unsigned long timeo = jiffies + 2;
 512
 513         /* 400ms timeout */
 514         if (in_interrupt() || oops_in_progress)
 515                 return panic_nand_wait_ready(mtd, 400);
 516
 517         led_trigger_event(nand_led_trigger, LED_FULL);
 518         /* wait until command is processed or timeout occures */
 519         do {
 520                 if (chip->dev_ready(mtd))
 521                         break;
 522                 touch_softlockup_watchdog();
 523         } while (time_before(jiffies, timeo));
 524         led_trigger_event(nand_led_trigger, LED_OFF);
 525 }
 526 EXPORT_SYMBOL_GPL(nand_wait_ready);
 527
 528 /**
 529  * nand_command - [DEFAULT] Send command to NAND device
 530  * @mtd:        MTD device structure
 531  * @command:    the command to be sent
 532  * @column:     the column address for this command, -1 if none
 533  * @page_addr:  the page address for this command, -1 if none
 534  *
 535  * Send command to NAND device. This function is used for small page
 536  * devices (256/512 Bytes per page)
 537  */
 538 static void nand_command(struct mtd_info *mtd, unsigned int command,
 539                          int column, int page_addr)
 540 {
 541         register struct nand_chip *chip = mtd->priv;
 542         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 543
 544         /*
 545          * Write out the command to the device.
 546          */
 547         if (command == NAND_CMD_SEQIN) {
 548                 int readcmd;
 549
 550                 if (column >= mtd->writesize) {
 551                         /* OOB area */
 552                         column -= mtd->writesize;
 553                         readcmd = NAND_CMD_READOOB;
 554                 } else if (column < 256) {
 555                         /* First 256 bytes --> READ0 */
 556                         readcmd = NAND_CMD_READ0;
 557                 } else {
 558                         column -= 256;
 559                         readcmd = NAND_CMD_READ1;
 560                 }
 561                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 562                 ctrl &= ~NAND_CTRL_CHANGE;
 563         }
 564         chip->cmd_ctrl(mtd, command, ctrl);
 565
 566         /*
 567          * Address cycle, when necessary
 568          */
 569         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 570         /* Serially input address */
 571         if (column != -1) {
 572                 /* Adjust columns for 16 bit buswidth */
 573                 if (chip->options & NAND_BUSWIDTH_16)
 574                         column >>= 1;
 575                 chip->cmd_ctrl(mtd, column, ctrl);
 576                 ctrl &= ~NAND_CTRL_CHANGE;
 577         }
 578         if (page_addr != -1) {
 579                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 580                 ctrl &= ~NAND_CTRL_CHANGE;
 581                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 582                 /* One more address cycle for devices > 32MiB */
 583                 if (chip->chipsize > (32 << 20))
 584                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 585         }
 586         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 587
 588         /*
 589          * program and erase have their own busy handlers
 590          * status and sequential in needs no delay
 591          */
 592         switch (command) {
 593
 594         case NAND_CMD_PAGEPROG:
 595         case NAND_CMD_ERASE1:
 596         case NAND_CMD_ERASE2:
 597         case NAND_CMD_SEQIN:
 598         case NAND_CMD_STATUS:
 599                 return;
 600
 601         case NAND_CMD_RESET:
 602                 if (chip->dev_ready)
 603                         break;
 604                 udelay(chip->chip_delay);
 605                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 606                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 607                 chip->cmd_ctrl(mtd,
 608                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 609                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 610                                 ;
 611                 return;
 612
 613                 /* This applies to read commands */
 614         default:
 615                 /*
 616                  * If we don't have access to the busy pin, we apply the given
 617                  * command delay
 618                  */
 619                 if (!chip->dev_ready) {
 620                         udelay(chip->chip_delay);
 621                         return;
 622                 }
 623         }
 624         /* Apply this short delay always to ensure that we do wait tWB in
 625          * any case on any machine. */
 626         ndelay(100);
 627
 628         nand_wait_ready(mtd);
 629 }
 630
 631 /**
 632  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 633  * @mtd:        MTD device structure
 634  * @command:    the command to be sent
 635  * @column:     the column address for this command, -1 if none
 636  * @page_addr:  the page address for this command, -1 if none
 637  *
 638  * Send command to NAND device. This is the version for the new large page
 639  * devices We dont have the separate regions as we have in the small page
 640  * devices.  We must emulate NAND_CMD_READOOB to keep the code compatible.
 641  */
 642 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 643                             int column, int page_addr)
 644 {
 645         register struct nand_chip *chip = mtd->priv;
 646
 647         /* Emulate NAND_CMD_READOOB */
 648         if (command == NAND_CMD_READOOB) {
 649                 column += mtd->writesize;
 650                 command = NAND_CMD_READ0;
 651         }
 652
 653         /* Command latch cycle */
 654         chip->cmd_ctrl(mtd, command & 0xff,
 655                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 656
 657         if (column != -1 || page_addr != -1) {
 658                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 659
 660                 /* Serially input address */
 661                 if (column != -1) {
 662                         /* Adjust columns for 16 bit buswidth */
 663                         if (chip->options & NAND_BUSWIDTH_16)
 664                                 column >>= 1;
 665                         chip->cmd_ctrl(mtd, column, ctrl);
 666                         ctrl &= ~NAND_CTRL_CHANGE;
 667                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 668                 }
 669                 if (page_addr != -1) {
 670                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 671                         chip->cmd_ctrl(mtd, page_addr >> 8,
 672                                        NAND_NCE | NAND_ALE);
 673                         /* One more address cycle for devices > 128MiB */
 674                         if (chip->chipsize > (128 << 20))
 675                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 676                                                NAND_NCE | NAND_ALE);
 677                 }
 678         }
 679         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 680
 681         /*
 682          * program and erase have their own busy handlers
 683          * status, sequential in, and deplete1 need no delay
 684          */
 685         switch (command) {
 686
 687         case NAND_CMD_CACHEDPROG:
 688         case NAND_CMD_PAGEPROG:
 689         case NAND_CMD_ERASE1:
 690         case NAND_CMD_ERASE2:
 691         case NAND_CMD_SEQIN:
 692         case NAND_CMD_RNDIN:
 693         case NAND_CMD_STATUS:
 694         case NAND_CMD_DEPLETE1:
 695                 return;
 696
 697                 /*
 698                  * read error status commands require only a short delay
 699                  */
 700         case NAND_CMD_STATUS_ERROR:
 701         case NAND_CMD_STATUS_ERROR0:
 702         case NAND_CMD_STATUS_ERROR1:
 703         case NAND_CMD_STATUS_ERROR2:
 704         case NAND_CMD_STATUS_ERROR3:
 705                 udelay(chip->chip_delay);
 706                 return;
 707
 708         case NAND_CMD_RESET:
 709                 if (chip->dev_ready)
 710                         break;
 711                 udelay(chip->chip_delay);
 712                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 713                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 714                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 715                                NAND_NCE | NAND_CTRL_CHANGE);
 716                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 717                                 ;
 718                 return;
 719
 720         case NAND_CMD_RNDOUT:
 721                 /* No ready / busy check necessary */
 722                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 723                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 724                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 725                                NAND_NCE | NAND_CTRL_CHANGE);
 726                 return;
 727
 728         case NAND_CMD_READ0:
 729                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 730                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 731                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 732                                NAND_NCE | NAND_CTRL_CHANGE);
 733
 734                 /* This applies to read commands */
 735         default:
 736                 /*
 737                  * If we don't have access to the busy pin, we apply the given
 738                  * command delay
 739                  */
 740                 if (!chip->dev_ready) {
 741                         udelay(chip->chip_delay);
 742                         return;
 743                 }
 744         }
 745
 746         /* Apply this short delay always to ensure that we do wait tWB in
 747          * any case on any machine. */
 748         ndelay(100);
 749
 750         nand_wait_ready(mtd);
 751 }
 752
 753 /**
 754  * panic_nand_get_device - [GENERIC] Get chip for selected access
 755  * @chip:       the nand chip descriptor
 756  * @mtd:        MTD device structure
 757  * @new_state:  the state which is requested
 758  *
 759  * Used when in panic, no locks are taken.
 760  */
 761 static void panic_nand_get_device(struct nand_chip *chip,
 762                       struct mtd_info *mtd, int new_state)
 763 {
 764         /* Hardware controller shared among independend devices */
 765         chip->controller->active = chip;
 766         chip->state = new_state;
 767 }
 768
 769 /**
 770  * nand_get_device - [GENERIC] Get chip for selected access
 771  * @chip:       the nand chip descriptor
 772  * @mtd:        MTD device structure
 773  * @new_state:  the state which is requested
 774  *
 775  * Get the device and lock it for exclusive access
 776  */
 777 static int
 778 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 779 {
 780         spinlock_t *lock = &chip->controller->lock;
 781         wait_queue_head_t *wq = &chip->controller->wq;
 782         DECLARE_WAITQUEUE(wait, current);
 783 retry:
 784         spin_lock(lock);
 785
 786         /* Hardware controller shared among independent devices */
 787         if (!chip->controller->active)
 788                 chip->controller->active = chip;
 789
 790         if (chip->controller->active == chip && chip->state == FL_READY) {
 791                 chip->state = new_state;
 792                 spin_unlock(lock);
 793                 return 0;
 794         }
 795         if (new_state == FL_PM_SUSPENDED) {
 796                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 797                         chip->state = FL_PM_SUSPENDED;
 798                         spin_unlock(lock);
 799                         return 0;
 800                 }
 801         }
 802         set_current_state(TASK_UNINTERRUPTIBLE);
 803         add_wait_queue(wq, &wait);
 804         spin_unlock(lock);
 805         schedule();
 806         remove_wait_queue(wq, &wait);
 807         goto retry;
 808 }
 809
 810 /**
 811  * panic_nand_wait - [GENERIC]  wait until the command is done
 812  * @mtd:        MTD device structure
 813  * @chip:       NAND chip structure
 814  * @timeo:      Timeout
 815  *
 816  * Wait for command done. This is a helper function for nand_wait used when
 817  * we are in interrupt context. May happen when in panic and trying to write
 818  * an oops through mtdoops.
 819  */
 820 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 821                             unsigned long timeo)
 822 {
 823         int i;
 824         for (i = 0; i < timeo; i++) {
 825                 if (chip->dev_ready) {
 826                         if (chip->dev_ready(mtd))
 827                                 break;
 828                 } else {
 829                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 830                                 break;
 831                 }
 832                 mdelay(1);
 833         }
 834 }
 835
 836 /**
 837  * nand_wait - [DEFAULT]  wait until the command is done
 838  * @mtd:        MTD device structure
 839  * @chip:       NAND chip structure
 840  *
 841  * Wait for command done. This applies to erase and program only
 842  * Erase can take up to 400ms and program up to 20ms according to
 843  * general NAND and SmartMedia specs
 844  */
 845 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 846 {
 847
 848         unsigned long timeo = jiffies;
 849         int status, state = chip->state;
 850
 851         if (state == FL_ERASING)
 852                 timeo += (HZ * 400) / 1000;
 853         else
 854                 timeo += (HZ * 20) / 1000;
 855
 856         led_trigger_event(nand_led_trigger, LED_FULL);
 857
 858         /* Apply this short delay always to ensure that we do wait tWB in
 859          * any case on any machine. */
 860         ndelay(100);
 861
 862         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 863                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 864         else
 865                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 866
 867         if (in_interrupt() || oops_in_progress)
 868                 panic_nand_wait(mtd, chip, timeo);
 869         else {
 870                 while (time_before(jiffies, timeo)) {
 871                         if (chip->dev_ready) {
 872                                 if (chip->dev_ready(mtd))
 873                                         break;
 874                         } else {
 875                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 876                                         break;
 877                         }
 878                         cond_resched();
 879                 }
 880         }
 881         led_trigger_event(nand_led_trigger, LED_OFF);
 882
 883         status = (int)chip->read_byte(mtd);
 884         return status;
 885 }
 886
 887 /**
 888  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 889  *
 890  * @mtd: mtd info
 891  * @ofs: offset to start unlock from
 892  * @len: length to unlock
 893  * @invert:   when = 0, unlock the range of blocks within the lower and
 894  *                      upper boundary address
 895  *            when = 1, unlock the range of blocks outside the boundaries
 896  *                      of the lower and upper boundary address
 897  *
 898  * return - unlock status
 899  */
 900 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 901                                         uint64_t len, int invert)
 902 {
 903         int ret = 0;
 904         int status, page;
 905         struct nand_chip *chip = mtd->priv;
 906
 907         /* Submit address of first page to unlock */
 908         page = ofs >> chip->page_shift;
 909         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 910
 911         /* Submit address of last page to unlock */
 912         page = (ofs + len) >> chip->page_shift;
 913         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 914                                 (page | invert) & chip->pagemask);
 915
 916         /* Call wait ready function */
 917         status = chip->waitfunc(mtd, chip);
 918         /* See if device thinks it succeeded */
 919         if (status & 0x01) {
 920                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
 921                                         __func__, status);
 922                 ret = -EIO;
 923         }
 924
 925         return ret;
 926 }
 927
 928 /**
 929  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 930  *
 931  * @mtd: mtd info
 932  * @ofs: offset to start unlock from
 933  * @len: length to unlock
 934  *
 935  * return - unlock status
 936  */
 937 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 938 {
 939         int ret = 0;
 940         int chipnr;
 941         struct nand_chip *chip = mtd->priv;
 942
 943         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 944                         __func__, (unsigned long long)ofs, len);
 945
 946         if (check_offs_len(mtd, ofs, len))
 947                 ret = -EINVAL;
 948
 949         /* Align to last block address if size addresses end of the device */
 950         if (ofs + len == mtd->size)
 951                 len -= mtd->erasesize;
 952
 953         nand_get_device(chip, mtd, FL_UNLOCKING);
 954
 955         /* Shift to get chip number */
 956         chipnr = ofs >> chip->chip_shift;
 957
 958         chip->select_chip(mtd, chipnr);
 959
 960         /* Check, if it is write protected */
 961         if (nand_check_wp(mtd)) {
 962                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 963                                         __func__);
 964                 ret = -EIO;
 965                 goto out;
 966         }
 967
 968         ret = __nand_unlock(mtd, ofs, len, 0);
 969
 970 out:
 971         nand_release_device(mtd);
 972
 973         return ret;
 974 }
 975 EXPORT_SYMBOL(nand_unlock);
 976
 977 /**
 978  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 979  *
 980  * @mtd: mtd info
 981  * @ofs: offset to start unlock from
 982  * @len: length to unlock
 983  *
 984  * return - lock status
 985  *
 986  * This feature is not supported in many NAND parts. 'Micron' NAND parts
 987  * do have this feature, but it allows only to lock all blocks, not for
 988  * specified range for block.
 989  *
 990  * Implementing 'lock' feature by making use of 'unlock', for now.
 991  */
 992 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 993 {
 994         int ret = 0;
 995         int chipnr, status, page;
 996         struct nand_chip *chip = mtd->priv;
 997
 998         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 999                         __func__, (unsigned long long)ofs, len);
1000
1001         if (check_offs_len(mtd, ofs, len))
1002                 ret = -EINVAL;
1003
1004         nand_get_device(chip, mtd, FL_LOCKING);
1005
1006         /* Shift to get chip number */
1007         chipnr = ofs >> chip->chip_shift;
1008
1009         chip->select_chip(mtd, chipnr);
1010
1011         /* Check, if it is write protected */
1012         if (nand_check_wp(mtd)) {
1013                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1014                                         __func__);
1015                 status = MTD_ERASE_FAILED;
1016                 ret = -EIO;
1017                 goto out;
1018         }
1019
1020         /* Submit address of first page to lock */
1021         page = ofs >> chip->page_shift;
1022         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1023
1024         /* Call wait ready function */
1025         status = chip->waitfunc(mtd, chip);
1026         /* See if device thinks it succeeded */
1027         if (status & 0x01) {
1028                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1029                                         __func__, status);
1030                 ret = -EIO;
1031                 goto out;
1032         }
1033
1034         ret = __nand_unlock(mtd, ofs, len, 0x1);
1035
1036 out:
1037         nand_release_device(mtd);
1038
1039         return ret;
1040 }
1041 EXPORT_SYMBOL(nand_lock);
1042
1043 /**
1044  * nand_read_page_raw - [Intern] read raw page data without ecc
1045  * @mtd:        mtd info structure
1046  * @chip:       nand chip info structure
1047  * @buf:        buffer to store read data
1048  * @page:       page number to read
1049  *
1050  * Not for syndrome calculating ecc controllers, which use a special oob layout
1051  */
1052 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1053                               uint8_t *buf, int page)
1054 {
1055         chip->read_buf(mtd, buf, mtd->writesize);
1056         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1057         return 0;
1058 }
1059
1060 /**
1061  * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1062  * @mtd:        mtd info structure
1063  * @chip:       nand chip info structure
1064  * @buf:        buffer to store read data
1065  * @page:       page number to read
1066  *
1067  * We need a special oob layout and handling even when OOB isn't used.
1068  */
1069 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1070                                         struct nand_chip *chip,
1071                                         uint8_t *buf, int page)
1072 {
1073         int eccsize = chip->ecc.size;
1074         int eccbytes = chip->ecc.bytes;
1075         uint8_t *oob = chip->oob_poi;
1076         int steps, size;
1077
1078         for (steps = chip->ecc.steps; steps > 0; steps--) {
1079                 chip->read_buf(mtd, buf, eccsize);
1080                 buf += eccsize;
1081
1082                 if (chip->ecc.prepad) {
1083                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1084                         oob += chip->ecc.prepad;
1085                 }
1086
1087                 chip->read_buf(mtd, oob, eccbytes);
1088                 oob += eccbytes;
1089
1090                 if (chip->ecc.postpad) {
1091                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1092                         oob += chip->ecc.postpad;
1093                 }
1094         }
1095
1096         size = mtd->oobsize - (oob - chip->oob_poi);
1097         if (size)
1098                 chip->read_buf(mtd, oob, size);
1099
1100         return 0;
1101 }
1102
1103 /**
1104  * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1105  * @mtd:        mtd info structure
1106  * @chip:       nand chip info structure
1107  * @buf:        buffer to store read data
1108  * @page:       page number to read
1109  */
1110 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1111                                 uint8_t *buf, int page)
1112 {
1113         int i, eccsize = chip->ecc.size;
1114         int eccbytes = chip->ecc.bytes;
1115         int eccsteps = chip->ecc.steps;
1116         uint8_t *p = buf;
1117         uint8_t *ecc_calc = chip->buffers->ecccalc;
1118         uint8_t *ecc_code = chip->buffers->ecccode;
1119         uint32_t *eccpos = chip->ecc.layout->eccpos;
1120
1121         chip->ecc.read_page_raw(mtd, chip, buf, page);
1122
1123         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1124                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1125
1126         for (i = 0; i < chip->ecc.total; i++)
1127                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1128
1129         eccsteps = chip->ecc.steps;
1130         p = buf;
1131
1132         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1133                 int stat;
1134
1135                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1136                 if (stat < 0)
1137                         mtd->ecc_stats.failed++;
1138                 else
1139                         mtd->ecc_stats.corrected += stat;
1140         }
1141         return 0;
1142 }
1143
1144 /**
1145  * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1146  * @mtd:        mtd info structure
1147  * @chip:       nand chip info structure
1148  * @data_offs:  offset of requested data within the page
1149  * @readlen:    data length
1150  * @bufpoi:     buffer to store read data
1151  */
1152 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1153                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1154 {
1155         int start_step, end_step, num_steps;
1156         uint32_t *eccpos = chip->ecc.layout->eccpos;
1157         uint8_t *p;
1158         int data_col_addr, i, gaps = 0;
1159         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1160         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1161         int index = 0;
1162
1163         /* Column address wihin the page aligned to ECC size (256bytes). */
1164         start_step = data_offs / chip->ecc.size;
1165         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1166         num_steps = end_step - start_step + 1;
1167
1168         /* Data size aligned to ECC ecc.size*/
1169         datafrag_len = num_steps * chip->ecc.size;
1170         eccfrag_len = num_steps * chip->ecc.bytes;
1171
1172         data_col_addr = start_step * chip->ecc.size;
1173         /* If we read not a page aligned data */
1174         if (data_col_addr != 0)
1175                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1176
1177         p = bufpoi + data_col_addr;
1178         chip->read_buf(mtd, p, datafrag_len);
1179
1180         /* Calculate  ECC */
1181         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1182                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1183
1184         /* The performance is faster if to position offsets
1185            according to ecc.pos. Let make sure here that
1186            there are no gaps in ecc positions */
1187         for (i = 0; i < eccfrag_len - 1; i++) {
1188                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1189                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1190                         gaps = 1;
1191                         break;
1192                 }
1193         }
1194         if (gaps) {
1195                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1196                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1197         } else {
1198                 /* send the command to read the particular ecc bytes */
1199                 /* take care about buswidth alignment in read_buf */
1200                 index = start_step * chip->ecc.bytes;
1201
1202                 aligned_pos = eccpos[index] & ~(busw - 1);
1203                 aligned_len = eccfrag_len;
1204                 if (eccpos[index] & (busw - 1))
1205                         aligned_len++;
1206                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1207                         aligned_len++;
1208
1209                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1210                                         mtd->writesize + aligned_pos, -1);
1211                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1212         }
1213
1214         for (i = 0; i < eccfrag_len; i++)
1215                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1216
1217         p = bufpoi + data_col_addr;
1218         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1219                 int stat;
1220
1221                 stat = chip->ecc.correct(mtd, p,
1222                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1223                 if (stat < 0)
1224                         mtd->ecc_stats.failed++;
1225                 else
1226                         mtd->ecc_stats.corrected += stat;
1227         }
1228         return 0;
1229 }
1230
1231 /**
1232  * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1233  * @mtd:        mtd info structure
1234  * @chip:       nand chip info structure
1235  * @buf:        buffer to store read data
1236  * @page:       page number to read
1237  *
1238  * Not for syndrome calculating ecc controllers which need a special oob layout
1239  */
1240 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1241                                 uint8_t *buf, int page)
1242 {
1243         int i, eccsize = chip->ecc.size;
1244         int eccbytes = chip->ecc.bytes;
1245         int eccsteps = chip->ecc.steps;
1246         uint8_t *p = buf;
1247         uint8_t *ecc_calc = chip->buffers->ecccalc;
1248         uint8_t *ecc_code = chip->buffers->ecccode;
1249         uint32_t *eccpos = chip->ecc.layout->eccpos;
1250
1251         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1252                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1253                 chip->read_buf(mtd, p, eccsize);
1254                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1255         }
1256         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1257
1258         for (i = 0; i < chip->ecc.total; i++)
1259                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1260
1261         eccsteps = chip->ecc.steps;
1262         p = buf;
1263
1264         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1265                 int stat;
1266
1267                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1268                 if (stat < 0)
1269                         mtd->ecc_stats.failed++;
1270                 else
1271                         mtd->ecc_stats.corrected += stat;
1272         }
1273         return 0;
1274 }
1275
1276 /**
1277  * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1278  * @mtd:        mtd info structure
1279  * @chip:       nand chip info structure
1280  * @buf:        buffer to store read data
1281  * @page:       page number to read
1282  *
1283  * Hardware ECC for large page chips, require OOB to be read first.
1284  * For this ECC mode, the write_page method is re-used from ECC_HW.
1285  * These methods read/write ECC from the OOB area, unlike the
1286  * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1287  * "infix ECC" scheme and reads/writes ECC from the data area, by
1288  * overwriting the NAND manufacturer bad block markings.
1289  */
1290 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1291         struct nand_chip *chip, uint8_t *buf, int page)
1292 {
1293         int i, eccsize = chip->ecc.size;
1294         int eccbytes = chip->ecc.bytes;
1295         int eccsteps = chip->ecc.steps;
1296         uint8_t *p = buf;
1297         uint8_t *ecc_code = chip->buffers->ecccode;
1298         uint32_t *eccpos = chip->ecc.layout->eccpos;
1299         uint8_t *ecc_calc = chip->buffers->ecccalc;
1300
1301         /* Read the OOB area first */
1302         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1303         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1304         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1305
1306         for (i = 0; i < chip->ecc.total; i++)
1307                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1308
1309         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1310                 int stat;
1311
1312                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1313                 chip->read_buf(mtd, p, eccsize);
1314                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1315
1316                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1317                 if (stat < 0)
1318                         mtd->ecc_stats.failed++;
1319                 else
1320                         mtd->ecc_stats.corrected += stat;
1321         }
1322         return 0;
1323 }
1324
1325 /**
1326  * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1327  * @mtd:        mtd info structure
1328  * @chip:       nand chip info structure
1329  * @buf:        buffer to store read data
1330  * @page:       page number to read
1331  *
1332  * The hw generator calculates the error syndrome automatically. Therefor
1333  * we need a special oob layout and handling.
1334  */
1335 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1336                                    uint8_t *buf, int page)
1337 {
1338         int i, eccsize = chip->ecc.size;
1339         int eccbytes = chip->ecc.bytes;
1340         int eccsteps = chip->ecc.steps;
1341         uint8_t *p = buf;
1342         uint8_t *oob = chip->oob_poi;
1343
1344         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1345                 int stat;
1346
1347                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1348                 chip->read_buf(mtd, p, eccsize);
1349
1350                 if (chip->ecc.prepad) {
1351                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1352                         oob += chip->ecc.prepad;
1353                 }
1354
1355                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1356                 chip->read_buf(mtd, oob, eccbytes);
1357                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1358
1359                 if (stat < 0)
1360                         mtd->ecc_stats.failed++;
1361                 else
1362                         mtd->ecc_stats.corrected += stat;
1363
1364                 oob += eccbytes;
1365
1366                 if (chip->ecc.postpad) {
1367                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1368                         oob += chip->ecc.postpad;
1369                 }
1370         }
1371
1372         /* Calculate remaining oob bytes */
1373         i = mtd->oobsize - (oob - chip->oob_poi);
1374         if (i)
1375                 chip->read_buf(mtd, oob, i);
1376
1377         return 0;
1378 }
1379
1380 /**
1381  * nand_transfer_oob - [Internal] Transfer oob to client buffer
1382  * @chip:       nand chip structure
1383  * @oob:        oob destination address
1384  * @ops:        oob ops structure
1385  * @len:        size of oob to transfer
1386  */
1387 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1388                                   struct mtd_oob_ops *ops, size_t len)
1389 {
1390         switch (ops->mode) {
1391
1392         case MTD_OOB_PLACE:
1393         case MTD_OOB_RAW:
1394                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1395                 return oob + len;
1396
1397         case MTD_OOB_AUTO: {
1398                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1399                 uint32_t boffs = 0, roffs = ops->ooboffs;
1400                 size_t bytes = 0;
1401
1402                 for (; free->length && len; free++, len -= bytes) {
1403                         /* Read request not from offset 0 ? */
1404                         if (unlikely(roffs)) {
1405                                 if (roffs >= free->length) {
1406                                         roffs -= free->length;
1407                                         continue;
1408                                 }
1409                                 boffs = free->offset + roffs;
1410                                 bytes = min_t(size_t, len,
1411                                               (free->length - roffs));
1412                                 roffs = 0;
1413                         } else {
1414                                 bytes = min_t(size_t, len, free->length);
1415                                 boffs = free->offset;
1416                         }
1417                         memcpy(oob, chip->oob_poi + boffs, bytes);
1418                         oob += bytes;
1419                 }
1420                 return oob;
1421         }
1422         default:
1423                 BUG();
1424         }
1425         return NULL;
1426 }
1427
1428 /**
1429  * nand_do_read_ops - [Internal] Read data with ECC
1430  *
1431  * @mtd:        MTD device structure
1432  * @from:       offset to read from
1433  * @ops:        oob ops structure
1434  *
1435  * Internal function. Called with chip held.
1436  */
1437 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1438                             struct mtd_oob_ops *ops)
1439 {
1440         int chipnr, page, realpage, col, bytes, aligned;
1441         struct nand_chip *chip = mtd->priv;
1442         struct mtd_ecc_stats stats;
1443         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1444         int sndcmd = 1;
1445         int ret = 0;
1446         uint32_t readlen = ops->len;
1447         uint32_t oobreadlen = ops->ooblen;
1448         uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1449                 mtd->oobavail : mtd->oobsize;
1450
1451         uint8_t *bufpoi, *oob, *buf;
1452
1453         stats = mtd->ecc_stats;
1454
1455         chipnr = (int)(from >> chip->chip_shift);
1456         chip->select_chip(mtd, chipnr);
1457
1458         realpage = (int)(from >> chip->page_shift);
1459         page = realpage & chip->pagemask;
1460
1461         col = (int)(from & (mtd->writesize - 1));
1462
1463         buf = ops->datbuf;
1464         oob = ops->oobbuf;
1465
1466         while (1) {
1467                 bytes = min(mtd->writesize - col, readlen);
1468                 aligned = (bytes == mtd->writesize);
1469
1470                 /* Is the current page in the buffer ? */
1471                 if (realpage != chip->pagebuf || oob) {
1472                         bufpoi = aligned ? buf : chip->buffers->databuf;
1473
1474                         if (likely(sndcmd)) {
1475                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1476                                 sndcmd = 0;
1477                         }
1478
1479                         /* Now read the page into the buffer */
1480                         if (unlikely(ops->mode == MTD_OOB_RAW))
1481                                 ret = chip->ecc.read_page_raw(mtd, chip,
1482                                                               bufpoi, page);
1483                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1484                                 ret = chip->ecc.read_subpage(mtd, chip,
1485                                                         col, bytes, bufpoi);
1486                         else
1487                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1488                                                           page);
1489                         if (ret < 0)
1490                                 break;
1491
1492                         /* Transfer not aligned data */
1493                         if (!aligned) {
1494                                 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1495                                     !(mtd->ecc_stats.failed - stats.failed))
1496                                         chip->pagebuf = realpage;
1497                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1498                         }
1499
1500                         buf += bytes;
1501
1502                         if (unlikely(oob)) {
1503
1504                                 int toread = min(oobreadlen, max_oobsize);
1505
1506                                 if (toread) {
1507                                         oob = nand_transfer_oob(chip,
1508                                                 oob, ops, toread);
1509                                         oobreadlen -= toread;
1510                                 }
1511                         }
1512
1513                         if (!(chip->options & NAND_NO_READRDY)) {
1514                                 /*
1515                                  * Apply delay or wait for ready/busy pin. Do
1516                                  * this before the AUTOINCR check, so no
1517                                  * problems arise if a chip which does auto
1518                                  * increment is marked as NOAUTOINCR by the
1519                                  * board driver.
1520                                  */
1521                                 if (!chip->dev_ready)
1522                                         udelay(chip->chip_delay);
1523                                 else
1524                                         nand_wait_ready(mtd);
1525                         }
1526                 } else {
1527                         memcpy(buf, chip->buffers->databuf + col, bytes);
1528                         buf += bytes;
1529                 }
1530
1531                 readlen -= bytes;
1532
1533                 if (!readlen)
1534                         break;
1535
1536                 /* For subsequent reads align to page boundary. */
1537                 col = 0;
1538                 /* Increment page address */
1539                 realpage++;
1540
1541                 page = realpage & chip->pagemask;
1542                 /* Check, if we cross a chip boundary */
1543                 if (!page) {
1544                         chipnr++;
1545                         chip->select_chip(mtd, -1);
1546                         chip->select_chip(mtd, chipnr);
1547                 }
1548
1549                 /* Check, if the chip supports auto page increment
1550                  * or if we have hit a block boundary.
1551                  */
1552                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1553                         sndcmd = 1;
1554         }
1555
1556         ops->retlen = ops->len - (size_t) readlen;
1557         if (oob)
1558                 ops->oobretlen = ops->ooblen - oobreadlen;
1559
1560         if (ret)
1561                 return ret;
1562
1563         if (mtd->ecc_stats.failed - stats.failed)
1564                 return -EBADMSG;
1565
1566         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1567 }
1568
1569 /**
1570  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1571  * @mtd:        MTD device structure
1572  * @from:       offset to read from
1573  * @len:        number of bytes to read
1574  * @retlen:     pointer to variable to store the number of read bytes
1575  * @buf:        the databuffer to put data
1576  *
1577  * Get hold of the chip and call nand_do_read
1578  */
1579 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1580                      size_t *retlen, uint8_t *buf)
1581 {
1582         struct nand_chip *chip = mtd->priv;
1583         int ret;
1584
1585         /* Do not allow reads past end of device */
1586         if ((from + len) > mtd->size)
1587                 return -EINVAL;
1588         if (!len)
1589                 return 0;
1590
1591         nand_get_device(chip, mtd, FL_READING);
1592
1593         chip->ops.len = len;
1594         chip->ops.datbuf = buf;
1595         chip->ops.oobbuf = NULL;
1596
1597         ret = nand_do_read_ops(mtd, from, &chip->ops);
1598
1599         *retlen = chip->ops.retlen;
1600
1601         nand_release_device(mtd);
1602
1603         return ret;
1604 }
1605
1606 /**
1607  * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1608  * @mtd:        mtd info structure
1609  * @chip:       nand chip info structure
1610  * @page:       page number to read
1611  * @sndcmd:     flag whether to issue read command or not
1612  */
1613 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1614                              int page, int sndcmd)
1615 {
1616         if (sndcmd) {
1617                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1618                 sndcmd = 0;
1619         }
1620         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1621         return sndcmd;
1622 }
1623
1624 /**
1625  * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1626  *                          with syndromes
1627  * @mtd:        mtd info structure
1628  * @chip:       nand chip info structure
1629  * @page:       page number to read
1630  * @sndcmd:     flag whether to issue read command or not
1631  */
1632 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1633                                   int page, int sndcmd)
1634 {
1635         uint8_t *buf = chip->oob_poi;
1636         int length = mtd->oobsize;
1637         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1638         int eccsize = chip->ecc.size;
1639         uint8_t *bufpoi = buf;
1640         int i, toread, sndrnd = 0, pos;
1641
1642         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1643         for (i = 0; i < chip->ecc.steps; i++) {
1644                 if (sndrnd) {
1645                         pos = eccsize + i * (eccsize + chunk);
1646                         if (mtd->writesize > 512)
1647                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1648                         else
1649                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1650                 } else
1651                         sndrnd = 1;
1652                 toread = min_t(int, length, chunk);
1653                 chip->read_buf(mtd, bufpoi, toread);
1654                 bufpoi += toread;
1655                 length -= toread;
1656         }
1657         if (length > 0)
1658                 chip->read_buf(mtd, bufpoi, length);
1659
1660         return 1;
1661 }
1662
1663 /**
1664  * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1665  * @mtd:        mtd info structure
1666  * @chip:       nand chip info structure
1667  * @page:       page number to write
1668  */
1669 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1670                               int page)
1671 {
1672         int status = 0;
1673         const uint8_t *buf = chip->oob_poi;
1674         int length = mtd->oobsize;
1675
1676         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1677         chip->write_buf(mtd, buf, length);
1678         /* Send command to program the OOB data */
1679         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1680
1681         status = chip->waitfunc(mtd, chip);
1682
1683         return status & NAND_STATUS_FAIL ? -EIO : 0;
1684 }
1685
1686 /**
1687  * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1688  *                           with syndrome - only for large page flash !
1689  * @mtd:        mtd info structure
1690  * @chip:       nand chip info structure
1691  * @page:       page number to write
1692  */
1693 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1694                                    struct nand_chip *chip, int page)
1695 {
1696         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1697         int eccsize = chip->ecc.size, length = mtd->oobsize;
1698         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1699         const uint8_t *bufpoi = chip->oob_poi;
1700
1701         /*
1702          * data-ecc-data-ecc ... ecc-oob
1703          * or
1704          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1705          */
1706         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1707                 pos = steps * (eccsize + chunk);
1708                 steps = 0;
1709         } else
1710                 pos = eccsize;
1711
1712         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1713         for (i = 0; i < steps; i++) {
1714                 if (sndcmd) {
1715                         if (mtd->writesize <= 512) {
1716                                 uint32_t fill = 0xFFFFFFFF;
1717
1718                                 len = eccsize;
1719                                 while (len > 0) {
1720                                         int num = min_t(int, len, 4);
1721                                         chip->write_buf(mtd, (uint8_t *)&fill,
1722                                                         num);
1723                                         len -= num;
1724                                 }
1725                         } else {
1726                                 pos = eccsize + i * (eccsize + chunk);
1727                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1728                         }
1729                 } else
1730                         sndcmd = 1;
1731                 len = min_t(int, length, chunk);
1732                 chip->write_buf(mtd, bufpoi, len);
1733                 bufpoi += len;
1734                 length -= len;
1735         }
1736         if (length > 0)
1737                 chip->write_buf(mtd, bufpoi, length);
1738
1739         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1740         status = chip->waitfunc(mtd, chip);
1741
1742         return status & NAND_STATUS_FAIL ? -EIO : 0;
1743 }
1744
1745 /**
1746  * nand_do_read_oob - [Intern] NAND read out-of-band
1747  * @mtd:        MTD device structure
1748  * @from:       offset to read from
1749  * @ops:        oob operations description structure
1750  *
1751  * NAND read out-of-band data from the spare area
1752  */
1753 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1754                             struct mtd_oob_ops *ops)
1755 {
1756         int page, realpage, chipnr, sndcmd = 1;
1757         struct nand_chip *chip = mtd->priv;
1758         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1759         int readlen = ops->ooblen;
1760         int len;
1761         uint8_t *buf = ops->oobbuf;
1762
1763         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1764                         __func__, (unsigned long long)from, readlen);
1765
1766         if (ops->mode == MTD_OOB_AUTO)
1767                 len = chip->ecc.layout->oobavail;
1768         else
1769                 len = mtd->oobsize;
1770
1771         if (unlikely(ops->ooboffs >= len)) {
1772                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1773                                         "outside oob\n", __func__);
1774                 return -EINVAL;
1775         }
1776
1777         /* Do not allow reads past end of device */
1778         if (unlikely(from >= mtd->size ||
1779                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1780                                         (from >> chip->page_shift)) * len)) {
1781                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1782                                         "of device\n", __func__);
1783                 return -EINVAL;
1784         }
1785
1786         chipnr = (int)(from >> chip->chip_shift);
1787         chip->select_chip(mtd, chipnr);
1788
1789         /* Shift to get page */
1790         realpage = (int)(from >> chip->page_shift);
1791         page = realpage & chip->pagemask;
1792
1793         while (1) {
1794                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1795
1796                 len = min(len, readlen);
1797                 buf = nand_transfer_oob(chip, buf, ops, len);
1798
1799                 if (!(chip->options & NAND_NO_READRDY)) {
1800                         /*
1801                          * Apply delay or wait for ready/busy pin. Do this
1802                          * before the AUTOINCR check, so no problems arise if a
1803                          * chip which does auto increment is marked as
1804                          * NOAUTOINCR by the board driver.
1805                          */
1806                         if (!chip->dev_ready)
1807                                 udelay(chip->chip_delay);
1808                         else
1809                                 nand_wait_ready(mtd);
1810                 }
1811
1812                 readlen -= len;
1813                 if (!readlen)
1814                         break;
1815
1816                 /* Increment page address */
1817                 realpage++;
1818
1819                 page = realpage & chip->pagemask;
1820                 /* Check, if we cross a chip boundary */
1821                 if (!page) {
1822                         chipnr++;
1823                         chip->select_chip(mtd, -1);
1824                         chip->select_chip(mtd, chipnr);
1825                 }
1826
1827                 /* Check, if the chip supports auto page increment
1828                  * or if we have hit a block boundary.
1829                  */
1830                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1831                         sndcmd = 1;
1832         }
1833
1834         ops->oobretlen = ops->ooblen;
1835         return 0;
1836 }
1837
1838 /**
1839  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1840  * @mtd:        MTD device structure
1841  * @from:       offset to read from
1842  * @ops:        oob operation description structure
1843  *
1844  * NAND read data and/or out-of-band data
1845  */
1846 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1847                          struct mtd_oob_ops *ops)
1848 {
1849         struct nand_chip *chip = mtd->priv;
1850         int ret = -ENOTSUPP;
1851
1852         ops->retlen = 0;
1853
1854         /* Do not allow reads past end of device */
1855         if (ops->datbuf && (from + ops->len) > mtd->size) {
1856                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1857                                 "beyond end of device\n", __func__);
1858                 return -EINVAL;
1859         }
1860
1861         nand_get_device(chip, mtd, FL_READING);
1862
1863         switch (ops->mode) {
1864         case MTD_OOB_PLACE:
1865         case MTD_OOB_AUTO:
1866         case MTD_OOB_RAW:
1867                 break;
1868
1869         default:
1870                 goto out;
1871         }
1872
1873         if (!ops->datbuf)
1874                 ret = nand_do_read_oob(mtd, from, ops);
1875         else
1876                 ret = nand_do_read_ops(mtd, from, ops);
1877
1878 out:
1879         nand_release_device(mtd);
1880         return ret;
1881 }
1882
1883
1884 /**
1885  * nand_write_page_raw - [Intern] raw page write function
1886  * @mtd:        mtd info structure
1887  * @chip:       nand chip info structure
1888  * @buf:        data buffer
1889  *
1890  * Not for syndrome calculating ecc controllers, which use a special oob layout
1891  */
1892 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1893                                 const uint8_t *buf)
1894 {
1895         chip->write_buf(mtd, buf, mtd->writesize);
1896         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1897 }
1898
1899 /**
1900  * nand_write_page_raw_syndrome - [Intern] raw page write function
1901  * @mtd:        mtd info structure
1902  * @chip:       nand chip info structure
1903  * @buf:        data buffer
1904  *
1905  * We need a special oob layout and handling even when ECC isn't checked.
1906  */
1907 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1908                                         struct nand_chip *chip,
1909                                         const uint8_t *buf)
1910 {
1911         int eccsize = chip->ecc.size;
1912         int eccbytes = chip->ecc.bytes;
1913         uint8_t *oob = chip->oob_poi;
1914         int steps, size;
1915
1916         for (steps = chip->ecc.steps; steps > 0; steps--) {
1917                 chip->write_buf(mtd, buf, eccsize);
1918                 buf += eccsize;
1919
1920                 if (chip->ecc.prepad) {
1921                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1922                         oob += chip->ecc.prepad;
1923                 }
1924
1925                 chip->read_buf(mtd, oob, eccbytes);
1926                 oob += eccbytes;
1927
1928                 if (chip->ecc.postpad) {
1929                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1930                         oob += chip->ecc.postpad;
1931                 }
1932         }
1933
1934         size = mtd->oobsize - (oob - chip->oob_poi);
1935         if (size)
1936                 chip->write_buf(mtd, oob, size);
1937 }
1938 /**
1939  * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1940  * @mtd:        mtd info structure
1941  * @chip:       nand chip info structure
1942  * @buf:        data buffer
1943  */
1944 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1945                                   const uint8_t *buf)
1946 {
1947         int i, eccsize = chip->ecc.size;
1948         int eccbytes = chip->ecc.bytes;
1949         int eccsteps = chip->ecc.steps;
1950         uint8_t *ecc_calc = chip->buffers->ecccalc;
1951         const uint8_t *p = buf;
1952         uint32_t *eccpos = chip->ecc.layout->eccpos;
1953
1954         /* Software ecc calculation */
1955         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1956                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1957
1958         for (i = 0; i < chip->ecc.total; i++)
1959                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1960
1961         chip->ecc.write_page_raw(mtd, chip, buf);
1962 }
1963
1964 /**
1965  * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1966  * @mtd:        mtd info structure
1967  * @chip:       nand chip info structure
1968  * @buf:        data buffer
1969  */
1970 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1971                                   const uint8_t *buf)
1972 {
1973         int i, eccsize = chip->ecc.size;
1974         int eccbytes = chip->ecc.bytes;
1975         int eccsteps = chip->ecc.steps;
1976         uint8_t *ecc_calc = chip->buffers->ecccalc;
1977         const uint8_t *p = buf;
1978         uint32_t *eccpos = chip->ecc.layout->eccpos;
1979
1980         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1981                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1982                 chip->write_buf(mtd, p, eccsize);
1983                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1984         }
1985
1986         for (i = 0; i < chip->ecc.total; i++)
1987                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1988
1989         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1990 }
1991
1992 /**
1993  * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
1994  * @mtd:        mtd info structure
1995  * @chip:       nand chip info structure
1996  * @buf:        data buffer
1997  *
1998  * The hw generator calculates the error syndrome automatically. Therefor
1999  * we need a special oob layout and handling.
2000  */
2001 static void nand_write_page_syndrome(struct mtd_info *mtd,
2002                                     struct nand_chip *chip, const uint8_t *buf)
2003 {
2004         int i, eccsize = chip->ecc.size;
2005         int eccbytes = chip->ecc.bytes;
2006         int eccsteps = chip->ecc.steps;
2007         const uint8_t *p = buf;
2008         uint8_t *oob = chip->oob_poi;
2009
2010         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2011
2012                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2013                 chip->write_buf(mtd, p, eccsize);
2014
2015                 if (chip->ecc.prepad) {
2016                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2017                         oob += chip->ecc.prepad;
2018                 }
2019
2020                 chip->ecc.calculate(mtd, p, oob);
2021                 chip->write_buf(mtd, oob, eccbytes);
2022                 oob += eccbytes;
2023
2024                 if (chip->ecc.postpad) {
2025                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2026                         oob += chip->ecc.postpad;
2027                 }
2028         }
2029
2030         /* Calculate remaining oob bytes */
2031         i = mtd->oobsize - (oob - chip->oob_poi);
2032         if (i)
2033                 chip->write_buf(mtd, oob, i);
2034 }
2035
2036 /**
2037  * nand_write_page - [REPLACEABLE] write one page
2038  * @mtd:        MTD device structure
2039  * @chip:       NAND chip descriptor
2040  * @buf:        the data to write
2041  * @page:       page number to write
2042  * @cached:     cached programming
2043  * @raw:        use _raw version of write_page
2044  */
2045 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2046                            const uint8_t *buf, int page, int cached, int raw)
2047 {
2048         int status;
2049
2050         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2051
2052         if (unlikely(raw))
2053                 chip->ecc.write_page_raw(mtd, chip, buf);
2054         else
2055                 chip->ecc.write_page(mtd, chip, buf);
2056
2057         /*
2058          * Cached progamming disabled for now, Not sure if its worth the
2059          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2060          */
2061         cached = 0;
2062
2063         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2064
2065                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2066                 status = chip->waitfunc(mtd, chip);
2067                 /*
2068                  * See if operation failed and additional status checks are
2069                  * available
2070                  */
2071                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2072                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2073                                                page);
2074
2075                 if (status & NAND_STATUS_FAIL)
2076                         return -EIO;
2077         } else {
2078                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2079                 status = chip->waitfunc(mtd, chip);
2080         }
2081
2082 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2083         /* Send command to read back the data */
2084         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2085
2086         if (chip->verify_buf(mtd, buf, mtd->writesize))
2087                 return -EIO;
2088 #endif
2089         return 0;
2090 }
2091
2092 /**
2093  * nand_fill_oob - [Internal] Transfer client buffer to oob
2094  * @chip:       nand chip structure
2095  * @oob:        oob data buffer
2096  * @len:        oob data write length
2097  * @ops:        oob ops structure
2098  */
2099 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2100                                                 struct mtd_oob_ops *ops)
2101 {
2102         switch (ops->mode) {
2103
2104         case MTD_OOB_PLACE:
2105         case MTD_OOB_RAW:
2106                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2107                 return oob + len;
2108
2109         case MTD_OOB_AUTO: {
2110                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2111                 uint32_t boffs = 0, woffs = ops->ooboffs;
2112                 size_t bytes = 0;
2113
2114                 for (; free->length && len; free++, len -= bytes) {
2115                         /* Write request not from offset 0 ? */
2116                         if (unlikely(woffs)) {
2117                                 if (woffs >= free->length) {
2118                                         woffs -= free->length;
2119                                         continue;
2120                                 }
2121                                 boffs = free->offset + woffs;
2122                                 bytes = min_t(size_t, len,
2123                                               (free->length - woffs));
2124                                 woffs = 0;
2125                         } else {
2126                                 bytes = min_t(size_t, len, free->length);
2127                                 boffs = free->offset;
2128                         }
2129                         memcpy(chip->oob_poi + boffs, oob, bytes);
2130                         oob += bytes;
2131                 }
2132                 return oob;
2133         }
2134         default:
2135                 BUG();
2136         }
2137         return NULL;
2138 }
2139
2140 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2141
2142 /**
2143  * nand_do_write_ops - [Internal] NAND write with ECC
2144  * @mtd:        MTD device structure
2145  * @to:         offset to write to
2146  * @ops:        oob operations description structure
2147  *
2148  * NAND write with ECC
2149  */
2150 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2151                              struct mtd_oob_ops *ops)
2152 {
2153         int chipnr, realpage, page, blockmask, column;
2154         struct nand_chip *chip = mtd->priv;
2155         uint32_t writelen = ops->len;
2156
2157         uint32_t oobwritelen = ops->ooblen;
2158         uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2159                                 mtd->oobavail : mtd->oobsize;
2160
2161         uint8_t *oob = ops->oobbuf;
2162         uint8_t *buf = ops->datbuf;
2163         int ret, subpage;
2164
2165         ops->retlen = 0;
2166         if (!writelen)
2167                 return 0;
2168
2169         /* reject writes, which are not page aligned */
2170         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2171                 printk(KERN_NOTICE "%s: Attempt to write not "
2172                                 "page aligned data\n", __func__);
2173                 return -EINVAL;
2174         }
2175
2176         column = to & (mtd->writesize - 1);
2177         subpage = column || (writelen & (mtd->writesize - 1));
2178
2179         if (subpage && oob)
2180                 return -EINVAL;
2181
2182         chipnr = (int)(to >> chip->chip_shift);
2183         chip->select_chip(mtd, chipnr);
2184
2185         /* Check, if it is write protected */
2186         if (nand_check_wp(mtd))
2187                 return -EIO;
2188
2189         realpage = (int)(to >> chip->page_shift);
2190         page = realpage & chip->pagemask;
2191         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2192
2193         /* Invalidate the page cache, when we write to the cached page */
2194         if (to <= (chip->pagebuf << chip->page_shift) &&
2195             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2196                 chip->pagebuf = -1;
2197
2198         /* If we're not given explicit OOB data, let it be 0xFF */
2199         if (likely(!oob))
2200                 memset(chip->oob_poi, 0xff, mtd->oobsize);
2201
2202         /* Don't allow multipage oob writes with offset */
2203         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2204                 return -EINVAL;
2205
2206         while (1) {
2207                 int bytes = mtd->writesize;
2208                 int cached = writelen > bytes && page != blockmask;
2209                 uint8_t *wbuf = buf;
2210
2211                 /* Partial page write ? */
2212                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2213                         cached = 0;
2214                         bytes = min_t(int, bytes - column, (int) writelen);
2215                         chip->pagebuf = -1;
2216                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2217                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2218                         wbuf = chip->buffers->databuf;
2219                 }
2220
2221                 if (unlikely(oob)) {
2222                         size_t len = min(oobwritelen, oobmaxlen);
2223                         oob = nand_fill_oob(chip, oob, len, ops);
2224                         oobwritelen -= len;
2225                 }
2226
2227                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2228                                        (ops->mode == MTD_OOB_RAW));
2229                 if (ret)
2230                         break;
2231
2232                 writelen -= bytes;
2233                 if (!writelen)
2234                         break;
2235
2236                 column = 0;
2237                 buf += bytes;
2238                 realpage++;
2239
2240                 page = realpage & chip->pagemask;
2241                 /* Check, if we cross a chip boundary */
2242                 if (!page) {
2243                         chipnr++;
2244                         chip->select_chip(mtd, -1);
2245                         chip->select_chip(mtd, chipnr);
2246                 }
2247         }
2248
2249         ops->retlen = ops->len - writelen;
2250         if (unlikely(oob))
2251                 ops->oobretlen = ops->ooblen;
2252         return ret;
2253 }
2254
2255 /**
2256  * panic_nand_write - [MTD Interface] NAND write with ECC
2257  * @mtd:        MTD device structure
2258  * @to:         offset to write to
2259  * @len:        number of bytes to write
2260  * @retlen:     pointer to variable to store the number of written bytes
2261  * @buf:        the data to write
2262  *
2263  * NAND write with ECC. Used when performing writes in interrupt context, this
2264  * may for example be called by mtdoops when writing an oops while in panic.
2265  */
2266 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2267                             size_t *retlen, const uint8_t *buf)
2268 {
2269         struct nand_chip *chip = mtd->priv;
2270         int ret;
2271
2272         /* Do not allow reads past end of device */
2273         if ((to + len) > mtd->size)
2274                 return -EINVAL;
2275         if (!len)
2276                 return 0;
2277
2278         /* Wait for the device to get ready.  */
2279         panic_nand_wait(mtd, chip, 400);
2280
2281         /* Grab the device.  */
2282         panic_nand_get_device(chip, mtd, FL_WRITING);
2283
2284         chip->ops.len = len;
2285         chip->ops.datbuf = (uint8_t *)buf;
2286         chip->ops.oobbuf = NULL;
2287
2288         ret = nand_do_write_ops(mtd, to, &chip->ops);
2289
2290         *retlen = chip->ops.retlen;
2291         return ret;
2292 }
2293
2294 /**
2295  * nand_write - [MTD Interface] NAND write with ECC
2296  * @mtd:        MTD device structure
2297  * @to:         offset to write to
2298  * @len:        number of bytes to write
2299  * @retlen:     pointer to variable to store the number of written bytes
2300  * @buf:        the data to write
2301  *
2302  * NAND write with ECC
2303  */
2304 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2305                           size_t *retlen, const uint8_t *buf)
2306 {
2307         struct nand_chip *chip = mtd->priv;
2308         int ret;
2309
2310         /* Do not allow reads past end of device */
2311         if ((to + len) > mtd->size)
2312                 return -EINVAL;
2313         if (!len)
2314                 return 0;
2315
2316         nand_get_device(chip, mtd, FL_WRITING);
2317
2318         chip->ops.len = len;
2319         chip->ops.datbuf = (uint8_t *)buf;
2320         chip->ops.oobbuf = NULL;
2321
2322         ret = nand_do_write_ops(mtd, to, &chip->ops);
2323
2324         *retlen = chip->ops.retlen;
2325
2326         nand_release_device(mtd);
2327
2328         return ret;
2329 }
2330
2331 /**
2332  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2333  * @mtd:        MTD device structure
2334  * @to:         offset to write to
2335  * @ops:        oob operation description structure
2336  *
2337  * NAND write out-of-band
2338  */
2339 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2340                              struct mtd_oob_ops *ops)
2341 {
2342         int chipnr, page, status, len;
2343         struct nand_chip *chip = mtd->priv;
2344
2345         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2346                          __func__, (unsigned int)to, (int)ops->ooblen);
2347
2348         if (ops->mode == MTD_OOB_AUTO)
2349                 len = chip->ecc.layout->oobavail;
2350         else
2351                 len = mtd->oobsize;
2352
2353         /* Do not allow write past end of page */
2354         if ((ops->ooboffs + ops->ooblen) > len) {
2355                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2356                                 "past end of page\n", __func__);
2357                 return -EINVAL;
2358         }
2359
2360         if (unlikely(ops->ooboffs >= len)) {
2361                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2362                                 "write outside oob\n", __func__);
2363                 return -EINVAL;
2364         }
2365
2366         /* Do not allow write past end of device */
2367         if (unlikely(to >= mtd->size ||
2368                      ops->ooboffs + ops->ooblen >
2369                         ((mtd->size >> chip->page_shift) -
2370                          (to >> chip->page_shift)) * len)) {
2371                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2372                                 "end of device\n", __func__);
2373                 return -EINVAL;
2374         }
2375
2376         chipnr = (int)(to >> chip->chip_shift);
2377         chip->select_chip(mtd, chipnr);
2378
2379         /* Shift to get page */
2380         page = (int)(to >> chip->page_shift);
2381
2382         /*
2383          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2384          * of my DiskOnChip 2000 test units) will clear the whole data page too
2385          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2386          * it in the doc2000 driver in August 1999.  dwmw2.
2387          */
2388         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2389
2390         /* Check, if it is write protected */
2391         if (nand_check_wp(mtd))
2392                 return -EROFS;
2393
2394         /* Invalidate the page cache, if we write to the cached page */
2395         if (page == chip->pagebuf)
2396                 chip->pagebuf = -1;
2397
2398         memset(chip->oob_poi, 0xff, mtd->oobsize);
2399         nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2400         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2401         memset(chip->oob_poi, 0xff, mtd->oobsize);
2402
2403         if (status)
2404                 return status;
2405
2406         ops->oobretlen = ops->ooblen;
2407
2408         return 0;
2409 }
2410
2411 /**
2412  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2413  * @mtd:        MTD device structure
2414  * @to:         offset to write to
2415  * @ops:        oob operation description structure
2416  */
2417 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2418                           struct mtd_oob_ops *ops)
2419 {
2420         struct nand_chip *chip = mtd->priv;
2421         int ret = -ENOTSUPP;
2422
2423         ops->retlen = 0;
2424
2425         /* Do not allow writes past end of device */
2426         if (ops->datbuf && (to + ops->len) > mtd->size) {
2427                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2428                                 "end of device\n", __func__);
2429                 return -EINVAL;
2430         }
2431
2432         nand_get_device(chip, mtd, FL_WRITING);
2433
2434         switch (ops->mode) {
2435         case MTD_OOB_PLACE:
2436         case MTD_OOB_AUTO:
2437         case MTD_OOB_RAW:
2438                 break;
2439
2440         default:
2441                 goto out;
2442         }
2443
2444         if (!ops->datbuf)
2445                 ret = nand_do_write_oob(mtd, to, ops);
2446         else
2447                 ret = nand_do_write_ops(mtd, to, ops);
2448
2449 out:
2450         nand_release_device(mtd);
2451         return ret;
2452 }
2453
2454 /**
2455  * single_erease_cmd - [GENERIC] NAND standard block erase command function
2456  * @mtd:        MTD device structure
2457  * @page:       the page address of the block which will be erased
2458  *
2459  * Standard erase command for NAND chips
2460  */
2461 static void single_erase_cmd(struct mtd_info *mtd, int page)
2462 {
2463         struct nand_chip *chip = mtd->priv;
2464         /* Send commands to erase a block */
2465         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2466         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2467 }
2468
2469 /**
2470  * multi_erease_cmd - [GENERIC] AND specific block erase command function
2471  * @mtd:        MTD device structure
2472  * @page:       the page address of the block which will be erased
2473  *
2474  * AND multi block erase command function
2475  * Erase 4 consecutive blocks
2476  */
2477 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2478 {
2479         struct nand_chip *chip = mtd->priv;
2480         /* Send commands to erase a block */
2481         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2482         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2483         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2484         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2485         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2486 }
2487
2488 /**
2489  * nand_erase - [MTD Interface] erase block(s)
2490  * @mtd:        MTD device structure
2491  * @instr:      erase instruction
2492  *
2493  * Erase one ore more blocks
2494  */
2495 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2496 {
2497         return nand_erase_nand(mtd, instr, 0);
2498 }
2499
2500 #define BBT_PAGE_MASK   0xffffff3f
2501 /**
2502  * nand_erase_nand - [Internal] erase block(s)
2503  * @mtd:        MTD device structure
2504  * @instr:      erase instruction
2505  * @allowbbt:   allow erasing the bbt area
2506  *
2507  * Erase one ore more blocks
2508  */
2509 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2510                     int allowbbt)
2511 {
2512         int page, status, pages_per_block, ret, chipnr;
2513         struct nand_chip *chip = mtd->priv;
2514         loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2515         unsigned int bbt_masked_page = 0xffffffff;
2516         loff_t len;
2517
2518         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2519                                 __func__, (unsigned long long)instr->addr,
2520                                 (unsigned long long)instr->len);
2521
2522         if (check_offs_len(mtd, instr->addr, instr->len))
2523                 return -EINVAL;
2524
2525         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2526
2527         /* Grab the lock and see if the device is available */
2528         nand_get_device(chip, mtd, FL_ERASING);
2529
2530         /* Shift to get first page */
2531         page = (int)(instr->addr >> chip->page_shift);
2532         chipnr = (int)(instr->addr >> chip->chip_shift);
2533
2534         /* Calculate pages in each block */
2535         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2536
2537         /* Select the NAND device */
2538         chip->select_chip(mtd, chipnr);
2539
2540         /* Check, if it is write protected */
2541         if (nand_check_wp(mtd)) {
2542                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2543                                         __func__);
2544                 instr->state = MTD_ERASE_FAILED;
2545                 goto erase_exit;
2546         }
2547
2548         /*
2549          * If BBT requires refresh, set the BBT page mask to see if the BBT
2550          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2551          * can not be matched. This is also done when the bbt is actually
2552          * erased to avoid recusrsive updates
2553          */
2554         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2555                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2556
2557         /* Loop through the pages */
2558         len = instr->len;
2559
2560         instr->state = MTD_ERASING;
2561
2562         while (len) {
2563                 /*
2564                  * heck if we have a bad block, we do not erase bad blocks !
2565                  */
2566                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2567                                         chip->page_shift, 0, allowbbt)) {
2568                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2569                                         "at page 0x%08x\n", __func__, page);
2570                         instr->state = MTD_ERASE_FAILED;
2571                         goto erase_exit;
2572                 }
2573
2574                 /*
2575                  * Invalidate the page cache, if we erase the block which
2576                  * contains the current cached page
2577                  */
2578                 if (page <= chip->pagebuf && chip->pagebuf <
2579                     (page + pages_per_block))
2580                         chip->pagebuf = -1;
2581
2582                 chip->erase_cmd(mtd, page & chip->pagemask);
2583
2584                 status = chip->waitfunc(mtd, chip);
2585
2586                 /*
2587                  * See if operation failed and additional status checks are
2588                  * available
2589                  */
2590                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2591                         status = chip->errstat(mtd, chip, FL_ERASING,
2592                                                status, page);
2593
2594                 /* See if block erase succeeded */
2595                 if (status & NAND_STATUS_FAIL) {
2596                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2597                                         "page 0x%08x\n", __func__, page);
2598                         instr->state = MTD_ERASE_FAILED;
2599                         instr->fail_addr =
2600                                 ((loff_t)page << chip->page_shift);
2601                         goto erase_exit;
2602                 }
2603
2604                 /*
2605                  * If BBT requires refresh, set the BBT rewrite flag to the
2606                  * page being erased
2607                  */
2608                 if (bbt_masked_page != 0xffffffff &&
2609                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2610                             rewrite_bbt[chipnr] =
2611                                         ((loff_t)page << chip->page_shift);
2612
2613                 /* Increment page address and decrement length */
2614                 len -= (1 << chip->phys_erase_shift);
2615                 page += pages_per_block;
2616
2617                 /* Check, if we cross a chip boundary */
2618                 if (len && !(page & chip->pagemask)) {
2619                         chipnr++;
2620                         chip->select_chip(mtd, -1);
2621                         chip->select_chip(mtd, chipnr);
2622
2623                         /*
2624                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2625                          * page mask to see if this BBT should be rewritten
2626                          */
2627                         if (bbt_masked_page != 0xffffffff &&
2628                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2629                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2630                                         BBT_PAGE_MASK;
2631                 }
2632         }
2633         instr->state = MTD_ERASE_DONE;
2634
2635 erase_exit:
2636
2637         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2638
2639         /* Deselect and wake up anyone waiting on the device */
2640         nand_release_device(mtd);
2641
2642         /* Do call back function */
2643         if (!ret)
2644                 mtd_erase_callback(instr);
2645
2646         /*
2647          * If BBT requires refresh and erase was successful, rewrite any
2648          * selected bad block tables
2649          */
2650         if (bbt_masked_page == 0xffffffff || ret)
2651                 return ret;
2652
2653         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2654                 if (!rewrite_bbt[chipnr])
2655                         continue;
2656                 /* update the BBT for chip */
2657                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2658                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2659                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2660                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2661         }
2662
2663         /* Return more or less happy */
2664         return ret;
2665 }
2666
2667 /**
2668  * nand_sync - [MTD Interface] sync
2669  * @mtd:        MTD device structure
2670  *
2671  * Sync is actually a wait for chip ready function
2672  */
2673 static void nand_sync(struct mtd_info *mtd)
2674 {
2675         struct nand_chip *chip = mtd->priv;
2676
2677         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2678
2679         /* Grab the lock and see if the device is available */
2680         nand_get_device(chip, mtd, FL_SYNCING);
2681         /* Release it and go back */
2682         nand_release_device(mtd);
2683 }
2684
2685 /**
2686  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2687  * @mtd:        MTD device structure
2688  * @offs:       offset relative to mtd start
2689  */
2690 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2691 {
2692         /* Check for invalid offset */
2693         if (offs > mtd->size)
2694                 return -EINVAL;
2695
2696         return nand_block_checkbad(mtd, offs, 1, 0);
2697 }
2698
2699 /**
2700  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2701  * @mtd:        MTD device structure
2702  * @ofs:        offset relative to mtd start
2703  */
2704 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2705 {
2706         struct nand_chip *chip = mtd->priv;
2707         int ret;
2708
2709         ret = nand_block_isbad(mtd, ofs);
2710         if (ret) {
2711                 /* If it was bad already, return success and do nothing. */
2712                 if (ret > 0)
2713                         return 0;
2714                 return ret;
2715         }
2716
2717         return chip->block_markbad(mtd, ofs);
2718 }
2719
2720 /**
2721  * nand_suspend - [MTD Interface] Suspend the NAND flash
2722  * @mtd:        MTD device structure
2723  */
2724 static int nand_suspend(struct mtd_info *mtd)
2725 {
2726         struct nand_chip *chip = mtd->priv;
2727
2728         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2729 }
2730
2731 /**
2732  * nand_resume - [MTD Interface] Resume the NAND flash
2733  * @mtd:        MTD device structure
2734  */
2735 static void nand_resume(struct mtd_info *mtd)
2736 {
2737         struct nand_chip *chip = mtd->priv;
2738
2739         if (chip->state == FL_PM_SUSPENDED)
2740                 nand_release_device(mtd);
2741         else
2742                 printk(KERN_ERR "%s called for a chip which is not "
2743                        "in suspended state\n", __func__);
2744 }
2745
2746 /*
2747  * Set default functions
2748  */
2749 static void nand_set_defaults(struct nand_chip *chip, int busw)
2750 {
2751         /* check for proper chip_delay setup, set 20us if not */
2752         if (!chip->chip_delay)
2753                 chip->chip_delay = 20;
2754
2755         /* check, if a user supplied command function given */
2756         if (chip->cmdfunc == NULL)
2757                 chip->cmdfunc = nand_command;
2758
2759         /* check, if a user supplied wait function given */
2760         if (chip->waitfunc == NULL)
2761                 chip->waitfunc = nand_wait;
2762
2763         if (!chip->select_chip)
2764                 chip->select_chip = nand_select_chip;
2765         if (!chip->read_byte)
2766                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2767         if (!chip->read_word)
2768                 chip->read_word = nand_read_word;
2769         if (!chip->block_bad)
2770                 chip->block_bad = nand_block_bad;
2771         if (!chip->block_markbad)
2772                 chip->block_markbad = nand_default_block_markbad;
2773         if (!chip->write_buf)
2774                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2775         if (!chip->read_buf)
2776                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2777         if (!chip->verify_buf)
2778                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2779         if (!chip->scan_bbt)
2780                 chip->scan_bbt = nand_default_bbt;
2781
2782         if (!chip->controller) {
2783                 chip->controller = &chip->hwcontrol;
2784                 spin_lock_init(&chip->controller->lock);
2785                 init_waitqueue_head(&chip->controller->wq);
2786         }
2787
2788 }
2789
2790 /*
2791  * sanitize ONFI strings so we can safely print them
2792  */
2793 static void sanitize_string(uint8_t *s, size_t len)
2794 {
2795         ssize_t i;
2796
2797         /* null terminate */
2798         s[len - 1] = 0;
2799
2800         /* remove non printable chars */
2801         for (i = 0; i < len - 1; i++) {
2802                 if (s[i] < ' ' || s[i] > 127)
2803                         s[i] = '?';
2804         }
2805
2806         /* remove trailing spaces */
2807         strim(s);
2808 }
2809
2810 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2811 {
2812         int i;
2813         while (len--) {
2814                 crc ^= *p++ << 8;
2815                 for (i = 0; i < 8; i++)
2816                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2817         }
2818
2819         return crc;
2820 }
2821
2822 /*
2823  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2824  */
2825 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2826                                         int busw)
2827 {
2828         struct nand_onfi_params *p = &chip->onfi_params;
2829         int i;
2830         int val;
2831
2832         /* try ONFI for unknow chip or LP */
2833         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2834         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2835                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2836                 return 0;
2837
2838         printk(KERN_INFO "ONFI flash detected\n");
2839         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2840         for (i = 0; i < 3; i++) {
2841                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2842                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2843                                 le16_to_cpu(p->crc)) {
2844                         printk(KERN_INFO "ONFI param page %d valid\n", i);
2845                         break;
2846                 }
2847         }
2848
2849         if (i == 3)
2850                 return 0;
2851
2852         /* check version */
2853         val = le16_to_cpu(p->revision);
2854         if (val & (1 << 5))
2855                 chip->onfi_version = 23;
2856         else if (val & (1 << 4))
2857                 chip->onfi_version = 22;
2858         else if (val & (1 << 3))
2859                 chip->onfi_version = 21;
2860         else if (val & (1 << 2))
2861                 chip->onfi_version = 20;
2862         else if (val & (1 << 1))
2863                 chip->onfi_version = 10;
2864         else
2865                 chip->onfi_version = 0;
2866
2867         if (!chip->onfi_version) {
2868                 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2869                                                                 __func__, val);
2870                 return 0;
2871         }
2872
2873         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2874         sanitize_string(p->model, sizeof(p->model));
2875         if (!mtd->name)
2876                 mtd->name = p->model;
2877         mtd->writesize = le32_to_cpu(p->byte_per_page);
2878         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2879         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2880         chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2881         busw = 0;
2882         if (le16_to_cpu(p->features) & 1)
2883                 busw = NAND_BUSWIDTH_16;
2884
2885         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2886         chip->options |= (NAND_NO_READRDY |
2887                         NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2888
2889         return 1;
2890 }
2891
2892 /*
2893  * Get the flash and manufacturer id and lookup if the type is supported
2894  */
2895 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2896                                                   struct nand_chip *chip,
2897                                                   int busw,
2898                                                   int *maf_id, int *dev_id,
2899                                                   struct nand_flash_dev *type)
2900 {
2901         int i, maf_idx;
2902         u8 id_data[8];
2903         int ret;
2904
2905         /* Select the device */
2906         chip->select_chip(mtd, 0);
2907
2908         /*
2909          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2910          * after power-up
2911          */
2912         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2913
2914         /* Send the command for reading device ID */
2915         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2916
2917         /* Read manufacturer and device IDs */
2918         *maf_id = chip->read_byte(mtd);
2919         *dev_id = chip->read_byte(mtd);
2920
2921         /* Try again to make sure, as some systems the bus-hold or other
2922          * interface concerns can cause random data which looks like a
2923          * possibly credible NAND flash to appear. If the two results do
2924          * not match, ignore the device completely.
2925          */
2926
2927         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2928
2929         for (i = 0; i < 2; i++)
2930                 id_data[i] = chip->read_byte(mtd);
2931
2932         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2933                 printk(KERN_INFO "%s: second ID read did not match "
2934                        "%02x,%02x against %02x,%02x\n", __func__,
2935                        *maf_id, *dev_id, id_data[0], id_data[1]);
2936                 return ERR_PTR(-ENODEV);
2937         }
2938
2939         if (!type)
2940                 type = nand_flash_ids;
2941
2942         for (; type->name != NULL; type++)
2943                 if (*dev_id == type->id)
2944                         break;
2945
2946         chip->onfi_version = 0;
2947         if (!type->name || !type->pagesize) {
2948                 /* Check is chip is ONFI compliant */
2949                 ret = nand_flash_detect_onfi(mtd, chip, busw);
2950                 if (ret)
2951                         goto ident_done;
2952         }
2953
2954         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2955
2956         /* Read entire ID string */
2957
2958         for (i = 0; i < 8; i++)
2959                 id_data[i] = chip->read_byte(mtd);
2960
2961         if (!type->name)
2962                 return ERR_PTR(-ENODEV);
2963
2964         if (!mtd->name)
2965                 mtd->name = type->name;
2966
2967         chip->chipsize = (uint64_t)type->chipsize << 20;
2968
2969         if (!type->pagesize && chip->init_size) {
2970                 /* set the pagesize, oobsize, erasesize by the driver*/
2971                 busw = chip->init_size(mtd, chip, id_data);
2972         } else if (!type->pagesize) {
2973                 int extid;
2974                 /* The 3rd id byte holds MLC / multichip data */
2975                 chip->cellinfo = id_data[2];
2976                 /* The 4th id byte is the important one */
2977                 extid = id_data[3];
2978
2979                 /*
2980                  * Field definitions are in the following datasheets:
2981                  * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2982                  * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
2983                  *
2984                  * Check for wraparound + Samsung ID + nonzero 6th byte
2985                  * to decide what to do.
2986                  */
2987                 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2988                                 id_data[0] == NAND_MFR_SAMSUNG &&
2989                                 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2990                                 id_data[5] != 0x00) {
2991                         /* Calc pagesize */
2992                         mtd->writesize = 2048 << (extid & 0x03);
2993                         extid >>= 2;
2994                         /* Calc oobsize */
2995                         switch (extid & 0x03) {
2996                         case 1:
2997                                 mtd->oobsize = 128;
2998                                 break;
2999                         case 2:
3000                                 mtd->oobsize = 218;
3001                                 break;
3002                         case 3:
3003                                 mtd->oobsize = 400;
3004                                 break;
3005                         default:
3006                                 mtd->oobsize = 436;
3007                                 break;
3008                         }
3009                         extid >>= 2;
3010                         /* Calc blocksize */
3011                         mtd->erasesize = (128 * 1024) <<
3012                                 (((extid >> 1) & 0x04) | (extid & 0x03));
3013                         busw = 0;
3014                 } else {
3015                         /* Calc pagesize */
3016                         mtd->writesize = 1024 << (extid & 0x03);
3017                         extid >>= 2;
3018                         /* Calc oobsize */
3019                         mtd->oobsize = (8 << (extid & 0x01)) *
3020                                 (mtd->writesize >> 9);
3021                         extid >>= 2;
3022                         /* Calc blocksize. Blocksize is multiples of 64KiB */
3023                         mtd->erasesize = (64 * 1024) << (extid & 0x03);
3024                         extid >>= 2;
3025                         /* Get buswidth information */
3026                         busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3027                 }
3028         } else {
3029                 /*
3030                  * Old devices have chip data hardcoded in the device id table
3031                  */
3032                 mtd->erasesize = type->erasesize;
3033                 mtd->writesize = type->pagesize;
3034                 mtd->oobsize = mtd->writesize / 32;
3035                 busw = type->options & NAND_BUSWIDTH_16;
3036
3037                 /*
3038                  * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3039                  * some Spansion chips have erasesize that conflicts with size
3040                  * listed in nand_ids table
3041                  * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3042                  */
3043                 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3044                                 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3045                                 id_data[7] == 0x00 && mtd->writesize == 512) {
3046                         mtd->erasesize = 128 * 1024;
3047                         mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3048                 }
3049         }
3050         /* Get chip options, preserve non chip based options */
3051         chip->options &= ~NAND_CHIPOPTIONS_MSK;
3052         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3053
3054         /* Check if chip is a not a samsung device. Do not clear the
3055          * options for chips which are not having an extended id.
3056          */
3057         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3058                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3059 ident_done:
3060
3061         /*
3062          * Set chip as a default. Board drivers can override it, if necessary
3063          */
3064         chip->options |= NAND_NO_AUTOINCR;
3065
3066         /* Try to identify manufacturer */
3067         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3068                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3069                         break;
3070         }
3071
3072         /*
3073          * Check, if buswidth is correct. Hardware drivers should set
3074          * chip correct !
3075          */
3076         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3077                 printk(KERN_INFO "NAND device: Manufacturer ID:"
3078                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3079                        *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3080                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
3081                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3082                        busw ? 16 : 8);
3083                 return ERR_PTR(-EINVAL);
3084         }
3085
3086         /* Calculate the address shift from the page size */
3087         chip->page_shift = ffs(mtd->writesize) - 1;
3088         /* Convert chipsize to number of pages per chip -1. */
3089         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3090
3091         chip->bbt_erase_shift = chip->phys_erase_shift =
3092                 ffs(mtd->erasesize) - 1;
3093         if (chip->chipsize & 0xffffffff)
3094                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3095         else {
3096                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3097                 chip->chip_shift += 32 - 1;
3098         }
3099
3100         chip->badblockbits = 8;
3101
3102         /* Set the bad block position */
3103         if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3104                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3105         else
3106                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3107
3108         /*
3109          * Bad block marker is stored in the last page of each block
3110          * on Samsung and Hynix MLC devices; stored in first two pages
3111          * of each block on Micron devices with 2KiB pages and on
3112          * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3113          * only the first page.
3114          */
3115         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3116                         (*maf_id == NAND_MFR_SAMSUNG ||
3117                          *maf_id == NAND_MFR_HYNIX))
3118                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3119         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3120                                 (*maf_id == NAND_MFR_SAMSUNG ||
3121                                  *maf_id == NAND_MFR_HYNIX ||
3122                                  *maf_id == NAND_MFR_TOSHIBA ||
3123                                  *maf_id == NAND_MFR_AMD)) ||
3124                         (mtd->writesize == 2048 &&
3125                          *maf_id == NAND_MFR_MICRON))
3126                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3127
3128         /* Check for AND chips with 4 page planes */
3129         if (chip->options & NAND_4PAGE_ARRAY)
3130                 chip->erase_cmd = multi_erase_cmd;
3131         else
3132                 chip->erase_cmd = single_erase_cmd;
3133
3134         /* Do not replace user supplied command function ! */
3135         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3136                 chip->cmdfunc = nand_command_lp;
3137
3138         printk(KERN_INFO "NAND device: Manufacturer ID:"
3139                 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3140                 nand_manuf_ids[maf_idx].name,
3141                 chip->onfi_version ? chip->onfi_params.model : type->name);
3142
3143         return type;
3144 }
3145
3146 /**
3147  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3148  * @mtd:             MTD device structure
3149  * @maxchips:        Number of chips to scan for
3150  * @table:           Alternative NAND ID table
3151  *
3152  * This is the first phase of the normal nand_scan() function. It
3153  * reads the flash ID and sets up MTD fields accordingly.
3154  *
3155  * The mtd->owner field must be set to the module of the caller.
3156  */
3157 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3158                     struct nand_flash_dev *table)
3159 {
3160         int i, busw, nand_maf_id, nand_dev_id;
3161         struct nand_chip *chip = mtd->priv;
3162         struct nand_flash_dev *type;
3163
3164         /* Get buswidth to select the correct functions */
3165         busw = chip->options & NAND_BUSWIDTH_16;
3166         /* Set the default functions */
3167         nand_set_defaults(chip, busw);
3168
3169         /* Read the flash type */
3170         type = nand_get_flash_type(mtd, chip, busw,
3171                                 &nand_maf_id, &nand_dev_id, table);
3172
3173         if (IS_ERR(type)) {
3174                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3175                         printk(KERN_WARNING "No NAND device found.\n");
3176                 chip->select_chip(mtd, -1);
3177                 return PTR_ERR(type);
3178         }
3179
3180         /* Check for a chip array */
3181         for (i = 1; i < maxchips; i++) {
3182                 chip->select_chip(mtd, i);
3183                 /* See comment in nand_get_flash_type for reset */
3184                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3185                 /* Send the command for reading device ID */
3186                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3187                 /* Read manufacturer and device IDs */
3188                 if (nand_maf_id != chip->read_byte(mtd) ||
3189                     nand_dev_id != chip->read_byte(mtd))
3190                         break;
3191         }
3192         if (i > 1)
3193                 printk(KERN_INFO "%d NAND chips detected\n", i);
3194
3195         /* Store the number of chips and calc total size for mtd */
3196         chip->numchips = i;
3197         mtd->size = i * chip->chipsize;
3198
3199         return 0;
3200 }
3201 EXPORT_SYMBOL(nand_scan_ident);
3202
3203
3204 /**
3205  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3206  * @mtd:            MTD device structure
3207  *
3208  * This is the second phase of the normal nand_scan() function. It
3209  * fills out all the uninitialized function pointers with the defaults
3210  * and scans for a bad block table if appropriate.
3211  */
3212 int nand_scan_tail(struct mtd_info *mtd)
3213 {
3214         int i;
3215         struct nand_chip *chip = mtd->priv;
3216
3217         if (!(chip->options & NAND_OWN_BUFFERS))
3218                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3219         if (!chip->buffers)
3220                 return -ENOMEM;
3221
3222         /* Set the internal oob buffer location, just after the page data */
3223         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3224
3225         /*
3226          * If no default placement scheme is given, select an appropriate one
3227          */
3228         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3229                 switch (mtd->oobsize) {
3230                 case 8:
3231                         chip->ecc.layout = &nand_oob_8;
3232                         break;
3233                 case 16:
3234                         chip->ecc.layout = &nand_oob_16;
3235                         break;
3236                 case 64:
3237                         chip->ecc.layout = &nand_oob_64;
3238                         break;
3239                 case 128:
3240                         chip->ecc.layout = &nand_oob_128;
3241                         break;
3242                 default:
3243                         printk(KERN_WARNING "No oob scheme defined for "
3244                                "oobsize %d\n", mtd->oobsize);
3245                         BUG();
3246                 }
3247         }
3248
3249         if (!chip->write_page)
3250                 chip->write_page = nand_write_page;
3251
3252         /*
3253          * check ECC mode, default to software if 3byte/512byte hardware ECC is
3254          * selected and we have 256 byte pagesize fallback to software ECC
3255          */
3256
3257         switch (chip->ecc.mode) {
3258         case NAND_ECC_HW_OOB_FIRST:
3259                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3260                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3261                      !chip->ecc.hwctl) {
3262                         printk(KERN_WARNING "No ECC functions supplied; "
3263                                "Hardware ECC not possible\n");
3264                         BUG();
3265                 }
3266                 if (!chip->ecc.read_page)
3267                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3268
3269         case NAND_ECC_HW:
3270                 /* Use standard hwecc read page function ? */
3271                 if (!chip->ecc.read_page)
3272                         chip->ecc.read_page = nand_read_page_hwecc;
3273                 if (!chip->ecc.write_page)
3274                         chip->ecc.write_page = nand_write_page_hwecc;
3275                 if (!chip->ecc.read_page_raw)
3276                         chip->ecc.read_page_raw = nand_read_page_raw;
3277                 if (!chip->ecc.write_page_raw)
3278                         chip->ecc.write_page_raw = nand_write_page_raw;
3279                 if (!chip->ecc.read_oob)
3280                         chip->ecc.read_oob = nand_read_oob_std;
3281                 if (!chip->ecc.write_oob)
3282                         chip->ecc.write_oob = nand_write_oob_std;
3283
3284         case NAND_ECC_HW_SYNDROME:
3285                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3286                      !chip->ecc.hwctl) &&
3287                     (!chip->ecc.read_page ||
3288                      chip->ecc.read_page == nand_read_page_hwecc ||
3289                      !chip->ecc.write_page ||
3290                      chip->ecc.write_page == nand_write_page_hwecc)) {
3291                         printk(KERN_WARNING "No ECC functions supplied; "
3292                                "Hardware ECC not possible\n");
3293                         BUG();
3294                 }
3295                 /* Use standard syndrome read/write page function ? */
3296                 if (!chip->ecc.read_page)
3297                         chip->ecc.read_page = nand_read_page_syndrome;
3298                 if (!chip->ecc.write_page)
3299                         chip->ecc.write_page = nand_write_page_syndrome;
3300                 if (!chip->ecc.read_page_raw)
3301                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3302                 if (!chip->ecc.write_page_raw)
3303                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3304                 if (!chip->ecc.read_oob)
3305                         chip->ecc.read_oob = nand_read_oob_syndrome;
3306                 if (!chip->ecc.write_oob)
3307                         chip->ecc.write_oob = nand_write_oob_syndrome;
3308
3309                 if (mtd->writesize >= chip->ecc.size)
3310                         break;
3311                 printk(KERN_WARNING "%d byte HW ECC not possible on "
3312                        "%d byte page size, fallback to SW ECC\n",
3313                        chip->ecc.size, mtd->writesize);
3314                 chip->ecc.mode = NAND_ECC_SOFT;
3315
3316         case NAND_ECC_SOFT:
3317                 chip->ecc.calculate = nand_calculate_ecc;
3318                 chip->ecc.correct = nand_correct_data;
3319                 chip->ecc.read_page = nand_read_page_swecc;
3320                 chip->ecc.read_subpage = nand_read_subpage;
3321                 chip->ecc.write_page = nand_write_page_swecc;
3322                 chip->ecc.read_page_raw = nand_read_page_raw;
3323                 chip->ecc.write_page_raw = nand_write_page_raw;
3324                 chip->ecc.read_oob = nand_read_oob_std;
3325                 chip->ecc.write_oob = nand_write_oob_std;
3326                 if (!chip->ecc.size)
3327                         chip->ecc.size = 256;
3328                 chip->ecc.bytes = 3;
3329                 break;
3330
3331         case NAND_ECC_SOFT_BCH:
3332                 if (!mtd_nand_has_bch()) {
3333                         printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3334                         BUG();
3335                 }
3336                 chip->ecc.calculate = nand_bch_calculate_ecc;
3337                 chip->ecc.correct = nand_bch_correct_data;
3338                 chip->ecc.read_page = nand_read_page_swecc;
3339                 chip->ecc.read_subpage = nand_read_subpage;
3340                 chip->ecc.write_page = nand_write_page_swecc;
3341                 chip->ecc.read_page_raw = nand_read_page_raw;
3342                 chip->ecc.write_page_raw = nand_write_page_raw;
3343                 chip->ecc.read_oob = nand_read_oob_std;
3344                 chip->ecc.write_oob = nand_write_oob_std;
3345                 /*
3346                  * Board driver should supply ecc.size and ecc.bytes values to
3347                  * select how many bits are correctable; see nand_bch_init()
3348                  * for details.
3349                  * Otherwise, default to 4 bits for large page devices
3350                  */
3351                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3352                         chip->ecc.size = 512;
3353                         chip->ecc.bytes = 7;
3354                 }
3355                 chip->ecc.priv = nand_bch_init(mtd,
3356                                                chip->ecc.size,
3357                                                chip->ecc.bytes,
3358                                                &chip->ecc.layout);
3359                 if (!chip->ecc.priv) {
3360                         printk(KERN_WARNING "BCH ECC initialization failed!\n");
3361                         BUG();
3362                 }
3363                 break;
3364
3365         case NAND_ECC_NONE:
3366                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3367                        "This is not recommended !!\n");
3368                 chip->ecc.read_page = nand_read_page_raw;
3369                 chip->ecc.write_page = nand_write_page_raw;
3370                 chip->ecc.read_oob = nand_read_oob_std;
3371                 chip->ecc.read_page_raw = nand_read_page_raw;
3372                 chip->ecc.write_page_raw = nand_write_page_raw;
3373                 chip->ecc.write_oob = nand_write_oob_std;
3374                 chip->ecc.size = mtd->writesize;
3375                 chip->ecc.bytes = 0;
3376                 break;
3377
3378         default:
3379                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3380                        chip->ecc.mode);
3381                 BUG();
3382         }
3383
3384         /*
3385          * The number of bytes available for a client to place data into
3386          * the out of band area
3387          */
3388         chip->ecc.layout->oobavail = 0;
3389         for (i = 0; chip->ecc.layout->oobfree[i].length
3390                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3391                 chip->ecc.layout->oobavail +=
3392                         chip->ecc.layout->oobfree[i].length;
3393         mtd->oobavail = chip->ecc.layout->oobavail;
3394
3395         /*
3396          * Set the number of read / write steps for one page depending on ECC
3397          * mode
3398          */
3399         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3400         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3401                 printk(KERN_WARNING "Invalid ecc parameters\n");
3402                 BUG();
3403         }
3404         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3405
3406         /*
3407          * Allow subpage writes up to ecc.steps. Not possible for MLC
3408          * FLASH.
3409          */
3410         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3411             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3412                 switch (chip->ecc.steps) {
3413                 case 2:
3414                         mtd->subpage_sft = 1;
3415                         break;
3416                 case 4:
3417                 case 8:
3418                 case 16:
3419                         mtd->subpage_sft = 2;
3420                         break;
3421                 }
3422         }
3423         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3424
3425         /* Initialize state */
3426         chip->state = FL_READY;
3427
3428         /* De-select the device */
3429         chip->select_chip(mtd, -1);
3430
3431         /* Invalidate the pagebuffer reference */
3432         chip->pagebuf = -1;
3433
3434         /* Fill in remaining MTD driver data */
3435         mtd->type = MTD_NANDFLASH;
3436         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3437                                                 MTD_CAP_NANDFLASH;
3438         mtd->erase = nand_erase;
3439         mtd->point = NULL;
3440         mtd->unpoint = NULL;
3441         mtd->read = nand_read;
3442         mtd->write = nand_write;
3443         mtd->panic_write = panic_nand_write;
3444         mtd->read_oob = nand_read_oob;
3445         mtd->write_oob = nand_write_oob;
3446         mtd->sync = nand_sync;
3447         mtd->lock = NULL;
3448         mtd->unlock = NULL;
3449         mtd->suspend = nand_suspend;
3450         mtd->resume = nand_resume;
3451         mtd->block_isbad = nand_block_isbad;
3452         mtd->block_markbad = nand_block_markbad;
3453         mtd->writebufsize = mtd->writesize;
3454
3455         /* propagate ecc.layout to mtd_info */
3456         mtd->ecclayout = chip->ecc.layout;
3457
3458         /* Check, if we should skip the bad block table scan */
3459         if (chip->options & NAND_SKIP_BBTSCAN)
3460                 return 0;
3461
3462         /* Build bad block table */
3463         return chip->scan_bbt(mtd);
3464 }
3465 EXPORT_SYMBOL(nand_scan_tail);
3466
3467 /* is_module_text_address() isn't exported, and it's mostly a pointless
3468  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3469  * to call us from in-kernel code if the core NAND support is modular. */
3470 #ifdef MODULE
3471 #define caller_is_module() (1)
3472 #else
3473 #define caller_is_module() \
3474         is_module_text_address((unsigned long)__builtin_return_address(0))
3475 #endif
3476
3477 /**
3478  * nand_scan - [NAND Interface] Scan for the NAND device
3479  * @mtd:        MTD device structure
3480  * @maxchips:   Number of chips to scan for
3481  *
3482  * This fills out all the uninitialized function pointers
3483  * with the defaults.
3484  * The flash ID is read and the mtd/chip structures are
3485  * filled with the appropriate values.
3486  * The mtd->owner field must be set to the module of the caller
3487  *
3488  */
3489 int nand_scan(struct mtd_info *mtd, int maxchips)
3490 {
3491         int ret;
3492
3493         /* Many callers got this wrong, so check for it for a while... */
3494         if (!mtd->owner && caller_is_module()) {
3495                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3496                                 __func__);
3497                 BUG();
3498         }
3499
3500         ret = nand_scan_ident(mtd, maxchips, NULL);
3501         if (!ret)
3502                 ret = nand_scan_tail(mtd);
3503         return ret;
3504 }
3505 EXPORT_SYMBOL(nand_scan);
3506
3507 /**
3508  * nand_release - [NAND Interface] Free resources held by the NAND device
3509  * @mtd:        MTD device structure
3510 */
3511 void nand_release(struct mtd_info *mtd)
3512 {
3513         struct nand_chip *chip = mtd->priv;
3514
3515         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3516                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3517
3518         mtd_device_unregister(mtd);
3519
3520         /* Free bad block table memory */
3521         kfree(chip->bbt);
3522         if (!(chip->options & NAND_OWN_BUFFERS))
3523                 kfree(chip->buffers);
3524
3525         /* Free bad block descriptor memory */
3526         if (chip->badblock_pattern && chip->badblock_pattern->options
3527                         & NAND_BBT_DYNAMICSTRUCT)
3528                 kfree(chip->badblock_pattern);
3529 }
3530 EXPORT_SYMBOL_GPL(nand_release);
3531
3532 static int __init nand_base_init(void)
3533 {
3534         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3535         return 0;
3536 }
3537
3538 static void __exit nand_base_exit(void)
3539 {
3540         led_trigger_unregister_simple(nand_led_trigger);
3541 }
3542
3543 module_init(nand_base_init);
3544 module_exit(nand_base_exit);
3545
3546 MODULE_LICENSE("GPL");
3547 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3548 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3549 MODULE_DESCRIPTION("Generic NAND flash driver code");