drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ECC support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 /* Define default oob placement schemes for large and small page devices */
  53 static struct nand_ecclayout nand_oob_8 = {
  54         .eccbytes = 3,
  55         .eccpos = {0, 1, 2},
  56         .oobfree = {
  57                 {.offset = 3,
  58                  .length = 2},
  59                 {.offset = 6,
  60                  .length = 2} }
  61 };
  62
  63 static struct nand_ecclayout nand_oob_16 = {
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {
  67                 {.offset = 8,
  68                  . length = 8} }
  69 };
  70
  71 static struct nand_ecclayout nand_oob_64 = {
  72         .eccbytes = 24,
  73         .eccpos = {
  74                    40, 41, 42, 43, 44, 45, 46, 47,
  75                    48, 49, 50, 51, 52, 53, 54, 55,
  76                    56, 57, 58, 59, 60, 61, 62, 63},
  77         .oobfree = {
  78                 {.offset = 2,
  79                  .length = 38} }
  80 };
  81
  82 static struct nand_ecclayout nand_oob_128 = {
  83         .eccbytes = 48,
  84         .eccpos = {
  85                    80, 81, 82, 83, 84, 85, 86, 87,
  86                    88, 89, 90, 91, 92, 93, 94, 95,
  87                    96, 97, 98, 99, 100, 101, 102, 103,
  88                    104, 105, 106, 107, 108, 109, 110, 111,
  89                    112, 113, 114, 115, 116, 117, 118, 119,
  90                    120, 121, 122, 123, 124, 125, 126, 127},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 78} }
  94 };
  95
  96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  97                            int new_state);
  98
  99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 100                              struct mtd_oob_ops *ops);
 101
 102 /*
 103  * For devices which display every fart in the system on a separate LED. Is
 104  * compiled away when LED support is disabled.
 105  */
 106 DEFINE_LED_TRIGGER(nand_led_trigger);
 107
 108 static int check_offs_len(struct mtd_info *mtd,
 109                                         loff_t ofs, uint64_t len)
 110 {
 111         struct nand_chip *chip = mtd->priv;
 112         int ret = 0;
 113
 114         /* Start address must align on block boundary */
 115         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 116                 pr_debug("%s: unaligned address\n", __func__);
 117                 ret = -EINVAL;
 118         }
 119
 120         /* Length must align on block boundary */
 121         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 122                 pr_debug("%s: length not block aligned\n", __func__);
 123                 ret = -EINVAL;
 124         }
 125
 126         /* Do not allow past end of device */
 127         if (ofs + len > mtd->size) {
 128                 pr_debug("%s: past end of device\n", __func__);
 129                 ret = -EINVAL;
 130         }
 131
 132         return ret;
 133 }
 134
 135 /**
 136  * nand_release_device - [GENERIC] release chip
 137  * @mtd: MTD device structure
 138  *
 139  * Deselect, release chip lock and wake up anyone waiting on the device.
 140  */
 141 static void nand_release_device(struct mtd_info *mtd)
 142 {
 143         struct nand_chip *chip = mtd->priv;
 144
 145         /* De-select the NAND device */
 146         chip->select_chip(mtd, -1);
 147
 148         /* Release the controller and the chip */
 149         spin_lock(&chip->controller->lock);
 150         chip->controller->active = NULL;
 151         chip->state = FL_READY;
 152         wake_up(&chip->controller->wq);
 153         spin_unlock(&chip->controller->lock);
 154 }
 155
 156 /**
 157  * nand_read_byte - [DEFAULT] read one byte from the chip
 158  * @mtd: MTD device structure
 159  *
 160  * Default read function for 8bit buswidth
 161  */
 162 static uint8_t nand_read_byte(struct mtd_info *mtd)
 163 {
 164         struct nand_chip *chip = mtd->priv;
 165         return readb(chip->IO_ADDR_R);
 166 }
 167
 168 /**
 169  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 170  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 171  * @mtd: MTD device structure
 172  *
 173  * Default read function for 16bit buswidth with endianness conversion.
 174  *
 175  */
 176 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 177 {
 178         struct nand_chip *chip = mtd->priv;
 179         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 180 }
 181
 182 /**
 183  * nand_read_word - [DEFAULT] read one word from the chip
 184  * @mtd: MTD device structure
 185  *
 186  * Default read function for 16bit buswidth without endianness conversion.
 187  */
 188 static u16 nand_read_word(struct mtd_info *mtd)
 189 {
 190         struct nand_chip *chip = mtd->priv;
 191         return readw(chip->IO_ADDR_R);
 192 }
 193
 194 /**
 195  * nand_select_chip - [DEFAULT] control CE line
 196  * @mtd: MTD device structure
 197  * @chipnr: chipnumber to select, -1 for deselect
 198  *
 199  * Default select function for 1 chip devices.
 200  */
 201 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 202 {
 203         struct nand_chip *chip = mtd->priv;
 204
 205         switch (chipnr) {
 206         case -1:
 207                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 208                 break;
 209         case 0:
 210                 break;
 211
 212         default:
 213                 BUG();
 214         }
 215 }
 216
 217 /**
 218  * nand_write_buf - [DEFAULT] write buffer to chip
 219  * @mtd: MTD device structure
 220  * @buf: data buffer
 221  * @len: number of bytes to write
 222  *
 223  * Default write function for 8bit buswidth.
 224  */
 225 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 226 {
 227         int i;
 228         struct nand_chip *chip = mtd->priv;
 229
 230         for (i = 0; i < len; i++)
 231                 writeb(buf[i], chip->IO_ADDR_W);
 232 }
 233
 234 /**
 235  * nand_read_buf - [DEFAULT] read chip data into buffer
 236  * @mtd: MTD device structure
 237  * @buf: buffer to store date
 238  * @len: number of bytes to read
 239  *
 240  * Default read function for 8bit buswidth.
 241  */
 242 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 243 {
 244         int i;
 245         struct nand_chip *chip = mtd->priv;
 246
 247         for (i = 0; i < len; i++)
 248                 buf[i] = readb(chip->IO_ADDR_R);
 249 }
 250
 251 /**
 252  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 253  * @mtd: MTD device structure
 254  * @buf: buffer containing the data to compare
 255  * @len: number of bytes to compare
 256  *
 257  * Default verify function for 8bit buswidth.
 258  */
 259 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 260 {
 261         int i;
 262         struct nand_chip *chip = mtd->priv;
 263
 264         for (i = 0; i < len; i++)
 265                 if (buf[i] != readb(chip->IO_ADDR_R))
 266                         return -EFAULT;
 267         return 0;
 268 }
 269
 270 /**
 271  * nand_write_buf16 - [DEFAULT] write buffer to chip
 272  * @mtd: MTD device structure
 273  * @buf: data buffer
 274  * @len: number of bytes to write
 275  *
 276  * Default write function for 16bit buswidth.
 277  */
 278 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 279 {
 280         int i;
 281         struct nand_chip *chip = mtd->priv;
 282         u16 *p = (u16 *) buf;
 283         len >>= 1;
 284
 285         for (i = 0; i < len; i++)
 286                 writew(p[i], chip->IO_ADDR_W);
 287
 288 }
 289
 290 /**
 291  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 292  * @mtd: MTD device structure
 293  * @buf: buffer to store date
 294  * @len: number of bytes to read
 295  *
 296  * Default read function for 16bit buswidth.
 297  */
 298 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 299 {
 300         int i;
 301         struct nand_chip *chip = mtd->priv;
 302         u16 *p = (u16 *) buf;
 303         len >>= 1;
 304
 305         for (i = 0; i < len; i++)
 306                 p[i] = readw(chip->IO_ADDR_R);
 307 }
 308
 309 /**
 310  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 311  * @mtd: MTD device structure
 312  * @buf: buffer containing the data to compare
 313  * @len: number of bytes to compare
 314  *
 315  * Default verify function for 16bit buswidth.
 316  */
 317 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 318 {
 319         int i;
 320         struct nand_chip *chip = mtd->priv;
 321         u16 *p = (u16 *) buf;
 322         len >>= 1;
 323
 324         for (i = 0; i < len; i++)
 325                 if (p[i] != readw(chip->IO_ADDR_R))
 326                         return -EFAULT;
 327
 328         return 0;
 329 }
 330
 331 /**
 332  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 333  * @mtd: MTD device structure
 334  * @ofs: offset from device start
 335  * @getchip: 0, if the chip is already selected
 336  *
 337  * Check, if the block is bad.
 338  */
 339 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 340 {
 341         int page, chipnr, res = 0;
 342         struct nand_chip *chip = mtd->priv;
 343         u16 bad;
 344
 345         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 346                 ofs += mtd->erasesize - mtd->writesize;
 347
 348         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 349
 350         if (getchip) {
 351                 chipnr = (int)(ofs >> chip->chip_shift);
 352
 353                 nand_get_device(chip, mtd, FL_READING);
 354
 355                 /* Select the NAND device */
 356                 chip->select_chip(mtd, chipnr);
 357         }
 358
 359         if (chip->options & NAND_BUSWIDTH_16) {
 360                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 361                               page);
 362                 bad = cpu_to_le16(chip->read_word(mtd));
 363                 if (chip->badblockpos & 0x1)
 364                         bad >>= 8;
 365                 else
 366                         bad &= 0xFF;
 367         } else {
 368                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 369                 bad = chip->read_byte(mtd);
 370         }
 371
 372         if (likely(chip->badblockbits == 8))
 373                 res = bad != 0xFF;
 374         else
 375                 res = hweight8(bad) < chip->badblockbits;
 376
 377         if (getchip)
 378                 nand_release_device(mtd);
 379
 380         return res;
 381 }
 382
 383 /**
 384  * nand_default_block_markbad - [DEFAULT] mark a block bad
 385  * @mtd: MTD device structure
 386  * @ofs: offset from device start
 387  *
 388  * This is the default implementation, which can be overridden by a hardware
 389  * specific driver.
 390 */
 391 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 392 {
 393         struct nand_chip *chip = mtd->priv;
 394         uint8_t buf[2] = { 0, 0 };
 395         int block, ret, i = 0;
 396
 397         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 398                 ofs += mtd->erasesize - mtd->writesize;
 399
 400         /* Get block number */
 401         block = (int)(ofs >> chip->bbt_erase_shift);
 402         if (chip->bbt)
 403                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 404
 405         /* Do we have a flash based bad block table? */
 406         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 407                 ret = nand_update_bbt(mtd, ofs);
 408         else {
 409                 struct mtd_oob_ops ops;
 410
 411                 nand_get_device(chip, mtd, FL_WRITING);
 412
 413                 /*
 414                  * Write to first two pages if necessary. If we write to more
 415                  * than one location, the first error encountered quits the
 416                  * procedure. We write two bytes per location, so we dont have
 417                  * to mess with 16 bit access.
 418                  */
 419                 ops.len = ops.ooblen = 2;
 420                 ops.datbuf = NULL;
 421                 ops.oobbuf = buf;
 422                 ops.ooboffs = chip->badblockpos & ~0x01;
 423                 ops.mode = MTD_OPS_PLACE_OOB;
 424                 do {
 425                         ret = nand_do_write_oob(mtd, ofs, &ops);
 426
 427                         i++;
 428                         ofs += mtd->writesize;
 429                 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
 430                                 i < 2);
 431
 432                 nand_release_device(mtd);
 433         }
 434         if (!ret)
 435                 mtd->ecc_stats.badblocks++;
 436
 437         return ret;
 438 }
 439
 440 /**
 441  * nand_check_wp - [GENERIC] check if the chip is write protected
 442  * @mtd: MTD device structure
 443  *
 444  * Check, if the device is write protected. The function expects, that the
 445  * device is already selected.
 446  */
 447 static int nand_check_wp(struct mtd_info *mtd)
 448 {
 449         struct nand_chip *chip = mtd->priv;
 450
 451         /* Broken xD cards report WP despite being writable */
 452         if (chip->options & NAND_BROKEN_XD)
 453                 return 0;
 454
 455         /* Check the WP bit */
 456         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 457         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 458 }
 459
 460 /**
 461  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 462  * @mtd: MTD device structure
 463  * @ofs: offset from device start
 464  * @getchip: 0, if the chip is already selected
 465  * @allowbbt: 1, if its allowed to access the bbt area
 466  *
 467  * Check, if the block is bad. Either by reading the bad block table or
 468  * calling of the scan function.
 469  */
 470 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 471                                int allowbbt)
 472 {
 473         struct nand_chip *chip = mtd->priv;
 474
 475         if (!chip->bbt)
 476                 return chip->block_bad(mtd, ofs, getchip);
 477
 478         /* Return info from the table */
 479         return nand_isbad_bbt(mtd, ofs, allowbbt);
 480 }
 481
 482 /**
 483  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 484  * @mtd: MTD device structure
 485  * @timeo: Timeout
 486  *
 487  * Helper function for nand_wait_ready used when needing to wait in interrupt
 488  * context.
 489  */
 490 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 491 {
 492         struct nand_chip *chip = mtd->priv;
 493         int i;
 494
 495         /* Wait for the device to get ready */
 496         for (i = 0; i < timeo; i++) {
 497                 if (chip->dev_ready(mtd))
 498                         break;
 499                 touch_softlockup_watchdog();
 500                 mdelay(1);
 501         }
 502 }
 503
 504 /* Wait for the ready pin, after a command. The timeout is caught later. */
 505 void nand_wait_ready(struct mtd_info *mtd)
 506 {
 507         struct nand_chip *chip = mtd->priv;
 508         unsigned long timeo = jiffies + 2;
 509
 510         /* 400ms timeout */
 511         if (in_interrupt() || oops_in_progress)
 512                 return panic_nand_wait_ready(mtd, 400);
 513
 514         led_trigger_event(nand_led_trigger, LED_FULL);
 515         /* Wait until command is processed or timeout occurs */
 516         do {
 517                 if (chip->dev_ready(mtd))
 518                         break;
 519                 touch_softlockup_watchdog();
 520         } while (time_before(jiffies, timeo));
 521         led_trigger_event(nand_led_trigger, LED_OFF);
 522 }
 523 EXPORT_SYMBOL_GPL(nand_wait_ready);
 524
 525 /**
 526  * nand_command - [DEFAULT] Send command to NAND device
 527  * @mtd: MTD device structure
 528  * @command: the command to be sent
 529  * @column: the column address for this command, -1 if none
 530  * @page_addr: the page address for this command, -1 if none
 531  *
 532  * Send command to NAND device. This function is used for small page devices
 533  * (256/512 Bytes per page).
 534  */
 535 static void nand_command(struct mtd_info *mtd, unsigned int command,
 536                          int column, int page_addr)
 537 {
 538         register struct nand_chip *chip = mtd->priv;
 539         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 540
 541         /* Write out the command to the device */
 542         if (command == NAND_CMD_SEQIN) {
 543                 int readcmd;
 544
 545                 if (column >= mtd->writesize) {
 546                         /* OOB area */
 547                         column -= mtd->writesize;
 548                         readcmd = NAND_CMD_READOOB;
 549                 } else if (column < 256) {
 550                         /* First 256 bytes --> READ0 */
 551                         readcmd = NAND_CMD_READ0;
 552                 } else {
 553                         column -= 256;
 554                         readcmd = NAND_CMD_READ1;
 555                 }
 556                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 557                 ctrl &= ~NAND_CTRL_CHANGE;
 558         }
 559         chip->cmd_ctrl(mtd, command, ctrl);
 560
 561         /* Address cycle, when necessary */
 562         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 563         /* Serially input address */
 564         if (column != -1) {
 565                 /* Adjust columns for 16 bit buswidth */
 566                 if (chip->options & NAND_BUSWIDTH_16)
 567                         column >>= 1;
 568                 chip->cmd_ctrl(mtd, column, ctrl);
 569                 ctrl &= ~NAND_CTRL_CHANGE;
 570         }
 571         if (page_addr != -1) {
 572                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 573                 ctrl &= ~NAND_CTRL_CHANGE;
 574                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 575                 /* One more address cycle for devices > 32MiB */
 576                 if (chip->chipsize > (32 << 20))
 577                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 578         }
 579         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 580
 581         /*
 582          * Program and erase have their own busy handlers status and sequential
 583          * in needs no delay
 584          */
 585         switch (command) {
 586
 587         case NAND_CMD_PAGEPROG:
 588         case NAND_CMD_ERASE1:
 589         case NAND_CMD_ERASE2:
 590         case NAND_CMD_SEQIN:
 591         case NAND_CMD_STATUS:
 592                 return;
 593
 594         case NAND_CMD_RESET:
 595                 if (chip->dev_ready)
 596                         break;
 597                 udelay(chip->chip_delay);
 598                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 599                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 600                 chip->cmd_ctrl(mtd,
 601                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 602                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 603                                 ;
 604                 return;
 605
 606                 /* This applies to read commands */
 607         default:
 608                 /*
 609                  * If we don't have access to the busy pin, we apply the given
 610                  * command delay
 611                  */
 612                 if (!chip->dev_ready) {
 613                         udelay(chip->chip_delay);
 614                         return;
 615                 }
 616         }
 617         /*
 618          * Apply this short delay always to ensure that we do wait tWB in
 619          * any case on any machine.
 620          */
 621         ndelay(100);
 622
 623         nand_wait_ready(mtd);
 624 }
 625
 626 /**
 627  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 628  * @mtd: MTD device structure
 629  * @command: the command to be sent
 630  * @column: the column address for this command, -1 if none
 631  * @page_addr: the page address for this command, -1 if none
 632  *
 633  * Send command to NAND device. This is the version for the new large page
 634  * devices. We don't have the separate regions as we have in the small page
 635  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 636  */
 637 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 638                             int column, int page_addr)
 639 {
 640         register struct nand_chip *chip = mtd->priv;
 641
 642         /* Emulate NAND_CMD_READOOB */
 643         if (command == NAND_CMD_READOOB) {
 644                 column += mtd->writesize;
 645                 command = NAND_CMD_READ0;
 646         }
 647
 648         /* Command latch cycle */
 649         chip->cmd_ctrl(mtd, command & 0xff,
 650                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 651
 652         if (column != -1 || page_addr != -1) {
 653                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 654
 655                 /* Serially input address */
 656                 if (column != -1) {
 657                         /* Adjust columns for 16 bit buswidth */
 658                         if (chip->options & NAND_BUSWIDTH_16)
 659                                 column >>= 1;
 660                         chip->cmd_ctrl(mtd, column, ctrl);
 661                         ctrl &= ~NAND_CTRL_CHANGE;
 662                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 663                 }
 664                 if (page_addr != -1) {
 665                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 666                         chip->cmd_ctrl(mtd, page_addr >> 8,
 667                                        NAND_NCE | NAND_ALE);
 668                         /* One more address cycle for devices > 128MiB */
 669                         if (chip->chipsize > (128 << 20))
 670                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 671                                                NAND_NCE | NAND_ALE);
 672                 }
 673         }
 674         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 675
 676         /*
 677          * Program and erase have their own busy handlers status, sequential
 678          * in, and deplete1 need no delay.
 679          */
 680         switch (command) {
 681
 682         case NAND_CMD_CACHEDPROG:
 683         case NAND_CMD_PAGEPROG:
 684         case NAND_CMD_ERASE1:
 685         case NAND_CMD_ERASE2:
 686         case NAND_CMD_SEQIN:
 687         case NAND_CMD_RNDIN:
 688         case NAND_CMD_STATUS:
 689         case NAND_CMD_DEPLETE1:
 690                 return;
 691
 692         case NAND_CMD_STATUS_ERROR:
 693         case NAND_CMD_STATUS_ERROR0:
 694         case NAND_CMD_STATUS_ERROR1:
 695         case NAND_CMD_STATUS_ERROR2:
 696         case NAND_CMD_STATUS_ERROR3:
 697                 /* Read error status commands require only a short delay */
 698                 udelay(chip->chip_delay);
 699                 return;
 700
 701         case NAND_CMD_RESET:
 702                 if (chip->dev_ready)
 703                         break;
 704                 udelay(chip->chip_delay);
 705                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 706                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 707                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 708                                NAND_NCE | NAND_CTRL_CHANGE);
 709                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 710                                 ;
 711                 return;
 712
 713         case NAND_CMD_RNDOUT:
 714                 /* No ready / busy check necessary */
 715                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 716                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 717                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 718                                NAND_NCE | NAND_CTRL_CHANGE);
 719                 return;
 720
 721         case NAND_CMD_READ0:
 722                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 723                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 724                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 725                                NAND_NCE | NAND_CTRL_CHANGE);
 726
 727                 /* This applies to read commands */
 728         default:
 729                 /*
 730                  * If we don't have access to the busy pin, we apply the given
 731                  * command delay.
 732                  */
 733                 if (!chip->dev_ready) {
 734                         udelay(chip->chip_delay);
 735                         return;
 736                 }
 737         }
 738
 739         /*
 740          * Apply this short delay always to ensure that we do wait tWB in
 741          * any case on any machine.
 742          */
 743         ndelay(100);
 744
 745         nand_wait_ready(mtd);
 746 }
 747
 748 /**
 749  * panic_nand_get_device - [GENERIC] Get chip for selected access
 750  * @chip: the nand chip descriptor
 751  * @mtd: MTD device structure
 752  * @new_state: the state which is requested
 753  *
 754  * Used when in panic, no locks are taken.
 755  */
 756 static void panic_nand_get_device(struct nand_chip *chip,
 757                       struct mtd_info *mtd, int new_state)
 758 {
 759         /* Hardware controller shared among independent devices */
 760         chip->controller->active = chip;
 761         chip->state = new_state;
 762 }
 763
 764 /**
 765  * nand_get_device - [GENERIC] Get chip for selected access
 766  * @chip: the nand chip descriptor
 767  * @mtd: MTD device structure
 768  * @new_state: the state which is requested
 769  *
 770  * Get the device and lock it for exclusive access
 771  */
 772 static int
 773 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 774 {
 775         spinlock_t *lock = &chip->controller->lock;
 776         wait_queue_head_t *wq = &chip->controller->wq;
 777         DECLARE_WAITQUEUE(wait, current);
 778 retry:
 779         spin_lock(lock);
 780
 781         /* Hardware controller shared among independent devices */
 782         if (!chip->controller->active)
 783                 chip->controller->active = chip;
 784
 785         if (chip->controller->active == chip && chip->state == FL_READY) {
 786                 chip->state = new_state;
 787                 spin_unlock(lock);
 788                 return 0;
 789         }
 790         if (new_state == FL_PM_SUSPENDED) {
 791                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 792                         chip->state = FL_PM_SUSPENDED;
 793                         spin_unlock(lock);
 794                         return 0;
 795                 }
 796         }
 797         set_current_state(TASK_UNINTERRUPTIBLE);
 798         add_wait_queue(wq, &wait);
 799         spin_unlock(lock);
 800         schedule();
 801         remove_wait_queue(wq, &wait);
 802         goto retry;
 803 }
 804
 805 /**
 806  * panic_nand_wait - [GENERIC] wait until the command is done
 807  * @mtd: MTD device structure
 808  * @chip: NAND chip structure
 809  * @timeo: timeout
 810  *
 811  * Wait for command done. This is a helper function for nand_wait used when
 812  * we are in interrupt context. May happen when in panic and trying to write
 813  * an oops through mtdoops.
 814  */
 815 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 816                             unsigned long timeo)
 817 {
 818         int i;
 819         for (i = 0; i < timeo; i++) {
 820                 if (chip->dev_ready) {
 821                         if (chip->dev_ready(mtd))
 822                                 break;
 823                 } else {
 824                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 825                                 break;
 826                 }
 827                 mdelay(1);
 828         }
 829 }
 830
 831 /**
 832  * nand_wait - [DEFAULT] wait until the command is done
 833  * @mtd: MTD device structure
 834  * @chip: NAND chip structure
 835  *
 836  * Wait for command done. This applies to erase and program only. Erase can
 837  * take up to 400ms and program up to 20ms according to general NAND and
 838  * SmartMedia specs.
 839  */
 840 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 841 {
 842
 843         unsigned long timeo = jiffies;
 844         int status, state = chip->state;
 845
 846         if (state == FL_ERASING)
 847                 timeo += (HZ * 400) / 1000;
 848         else
 849                 timeo += (HZ * 20) / 1000;
 850
 851         led_trigger_event(nand_led_trigger, LED_FULL);
 852
 853         /*
 854          * Apply this short delay always to ensure that we do wait tWB in any
 855          * case on any machine.
 856          */
 857         ndelay(100);
 858
 859         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 860                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 861         else
 862                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 863
 864         if (in_interrupt() || oops_in_progress)
 865                 panic_nand_wait(mtd, chip, timeo);
 866         else {
 867                 while (time_before(jiffies, timeo)) {
 868                         if (chip->dev_ready) {
 869                                 if (chip->dev_ready(mtd))
 870                                         break;
 871                         } else {
 872                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 873                                         break;
 874                         }
 875                         cond_resched();
 876                 }
 877         }
 878         led_trigger_event(nand_led_trigger, LED_OFF);
 879
 880         status = (int)chip->read_byte(mtd);
 881         return status;
 882 }
 883
 884 /**
 885  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 886  * @mtd: mtd info
 887  * @ofs: offset to start unlock from
 888  * @len: length to unlock
 889  * @invert: when = 0, unlock the range of blocks within the lower and
 890  *                    upper boundary address
 891  *          when = 1, unlock the range of blocks outside the boundaries
 892  *                    of the lower and upper boundary address
 893  *
 894  * Returs unlock status.
 895  */
 896 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 897                                         uint64_t len, int invert)
 898 {
 899         int ret = 0;
 900         int status, page;
 901         struct nand_chip *chip = mtd->priv;
 902
 903         /* Submit address of first page to unlock */
 904         page = ofs >> chip->page_shift;
 905         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 906
 907         /* Submit address of last page to unlock */
 908         page = (ofs + len) >> chip->page_shift;
 909         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 910                                 (page | invert) & chip->pagemask);
 911
 912         /* Call wait ready function */
 913         status = chip->waitfunc(mtd, chip);
 914         /* See if device thinks it succeeded */
 915         if (status & 0x01) {
 916                 pr_debug("%s: error status = 0x%08x\n",
 917                                         __func__, status);
 918                 ret = -EIO;
 919         }
 920
 921         return ret;
 922 }
 923
 924 /**
 925  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 926  * @mtd: mtd info
 927  * @ofs: offset to start unlock from
 928  * @len: length to unlock
 929  *
 930  * Returns unlock status.
 931  */
 932 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 933 {
 934         int ret = 0;
 935         int chipnr;
 936         struct nand_chip *chip = mtd->priv;
 937
 938         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 939                         __func__, (unsigned long long)ofs, len);
 940
 941         if (check_offs_len(mtd, ofs, len))
 942                 ret = -EINVAL;
 943
 944         /* Align to last block address if size addresses end of the device */
 945         if (ofs + len == mtd->size)
 946                 len -= mtd->erasesize;
 947
 948         nand_get_device(chip, mtd, FL_UNLOCKING);
 949
 950         /* Shift to get chip number */
 951         chipnr = ofs >> chip->chip_shift;
 952
 953         chip->select_chip(mtd, chipnr);
 954
 955         /* Check, if it is write protected */
 956         if (nand_check_wp(mtd)) {
 957                 pr_debug("%s: device is write protected!\n",
 958                                         __func__);
 959                 ret = -EIO;
 960                 goto out;
 961         }
 962
 963         ret = __nand_unlock(mtd, ofs, len, 0);
 964
 965 out:
 966         nand_release_device(mtd);
 967
 968         return ret;
 969 }
 970 EXPORT_SYMBOL(nand_unlock);
 971
 972 /**
 973  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 974  * @mtd: mtd info
 975  * @ofs: offset to start unlock from
 976  * @len: length to unlock
 977  *
 978  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 979  * have this feature, but it allows only to lock all blocks, not for specified
 980  * range for block. Implementing 'lock' feature by making use of 'unlock', for
 981  * now.
 982  *
 983  * Returns lock status.
 984  */
 985 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 986 {
 987         int ret = 0;
 988         int chipnr, status, page;
 989         struct nand_chip *chip = mtd->priv;
 990
 991         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 992                         __func__, (unsigned long long)ofs, len);
 993
 994         if (check_offs_len(mtd, ofs, len))
 995                 ret = -EINVAL;
 996
 997         nand_get_device(chip, mtd, FL_LOCKING);
 998
 999         /* Shift to get chip number */
1000         chipnr = ofs >> chip->chip_shift;
1001
1002         chip->select_chip(mtd, chipnr);
1003
1004         /* Check, if it is write protected */
1005         if (nand_check_wp(mtd)) {
1006                 pr_debug("%s: device is write protected!\n",
1007                                         __func__);
1008                 status = MTD_ERASE_FAILED;
1009                 ret = -EIO;
1010                 goto out;
1011         }
1012
1013         /* Submit address of first page to lock */
1014         page = ofs >> chip->page_shift;
1015         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1016
1017         /* Call wait ready function */
1018         status = chip->waitfunc(mtd, chip);
1019         /* See if device thinks it succeeded */
1020         if (status & 0x01) {
1021                 pr_debug("%s: error status = 0x%08x\n",
1022                                         __func__, status);
1023                 ret = -EIO;
1024                 goto out;
1025         }
1026
1027         ret = __nand_unlock(mtd, ofs, len, 0x1);
1028
1029 out:
1030         nand_release_device(mtd);
1031
1032         return ret;
1033 }
1034 EXPORT_SYMBOL(nand_lock);
1035
1036 /**
1037  * nand_read_page_raw - [INTERN] read raw page data without ecc
1038  * @mtd: mtd info structure
1039  * @chip: nand chip info structure
1040  * @buf: buffer to store read data
1041  * @page: page number to read
1042  *
1043  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1044  */
1045 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1046                               uint8_t *buf, int page)
1047 {
1048         chip->read_buf(mtd, buf, mtd->writesize);
1049         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1050         return 0;
1051 }
1052
1053 /**
1054  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1055  * @mtd: mtd info structure
1056  * @chip: nand chip info structure
1057  * @buf: buffer to store read data
1058  * @page: page number to read
1059  *
1060  * We need a special oob layout and handling even when OOB isn't used.
1061  */
1062 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1063                                         struct nand_chip *chip,
1064                                         uint8_t *buf, int page)
1065 {
1066         int eccsize = chip->ecc.size;
1067         int eccbytes = chip->ecc.bytes;
1068         uint8_t *oob = chip->oob_poi;
1069         int steps, size;
1070
1071         for (steps = chip->ecc.steps; steps > 0; steps--) {
1072                 chip->read_buf(mtd, buf, eccsize);
1073                 buf += eccsize;
1074
1075                 if (chip->ecc.prepad) {
1076                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1077                         oob += chip->ecc.prepad;
1078                 }
1079
1080                 chip->read_buf(mtd, oob, eccbytes);
1081                 oob += eccbytes;
1082
1083                 if (chip->ecc.postpad) {
1084                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1085                         oob += chip->ecc.postpad;
1086                 }
1087         }
1088
1089         size = mtd->oobsize - (oob - chip->oob_poi);
1090         if (size)
1091                 chip->read_buf(mtd, oob, size);
1092
1093         return 0;
1094 }
1095
1096 /**
1097  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1098  * @mtd: mtd info structure
1099  * @chip: nand chip info structure
1100  * @buf: buffer to store read data
1101  * @page: page number to read
1102  */
1103 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1104                                 uint8_t *buf, int page)
1105 {
1106         int i, eccsize = chip->ecc.size;
1107         int eccbytes = chip->ecc.bytes;
1108         int eccsteps = chip->ecc.steps;
1109         uint8_t *p = buf;
1110         uint8_t *ecc_calc = chip->buffers->ecccalc;
1111         uint8_t *ecc_code = chip->buffers->ecccode;
1112         uint32_t *eccpos = chip->ecc.layout->eccpos;
1113
1114         chip->ecc.read_page_raw(mtd, chip, buf, page);
1115
1116         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1117                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1118
1119         for (i = 0; i < chip->ecc.total; i++)
1120                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1121
1122         eccsteps = chip->ecc.steps;
1123         p = buf;
1124
1125         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1126                 int stat;
1127
1128                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1129                 if (stat < 0)
1130                         mtd->ecc_stats.failed++;
1131                 else
1132                         mtd->ecc_stats.corrected += stat;
1133         }
1134         return 0;
1135 }
1136
1137 /**
1138  * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1139  * @mtd: mtd info structure
1140  * @chip: nand chip info structure
1141  * @data_offs: offset of requested data within the page
1142  * @readlen: data length
1143  * @bufpoi: buffer to store read data
1144  */
1145 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1146                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1147 {
1148         int start_step, end_step, num_steps;
1149         uint32_t *eccpos = chip->ecc.layout->eccpos;
1150         uint8_t *p;
1151         int data_col_addr, i, gaps = 0;
1152         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1153         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1154         int index = 0;
1155
1156         /* Column address within the page aligned to ECC size (256bytes) */
1157         start_step = data_offs / chip->ecc.size;
1158         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1159         num_steps = end_step - start_step + 1;
1160
1161         /* Data size aligned to ECC ecc.size */
1162         datafrag_len = num_steps * chip->ecc.size;
1163         eccfrag_len = num_steps * chip->ecc.bytes;
1164
1165         data_col_addr = start_step * chip->ecc.size;
1166         /* If we read not a page aligned data */
1167         if (data_col_addr != 0)
1168                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1169
1170         p = bufpoi + data_col_addr;
1171         chip->read_buf(mtd, p, datafrag_len);
1172
1173         /* Calculate ECC */
1174         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1175                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1176
1177         /*
1178          * The performance is faster if we position offsets according to
1179          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1180          */
1181         for (i = 0; i < eccfrag_len - 1; i++) {
1182                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1183                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1184                         gaps = 1;
1185                         break;
1186                 }
1187         }
1188         if (gaps) {
1189                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1190                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1191         } else {
1192                 /*
1193                  * Send the command to read the particular ECC bytes take care
1194                  * about buswidth alignment in read_buf.
1195                  */
1196                 index = start_step * chip->ecc.bytes;
1197
1198                 aligned_pos = eccpos[index] & ~(busw - 1);
1199                 aligned_len = eccfrag_len;
1200                 if (eccpos[index] & (busw - 1))
1201                         aligned_len++;
1202                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1203                         aligned_len++;
1204
1205                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1206                                         mtd->writesize + aligned_pos, -1);
1207                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1208         }
1209
1210         for (i = 0; i < eccfrag_len; i++)
1211                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1212
1213         p = bufpoi + data_col_addr;
1214         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1215                 int stat;
1216
1217                 stat = chip->ecc.correct(mtd, p,
1218                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1219                 if (stat < 0)
1220                         mtd->ecc_stats.failed++;
1221                 else
1222                         mtd->ecc_stats.corrected += stat;
1223         }
1224         return 0;
1225 }
1226
1227 /**
1228  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1229  * @mtd: mtd info structure
1230  * @chip: nand chip info structure
1231  * @buf: buffer to store read data
1232  * @page: page number to read
1233  *
1234  * Not for syndrome calculating ECC controllers which need a special oob layout.
1235  */
1236 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1237                                 uint8_t *buf, int page)
1238 {
1239         int i, eccsize = chip->ecc.size;
1240         int eccbytes = chip->ecc.bytes;
1241         int eccsteps = chip->ecc.steps;
1242         uint8_t *p = buf;
1243         uint8_t *ecc_calc = chip->buffers->ecccalc;
1244         uint8_t *ecc_code = chip->buffers->ecccode;
1245         uint32_t *eccpos = chip->ecc.layout->eccpos;
1246
1247         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1248                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1249                 chip->read_buf(mtd, p, eccsize);
1250                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1251         }
1252         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1253
1254         for (i = 0; i < chip->ecc.total; i++)
1255                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1256
1257         eccsteps = chip->ecc.steps;
1258         p = buf;
1259
1260         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1261                 int stat;
1262
1263                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1264                 if (stat < 0)
1265                         mtd->ecc_stats.failed++;
1266                 else
1267                         mtd->ecc_stats.corrected += stat;
1268         }
1269         return 0;
1270 }
1271
1272 /**
1273  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1274  * @mtd: mtd info structure
1275  * @chip: nand chip info structure
1276  * @buf: buffer to store read data
1277  * @page: page number to read
1278  *
1279  * Hardware ECC for large page chips, require OOB to be read first. For this
1280  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1281  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1282  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1283  * the data area, by overwriting the NAND manufacturer bad block markings.
1284  */
1285 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1286         struct nand_chip *chip, uint8_t *buf, int page)
1287 {
1288         int i, eccsize = chip->ecc.size;
1289         int eccbytes = chip->ecc.bytes;
1290         int eccsteps = chip->ecc.steps;
1291         uint8_t *p = buf;
1292         uint8_t *ecc_code = chip->buffers->ecccode;
1293         uint32_t *eccpos = chip->ecc.layout->eccpos;
1294         uint8_t *ecc_calc = chip->buffers->ecccalc;
1295
1296         /* Read the OOB area first */
1297         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1298         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1299         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1300
1301         for (i = 0; i < chip->ecc.total; i++)
1302                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1303
1304         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1305                 int stat;
1306
1307                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1308                 chip->read_buf(mtd, p, eccsize);
1309                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1310
1311                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1312                 if (stat < 0)
1313                         mtd->ecc_stats.failed++;
1314                 else
1315                         mtd->ecc_stats.corrected += stat;
1316         }
1317         return 0;
1318 }
1319
1320 /**
1321  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1322  * @mtd: mtd info structure
1323  * @chip: nand chip info structure
1324  * @buf: buffer to store read data
1325  * @page: page number to read
1326  *
1327  * The hw generator calculates the error syndrome automatically. Therefore we
1328  * need a special oob layout and handling.
1329  */
1330 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1331                                    uint8_t *buf, int page)
1332 {
1333         int i, eccsize = chip->ecc.size;
1334         int eccbytes = chip->ecc.bytes;
1335         int eccsteps = chip->ecc.steps;
1336         uint8_t *p = buf;
1337         uint8_t *oob = chip->oob_poi;
1338
1339         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1340                 int stat;
1341
1342                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1343                 chip->read_buf(mtd, p, eccsize);
1344
1345                 if (chip->ecc.prepad) {
1346                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1347                         oob += chip->ecc.prepad;
1348                 }
1349
1350                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1351                 chip->read_buf(mtd, oob, eccbytes);
1352                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1353
1354                 if (stat < 0)
1355                         mtd->ecc_stats.failed++;
1356                 else
1357                         mtd->ecc_stats.corrected += stat;
1358
1359                 oob += eccbytes;
1360
1361                 if (chip->ecc.postpad) {
1362                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1363                         oob += chip->ecc.postpad;
1364                 }
1365         }
1366
1367         /* Calculate remaining oob bytes */
1368         i = mtd->oobsize - (oob - chip->oob_poi);
1369         if (i)
1370                 chip->read_buf(mtd, oob, i);
1371
1372         return 0;
1373 }
1374
1375 /**
1376  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1377  * @chip: nand chip structure
1378  * @oob: oob destination address
1379  * @ops: oob ops structure
1380  * @len: size of oob to transfer
1381  */
1382 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1383                                   struct mtd_oob_ops *ops, size_t len)
1384 {
1385         switch (ops->mode) {
1386
1387         case MTD_OPS_PLACE_OOB:
1388         case MTD_OPS_RAW:
1389                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1390                 return oob + len;
1391
1392         case MTD_OPS_AUTO_OOB: {
1393                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1394                 uint32_t boffs = 0, roffs = ops->ooboffs;
1395                 size_t bytes = 0;
1396
1397                 for (; free->length && len; free++, len -= bytes) {
1398                         /* Read request not from offset 0? */
1399                         if (unlikely(roffs)) {
1400                                 if (roffs >= free->length) {
1401                                         roffs -= free->length;
1402                                         continue;
1403                                 }
1404                                 boffs = free->offset + roffs;
1405                                 bytes = min_t(size_t, len,
1406                                               (free->length - roffs));
1407                                 roffs = 0;
1408                         } else {
1409                                 bytes = min_t(size_t, len, free->length);
1410                                 boffs = free->offset;
1411                         }
1412                         memcpy(oob, chip->oob_poi + boffs, bytes);
1413                         oob += bytes;
1414                 }
1415                 return oob;
1416         }
1417         default:
1418                 BUG();
1419         }
1420         return NULL;
1421 }
1422
1423 /**
1424  * nand_do_read_ops - [INTERN] Read data with ECC
1425  * @mtd: MTD device structure
1426  * @from: offset to read from
1427  * @ops: oob ops structure
1428  *
1429  * Internal function. Called with chip held.
1430  */
1431 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1432                             struct mtd_oob_ops *ops)
1433 {
1434         int chipnr, page, realpage, col, bytes, aligned;
1435         struct nand_chip *chip = mtd->priv;
1436         struct mtd_ecc_stats stats;
1437         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1438         int sndcmd = 1;
1439         int ret = 0;
1440         uint32_t readlen = ops->len;
1441         uint32_t oobreadlen = ops->ooblen;
1442         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1443                 mtd->oobavail : mtd->oobsize;
1444
1445         uint8_t *bufpoi, *oob, *buf;
1446
1447         stats = mtd->ecc_stats;
1448
1449         chipnr = (int)(from >> chip->chip_shift);
1450         chip->select_chip(mtd, chipnr);
1451
1452         realpage = (int)(from >> chip->page_shift);
1453         page = realpage & chip->pagemask;
1454
1455         col = (int)(from & (mtd->writesize - 1));
1456
1457         buf = ops->datbuf;
1458         oob = ops->oobbuf;
1459
1460         while (1) {
1461                 bytes = min(mtd->writesize - col, readlen);
1462                 aligned = (bytes == mtd->writesize);
1463
1464                 /* Is the current page in the buffer? */
1465                 if (realpage != chip->pagebuf || oob) {
1466                         bufpoi = aligned ? buf : chip->buffers->databuf;
1467
1468                         if (likely(sndcmd)) {
1469                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1470                                 sndcmd = 0;
1471                         }
1472
1473                         /* Now read the page into the buffer */
1474                         if (unlikely(ops->mode == MTD_OPS_RAW))
1475                                 ret = chip->ecc.read_page_raw(mtd, chip,
1476                                                               bufpoi, page);
1477                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1478                                 ret = chip->ecc.read_subpage(mtd, chip,
1479                                                         col, bytes, bufpoi);
1480                         else
1481                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1482                                                           page);
1483                         if (ret < 0) {
1484                                 if (!aligned)
1485                                         /* Invalidate page cache */
1486                                         chip->pagebuf = -1;
1487                                 break;
1488                         }
1489
1490                         /* Transfer not aligned data */
1491                         if (!aligned) {
1492                                 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1493                                     !(mtd->ecc_stats.failed - stats.failed) &&
1494                                     (ops->mode != MTD_OPS_RAW))
1495                                         chip->pagebuf = realpage;
1496                                 else
1497                                         /* Invalidate page cache */
1498                                         chip->pagebuf = -1;
1499                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1500                         }
1501
1502                         buf += bytes;
1503
1504                         if (unlikely(oob)) {
1505
1506                                 int toread = min(oobreadlen, max_oobsize);
1507
1508                                 if (toread) {
1509                                         oob = nand_transfer_oob(chip,
1510                                                 oob, ops, toread);
1511                                         oobreadlen -= toread;
1512                                 }
1513                         }
1514
1515                         if (!(chip->options & NAND_NO_READRDY)) {
1516                                 /*
1517                                  * Apply delay or wait for ready/busy pin. Do
1518                                  * this before the AUTOINCR check, so no
1519                                  * problems arise if a chip which does auto
1520                                  * increment is marked as NOAUTOINCR by the
1521                                  * board driver.
1522                                  */
1523                                 if (!chip->dev_ready)
1524                                         udelay(chip->chip_delay);
1525                                 else
1526                                         nand_wait_ready(mtd);
1527                         }
1528                 } else {
1529                         memcpy(buf, chip->buffers->databuf + col, bytes);
1530                         buf += bytes;
1531                 }
1532
1533                 readlen -= bytes;
1534
1535                 if (!readlen)
1536                         break;
1537
1538                 /* For subsequent reads align to page boundary */
1539                 col = 0;
1540                 /* Increment page address */
1541                 realpage++;
1542
1543                 page = realpage & chip->pagemask;
1544                 /* Check, if we cross a chip boundary */
1545                 if (!page) {
1546                         chipnr++;
1547                         chip->select_chip(mtd, -1);
1548                         chip->select_chip(mtd, chipnr);
1549                 }
1550
1551                 /*
1552                  * Check, if the chip supports auto page increment or if we
1553                  * have hit a block boundary.
1554                  */
1555                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1556                         sndcmd = 1;
1557         }
1558
1559         ops->retlen = ops->len - (size_t) readlen;
1560         if (oob)
1561                 ops->oobretlen = ops->ooblen - oobreadlen;
1562
1563         if (ret)
1564                 return ret;
1565
1566         if (mtd->ecc_stats.failed - stats.failed)
1567                 return -EBADMSG;
1568
1569         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1570 }
1571
1572 /**
1573  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1574  * @mtd: MTD device structure
1575  * @from: offset to read from
1576  * @len: number of bytes to read
1577  * @retlen: pointer to variable to store the number of read bytes
1578  * @buf: the databuffer to put data
1579  *
1580  * Get hold of the chip and call nand_do_read.
1581  */
1582 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1583                      size_t *retlen, uint8_t *buf)
1584 {
1585         struct nand_chip *chip = mtd->priv;
1586         struct mtd_oob_ops ops;
1587         int ret;
1588
1589         /* Do not allow reads past end of device */
1590         if ((from + len) > mtd->size)
1591                 return -EINVAL;
1592         if (!len)
1593                 return 0;
1594
1595         nand_get_device(chip, mtd, FL_READING);
1596
1597         ops.len = len;
1598         ops.datbuf = buf;
1599         ops.oobbuf = NULL;
1600         ops.mode = 0;
1601
1602         ret = nand_do_read_ops(mtd, from, &ops);
1603
1604         *retlen = ops.retlen;
1605
1606         nand_release_device(mtd);
1607
1608         return ret;
1609 }
1610
1611 /**
1612  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1613  * @mtd: mtd info structure
1614  * @chip: nand chip info structure
1615  * @page: page number to read
1616  * @sndcmd: flag whether to issue read command or not
1617  */
1618 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1619                              int page, int sndcmd)
1620 {
1621         if (sndcmd) {
1622                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1623                 sndcmd = 0;
1624         }
1625         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1626         return sndcmd;
1627 }
1628
1629 /**
1630  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1631  *                          with syndromes
1632  * @mtd: mtd info structure
1633  * @chip: nand chip info structure
1634  * @page: page number to read
1635  * @sndcmd: flag whether to issue read command or not
1636  */
1637 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1638                                   int page, int sndcmd)
1639 {
1640         uint8_t *buf = chip->oob_poi;
1641         int length = mtd->oobsize;
1642         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1643         int eccsize = chip->ecc.size;
1644         uint8_t *bufpoi = buf;
1645         int i, toread, sndrnd = 0, pos;
1646
1647         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1648         for (i = 0; i < chip->ecc.steps; i++) {
1649                 if (sndrnd) {
1650                         pos = eccsize + i * (eccsize + chunk);
1651                         if (mtd->writesize > 512)
1652                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1653                         else
1654                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1655                 } else
1656                         sndrnd = 1;
1657                 toread = min_t(int, length, chunk);
1658                 chip->read_buf(mtd, bufpoi, toread);
1659                 bufpoi += toread;
1660                 length -= toread;
1661         }
1662         if (length > 0)
1663                 chip->read_buf(mtd, bufpoi, length);
1664
1665         return 1;
1666 }
1667
1668 /**
1669  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1670  * @mtd: mtd info structure
1671  * @chip: nand chip info structure
1672  * @page: page number to write
1673  */
1674 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1675                               int page)
1676 {
1677         int status = 0;
1678         const uint8_t *buf = chip->oob_poi;
1679         int length = mtd->oobsize;
1680
1681         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1682         chip->write_buf(mtd, buf, length);
1683         /* Send command to program the OOB data */
1684         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1685
1686         status = chip->waitfunc(mtd, chip);
1687
1688         return status & NAND_STATUS_FAIL ? -EIO : 0;
1689 }
1690
1691 /**
1692  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1693  *                           with syndrome - only for large page flash
1694  * @mtd: mtd info structure
1695  * @chip: nand chip info structure
1696  * @page: page number to write
1697  */
1698 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1699                                    struct nand_chip *chip, int page)
1700 {
1701         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1702         int eccsize = chip->ecc.size, length = mtd->oobsize;
1703         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1704         const uint8_t *bufpoi = chip->oob_poi;
1705
1706         /*
1707          * data-ecc-data-ecc ... ecc-oob
1708          * or
1709          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1710          */
1711         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1712                 pos = steps * (eccsize + chunk);
1713                 steps = 0;
1714         } else
1715                 pos = eccsize;
1716
1717         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1718         for (i = 0; i < steps; i++) {
1719                 if (sndcmd) {
1720                         if (mtd->writesize <= 512) {
1721                                 uint32_t fill = 0xFFFFFFFF;
1722
1723                                 len = eccsize;
1724                                 while (len > 0) {
1725                                         int num = min_t(int, len, 4);
1726                                         chip->write_buf(mtd, (uint8_t *)&fill,
1727                                                         num);
1728                                         len -= num;
1729                                 }
1730                         } else {
1731                                 pos = eccsize + i * (eccsize + chunk);
1732                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1733                         }
1734                 } else
1735                         sndcmd = 1;
1736                 len = min_t(int, length, chunk);
1737                 chip->write_buf(mtd, bufpoi, len);
1738                 bufpoi += len;
1739                 length -= len;
1740         }
1741         if (length > 0)
1742                 chip->write_buf(mtd, bufpoi, length);
1743
1744         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1745         status = chip->waitfunc(mtd, chip);
1746
1747         return status & NAND_STATUS_FAIL ? -EIO : 0;
1748 }
1749
1750 /**
1751  * nand_do_read_oob - [INTERN] NAND read out-of-band
1752  * @mtd: MTD device structure
1753  * @from: offset to read from
1754  * @ops: oob operations description structure
1755  *
1756  * NAND read out-of-band data from the spare area.
1757  */
1758 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1759                             struct mtd_oob_ops *ops)
1760 {
1761         int page, realpage, chipnr, sndcmd = 1;
1762         struct nand_chip *chip = mtd->priv;
1763         struct mtd_ecc_stats stats;
1764         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1765         int readlen = ops->ooblen;
1766         int len;
1767         uint8_t *buf = ops->oobbuf;
1768
1769         pr_debug("%s: from = 0x%08Lx, len = %i\n",
1770                         __func__, (unsigned long long)from, readlen);
1771
1772         stats = mtd->ecc_stats;
1773
1774         if (ops->mode == MTD_OPS_AUTO_OOB)
1775                 len = chip->ecc.layout->oobavail;
1776         else
1777                 len = mtd->oobsize;
1778
1779         if (unlikely(ops->ooboffs >= len)) {
1780                 pr_debug("%s: attempt to start read outside oob\n",
1781                                 __func__);
1782                 return -EINVAL;
1783         }
1784
1785         /* Do not allow reads past end of device */
1786         if (unlikely(from >= mtd->size ||
1787                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1788                                         (from >> chip->page_shift)) * len)) {
1789                 pr_debug("%s: attempt to read beyond end of device\n",
1790                                 __func__);
1791                 return -EINVAL;
1792         }
1793
1794         chipnr = (int)(from >> chip->chip_shift);
1795         chip->select_chip(mtd, chipnr);
1796
1797         /* Shift to get page */
1798         realpage = (int)(from >> chip->page_shift);
1799         page = realpage & chip->pagemask;
1800
1801         while (1) {
1802                 if (ops->mode == MTD_OPS_RAW)
1803                         sndcmd = chip->ecc.read_oob_raw(mtd, chip, page, sndcmd);
1804                 else
1805                         sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1806
1807                 len = min(len, readlen);
1808                 buf = nand_transfer_oob(chip, buf, ops, len);
1809
1810                 if (!(chip->options & NAND_NO_READRDY)) {
1811                         /*
1812                          * Apply delay or wait for ready/busy pin. Do this
1813                          * before the AUTOINCR check, so no problems arise if a
1814                          * chip which does auto increment is marked as
1815                          * NOAUTOINCR by the board driver.
1816                          */
1817                         if (!chip->dev_ready)
1818                                 udelay(chip->chip_delay);
1819                         else
1820                                 nand_wait_ready(mtd);
1821                 }
1822
1823                 readlen -= len;
1824                 if (!readlen)
1825                         break;
1826
1827                 /* Increment page address */
1828                 realpage++;
1829
1830                 page = realpage & chip->pagemask;
1831                 /* Check, if we cross a chip boundary */
1832                 if (!page) {
1833                         chipnr++;
1834                         chip->select_chip(mtd, -1);
1835                         chip->select_chip(mtd, chipnr);
1836                 }
1837
1838                 /*
1839                  * Check, if the chip supports auto page increment or if we
1840                  * have hit a block boundary.
1841                  */
1842                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1843                         sndcmd = 1;
1844         }
1845
1846         ops->oobretlen = ops->ooblen;
1847
1848         if (mtd->ecc_stats.failed - stats.failed)
1849                 return -EBADMSG;
1850
1851         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1852 }
1853
1854 /**
1855  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1856  * @mtd: MTD device structure
1857  * @from: offset to read from
1858  * @ops: oob operation description structure
1859  *
1860  * NAND read data and/or out-of-band data.
1861  */
1862 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1863                          struct mtd_oob_ops *ops)
1864 {
1865         struct nand_chip *chip = mtd->priv;
1866         int ret = -ENOTSUPP;
1867
1868         ops->retlen = 0;
1869
1870         /* Do not allow reads past end of device */
1871         if (ops->datbuf && (from + ops->len) > mtd->size) {
1872                 pr_debug("%s: attempt to read beyond end of device\n",
1873                                 __func__);
1874                 return -EINVAL;
1875         }
1876
1877         nand_get_device(chip, mtd, FL_READING);
1878
1879         switch (ops->mode) {
1880         case MTD_OPS_PLACE_OOB:
1881         case MTD_OPS_AUTO_OOB:
1882         case MTD_OPS_RAW:
1883                 break;
1884
1885         default:
1886                 goto out;
1887         }
1888
1889         if (!ops->datbuf)
1890                 ret = nand_do_read_oob(mtd, from, ops);
1891         else
1892                 ret = nand_do_read_ops(mtd, from, ops);
1893
1894 out:
1895         nand_release_device(mtd);
1896         return ret;
1897 }
1898
1899
1900 /**
1901  * nand_write_page_raw - [INTERN] raw page write function
1902  * @mtd: mtd info structure
1903  * @chip: nand chip info structure
1904  * @buf: data buffer
1905  *
1906  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1907  */
1908 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1909                                 const uint8_t *buf)
1910 {
1911         chip->write_buf(mtd, buf, mtd->writesize);
1912         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1913 }
1914
1915 /**
1916  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1917  * @mtd: mtd info structure
1918  * @chip: nand chip info structure
1919  * @buf: data buffer
1920  *
1921  * We need a special oob layout and handling even when ECC isn't checked.
1922  */
1923 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1924                                         struct nand_chip *chip,
1925                                         const uint8_t *buf)
1926 {
1927         int eccsize = chip->ecc.size;
1928         int eccbytes = chip->ecc.bytes;
1929         uint8_t *oob = chip->oob_poi;
1930         int steps, size;
1931
1932         for (steps = chip->ecc.steps; steps > 0; steps--) {
1933                 chip->write_buf(mtd, buf, eccsize);
1934                 buf += eccsize;
1935
1936                 if (chip->ecc.prepad) {
1937                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1938                         oob += chip->ecc.prepad;
1939                 }
1940
1941                 chip->read_buf(mtd, oob, eccbytes);
1942                 oob += eccbytes;
1943
1944                 if (chip->ecc.postpad) {
1945                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1946                         oob += chip->ecc.postpad;
1947                 }
1948         }
1949
1950         size = mtd->oobsize - (oob - chip->oob_poi);
1951         if (size)
1952                 chip->write_buf(mtd, oob, size);
1953 }
1954 /**
1955  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1956  * @mtd: mtd info structure
1957  * @chip: nand chip info structure
1958  * @buf: data buffer
1959  */
1960 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1961                                   const uint8_t *buf)
1962 {
1963         int i, eccsize = chip->ecc.size;
1964         int eccbytes = chip->ecc.bytes;
1965         int eccsteps = chip->ecc.steps;
1966         uint8_t *ecc_calc = chip->buffers->ecccalc;
1967         const uint8_t *p = buf;
1968         uint32_t *eccpos = chip->ecc.layout->eccpos;
1969
1970         /* Software ECC calculation */
1971         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1972                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1973
1974         for (i = 0; i < chip->ecc.total; i++)
1975                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1976
1977         chip->ecc.write_page_raw(mtd, chip, buf);
1978 }
1979
1980 /**
1981  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1982  * @mtd: mtd info structure
1983  * @chip: nand chip info structure
1984  * @buf: data buffer
1985  */
1986 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1987                                   const uint8_t *buf)
1988 {
1989         int i, eccsize = chip->ecc.size;
1990         int eccbytes = chip->ecc.bytes;
1991         int eccsteps = chip->ecc.steps;
1992         uint8_t *ecc_calc = chip->buffers->ecccalc;
1993         const uint8_t *p = buf;
1994         uint32_t *eccpos = chip->ecc.layout->eccpos;
1995
1996         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1997                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1998                 chip->write_buf(mtd, p, eccsize);
1999                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
2000         }
2001
2002         for (i = 0; i < chip->ecc.total; i++)
2003                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
2004
2005         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2006 }
2007
2008 /**
2009  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
2010  * @mtd: mtd info structure
2011  * @chip: nand chip info structure
2012  * @buf: data buffer
2013  *
2014  * The hw generator calculates the error syndrome automatically. Therefore we
2015  * need a special oob layout and handling.
2016  */
2017 static void nand_write_page_syndrome(struct mtd_info *mtd,
2018                                     struct nand_chip *chip, const uint8_t *buf)
2019 {
2020         int i, eccsize = chip->ecc.size;
2021         int eccbytes = chip->ecc.bytes;
2022         int eccsteps = chip->ecc.steps;
2023         const uint8_t *p = buf;
2024         uint8_t *oob = chip->oob_poi;
2025
2026         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2027
2028                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2029                 chip->write_buf(mtd, p, eccsize);
2030
2031                 if (chip->ecc.prepad) {
2032                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2033                         oob += chip->ecc.prepad;
2034                 }
2035
2036                 chip->ecc.calculate(mtd, p, oob);
2037                 chip->write_buf(mtd, oob, eccbytes);
2038                 oob += eccbytes;
2039
2040                 if (chip->ecc.postpad) {
2041                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2042                         oob += chip->ecc.postpad;
2043                 }
2044         }
2045
2046         /* Calculate remaining oob bytes */
2047         i = mtd->oobsize - (oob - chip->oob_poi);
2048         if (i)
2049                 chip->write_buf(mtd, oob, i);
2050 }
2051
2052 /**
2053  * nand_write_page - [REPLACEABLE] write one page
2054  * @mtd: MTD device structure
2055  * @chip: NAND chip descriptor
2056  * @buf: the data to write
2057  * @page: page number to write
2058  * @cached: cached programming
2059  * @raw: use _raw version of write_page
2060  */
2061 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2062                            const uint8_t *buf, int page, int cached, int raw)
2063 {
2064         int status;
2065
2066         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2067
2068         if (unlikely(raw))
2069                 chip->ecc.write_page_raw(mtd, chip, buf);
2070         else
2071                 chip->ecc.write_page(mtd, chip, buf);
2072
2073         /*
2074          * Cached progamming disabled for now. Not sure if it's worth the
2075          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2076          */
2077         cached = 0;
2078
2079         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2080
2081                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2082                 status = chip->waitfunc(mtd, chip);
2083                 /*
2084                  * See if operation failed and additional status checks are
2085                  * available.
2086                  */
2087                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2088                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2089                                                page);
2090
2091                 if (status & NAND_STATUS_FAIL)
2092                         return -EIO;
2093         } else {
2094                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2095                 status = chip->waitfunc(mtd, chip);
2096         }
2097
2098 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2099         /* Send command to read back the data */
2100         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2101
2102         if (chip->verify_buf(mtd, buf, mtd->writesize))
2103                 return -EIO;
2104 #endif
2105         return 0;
2106 }
2107
2108 /**
2109  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2110  * @mtd: MTD device structure
2111  * @oob: oob data buffer
2112  * @len: oob data write length
2113  * @ops: oob ops structure
2114  */
2115 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2116                               struct mtd_oob_ops *ops)
2117 {
2118         struct nand_chip *chip = mtd->priv;
2119
2120         /*
2121          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2122          * data from a previous OOB read.
2123          */
2124         memset(chip->oob_poi, 0xff, mtd->oobsize);
2125
2126         switch (ops->mode) {
2127
2128         case MTD_OPS_PLACE_OOB:
2129         case MTD_OPS_RAW:
2130                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2131                 return oob + len;
2132
2133         case MTD_OPS_AUTO_OOB: {
2134                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2135                 uint32_t boffs = 0, woffs = ops->ooboffs;
2136                 size_t bytes = 0;
2137
2138                 for (; free->length && len; free++, len -= bytes) {
2139                         /* Write request not from offset 0? */
2140                         if (unlikely(woffs)) {
2141                                 if (woffs >= free->length) {
2142                                         woffs -= free->length;
2143                                         continue;
2144                                 }
2145                                 boffs = free->offset + woffs;
2146                                 bytes = min_t(size_t, len,
2147                                               (free->length - woffs));
2148                                 woffs = 0;
2149                         } else {
2150                                 bytes = min_t(size_t, len, free->length);
2151                                 boffs = free->offset;
2152                         }
2153                         memcpy(chip->oob_poi + boffs, oob, bytes);
2154                         oob += bytes;
2155                 }
2156                 return oob;
2157         }
2158         default:
2159                 BUG();
2160         }
2161         return NULL;
2162 }
2163
2164 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2165
2166 /**
2167  * nand_do_write_ops - [INTERN] NAND write with ECC
2168  * @mtd: MTD device structure
2169  * @to: offset to write to
2170  * @ops: oob operations description structure
2171  *
2172  * NAND write with ECC.
2173  */
2174 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2175                              struct mtd_oob_ops *ops)
2176 {
2177         int chipnr, realpage, page, blockmask, column;
2178         struct nand_chip *chip = mtd->priv;
2179         uint32_t writelen = ops->len;
2180
2181         uint32_t oobwritelen = ops->ooblen;
2182         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2183                                 mtd->oobavail : mtd->oobsize;
2184
2185         uint8_t *oob = ops->oobbuf;
2186         uint8_t *buf = ops->datbuf;
2187         int ret, subpage;
2188
2189         ops->retlen = 0;
2190         if (!writelen)
2191                 return 0;
2192
2193         /* Reject writes, which are not page aligned */
2194         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2195                 pr_notice("%s: attempt to write non page aligned data\n",
2196                            __func__);
2197                 return -EINVAL;
2198         }
2199
2200         column = to & (mtd->writesize - 1);
2201         subpage = column || (writelen & (mtd->writesize - 1));
2202
2203         if (subpage && oob)
2204                 return -EINVAL;
2205
2206         chipnr = (int)(to >> chip->chip_shift);
2207         chip->select_chip(mtd, chipnr);
2208
2209         /* Check, if it is write protected */
2210         if (nand_check_wp(mtd))
2211                 return -EIO;
2212
2213         realpage = (int)(to >> chip->page_shift);
2214         page = realpage & chip->pagemask;
2215         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2216
2217         /* Invalidate the page cache, when we write to the cached page */
2218         if (to <= (chip->pagebuf << chip->page_shift) &&
2219             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2220                 chip->pagebuf = -1;
2221
2222         /* Don't allow multipage oob writes with offset */
2223         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2224                 return -EINVAL;
2225
2226         while (1) {
2227                 int bytes = mtd->writesize;
2228                 int cached = writelen > bytes && page != blockmask;
2229                 uint8_t *wbuf = buf;
2230
2231                 /* Partial page write? */
2232                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2233                         cached = 0;
2234                         bytes = min_t(int, bytes - column, (int) writelen);
2235                         chip->pagebuf = -1;
2236                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2237                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2238                         wbuf = chip->buffers->databuf;
2239                 }
2240
2241                 if (unlikely(oob)) {
2242                         size_t len = min(oobwritelen, oobmaxlen);
2243                         oob = nand_fill_oob(mtd, oob, len, ops);
2244                         oobwritelen -= len;
2245                 } else {
2246                         /* We still need to erase leftover OOB data */
2247                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2248                 }
2249
2250                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2251                                        (ops->mode == MTD_OPS_RAW));
2252                 if (ret)
2253                         break;
2254
2255                 writelen -= bytes;
2256                 if (!writelen)
2257                         break;
2258
2259                 column = 0;
2260                 buf += bytes;
2261                 realpage++;
2262
2263                 page = realpage & chip->pagemask;
2264                 /* Check, if we cross a chip boundary */
2265                 if (!page) {
2266                         chipnr++;
2267                         chip->select_chip(mtd, -1);
2268                         chip->select_chip(mtd, chipnr);
2269                 }
2270         }
2271
2272         ops->retlen = ops->len - writelen;
2273         if (unlikely(oob))
2274                 ops->oobretlen = ops->ooblen;
2275         return ret;
2276 }
2277
2278 /**
2279  * panic_nand_write - [MTD Interface] NAND write with ECC
2280  * @mtd: MTD device structure
2281  * @to: offset to write to
2282  * @len: number of bytes to write
2283  * @retlen: pointer to variable to store the number of written bytes
2284  * @buf: the data to write
2285  *
2286  * NAND write with ECC. Used when performing writes in interrupt context, this
2287  * may for example be called by mtdoops when writing an oops while in panic.
2288  */
2289 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2290                             size_t *retlen, const uint8_t *buf)
2291 {
2292         struct nand_chip *chip = mtd->priv;
2293         struct mtd_oob_ops ops;
2294         int ret;
2295
2296         /* Do not allow reads past end of device */
2297         if ((to + len) > mtd->size)
2298                 return -EINVAL;
2299         if (!len)
2300                 return 0;
2301
2302         /* Wait for the device to get ready */
2303         panic_nand_wait(mtd, chip, 400);
2304
2305         /* Grab the device */
2306         panic_nand_get_device(chip, mtd, FL_WRITING);
2307
2308         ops.len = len;
2309         ops.datbuf = (uint8_t *)buf;
2310         ops.oobbuf = NULL;
2311         ops.mode = 0;
2312
2313         ret = nand_do_write_ops(mtd, to, &ops);
2314
2315         *retlen = ops.retlen;
2316         return ret;
2317 }
2318
2319 /**
2320  * nand_write - [MTD Interface] NAND write with ECC
2321  * @mtd: MTD device structure
2322  * @to: offset to write to
2323  * @len: number of bytes to write
2324  * @retlen: pointer to variable to store the number of written bytes
2325  * @buf: the data to write
2326  *
2327  * NAND write with ECC.
2328  */
2329 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2330                           size_t *retlen, const uint8_t *buf)
2331 {
2332         struct nand_chip *chip = mtd->priv;
2333         struct mtd_oob_ops ops;
2334         int ret;
2335
2336         /* Do not allow reads past end of device */
2337         if ((to + len) > mtd->size)
2338                 return -EINVAL;
2339         if (!len)
2340                 return 0;
2341
2342         nand_get_device(chip, mtd, FL_WRITING);
2343
2344         ops.len = len;
2345         ops.datbuf = (uint8_t *)buf;
2346         ops.oobbuf = NULL;
2347         ops.mode = 0;
2348
2349         ret = nand_do_write_ops(mtd, to, &ops);
2350
2351         *retlen = ops.retlen;
2352
2353         nand_release_device(mtd);
2354
2355         return ret;
2356 }
2357
2358 /**
2359  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2360  * @mtd: MTD device structure
2361  * @to: offset to write to
2362  * @ops: oob operation description structure
2363  *
2364  * NAND write out-of-band.
2365  */
2366 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2367                              struct mtd_oob_ops *ops)
2368 {
2369         int chipnr, page, status, len;
2370         struct nand_chip *chip = mtd->priv;
2371
2372         pr_debug("%s: to = 0x%08x, len = %i\n",
2373                          __func__, (unsigned int)to, (int)ops->ooblen);
2374
2375         if (ops->mode == MTD_OPS_AUTO_OOB)
2376                 len = chip->ecc.layout->oobavail;
2377         else
2378                 len = mtd->oobsize;
2379
2380         /* Do not allow write past end of page */
2381         if ((ops->ooboffs + ops->ooblen) > len) {
2382                 pr_debug("%s: attempt to write past end of page\n",
2383                                 __func__);
2384                 return -EINVAL;
2385         }
2386
2387         if (unlikely(ops->ooboffs >= len)) {
2388                 pr_debug("%s: attempt to start write outside oob\n",
2389                                 __func__);
2390                 return -EINVAL;
2391         }
2392
2393         /* Do not allow write past end of device */
2394         if (unlikely(to >= mtd->size ||
2395                      ops->ooboffs + ops->ooblen >
2396                         ((mtd->size >> chip->page_shift) -
2397                          (to >> chip->page_shift)) * len)) {
2398                 pr_debug("%s: attempt to write beyond end of device\n",
2399                                 __func__);
2400                 return -EINVAL;
2401         }
2402
2403         chipnr = (int)(to >> chip->chip_shift);
2404         chip->select_chip(mtd, chipnr);
2405
2406         /* Shift to get page */
2407         page = (int)(to >> chip->page_shift);
2408
2409         /*
2410          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2411          * of my DiskOnChip 2000 test units) will clear the whole data page too
2412          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2413          * it in the doc2000 driver in August 1999.  dwmw2.
2414          */
2415         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2416
2417         /* Check, if it is write protected */
2418         if (nand_check_wp(mtd))
2419                 return -EROFS;
2420
2421         /* Invalidate the page cache, if we write to the cached page */
2422         if (page == chip->pagebuf)
2423                 chip->pagebuf = -1;
2424
2425         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2426
2427         if (ops->mode == MTD_OPS_RAW)
2428                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2429         else
2430                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2431
2432         if (status)
2433                 return status;
2434
2435         ops->oobretlen = ops->ooblen;
2436
2437         return 0;
2438 }
2439
2440 /**
2441  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2442  * @mtd: MTD device structure
2443  * @to: offset to write to
2444  * @ops: oob operation description structure
2445  */
2446 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2447                           struct mtd_oob_ops *ops)
2448 {
2449         struct nand_chip *chip = mtd->priv;
2450         int ret = -ENOTSUPP;
2451
2452         ops->retlen = 0;
2453
2454         /* Do not allow writes past end of device */
2455         if (ops->datbuf && (to + ops->len) > mtd->size) {
2456                 pr_debug("%s: attempt to write beyond end of device\n",
2457                                 __func__);
2458                 return -EINVAL;
2459         }
2460
2461         nand_get_device(chip, mtd, FL_WRITING);
2462
2463         switch (ops->mode) {
2464         case MTD_OPS_PLACE_OOB:
2465         case MTD_OPS_AUTO_OOB:
2466         case MTD_OPS_RAW:
2467                 break;
2468
2469         default:
2470                 goto out;
2471         }
2472
2473         if (!ops->datbuf)
2474                 ret = nand_do_write_oob(mtd, to, ops);
2475         else
2476                 ret = nand_do_write_ops(mtd, to, ops);
2477
2478 out:
2479         nand_release_device(mtd);
2480         return ret;
2481 }
2482
2483 /**
2484  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2485  * @mtd: MTD device structure
2486  * @page: the page address of the block which will be erased
2487  *
2488  * Standard erase command for NAND chips.
2489  */
2490 static void single_erase_cmd(struct mtd_info *mtd, int page)
2491 {
2492         struct nand_chip *chip = mtd->priv;
2493         /* Send commands to erase a block */
2494         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2495         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2496 }
2497
2498 /**
2499  * multi_erase_cmd - [GENERIC] AND specific block erase command function
2500  * @mtd: MTD device structure
2501  * @page: the page address of the block which will be erased
2502  *
2503  * AND multi block erase command function. Erase 4 consecutive blocks.
2504  */
2505 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2506 {
2507         struct nand_chip *chip = mtd->priv;
2508         /* Send commands to erase a block */
2509         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2510         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2511         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2512         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2513         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2514 }
2515
2516 /**
2517  * nand_erase - [MTD Interface] erase block(s)
2518  * @mtd: MTD device structure
2519  * @instr: erase instruction
2520  *
2521  * Erase one ore more blocks.
2522  */
2523 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2524 {
2525         return nand_erase_nand(mtd, instr, 0);
2526 }
2527
2528 #define BBT_PAGE_MASK   0xffffff3f
2529 /**
2530  * nand_erase_nand - [INTERN] erase block(s)
2531  * @mtd: MTD device structure
2532  * @instr: erase instruction
2533  * @allowbbt: allow erasing the bbt area
2534  *
2535  * Erase one ore more blocks.
2536  */
2537 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2538                     int allowbbt)
2539 {
2540         int page, status, pages_per_block, ret, chipnr;
2541         struct nand_chip *chip = mtd->priv;
2542         loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2543         unsigned int bbt_masked_page = 0xffffffff;
2544         loff_t len;
2545
2546         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2547                         __func__, (unsigned long long)instr->addr,
2548                         (unsigned long long)instr->len);
2549
2550         if (check_offs_len(mtd, instr->addr, instr->len))
2551                 return -EINVAL;
2552
2553         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2554
2555         /* Grab the lock and see if the device is available */
2556         nand_get_device(chip, mtd, FL_ERASING);
2557
2558         /* Shift to get first page */
2559         page = (int)(instr->addr >> chip->page_shift);
2560         chipnr = (int)(instr->addr >> chip->chip_shift);
2561
2562         /* Calculate pages in each block */
2563         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2564
2565         /* Select the NAND device */
2566         chip->select_chip(mtd, chipnr);
2567
2568         /* Check, if it is write protected */
2569         if (nand_check_wp(mtd)) {
2570                 pr_debug("%s: device is write protected!\n",
2571                                 __func__);
2572                 instr->state = MTD_ERASE_FAILED;
2573                 goto erase_exit;
2574         }
2575
2576         /*
2577          * If BBT requires refresh, set the BBT page mask to see if the BBT
2578          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2579          * can not be matched. This is also done when the bbt is actually
2580          * erased to avoid recursive updates.
2581          */
2582         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2583                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2584
2585         /* Loop through the pages */
2586         len = instr->len;
2587
2588         instr->state = MTD_ERASING;
2589
2590         while (len) {
2591                 /* Heck if we have a bad block, we do not erase bad blocks! */
2592                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2593                                         chip->page_shift, 0, allowbbt)) {
2594                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2595                                     __func__, page);
2596                         instr->state = MTD_ERASE_FAILED;
2597                         goto erase_exit;
2598                 }
2599
2600                 /*
2601                  * Invalidate the page cache, if we erase the block which
2602                  * contains the current cached page.
2603                  */
2604                 if (page <= chip->pagebuf && chip->pagebuf <
2605                     (page + pages_per_block))
2606                         chip->pagebuf = -1;
2607
2608                 chip->erase_cmd(mtd, page & chip->pagemask);
2609
2610                 status = chip->waitfunc(mtd, chip);
2611
2612                 /*
2613                  * See if operation failed and additional status checks are
2614                  * available
2615                  */
2616                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2617                         status = chip->errstat(mtd, chip, FL_ERASING,
2618                                                status, page);
2619
2620                 /* See if block erase succeeded */
2621                 if (status & NAND_STATUS_FAIL) {
2622                         pr_debug("%s: failed erase, page 0x%08x\n",
2623                                         __func__, page);
2624                         instr->state = MTD_ERASE_FAILED;
2625                         instr->fail_addr =
2626                                 ((loff_t)page << chip->page_shift);
2627                         goto erase_exit;
2628                 }
2629
2630                 /*
2631                  * If BBT requires refresh, set the BBT rewrite flag to the
2632                  * page being erased.
2633                  */
2634                 if (bbt_masked_page != 0xffffffff &&
2635                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2636                             rewrite_bbt[chipnr] =
2637                                         ((loff_t)page << chip->page_shift);
2638
2639                 /* Increment page address and decrement length */
2640                 len -= (1 << chip->phys_erase_shift);
2641                 page += pages_per_block;
2642
2643                 /* Check, if we cross a chip boundary */
2644                 if (len && !(page & chip->pagemask)) {
2645                         chipnr++;
2646                         chip->select_chip(mtd, -1);
2647                         chip->select_chip(mtd, chipnr);
2648
2649                         /*
2650                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2651                          * page mask to see if this BBT should be rewritten.
2652                          */
2653                         if (bbt_masked_page != 0xffffffff &&
2654                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2655                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2656                                         BBT_PAGE_MASK;
2657                 }
2658         }
2659         instr->state = MTD_ERASE_DONE;
2660
2661 erase_exit:
2662
2663         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2664
2665         /* Deselect and wake up anyone waiting on the device */
2666         nand_release_device(mtd);
2667
2668         /* Do call back function */
2669         if (!ret)
2670                 mtd_erase_callback(instr);
2671
2672         /*
2673          * If BBT requires refresh and erase was successful, rewrite any
2674          * selected bad block tables.
2675          */
2676         if (bbt_masked_page == 0xffffffff || ret)
2677                 return ret;
2678
2679         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2680                 if (!rewrite_bbt[chipnr])
2681                         continue;
2682                 /* Update the BBT for chip */
2683                 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2684                                 __func__, chipnr, rewrite_bbt[chipnr],
2685                                 chip->bbt_td->pages[chipnr]);
2686                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2687         }
2688
2689         /* Return more or less happy */
2690         return ret;
2691 }
2692
2693 /**
2694  * nand_sync - [MTD Interface] sync
2695  * @mtd: MTD device structure
2696  *
2697  * Sync is actually a wait for chip ready function.
2698  */
2699 static void nand_sync(struct mtd_info *mtd)
2700 {
2701         struct nand_chip *chip = mtd->priv;
2702
2703         pr_debug("%s: called\n", __func__);
2704
2705         /* Grab the lock and see if the device is available */
2706         nand_get_device(chip, mtd, FL_SYNCING);
2707         /* Release it and go back */
2708         nand_release_device(mtd);
2709 }
2710
2711 /**
2712  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2713  * @mtd: MTD device structure
2714  * @offs: offset relative to mtd start
2715  */
2716 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2717 {
2718         /* Check for invalid offset */
2719         if (offs > mtd->size)
2720                 return -EINVAL;
2721
2722         return nand_block_checkbad(mtd, offs, 1, 0);
2723 }
2724
2725 /**
2726  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2727  * @mtd: MTD device structure
2728  * @ofs: offset relative to mtd start
2729  */
2730 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2731 {
2732         struct nand_chip *chip = mtd->priv;
2733         int ret;
2734
2735         ret = nand_block_isbad(mtd, ofs);
2736         if (ret) {
2737                 /* If it was bad already, return success and do nothing */
2738                 if (ret > 0)
2739                         return 0;
2740                 return ret;
2741         }
2742
2743         return chip->block_markbad(mtd, ofs);
2744 }
2745
2746 /**
2747  * nand_suspend - [MTD Interface] Suspend the NAND flash
2748  * @mtd: MTD device structure
2749  */
2750 static int nand_suspend(struct mtd_info *mtd)
2751 {
2752         struct nand_chip *chip = mtd->priv;
2753
2754         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2755 }
2756
2757 /**
2758  * nand_resume - [MTD Interface] Resume the NAND flash
2759  * @mtd: MTD device structure
2760  */
2761 static void nand_resume(struct mtd_info *mtd)
2762 {
2763         struct nand_chip *chip = mtd->priv;
2764
2765         if (chip->state == FL_PM_SUSPENDED)
2766                 nand_release_device(mtd);
2767         else
2768                 pr_err("%s called for a chip which is not in suspended state\n",
2769                         __func__);
2770 }
2771
2772 /* Set default functions */
2773 static void nand_set_defaults(struct nand_chip *chip, int busw)
2774 {
2775         /* check for proper chip_delay setup, set 20us if not */
2776         if (!chip->chip_delay)
2777                 chip->chip_delay = 20;
2778
2779         /* check, if a user supplied command function given */
2780         if (chip->cmdfunc == NULL)
2781                 chip->cmdfunc = nand_command;
2782
2783         /* check, if a user supplied wait function given */
2784         if (chip->waitfunc == NULL)
2785                 chip->waitfunc = nand_wait;
2786
2787         if (!chip->select_chip)
2788                 chip->select_chip = nand_select_chip;
2789         if (!chip->read_byte)
2790                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2791         if (!chip->read_word)
2792                 chip->read_word = nand_read_word;
2793         if (!chip->block_bad)
2794                 chip->block_bad = nand_block_bad;
2795         if (!chip->block_markbad)
2796                 chip->block_markbad = nand_default_block_markbad;
2797         if (!chip->write_buf)
2798                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2799         if (!chip->read_buf)
2800                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2801         if (!chip->verify_buf)
2802                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2803         if (!chip->scan_bbt)
2804                 chip->scan_bbt = nand_default_bbt;
2805
2806         if (!chip->controller) {
2807                 chip->controller = &chip->hwcontrol;
2808                 spin_lock_init(&chip->controller->lock);
2809                 init_waitqueue_head(&chip->controller->wq);
2810         }
2811
2812 }
2813
2814 /* Sanitize ONFI strings so we can safely print them */
2815 static void sanitize_string(uint8_t *s, size_t len)
2816 {
2817         ssize_t i;
2818
2819         /* Null terminate */
2820         s[len - 1] = 0;
2821
2822         /* Remove non printable chars */
2823         for (i = 0; i < len - 1; i++) {
2824                 if (s[i] < ' ' || s[i] > 127)
2825                         s[i] = '?';
2826         }
2827
2828         /* Remove trailing spaces */
2829         strim(s);
2830 }
2831
2832 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2833 {
2834         int i;
2835         while (len--) {
2836                 crc ^= *p++ << 8;
2837                 for (i = 0; i < 8; i++)
2838                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2839         }
2840
2841         return crc;
2842 }
2843
2844 /*
2845  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2846  */
2847 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2848                                         int *busw)
2849 {
2850         struct nand_onfi_params *p = &chip->onfi_params;
2851         int i;
2852         int val;
2853
2854         /* Try ONFI for unknown chip or LP */
2855         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2856         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2857                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2858                 return 0;
2859
2860         pr_info("ONFI flash detected\n");
2861         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2862         for (i = 0; i < 3; i++) {
2863                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2864                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2865                                 le16_to_cpu(p->crc)) {
2866                         pr_info("ONFI param page %d valid\n", i);
2867                         break;
2868                 }
2869         }
2870
2871         if (i == 3)
2872                 return 0;
2873
2874         /* Check version */
2875         val = le16_to_cpu(p->revision);
2876         if (val & (1 << 5))
2877                 chip->onfi_version = 23;
2878         else if (val & (1 << 4))
2879                 chip->onfi_version = 22;
2880         else if (val & (1 << 3))
2881                 chip->onfi_version = 21;
2882         else if (val & (1 << 2))
2883                 chip->onfi_version = 20;
2884         else if (val & (1 << 1))
2885                 chip->onfi_version = 10;
2886         else
2887                 chip->onfi_version = 0;
2888
2889         if (!chip->onfi_version) {
2890                 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2891                 return 0;
2892         }
2893
2894         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2895         sanitize_string(p->model, sizeof(p->model));
2896         if (!mtd->name)
2897                 mtd->name = p->model;
2898         mtd->writesize = le32_to_cpu(p->byte_per_page);
2899         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2900         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2901         chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2902         *busw = 0;
2903         if (le16_to_cpu(p->features) & 1)
2904                 *busw = NAND_BUSWIDTH_16;
2905
2906         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2907         chip->options |= (NAND_NO_READRDY |
2908                         NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2909
2910         return 1;
2911 }
2912
2913 /*
2914  * Get the flash and manufacturer id and lookup if the type is supported.
2915  */
2916 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2917                                                   struct nand_chip *chip,
2918                                                   int busw,
2919                                                   int *maf_id, int *dev_id,
2920                                                   struct nand_flash_dev *type)
2921 {
2922         int i, maf_idx;
2923         u8 id_data[8];
2924         int ret;
2925
2926         /* Select the device */
2927         chip->select_chip(mtd, 0);
2928
2929         /*
2930          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2931          * after power-up.
2932          */
2933         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2934
2935         /* Send the command for reading device ID */
2936         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2937
2938         /* Read manufacturer and device IDs */
2939         *maf_id = chip->read_byte(mtd);
2940         *dev_id = chip->read_byte(mtd);
2941
2942         /*
2943          * Try again to make sure, as some systems the bus-hold or other
2944          * interface concerns can cause random data which looks like a
2945          * possibly credible NAND flash to appear. If the two results do
2946          * not match, ignore the device completely.
2947          */
2948
2949         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2950
2951         for (i = 0; i < 2; i++)
2952                 id_data[i] = chip->read_byte(mtd);
2953
2954         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2955                 pr_info("%s: second ID read did not match "
2956                         "%02x,%02x against %02x,%02x\n", __func__,
2957                         *maf_id, *dev_id, id_data[0], id_data[1]);
2958                 return ERR_PTR(-ENODEV);
2959         }
2960
2961         if (!type)
2962                 type = nand_flash_ids;
2963
2964         for (; type->name != NULL; type++)
2965                 if (*dev_id == type->id)
2966                         break;
2967
2968         chip->onfi_version = 0;
2969         if (!type->name || !type->pagesize) {
2970                 /* Check is chip is ONFI compliant */
2971                 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2972                 if (ret)
2973                         goto ident_done;
2974         }
2975
2976         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2977
2978         /* Read entire ID string */
2979
2980         for (i = 0; i < 8; i++)
2981                 id_data[i] = chip->read_byte(mtd);
2982
2983         if (!type->name)
2984                 return ERR_PTR(-ENODEV);
2985
2986         if (!mtd->name)
2987                 mtd->name = type->name;
2988
2989         chip->chipsize = (uint64_t)type->chipsize << 20;
2990
2991         if (!type->pagesize && chip->init_size) {
2992                 /* Set the pagesize, oobsize, erasesize by the driver */
2993                 busw = chip->init_size(mtd, chip, id_data);
2994         } else if (!type->pagesize) {
2995                 int extid;
2996                 /* The 3rd id byte holds MLC / multichip data */
2997                 chip->cellinfo = id_data[2];
2998                 /* The 4th id byte is the important one */
2999                 extid = id_data[3];
3000
3001                 /*
3002                  * Field definitions are in the following datasheets:
3003                  * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
3004                  * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
3005                  *
3006                  * Check for wraparound + Samsung ID + nonzero 6th byte
3007                  * to decide what to do.
3008                  */
3009                 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
3010                                 id_data[0] == NAND_MFR_SAMSUNG &&
3011                                 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3012                                 id_data[5] != 0x00) {
3013                         /* Calc pagesize */
3014                         mtd->writesize = 2048 << (extid & 0x03);
3015                         extid >>= 2;
3016                         /* Calc oobsize */
3017                         switch (extid & 0x03) {
3018                         case 1:
3019                                 mtd->oobsize = 128;
3020                                 break;
3021                         case 2:
3022                                 mtd->oobsize = 218;
3023                                 break;
3024                         case 3:
3025                                 mtd->oobsize = 400;
3026                                 break;
3027                         default:
3028                                 mtd->oobsize = 436;
3029                                 break;
3030                         }
3031                         extid >>= 2;
3032                         /* Calc blocksize */
3033                         mtd->erasesize = (128 * 1024) <<
3034                                 (((extid >> 1) & 0x04) | (extid & 0x03));
3035                         busw = 0;
3036                 } else {
3037                         /* Calc pagesize */
3038                         mtd->writesize = 1024 << (extid & 0x03);
3039                         extid >>= 2;
3040                         /* Calc oobsize */
3041                         mtd->oobsize = (8 << (extid & 0x01)) *
3042                                 (mtd->writesize >> 9);
3043                         extid >>= 2;
3044                         /* Calc blocksize. Blocksize is multiples of 64KiB */
3045                         mtd->erasesize = (64 * 1024) << (extid & 0x03);
3046                         extid >>= 2;
3047                         /* Get buswidth information */
3048                         busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3049                 }
3050         } else {
3051                 /*
3052                  * Old devices have chip data hardcoded in the device id table.
3053                  */
3054                 mtd->erasesize = type->erasesize;
3055                 mtd->writesize = type->pagesize;
3056                 mtd->oobsize = mtd->writesize / 32;
3057                 busw = type->options & NAND_BUSWIDTH_16;
3058
3059                 /*
3060                  * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3061                  * some Spansion chips have erasesize that conflicts with size
3062                  * listed in nand_ids table.
3063                  * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3064                  */
3065                 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3066                                 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3067                                 id_data[7] == 0x00 && mtd->writesize == 512) {
3068                         mtd->erasesize = 128 * 1024;
3069                         mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3070                 }
3071         }
3072         /* Get chip options, preserve non chip based options */
3073         chip->options &= ~NAND_CHIPOPTIONS_MSK;
3074         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3075
3076         /*
3077          * Check if chip is not a Samsung device. Do not clear the
3078          * options for chips which do not have an extended id.
3079          */
3080         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3081                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3082 ident_done:
3083
3084         /*
3085          * Set chip as a default. Board drivers can override it, if necessary.
3086          */
3087         chip->options |= NAND_NO_AUTOINCR;
3088
3089         /* Try to identify manufacturer */
3090         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3091                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3092                         break;
3093         }
3094
3095         /*
3096          * Check, if buswidth is correct. Hardware drivers should set
3097          * chip correct!
3098          */
3099         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3100                 pr_info("NAND device: Manufacturer ID:"
3101                         " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3102                         *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3103                 pr_warn("NAND bus width %d instead %d bit\n",
3104                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3105                            busw ? 16 : 8);
3106                 return ERR_PTR(-EINVAL);
3107         }
3108
3109         /* Calculate the address shift from the page size */
3110         chip->page_shift = ffs(mtd->writesize) - 1;
3111         /* Convert chipsize to number of pages per chip -1 */
3112         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3113
3114         chip->bbt_erase_shift = chip->phys_erase_shift =
3115                 ffs(mtd->erasesize) - 1;
3116         if (chip->chipsize & 0xffffffff)
3117                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3118         else {
3119                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3120                 chip->chip_shift += 32 - 1;
3121         }
3122
3123         chip->badblockbits = 8;
3124
3125         /* Set the bad block position */
3126         if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3127                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3128         else
3129                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3130
3131         /*
3132          * Bad block marker is stored in the last page of each block
3133          * on Samsung and Hynix MLC devices; stored in first two pages
3134          * of each block on Micron devices with 2KiB pages and on
3135          * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3136          * only the first page.
3137          */
3138         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3139                         (*maf_id == NAND_MFR_SAMSUNG ||
3140                          *maf_id == NAND_MFR_HYNIX))
3141                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3142         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3143                                 (*maf_id == NAND_MFR_SAMSUNG ||
3144                                  *maf_id == NAND_MFR_HYNIX ||
3145                                  *maf_id == NAND_MFR_TOSHIBA ||
3146                                  *maf_id == NAND_MFR_AMD)) ||
3147                         (mtd->writesize == 2048 &&
3148                          *maf_id == NAND_MFR_MICRON))
3149                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3150
3151         /* Check for AND chips with 4 page planes */
3152         if (chip->options & NAND_4PAGE_ARRAY)
3153                 chip->erase_cmd = multi_erase_cmd;
3154         else
3155                 chip->erase_cmd = single_erase_cmd;
3156
3157         /* Do not replace user supplied command function! */
3158         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3159                 chip->cmdfunc = nand_command_lp;
3160
3161         pr_info("NAND device: Manufacturer ID:"
3162                 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3163                 nand_manuf_ids[maf_idx].name,
3164                 chip->onfi_version ? chip->onfi_params.model : type->name);
3165
3166         return type;
3167 }
3168
3169 /**
3170  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3171  * @mtd: MTD device structure
3172  * @maxchips: number of chips to scan for
3173  * @table: alternative NAND ID table
3174  *
3175  * This is the first phase of the normal nand_scan() function. It reads the
3176  * flash ID and sets up MTD fields accordingly.
3177  *
3178  * The mtd->owner field must be set to the module of the caller.
3179  */
3180 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3181                     struct nand_flash_dev *table)
3182 {
3183         int i, busw, nand_maf_id, nand_dev_id;
3184         struct nand_chip *chip = mtd->priv;
3185         struct nand_flash_dev *type;
3186
3187         /* Get buswidth to select the correct functions */
3188         busw = chip->options & NAND_BUSWIDTH_16;
3189         /* Set the default functions */
3190         nand_set_defaults(chip, busw);
3191
3192         /* Read the flash type */
3193         type = nand_get_flash_type(mtd, chip, busw,
3194                                 &nand_maf_id, &nand_dev_id, table);
3195
3196         if (IS_ERR(type)) {
3197                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3198                         pr_warn("No NAND device found\n");
3199                 chip->select_chip(mtd, -1);
3200                 return PTR_ERR(type);
3201         }
3202
3203         /* Check for a chip array */
3204         for (i = 1; i < maxchips; i++) {
3205                 chip->select_chip(mtd, i);
3206                 /* See comment in nand_get_flash_type for reset */
3207                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3208                 /* Send the command for reading device ID */
3209                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3210                 /* Read manufacturer and device IDs */
3211                 if (nand_maf_id != chip->read_byte(mtd) ||
3212                     nand_dev_id != chip->read_byte(mtd))
3213                         break;
3214         }
3215         if (i > 1)
3216                 pr_info("%d NAND chips detected\n", i);
3217
3218         /* Store the number of chips and calc total size for mtd */
3219         chip->numchips = i;
3220         mtd->size = i * chip->chipsize;
3221
3222         return 0;
3223 }
3224 EXPORT_SYMBOL(nand_scan_ident);
3225
3226
3227 /**
3228  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3229  * @mtd: MTD device structure
3230  *
3231  * This is the second phase of the normal nand_scan() function. It fills out
3232  * all the uninitialized function pointers with the defaults and scans for a
3233  * bad block table if appropriate.
3234  */
3235 int nand_scan_tail(struct mtd_info *mtd)
3236 {
3237         int i;
3238         struct nand_chip *chip = mtd->priv;
3239
3240         if (!(chip->options & NAND_OWN_BUFFERS))
3241                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3242         if (!chip->buffers)
3243                 return -ENOMEM;
3244
3245         /* Set the internal oob buffer location, just after the page data */
3246         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3247
3248         /*
3249          * If no default placement scheme is given, select an appropriate one.
3250          */
3251         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3252                 switch (mtd->oobsize) {
3253                 case 8:
3254                         chip->ecc.layout = &nand_oob_8;
3255                         break;
3256                 case 16:
3257                         chip->ecc.layout = &nand_oob_16;
3258                         break;
3259                 case 64:
3260                         chip->ecc.layout = &nand_oob_64;
3261                         break;
3262                 case 128:
3263                         chip->ecc.layout = &nand_oob_128;
3264                         break;
3265                 default:
3266                         pr_warn("No oob scheme defined for oobsize %d\n",
3267                                    mtd->oobsize);
3268                         BUG();
3269                 }
3270         }
3271
3272         if (!chip->write_page)
3273                 chip->write_page = nand_write_page;
3274
3275         /*
3276          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3277          * selected and we have 256 byte pagesize fallback to software ECC
3278          */
3279
3280         switch (chip->ecc.mode) {
3281         case NAND_ECC_HW_OOB_FIRST:
3282                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3283                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3284                      !chip->ecc.hwctl) {
3285                         pr_warn("No ECC functions supplied; "
3286                                    "hardware ECC not possible\n");
3287                         BUG();
3288                 }
3289                 if (!chip->ecc.read_page)
3290                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3291
3292         case NAND_ECC_HW:
3293                 /* Use standard hwecc read page function? */
3294                 if (!chip->ecc.read_page)
3295                         chip->ecc.read_page = nand_read_page_hwecc;
3296                 if (!chip->ecc.write_page)
3297                         chip->ecc.write_page = nand_write_page_hwecc;
3298                 if (!chip->ecc.read_page_raw)
3299                         chip->ecc.read_page_raw = nand_read_page_raw;
3300                 if (!chip->ecc.write_page_raw)
3301                         chip->ecc.write_page_raw = nand_write_page_raw;
3302                 if (!chip->ecc.read_oob)
3303                         chip->ecc.read_oob = nand_read_oob_std;
3304                 if (!chip->ecc.write_oob)
3305                         chip->ecc.write_oob = nand_write_oob_std;
3306
3307         case NAND_ECC_HW_SYNDROME:
3308                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3309                      !chip->ecc.hwctl) &&
3310                     (!chip->ecc.read_page ||
3311                      chip->ecc.read_page == nand_read_page_hwecc ||
3312                      !chip->ecc.write_page ||
3313                      chip->ecc.write_page == nand_write_page_hwecc)) {
3314                         pr_warn("No ECC functions supplied; "
3315                                    "hardware ECC not possible\n");
3316                         BUG();
3317                 }
3318                 /* Use standard syndrome read/write page function? */
3319                 if (!chip->ecc.read_page)
3320                         chip->ecc.read_page = nand_read_page_syndrome;
3321                 if (!chip->ecc.write_page)
3322                         chip->ecc.write_page = nand_write_page_syndrome;
3323                 if (!chip->ecc.read_page_raw)
3324                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3325                 if (!chip->ecc.write_page_raw)
3326                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3327                 if (!chip->ecc.read_oob)
3328                         chip->ecc.read_oob = nand_read_oob_syndrome;
3329                 if (!chip->ecc.write_oob)
3330                         chip->ecc.write_oob = nand_write_oob_syndrome;
3331
3332                 if (mtd->writesize >= chip->ecc.size)
3333                         break;
3334                 pr_warn("%d byte HW ECC not possible on "
3335                            "%d byte page size, fallback to SW ECC\n",
3336                            chip->ecc.size, mtd->writesize);
3337                 chip->ecc.mode = NAND_ECC_SOFT;
3338
3339         case NAND_ECC_SOFT:
3340                 chip->ecc.calculate = nand_calculate_ecc;
3341                 chip->ecc.correct = nand_correct_data;
3342                 chip->ecc.read_page = nand_read_page_swecc;
3343                 chip->ecc.read_subpage = nand_read_subpage;
3344                 chip->ecc.write_page = nand_write_page_swecc;
3345                 chip->ecc.read_page_raw = nand_read_page_raw;
3346                 chip->ecc.write_page_raw = nand_write_page_raw;
3347                 chip->ecc.read_oob = nand_read_oob_std;
3348                 chip->ecc.write_oob = nand_write_oob_std;
3349                 if (!chip->ecc.size)
3350                         chip->ecc.size = 256;
3351                 chip->ecc.bytes = 3;
3352                 break;
3353
3354         case NAND_ECC_SOFT_BCH:
3355                 if (!mtd_nand_has_bch()) {
3356                         pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3357                         BUG();
3358                 }
3359                 chip->ecc.calculate = nand_bch_calculate_ecc;
3360                 chip->ecc.correct = nand_bch_correct_data;
3361                 chip->ecc.read_page = nand_read_page_swecc;
3362                 chip->ecc.read_subpage = nand_read_subpage;
3363                 chip->ecc.write_page = nand_write_page_swecc;
3364                 chip->ecc.read_page_raw = nand_read_page_raw;
3365                 chip->ecc.write_page_raw = nand_write_page_raw;
3366                 chip->ecc.read_oob = nand_read_oob_std;
3367                 chip->ecc.write_oob = nand_write_oob_std;
3368                 /*
3369                  * Board driver should supply ecc.size and ecc.bytes values to
3370                  * select how many bits are correctable; see nand_bch_init()
3371                  * for details. Otherwise, default to 4 bits for large page
3372                  * devices.
3373                  */
3374                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3375                         chip->ecc.size = 512;
3376                         chip->ecc.bytes = 7;
3377                 }
3378                 chip->ecc.priv = nand_bch_init(mtd,
3379                                                chip->ecc.size,
3380                                                chip->ecc.bytes,
3381                                                &chip->ecc.layout);
3382                 if (!chip->ecc.priv) {
3383                         pr_warn("BCH ECC initialization failed!\n");
3384                         BUG();
3385                 }
3386                 break;
3387
3388         case NAND_ECC_NONE:
3389                 pr_warn("NAND_ECC_NONE selected by board driver. "
3390                            "This is not recommended!\n");
3391                 chip->ecc.read_page = nand_read_page_raw;
3392                 chip->ecc.write_page = nand_write_page_raw;
3393                 chip->ecc.read_oob = nand_read_oob_std;
3394                 chip->ecc.read_page_raw = nand_read_page_raw;
3395                 chip->ecc.write_page_raw = nand_write_page_raw;
3396                 chip->ecc.write_oob = nand_write_oob_std;
3397                 chip->ecc.size = mtd->writesize;
3398                 chip->ecc.bytes = 0;
3399                 break;
3400
3401         default:
3402                 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3403                 BUG();
3404         }
3405
3406         /* For many systems, the standard OOB write also works for raw */
3407         if (!chip->ecc.read_oob_raw)
3408                 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3409         if (!chip->ecc.write_oob_raw)
3410                 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3411
3412         /*
3413          * The number of bytes available for a client to place data into
3414          * the out of band area.
3415          */
3416         chip->ecc.layout->oobavail = 0;
3417         for (i = 0; chip->ecc.layout->oobfree[i].length
3418                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3419                 chip->ecc.layout->oobavail +=
3420                         chip->ecc.layout->oobfree[i].length;
3421         mtd->oobavail = chip->ecc.layout->oobavail;
3422
3423         /*
3424          * Set the number of read / write steps for one page depending on ECC
3425          * mode.
3426          */
3427         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3428         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3429                 pr_warn("Invalid ECC parameters\n");
3430                 BUG();
3431         }
3432         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3433
3434         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3435         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3436             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3437                 switch (chip->ecc.steps) {
3438                 case 2:
3439                         mtd->subpage_sft = 1;
3440                         break;
3441                 case 4:
3442                 case 8:
3443                 case 16:
3444                         mtd->subpage_sft = 2;
3445                         break;
3446                 }
3447         }
3448         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3449
3450         /* Initialize state */
3451         chip->state = FL_READY;
3452
3453         /* De-select the device */
3454         chip->select_chip(mtd, -1);
3455
3456         /* Invalidate the pagebuffer reference */
3457         chip->pagebuf = -1;
3458
3459         /* Fill in remaining MTD driver data */
3460         mtd->type = MTD_NANDFLASH;
3461         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3462                                                 MTD_CAP_NANDFLASH;
3463         mtd->erase = nand_erase;
3464         mtd->point = NULL;
3465         mtd->unpoint = NULL;
3466         mtd->read = nand_read;
3467         mtd->write = nand_write;
3468         mtd->panic_write = panic_nand_write;
3469         mtd->read_oob = nand_read_oob;
3470         mtd->write_oob = nand_write_oob;
3471         mtd->sync = nand_sync;
3472         mtd->lock = NULL;
3473         mtd->unlock = NULL;
3474         mtd->suspend = nand_suspend;
3475         mtd->resume = nand_resume;
3476         mtd->block_isbad = nand_block_isbad;
3477         mtd->block_markbad = nand_block_markbad;
3478         mtd->writebufsize = mtd->writesize;
3479
3480         /* propagate ecc.layout to mtd_info */
3481         mtd->ecclayout = chip->ecc.layout;
3482
3483         /* Check, if we should skip the bad block table scan */
3484         if (chip->options & NAND_SKIP_BBTSCAN)
3485                 return 0;
3486
3487         /* Build bad block table */
3488         return chip->scan_bbt(mtd);
3489 }
3490 EXPORT_SYMBOL(nand_scan_tail);
3491
3492 /*
3493  * is_module_text_address() isn't exported, and it's mostly a pointless
3494  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3495  * to call us from in-kernel code if the core NAND support is modular.
3496  */
3497 #ifdef MODULE
3498 #define caller_is_module() (1)
3499 #else
3500 #define caller_is_module() \
3501         is_module_text_address((unsigned long)__builtin_return_address(0))
3502 #endif
3503
3504 /**
3505  * nand_scan - [NAND Interface] Scan for the NAND device
3506  * @mtd: MTD device structure
3507  * @maxchips: number of chips to scan for
3508  *
3509  * This fills out all the uninitialized function pointers with the defaults.
3510  * The flash ID is read and the mtd/chip structures are filled with the
3511  * appropriate values. The mtd->owner field must be set to the module of the
3512  * caller.
3513  */
3514 int nand_scan(struct mtd_info *mtd, int maxchips)
3515 {
3516         int ret;
3517
3518         /* Many callers got this wrong, so check for it for a while... */
3519         if (!mtd->owner && caller_is_module()) {
3520                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3521                 BUG();
3522         }
3523
3524         ret = nand_scan_ident(mtd, maxchips, NULL);
3525         if (!ret)
3526                 ret = nand_scan_tail(mtd);
3527         return ret;
3528 }
3529 EXPORT_SYMBOL(nand_scan);
3530
3531 /**
3532  * nand_release - [NAND Interface] Free resources held by the NAND device
3533  * @mtd: MTD device structure
3534  */
3535 void nand_release(struct mtd_info *mtd)
3536 {
3537         struct nand_chip *chip = mtd->priv;
3538
3539         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3540                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3541
3542         mtd_device_unregister(mtd);
3543
3544         /* Free bad block table memory */
3545         kfree(chip->bbt);
3546         if (!(chip->options & NAND_OWN_BUFFERS))
3547                 kfree(chip->buffers);
3548
3549         /* Free bad block descriptor memory */
3550         if (chip->badblock_pattern && chip->badblock_pattern->options
3551                         & NAND_BBT_DYNAMICSTRUCT)
3552                 kfree(chip->badblock_pattern);
3553 }
3554 EXPORT_SYMBOL_GPL(nand_release);
3555
3556 static int __init nand_base_init(void)
3557 {
3558         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3559         return 0;
3560 }
3561
3562 static void __exit nand_base_exit(void)
3563 {
3564         led_trigger_unregister_simple(nand_led_trigger);
3565 }
3566
3567 module_init(nand_base_init);
3568 module_exit(nand_base_exit);
3569
3570 MODULE_LICENSE("GPL");
3571 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3572 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3573 MODULE_DESCRIPTION("Generic NAND flash driver code");