drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ECC support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 /* Define default oob placement schemes for large and small page devices */
  53 static struct nand_ecclayout nand_oob_8 = {
  54         .eccbytes = 3,
  55         .eccpos = {0, 1, 2},
  56         .oobfree = {
  57                 {.offset = 3,
  58                  .length = 2},
  59                 {.offset = 6,
  60                  .length = 2} }
  61 };
  62
  63 static struct nand_ecclayout nand_oob_16 = {
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {
  67                 {.offset = 8,
  68                  . length = 8} }
  69 };
  70
  71 static struct nand_ecclayout nand_oob_64 = {
  72         .eccbytes = 24,
  73         .eccpos = {
  74                    40, 41, 42, 43, 44, 45, 46, 47,
  75                    48, 49, 50, 51, 52, 53, 54, 55,
  76                    56, 57, 58, 59, 60, 61, 62, 63},
  77         .oobfree = {
  78                 {.offset = 2,
  79                  .length = 38} }
  80 };
  81
  82 static struct nand_ecclayout nand_oob_128 = {
  83         .eccbytes = 48,
  84         .eccpos = {
  85                    80, 81, 82, 83, 84, 85, 86, 87,
  86                    88, 89, 90, 91, 92, 93, 94, 95,
  87                    96, 97, 98, 99, 100, 101, 102, 103,
  88                    104, 105, 106, 107, 108, 109, 110, 111,
  89                    112, 113, 114, 115, 116, 117, 118, 119,
  90                    120, 121, 122, 123, 124, 125, 126, 127},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 78} }
  94 };
  95
  96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  97                            int new_state);
  98
  99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 100                              struct mtd_oob_ops *ops);
 101
 102 /*
 103  * For devices which display every fart in the system on a separate LED. Is
 104  * compiled away when LED support is disabled.
 105  */
 106 DEFINE_LED_TRIGGER(nand_led_trigger);
 107
 108 static int check_offs_len(struct mtd_info *mtd,
 109                                         loff_t ofs, uint64_t len)
 110 {
 111         struct nand_chip *chip = mtd->priv;
 112         int ret = 0;
 113
 114         /* Start address must align on block boundary */
 115         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 116                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
 117                 ret = -EINVAL;
 118         }
 119
 120         /* Length must align on block boundary */
 121         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 122                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
 123                                         __func__);
 124                 ret = -EINVAL;
 125         }
 126
 127         /* Do not allow past end of device */
 128         if (ofs + len > mtd->size) {
 129                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
 130                                         __func__);
 131                 ret = -EINVAL;
 132         }
 133
 134         return ret;
 135 }
 136
 137 /**
 138  * nand_release_device - [GENERIC] release chip
 139  * @mtd: MTD device structure
 140  *
 141  * Deselect, release chip lock and wake up anyone waiting on the device.
 142  */
 143 static void nand_release_device(struct mtd_info *mtd)
 144 {
 145         struct nand_chip *chip = mtd->priv;
 146
 147         /* De-select the NAND device */
 148         chip->select_chip(mtd, -1);
 149
 150         /* Release the controller and the chip */
 151         spin_lock(&chip->controller->lock);
 152         chip->controller->active = NULL;
 153         chip->state = FL_READY;
 154         wake_up(&chip->controller->wq);
 155         spin_unlock(&chip->controller->lock);
 156 }
 157
 158 /**
 159  * nand_read_byte - [DEFAULT] read one byte from the chip
 160  * @mtd: MTD device structure
 161  *
 162  * Default read function for 8bit buswidth
 163  */
 164 static uint8_t nand_read_byte(struct mtd_info *mtd)
 165 {
 166         struct nand_chip *chip = mtd->priv;
 167         return readb(chip->IO_ADDR_R);
 168 }
 169
 170 /**
 171  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 172  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 173  * @mtd: MTD device structure
 174  *
 175  * Default read function for 16bit buswidth with endianness conversion.
 176  *
 177  */
 178 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 179 {
 180         struct nand_chip *chip = mtd->priv;
 181         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 182 }
 183
 184 /**
 185  * nand_read_word - [DEFAULT] read one word from the chip
 186  * @mtd: MTD device structure
 187  *
 188  * Default read function for 16bit buswidth without endianness conversion.
 189  */
 190 static u16 nand_read_word(struct mtd_info *mtd)
 191 {
 192         struct nand_chip *chip = mtd->priv;
 193         return readw(chip->IO_ADDR_R);
 194 }
 195
 196 /**
 197  * nand_select_chip - [DEFAULT] control CE line
 198  * @mtd: MTD device structure
 199  * @chipnr: chipnumber to select, -1 for deselect
 200  *
 201  * Default select function for 1 chip devices.
 202  */
 203 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 204 {
 205         struct nand_chip *chip = mtd->priv;
 206
 207         switch (chipnr) {
 208         case -1:
 209                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 210                 break;
 211         case 0:
 212                 break;
 213
 214         default:
 215                 BUG();
 216         }
 217 }
 218
 219 /**
 220  * nand_write_buf - [DEFAULT] write buffer to chip
 221  * @mtd: MTD device structure
 222  * @buf: data buffer
 223  * @len: number of bytes to write
 224  *
 225  * Default write function for 8bit buswidth.
 226  */
 227 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 228 {
 229         int i;
 230         struct nand_chip *chip = mtd->priv;
 231
 232         for (i = 0; i < len; i++)
 233                 writeb(buf[i], chip->IO_ADDR_W);
 234 }
 235
 236 /**
 237  * nand_read_buf - [DEFAULT] read chip data into buffer
 238  * @mtd: MTD device structure
 239  * @buf: buffer to store date
 240  * @len: number of bytes to read
 241  *
 242  * Default read function for 8bit buswidth.
 243  */
 244 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 245 {
 246         int i;
 247         struct nand_chip *chip = mtd->priv;
 248
 249         for (i = 0; i < len; i++)
 250                 buf[i] = readb(chip->IO_ADDR_R);
 251 }
 252
 253 /**
 254  * nand_verify_buf - [DEFAULT] Verify chip data against buffer
 255  * @mtd: MTD device structure
 256  * @buf: buffer containing the data to compare
 257  * @len: number of bytes to compare
 258  *
 259  * Default verify function for 8bit buswidth.
 260  */
 261 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 262 {
 263         int i;
 264         struct nand_chip *chip = mtd->priv;
 265
 266         for (i = 0; i < len; i++)
 267                 if (buf[i] != readb(chip->IO_ADDR_R))
 268                         return -EFAULT;
 269         return 0;
 270 }
 271
 272 /**
 273  * nand_write_buf16 - [DEFAULT] write buffer to chip
 274  * @mtd: MTD device structure
 275  * @buf: data buffer
 276  * @len: number of bytes to write
 277  *
 278  * Default write function for 16bit buswidth.
 279  */
 280 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 281 {
 282         int i;
 283         struct nand_chip *chip = mtd->priv;
 284         u16 *p = (u16 *) buf;
 285         len >>= 1;
 286
 287         for (i = 0; i < len; i++)
 288                 writew(p[i], chip->IO_ADDR_W);
 289
 290 }
 291
 292 /**
 293  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 294  * @mtd: MTD device structure
 295  * @buf: buffer to store date
 296  * @len: number of bytes to read
 297  *
 298  * Default read function for 16bit buswidth.
 299  */
 300 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 301 {
 302         int i;
 303         struct nand_chip *chip = mtd->priv;
 304         u16 *p = (u16 *) buf;
 305         len >>= 1;
 306
 307         for (i = 0; i < len; i++)
 308                 p[i] = readw(chip->IO_ADDR_R);
 309 }
 310
 311 /**
 312  * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
 313  * @mtd: MTD device structure
 314  * @buf: buffer containing the data to compare
 315  * @len: number of bytes to compare
 316  *
 317  * Default verify function for 16bit buswidth.
 318  */
 319 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 320 {
 321         int i;
 322         struct nand_chip *chip = mtd->priv;
 323         u16 *p = (u16 *) buf;
 324         len >>= 1;
 325
 326         for (i = 0; i < len; i++)
 327                 if (p[i] != readw(chip->IO_ADDR_R))
 328                         return -EFAULT;
 329
 330         return 0;
 331 }
 332
 333 /**
 334  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 335  * @mtd: MTD device structure
 336  * @ofs: offset from device start
 337  * @getchip: 0, if the chip is already selected
 338  *
 339  * Check, if the block is bad.
 340  */
 341 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 342 {
 343         int page, chipnr, res = 0;
 344         struct nand_chip *chip = mtd->priv;
 345         u16 bad;
 346
 347         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 348                 ofs += mtd->erasesize - mtd->writesize;
 349
 350         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 351
 352         if (getchip) {
 353                 chipnr = (int)(ofs >> chip->chip_shift);
 354
 355                 nand_get_device(chip, mtd, FL_READING);
 356
 357                 /* Select the NAND device */
 358                 chip->select_chip(mtd, chipnr);
 359         }
 360
 361         if (chip->options & NAND_BUSWIDTH_16) {
 362                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
 363                               page);
 364                 bad = cpu_to_le16(chip->read_word(mtd));
 365                 if (chip->badblockpos & 0x1)
 366                         bad >>= 8;
 367                 else
 368                         bad &= 0xFF;
 369         } else {
 370                 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
 371                 bad = chip->read_byte(mtd);
 372         }
 373
 374         if (likely(chip->badblockbits == 8))
 375                 res = bad != 0xFF;
 376         else
 377                 res = hweight8(bad) < chip->badblockbits;
 378
 379         if (getchip)
 380                 nand_release_device(mtd);
 381
 382         return res;
 383 }
 384
 385 /**
 386  * nand_default_block_markbad - [DEFAULT] mark a block bad
 387  * @mtd: MTD device structure
 388  * @ofs: offset from device start
 389  *
 390  * This is the default implementation, which can be overridden by a hardware
 391  * specific driver.
 392 */
 393 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 394 {
 395         struct nand_chip *chip = mtd->priv;
 396         uint8_t buf[2] = { 0, 0 };
 397         int block, ret, i = 0;
 398
 399         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 400                 ofs += mtd->erasesize - mtd->writesize;
 401
 402         /* Get block number */
 403         block = (int)(ofs >> chip->bbt_erase_shift);
 404         if (chip->bbt)
 405                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 406
 407         /* Do we have a flash based bad block table? */
 408         if (chip->bbt_options & NAND_BBT_USE_FLASH)
 409                 ret = nand_update_bbt(mtd, ofs);
 410         else {
 411                 nand_get_device(chip, mtd, FL_WRITING);
 412
 413                 /*
 414                  * Write to first two pages if necessary. If we write to more
 415                  * than one location, the first error encountered quits the
 416                  * procedure. We write two bytes per location, so we dont have
 417                  * to mess with 16 bit access.
 418                  */
 419                 do {
 420                         chip->ops.len = chip->ops.ooblen = 2;
 421                         chip->ops.datbuf = NULL;
 422                         chip->ops.oobbuf = buf;
 423                         chip->ops.ooboffs = chip->badblockpos & ~0x01;
 424
 425                         ret = nand_do_write_oob(mtd, ofs, &chip->ops);
 426
 427                         i++;
 428                         ofs += mtd->writesize;
 429                 } while (!ret && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE) &&
 430                                 i < 2);
 431
 432                 nand_release_device(mtd);
 433         }
 434         if (!ret)
 435                 mtd->ecc_stats.badblocks++;
 436
 437         return ret;
 438 }
 439
 440 /**
 441  * nand_check_wp - [GENERIC] check if the chip is write protected
 442  * @mtd: MTD device structure
 443  *
 444  * Check, if the device is write protected. The function expects, that the
 445  * device is already selected.
 446  */
 447 static int nand_check_wp(struct mtd_info *mtd)
 448 {
 449         struct nand_chip *chip = mtd->priv;
 450
 451         /* Broken xD cards report WP despite being writable */
 452         if (chip->options & NAND_BROKEN_XD)
 453                 return 0;
 454
 455         /* Check the WP bit */
 456         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 457         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 458 }
 459
 460 /**
 461  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 462  * @mtd: MTD device structure
 463  * @ofs: offset from device start
 464  * @getchip: 0, if the chip is already selected
 465  * @allowbbt: 1, if its allowed to access the bbt area
 466  *
 467  * Check, if the block is bad. Either by reading the bad block table or
 468  * calling of the scan function.
 469  */
 470 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 471                                int allowbbt)
 472 {
 473         struct nand_chip *chip = mtd->priv;
 474
 475         if (!chip->bbt)
 476                 return chip->block_bad(mtd, ofs, getchip);
 477
 478         /* Return info from the table */
 479         return nand_isbad_bbt(mtd, ofs, allowbbt);
 480 }
 481
 482 /**
 483  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 484  * @mtd: MTD device structure
 485  * @timeo: Timeout
 486  *
 487  * Helper function for nand_wait_ready used when needing to wait in interrupt
 488  * context.
 489  */
 490 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 491 {
 492         struct nand_chip *chip = mtd->priv;
 493         int i;
 494
 495         /* Wait for the device to get ready */
 496         for (i = 0; i < timeo; i++) {
 497                 if (chip->dev_ready(mtd))
 498                         break;
 499                 touch_softlockup_watchdog();
 500                 mdelay(1);
 501         }
 502 }
 503
 504 /* Wait for the ready pin, after a command. The timeout is caught later. */
 505 void nand_wait_ready(struct mtd_info *mtd)
 506 {
 507         struct nand_chip *chip = mtd->priv;
 508         unsigned long timeo = jiffies + 2;
 509
 510         /* 400ms timeout */
 511         if (in_interrupt() || oops_in_progress)
 512                 return panic_nand_wait_ready(mtd, 400);
 513
 514         led_trigger_event(nand_led_trigger, LED_FULL);
 515         /* Wait until command is processed or timeout occurs */
 516         do {
 517                 if (chip->dev_ready(mtd))
 518                         break;
 519                 touch_softlockup_watchdog();
 520         } while (time_before(jiffies, timeo));
 521         led_trigger_event(nand_led_trigger, LED_OFF);
 522 }
 523 EXPORT_SYMBOL_GPL(nand_wait_ready);
 524
 525 /**
 526  * nand_command - [DEFAULT] Send command to NAND device
 527  * @mtd: MTD device structure
 528  * @command: the command to be sent
 529  * @column: the column address for this command, -1 if none
 530  * @page_addr: the page address for this command, -1 if none
 531  *
 532  * Send command to NAND device. This function is used for small page devices
 533  * (256/512 Bytes per page).
 534  */
 535 static void nand_command(struct mtd_info *mtd, unsigned int command,
 536                          int column, int page_addr)
 537 {
 538         register struct nand_chip *chip = mtd->priv;
 539         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 540
 541         /* Write out the command to the device */
 542         if (command == NAND_CMD_SEQIN) {
 543                 int readcmd;
 544
 545                 if (column >= mtd->writesize) {
 546                         /* OOB area */
 547                         column -= mtd->writesize;
 548                         readcmd = NAND_CMD_READOOB;
 549                 } else if (column < 256) {
 550                         /* First 256 bytes --> READ0 */
 551                         readcmd = NAND_CMD_READ0;
 552                 } else {
 553                         column -= 256;
 554                         readcmd = NAND_CMD_READ1;
 555                 }
 556                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 557                 ctrl &= ~NAND_CTRL_CHANGE;
 558         }
 559         chip->cmd_ctrl(mtd, command, ctrl);
 560
 561         /* Address cycle, when necessary */
 562         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 563         /* Serially input address */
 564         if (column != -1) {
 565                 /* Adjust columns for 16 bit buswidth */
 566                 if (chip->options & NAND_BUSWIDTH_16)
 567                         column >>= 1;
 568                 chip->cmd_ctrl(mtd, column, ctrl);
 569                 ctrl &= ~NAND_CTRL_CHANGE;
 570         }
 571         if (page_addr != -1) {
 572                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 573                 ctrl &= ~NAND_CTRL_CHANGE;
 574                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 575                 /* One more address cycle for devices > 32MiB */
 576                 if (chip->chipsize > (32 << 20))
 577                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 578         }
 579         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 580
 581         /*
 582          * Program and erase have their own busy handlers status and sequential
 583          * in needs no delay
 584          */
 585         switch (command) {
 586
 587         case NAND_CMD_PAGEPROG:
 588         case NAND_CMD_ERASE1:
 589         case NAND_CMD_ERASE2:
 590         case NAND_CMD_SEQIN:
 591         case NAND_CMD_STATUS:
 592                 return;
 593
 594         case NAND_CMD_RESET:
 595                 if (chip->dev_ready)
 596                         break;
 597                 udelay(chip->chip_delay);
 598                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 599                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 600                 chip->cmd_ctrl(mtd,
 601                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 602                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 603                                 ;
 604                 return;
 605
 606                 /* This applies to read commands */
 607         default:
 608                 /*
 609                  * If we don't have access to the busy pin, we apply the given
 610                  * command delay
 611                  */
 612                 if (!chip->dev_ready) {
 613                         udelay(chip->chip_delay);
 614                         return;
 615                 }
 616         }
 617         /*
 618          * Apply this short delay always to ensure that we do wait tWB in
 619          * any case on any machine.
 620          */
 621         ndelay(100);
 622
 623         nand_wait_ready(mtd);
 624 }
 625
 626 /**
 627  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 628  * @mtd: MTD device structure
 629  * @command: the command to be sent
 630  * @column: the column address for this command, -1 if none
 631  * @page_addr: the page address for this command, -1 if none
 632  *
 633  * Send command to NAND device. This is the version for the new large page
 634  * devices. We don't have the separate regions as we have in the small page
 635  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 636  */
 637 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 638                             int column, int page_addr)
 639 {
 640         register struct nand_chip *chip = mtd->priv;
 641
 642         /* Emulate NAND_CMD_READOOB */
 643         if (command == NAND_CMD_READOOB) {
 644                 column += mtd->writesize;
 645                 command = NAND_CMD_READ0;
 646         }
 647
 648         /* Command latch cycle */
 649         chip->cmd_ctrl(mtd, command & 0xff,
 650                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 651
 652         if (column != -1 || page_addr != -1) {
 653                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 654
 655                 /* Serially input address */
 656                 if (column != -1) {
 657                         /* Adjust columns for 16 bit buswidth */
 658                         if (chip->options & NAND_BUSWIDTH_16)
 659                                 column >>= 1;
 660                         chip->cmd_ctrl(mtd, column, ctrl);
 661                         ctrl &= ~NAND_CTRL_CHANGE;
 662                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 663                 }
 664                 if (page_addr != -1) {
 665                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 666                         chip->cmd_ctrl(mtd, page_addr >> 8,
 667                                        NAND_NCE | NAND_ALE);
 668                         /* One more address cycle for devices > 128MiB */
 669                         if (chip->chipsize > (128 << 20))
 670                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 671                                                NAND_NCE | NAND_ALE);
 672                 }
 673         }
 674         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 675
 676         /*
 677          * Program and erase have their own busy handlers status, sequential
 678          * in, and deplete1 need no delay.
 679          */
 680         switch (command) {
 681
 682         case NAND_CMD_CACHEDPROG:
 683         case NAND_CMD_PAGEPROG:
 684         case NAND_CMD_ERASE1:
 685         case NAND_CMD_ERASE2:
 686         case NAND_CMD_SEQIN:
 687         case NAND_CMD_RNDIN:
 688         case NAND_CMD_STATUS:
 689         case NAND_CMD_DEPLETE1:
 690                 return;
 691
 692         case NAND_CMD_STATUS_ERROR:
 693         case NAND_CMD_STATUS_ERROR0:
 694         case NAND_CMD_STATUS_ERROR1:
 695         case NAND_CMD_STATUS_ERROR2:
 696         case NAND_CMD_STATUS_ERROR3:
 697                 /* Read error status commands require only a short delay */
 698                 udelay(chip->chip_delay);
 699                 return;
 700
 701         case NAND_CMD_RESET:
 702                 if (chip->dev_ready)
 703                         break;
 704                 udelay(chip->chip_delay);
 705                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 706                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 707                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 708                                NAND_NCE | NAND_CTRL_CHANGE);
 709                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 710                                 ;
 711                 return;
 712
 713         case NAND_CMD_RNDOUT:
 714                 /* No ready / busy check necessary */
 715                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 716                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 717                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 718                                NAND_NCE | NAND_CTRL_CHANGE);
 719                 return;
 720
 721         case NAND_CMD_READ0:
 722                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 723                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 724                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 725                                NAND_NCE | NAND_CTRL_CHANGE);
 726
 727                 /* This applies to read commands */
 728         default:
 729                 /*
 730                  * If we don't have access to the busy pin, we apply the given
 731                  * command delay.
 732                  */
 733                 if (!chip->dev_ready) {
 734                         udelay(chip->chip_delay);
 735                         return;
 736                 }
 737         }
 738
 739         /*
 740          * Apply this short delay always to ensure that we do wait tWB in
 741          * any case on any machine.
 742          */
 743         ndelay(100);
 744
 745         nand_wait_ready(mtd);
 746 }
 747
 748 /**
 749  * panic_nand_get_device - [GENERIC] Get chip for selected access
 750  * @chip: the nand chip descriptor
 751  * @mtd: MTD device structure
 752  * @new_state: the state which is requested
 753  *
 754  * Used when in panic, no locks are taken.
 755  */
 756 static void panic_nand_get_device(struct nand_chip *chip,
 757                       struct mtd_info *mtd, int new_state)
 758 {
 759         /* Hardware controller shared among independent devices */
 760         chip->controller->active = chip;
 761         chip->state = new_state;
 762 }
 763
 764 /**
 765  * nand_get_device - [GENERIC] Get chip for selected access
 766  * @chip: the nand chip descriptor
 767  * @mtd: MTD device structure
 768  * @new_state: the state which is requested
 769  *
 770  * Get the device and lock it for exclusive access
 771  */
 772 static int
 773 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 774 {
 775         spinlock_t *lock = &chip->controller->lock;
 776         wait_queue_head_t *wq = &chip->controller->wq;
 777         DECLARE_WAITQUEUE(wait, current);
 778 retry:
 779         spin_lock(lock);
 780
 781         /* Hardware controller shared among independent devices */
 782         if (!chip->controller->active)
 783                 chip->controller->active = chip;
 784
 785         if (chip->controller->active == chip && chip->state == FL_READY) {
 786                 chip->state = new_state;
 787                 spin_unlock(lock);
 788                 return 0;
 789         }
 790         if (new_state == FL_PM_SUSPENDED) {
 791                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 792                         chip->state = FL_PM_SUSPENDED;
 793                         spin_unlock(lock);
 794                         return 0;
 795                 }
 796         }
 797         set_current_state(TASK_UNINTERRUPTIBLE);
 798         add_wait_queue(wq, &wait);
 799         spin_unlock(lock);
 800         schedule();
 801         remove_wait_queue(wq, &wait);
 802         goto retry;
 803 }
 804
 805 /**
 806  * panic_nand_wait - [GENERIC] wait until the command is done
 807  * @mtd: MTD device structure
 808  * @chip: NAND chip structure
 809  * @timeo: timeout
 810  *
 811  * Wait for command done. This is a helper function for nand_wait used when
 812  * we are in interrupt context. May happen when in panic and trying to write
 813  * an oops through mtdoops.
 814  */
 815 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 816                             unsigned long timeo)
 817 {
 818         int i;
 819         for (i = 0; i < timeo; i++) {
 820                 if (chip->dev_ready) {
 821                         if (chip->dev_ready(mtd))
 822                                 break;
 823                 } else {
 824                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 825                                 break;
 826                 }
 827                 mdelay(1);
 828         }
 829 }
 830
 831 /**
 832  * nand_wait - [DEFAULT] wait until the command is done
 833  * @mtd: MTD device structure
 834  * @chip: NAND chip structure
 835  *
 836  * Wait for command done. This applies to erase and program only. Erase can
 837  * take up to 400ms and program up to 20ms according to general NAND and
 838  * SmartMedia specs.
 839  */
 840 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 841 {
 842
 843         unsigned long timeo = jiffies;
 844         int status, state = chip->state;
 845
 846         if (state == FL_ERASING)
 847                 timeo += (HZ * 400) / 1000;
 848         else
 849                 timeo += (HZ * 20) / 1000;
 850
 851         led_trigger_event(nand_led_trigger, LED_FULL);
 852
 853         /*
 854          * Apply this short delay always to ensure that we do wait tWB in any
 855          * case on any machine.
 856          */
 857         ndelay(100);
 858
 859         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 860                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 861         else
 862                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 863
 864         if (in_interrupt() || oops_in_progress)
 865                 panic_nand_wait(mtd, chip, timeo);
 866         else {
 867                 while (time_before(jiffies, timeo)) {
 868                         if (chip->dev_ready) {
 869                                 if (chip->dev_ready(mtd))
 870                                         break;
 871                         } else {
 872                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 873                                         break;
 874                         }
 875                         cond_resched();
 876                 }
 877         }
 878         led_trigger_event(nand_led_trigger, LED_OFF);
 879
 880         status = (int)chip->read_byte(mtd);
 881         return status;
 882 }
 883
 884 /**
 885  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 886  * @mtd: mtd info
 887  * @ofs: offset to start unlock from
 888  * @len: length to unlock
 889  * @invert: when = 0, unlock the range of blocks within the lower and
 890  *                    upper boundary address
 891  *          when = 1, unlock the range of blocks outside the boundaries
 892  *                    of the lower and upper boundary address
 893  *
 894  * Returs unlock status.
 895  */
 896 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 897                                         uint64_t len, int invert)
 898 {
 899         int ret = 0;
 900         int status, page;
 901         struct nand_chip *chip = mtd->priv;
 902
 903         /* Submit address of first page to unlock */
 904         page = ofs >> chip->page_shift;
 905         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 906
 907         /* Submit address of last page to unlock */
 908         page = (ofs + len) >> chip->page_shift;
 909         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 910                                 (page | invert) & chip->pagemask);
 911
 912         /* Call wait ready function */
 913         status = chip->waitfunc(mtd, chip);
 914         /* See if device thinks it succeeded */
 915         if (status & 0x01) {
 916                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
 917                                         __func__, status);
 918                 ret = -EIO;
 919         }
 920
 921         return ret;
 922 }
 923
 924 /**
 925  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 926  * @mtd: mtd info
 927  * @ofs: offset to start unlock from
 928  * @len: length to unlock
 929  *
 930  * Returns unlock status.
 931  */
 932 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 933 {
 934         int ret = 0;
 935         int chipnr;
 936         struct nand_chip *chip = mtd->priv;
 937
 938         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 939                         __func__, (unsigned long long)ofs, len);
 940
 941         if (check_offs_len(mtd, ofs, len))
 942                 ret = -EINVAL;
 943
 944         /* Align to last block address if size addresses end of the device */
 945         if (ofs + len == mtd->size)
 946                 len -= mtd->erasesize;
 947
 948         nand_get_device(chip, mtd, FL_UNLOCKING);
 949
 950         /* Shift to get chip number */
 951         chipnr = ofs >> chip->chip_shift;
 952
 953         chip->select_chip(mtd, chipnr);
 954
 955         /* Check, if it is write protected */
 956         if (nand_check_wp(mtd)) {
 957                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
 958                                         __func__);
 959                 ret = -EIO;
 960                 goto out;
 961         }
 962
 963         ret = __nand_unlock(mtd, ofs, len, 0);
 964
 965 out:
 966         nand_release_device(mtd);
 967
 968         return ret;
 969 }
 970 EXPORT_SYMBOL(nand_unlock);
 971
 972 /**
 973  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 974  * @mtd: mtd info
 975  * @ofs: offset to start unlock from
 976  * @len: length to unlock
 977  *
 978  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 979  * have this feature, but it allows only to lock all blocks, not for specified
 980  * range for block. Implementing 'lock' feature by making use of 'unlock', for
 981  * now.
 982  *
 983  * Returns lock status.
 984  */
 985 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 986 {
 987         int ret = 0;
 988         int chipnr, status, page;
 989         struct nand_chip *chip = mtd->priv;
 990
 991         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
 992                         __func__, (unsigned long long)ofs, len);
 993
 994         if (check_offs_len(mtd, ofs, len))
 995                 ret = -EINVAL;
 996
 997         nand_get_device(chip, mtd, FL_LOCKING);
 998
 999         /* Shift to get chip number */
1000         chipnr = ofs >> chip->chip_shift;
1001
1002         chip->select_chip(mtd, chipnr);
1003
1004         /* Check, if it is write protected */
1005         if (nand_check_wp(mtd)) {
1006                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1007                                         __func__);
1008                 status = MTD_ERASE_FAILED;
1009                 ret = -EIO;
1010                 goto out;
1011         }
1012
1013         /* Submit address of first page to lock */
1014         page = ofs >> chip->page_shift;
1015         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1016
1017         /* Call wait ready function */
1018         status = chip->waitfunc(mtd, chip);
1019         /* See if device thinks it succeeded */
1020         if (status & 0x01) {
1021                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1022                                         __func__, status);
1023                 ret = -EIO;
1024                 goto out;
1025         }
1026
1027         ret = __nand_unlock(mtd, ofs, len, 0x1);
1028
1029 out:
1030         nand_release_device(mtd);
1031
1032         return ret;
1033 }
1034 EXPORT_SYMBOL(nand_lock);
1035
1036 /**
1037  * nand_read_page_raw - [INTERN] read raw page data without ecc
1038  * @mtd: mtd info structure
1039  * @chip: nand chip info structure
1040  * @buf: buffer to store read data
1041  * @page: page number to read
1042  *
1043  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1044  */
1045 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1046                               uint8_t *buf, int page)
1047 {
1048         chip->read_buf(mtd, buf, mtd->writesize);
1049         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1050         return 0;
1051 }
1052
1053 /**
1054  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1055  * @mtd: mtd info structure
1056  * @chip: nand chip info structure
1057  * @buf: buffer to store read data
1058  * @page: page number to read
1059  *
1060  * We need a special oob layout and handling even when OOB isn't used.
1061  */
1062 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1063                                         struct nand_chip *chip,
1064                                         uint8_t *buf, int page)
1065 {
1066         int eccsize = chip->ecc.size;
1067         int eccbytes = chip->ecc.bytes;
1068         uint8_t *oob = chip->oob_poi;
1069         int steps, size;
1070
1071         for (steps = chip->ecc.steps; steps > 0; steps--) {
1072                 chip->read_buf(mtd, buf, eccsize);
1073                 buf += eccsize;
1074
1075                 if (chip->ecc.prepad) {
1076                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1077                         oob += chip->ecc.prepad;
1078                 }
1079
1080                 chip->read_buf(mtd, oob, eccbytes);
1081                 oob += eccbytes;
1082
1083                 if (chip->ecc.postpad) {
1084                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1085                         oob += chip->ecc.postpad;
1086                 }
1087         }
1088
1089         size = mtd->oobsize - (oob - chip->oob_poi);
1090         if (size)
1091                 chip->read_buf(mtd, oob, size);
1092
1093         return 0;
1094 }
1095
1096 /**
1097  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1098  * @mtd: mtd info structure
1099  * @chip: nand chip info structure
1100  * @buf: buffer to store read data
1101  * @page: page number to read
1102  */
1103 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1104                                 uint8_t *buf, int page)
1105 {
1106         int i, eccsize = chip->ecc.size;
1107         int eccbytes = chip->ecc.bytes;
1108         int eccsteps = chip->ecc.steps;
1109         uint8_t *p = buf;
1110         uint8_t *ecc_calc = chip->buffers->ecccalc;
1111         uint8_t *ecc_code = chip->buffers->ecccode;
1112         uint32_t *eccpos = chip->ecc.layout->eccpos;
1113
1114         chip->ecc.read_page_raw(mtd, chip, buf, page);
1115
1116         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1117                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1118
1119         for (i = 0; i < chip->ecc.total; i++)
1120                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1121
1122         eccsteps = chip->ecc.steps;
1123         p = buf;
1124
1125         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1126                 int stat;
1127
1128                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1129                 if (stat < 0)
1130                         mtd->ecc_stats.failed++;
1131                 else
1132                         mtd->ecc_stats.corrected += stat;
1133         }
1134         return 0;
1135 }
1136
1137 /**
1138  * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1139  * @mtd: mtd info structure
1140  * @chip: nand chip info structure
1141  * @data_offs: offset of requested data within the page
1142  * @readlen: data length
1143  * @bufpoi: buffer to store read data
1144  */
1145 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1146                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1147 {
1148         int start_step, end_step, num_steps;
1149         uint32_t *eccpos = chip->ecc.layout->eccpos;
1150         uint8_t *p;
1151         int data_col_addr, i, gaps = 0;
1152         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1153         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1154         int index = 0;
1155
1156         /* Column address within the page aligned to ECC size (256bytes) */
1157         start_step = data_offs / chip->ecc.size;
1158         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1159         num_steps = end_step - start_step + 1;
1160
1161         /* Data size aligned to ECC ecc.size */
1162         datafrag_len = num_steps * chip->ecc.size;
1163         eccfrag_len = num_steps * chip->ecc.bytes;
1164
1165         data_col_addr = start_step * chip->ecc.size;
1166         /* If we read not a page aligned data */
1167         if (data_col_addr != 0)
1168                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1169
1170         p = bufpoi + data_col_addr;
1171         chip->read_buf(mtd, p, datafrag_len);
1172
1173         /* Calculate ECC */
1174         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1175                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1176
1177         /*
1178          * The performance is faster if we position offsets according to
1179          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1180          */
1181         for (i = 0; i < eccfrag_len - 1; i++) {
1182                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1183                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1184                         gaps = 1;
1185                         break;
1186                 }
1187         }
1188         if (gaps) {
1189                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1190                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1191         } else {
1192                 /*
1193                  * Send the command to read the particular ECC bytes take care
1194                  * about buswidth alignment in read_buf.
1195                  */
1196                 index = start_step * chip->ecc.bytes;
1197
1198                 aligned_pos = eccpos[index] & ~(busw - 1);
1199                 aligned_len = eccfrag_len;
1200                 if (eccpos[index] & (busw - 1))
1201                         aligned_len++;
1202                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1203                         aligned_len++;
1204
1205                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1206                                         mtd->writesize + aligned_pos, -1);
1207                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1208         }
1209
1210         for (i = 0; i < eccfrag_len; i++)
1211                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1212
1213         p = bufpoi + data_col_addr;
1214         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1215                 int stat;
1216
1217                 stat = chip->ecc.correct(mtd, p,
1218                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1219                 if (stat < 0)
1220                         mtd->ecc_stats.failed++;
1221                 else
1222                         mtd->ecc_stats.corrected += stat;
1223         }
1224         return 0;
1225 }
1226
1227 /**
1228  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1229  * @mtd: mtd info structure
1230  * @chip: nand chip info structure
1231  * @buf: buffer to store read data
1232  * @page: page number to read
1233  *
1234  * Not for syndrome calculating ECC controllers which need a special oob layout.
1235  */
1236 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1237                                 uint8_t *buf, int page)
1238 {
1239         int i, eccsize = chip->ecc.size;
1240         int eccbytes = chip->ecc.bytes;
1241         int eccsteps = chip->ecc.steps;
1242         uint8_t *p = buf;
1243         uint8_t *ecc_calc = chip->buffers->ecccalc;
1244         uint8_t *ecc_code = chip->buffers->ecccode;
1245         uint32_t *eccpos = chip->ecc.layout->eccpos;
1246
1247         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1248                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1249                 chip->read_buf(mtd, p, eccsize);
1250                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1251         }
1252         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1253
1254         for (i = 0; i < chip->ecc.total; i++)
1255                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1256
1257         eccsteps = chip->ecc.steps;
1258         p = buf;
1259
1260         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1261                 int stat;
1262
1263                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1264                 if (stat < 0)
1265                         mtd->ecc_stats.failed++;
1266                 else
1267                         mtd->ecc_stats.corrected += stat;
1268         }
1269         return 0;
1270 }
1271
1272 /**
1273  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1274  * @mtd: mtd info structure
1275  * @chip: nand chip info structure
1276  * @buf: buffer to store read data
1277  * @page: page number to read
1278  *
1279  * Hardware ECC for large page chips, require OOB to be read first. For this
1280  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1281  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1282  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1283  * the data area, by overwriting the NAND manufacturer bad block markings.
1284  */
1285 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1286         struct nand_chip *chip, uint8_t *buf, int page)
1287 {
1288         int i, eccsize = chip->ecc.size;
1289         int eccbytes = chip->ecc.bytes;
1290         int eccsteps = chip->ecc.steps;
1291         uint8_t *p = buf;
1292         uint8_t *ecc_code = chip->buffers->ecccode;
1293         uint32_t *eccpos = chip->ecc.layout->eccpos;
1294         uint8_t *ecc_calc = chip->buffers->ecccalc;
1295
1296         /* Read the OOB area first */
1297         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1298         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1299         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1300
1301         for (i = 0; i < chip->ecc.total; i++)
1302                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1303
1304         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1305                 int stat;
1306
1307                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1308                 chip->read_buf(mtd, p, eccsize);
1309                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1310
1311                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1312                 if (stat < 0)
1313                         mtd->ecc_stats.failed++;
1314                 else
1315                         mtd->ecc_stats.corrected += stat;
1316         }
1317         return 0;
1318 }
1319
1320 /**
1321  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1322  * @mtd: mtd info structure
1323  * @chip: nand chip info structure
1324  * @buf: buffer to store read data
1325  * @page: page number to read
1326  *
1327  * The hw generator calculates the error syndrome automatically. Therefore we
1328  * need a special oob layout and handling.
1329  */
1330 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1331                                    uint8_t *buf, int page)
1332 {
1333         int i, eccsize = chip->ecc.size;
1334         int eccbytes = chip->ecc.bytes;
1335         int eccsteps = chip->ecc.steps;
1336         uint8_t *p = buf;
1337         uint8_t *oob = chip->oob_poi;
1338
1339         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1340                 int stat;
1341
1342                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1343                 chip->read_buf(mtd, p, eccsize);
1344
1345                 if (chip->ecc.prepad) {
1346                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1347                         oob += chip->ecc.prepad;
1348                 }
1349
1350                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1351                 chip->read_buf(mtd, oob, eccbytes);
1352                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1353
1354                 if (stat < 0)
1355                         mtd->ecc_stats.failed++;
1356                 else
1357                         mtd->ecc_stats.corrected += stat;
1358
1359                 oob += eccbytes;
1360
1361                 if (chip->ecc.postpad) {
1362                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1363                         oob += chip->ecc.postpad;
1364                 }
1365         }
1366
1367         /* Calculate remaining oob bytes */
1368         i = mtd->oobsize - (oob - chip->oob_poi);
1369         if (i)
1370                 chip->read_buf(mtd, oob, i);
1371
1372         return 0;
1373 }
1374
1375 /**
1376  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1377  * @chip: nand chip structure
1378  * @oob: oob destination address
1379  * @ops: oob ops structure
1380  * @len: size of oob to transfer
1381  */
1382 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1383                                   struct mtd_oob_ops *ops, size_t len)
1384 {
1385         switch (ops->mode) {
1386
1387         case MTD_OOB_PLACE:
1388         case MTD_OOB_RAW:
1389                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1390                 return oob + len;
1391
1392         case MTD_OOB_AUTO: {
1393                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1394                 uint32_t boffs = 0, roffs = ops->ooboffs;
1395                 size_t bytes = 0;
1396
1397                 for (; free->length && len; free++, len -= bytes) {
1398                         /* Read request not from offset 0? */
1399                         if (unlikely(roffs)) {
1400                                 if (roffs >= free->length) {
1401                                         roffs -= free->length;
1402                                         continue;
1403                                 }
1404                                 boffs = free->offset + roffs;
1405                                 bytes = min_t(size_t, len,
1406                                               (free->length - roffs));
1407                                 roffs = 0;
1408                         } else {
1409                                 bytes = min_t(size_t, len, free->length);
1410                                 boffs = free->offset;
1411                         }
1412                         memcpy(oob, chip->oob_poi + boffs, bytes);
1413                         oob += bytes;
1414                 }
1415                 return oob;
1416         }
1417         default:
1418                 BUG();
1419         }
1420         return NULL;
1421 }
1422
1423 /**
1424  * nand_do_read_ops - [INTERN] Read data with ECC
1425  * @mtd: MTD device structure
1426  * @from: offset to read from
1427  * @ops: oob ops structure
1428  *
1429  * Internal function. Called with chip held.
1430  */
1431 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1432                             struct mtd_oob_ops *ops)
1433 {
1434         int chipnr, page, realpage, col, bytes, aligned;
1435         struct nand_chip *chip = mtd->priv;
1436         struct mtd_ecc_stats stats;
1437         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1438         int sndcmd = 1;
1439         int ret = 0;
1440         uint32_t readlen = ops->len;
1441         uint32_t oobreadlen = ops->ooblen;
1442         uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1443                 mtd->oobavail : mtd->oobsize;
1444
1445         uint8_t *bufpoi, *oob, *buf;
1446
1447         stats = mtd->ecc_stats;
1448
1449         chipnr = (int)(from >> chip->chip_shift);
1450         chip->select_chip(mtd, chipnr);
1451
1452         realpage = (int)(from >> chip->page_shift);
1453         page = realpage & chip->pagemask;
1454
1455         col = (int)(from & (mtd->writesize - 1));
1456
1457         buf = ops->datbuf;
1458         oob = ops->oobbuf;
1459
1460         while (1) {
1461                 bytes = min(mtd->writesize - col, readlen);
1462                 aligned = (bytes == mtd->writesize);
1463
1464                 /* Is the current page in the buffer? */
1465                 if (realpage != chip->pagebuf || oob) {
1466                         bufpoi = aligned ? buf : chip->buffers->databuf;
1467
1468                         if (likely(sndcmd)) {
1469                                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1470                                 sndcmd = 0;
1471                         }
1472
1473                         /* Now read the page into the buffer */
1474                         if (unlikely(ops->mode == MTD_OOB_RAW))
1475                                 ret = chip->ecc.read_page_raw(mtd, chip,
1476                                                               bufpoi, page);
1477                         else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1478                                 ret = chip->ecc.read_subpage(mtd, chip,
1479                                                         col, bytes, bufpoi);
1480                         else
1481                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1482                                                           page);
1483                         if (ret < 0)
1484                                 break;
1485
1486                         /* Transfer not aligned data */
1487                         if (!aligned) {
1488                                 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1489                                     !(mtd->ecc_stats.failed - stats.failed))
1490                                         chip->pagebuf = realpage;
1491                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1492                         }
1493
1494                         buf += bytes;
1495
1496                         if (unlikely(oob)) {
1497
1498                                 int toread = min(oobreadlen, max_oobsize);
1499
1500                                 if (toread) {
1501                                         oob = nand_transfer_oob(chip,
1502                                                 oob, ops, toread);
1503                                         oobreadlen -= toread;
1504                                 }
1505                         }
1506
1507                         if (!(chip->options & NAND_NO_READRDY)) {
1508                                 /*
1509                                  * Apply delay or wait for ready/busy pin. Do
1510                                  * this before the AUTOINCR check, so no
1511                                  * problems arise if a chip which does auto
1512                                  * increment is marked as NOAUTOINCR by the
1513                                  * board driver.
1514                                  */
1515                                 if (!chip->dev_ready)
1516                                         udelay(chip->chip_delay);
1517                                 else
1518                                         nand_wait_ready(mtd);
1519                         }
1520                 } else {
1521                         memcpy(buf, chip->buffers->databuf + col, bytes);
1522                         buf += bytes;
1523                 }
1524
1525                 readlen -= bytes;
1526
1527                 if (!readlen)
1528                         break;
1529
1530                 /* For subsequent reads align to page boundary */
1531                 col = 0;
1532                 /* Increment page address */
1533                 realpage++;
1534
1535                 page = realpage & chip->pagemask;
1536                 /* Check, if we cross a chip boundary */
1537                 if (!page) {
1538                         chipnr++;
1539                         chip->select_chip(mtd, -1);
1540                         chip->select_chip(mtd, chipnr);
1541                 }
1542
1543                 /*
1544                  * Check, if the chip supports auto page increment or if we
1545                  * have hit a block boundary.
1546                  */
1547                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1548                         sndcmd = 1;
1549         }
1550
1551         ops->retlen = ops->len - (size_t) readlen;
1552         if (oob)
1553                 ops->oobretlen = ops->ooblen - oobreadlen;
1554
1555         if (ret)
1556                 return ret;
1557
1558         if (mtd->ecc_stats.failed - stats.failed)
1559                 return -EBADMSG;
1560
1561         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1562 }
1563
1564 /**
1565  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1566  * @mtd: MTD device structure
1567  * @from: offset to read from
1568  * @len: number of bytes to read
1569  * @retlen: pointer to variable to store the number of read bytes
1570  * @buf: the databuffer to put data
1571  *
1572  * Get hold of the chip and call nand_do_read.
1573  */
1574 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1575                      size_t *retlen, uint8_t *buf)
1576 {
1577         struct nand_chip *chip = mtd->priv;
1578         int ret;
1579
1580         /* Do not allow reads past end of device */
1581         if ((from + len) > mtd->size)
1582                 return -EINVAL;
1583         if (!len)
1584                 return 0;
1585
1586         nand_get_device(chip, mtd, FL_READING);
1587
1588         chip->ops.len = len;
1589         chip->ops.datbuf = buf;
1590         chip->ops.oobbuf = NULL;
1591
1592         ret = nand_do_read_ops(mtd, from, &chip->ops);
1593
1594         *retlen = chip->ops.retlen;
1595
1596         nand_release_device(mtd);
1597
1598         return ret;
1599 }
1600
1601 /**
1602  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1603  * @mtd: mtd info structure
1604  * @chip: nand chip info structure
1605  * @page: page number to read
1606  * @sndcmd: flag whether to issue read command or not
1607  */
1608 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1609                              int page, int sndcmd)
1610 {
1611         if (sndcmd) {
1612                 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1613                 sndcmd = 0;
1614         }
1615         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1616         return sndcmd;
1617 }
1618
1619 /**
1620  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1621  *                          with syndromes
1622  * @mtd: mtd info structure
1623  * @chip: nand chip info structure
1624  * @page: page number to read
1625  * @sndcmd: flag whether to issue read command or not
1626  */
1627 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1628                                   int page, int sndcmd)
1629 {
1630         uint8_t *buf = chip->oob_poi;
1631         int length = mtd->oobsize;
1632         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1633         int eccsize = chip->ecc.size;
1634         uint8_t *bufpoi = buf;
1635         int i, toread, sndrnd = 0, pos;
1636
1637         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1638         for (i = 0; i < chip->ecc.steps; i++) {
1639                 if (sndrnd) {
1640                         pos = eccsize + i * (eccsize + chunk);
1641                         if (mtd->writesize > 512)
1642                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1643                         else
1644                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1645                 } else
1646                         sndrnd = 1;
1647                 toread = min_t(int, length, chunk);
1648                 chip->read_buf(mtd, bufpoi, toread);
1649                 bufpoi += toread;
1650                 length -= toread;
1651         }
1652         if (length > 0)
1653                 chip->read_buf(mtd, bufpoi, length);
1654
1655         return 1;
1656 }
1657
1658 /**
1659  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1660  * @mtd: mtd info structure
1661  * @chip: nand chip info structure
1662  * @page: page number to write
1663  */
1664 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1665                               int page)
1666 {
1667         int status = 0;
1668         const uint8_t *buf = chip->oob_poi;
1669         int length = mtd->oobsize;
1670
1671         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1672         chip->write_buf(mtd, buf, length);
1673         /* Send command to program the OOB data */
1674         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1675
1676         status = chip->waitfunc(mtd, chip);
1677
1678         return status & NAND_STATUS_FAIL ? -EIO : 0;
1679 }
1680
1681 /**
1682  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1683  *                           with syndrome - only for large page flash
1684  * @mtd: mtd info structure
1685  * @chip: nand chip info structure
1686  * @page: page number to write
1687  */
1688 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1689                                    struct nand_chip *chip, int page)
1690 {
1691         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1692         int eccsize = chip->ecc.size, length = mtd->oobsize;
1693         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1694         const uint8_t *bufpoi = chip->oob_poi;
1695
1696         /*
1697          * data-ecc-data-ecc ... ecc-oob
1698          * or
1699          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1700          */
1701         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1702                 pos = steps * (eccsize + chunk);
1703                 steps = 0;
1704         } else
1705                 pos = eccsize;
1706
1707         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1708         for (i = 0; i < steps; i++) {
1709                 if (sndcmd) {
1710                         if (mtd->writesize <= 512) {
1711                                 uint32_t fill = 0xFFFFFFFF;
1712
1713                                 len = eccsize;
1714                                 while (len > 0) {
1715                                         int num = min_t(int, len, 4);
1716                                         chip->write_buf(mtd, (uint8_t *)&fill,
1717                                                         num);
1718                                         len -= num;
1719                                 }
1720                         } else {
1721                                 pos = eccsize + i * (eccsize + chunk);
1722                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1723                         }
1724                 } else
1725                         sndcmd = 1;
1726                 len = min_t(int, length, chunk);
1727                 chip->write_buf(mtd, bufpoi, len);
1728                 bufpoi += len;
1729                 length -= len;
1730         }
1731         if (length > 0)
1732                 chip->write_buf(mtd, bufpoi, length);
1733
1734         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1735         status = chip->waitfunc(mtd, chip);
1736
1737         return status & NAND_STATUS_FAIL ? -EIO : 0;
1738 }
1739
1740 /**
1741  * nand_do_read_oob - [INTERN] NAND read out-of-band
1742  * @mtd: MTD device structure
1743  * @from: offset to read from
1744  * @ops: oob operations description structure
1745  *
1746  * NAND read out-of-band data from the spare area.
1747  */
1748 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1749                             struct mtd_oob_ops *ops)
1750 {
1751         int page, realpage, chipnr, sndcmd = 1;
1752         struct nand_chip *chip = mtd->priv;
1753         struct mtd_ecc_stats stats;
1754         int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1755         int readlen = ops->ooblen;
1756         int len;
1757         uint8_t *buf = ops->oobbuf;
1758
1759         DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1760                         __func__, (unsigned long long)from, readlen);
1761
1762         stats = mtd->ecc_stats;
1763
1764         if (ops->mode == MTD_OOB_AUTO)
1765                 len = chip->ecc.layout->oobavail;
1766         else
1767                 len = mtd->oobsize;
1768
1769         if (unlikely(ops->ooboffs >= len)) {
1770                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1771                                         "outside oob\n", __func__);
1772                 return -EINVAL;
1773         }
1774
1775         /* Do not allow reads past end of device */
1776         if (unlikely(from >= mtd->size ||
1777                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1778                                         (from >> chip->page_shift)) * len)) {
1779                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1780                                         "of device\n", __func__);
1781                 return -EINVAL;
1782         }
1783
1784         chipnr = (int)(from >> chip->chip_shift);
1785         chip->select_chip(mtd, chipnr);
1786
1787         /* Shift to get page */
1788         realpage = (int)(from >> chip->page_shift);
1789         page = realpage & chip->pagemask;
1790
1791         while (1) {
1792                 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1793
1794                 len = min(len, readlen);
1795                 buf = nand_transfer_oob(chip, buf, ops, len);
1796
1797                 if (!(chip->options & NAND_NO_READRDY)) {
1798                         /*
1799                          * Apply delay or wait for ready/busy pin. Do this
1800                          * before the AUTOINCR check, so no problems arise if a
1801                          * chip which does auto increment is marked as
1802                          * NOAUTOINCR by the board driver.
1803                          */
1804                         if (!chip->dev_ready)
1805                                 udelay(chip->chip_delay);
1806                         else
1807                                 nand_wait_ready(mtd);
1808                 }
1809
1810                 readlen -= len;
1811                 if (!readlen)
1812                         break;
1813
1814                 /* Increment page address */
1815                 realpage++;
1816
1817                 page = realpage & chip->pagemask;
1818                 /* Check, if we cross a chip boundary */
1819                 if (!page) {
1820                         chipnr++;
1821                         chip->select_chip(mtd, -1);
1822                         chip->select_chip(mtd, chipnr);
1823                 }
1824
1825                 /*
1826                  * Check, if the chip supports auto page increment or if we
1827                  * have hit a block boundary.
1828                  */
1829                 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1830                         sndcmd = 1;
1831         }
1832
1833         ops->oobretlen = ops->ooblen;
1834
1835         if (mtd->ecc_stats.failed - stats.failed)
1836                 return -EBADMSG;
1837
1838         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1839 }
1840
1841 /**
1842  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1843  * @mtd: MTD device structure
1844  * @from: offset to read from
1845  * @ops: oob operation description structure
1846  *
1847  * NAND read data and/or out-of-band data.
1848  */
1849 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1850                          struct mtd_oob_ops *ops)
1851 {
1852         struct nand_chip *chip = mtd->priv;
1853         int ret = -ENOTSUPP;
1854
1855         ops->retlen = 0;
1856
1857         /* Do not allow reads past end of device */
1858         if (ops->datbuf && (from + ops->len) > mtd->size) {
1859                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1860                                 "beyond end of device\n", __func__);
1861                 return -EINVAL;
1862         }
1863
1864         nand_get_device(chip, mtd, FL_READING);
1865
1866         switch (ops->mode) {
1867         case MTD_OOB_PLACE:
1868         case MTD_OOB_AUTO:
1869         case MTD_OOB_RAW:
1870                 break;
1871
1872         default:
1873                 goto out;
1874         }
1875
1876         if (!ops->datbuf)
1877                 ret = nand_do_read_oob(mtd, from, ops);
1878         else
1879                 ret = nand_do_read_ops(mtd, from, ops);
1880
1881 out:
1882         nand_release_device(mtd);
1883         return ret;
1884 }
1885
1886
1887 /**
1888  * nand_write_page_raw - [INTERN] raw page write function
1889  * @mtd: mtd info structure
1890  * @chip: nand chip info structure
1891  * @buf: data buffer
1892  *
1893  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1894  */
1895 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1896                                 const uint8_t *buf)
1897 {
1898         chip->write_buf(mtd, buf, mtd->writesize);
1899         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1900 }
1901
1902 /**
1903  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1904  * @mtd: mtd info structure
1905  * @chip: nand chip info structure
1906  * @buf: data buffer
1907  *
1908  * We need a special oob layout and handling even when ECC isn't checked.
1909  */
1910 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1911                                         struct nand_chip *chip,
1912                                         const uint8_t *buf)
1913 {
1914         int eccsize = chip->ecc.size;
1915         int eccbytes = chip->ecc.bytes;
1916         uint8_t *oob = chip->oob_poi;
1917         int steps, size;
1918
1919         for (steps = chip->ecc.steps; steps > 0; steps--) {
1920                 chip->write_buf(mtd, buf, eccsize);
1921                 buf += eccsize;
1922
1923                 if (chip->ecc.prepad) {
1924                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1925                         oob += chip->ecc.prepad;
1926                 }
1927
1928                 chip->read_buf(mtd, oob, eccbytes);
1929                 oob += eccbytes;
1930
1931                 if (chip->ecc.postpad) {
1932                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1933                         oob += chip->ecc.postpad;
1934                 }
1935         }
1936
1937         size = mtd->oobsize - (oob - chip->oob_poi);
1938         if (size)
1939                 chip->write_buf(mtd, oob, size);
1940 }
1941 /**
1942  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1943  * @mtd: mtd info structure
1944  * @chip: nand chip info structure
1945  * @buf: data buffer
1946  */
1947 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1948                                   const uint8_t *buf)
1949 {
1950         int i, eccsize = chip->ecc.size;
1951         int eccbytes = chip->ecc.bytes;
1952         int eccsteps = chip->ecc.steps;
1953         uint8_t *ecc_calc = chip->buffers->ecccalc;
1954         const uint8_t *p = buf;
1955         uint32_t *eccpos = chip->ecc.layout->eccpos;
1956
1957         /* Software ECC calculation */
1958         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1959                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1960
1961         for (i = 0; i < chip->ecc.total; i++)
1962                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1963
1964         chip->ecc.write_page_raw(mtd, chip, buf);
1965 }
1966
1967 /**
1968  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1969  * @mtd: mtd info structure
1970  * @chip: nand chip info structure
1971  * @buf: data buffer
1972  */
1973 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1974                                   const uint8_t *buf)
1975 {
1976         int i, eccsize = chip->ecc.size;
1977         int eccbytes = chip->ecc.bytes;
1978         int eccsteps = chip->ecc.steps;
1979         uint8_t *ecc_calc = chip->buffers->ecccalc;
1980         const uint8_t *p = buf;
1981         uint32_t *eccpos = chip->ecc.layout->eccpos;
1982
1983         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1984                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1985                 chip->write_buf(mtd, p, eccsize);
1986                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1987         }
1988
1989         for (i = 0; i < chip->ecc.total; i++)
1990                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1991
1992         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1993 }
1994
1995 /**
1996  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1997  * @mtd: mtd info structure
1998  * @chip: nand chip info structure
1999  * @buf: data buffer
2000  *
2001  * The hw generator calculates the error syndrome automatically. Therefore we
2002  * need a special oob layout and handling.
2003  */
2004 static void nand_write_page_syndrome(struct mtd_info *mtd,
2005                                     struct nand_chip *chip, const uint8_t *buf)
2006 {
2007         int i, eccsize = chip->ecc.size;
2008         int eccbytes = chip->ecc.bytes;
2009         int eccsteps = chip->ecc.steps;
2010         const uint8_t *p = buf;
2011         uint8_t *oob = chip->oob_poi;
2012
2013         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2014
2015                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2016                 chip->write_buf(mtd, p, eccsize);
2017
2018                 if (chip->ecc.prepad) {
2019                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2020                         oob += chip->ecc.prepad;
2021                 }
2022
2023                 chip->ecc.calculate(mtd, p, oob);
2024                 chip->write_buf(mtd, oob, eccbytes);
2025                 oob += eccbytes;
2026
2027                 if (chip->ecc.postpad) {
2028                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2029                         oob += chip->ecc.postpad;
2030                 }
2031         }
2032
2033         /* Calculate remaining oob bytes */
2034         i = mtd->oobsize - (oob - chip->oob_poi);
2035         if (i)
2036                 chip->write_buf(mtd, oob, i);
2037 }
2038
2039 /**
2040  * nand_write_page - [REPLACEABLE] write one page
2041  * @mtd: MTD device structure
2042  * @chip: NAND chip descriptor
2043  * @buf: the data to write
2044  * @page: page number to write
2045  * @cached: cached programming
2046  * @raw: use _raw version of write_page
2047  */
2048 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2049                            const uint8_t *buf, int page, int cached, int raw)
2050 {
2051         int status;
2052
2053         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2054
2055         if (unlikely(raw))
2056                 chip->ecc.write_page_raw(mtd, chip, buf);
2057         else
2058                 chip->ecc.write_page(mtd, chip, buf);
2059
2060         /*
2061          * Cached progamming disabled for now. Not sure if it's worth the
2062          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2063          */
2064         cached = 0;
2065
2066         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2067
2068                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2069                 status = chip->waitfunc(mtd, chip);
2070                 /*
2071                  * See if operation failed and additional status checks are
2072                  * available.
2073                  */
2074                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2075                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2076                                                page);
2077
2078                 if (status & NAND_STATUS_FAIL)
2079                         return -EIO;
2080         } else {
2081                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2082                 status = chip->waitfunc(mtd, chip);
2083         }
2084
2085 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2086         /* Send command to read back the data */
2087         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2088
2089         if (chip->verify_buf(mtd, buf, mtd->writesize))
2090                 return -EIO;
2091 #endif
2092         return 0;
2093 }
2094
2095 /**
2096  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2097  * @mtd: MTD device structure
2098  * @oob: oob data buffer
2099  * @len: oob data write length
2100  * @ops: oob ops structure
2101  */
2102 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2103                               struct mtd_oob_ops *ops)
2104 {
2105         struct nand_chip *chip = mtd->priv;
2106
2107         /*
2108          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2109          * data from a previous OOB read.
2110          */
2111         memset(chip->oob_poi, 0xff, mtd->oobsize);
2112
2113         switch (ops->mode) {
2114
2115         case MTD_OOB_PLACE:
2116         case MTD_OOB_RAW:
2117                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2118                 return oob + len;
2119
2120         case MTD_OOB_AUTO: {
2121                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2122                 uint32_t boffs = 0, woffs = ops->ooboffs;
2123                 size_t bytes = 0;
2124
2125                 for (; free->length && len; free++, len -= bytes) {
2126                         /* Write request not from offset 0? */
2127                         if (unlikely(woffs)) {
2128                                 if (woffs >= free->length) {
2129                                         woffs -= free->length;
2130                                         continue;
2131                                 }
2132                                 boffs = free->offset + woffs;
2133                                 bytes = min_t(size_t, len,
2134                                               (free->length - woffs));
2135                                 woffs = 0;
2136                         } else {
2137                                 bytes = min_t(size_t, len, free->length);
2138                                 boffs = free->offset;
2139                         }
2140                         memcpy(chip->oob_poi + boffs, oob, bytes);
2141                         oob += bytes;
2142                 }
2143                 return oob;
2144         }
2145         default:
2146                 BUG();
2147         }
2148         return NULL;
2149 }
2150
2151 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2152
2153 /**
2154  * nand_do_write_ops - [INTERN] NAND write with ECC
2155  * @mtd: MTD device structure
2156  * @to: offset to write to
2157  * @ops: oob operations description structure
2158  *
2159  * NAND write with ECC.
2160  */
2161 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2162                              struct mtd_oob_ops *ops)
2163 {
2164         int chipnr, realpage, page, blockmask, column;
2165         struct nand_chip *chip = mtd->priv;
2166         uint32_t writelen = ops->len;
2167
2168         uint32_t oobwritelen = ops->ooblen;
2169         uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2170                                 mtd->oobavail : mtd->oobsize;
2171
2172         uint8_t *oob = ops->oobbuf;
2173         uint8_t *buf = ops->datbuf;
2174         int ret, subpage;
2175
2176         ops->retlen = 0;
2177         if (!writelen)
2178                 return 0;
2179
2180         /* Reject writes, which are not page aligned */
2181         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2182                 printk(KERN_NOTICE "%s: Attempt to write not "
2183                                 "page aligned data\n", __func__);
2184                 return -EINVAL;
2185         }
2186
2187         column = to & (mtd->writesize - 1);
2188         subpage = column || (writelen & (mtd->writesize - 1));
2189
2190         if (subpage && oob)
2191                 return -EINVAL;
2192
2193         chipnr = (int)(to >> chip->chip_shift);
2194         chip->select_chip(mtd, chipnr);
2195
2196         /* Check, if it is write protected */
2197         if (nand_check_wp(mtd))
2198                 return -EIO;
2199
2200         realpage = (int)(to >> chip->page_shift);
2201         page = realpage & chip->pagemask;
2202         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2203
2204         /* Invalidate the page cache, when we write to the cached page */
2205         if (to <= (chip->pagebuf << chip->page_shift) &&
2206             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2207                 chip->pagebuf = -1;
2208
2209         /* Don't allow multipage oob writes with offset */
2210         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2211                 return -EINVAL;
2212
2213         while (1) {
2214                 int bytes = mtd->writesize;
2215                 int cached = writelen > bytes && page != blockmask;
2216                 uint8_t *wbuf = buf;
2217
2218                 /* Partial page write? */
2219                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2220                         cached = 0;
2221                         bytes = min_t(int, bytes - column, (int) writelen);
2222                         chip->pagebuf = -1;
2223                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2224                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2225                         wbuf = chip->buffers->databuf;
2226                 }
2227
2228                 if (unlikely(oob)) {
2229                         size_t len = min(oobwritelen, oobmaxlen);
2230                         oob = nand_fill_oob(mtd, oob, len, ops);
2231                         oobwritelen -= len;
2232                 } else {
2233                         /* We still need to erase leftover OOB data */
2234                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2235                 }
2236
2237                 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2238                                        (ops->mode == MTD_OOB_RAW));
2239                 if (ret)
2240                         break;
2241
2242                 writelen -= bytes;
2243                 if (!writelen)
2244                         break;
2245
2246                 column = 0;
2247                 buf += bytes;
2248                 realpage++;
2249
2250                 page = realpage & chip->pagemask;
2251                 /* Check, if we cross a chip boundary */
2252                 if (!page) {
2253                         chipnr++;
2254                         chip->select_chip(mtd, -1);
2255                         chip->select_chip(mtd, chipnr);
2256                 }
2257         }
2258
2259         ops->retlen = ops->len - writelen;
2260         if (unlikely(oob))
2261                 ops->oobretlen = ops->ooblen;
2262         return ret;
2263 }
2264
2265 /**
2266  * panic_nand_write - [MTD Interface] NAND write with ECC
2267  * @mtd: MTD device structure
2268  * @to: offset to write to
2269  * @len: number of bytes to write
2270  * @retlen: pointer to variable to store the number of written bytes
2271  * @buf: the data to write
2272  *
2273  * NAND write with ECC. Used when performing writes in interrupt context, this
2274  * may for example be called by mtdoops when writing an oops while in panic.
2275  */
2276 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2277                             size_t *retlen, const uint8_t *buf)
2278 {
2279         struct nand_chip *chip = mtd->priv;
2280         int ret;
2281
2282         /* Do not allow reads past end of device */
2283         if ((to + len) > mtd->size)
2284                 return -EINVAL;
2285         if (!len)
2286                 return 0;
2287
2288         /* Wait for the device to get ready */
2289         panic_nand_wait(mtd, chip, 400);
2290
2291         /* Grab the device */
2292         panic_nand_get_device(chip, mtd, FL_WRITING);
2293
2294         chip->ops.len = len;
2295         chip->ops.datbuf = (uint8_t *)buf;
2296         chip->ops.oobbuf = NULL;
2297
2298         ret = nand_do_write_ops(mtd, to, &chip->ops);
2299
2300         *retlen = chip->ops.retlen;
2301         return ret;
2302 }
2303
2304 /**
2305  * nand_write - [MTD Interface] NAND write with ECC
2306  * @mtd: MTD device structure
2307  * @to: offset to write to
2308  * @len: number of bytes to write
2309  * @retlen: pointer to variable to store the number of written bytes
2310  * @buf: the data to write
2311  *
2312  * NAND write with ECC.
2313  */
2314 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2315                           size_t *retlen, const uint8_t *buf)
2316 {
2317         struct nand_chip *chip = mtd->priv;
2318         int ret;
2319
2320         /* Do not allow reads past end of device */
2321         if ((to + len) > mtd->size)
2322                 return -EINVAL;
2323         if (!len)
2324                 return 0;
2325
2326         nand_get_device(chip, mtd, FL_WRITING);
2327
2328         chip->ops.len = len;
2329         chip->ops.datbuf = (uint8_t *)buf;
2330         chip->ops.oobbuf = NULL;
2331
2332         ret = nand_do_write_ops(mtd, to, &chip->ops);
2333
2334         *retlen = chip->ops.retlen;
2335
2336         nand_release_device(mtd);
2337
2338         return ret;
2339 }
2340
2341 /**
2342  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2343  * @mtd: MTD device structure
2344  * @to: offset to write to
2345  * @ops: oob operation description structure
2346  *
2347  * NAND write out-of-band.
2348  */
2349 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2350                              struct mtd_oob_ops *ops)
2351 {
2352         int chipnr, page, status, len;
2353         struct nand_chip *chip = mtd->priv;
2354
2355         DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2356                          __func__, (unsigned int)to, (int)ops->ooblen);
2357
2358         if (ops->mode == MTD_OOB_AUTO)
2359                 len = chip->ecc.layout->oobavail;
2360         else
2361                 len = mtd->oobsize;
2362
2363         /* Do not allow write past end of page */
2364         if ((ops->ooboffs + ops->ooblen) > len) {
2365                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2366                                 "past end of page\n", __func__);
2367                 return -EINVAL;
2368         }
2369
2370         if (unlikely(ops->ooboffs >= len)) {
2371                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2372                                 "write outside oob\n", __func__);
2373                 return -EINVAL;
2374         }
2375
2376         /* Do not allow write past end of device */
2377         if (unlikely(to >= mtd->size ||
2378                      ops->ooboffs + ops->ooblen >
2379                         ((mtd->size >> chip->page_shift) -
2380                          (to >> chip->page_shift)) * len)) {
2381                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2382                                 "end of device\n", __func__);
2383                 return -EINVAL;
2384         }
2385
2386         chipnr = (int)(to >> chip->chip_shift);
2387         chip->select_chip(mtd, chipnr);
2388
2389         /* Shift to get page */
2390         page = (int)(to >> chip->page_shift);
2391
2392         /*
2393          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2394          * of my DiskOnChip 2000 test units) will clear the whole data page too
2395          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2396          * it in the doc2000 driver in August 1999.  dwmw2.
2397          */
2398         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2399
2400         /* Check, if it is write protected */
2401         if (nand_check_wp(mtd))
2402                 return -EROFS;
2403
2404         /* Invalidate the page cache, if we write to the cached page */
2405         if (page == chip->pagebuf)
2406                 chip->pagebuf = -1;
2407
2408         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2409         status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2410
2411         if (status)
2412                 return status;
2413
2414         ops->oobretlen = ops->ooblen;
2415
2416         return 0;
2417 }
2418
2419 /**
2420  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2421  * @mtd: MTD device structure
2422  * @to: offset to write to
2423  * @ops: oob operation description structure
2424  */
2425 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2426                           struct mtd_oob_ops *ops)
2427 {
2428         struct nand_chip *chip = mtd->priv;
2429         int ret = -ENOTSUPP;
2430
2431         ops->retlen = 0;
2432
2433         /* Do not allow writes past end of device */
2434         if (ops->datbuf && (to + ops->len) > mtd->size) {
2435                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2436                                 "end of device\n", __func__);
2437                 return -EINVAL;
2438         }
2439
2440         nand_get_device(chip, mtd, FL_WRITING);
2441
2442         switch (ops->mode) {
2443         case MTD_OOB_PLACE:
2444         case MTD_OOB_AUTO:
2445         case MTD_OOB_RAW:
2446                 break;
2447
2448         default:
2449                 goto out;
2450         }
2451
2452         if (!ops->datbuf)
2453                 ret = nand_do_write_oob(mtd, to, ops);
2454         else
2455                 ret = nand_do_write_ops(mtd, to, ops);
2456
2457 out:
2458         nand_release_device(mtd);
2459         return ret;
2460 }
2461
2462 /**
2463  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2464  * @mtd: MTD device structure
2465  * @page: the page address of the block which will be erased
2466  *
2467  * Standard erase command for NAND chips.
2468  */
2469 static void single_erase_cmd(struct mtd_info *mtd, int page)
2470 {
2471         struct nand_chip *chip = mtd->priv;
2472         /* Send commands to erase a block */
2473         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2474         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2475 }
2476
2477 /**
2478  * multi_erase_cmd - [GENERIC] AND specific block erase command function
2479  * @mtd: MTD device structure
2480  * @page: the page address of the block which will be erased
2481  *
2482  * AND multi block erase command function. Erase 4 consecutive blocks.
2483  */
2484 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2485 {
2486         struct nand_chip *chip = mtd->priv;
2487         /* Send commands to erase a block */
2488         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2489         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2490         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2491         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2492         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2493 }
2494
2495 /**
2496  * nand_erase - [MTD Interface] erase block(s)
2497  * @mtd: MTD device structure
2498  * @instr: erase instruction
2499  *
2500  * Erase one ore more blocks.
2501  */
2502 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2503 {
2504         return nand_erase_nand(mtd, instr, 0);
2505 }
2506
2507 #define BBT_PAGE_MASK   0xffffff3f
2508 /**
2509  * nand_erase_nand - [INTERN] erase block(s)
2510  * @mtd: MTD device structure
2511  * @instr: erase instruction
2512  * @allowbbt: allow erasing the bbt area
2513  *
2514  * Erase one ore more blocks.
2515  */
2516 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2517                     int allowbbt)
2518 {
2519         int page, status, pages_per_block, ret, chipnr;
2520         struct nand_chip *chip = mtd->priv;
2521         loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2522         unsigned int bbt_masked_page = 0xffffffff;
2523         loff_t len;
2524
2525         DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2526                                 __func__, (unsigned long long)instr->addr,
2527                                 (unsigned long long)instr->len);
2528
2529         if (check_offs_len(mtd, instr->addr, instr->len))
2530                 return -EINVAL;
2531
2532         instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2533
2534         /* Grab the lock and see if the device is available */
2535         nand_get_device(chip, mtd, FL_ERASING);
2536
2537         /* Shift to get first page */
2538         page = (int)(instr->addr >> chip->page_shift);
2539         chipnr = (int)(instr->addr >> chip->chip_shift);
2540
2541         /* Calculate pages in each block */
2542         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2543
2544         /* Select the NAND device */
2545         chip->select_chip(mtd, chipnr);
2546
2547         /* Check, if it is write protected */
2548         if (nand_check_wp(mtd)) {
2549                 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2550                                         __func__);
2551                 instr->state = MTD_ERASE_FAILED;
2552                 goto erase_exit;
2553         }
2554
2555         /*
2556          * If BBT requires refresh, set the BBT page mask to see if the BBT
2557          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2558          * can not be matched. This is also done when the bbt is actually
2559          * erased to avoid recursive updates.
2560          */
2561         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2562                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2563
2564         /* Loop through the pages */
2565         len = instr->len;
2566
2567         instr->state = MTD_ERASING;
2568
2569         while (len) {
2570                 /* Heck if we have a bad block, we do not erase bad blocks! */
2571                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2572                                         chip->page_shift, 0, allowbbt)) {
2573                         printk(KERN_WARNING "%s: attempt to erase a bad block "
2574                                         "at page 0x%08x\n", __func__, page);
2575                         instr->state = MTD_ERASE_FAILED;
2576                         goto erase_exit;
2577                 }
2578
2579                 /*
2580                  * Invalidate the page cache, if we erase the block which
2581                  * contains the current cached page.
2582                  */
2583                 if (page <= chip->pagebuf && chip->pagebuf <
2584                     (page + pages_per_block))
2585                         chip->pagebuf = -1;
2586
2587                 chip->erase_cmd(mtd, page & chip->pagemask);
2588
2589                 status = chip->waitfunc(mtd, chip);
2590
2591                 /*
2592                  * See if operation failed and additional status checks are
2593                  * available
2594                  */
2595                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2596                         status = chip->errstat(mtd, chip, FL_ERASING,
2597                                                status, page);
2598
2599                 /* See if block erase succeeded */
2600                 if (status & NAND_STATUS_FAIL) {
2601                         DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2602                                         "page 0x%08x\n", __func__, page);
2603                         instr->state = MTD_ERASE_FAILED;
2604                         instr->fail_addr =
2605                                 ((loff_t)page << chip->page_shift);
2606                         goto erase_exit;
2607                 }
2608
2609                 /*
2610                  * If BBT requires refresh, set the BBT rewrite flag to the
2611                  * page being erased.
2612                  */
2613                 if (bbt_masked_page != 0xffffffff &&
2614                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2615                             rewrite_bbt[chipnr] =
2616                                         ((loff_t)page << chip->page_shift);
2617
2618                 /* Increment page address and decrement length */
2619                 len -= (1 << chip->phys_erase_shift);
2620                 page += pages_per_block;
2621
2622                 /* Check, if we cross a chip boundary */
2623                 if (len && !(page & chip->pagemask)) {
2624                         chipnr++;
2625                         chip->select_chip(mtd, -1);
2626                         chip->select_chip(mtd, chipnr);
2627
2628                         /*
2629                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2630                          * page mask to see if this BBT should be rewritten.
2631                          */
2632                         if (bbt_masked_page != 0xffffffff &&
2633                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2634                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2635                                         BBT_PAGE_MASK;
2636                 }
2637         }
2638         instr->state = MTD_ERASE_DONE;
2639
2640 erase_exit:
2641
2642         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2643
2644         /* Deselect and wake up anyone waiting on the device */
2645         nand_release_device(mtd);
2646
2647         /* Do call back function */
2648         if (!ret)
2649                 mtd_erase_callback(instr);
2650
2651         /*
2652          * If BBT requires refresh and erase was successful, rewrite any
2653          * selected bad block tables.
2654          */
2655         if (bbt_masked_page == 0xffffffff || ret)
2656                 return ret;
2657
2658         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2659                 if (!rewrite_bbt[chipnr])
2660                         continue;
2661                 /* Update the BBT for chip */
2662                 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2663                         "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2664                         rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2665                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2666         }
2667
2668         /* Return more or less happy */
2669         return ret;
2670 }
2671
2672 /**
2673  * nand_sync - [MTD Interface] sync
2674  * @mtd: MTD device structure
2675  *
2676  * Sync is actually a wait for chip ready function.
2677  */
2678 static void nand_sync(struct mtd_info *mtd)
2679 {
2680         struct nand_chip *chip = mtd->priv;
2681
2682         DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2683
2684         /* Grab the lock and see if the device is available */
2685         nand_get_device(chip, mtd, FL_SYNCING);
2686         /* Release it and go back */
2687         nand_release_device(mtd);
2688 }
2689
2690 /**
2691  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2692  * @mtd: MTD device structure
2693  * @offs: offset relative to mtd start
2694  */
2695 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2696 {
2697         /* Check for invalid offset */
2698         if (offs > mtd->size)
2699                 return -EINVAL;
2700
2701         return nand_block_checkbad(mtd, offs, 1, 0);
2702 }
2703
2704 /**
2705  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2706  * @mtd: MTD device structure
2707  * @ofs: offset relative to mtd start
2708  */
2709 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2710 {
2711         struct nand_chip *chip = mtd->priv;
2712         int ret;
2713
2714         ret = nand_block_isbad(mtd, ofs);
2715         if (ret) {
2716                 /* If it was bad already, return success and do nothing */
2717                 if (ret > 0)
2718                         return 0;
2719                 return ret;
2720         }
2721
2722         return chip->block_markbad(mtd, ofs);
2723 }
2724
2725 /**
2726  * nand_suspend - [MTD Interface] Suspend the NAND flash
2727  * @mtd: MTD device structure
2728  */
2729 static int nand_suspend(struct mtd_info *mtd)
2730 {
2731         struct nand_chip *chip = mtd->priv;
2732
2733         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2734 }
2735
2736 /**
2737  * nand_resume - [MTD Interface] Resume the NAND flash
2738  * @mtd: MTD device structure
2739  */
2740 static void nand_resume(struct mtd_info *mtd)
2741 {
2742         struct nand_chip *chip = mtd->priv;
2743
2744         if (chip->state == FL_PM_SUSPENDED)
2745                 nand_release_device(mtd);
2746         else
2747                 printk(KERN_ERR "%s called for a chip which is not "
2748                        "in suspended state\n", __func__);
2749 }
2750
2751 /* Set default functions */
2752 static void nand_set_defaults(struct nand_chip *chip, int busw)
2753 {
2754         /* check for proper chip_delay setup, set 20us if not */
2755         if (!chip->chip_delay)
2756                 chip->chip_delay = 20;
2757
2758         /* check, if a user supplied command function given */
2759         if (chip->cmdfunc == NULL)
2760                 chip->cmdfunc = nand_command;
2761
2762         /* check, if a user supplied wait function given */
2763         if (chip->waitfunc == NULL)
2764                 chip->waitfunc = nand_wait;
2765
2766         if (!chip->select_chip)
2767                 chip->select_chip = nand_select_chip;
2768         if (!chip->read_byte)
2769                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2770         if (!chip->read_word)
2771                 chip->read_word = nand_read_word;
2772         if (!chip->block_bad)
2773                 chip->block_bad = nand_block_bad;
2774         if (!chip->block_markbad)
2775                 chip->block_markbad = nand_default_block_markbad;
2776         if (!chip->write_buf)
2777                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2778         if (!chip->read_buf)
2779                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2780         if (!chip->verify_buf)
2781                 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2782         if (!chip->scan_bbt)
2783                 chip->scan_bbt = nand_default_bbt;
2784
2785         if (!chip->controller) {
2786                 chip->controller = &chip->hwcontrol;
2787                 spin_lock_init(&chip->controller->lock);
2788                 init_waitqueue_head(&chip->controller->wq);
2789         }
2790
2791 }
2792
2793 /* Sanitize ONFI strings so we can safely print them */
2794 static void sanitize_string(uint8_t *s, size_t len)
2795 {
2796         ssize_t i;
2797
2798         /* Null terminate */
2799         s[len - 1] = 0;
2800
2801         /* Remove non printable chars */
2802         for (i = 0; i < len - 1; i++) {
2803                 if (s[i] < ' ' || s[i] > 127)
2804                         s[i] = '?';
2805         }
2806
2807         /* Remove trailing spaces */
2808         strim(s);
2809 }
2810
2811 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2812 {
2813         int i;
2814         while (len--) {
2815                 crc ^= *p++ << 8;
2816                 for (i = 0; i < 8; i++)
2817                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2818         }
2819
2820         return crc;
2821 }
2822
2823 /*
2824  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2825  */
2826 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2827                                         int *busw)
2828 {
2829         struct nand_onfi_params *p = &chip->onfi_params;
2830         int i;
2831         int val;
2832
2833         /* Try ONFI for unknown chip or LP */
2834         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2835         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2836                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2837                 return 0;
2838
2839         printk(KERN_INFO "ONFI flash detected\n");
2840         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2841         for (i = 0; i < 3; i++) {
2842                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2843                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2844                                 le16_to_cpu(p->crc)) {
2845                         printk(KERN_INFO "ONFI param page %d valid\n", i);
2846                         break;
2847                 }
2848         }
2849
2850         if (i == 3)
2851                 return 0;
2852
2853         /* Check version */
2854         val = le16_to_cpu(p->revision);
2855         if (val & (1 << 5))
2856                 chip->onfi_version = 23;
2857         else if (val & (1 << 4))
2858                 chip->onfi_version = 22;
2859         else if (val & (1 << 3))
2860                 chip->onfi_version = 21;
2861         else if (val & (1 << 2))
2862                 chip->onfi_version = 20;
2863         else if (val & (1 << 1))
2864                 chip->onfi_version = 10;
2865         else
2866                 chip->onfi_version = 0;
2867
2868         if (!chip->onfi_version) {
2869                 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2870                                                                 __func__, val);
2871                 return 0;
2872         }
2873
2874         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2875         sanitize_string(p->model, sizeof(p->model));
2876         if (!mtd->name)
2877                 mtd->name = p->model;
2878         mtd->writesize = le32_to_cpu(p->byte_per_page);
2879         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2880         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2881         chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2882         *busw = 0;
2883         if (le16_to_cpu(p->features) & 1)
2884                 *busw = NAND_BUSWIDTH_16;
2885
2886         chip->options &= ~NAND_CHIPOPTIONS_MSK;
2887         chip->options |= (NAND_NO_READRDY |
2888                         NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2889
2890         return 1;
2891 }
2892
2893 /*
2894  * Get the flash and manufacturer id and lookup if the type is supported.
2895  */
2896 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2897                                                   struct nand_chip *chip,
2898                                                   int busw,
2899                                                   int *maf_id, int *dev_id,
2900                                                   struct nand_flash_dev *type)
2901 {
2902         int i, maf_idx;
2903         u8 id_data[8];
2904         int ret;
2905
2906         /* Select the device */
2907         chip->select_chip(mtd, 0);
2908
2909         /*
2910          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2911          * after power-up.
2912          */
2913         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2914
2915         /* Send the command for reading device ID */
2916         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2917
2918         /* Read manufacturer and device IDs */
2919         *maf_id = chip->read_byte(mtd);
2920         *dev_id = chip->read_byte(mtd);
2921
2922         /*
2923          * Try again to make sure, as some systems the bus-hold or other
2924          * interface concerns can cause random data which looks like a
2925          * possibly credible NAND flash to appear. If the two results do
2926          * not match, ignore the device completely.
2927          */
2928
2929         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2930
2931         for (i = 0; i < 2; i++)
2932                 id_data[i] = chip->read_byte(mtd);
2933
2934         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2935                 printk(KERN_INFO "%s: second ID read did not match "
2936                        "%02x,%02x against %02x,%02x\n", __func__,
2937                        *maf_id, *dev_id, id_data[0], id_data[1]);
2938                 return ERR_PTR(-ENODEV);
2939         }
2940
2941         if (!type)
2942                 type = nand_flash_ids;
2943
2944         for (; type->name != NULL; type++)
2945                 if (*dev_id == type->id)
2946                         break;
2947
2948         chip->onfi_version = 0;
2949         if (!type->name || !type->pagesize) {
2950                 /* Check is chip is ONFI compliant */
2951                 ret = nand_flash_detect_onfi(mtd, chip, &busw);
2952                 if (ret)
2953                         goto ident_done;
2954         }
2955
2956         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2957
2958         /* Read entire ID string */
2959
2960         for (i = 0; i < 8; i++)
2961                 id_data[i] = chip->read_byte(mtd);
2962
2963         if (!type->name)
2964                 return ERR_PTR(-ENODEV);
2965
2966         if (!mtd->name)
2967                 mtd->name = type->name;
2968
2969         chip->chipsize = (uint64_t)type->chipsize << 20;
2970
2971         if (!type->pagesize && chip->init_size) {
2972                 /* Set the pagesize, oobsize, erasesize by the driver */
2973                 busw = chip->init_size(mtd, chip, id_data);
2974         } else if (!type->pagesize) {
2975                 int extid;
2976                 /* The 3rd id byte holds MLC / multichip data */
2977                 chip->cellinfo = id_data[2];
2978                 /* The 4th id byte is the important one */
2979                 extid = id_data[3];
2980
2981                 /*
2982                  * Field definitions are in the following datasheets:
2983                  * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2984                  * New style   (6 byte ID): Samsung K9GBG08U0M (p.40)
2985                  *
2986                  * Check for wraparound + Samsung ID + nonzero 6th byte
2987                  * to decide what to do.
2988                  */
2989                 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2990                                 id_data[0] == NAND_MFR_SAMSUNG &&
2991                                 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2992                                 id_data[5] != 0x00) {
2993                         /* Calc pagesize */
2994                         mtd->writesize = 2048 << (extid & 0x03);
2995                         extid >>= 2;
2996                         /* Calc oobsize */
2997                         switch (extid & 0x03) {
2998                         case 1:
2999                                 mtd->oobsize = 128;
3000                                 break;
3001                         case 2:
3002                                 mtd->oobsize = 218;
3003                                 break;
3004                         case 3:
3005                                 mtd->oobsize = 400;
3006                                 break;
3007                         default:
3008                                 mtd->oobsize = 436;
3009                                 break;
3010                         }
3011                         extid >>= 2;
3012                         /* Calc blocksize */
3013                         mtd->erasesize = (128 * 1024) <<
3014                                 (((extid >> 1) & 0x04) | (extid & 0x03));
3015                         busw = 0;
3016                 } else {
3017                         /* Calc pagesize */
3018                         mtd->writesize = 1024 << (extid & 0x03);
3019                         extid >>= 2;
3020                         /* Calc oobsize */
3021                         mtd->oobsize = (8 << (extid & 0x01)) *
3022                                 (mtd->writesize >> 9);
3023                         extid >>= 2;
3024                         /* Calc blocksize. Blocksize is multiples of 64KiB */
3025                         mtd->erasesize = (64 * 1024) << (extid & 0x03);
3026                         extid >>= 2;
3027                         /* Get buswidth information */
3028                         busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3029                 }
3030         } else {
3031                 /*
3032                  * Old devices have chip data hardcoded in the device id table.
3033                  */
3034                 mtd->erasesize = type->erasesize;
3035                 mtd->writesize = type->pagesize;
3036                 mtd->oobsize = mtd->writesize / 32;
3037                 busw = type->options & NAND_BUSWIDTH_16;
3038
3039                 /*
3040                  * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3041                  * some Spansion chips have erasesize that conflicts with size
3042                  * listed in nand_ids table.
3043                  * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3044                  */
3045                 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3046                                 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3047                                 id_data[7] == 0x00 && mtd->writesize == 512) {
3048                         mtd->erasesize = 128 * 1024;
3049                         mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3050                 }
3051         }
3052         /* Get chip options, preserve non chip based options */
3053         chip->options &= ~NAND_CHIPOPTIONS_MSK;
3054         chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3055
3056         /*
3057          * Check if chip is not a Samsung device. Do not clear the
3058          * options for chips which do not have an extended id.
3059          */
3060         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3061                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3062 ident_done:
3063
3064         /*
3065          * Set chip as a default. Board drivers can override it, if necessary.
3066          */
3067         chip->options |= NAND_NO_AUTOINCR;
3068
3069         /* Try to identify manufacturer */
3070         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3071                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3072                         break;
3073         }
3074
3075         /*
3076          * Check, if buswidth is correct. Hardware drivers should set
3077          * chip correct!
3078          */
3079         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3080                 printk(KERN_INFO "NAND device: Manufacturer ID:"
3081                        " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3082                        *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3083                 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
3084                        (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3085                        busw ? 16 : 8);
3086                 return ERR_PTR(-EINVAL);
3087         }
3088
3089         /* Calculate the address shift from the page size */
3090         chip->page_shift = ffs(mtd->writesize) - 1;
3091         /* Convert chipsize to number of pages per chip -1 */
3092         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3093
3094         chip->bbt_erase_shift = chip->phys_erase_shift =
3095                 ffs(mtd->erasesize) - 1;
3096         if (chip->chipsize & 0xffffffff)
3097                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3098         else {
3099                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3100                 chip->chip_shift += 32 - 1;
3101         }
3102
3103         chip->badblockbits = 8;
3104
3105         /* Set the bad block position */
3106         if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3107                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3108         else
3109                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3110
3111         /*
3112          * Bad block marker is stored in the last page of each block
3113          * on Samsung and Hynix MLC devices; stored in first two pages
3114          * of each block on Micron devices with 2KiB pages and on
3115          * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3116          * only the first page.
3117          */
3118         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3119                         (*maf_id == NAND_MFR_SAMSUNG ||
3120                          *maf_id == NAND_MFR_HYNIX))
3121                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3122         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3123                                 (*maf_id == NAND_MFR_SAMSUNG ||
3124                                  *maf_id == NAND_MFR_HYNIX ||
3125                                  *maf_id == NAND_MFR_TOSHIBA ||
3126                                  *maf_id == NAND_MFR_AMD)) ||
3127                         (mtd->writesize == 2048 &&
3128                          *maf_id == NAND_MFR_MICRON))
3129                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3130
3131         /* Check for AND chips with 4 page planes */
3132         if (chip->options & NAND_4PAGE_ARRAY)
3133                 chip->erase_cmd = multi_erase_cmd;
3134         else
3135                 chip->erase_cmd = single_erase_cmd;
3136
3137         /* Do not replace user supplied command function! */
3138         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3139                 chip->cmdfunc = nand_command_lp;
3140
3141         printk(KERN_INFO "NAND device: Manufacturer ID:"
3142                 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3143                 nand_manuf_ids[maf_idx].name,
3144                 chip->onfi_version ? chip->onfi_params.model : type->name);
3145
3146         return type;
3147 }
3148
3149 /**
3150  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3151  * @mtd: MTD device structure
3152  * @maxchips: number of chips to scan for
3153  * @table: alternative NAND ID table
3154  *
3155  * This is the first phase of the normal nand_scan() function. It reads the
3156  * flash ID and sets up MTD fields accordingly.
3157  *
3158  * The mtd->owner field must be set to the module of the caller.
3159  */
3160 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3161                     struct nand_flash_dev *table)
3162 {
3163         int i, busw, nand_maf_id, nand_dev_id;
3164         struct nand_chip *chip = mtd->priv;
3165         struct nand_flash_dev *type;
3166
3167         /* Get buswidth to select the correct functions */
3168         busw = chip->options & NAND_BUSWIDTH_16;
3169         /* Set the default functions */
3170         nand_set_defaults(chip, busw);
3171
3172         /* Read the flash type */
3173         type = nand_get_flash_type(mtd, chip, busw,
3174                                 &nand_maf_id, &nand_dev_id, table);
3175
3176         if (IS_ERR(type)) {
3177                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3178                         printk(KERN_WARNING "No NAND device found.\n");
3179                 chip->select_chip(mtd, -1);
3180                 return PTR_ERR(type);
3181         }
3182
3183         /* Check for a chip array */
3184         for (i = 1; i < maxchips; i++) {
3185                 chip->select_chip(mtd, i);
3186                 /* See comment in nand_get_flash_type for reset */
3187                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3188                 /* Send the command for reading device ID */
3189                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3190                 /* Read manufacturer and device IDs */
3191                 if (nand_maf_id != chip->read_byte(mtd) ||
3192                     nand_dev_id != chip->read_byte(mtd))
3193                         break;
3194         }
3195         if (i > 1)
3196                 printk(KERN_INFO "%d NAND chips detected\n", i);
3197
3198         /* Store the number of chips and calc total size for mtd */
3199         chip->numchips = i;
3200         mtd->size = i * chip->chipsize;
3201
3202         return 0;
3203 }
3204 EXPORT_SYMBOL(nand_scan_ident);
3205
3206
3207 /**
3208  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3209  * @mtd: MTD device structure
3210  *
3211  * This is the second phase of the normal nand_scan() function. It fills out
3212  * all the uninitialized function pointers with the defaults and scans for a
3213  * bad block table if appropriate.
3214  */
3215 int nand_scan_tail(struct mtd_info *mtd)
3216 {
3217         int i;
3218         struct nand_chip *chip = mtd->priv;
3219
3220         if (!(chip->options & NAND_OWN_BUFFERS))
3221                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3222         if (!chip->buffers)
3223                 return -ENOMEM;
3224
3225         /* Set the internal oob buffer location, just after the page data */
3226         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3227
3228         /*
3229          * If no default placement scheme is given, select an appropriate one.
3230          */
3231         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3232                 switch (mtd->oobsize) {
3233                 case 8:
3234                         chip->ecc.layout = &nand_oob_8;
3235                         break;
3236                 case 16:
3237                         chip->ecc.layout = &nand_oob_16;
3238                         break;
3239                 case 64:
3240                         chip->ecc.layout = &nand_oob_64;
3241                         break;
3242                 case 128:
3243                         chip->ecc.layout = &nand_oob_128;
3244                         break;
3245                 default:
3246                         printk(KERN_WARNING "No oob scheme defined for "
3247                                "oobsize %d\n", mtd->oobsize);
3248                         BUG();
3249                 }
3250         }
3251
3252         if (!chip->write_page)
3253                 chip->write_page = nand_write_page;
3254
3255         /*
3256          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3257          * selected and we have 256 byte pagesize fallback to software ECC
3258          */
3259
3260         switch (chip->ecc.mode) {
3261         case NAND_ECC_HW_OOB_FIRST:
3262                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3263                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3264                      !chip->ecc.hwctl) {
3265                         printk(KERN_WARNING "No ECC functions supplied; "
3266                                "Hardware ECC not possible\n");
3267                         BUG();
3268                 }
3269                 if (!chip->ecc.read_page)
3270                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3271
3272         case NAND_ECC_HW:
3273                 /* Use standard hwecc read page function? */
3274                 if (!chip->ecc.read_page)
3275                         chip->ecc.read_page = nand_read_page_hwecc;
3276                 if (!chip->ecc.write_page)
3277                         chip->ecc.write_page = nand_write_page_hwecc;
3278                 if (!chip->ecc.read_page_raw)
3279                         chip->ecc.read_page_raw = nand_read_page_raw;
3280                 if (!chip->ecc.write_page_raw)
3281                         chip->ecc.write_page_raw = nand_write_page_raw;
3282                 if (!chip->ecc.read_oob)
3283                         chip->ecc.read_oob = nand_read_oob_std;
3284                 if (!chip->ecc.write_oob)
3285                         chip->ecc.write_oob = nand_write_oob_std;
3286
3287         case NAND_ECC_HW_SYNDROME:
3288                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3289                      !chip->ecc.hwctl) &&
3290                     (!chip->ecc.read_page ||
3291                      chip->ecc.read_page == nand_read_page_hwecc ||
3292                      !chip->ecc.write_page ||
3293                      chip->ecc.write_page == nand_write_page_hwecc)) {
3294                         printk(KERN_WARNING "No ECC functions supplied; "
3295                                "Hardware ECC not possible\n");
3296                         BUG();
3297                 }
3298                 /* Use standard syndrome read/write page function? */
3299                 if (!chip->ecc.read_page)
3300                         chip->ecc.read_page = nand_read_page_syndrome;
3301                 if (!chip->ecc.write_page)
3302                         chip->ecc.write_page = nand_write_page_syndrome;
3303                 if (!chip->ecc.read_page_raw)
3304                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3305                 if (!chip->ecc.write_page_raw)
3306                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3307                 if (!chip->ecc.read_oob)
3308                         chip->ecc.read_oob = nand_read_oob_syndrome;
3309                 if (!chip->ecc.write_oob)
3310                         chip->ecc.write_oob = nand_write_oob_syndrome;
3311
3312                 if (mtd->writesize >= chip->ecc.size)
3313                         break;
3314                 printk(KERN_WARNING "%d byte HW ECC not possible on "
3315                        "%d byte page size, fallback to SW ECC\n",
3316                        chip->ecc.size, mtd->writesize);
3317                 chip->ecc.mode = NAND_ECC_SOFT;
3318
3319         case NAND_ECC_SOFT:
3320                 chip->ecc.calculate = nand_calculate_ecc;
3321                 chip->ecc.correct = nand_correct_data;
3322                 chip->ecc.read_page = nand_read_page_swecc;
3323                 chip->ecc.read_subpage = nand_read_subpage;
3324                 chip->ecc.write_page = nand_write_page_swecc;
3325                 chip->ecc.read_page_raw = nand_read_page_raw;
3326                 chip->ecc.write_page_raw = nand_write_page_raw;
3327                 chip->ecc.read_oob = nand_read_oob_std;
3328                 chip->ecc.write_oob = nand_write_oob_std;
3329                 if (!chip->ecc.size)
3330                         chip->ecc.size = 256;
3331                 chip->ecc.bytes = 3;
3332                 break;
3333
3334         case NAND_ECC_SOFT_BCH:
3335                 if (!mtd_nand_has_bch()) {
3336                         printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3337                         BUG();
3338                 }
3339                 chip->ecc.calculate = nand_bch_calculate_ecc;
3340                 chip->ecc.correct = nand_bch_correct_data;
3341                 chip->ecc.read_page = nand_read_page_swecc;
3342                 chip->ecc.read_subpage = nand_read_subpage;
3343                 chip->ecc.write_page = nand_write_page_swecc;
3344                 chip->ecc.read_page_raw = nand_read_page_raw;
3345                 chip->ecc.write_page_raw = nand_write_page_raw;
3346                 chip->ecc.read_oob = nand_read_oob_std;
3347                 chip->ecc.write_oob = nand_write_oob_std;
3348                 /*
3349                  * Board driver should supply ecc.size and ecc.bytes values to
3350                  * select how many bits are correctable; see nand_bch_init()
3351                  * for details. Otherwise, default to 4 bits for large page
3352                  * devices.
3353                  */
3354                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3355                         chip->ecc.size = 512;
3356                         chip->ecc.bytes = 7;
3357                 }
3358                 chip->ecc.priv = nand_bch_init(mtd,
3359                                                chip->ecc.size,
3360                                                chip->ecc.bytes,
3361                                                &chip->ecc.layout);
3362                 if (!chip->ecc.priv) {
3363                         printk(KERN_WARNING "BCH ECC initialization failed!\n");
3364                         BUG();
3365                 }
3366                 break;
3367
3368         case NAND_ECC_NONE:
3369                 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3370                        "This is not recommended !!\n");
3371                 chip->ecc.read_page = nand_read_page_raw;
3372                 chip->ecc.write_page = nand_write_page_raw;
3373                 chip->ecc.read_oob = nand_read_oob_std;
3374                 chip->ecc.read_page_raw = nand_read_page_raw;
3375                 chip->ecc.write_page_raw = nand_write_page_raw;
3376                 chip->ecc.write_oob = nand_write_oob_std;
3377                 chip->ecc.size = mtd->writesize;
3378                 chip->ecc.bytes = 0;
3379                 break;
3380
3381         default:
3382                 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3383                        chip->ecc.mode);
3384                 BUG();
3385         }
3386
3387         /*
3388          * The number of bytes available for a client to place data into
3389          * the out of band area.
3390          */
3391         chip->ecc.layout->oobavail = 0;
3392         for (i = 0; chip->ecc.layout->oobfree[i].length
3393                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3394                 chip->ecc.layout->oobavail +=
3395                         chip->ecc.layout->oobfree[i].length;
3396         mtd->oobavail = chip->ecc.layout->oobavail;
3397
3398         /*
3399          * Set the number of read / write steps for one page depending on ECC
3400          * mode.
3401          */
3402         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3403         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3404                 printk(KERN_WARNING "Invalid ECC parameters\n");
3405                 BUG();
3406         }
3407         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3408
3409         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3410         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3411             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3412                 switch (chip->ecc.steps) {
3413                 case 2:
3414                         mtd->subpage_sft = 1;
3415                         break;
3416                 case 4:
3417                 case 8:
3418                 case 16:
3419                         mtd->subpage_sft = 2;
3420                         break;
3421                 }
3422         }
3423         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3424
3425         /* Initialize state */
3426         chip->state = FL_READY;
3427
3428         /* De-select the device */
3429         chip->select_chip(mtd, -1);
3430
3431         /* Invalidate the pagebuffer reference */
3432         chip->pagebuf = -1;
3433
3434         /* Fill in remaining MTD driver data */
3435         mtd->type = MTD_NANDFLASH;
3436         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3437                                                 MTD_CAP_NANDFLASH;
3438         mtd->erase = nand_erase;
3439         mtd->point = NULL;
3440         mtd->unpoint = NULL;
3441         mtd->read = nand_read;
3442         mtd->write = nand_write;
3443         mtd->panic_write = panic_nand_write;
3444         mtd->read_oob = nand_read_oob;
3445         mtd->write_oob = nand_write_oob;
3446         mtd->sync = nand_sync;
3447         mtd->lock = NULL;
3448         mtd->unlock = NULL;
3449         mtd->suspend = nand_suspend;
3450         mtd->resume = nand_resume;
3451         mtd->block_isbad = nand_block_isbad;
3452         mtd->block_markbad = nand_block_markbad;
3453         mtd->writebufsize = mtd->writesize;
3454
3455         /* propagate ecc.layout to mtd_info */
3456         mtd->ecclayout = chip->ecc.layout;
3457
3458         /* Check, if we should skip the bad block table scan */
3459         if (chip->options & NAND_SKIP_BBTSCAN)
3460                 return 0;
3461
3462         /* Build bad block table */
3463         return chip->scan_bbt(mtd);
3464 }
3465 EXPORT_SYMBOL(nand_scan_tail);
3466
3467 /*
3468  * is_module_text_address() isn't exported, and it's mostly a pointless
3469  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3470  * to call us from in-kernel code if the core NAND support is modular.
3471  */
3472 #ifdef MODULE
3473 #define caller_is_module() (1)
3474 #else
3475 #define caller_is_module() \
3476         is_module_text_address((unsigned long)__builtin_return_address(0))
3477 #endif
3478
3479 /**
3480  * nand_scan - [NAND Interface] Scan for the NAND device
3481  * @mtd: MTD device structure
3482  * @maxchips: number of chips to scan for
3483  *
3484  * This fills out all the uninitialized function pointers with the defaults.
3485  * The flash ID is read and the mtd/chip structures are filled with the
3486  * appropriate values. The mtd->owner field must be set to the module of the
3487  * caller.
3488  */
3489 int nand_scan(struct mtd_info *mtd, int maxchips)
3490 {
3491         int ret;
3492
3493         /* Many callers got this wrong, so check for it for a while... */
3494         if (!mtd->owner && caller_is_module()) {
3495                 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3496                                 __func__);
3497                 BUG();
3498         }
3499
3500         ret = nand_scan_ident(mtd, maxchips, NULL);
3501         if (!ret)
3502                 ret = nand_scan_tail(mtd);
3503         return ret;
3504 }
3505 EXPORT_SYMBOL(nand_scan);
3506
3507 /**
3508  * nand_release - [NAND Interface] Free resources held by the NAND device
3509  * @mtd: MTD device structure
3510  */
3511 void nand_release(struct mtd_info *mtd)
3512 {
3513         struct nand_chip *chip = mtd->priv;
3514
3515         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3516                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3517
3518         mtd_device_unregister(mtd);
3519
3520         /* Free bad block table memory */
3521         kfree(chip->bbt);
3522         if (!(chip->options & NAND_OWN_BUFFERS))
3523                 kfree(chip->buffers);
3524
3525         /* Free bad block descriptor memory */
3526         if (chip->badblock_pattern && chip->badblock_pattern->options
3527                         & NAND_BBT_DYNAMICSTRUCT)
3528                 kfree(chip->badblock_pattern);
3529 }
3530 EXPORT_SYMBOL_GPL(nand_release);
3531
3532 static int __init nand_base_init(void)
3533 {
3534         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3535         return 0;
3536 }
3537
3538 static void __exit nand_base_exit(void)
3539 {
3540         led_trigger_unregister_simple(nand_led_trigger);
3541 }
3542
3543 module_init(nand_base_init);
3544 module_exit(nand_base_exit);
3545
3546 MODULE_LICENSE("GPL");
3547 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3548 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3549 MODULE_DESCRIPTION("Generic NAND flash driver code");