2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
36 #include <asm/mach/flash.h>
37 #include <mach/mxc_nand.h>
38 #include <mach/hardware.h>
40 #define DRIVER_NAME "mxc_nand"
42 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
43 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
44 #define nfc_is_v3_2() (cpu_is_mx51() || cpu_is_mx53())
45 #define nfc_is_v3() nfc_is_v3_2()
47 /* Addresses for NFC registers */
48 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
57 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
60 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
61 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
62 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
63 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
64 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
65 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
66 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
67 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
68 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
69 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
71 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
72 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
73 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
74 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
75 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
76 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
77 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
78 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
79 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
80 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
82 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
85 * Operation modes for the NFC. Valid for v1, v2 and v3
88 #define NFC_CMD (1 << 0)
89 #define NFC_ADDR (1 << 1)
90 #define NFC_INPUT (1 << 2)
91 #define NFC_OUTPUT (1 << 3)
92 #define NFC_ID (1 << 4)
93 #define NFC_STATUS (1 << 5)
95 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
96 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
98 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
99 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
100 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
102 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
104 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
106 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
107 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
108 #define NFC_V3_WRPROT_LOCK (1 << 1)
109 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
110 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
112 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
114 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
115 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
116 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
117 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
118 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
119 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
120 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
122 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
123 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
124 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
125 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
126 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
127 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
129 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
130 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
131 #define NFC_V3_CONFIG3_FW8 (1 << 3)
132 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
133 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
134 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
135 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
137 #define NFC_V3_IPC (host->regs_ip + 0x2C)
138 #define NFC_V3_IPC_CREQ (1 << 0)
139 #define NFC_V3_IPC_INT (1 << 31)
141 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
143 struct mxc_nand_host {
145 struct nand_chip nand;
153 void __iomem *regs_axi;
154 void __iomem *regs_ip;
162 struct completion op_completion;
165 unsigned int buf_start;
168 void (*preset)(struct mtd_info *);
169 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
170 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
171 void (*send_page)(struct mtd_info *, unsigned int);
172 void (*send_read_id)(struct mxc_nand_host *);
173 uint16_t (*get_dev_status)(struct mxc_nand_host *);
174 int (*check_int)(struct mxc_nand_host *);
175 void (*irq_control)(struct mxc_nand_host *, int);
178 /* OOB placement block for use with hardware ecc generation */
179 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
181 .eccpos = {6, 7, 8, 9, 10},
182 .oobfree = {{0, 5}, {12, 4}, }
185 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
187 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
188 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
189 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
192 /* OOB description for 512 byte pages with 16 byte OOB */
193 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
196 7, 8, 9, 10, 11, 12, 13, 14, 15
199 {.offset = 0, .length = 5}
203 /* OOB description for 2048 byte pages with 64 byte OOB */
204 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
207 7, 8, 9, 10, 11, 12, 13, 14, 15,
208 23, 24, 25, 26, 27, 28, 29, 30, 31,
209 39, 40, 41, 42, 43, 44, 45, 46, 47,
210 55, 56, 57, 58, 59, 60, 61, 62, 63
213 {.offset = 2, .length = 4},
214 {.offset = 16, .length = 7},
215 {.offset = 32, .length = 7},
216 {.offset = 48, .length = 7}
220 /* OOB description for 4096 byte pages with 128 byte OOB */
221 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
224 7, 8, 9, 10, 11, 12, 13, 14, 15,
225 23, 24, 25, 26, 27, 28, 29, 30, 31,
226 39, 40, 41, 42, 43, 44, 45, 46, 47,
227 55, 56, 57, 58, 59, 60, 61, 62, 63,
228 71, 72, 73, 74, 75, 76, 77, 78, 79,
229 87, 88, 89, 90, 91, 92, 93, 94, 95,
230 103, 104, 105, 106, 107, 108, 109, 110, 111,
231 119, 120, 121, 122, 123, 124, 125, 126, 127,
234 {.offset = 2, .length = 4},
235 {.offset = 16, .length = 7},
236 {.offset = 32, .length = 7},
237 {.offset = 48, .length = 7},
238 {.offset = 64, .length = 7},
239 {.offset = 80, .length = 7},
240 {.offset = 96, .length = 7},
241 {.offset = 112, .length = 7},
245 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
247 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
249 struct mxc_nand_host *host = dev_id;
251 if (!host->check_int(host))
254 host->irq_control(host, 0);
256 complete(&host->op_completion);
261 static int check_int_v3(struct mxc_nand_host *host)
265 tmp = readl(NFC_V3_IPC);
266 if (!(tmp & NFC_V3_IPC_INT))
269 tmp &= ~NFC_V3_IPC_INT;
270 writel(tmp, NFC_V3_IPC);
275 static int check_int_v1_v2(struct mxc_nand_host *host)
279 tmp = readw(NFC_V1_V2_CONFIG2);
280 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
284 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
290 * It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
291 * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
292 * driver can enable/disable the irq line rather than simply masking the
295 static void irq_control_mx21(struct mxc_nand_host *host, int activate)
298 enable_irq(host->irq);
300 disable_irq_nosync(host->irq);
303 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
307 tmp = readw(NFC_V1_V2_CONFIG1);
310 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
312 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
314 writew(tmp, NFC_V1_V2_CONFIG1);
317 static void irq_control_v3(struct mxc_nand_host *host, int activate)
321 tmp = readl(NFC_V3_CONFIG2);
324 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
326 tmp |= NFC_V3_CONFIG2_INT_MSK;
328 writel(tmp, NFC_V3_CONFIG2);
331 /* This function polls the NANDFC to wait for the basic operation to
332 * complete by checking the INT bit of config2 register.
334 static void wait_op_done(struct mxc_nand_host *host, int useirq)
336 int max_retries = 8000;
339 if (!host->check_int(host)) {
340 INIT_COMPLETION(host->op_completion);
341 host->irq_control(host, 1);
342 wait_for_completion(&host->op_completion);
345 while (max_retries-- > 0) {
346 if (host->check_int(host))
352 pr_debug("%s: INT not set\n", __func__);
356 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
359 writel(cmd, NFC_V3_FLASH_CMD);
361 /* send out command */
362 writel(NFC_CMD, NFC_V3_LAUNCH);
364 /* Wait for operation to complete */
365 wait_op_done(host, useirq);
368 /* This function issues the specified command to the NAND device and
369 * waits for completion. */
370 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
372 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
374 writew(cmd, NFC_V1_V2_FLASH_CMD);
375 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
377 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
378 int max_retries = 100;
379 /* Reset completion is indicated by NFC_CONFIG2 */
381 while (max_retries-- > 0) {
382 if (readw(NFC_V1_V2_CONFIG2) == 0) {
388 pr_debug("%s: RESET failed\n", __func__);
390 /* Wait for operation to complete */
391 wait_op_done(host, useirq);
395 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
398 writel(addr, NFC_V3_FLASH_ADDR0);
400 /* send out address */
401 writel(NFC_ADDR, NFC_V3_LAUNCH);
403 wait_op_done(host, 0);
406 /* This function sends an address (or partial address) to the
407 * NAND device. The address is used to select the source/destination for
409 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
411 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
413 writew(addr, NFC_V1_V2_FLASH_ADDR);
414 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
416 /* Wait for operation to complete */
417 wait_op_done(host, islast);
420 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
422 struct nand_chip *nand_chip = mtd->priv;
423 struct mxc_nand_host *host = nand_chip->priv;
426 tmp = readl(NFC_V3_CONFIG1);
428 writel(tmp, NFC_V3_CONFIG1);
430 /* transfer data from NFC ram to nand */
431 writel(ops, NFC_V3_LAUNCH);
433 wait_op_done(host, false);
436 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
438 struct nand_chip *nand_chip = mtd->priv;
439 struct mxc_nand_host *host = nand_chip->priv;
442 if (nfc_is_v1() && mtd->writesize > 512)
447 for (i = 0; i < bufs; i++) {
449 /* NANDFC buffer 0 is used for page read/write */
450 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
452 writew(ops, NFC_V1_V2_CONFIG2);
454 /* Wait for operation to complete */
455 wait_op_done(host, true);
459 static void send_read_id_v3(struct mxc_nand_host *host)
461 /* Read ID into main buffer */
462 writel(NFC_ID, NFC_V3_LAUNCH);
464 wait_op_done(host, true);
466 memcpy(host->data_buf, host->main_area0, 16);
469 /* Request the NANDFC to perform a read of the NAND device ID. */
470 static void send_read_id_v1_v2(struct mxc_nand_host *host)
472 struct nand_chip *this = &host->nand;
474 /* NANDFC buffer 0 is used for device ID output */
475 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
477 writew(NFC_ID, NFC_V1_V2_CONFIG2);
479 /* Wait for operation to complete */
480 wait_op_done(host, true);
482 memcpy(host->data_buf, host->main_area0, 16);
484 if (this->options & NAND_BUSWIDTH_16) {
485 /* compress the ID info */
486 host->data_buf[1] = host->data_buf[2];
487 host->data_buf[2] = host->data_buf[4];
488 host->data_buf[3] = host->data_buf[6];
489 host->data_buf[4] = host->data_buf[8];
490 host->data_buf[5] = host->data_buf[10];
494 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
496 writew(NFC_STATUS, NFC_V3_LAUNCH);
497 wait_op_done(host, true);
499 return readl(NFC_V3_CONFIG1) >> 16;
502 /* This function requests the NANDFC to perform a read of the
503 * NAND device status and returns the current status. */
504 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
506 void __iomem *main_buf = host->main_area0;
510 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
513 * The device status is stored in main_area0. To
514 * prevent corruption of the buffer save the value
515 * and restore it afterwards.
517 store = readl(main_buf);
519 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
520 wait_op_done(host, true);
522 ret = readw(main_buf);
524 writel(store, main_buf);
529 /* This functions is used by upper layer to checks if device is ready */
530 static int mxc_nand_dev_ready(struct mtd_info *mtd)
533 * NFC handles R/B internally. Therefore, this function
534 * always returns status as ready.
539 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
542 * If HW ECC is enabled, we turn it on during init. There is
543 * no need to enable again here.
547 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
548 u_char *read_ecc, u_char *calc_ecc)
550 struct nand_chip *nand_chip = mtd->priv;
551 struct mxc_nand_host *host = nand_chip->priv;
554 * 1-Bit errors are automatically corrected in HW. No need for
555 * additional correction. 2-Bit errors cannot be corrected by
556 * HW ECC, so we need to return failure
558 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
560 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
561 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
568 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
569 u_char *read_ecc, u_char *calc_ecc)
571 struct nand_chip *nand_chip = mtd->priv;
572 struct mxc_nand_host *host = nand_chip->priv;
576 u8 ecc_bit_mask, err_limit;
578 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
579 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
581 no_subpages = mtd->writesize >> 9;
584 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
586 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
589 err = ecc_stat & ecc_bit_mask;
590 if (err > err_limit) {
591 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
597 } while (--no_subpages);
599 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
604 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
610 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
612 struct nand_chip *nand_chip = mtd->priv;
613 struct mxc_nand_host *host = nand_chip->priv;
616 /* Check for status request */
617 if (host->status_request)
618 return host->get_dev_status(host) & 0xFF;
620 ret = *(uint8_t *)(host->data_buf + host->buf_start);
626 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
628 struct nand_chip *nand_chip = mtd->priv;
629 struct mxc_nand_host *host = nand_chip->priv;
632 ret = *(uint16_t *)(host->data_buf + host->buf_start);
633 host->buf_start += 2;
638 /* Write data of length len to buffer buf. The data to be
639 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
640 * Operation by the NFC, the data is written to NAND Flash */
641 static void mxc_nand_write_buf(struct mtd_info *mtd,
642 const u_char *buf, int len)
644 struct nand_chip *nand_chip = mtd->priv;
645 struct mxc_nand_host *host = nand_chip->priv;
646 u16 col = host->buf_start;
647 int n = mtd->oobsize + mtd->writesize - col;
651 memcpy(host->data_buf + col, buf, n);
653 host->buf_start += n;
656 /* Read the data buffer from the NAND Flash. To read the data from NAND
657 * Flash first the data output cycle is initiated by the NFC, which copies
658 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
660 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
662 struct nand_chip *nand_chip = mtd->priv;
663 struct mxc_nand_host *host = nand_chip->priv;
664 u16 col = host->buf_start;
665 int n = mtd->oobsize + mtd->writesize - col;
669 memcpy(buf, host->data_buf + col, n);
671 host->buf_start += n;
674 /* Used by the upper layer to verify the data in NAND Flash
675 * with the data in the buf. */
676 static int mxc_nand_verify_buf(struct mtd_info *mtd,
677 const u_char *buf, int len)
682 /* This function is used by upper layer for select and
683 * deselect of the NAND chip */
684 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
686 struct nand_chip *nand_chip = mtd->priv;
687 struct mxc_nand_host *host = nand_chip->priv;
690 /* Disable the NFC clock */
692 clk_disable(host->clk);
698 if (!host->clk_act) {
699 /* Enable the NFC clock */
700 clk_enable(host->clk);
705 host->active_cs = chip;
706 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
711 * Function to transfer data to/from spare area.
713 static void copy_spare(struct mtd_info *mtd, bool bfrom)
715 struct nand_chip *this = mtd->priv;
716 struct mxc_nand_host *host = this->priv;
718 u16 n = mtd->writesize >> 9;
719 u8 *d = host->data_buf + mtd->writesize;
720 u8 *s = host->spare0;
721 u16 t = host->spare_len;
723 j = (mtd->oobsize / n >> 1) << 1;
726 for (i = 0; i < n - 1; i++)
727 memcpy(d + i * j, s + i * t, j);
729 /* the last section */
730 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
732 for (i = 0; i < n - 1; i++)
733 memcpy(&s[i * t], &d[i * j], j);
735 /* the last section */
736 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
740 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
742 struct nand_chip *nand_chip = mtd->priv;
743 struct mxc_nand_host *host = nand_chip->priv;
745 /* Write out column address, if necessary */
748 * MXC NANDFC can only perform full page+spare or
749 * spare-only read/write. When the upper layers
750 * perform a read/write buf operation, the saved column
751 * address is used to index into the full page.
753 host->send_addr(host, 0, page_addr == -1);
754 if (mtd->writesize > 512)
755 /* another col addr cycle for 2k page */
756 host->send_addr(host, 0, false);
759 /* Write out page address, if necessary */
760 if (page_addr != -1) {
761 /* paddr_0 - p_addr_7 */
762 host->send_addr(host, (page_addr & 0xff), false);
764 if (mtd->writesize > 512) {
765 if (mtd->size >= 0x10000000) {
766 /* paddr_8 - paddr_15 */
767 host->send_addr(host, (page_addr >> 8) & 0xff, false);
768 host->send_addr(host, (page_addr >> 16) & 0xff, true);
770 /* paddr_8 - paddr_15 */
771 host->send_addr(host, (page_addr >> 8) & 0xff, true);
773 /* One more address cycle for higher density devices */
774 if (mtd->size >= 0x4000000) {
775 /* paddr_8 - paddr_15 */
776 host->send_addr(host, (page_addr >> 8) & 0xff, false);
777 host->send_addr(host, (page_addr >> 16) & 0xff, true);
779 /* paddr_8 - paddr_15 */
780 host->send_addr(host, (page_addr >> 8) & 0xff, true);
786 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
787 * on how much oob the nand chip has. For 8bit ecc we need at least
788 * 26 bytes of oob data per 512 byte block.
790 static int get_eccsize(struct mtd_info *mtd)
792 int oobbytes_per_512 = 0;
794 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
796 if (oobbytes_per_512 < 26)
802 static void preset_v1_v2(struct mtd_info *mtd)
804 struct nand_chip *nand_chip = mtd->priv;
805 struct mxc_nand_host *host = nand_chip->priv;
806 uint16_t config1 = 0;
808 if (nand_chip->ecc.mode == NAND_ECC_HW)
809 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
812 config1 |= NFC_V2_CONFIG1_FP_INT;
815 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
817 if (nfc_is_v21() && mtd->writesize) {
818 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
820 host->eccsize = get_eccsize(mtd);
821 if (host->eccsize == 4)
822 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
824 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
829 writew(config1, NFC_V1_V2_CONFIG1);
830 /* preset operation */
832 /* Unlock the internal RAM Buffer */
833 writew(0x2, NFC_V1_V2_CONFIG);
835 /* Blocks to be unlocked */
837 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
838 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
839 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
840 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
841 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
842 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
843 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
844 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
845 } else if (nfc_is_v1()) {
846 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
847 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
851 /* Unlock Block Command for given address range */
852 writew(0x4, NFC_V1_V2_WRPROT);
855 static void preset_v3(struct mtd_info *mtd)
857 struct nand_chip *chip = mtd->priv;
858 struct mxc_nand_host *host = chip->priv;
859 uint32_t config2, config3;
862 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
863 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
865 /* Unlock the internal RAM Buffer */
866 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
869 /* Blocks to be unlocked */
870 for (i = 0; i < NAND_MAX_CHIPS; i++)
871 writel(0x0 | (0xffff << 16),
872 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
874 writel(0, NFC_V3_IPC);
876 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
877 NFC_V3_CONFIG2_2CMD_PHASES |
878 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
879 NFC_V3_CONFIG2_ST_CMD(0x70) |
880 NFC_V3_CONFIG2_INT_MSK |
881 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
883 if (chip->ecc.mode == NAND_ECC_HW)
884 config2 |= NFC_V3_CONFIG2_ECC_EN;
886 addr_phases = fls(chip->pagemask) >> 3;
888 if (mtd->writesize == 2048) {
889 config2 |= NFC_V3_CONFIG2_PS_2048;
890 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
891 } else if (mtd->writesize == 4096) {
892 config2 |= NFC_V3_CONFIG2_PS_4096;
893 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
895 config2 |= NFC_V3_CONFIG2_PS_512;
896 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
899 if (mtd->writesize) {
900 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
901 host->eccsize = get_eccsize(mtd);
902 if (host->eccsize == 8)
903 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
906 writel(config2, NFC_V3_CONFIG2);
908 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
909 NFC_V3_CONFIG3_NO_SDMA |
910 NFC_V3_CONFIG3_RBB_MODE |
911 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
912 NFC_V3_CONFIG3_ADD_OP(0);
914 if (!(chip->options & NAND_BUSWIDTH_16))
915 config3 |= NFC_V3_CONFIG3_FW8;
917 writel(config3, NFC_V3_CONFIG3);
919 writel(0, NFC_V3_DELAY_LINE);
922 /* Used by the upper layer to write command to NAND Flash for
923 * different operations to be carried out on NAND Flash */
924 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
925 int column, int page_addr)
927 struct nand_chip *nand_chip = mtd->priv;
928 struct mxc_nand_host *host = nand_chip->priv;
930 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
931 command, column, page_addr);
933 /* Reset command state information */
934 host->status_request = false;
936 /* Command pre-processing step */
940 host->send_cmd(host, command, false);
943 case NAND_CMD_STATUS:
945 host->status_request = true;
947 host->send_cmd(host, command, true);
948 mxc_do_addr_cycle(mtd, column, page_addr);
952 case NAND_CMD_READOOB:
953 if (command == NAND_CMD_READ0)
954 host->buf_start = column;
956 host->buf_start = column + mtd->writesize;
958 command = NAND_CMD_READ0; /* only READ0 is valid */
960 host->send_cmd(host, command, false);
961 mxc_do_addr_cycle(mtd, column, page_addr);
963 if (mtd->writesize > 512)
964 host->send_cmd(host, NAND_CMD_READSTART, true);
966 host->send_page(mtd, NFC_OUTPUT);
968 memcpy(host->data_buf, host->main_area0, mtd->writesize);
969 copy_spare(mtd, true);
973 if (column >= mtd->writesize)
974 /* call ourself to read a page */
975 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
977 host->buf_start = column;
979 host->send_cmd(host, command, false);
980 mxc_do_addr_cycle(mtd, column, page_addr);
983 case NAND_CMD_PAGEPROG:
984 memcpy(host->main_area0, host->data_buf, mtd->writesize);
985 copy_spare(mtd, false);
986 host->send_page(mtd, NFC_INPUT);
987 host->send_cmd(host, command, true);
988 mxc_do_addr_cycle(mtd, column, page_addr);
991 case NAND_CMD_READID:
992 host->send_cmd(host, command, true);
993 mxc_do_addr_cycle(mtd, column, page_addr);
994 host->send_read_id(host);
995 host->buf_start = column;
998 case NAND_CMD_ERASE1:
999 case NAND_CMD_ERASE2:
1000 host->send_cmd(host, command, false);
1001 mxc_do_addr_cycle(mtd, column, page_addr);
1008 * The generic flash bbt decriptors overlap with our ecc
1009 * hardware, so define some i.MX specific ones.
1011 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1012 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1014 static struct nand_bbt_descr bbt_main_descr = {
1015 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1016 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1021 .pattern = bbt_pattern,
1024 static struct nand_bbt_descr bbt_mirror_descr = {
1025 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1026 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1031 .pattern = mirror_pattern,
1034 static int __init mxcnd_probe(struct platform_device *pdev)
1036 struct nand_chip *this;
1037 struct mtd_info *mtd;
1038 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1039 struct mxc_nand_host *host;
1040 struct resource *res;
1042 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1044 /* Allocate memory for MTD device structure and private data */
1045 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1046 NAND_MAX_OOBSIZE, GFP_KERNEL);
1050 host->data_buf = (uint8_t *)(host + 1);
1052 host->dev = &pdev->dev;
1053 /* structures must be linked */
1057 mtd->owner = THIS_MODULE;
1058 mtd->dev.parent = &pdev->dev;
1059 mtd->name = DRIVER_NAME;
1061 /* 50 us command delay time */
1062 this->chip_delay = 5;
1065 this->dev_ready = mxc_nand_dev_ready;
1066 this->cmdfunc = mxc_nand_command;
1067 this->select_chip = mxc_nand_select_chip;
1068 this->read_byte = mxc_nand_read_byte;
1069 this->read_word = mxc_nand_read_word;
1070 this->write_buf = mxc_nand_write_buf;
1071 this->read_buf = mxc_nand_read_buf;
1072 this->verify_buf = mxc_nand_verify_buf;
1074 host->clk = clk_get(&pdev->dev, "nfc");
1075 if (IS_ERR(host->clk)) {
1076 err = PTR_ERR(host->clk);
1080 clk_enable(host->clk);
1083 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1089 host->base = ioremap(res->start, resource_size(res));
1095 host->main_area0 = host->base;
1097 if (nfc_is_v1() || nfc_is_v21()) {
1098 host->preset = preset_v1_v2;
1099 host->send_cmd = send_cmd_v1_v2;
1100 host->send_addr = send_addr_v1_v2;
1101 host->send_page = send_page_v1_v2;
1102 host->send_read_id = send_read_id_v1_v2;
1103 host->get_dev_status = get_dev_status_v1_v2;
1104 host->check_int = check_int_v1_v2;
1106 host->irq_control = irq_control_mx21;
1108 host->irq_control = irq_control_v1_v2;
1112 host->regs = host->base + 0x1e00;
1113 host->spare0 = host->base + 0x1000;
1114 host->spare_len = 64;
1115 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1116 oob_largepage = &nandv2_hw_eccoob_largepage;
1117 this->ecc.bytes = 9;
1118 } else if (nfc_is_v1()) {
1119 host->regs = host->base + 0xe00;
1120 host->spare0 = host->base + 0x800;
1121 host->spare_len = 16;
1122 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1123 oob_largepage = &nandv1_hw_eccoob_largepage;
1124 this->ecc.bytes = 3;
1126 } else if (nfc_is_v3_2()) {
1127 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1132 host->regs_ip = ioremap(res->start, resource_size(res));
1133 if (!host->regs_ip) {
1137 host->regs_axi = host->base + 0x1e00;
1138 host->spare0 = host->base + 0x1000;
1139 host->spare_len = 64;
1140 host->preset = preset_v3;
1141 host->send_cmd = send_cmd_v3;
1142 host->send_addr = send_addr_v3;
1143 host->send_page = send_page_v3;
1144 host->send_read_id = send_read_id_v3;
1145 host->check_int = check_int_v3;
1146 host->get_dev_status = get_dev_status_v3;
1147 host->irq_control = irq_control_v3;
1148 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1149 oob_largepage = &nandv2_hw_eccoob_largepage;
1153 this->ecc.size = 512;
1154 this->ecc.layout = oob_smallpage;
1156 if (pdata->hw_ecc) {
1157 this->ecc.calculate = mxc_nand_calculate_ecc;
1158 this->ecc.hwctl = mxc_nand_enable_hwecc;
1160 this->ecc.correct = mxc_nand_correct_data_v1;
1162 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1163 this->ecc.mode = NAND_ECC_HW;
1165 this->ecc.mode = NAND_ECC_SOFT;
1168 /* NAND bus width determines access funtions used by upper layer */
1169 if (pdata->width == 2)
1170 this->options |= NAND_BUSWIDTH_16;
1172 if (pdata->flash_bbt) {
1173 this->bbt_td = &bbt_main_descr;
1174 this->bbt_md = &bbt_mirror_descr;
1175 /* update flash based bbt */
1176 this->bbt_options |= NAND_BBT_USE_FLASH;
1179 init_completion(&host->op_completion);
1181 host->irq = platform_get_irq(pdev, 0);
1184 * mask the interrupt. For i.MX21 explicitely call
1185 * irq_control_v1_v2 to use the mask bit. We can't call
1186 * disable_irq_nosync() for an interrupt we do not own yet.
1189 irq_control_v1_v2(host, 0);
1191 host->irq_control(host, 0);
1193 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1197 host->irq_control(host, 0);
1200 * Now that the interrupt is disabled make sure the interrupt
1201 * mask bit is cleared on i.MX21. Otherwise we can't read
1202 * the interrupt status bit on this machine.
1205 irq_control_v1_v2(host, 1);
1207 /* first scan to find the device and get the page size */
1208 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1213 /* Call preset again, with correct writesize this time */
1216 if (mtd->writesize == 2048)
1217 this->ecc.layout = oob_largepage;
1218 if (nfc_is_v21() && mtd->writesize == 4096)
1219 this->ecc.layout = &nandv2_hw_eccoob_4k;
1221 /* second phase scan */
1222 if (nand_scan_tail(mtd)) {
1227 /* Register the partitions */
1228 mtd_device_parse_register(mtd, part_probes, 0,
1229 pdata->parts, pdata->nr_parts);
1231 platform_set_drvdata(pdev, host);
1236 free_irq(host->irq, host);
1239 iounmap(host->regs_ip);
1240 iounmap(host->base);
1249 static int __devexit mxcnd_remove(struct platform_device *pdev)
1251 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1255 platform_set_drvdata(pdev, NULL);
1257 nand_release(&host->mtd);
1258 free_irq(host->irq, host);
1260 iounmap(host->regs_ip);
1261 iounmap(host->base);
1267 static struct platform_driver mxcnd_driver = {
1269 .name = DRIVER_NAME,
1271 .remove = __devexit_p(mxcnd_remove),
1274 static int __init mxc_nd_init(void)
1276 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1279 static void __exit mxc_nd_cleanup(void)
1281 /* Unregister the device structure */
1282 platform_driver_unregister(&mxcnd_driver);
1285 module_init(mxc_nd_init);
1286 module_exit(mxc_nd_cleanup);
1288 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1289 MODULE_DESCRIPTION("MXC NAND MTD driver");
1290 MODULE_LICENSE("GPL");