2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35 #include <linux/of_device.h>
36 #include <linux/of_mtd.h>
38 #include <asm/mach/flash.h>
39 #include <mach/mxc_nand.h>
40 #include <mach/hardware.h>
42 #define DRIVER_NAME "mxc_nand"
44 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
45 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
46 #define nfc_is_v3_2() (cpu_is_mx51() || cpu_is_mx53())
47 #define nfc_is_v3() nfc_is_v3_2()
49 /* Addresses for NFC registers */
50 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
51 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
52 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
53 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
54 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
55 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
56 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
57 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
58 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
59 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
60 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
61 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
62 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
63 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
64 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
65 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
66 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
67 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
68 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
69 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
70 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
71 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
73 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
74 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
75 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
76 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
77 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
78 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
79 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
80 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
81 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
82 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
84 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
87 * Operation modes for the NFC. Valid for v1, v2 and v3
90 #define NFC_CMD (1 << 0)
91 #define NFC_ADDR (1 << 1)
92 #define NFC_INPUT (1 << 2)
93 #define NFC_OUTPUT (1 << 3)
94 #define NFC_ID (1 << 4)
95 #define NFC_STATUS (1 << 5)
97 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
98 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
100 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
101 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
102 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
104 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
106 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
108 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
109 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
110 #define NFC_V3_WRPROT_LOCK (1 << 1)
111 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
112 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
114 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
116 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
117 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
118 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
119 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
120 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
121 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
122 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
123 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
124 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
125 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
126 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
127 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
128 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
129 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
131 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
132 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
133 #define NFC_V3_CONFIG3_FW8 (1 << 3)
134 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
135 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
136 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
137 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
139 #define NFC_V3_IPC (host->regs_ip + 0x2C)
140 #define NFC_V3_IPC_CREQ (1 << 0)
141 #define NFC_V3_IPC_INT (1 << 31)
143 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
145 struct mxc_nand_host;
147 struct mxc_nand_devtype_data {
148 void (*preset)(struct mtd_info *);
149 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
150 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
151 void (*send_page)(struct mtd_info *, unsigned int);
152 void (*send_read_id)(struct mxc_nand_host *);
153 uint16_t (*get_dev_status)(struct mxc_nand_host *);
154 int (*check_int)(struct mxc_nand_host *);
155 void (*irq_control)(struct mxc_nand_host *, int);
156 u32 (*get_ecc_status)(struct mxc_nand_host *);
157 struct nand_ecclayout *ecclayout_512, *ecclayout_2k, *ecclayout_4k;
158 void (*select_chip)(struct mtd_info *mtd, int chip);
159 int (*correct_data)(struct mtd_info *mtd, u_char *dat,
160 u_char *read_ecc, u_char *calc_ecc);
163 * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
164 * (CONFIG1:INT_MSK is set). To handle this the driver uses
165 * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
167 int irqpending_quirk;
171 size_t spare0_offset;
179 struct mxc_nand_host {
181 struct nand_chip nand;
184 void __iomem *spare0;
185 void __iomem *main_area0;
189 void __iomem *regs_axi;
190 void __iomem *regs_ip;
198 struct completion op_completion;
201 unsigned int buf_start;
203 const struct mxc_nand_devtype_data *devtype_data;
204 struct mxc_nand_platform_data pdata;
207 /* OOB placement block for use with hardware ecc generation */
208 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
210 .eccpos = {6, 7, 8, 9, 10},
211 .oobfree = {{0, 5}, {12, 4}, }
214 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
216 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
217 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
218 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
221 /* OOB description for 512 byte pages with 16 byte OOB */
222 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
225 7, 8, 9, 10, 11, 12, 13, 14, 15
228 {.offset = 0, .length = 5}
232 /* OOB description for 2048 byte pages with 64 byte OOB */
233 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
236 7, 8, 9, 10, 11, 12, 13, 14, 15,
237 23, 24, 25, 26, 27, 28, 29, 30, 31,
238 39, 40, 41, 42, 43, 44, 45, 46, 47,
239 55, 56, 57, 58, 59, 60, 61, 62, 63
242 {.offset = 2, .length = 4},
243 {.offset = 16, .length = 7},
244 {.offset = 32, .length = 7},
245 {.offset = 48, .length = 7}
249 /* OOB description for 4096 byte pages with 128 byte OOB */
250 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
253 7, 8, 9, 10, 11, 12, 13, 14, 15,
254 23, 24, 25, 26, 27, 28, 29, 30, 31,
255 39, 40, 41, 42, 43, 44, 45, 46, 47,
256 55, 56, 57, 58, 59, 60, 61, 62, 63,
257 71, 72, 73, 74, 75, 76, 77, 78, 79,
258 87, 88, 89, 90, 91, 92, 93, 94, 95,
259 103, 104, 105, 106, 107, 108, 109, 110, 111,
260 119, 120, 121, 122, 123, 124, 125, 126, 127,
263 {.offset = 2, .length = 4},
264 {.offset = 16, .length = 7},
265 {.offset = 32, .length = 7},
266 {.offset = 48, .length = 7},
267 {.offset = 64, .length = 7},
268 {.offset = 80, .length = 7},
269 {.offset = 96, .length = 7},
270 {.offset = 112, .length = 7},
274 static const char *part_probes[] = { "RedBoot", "cmdlinepart", "ofpart", NULL };
276 static int check_int_v3(struct mxc_nand_host *host)
280 tmp = readl(NFC_V3_IPC);
281 if (!(tmp & NFC_V3_IPC_INT))
284 tmp &= ~NFC_V3_IPC_INT;
285 writel(tmp, NFC_V3_IPC);
290 static int check_int_v1_v2(struct mxc_nand_host *host)
294 tmp = readw(NFC_V1_V2_CONFIG2);
295 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
298 if (!host->devtype_data->irqpending_quirk)
299 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
304 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
308 tmp = readw(NFC_V1_V2_CONFIG1);
311 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
313 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
315 writew(tmp, NFC_V1_V2_CONFIG1);
318 static void irq_control_v3(struct mxc_nand_host *host, int activate)
322 tmp = readl(NFC_V3_CONFIG2);
325 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
327 tmp |= NFC_V3_CONFIG2_INT_MSK;
329 writel(tmp, NFC_V3_CONFIG2);
332 static void irq_control(struct mxc_nand_host *host, int activate)
334 if (host->devtype_data->irqpending_quirk) {
336 enable_irq(host->irq);
338 disable_irq_nosync(host->irq);
340 host->devtype_data->irq_control(host, activate);
344 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
346 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
349 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
351 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
354 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
356 return readl(NFC_V3_ECC_STATUS_RESULT);
359 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
361 struct mxc_nand_host *host = dev_id;
363 if (!host->devtype_data->check_int(host))
366 irq_control(host, 0);
368 complete(&host->op_completion);
373 /* This function polls the NANDFC to wait for the basic operation to
374 * complete by checking the INT bit of config2 register.
376 static void wait_op_done(struct mxc_nand_host *host, int useirq)
378 int max_retries = 8000;
381 if (!host->devtype_data->check_int(host)) {
382 INIT_COMPLETION(host->op_completion);
383 irq_control(host, 1);
384 wait_for_completion(&host->op_completion);
387 while (max_retries-- > 0) {
388 if (host->devtype_data->check_int(host))
394 pr_debug("%s: INT not set\n", __func__);
398 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
401 writel(cmd, NFC_V3_FLASH_CMD);
403 /* send out command */
404 writel(NFC_CMD, NFC_V3_LAUNCH);
406 /* Wait for operation to complete */
407 wait_op_done(host, useirq);
410 /* This function issues the specified command to the NAND device and
411 * waits for completion. */
412 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
414 pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
416 writew(cmd, NFC_V1_V2_FLASH_CMD);
417 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
419 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
420 int max_retries = 100;
421 /* Reset completion is indicated by NFC_CONFIG2 */
423 while (max_retries-- > 0) {
424 if (readw(NFC_V1_V2_CONFIG2) == 0) {
430 pr_debug("%s: RESET failed\n", __func__);
432 /* Wait for operation to complete */
433 wait_op_done(host, useirq);
437 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
440 writel(addr, NFC_V3_FLASH_ADDR0);
442 /* send out address */
443 writel(NFC_ADDR, NFC_V3_LAUNCH);
445 wait_op_done(host, 0);
448 /* This function sends an address (or partial address) to the
449 * NAND device. The address is used to select the source/destination for
451 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
453 pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
455 writew(addr, NFC_V1_V2_FLASH_ADDR);
456 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
458 /* Wait for operation to complete */
459 wait_op_done(host, islast);
462 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
464 struct nand_chip *nand_chip = mtd->priv;
465 struct mxc_nand_host *host = nand_chip->priv;
468 tmp = readl(NFC_V3_CONFIG1);
470 writel(tmp, NFC_V3_CONFIG1);
472 /* transfer data from NFC ram to nand */
473 writel(ops, NFC_V3_LAUNCH);
475 wait_op_done(host, false);
478 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
480 struct nand_chip *nand_chip = mtd->priv;
481 struct mxc_nand_host *host = nand_chip->priv;
483 /* NANDFC buffer 0 is used for page read/write */
484 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
486 writew(ops, NFC_V1_V2_CONFIG2);
488 /* Wait for operation to complete */
489 wait_op_done(host, true);
492 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
494 struct nand_chip *nand_chip = mtd->priv;
495 struct mxc_nand_host *host = nand_chip->priv;
498 if (mtd->writesize > 512)
503 for (i = 0; i < bufs; i++) {
505 /* NANDFC buffer 0 is used for page read/write */
506 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
508 writew(ops, NFC_V1_V2_CONFIG2);
510 /* Wait for operation to complete */
511 wait_op_done(host, true);
515 static void send_read_id_v3(struct mxc_nand_host *host)
517 /* Read ID into main buffer */
518 writel(NFC_ID, NFC_V3_LAUNCH);
520 wait_op_done(host, true);
522 memcpy_fromio(host->data_buf, host->main_area0, 16);
525 /* Request the NANDFC to perform a read of the NAND device ID. */
526 static void send_read_id_v1_v2(struct mxc_nand_host *host)
528 struct nand_chip *this = &host->nand;
530 /* NANDFC buffer 0 is used for device ID output */
531 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
533 writew(NFC_ID, NFC_V1_V2_CONFIG2);
535 /* Wait for operation to complete */
536 wait_op_done(host, true);
538 memcpy_fromio(host->data_buf, host->main_area0, 16);
540 if (this->options & NAND_BUSWIDTH_16) {
541 /* compress the ID info */
542 host->data_buf[1] = host->data_buf[2];
543 host->data_buf[2] = host->data_buf[4];
544 host->data_buf[3] = host->data_buf[6];
545 host->data_buf[4] = host->data_buf[8];
546 host->data_buf[5] = host->data_buf[10];
550 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
552 writew(NFC_STATUS, NFC_V3_LAUNCH);
553 wait_op_done(host, true);
555 return readl(NFC_V3_CONFIG1) >> 16;
558 /* This function requests the NANDFC to perform a read of the
559 * NAND device status and returns the current status. */
560 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
562 void __iomem *main_buf = host->main_area0;
566 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
569 * The device status is stored in main_area0. To
570 * prevent corruption of the buffer save the value
571 * and restore it afterwards.
573 store = readl(main_buf);
575 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
576 wait_op_done(host, true);
578 ret = readw(main_buf);
580 writel(store, main_buf);
585 /* This functions is used by upper layer to checks if device is ready */
586 static int mxc_nand_dev_ready(struct mtd_info *mtd)
589 * NFC handles R/B internally. Therefore, this function
590 * always returns status as ready.
595 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
598 * If HW ECC is enabled, we turn it on during init. There is
599 * no need to enable again here.
603 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
604 u_char *read_ecc, u_char *calc_ecc)
606 struct nand_chip *nand_chip = mtd->priv;
607 struct mxc_nand_host *host = nand_chip->priv;
610 * 1-Bit errors are automatically corrected in HW. No need for
611 * additional correction. 2-Bit errors cannot be corrected by
612 * HW ECC, so we need to return failure
614 uint16_t ecc_status = get_ecc_status_v1(host);
616 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
617 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
624 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
625 u_char *read_ecc, u_char *calc_ecc)
627 struct nand_chip *nand_chip = mtd->priv;
628 struct mxc_nand_host *host = nand_chip->priv;
632 u8 ecc_bit_mask, err_limit;
634 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
635 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
637 no_subpages = mtd->writesize >> 9;
639 ecc_stat = host->devtype_data->get_ecc_status(host);
642 err = ecc_stat & ecc_bit_mask;
643 if (err > err_limit) {
644 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
650 } while (--no_subpages);
652 mtd->ecc_stats.corrected += ret;
653 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
658 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
664 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
666 struct nand_chip *nand_chip = mtd->priv;
667 struct mxc_nand_host *host = nand_chip->priv;
670 /* Check for status request */
671 if (host->status_request)
672 return host->devtype_data->get_dev_status(host) & 0xFF;
674 ret = *(uint8_t *)(host->data_buf + host->buf_start);
680 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
682 struct nand_chip *nand_chip = mtd->priv;
683 struct mxc_nand_host *host = nand_chip->priv;
686 ret = *(uint16_t *)(host->data_buf + host->buf_start);
687 host->buf_start += 2;
692 /* Write data of length len to buffer buf. The data to be
693 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
694 * Operation by the NFC, the data is written to NAND Flash */
695 static void mxc_nand_write_buf(struct mtd_info *mtd,
696 const u_char *buf, int len)
698 struct nand_chip *nand_chip = mtd->priv;
699 struct mxc_nand_host *host = nand_chip->priv;
700 u16 col = host->buf_start;
701 int n = mtd->oobsize + mtd->writesize - col;
705 memcpy(host->data_buf + col, buf, n);
707 host->buf_start += n;
710 /* Read the data buffer from the NAND Flash. To read the data from NAND
711 * Flash first the data output cycle is initiated by the NFC, which copies
712 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
714 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
716 struct nand_chip *nand_chip = mtd->priv;
717 struct mxc_nand_host *host = nand_chip->priv;
718 u16 col = host->buf_start;
719 int n = mtd->oobsize + mtd->writesize - col;
723 memcpy(buf, host->data_buf + col, n);
725 host->buf_start += n;
728 /* Used by the upper layer to verify the data in NAND Flash
729 * with the data in the buf. */
730 static int mxc_nand_verify_buf(struct mtd_info *mtd,
731 const u_char *buf, int len)
736 /* This function is used by upper layer for select and
737 * deselect of the NAND chip */
738 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
740 struct nand_chip *nand_chip = mtd->priv;
741 struct mxc_nand_host *host = nand_chip->priv;
744 /* Disable the NFC clock */
746 clk_disable_unprepare(host->clk);
752 if (!host->clk_act) {
753 /* Enable the NFC clock */
754 clk_prepare_enable(host->clk);
759 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
761 struct nand_chip *nand_chip = mtd->priv;
762 struct mxc_nand_host *host = nand_chip->priv;
765 /* Disable the NFC clock */
767 clk_disable(host->clk);
773 if (!host->clk_act) {
774 /* Enable the NFC clock */
775 clk_enable(host->clk);
779 host->active_cs = chip;
780 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
784 * Function to transfer data to/from spare area.
786 static void copy_spare(struct mtd_info *mtd, bool bfrom)
788 struct nand_chip *this = mtd->priv;
789 struct mxc_nand_host *host = this->priv;
791 u16 n = mtd->writesize >> 9;
792 u8 *d = host->data_buf + mtd->writesize;
793 u8 __iomem *s = host->spare0;
794 u16 t = host->devtype_data->spare_len;
796 j = (mtd->oobsize / n >> 1) << 1;
799 for (i = 0; i < n - 1; i++)
800 memcpy_fromio(d + i * j, s + i * t, j);
802 /* the last section */
803 memcpy_fromio(d + i * j, s + i * t, mtd->oobsize - i * j);
805 for (i = 0; i < n - 1; i++)
806 memcpy_toio(&s[i * t], &d[i * j], j);
808 /* the last section */
809 memcpy_toio(&s[i * t], &d[i * j], mtd->oobsize - i * j);
813 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
815 struct nand_chip *nand_chip = mtd->priv;
816 struct mxc_nand_host *host = nand_chip->priv;
818 /* Write out column address, if necessary */
821 * MXC NANDFC can only perform full page+spare or
822 * spare-only read/write. When the upper layers
823 * perform a read/write buf operation, the saved column
824 * address is used to index into the full page.
826 host->devtype_data->send_addr(host, 0, page_addr == -1);
827 if (mtd->writesize > 512)
828 /* another col addr cycle for 2k page */
829 host->devtype_data->send_addr(host, 0, false);
832 /* Write out page address, if necessary */
833 if (page_addr != -1) {
834 /* paddr_0 - p_addr_7 */
835 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
837 if (mtd->writesize > 512) {
838 if (mtd->size >= 0x10000000) {
839 /* paddr_8 - paddr_15 */
840 host->devtype_data->send_addr(host,
841 (page_addr >> 8) & 0xff,
843 host->devtype_data->send_addr(host,
844 (page_addr >> 16) & 0xff,
847 /* paddr_8 - paddr_15 */
848 host->devtype_data->send_addr(host,
849 (page_addr >> 8) & 0xff, true);
851 /* One more address cycle for higher density devices */
852 if (mtd->size >= 0x4000000) {
853 /* paddr_8 - paddr_15 */
854 host->devtype_data->send_addr(host,
855 (page_addr >> 8) & 0xff,
857 host->devtype_data->send_addr(host,
858 (page_addr >> 16) & 0xff,
861 /* paddr_8 - paddr_15 */
862 host->devtype_data->send_addr(host,
863 (page_addr >> 8) & 0xff, true);
869 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
870 * on how much oob the nand chip has. For 8bit ecc we need at least
871 * 26 bytes of oob data per 512 byte block.
873 static int get_eccsize(struct mtd_info *mtd)
875 int oobbytes_per_512 = 0;
877 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
879 if (oobbytes_per_512 < 26)
885 static void preset_v1(struct mtd_info *mtd)
887 struct nand_chip *nand_chip = mtd->priv;
888 struct mxc_nand_host *host = nand_chip->priv;
889 uint16_t config1 = 0;
891 if (nand_chip->ecc.mode == NAND_ECC_HW)
892 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
894 if (!host->devtype_data->irqpending_quirk)
895 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
899 writew(config1, NFC_V1_V2_CONFIG1);
900 /* preset operation */
902 /* Unlock the internal RAM Buffer */
903 writew(0x2, NFC_V1_V2_CONFIG);
905 /* Blocks to be unlocked */
906 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
907 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
909 /* Unlock Block Command for given address range */
910 writew(0x4, NFC_V1_V2_WRPROT);
913 static void preset_v2(struct mtd_info *mtd)
915 struct nand_chip *nand_chip = mtd->priv;
916 struct mxc_nand_host *host = nand_chip->priv;
917 uint16_t config1 = 0;
919 if (nand_chip->ecc.mode == NAND_ECC_HW)
920 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
922 config1 |= NFC_V2_CONFIG1_FP_INT;
924 if (!host->devtype_data->irqpending_quirk)
925 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
927 if (mtd->writesize) {
928 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
930 host->eccsize = get_eccsize(mtd);
931 if (host->eccsize == 4)
932 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
934 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
939 writew(config1, NFC_V1_V2_CONFIG1);
940 /* preset operation */
942 /* Unlock the internal RAM Buffer */
943 writew(0x2, NFC_V1_V2_CONFIG);
945 /* Blocks to be unlocked */
946 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
947 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
948 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
949 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
950 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
951 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
952 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
953 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
955 /* Unlock Block Command for given address range */
956 writew(0x4, NFC_V1_V2_WRPROT);
959 static void preset_v3(struct mtd_info *mtd)
961 struct nand_chip *chip = mtd->priv;
962 struct mxc_nand_host *host = chip->priv;
963 uint32_t config2, config3;
966 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
967 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
969 /* Unlock the internal RAM Buffer */
970 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
973 /* Blocks to be unlocked */
974 for (i = 0; i < NAND_MAX_CHIPS; i++)
975 writel(0x0 | (0xffff << 16),
976 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
978 writel(0, NFC_V3_IPC);
980 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
981 NFC_V3_CONFIG2_2CMD_PHASES |
982 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
983 NFC_V3_CONFIG2_ST_CMD(0x70) |
984 NFC_V3_CONFIG2_INT_MSK |
985 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
987 if (chip->ecc.mode == NAND_ECC_HW)
988 config2 |= NFC_V3_CONFIG2_ECC_EN;
990 addr_phases = fls(chip->pagemask) >> 3;
992 if (mtd->writesize == 2048) {
993 config2 |= NFC_V3_CONFIG2_PS_2048;
994 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
995 } else if (mtd->writesize == 4096) {
996 config2 |= NFC_V3_CONFIG2_PS_4096;
997 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
999 config2 |= NFC_V3_CONFIG2_PS_512;
1000 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1003 if (mtd->writesize) {
1004 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
1005 host->eccsize = get_eccsize(mtd);
1006 if (host->eccsize == 8)
1007 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1010 writel(config2, NFC_V3_CONFIG2);
1012 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1013 NFC_V3_CONFIG3_NO_SDMA |
1014 NFC_V3_CONFIG3_RBB_MODE |
1015 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1016 NFC_V3_CONFIG3_ADD_OP(0);
1018 if (!(chip->options & NAND_BUSWIDTH_16))
1019 config3 |= NFC_V3_CONFIG3_FW8;
1021 writel(config3, NFC_V3_CONFIG3);
1023 writel(0, NFC_V3_DELAY_LINE);
1026 /* Used by the upper layer to write command to NAND Flash for
1027 * different operations to be carried out on NAND Flash */
1028 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1029 int column, int page_addr)
1031 struct nand_chip *nand_chip = mtd->priv;
1032 struct mxc_nand_host *host = nand_chip->priv;
1034 pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1035 command, column, page_addr);
1037 /* Reset command state information */
1038 host->status_request = false;
1040 /* Command pre-processing step */
1042 case NAND_CMD_RESET:
1043 host->devtype_data->preset(mtd);
1044 host->devtype_data->send_cmd(host, command, false);
1047 case NAND_CMD_STATUS:
1048 host->buf_start = 0;
1049 host->status_request = true;
1051 host->devtype_data->send_cmd(host, command, true);
1052 mxc_do_addr_cycle(mtd, column, page_addr);
1055 case NAND_CMD_READ0:
1056 case NAND_CMD_READOOB:
1057 if (command == NAND_CMD_READ0)
1058 host->buf_start = column;
1060 host->buf_start = column + mtd->writesize;
1062 command = NAND_CMD_READ0; /* only READ0 is valid */
1064 host->devtype_data->send_cmd(host, command, false);
1065 mxc_do_addr_cycle(mtd, column, page_addr);
1067 if (mtd->writesize > 512)
1068 host->devtype_data->send_cmd(host,
1069 NAND_CMD_READSTART, true);
1071 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1073 memcpy_fromio(host->data_buf, host->main_area0, mtd->writesize);
1074 copy_spare(mtd, true);
1077 case NAND_CMD_SEQIN:
1078 if (column >= mtd->writesize)
1079 /* call ourself to read a page */
1080 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1082 host->buf_start = column;
1084 host->devtype_data->send_cmd(host, command, false);
1085 mxc_do_addr_cycle(mtd, column, page_addr);
1088 case NAND_CMD_PAGEPROG:
1089 memcpy_toio(host->main_area0, host->data_buf, mtd->writesize);
1090 copy_spare(mtd, false);
1091 host->devtype_data->send_page(mtd, NFC_INPUT);
1092 host->devtype_data->send_cmd(host, command, true);
1093 mxc_do_addr_cycle(mtd, column, page_addr);
1096 case NAND_CMD_READID:
1097 host->devtype_data->send_cmd(host, command, true);
1098 mxc_do_addr_cycle(mtd, column, page_addr);
1099 host->devtype_data->send_read_id(host);
1100 host->buf_start = column;
1103 case NAND_CMD_ERASE1:
1104 case NAND_CMD_ERASE2:
1105 host->devtype_data->send_cmd(host, command, false);
1106 mxc_do_addr_cycle(mtd, column, page_addr);
1113 * The generic flash bbt decriptors overlap with our ecc
1114 * hardware, so define some i.MX specific ones.
1116 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1117 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1119 static struct nand_bbt_descr bbt_main_descr = {
1120 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1121 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1126 .pattern = bbt_pattern,
1129 static struct nand_bbt_descr bbt_mirror_descr = {
1130 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1131 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1136 .pattern = mirror_pattern,
1139 /* v1 + irqpending_quirk: i.MX21 */
1140 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1141 .preset = preset_v1,
1142 .send_cmd = send_cmd_v1_v2,
1143 .send_addr = send_addr_v1_v2,
1144 .send_page = send_page_v1,
1145 .send_read_id = send_read_id_v1_v2,
1146 .get_dev_status = get_dev_status_v1_v2,
1147 .check_int = check_int_v1_v2,
1148 .irq_control = irq_control_v1_v2,
1149 .get_ecc_status = get_ecc_status_v1,
1150 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1151 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1152 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1153 .select_chip = mxc_nand_select_chip_v1_v3,
1154 .correct_data = mxc_nand_correct_data_v1,
1155 .irqpending_quirk = 1,
1157 .regs_offset = 0xe00,
1158 .spare0_offset = 0x800,
1164 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1165 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1166 .preset = preset_v1,
1167 .send_cmd = send_cmd_v1_v2,
1168 .send_addr = send_addr_v1_v2,
1169 .send_page = send_page_v1,
1170 .send_read_id = send_read_id_v1_v2,
1171 .get_dev_status = get_dev_status_v1_v2,
1172 .check_int = check_int_v1_v2,
1173 .irq_control = irq_control_v1_v2,
1174 .get_ecc_status = get_ecc_status_v1,
1175 .ecclayout_512 = &nandv1_hw_eccoob_smallpage,
1176 .ecclayout_2k = &nandv1_hw_eccoob_largepage,
1177 .ecclayout_4k = &nandv1_hw_eccoob_smallpage, /* XXX: needs fix */
1178 .select_chip = mxc_nand_select_chip_v1_v3,
1179 .correct_data = mxc_nand_correct_data_v1,
1180 .irqpending_quirk = 0,
1182 .regs_offset = 0xe00,
1183 .spare0_offset = 0x800,
1190 /* v21: i.MX25, i.MX35 */
1191 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1192 .preset = preset_v2,
1193 .send_cmd = send_cmd_v1_v2,
1194 .send_addr = send_addr_v1_v2,
1195 .send_page = send_page_v2,
1196 .send_read_id = send_read_id_v1_v2,
1197 .get_dev_status = get_dev_status_v1_v2,
1198 .check_int = check_int_v1_v2,
1199 .irq_control = irq_control_v1_v2,
1200 .get_ecc_status = get_ecc_status_v2,
1201 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1202 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1203 .ecclayout_4k = &nandv2_hw_eccoob_4k,
1204 .select_chip = mxc_nand_select_chip_v2,
1205 .correct_data = mxc_nand_correct_data_v2_v3,
1206 .irqpending_quirk = 0,
1208 .regs_offset = 0x1e00,
1209 .spare0_offset = 0x1000,
1216 /* v3: i.MX51, i.MX53 */
1217 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1218 .preset = preset_v3,
1219 .send_cmd = send_cmd_v3,
1220 .send_addr = send_addr_v3,
1221 .send_page = send_page_v3,
1222 .send_read_id = send_read_id_v3,
1223 .get_dev_status = get_dev_status_v3,
1224 .check_int = check_int_v3,
1225 .irq_control = irq_control_v3,
1226 .get_ecc_status = get_ecc_status_v3,
1227 .ecclayout_512 = &nandv2_hw_eccoob_smallpage,
1228 .ecclayout_2k = &nandv2_hw_eccoob_largepage,
1229 .ecclayout_4k = &nandv2_hw_eccoob_smallpage, /* XXX: needs fix */
1230 .select_chip = mxc_nand_select_chip_v1_v3,
1231 .correct_data = mxc_nand_correct_data_v2_v3,
1232 .irqpending_quirk = 0,
1235 .spare0_offset = 0x1000,
1236 .axi_offset = 0x1e00,
1242 #ifdef CONFIG_OF_MTD
1243 static const struct of_device_id mxcnd_dt_ids[] = {
1245 .compatible = "fsl,imx21-nand",
1246 .data = &imx21_nand_devtype_data,
1248 .compatible = "fsl,imx27-nand",
1249 .data = &imx27_nand_devtype_data,
1251 .compatible = "fsl,imx25-nand",
1252 .data = &imx25_nand_devtype_data,
1254 .compatible = "fsl,imx51-nand",
1255 .data = &imx51_nand_devtype_data,
1260 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1262 struct device_node *np = host->dev->of_node;
1263 struct mxc_nand_platform_data *pdata = &host->pdata;
1264 const struct of_device_id *of_id =
1265 of_match_device(mxcnd_dt_ids, host->dev);
1271 if (of_get_nand_ecc_mode(np) >= 0)
1274 pdata->flash_bbt = of_get_nand_on_flash_bbt(np);
1276 buswidth = of_get_nand_bus_width(np);
1280 pdata->width = buswidth / 8;
1282 host->devtype_data = of_id->data;
1287 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1293 static int __init mxcnd_probe_pdata(struct mxc_nand_host *host)
1295 struct mxc_nand_platform_data *pdata = host->dev->platform_data;
1300 host->pdata = *pdata;
1304 host->devtype_data = &imx21_nand_devtype_data;
1306 host->devtype_data = &imx27_nand_devtype_data;
1307 } else if (nfc_is_v21()) {
1308 host->devtype_data = &imx25_nand_devtype_data;
1309 } else if (nfc_is_v3_2()) {
1310 host->devtype_data = &imx51_nand_devtype_data;
1317 static int __init mxcnd_probe(struct platform_device *pdev)
1319 struct nand_chip *this;
1320 struct mtd_info *mtd;
1321 struct mxc_nand_host *host;
1322 struct resource *res;
1325 /* Allocate memory for MTD device structure and private data */
1326 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1327 NAND_MAX_OOBSIZE, GFP_KERNEL);
1331 host->data_buf = (uint8_t *)(host + 1);
1333 host->dev = &pdev->dev;
1334 /* structures must be linked */
1338 mtd->owner = THIS_MODULE;
1339 mtd->dev.parent = &pdev->dev;
1340 mtd->name = DRIVER_NAME;
1342 /* 50 us command delay time */
1343 this->chip_delay = 5;
1346 this->dev_ready = mxc_nand_dev_ready;
1347 this->cmdfunc = mxc_nand_command;
1348 this->read_byte = mxc_nand_read_byte;
1349 this->read_word = mxc_nand_read_word;
1350 this->write_buf = mxc_nand_write_buf;
1351 this->read_buf = mxc_nand_read_buf;
1352 this->verify_buf = mxc_nand_verify_buf;
1354 host->clk = clk_get(&pdev->dev, "nfc");
1355 if (IS_ERR(host->clk)) {
1356 err = PTR_ERR(host->clk);
1360 clk_prepare_enable(host->clk);
1363 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1369 host->base = ioremap(res->start, resource_size(res));
1375 host->main_area0 = host->base;
1377 err = mxcnd_probe_dt(host);
1379 err = mxcnd_probe_pdata(host);
1383 if (host->devtype_data->regs_offset)
1384 host->regs = host->base + host->devtype_data->regs_offset;
1385 host->spare0 = host->base + host->devtype_data->spare0_offset;
1386 if (host->devtype_data->axi_offset)
1387 host->regs_axi = host->base + host->devtype_data->axi_offset;
1389 this->ecc.bytes = host->devtype_data->eccbytes;
1390 host->eccsize = host->devtype_data->eccsize;
1392 this->select_chip = host->devtype_data->select_chip;
1393 this->ecc.size = 512;
1394 this->ecc.layout = host->devtype_data->ecclayout_512;
1396 if (host->devtype_data->needs_ip) {
1397 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1402 host->regs_ip = ioremap(res->start, resource_size(res));
1403 if (!host->regs_ip) {
1409 if (host->pdata.hw_ecc) {
1410 this->ecc.calculate = mxc_nand_calculate_ecc;
1411 this->ecc.hwctl = mxc_nand_enable_hwecc;
1412 this->ecc.correct = host->devtype_data->correct_data;
1413 this->ecc.mode = NAND_ECC_HW;
1415 this->ecc.mode = NAND_ECC_SOFT;
1418 /* NAND bus width determines access functions used by upper layer */
1419 if (host->pdata.width == 2)
1420 this->options |= NAND_BUSWIDTH_16;
1422 if (host->pdata.flash_bbt) {
1423 this->bbt_td = &bbt_main_descr;
1424 this->bbt_md = &bbt_mirror_descr;
1425 /* update flash based bbt */
1426 this->bbt_options |= NAND_BBT_USE_FLASH;
1429 init_completion(&host->op_completion);
1431 host->irq = platform_get_irq(pdev, 0);
1434 * Use host->devtype_data->irq_control() here instead of irq_control()
1435 * because we must not disable_irq_nosync without having requested the
1438 host->devtype_data->irq_control(host, 0);
1440 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1445 * Now that we "own" the interrupt make sure the interrupt mask bit is
1446 * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1449 if (host->devtype_data->irqpending_quirk) {
1450 disable_irq_nosync(host->irq);
1451 host->devtype_data->irq_control(host, 1);
1454 /* first scan to find the device and get the page size */
1455 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1460 /* Call preset again, with correct writesize this time */
1461 host->devtype_data->preset(mtd);
1463 if (mtd->writesize == 2048)
1464 this->ecc.layout = host->devtype_data->ecclayout_2k;
1465 else if (mtd->writesize == 4096)
1466 this->ecc.layout = host->devtype_data->ecclayout_4k;
1468 if (this->ecc.mode == NAND_ECC_HW) {
1470 this->ecc.strength = 1;
1472 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1475 /* second phase scan */
1476 if (nand_scan_tail(mtd)) {
1481 /* Register the partitions */
1482 mtd_device_parse_register(mtd, part_probes,
1483 &(struct mtd_part_parser_data){
1484 .of_node = pdev->dev.of_node,
1487 host->pdata.nr_parts);
1489 platform_set_drvdata(pdev, host);
1494 free_irq(host->irq, host);
1497 iounmap(host->regs_ip);
1498 iounmap(host->base);
1507 static int __devexit mxcnd_remove(struct platform_device *pdev)
1509 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1513 platform_set_drvdata(pdev, NULL);
1515 nand_release(&host->mtd);
1516 free_irq(host->irq, host);
1518 iounmap(host->regs_ip);
1519 iounmap(host->base);
1525 static struct platform_driver mxcnd_driver = {
1527 .name = DRIVER_NAME,
1528 .owner = THIS_MODULE,
1529 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1531 .remove = __devexit_p(mxcnd_remove),
1534 static int __init mxc_nd_init(void)
1536 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1539 static void __exit mxc_nd_cleanup(void)
1541 /* Unregister the device structure */
1542 platform_driver_unregister(&mxcnd_driver);
1545 module_init(mxc_nd_init);
1546 module_exit(mxc_nd_cleanup);
1548 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1549 MODULE_DESCRIPTION("MXC NAND MTD driver");
1550 MODULE_LICENSE("GPL");