2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
36 #include <asm/mach/flash.h>
37 #include <mach/mxc_nand.h>
38 #include <mach/hardware.h>
40 #define DRIVER_NAME "mxc_nand"
42 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
43 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
44 #define nfc_is_v3_2() cpu_is_mx51()
45 #define nfc_is_v3() nfc_is_v3_2()
47 /* Addresses for NFC registers */
48 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
57 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
60 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
61 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
62 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
63 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
64 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
65 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
66 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
67 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
68 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
69 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
71 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
72 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
73 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
74 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
75 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
76 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
77 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
78 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
79 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
80 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
82 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
85 * Operation modes for the NFC. Valid for v1, v2 and v3
88 #define NFC_CMD (1 << 0)
89 #define NFC_ADDR (1 << 1)
90 #define NFC_INPUT (1 << 2)
91 #define NFC_OUTPUT (1 << 3)
92 #define NFC_ID (1 << 4)
93 #define NFC_STATUS (1 << 5)
95 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
96 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
98 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
99 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
100 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
102 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
104 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
106 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
107 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
108 #define NFC_V3_WRPROT_LOCK (1 << 1)
109 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
110 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
112 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
114 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
115 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
116 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
117 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
118 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
119 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
120 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
122 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
123 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
124 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
125 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
126 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
127 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
129 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
130 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
131 #define NFC_V3_CONFIG3_FW8 (1 << 3)
132 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
133 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
134 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
135 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
137 #define NFC_V3_IPC (host->regs_ip + 0x2C)
138 #define NFC_V3_IPC_CREQ (1 << 0)
139 #define NFC_V3_IPC_INT (1 << 31)
141 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
143 struct mxc_nand_host {
145 struct nand_chip nand;
153 void __iomem *regs_axi;
154 void __iomem *regs_ip;
162 struct completion op_completion;
165 unsigned int buf_start;
168 void (*preset)(struct mtd_info *);
169 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
170 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
171 void (*send_page)(struct mtd_info *, unsigned int);
172 void (*send_read_id)(struct mxc_nand_host *);
173 uint16_t (*get_dev_status)(struct mxc_nand_host *);
174 int (*check_int)(struct mxc_nand_host *);
175 void (*irq_control)(struct mxc_nand_host *, int);
178 /* OOB placement block for use with hardware ecc generation */
179 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
181 .eccpos = {6, 7, 8, 9, 10},
182 .oobfree = {{0, 5}, {12, 4}, }
185 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
187 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
188 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
189 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
192 /* OOB description for 512 byte pages with 16 byte OOB */
193 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
196 7, 8, 9, 10, 11, 12, 13, 14, 15
199 {.offset = 0, .length = 5}
203 /* OOB description for 2048 byte pages with 64 byte OOB */
204 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
207 7, 8, 9, 10, 11, 12, 13, 14, 15,
208 23, 24, 25, 26, 27, 28, 29, 30, 31,
209 39, 40, 41, 42, 43, 44, 45, 46, 47,
210 55, 56, 57, 58, 59, 60, 61, 62, 63
213 {.offset = 2, .length = 4},
214 {.offset = 16, .length = 7},
215 {.offset = 32, .length = 7},
216 {.offset = 48, .length = 7}
220 /* OOB description for 4096 byte pages with 128 byte OOB */
221 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
224 7, 8, 9, 10, 11, 12, 13, 14, 15,
225 23, 24, 25, 26, 27, 28, 29, 30, 31,
226 39, 40, 41, 42, 43, 44, 45, 46, 47,
227 55, 56, 57, 58, 59, 60, 61, 62, 63,
228 71, 72, 73, 74, 75, 76, 77, 78, 79,
229 87, 88, 89, 90, 91, 92, 93, 94, 95,
230 103, 104, 105, 106, 107, 108, 109, 110, 111,
231 119, 120, 121, 122, 123, 124, 125, 126, 127,
234 {.offset = 2, .length = 4},
235 {.offset = 16, .length = 7},
236 {.offset = 32, .length = 7},
237 {.offset = 48, .length = 7},
238 {.offset = 64, .length = 7},
239 {.offset = 80, .length = 7},
240 {.offset = 96, .length = 7},
241 {.offset = 112, .length = 7},
245 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
247 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
249 struct mxc_nand_host *host = dev_id;
251 if (!host->check_int(host))
254 host->irq_control(host, 0);
256 complete(&host->op_completion);
261 static int check_int_v3(struct mxc_nand_host *host)
265 tmp = readl(NFC_V3_IPC);
266 if (!(tmp & NFC_V3_IPC_INT))
269 tmp &= ~NFC_V3_IPC_INT;
270 writel(tmp, NFC_V3_IPC);
275 static int check_int_v1_v2(struct mxc_nand_host *host)
279 tmp = readw(NFC_V1_V2_CONFIG2);
280 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
284 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
290 * It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
291 * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
292 * driver can enable/disable the irq line rather than simply masking the
295 static void irq_control_mx21(struct mxc_nand_host *host, int activate)
298 enable_irq(host->irq);
300 disable_irq_nosync(host->irq);
303 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
307 tmp = readw(NFC_V1_V2_CONFIG1);
310 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
312 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
314 writew(tmp, NFC_V1_V2_CONFIG1);
317 static void irq_control_v3(struct mxc_nand_host *host, int activate)
321 tmp = readl(NFC_V3_CONFIG2);
324 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
326 tmp |= NFC_V3_CONFIG2_INT_MSK;
328 writel(tmp, NFC_V3_CONFIG2);
331 /* This function polls the NANDFC to wait for the basic operation to
332 * complete by checking the INT bit of config2 register.
334 static void wait_op_done(struct mxc_nand_host *host, int useirq)
336 int max_retries = 8000;
339 if (!host->check_int(host)) {
340 INIT_COMPLETION(host->op_completion);
341 host->irq_control(host, 1);
342 wait_for_completion(&host->op_completion);
345 while (max_retries-- > 0) {
346 if (host->check_int(host))
352 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
357 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
360 writel(cmd, NFC_V3_FLASH_CMD);
362 /* send out command */
363 writel(NFC_CMD, NFC_V3_LAUNCH);
365 /* Wait for operation to complete */
366 wait_op_done(host, useirq);
369 /* This function issues the specified command to the NAND device and
370 * waits for completion. */
371 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
373 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
375 writew(cmd, NFC_V1_V2_FLASH_CMD);
376 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
378 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
379 int max_retries = 100;
380 /* Reset completion is indicated by NFC_CONFIG2 */
382 while (max_retries-- > 0) {
383 if (readw(NFC_V1_V2_CONFIG2) == 0) {
389 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
392 /* Wait for operation to complete */
393 wait_op_done(host, useirq);
397 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
400 writel(addr, NFC_V3_FLASH_ADDR0);
402 /* send out address */
403 writel(NFC_ADDR, NFC_V3_LAUNCH);
405 wait_op_done(host, 0);
408 /* This function sends an address (or partial address) to the
409 * NAND device. The address is used to select the source/destination for
411 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
413 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
415 writew(addr, NFC_V1_V2_FLASH_ADDR);
416 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
418 /* Wait for operation to complete */
419 wait_op_done(host, islast);
422 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
424 struct nand_chip *nand_chip = mtd->priv;
425 struct mxc_nand_host *host = nand_chip->priv;
428 tmp = readl(NFC_V3_CONFIG1);
430 writel(tmp, NFC_V3_CONFIG1);
432 /* transfer data from NFC ram to nand */
433 writel(ops, NFC_V3_LAUNCH);
435 wait_op_done(host, false);
438 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
440 struct nand_chip *nand_chip = mtd->priv;
441 struct mxc_nand_host *host = nand_chip->priv;
444 if (nfc_is_v1() && mtd->writesize > 512)
449 for (i = 0; i < bufs; i++) {
451 /* NANDFC buffer 0 is used for page read/write */
452 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
454 writew(ops, NFC_V1_V2_CONFIG2);
456 /* Wait for operation to complete */
457 wait_op_done(host, true);
461 static void send_read_id_v3(struct mxc_nand_host *host)
463 /* Read ID into main buffer */
464 writel(NFC_ID, NFC_V3_LAUNCH);
466 wait_op_done(host, true);
468 memcpy(host->data_buf, host->main_area0, 16);
471 /* Request the NANDFC to perform a read of the NAND device ID. */
472 static void send_read_id_v1_v2(struct mxc_nand_host *host)
474 struct nand_chip *this = &host->nand;
476 /* NANDFC buffer 0 is used for device ID output */
477 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
479 writew(NFC_ID, NFC_V1_V2_CONFIG2);
481 /* Wait for operation to complete */
482 wait_op_done(host, true);
484 memcpy(host->data_buf, host->main_area0, 16);
486 if (this->options & NAND_BUSWIDTH_16) {
487 /* compress the ID info */
488 host->data_buf[1] = host->data_buf[2];
489 host->data_buf[2] = host->data_buf[4];
490 host->data_buf[3] = host->data_buf[6];
491 host->data_buf[4] = host->data_buf[8];
492 host->data_buf[5] = host->data_buf[10];
496 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
498 writew(NFC_STATUS, NFC_V3_LAUNCH);
499 wait_op_done(host, true);
501 return readl(NFC_V3_CONFIG1) >> 16;
504 /* This function requests the NANDFC to perform a read of the
505 * NAND device status and returns the current status. */
506 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
508 void __iomem *main_buf = host->main_area0;
512 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
515 * The device status is stored in main_area0. To
516 * prevent corruption of the buffer save the value
517 * and restore it afterwards.
519 store = readl(main_buf);
521 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
522 wait_op_done(host, true);
524 ret = readw(main_buf);
526 writel(store, main_buf);
531 /* This functions is used by upper layer to checks if device is ready */
532 static int mxc_nand_dev_ready(struct mtd_info *mtd)
535 * NFC handles R/B internally. Therefore, this function
536 * always returns status as ready.
541 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
544 * If HW ECC is enabled, we turn it on during init. There is
545 * no need to enable again here.
549 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
550 u_char *read_ecc, u_char *calc_ecc)
552 struct nand_chip *nand_chip = mtd->priv;
553 struct mxc_nand_host *host = nand_chip->priv;
556 * 1-Bit errors are automatically corrected in HW. No need for
557 * additional correction. 2-Bit errors cannot be corrected by
558 * HW ECC, so we need to return failure
560 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
562 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
563 DEBUG(MTD_DEBUG_LEVEL0,
564 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
571 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
572 u_char *read_ecc, u_char *calc_ecc)
574 struct nand_chip *nand_chip = mtd->priv;
575 struct mxc_nand_host *host = nand_chip->priv;
579 u8 ecc_bit_mask, err_limit;
581 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
582 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
584 no_subpages = mtd->writesize >> 9;
587 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
589 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
592 err = ecc_stat & ecc_bit_mask;
593 if (err > err_limit) {
594 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
600 } while (--no_subpages);
602 mtd->ecc_stats.corrected += ret;
603 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
608 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
614 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
616 struct nand_chip *nand_chip = mtd->priv;
617 struct mxc_nand_host *host = nand_chip->priv;
620 /* Check for status request */
621 if (host->status_request)
622 return host->get_dev_status(host) & 0xFF;
624 ret = *(uint8_t *)(host->data_buf + host->buf_start);
630 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
632 struct nand_chip *nand_chip = mtd->priv;
633 struct mxc_nand_host *host = nand_chip->priv;
636 ret = *(uint16_t *)(host->data_buf + host->buf_start);
637 host->buf_start += 2;
642 /* Write data of length len to buffer buf. The data to be
643 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
644 * Operation by the NFC, the data is written to NAND Flash */
645 static void mxc_nand_write_buf(struct mtd_info *mtd,
646 const u_char *buf, int len)
648 struct nand_chip *nand_chip = mtd->priv;
649 struct mxc_nand_host *host = nand_chip->priv;
650 u16 col = host->buf_start;
651 int n = mtd->oobsize + mtd->writesize - col;
655 memcpy(host->data_buf + col, buf, n);
657 host->buf_start += n;
660 /* Read the data buffer from the NAND Flash. To read the data from NAND
661 * Flash first the data output cycle is initiated by the NFC, which copies
662 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
664 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
666 struct nand_chip *nand_chip = mtd->priv;
667 struct mxc_nand_host *host = nand_chip->priv;
668 u16 col = host->buf_start;
669 int n = mtd->oobsize + mtd->writesize - col;
673 memcpy(buf, host->data_buf + col, n);
675 host->buf_start += n;
678 /* Used by the upper layer to verify the data in NAND Flash
679 * with the data in the buf. */
680 static int mxc_nand_verify_buf(struct mtd_info *mtd,
681 const u_char *buf, int len)
686 /* This function is used by upper layer for select and
687 * deselect of the NAND chip */
688 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
690 struct nand_chip *nand_chip = mtd->priv;
691 struct mxc_nand_host *host = nand_chip->priv;
694 /* Disable the NFC clock */
696 clk_disable(host->clk);
702 if (!host->clk_act) {
703 /* Enable the NFC clock */
704 clk_enable(host->clk);
709 host->active_cs = chip;
710 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
715 * Function to transfer data to/from spare area.
717 static void copy_spare(struct mtd_info *mtd, bool bfrom)
719 struct nand_chip *this = mtd->priv;
720 struct mxc_nand_host *host = this->priv;
722 u16 n = mtd->writesize >> 9;
723 u8 *d = host->data_buf + mtd->writesize;
724 u8 *s = host->spare0;
725 u16 t = host->spare_len;
727 j = (mtd->oobsize / n >> 1) << 1;
730 for (i = 0; i < n - 1; i++)
731 memcpy(d + i * j, s + i * t, j);
733 /* the last section */
734 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
736 for (i = 0; i < n - 1; i++)
737 memcpy(&s[i * t], &d[i * j], j);
739 /* the last section */
740 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
744 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
746 struct nand_chip *nand_chip = mtd->priv;
747 struct mxc_nand_host *host = nand_chip->priv;
749 /* Write out column address, if necessary */
752 * MXC NANDFC can only perform full page+spare or
753 * spare-only read/write. When the upper layers
754 * perform a read/write buf operation, the saved column
755 * address is used to index into the full page.
757 host->send_addr(host, 0, page_addr == -1);
758 if (mtd->writesize > 512)
759 /* another col addr cycle for 2k page */
760 host->send_addr(host, 0, false);
763 /* Write out page address, if necessary */
764 if (page_addr != -1) {
765 /* paddr_0 - p_addr_7 */
766 host->send_addr(host, (page_addr & 0xff), false);
768 if (mtd->writesize > 512) {
769 if (mtd->size >= 0x10000000) {
770 /* paddr_8 - paddr_15 */
771 host->send_addr(host, (page_addr >> 8) & 0xff, false);
772 host->send_addr(host, (page_addr >> 16) & 0xff, true);
774 /* paddr_8 - paddr_15 */
775 host->send_addr(host, (page_addr >> 8) & 0xff, true);
777 /* One more address cycle for higher density devices */
778 if (mtd->size >= 0x4000000) {
779 /* paddr_8 - paddr_15 */
780 host->send_addr(host, (page_addr >> 8) & 0xff, false);
781 host->send_addr(host, (page_addr >> 16) & 0xff, true);
783 /* paddr_8 - paddr_15 */
784 host->send_addr(host, (page_addr >> 8) & 0xff, true);
790 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
791 * on how much oob the nand chip has. For 8bit ecc we need at least
792 * 26 bytes of oob data per 512 byte block.
794 static int get_eccsize(struct mtd_info *mtd)
796 int oobbytes_per_512 = 0;
798 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
800 if (oobbytes_per_512 < 26)
806 static void preset_v1_v2(struct mtd_info *mtd)
808 struct nand_chip *nand_chip = mtd->priv;
809 struct mxc_nand_host *host = nand_chip->priv;
810 uint16_t config1 = 0;
812 if (nand_chip->ecc.mode == NAND_ECC_HW)
813 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
816 config1 |= NFC_V2_CONFIG1_FP_INT;
819 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
821 if (nfc_is_v21() && mtd->writesize) {
822 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
824 host->eccsize = get_eccsize(mtd);
825 if (host->eccsize == 4)
826 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
828 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
833 writew(config1, NFC_V1_V2_CONFIG1);
834 /* preset operation */
836 /* Unlock the internal RAM Buffer */
837 writew(0x2, NFC_V1_V2_CONFIG);
839 /* Blocks to be unlocked */
841 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
842 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
843 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
844 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
845 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
846 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
847 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
848 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
849 } else if (nfc_is_v1()) {
850 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
851 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
855 /* Unlock Block Command for given address range */
856 writew(0x4, NFC_V1_V2_WRPROT);
859 static void preset_v3(struct mtd_info *mtd)
861 struct nand_chip *chip = mtd->priv;
862 struct mxc_nand_host *host = chip->priv;
863 uint32_t config2, config3;
866 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
867 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
869 /* Unlock the internal RAM Buffer */
870 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
873 /* Blocks to be unlocked */
874 for (i = 0; i < NAND_MAX_CHIPS; i++)
875 writel(0x0 | (0xffff << 16),
876 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
878 writel(0, NFC_V3_IPC);
880 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
881 NFC_V3_CONFIG2_2CMD_PHASES |
882 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
883 NFC_V3_CONFIG2_ST_CMD(0x70) |
884 NFC_V3_CONFIG2_INT_MSK |
885 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
887 if (chip->ecc.mode == NAND_ECC_HW)
888 config2 |= NFC_V3_CONFIG2_ECC_EN;
890 addr_phases = fls(chip->pagemask) >> 3;
892 if (mtd->writesize == 2048) {
893 config2 |= NFC_V3_CONFIG2_PS_2048;
894 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
895 } else if (mtd->writesize == 4096) {
896 config2 |= NFC_V3_CONFIG2_PS_4096;
897 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
899 config2 |= NFC_V3_CONFIG2_PS_512;
900 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
903 if (mtd->writesize) {
904 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
905 host->eccsize = get_eccsize(mtd);
906 if (host->eccsize == 8)
907 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
910 writel(config2, NFC_V3_CONFIG2);
912 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
913 NFC_V3_CONFIG3_NO_SDMA |
914 NFC_V3_CONFIG3_RBB_MODE |
915 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
916 NFC_V3_CONFIG3_ADD_OP(0);
918 if (!(chip->options & NAND_BUSWIDTH_16))
919 config3 |= NFC_V3_CONFIG3_FW8;
921 writel(config3, NFC_V3_CONFIG3);
923 writel(0, NFC_V3_DELAY_LINE);
926 /* Used by the upper layer to write command to NAND Flash for
927 * different operations to be carried out on NAND Flash */
928 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
929 int column, int page_addr)
931 struct nand_chip *nand_chip = mtd->priv;
932 struct mxc_nand_host *host = nand_chip->priv;
934 DEBUG(MTD_DEBUG_LEVEL3,
935 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
936 command, column, page_addr);
938 /* Reset command state information */
939 host->status_request = false;
941 /* Command pre-processing step */
945 host->send_cmd(host, command, false);
948 case NAND_CMD_STATUS:
950 host->status_request = true;
952 host->send_cmd(host, command, true);
953 mxc_do_addr_cycle(mtd, column, page_addr);
957 case NAND_CMD_READOOB:
958 if (command == NAND_CMD_READ0)
959 host->buf_start = column;
961 host->buf_start = column + mtd->writesize;
963 command = NAND_CMD_READ0; /* only READ0 is valid */
965 host->send_cmd(host, command, false);
966 mxc_do_addr_cycle(mtd, column, page_addr);
968 if (mtd->writesize > 512)
969 host->send_cmd(host, NAND_CMD_READSTART, true);
971 host->send_page(mtd, NFC_OUTPUT);
973 memcpy(host->data_buf, host->main_area0, mtd->writesize);
974 copy_spare(mtd, true);
978 if (column >= mtd->writesize)
979 /* call ourself to read a page */
980 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
982 host->buf_start = column;
984 host->send_cmd(host, command, false);
985 mxc_do_addr_cycle(mtd, column, page_addr);
988 case NAND_CMD_PAGEPROG:
989 memcpy(host->main_area0, host->data_buf, mtd->writesize);
990 copy_spare(mtd, false);
991 host->send_page(mtd, NFC_INPUT);
992 host->send_cmd(host, command, true);
993 mxc_do_addr_cycle(mtd, column, page_addr);
996 case NAND_CMD_READID:
997 host->send_cmd(host, command, true);
998 mxc_do_addr_cycle(mtd, column, page_addr);
999 host->send_read_id(host);
1000 host->buf_start = column;
1003 case NAND_CMD_ERASE1:
1004 case NAND_CMD_ERASE2:
1005 host->send_cmd(host, command, false);
1006 mxc_do_addr_cycle(mtd, column, page_addr);
1013 * The generic flash bbt decriptors overlap with our ecc
1014 * hardware, so define some i.MX specific ones.
1016 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1017 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1019 static struct nand_bbt_descr bbt_main_descr = {
1020 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1021 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1026 .pattern = bbt_pattern,
1029 static struct nand_bbt_descr bbt_mirror_descr = {
1030 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1031 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1036 .pattern = mirror_pattern,
1039 static int __init mxcnd_probe(struct platform_device *pdev)
1041 struct nand_chip *this;
1042 struct mtd_info *mtd;
1043 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1044 struct mxc_nand_host *host;
1045 struct resource *res;
1047 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1049 /* Allocate memory for MTD device structure and private data */
1050 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1051 NAND_MAX_OOBSIZE, GFP_KERNEL);
1055 host->data_buf = (uint8_t *)(host + 1);
1057 host->dev = &pdev->dev;
1058 /* structures must be linked */
1062 mtd->owner = THIS_MODULE;
1063 mtd->dev.parent = &pdev->dev;
1064 mtd->name = DRIVER_NAME;
1066 /* 50 us command delay time */
1067 this->chip_delay = 5;
1070 this->dev_ready = mxc_nand_dev_ready;
1071 this->cmdfunc = mxc_nand_command;
1072 this->select_chip = mxc_nand_select_chip;
1073 this->read_byte = mxc_nand_read_byte;
1074 this->read_word = mxc_nand_read_word;
1075 this->write_buf = mxc_nand_write_buf;
1076 this->read_buf = mxc_nand_read_buf;
1077 this->verify_buf = mxc_nand_verify_buf;
1079 host->clk = clk_get(&pdev->dev, "nfc");
1080 if (IS_ERR(host->clk)) {
1081 err = PTR_ERR(host->clk);
1085 clk_enable(host->clk);
1088 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1094 host->base = ioremap(res->start, resource_size(res));
1100 host->main_area0 = host->base;
1102 if (nfc_is_v1() || nfc_is_v21()) {
1103 host->preset = preset_v1_v2;
1104 host->send_cmd = send_cmd_v1_v2;
1105 host->send_addr = send_addr_v1_v2;
1106 host->send_page = send_page_v1_v2;
1107 host->send_read_id = send_read_id_v1_v2;
1108 host->get_dev_status = get_dev_status_v1_v2;
1109 host->check_int = check_int_v1_v2;
1111 host->irq_control = irq_control_mx21;
1113 host->irq_control = irq_control_v1_v2;
1117 host->regs = host->base + 0x1e00;
1118 host->spare0 = host->base + 0x1000;
1119 host->spare_len = 64;
1120 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1121 oob_largepage = &nandv2_hw_eccoob_largepage;
1122 this->ecc.bytes = 9;
1123 } else if (nfc_is_v1()) {
1124 host->regs = host->base + 0xe00;
1125 host->spare0 = host->base + 0x800;
1126 host->spare_len = 16;
1127 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1128 oob_largepage = &nandv1_hw_eccoob_largepage;
1129 this->ecc.bytes = 3;
1131 } else if (nfc_is_v3_2()) {
1132 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1137 host->regs_ip = ioremap(res->start, resource_size(res));
1138 if (!host->regs_ip) {
1142 host->regs_axi = host->base + 0x1e00;
1143 host->spare0 = host->base + 0x1000;
1144 host->spare_len = 64;
1145 host->preset = preset_v3;
1146 host->send_cmd = send_cmd_v3;
1147 host->send_addr = send_addr_v3;
1148 host->send_page = send_page_v3;
1149 host->send_read_id = send_read_id_v3;
1150 host->check_int = check_int_v3;
1151 host->get_dev_status = get_dev_status_v3;
1152 host->irq_control = irq_control_v3;
1153 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1154 oob_largepage = &nandv2_hw_eccoob_largepage;
1158 this->ecc.size = 512;
1159 this->ecc.layout = oob_smallpage;
1161 if (pdata->hw_ecc) {
1162 this->ecc.calculate = mxc_nand_calculate_ecc;
1163 this->ecc.hwctl = mxc_nand_enable_hwecc;
1165 this->ecc.correct = mxc_nand_correct_data_v1;
1167 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1168 this->ecc.mode = NAND_ECC_HW;
1170 this->ecc.mode = NAND_ECC_SOFT;
1173 /* NAND bus width determines access funtions used by upper layer */
1174 if (pdata->width == 2)
1175 this->options |= NAND_BUSWIDTH_16;
1177 if (pdata->flash_bbt) {
1178 this->bbt_td = &bbt_main_descr;
1179 this->bbt_md = &bbt_mirror_descr;
1180 /* update flash based bbt */
1181 this->bbt_options |= NAND_BBT_USE_FLASH;
1184 init_completion(&host->op_completion);
1186 host->irq = platform_get_irq(pdev, 0);
1189 * mask the interrupt. For i.MX21 explicitely call
1190 * irq_control_v1_v2 to use the mask bit. We can't call
1191 * disable_irq_nosync() for an interrupt we do not own yet.
1194 irq_control_v1_v2(host, 0);
1196 host->irq_control(host, 0);
1198 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1202 host->irq_control(host, 0);
1205 * Now that the interrupt is disabled make sure the interrupt
1206 * mask bit is cleared on i.MX21. Otherwise we can't read
1207 * the interrupt status bit on this machine.
1210 irq_control_v1_v2(host, 1);
1212 /* first scan to find the device and get the page size */
1213 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1218 /* Call preset again, with correct writesize this time */
1221 if (mtd->writesize == 2048)
1222 this->ecc.layout = oob_largepage;
1223 if (nfc_is_v21() && mtd->writesize == 4096)
1224 this->ecc.layout = &nandv2_hw_eccoob_4k;
1226 /* second phase scan */
1227 if (nand_scan_tail(mtd)) {
1232 /* Register the partitions */
1233 mtd_device_parse_register(mtd, part_probes, 0,
1234 pdata->parts, pdata->nr_parts);
1236 platform_set_drvdata(pdev, host);
1241 free_irq(host->irq, host);
1244 iounmap(host->regs_ip);
1245 iounmap(host->base);
1254 static int __devexit mxcnd_remove(struct platform_device *pdev)
1256 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1260 platform_set_drvdata(pdev, NULL);
1262 nand_release(&host->mtd);
1263 free_irq(host->irq, host);
1265 iounmap(host->regs_ip);
1266 iounmap(host->base);
1272 static struct platform_driver mxcnd_driver = {
1274 .name = DRIVER_NAME,
1276 .remove = __devexit_p(mxcnd_remove),
1279 static int __init mxc_nd_init(void)
1281 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1284 static void __exit mxc_nd_cleanup(void)
1286 /* Unregister the device structure */
1287 platform_driver_unregister(&mxcnd_driver);
1290 module_init(mxc_nd_init);
1291 module_exit(mxc_nd_cleanup);
1293 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1294 MODULE_DESCRIPTION("MXC NAND MTD driver");
1295 MODULE_LICENSE("GPL");