2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
38 #define DRIVER_NAME "mxc_nand"
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27())
43 /* Addresses for NFC registers */
44 #define NFC_BUF_SIZE 0xE00
45 #define NFC_BUF_ADDR 0xE04
46 #define NFC_FLASH_ADDR 0xE06
47 #define NFC_FLASH_CMD 0xE08
48 #define NFC_CONFIG 0xE0A
49 #define NFC_ECC_STATUS_RESULT 0xE0C
50 #define NFC_RSLTMAIN_AREA 0xE0E
51 #define NFC_RSLTSPARE_AREA 0xE10
52 #define NFC_WRPROT 0xE12
53 #define NFC_V1_UNLOCKSTART_BLKADDR 0xe14
54 #define NFC_V1_UNLOCKEND_BLKADDR 0xe16
55 #define NFC_V21_UNLOCKSTART_BLKADDR 0xe20
56 #define NFC_V21_UNLOCKEND_BLKADDR 0xe22
57 #define NFC_NF_WRPRST 0xE18
58 #define NFC_CONFIG1 0xE1A
59 #define NFC_CONFIG2 0xE1C
61 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
62 * for Command operation */
65 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
66 * for Address operation */
69 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
70 * for Input operation */
73 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
74 * for Data Output operation */
75 #define NFC_OUTPUT 0x8
77 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
78 * for Read ID operation */
81 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
82 * for Read Status operation */
83 #define NFC_STATUS 0x20
85 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
87 #define NFC_INT 0x8000
89 #define NFC_SP_EN (1 << 2)
90 #define NFC_ECC_EN (1 << 3)
91 #define NFC_INT_MSK (1 << 4)
92 #define NFC_BIG (1 << 5)
93 #define NFC_RST (1 << 6)
94 #define NFC_CE (1 << 7)
95 #define NFC_ONE_CYCLE (1 << 8)
97 struct mxc_nand_host {
99 struct nand_chip nand;
100 struct mtd_partition *parts;
114 wait_queue_head_t irq_waitq;
117 unsigned int buf_start;
121 /* Define delays in microsec for NAND device operations */
122 #define TROP_US_DELAY 2000
124 /* OOB placement block for use with hardware ecc generation */
125 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
127 .eccpos = {6, 7, 8, 9, 10},
128 .oobfree = {{0, 5}, {12, 4}, }
131 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
133 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
134 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
135 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
138 /* OOB description for 512 byte pages with 16 byte OOB */
139 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
142 7, 8, 9, 10, 11, 12, 13, 14, 15
145 {.offset = 0, .length = 5}
149 /* OOB description for 2048 byte pages with 64 byte OOB */
150 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
153 7, 8, 9, 10, 11, 12, 13, 14, 15,
154 23, 24, 25, 26, 27, 28, 29, 30, 31,
155 39, 40, 41, 42, 43, 44, 45, 46, 47,
156 55, 56, 57, 58, 59, 60, 61, 62, 63
159 {.offset = 2, .length = 4},
160 {.offset = 16, .length = 7},
161 {.offset = 32, .length = 7},
162 {.offset = 48, .length = 7}
166 #ifdef CONFIG_MTD_PARTITIONS
167 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
170 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
172 struct mxc_nand_host *host = dev_id;
176 tmp = readw(host->regs + NFC_CONFIG1);
177 tmp |= NFC_INT_MSK; /* Disable interrupt */
178 writew(tmp, host->regs + NFC_CONFIG1);
180 wake_up(&host->irq_waitq);
185 /* This function polls the NANDFC to wait for the basic operation to
186 * complete by checking the INT bit of config2 register.
188 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
194 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
196 tmp = readw(host->regs + NFC_CONFIG1);
197 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
198 writew(tmp, host->regs + NFC_CONFIG1);
200 wait_event(host->irq_waitq,
201 readw(host->regs + NFC_CONFIG2) & NFC_INT);
203 tmp = readw(host->regs + NFC_CONFIG2);
205 writew(tmp, host->regs + NFC_CONFIG2);
208 while (max_retries-- > 0) {
209 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
210 tmp = readw(host->regs + NFC_CONFIG2);
212 writew(tmp, host->regs + NFC_CONFIG2);
218 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
223 /* This function issues the specified command to the NAND device and
224 * waits for completion. */
225 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
227 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
229 writew(cmd, host->regs + NFC_FLASH_CMD);
230 writew(NFC_CMD, host->regs + NFC_CONFIG2);
232 /* Wait for operation to complete */
233 wait_op_done(host, TROP_US_DELAY, useirq);
236 /* This function sends an address (or partial address) to the
237 * NAND device. The address is used to select the source/destination for
239 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
241 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
243 writew(addr, host->regs + NFC_FLASH_ADDR);
244 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
246 /* Wait for operation to complete */
247 wait_op_done(host, TROP_US_DELAY, islast);
250 static void send_page(struct mtd_info *mtd, unsigned int ops)
252 struct nand_chip *nand_chip = mtd->priv;
253 struct mxc_nand_host *host = nand_chip->priv;
256 if (nfc_is_v1() && mtd->writesize > 512)
261 for (i = 0; i < bufs; i++) {
263 /* NANDFC buffer 0 is used for page read/write */
264 writew(i, host->regs + NFC_BUF_ADDR);
266 writew(ops, host->regs + NFC_CONFIG2);
268 /* Wait for operation to complete */
269 wait_op_done(host, TROP_US_DELAY, true);
273 /* Request the NANDFC to perform a read of the NAND device ID. */
274 static void send_read_id(struct mxc_nand_host *host)
276 struct nand_chip *this = &host->nand;
278 /* NANDFC buffer 0 is used for device ID output */
279 writew(0x0, host->regs + NFC_BUF_ADDR);
281 writew(NFC_ID, host->regs + NFC_CONFIG2);
283 /* Wait for operation to complete */
284 wait_op_done(host, TROP_US_DELAY, true);
286 if (this->options & NAND_BUSWIDTH_16) {
287 void __iomem *main_buf = host->main_area0;
288 /* compress the ID info */
289 writeb(readb(main_buf + 2), main_buf + 1);
290 writeb(readb(main_buf + 4), main_buf + 2);
291 writeb(readb(main_buf + 6), main_buf + 3);
292 writeb(readb(main_buf + 8), main_buf + 4);
293 writeb(readb(main_buf + 10), main_buf + 5);
295 memcpy(host->data_buf, host->main_area0, 16);
298 /* This function requests the NANDFC to perform a read of the
299 * NAND device status and returns the current status. */
300 static uint16_t get_dev_status(struct mxc_nand_host *host)
302 void __iomem *main_buf = host->main_area1;
305 /* Issue status request to NAND device */
307 /* store the main area1 first word, later do recovery */
308 store = readl(main_buf);
309 /* NANDFC buffer 1 is used for device status to prevent
310 * corruption of read/write buffer on status requests. */
311 writew(1, host->regs + NFC_BUF_ADDR);
313 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
315 /* Wait for operation to complete */
316 wait_op_done(host, TROP_US_DELAY, true);
318 /* Status is placed in first word of main buffer */
319 /* get status, then recovery area 1 data */
320 ret = readw(main_buf);
321 writel(store, main_buf);
326 /* This functions is used by upper layer to checks if device is ready */
327 static int mxc_nand_dev_ready(struct mtd_info *mtd)
330 * NFC handles R/B internally. Therefore, this function
331 * always returns status as ready.
336 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
339 * If HW ECC is enabled, we turn it on during init. There is
340 * no need to enable again here.
344 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
345 u_char *read_ecc, u_char *calc_ecc)
347 struct nand_chip *nand_chip = mtd->priv;
348 struct mxc_nand_host *host = nand_chip->priv;
351 * 1-Bit errors are automatically corrected in HW. No need for
352 * additional correction. 2-Bit errors cannot be corrected by
353 * HW ECC, so we need to return failure
355 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
357 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
358 DEBUG(MTD_DEBUG_LEVEL0,
359 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
366 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
372 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
374 struct nand_chip *nand_chip = mtd->priv;
375 struct mxc_nand_host *host = nand_chip->priv;
378 /* Check for status request */
379 if (host->status_request)
380 return get_dev_status(host) & 0xFF;
382 ret = *(uint8_t *)(host->data_buf + host->buf_start);
388 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
390 struct nand_chip *nand_chip = mtd->priv;
391 struct mxc_nand_host *host = nand_chip->priv;
394 ret = *(uint16_t *)(host->data_buf + host->buf_start);
395 host->buf_start += 2;
400 /* Write data of length len to buffer buf. The data to be
401 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
402 * Operation by the NFC, the data is written to NAND Flash */
403 static void mxc_nand_write_buf(struct mtd_info *mtd,
404 const u_char *buf, int len)
406 struct nand_chip *nand_chip = mtd->priv;
407 struct mxc_nand_host *host = nand_chip->priv;
408 u16 col = host->buf_start;
409 int n = mtd->oobsize + mtd->writesize - col;
413 memcpy(host->data_buf + col, buf, n);
415 host->buf_start += n;
418 /* Read the data buffer from the NAND Flash. To read the data from NAND
419 * Flash first the data output cycle is initiated by the NFC, which copies
420 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
422 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
424 struct nand_chip *nand_chip = mtd->priv;
425 struct mxc_nand_host *host = nand_chip->priv;
426 u16 col = host->buf_start;
427 int n = mtd->oobsize + mtd->writesize - col;
431 memcpy(buf, host->data_buf + col, len);
433 host->buf_start += len;
436 /* Used by the upper layer to verify the data in NAND Flash
437 * with the data in the buf. */
438 static int mxc_nand_verify_buf(struct mtd_info *mtd,
439 const u_char *buf, int len)
444 /* This function is used by upper layer for select and
445 * deselect of the NAND chip */
446 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
448 struct nand_chip *nand_chip = mtd->priv;
449 struct mxc_nand_host *host = nand_chip->priv;
453 /* Disable the NFC clock */
455 clk_disable(host->clk);
460 /* Enable the NFC clock */
461 if (!host->clk_act) {
462 clk_enable(host->clk);
473 * Function to transfer data to/from spare area.
475 static void copy_spare(struct mtd_info *mtd, bool bfrom)
477 struct nand_chip *this = mtd->priv;
478 struct mxc_nand_host *host = this->priv;
480 u16 n = mtd->writesize >> 9;
481 u8 *d = host->data_buf + mtd->writesize;
482 u8 *s = host->spare0;
483 u16 t = host->spare_len;
485 j = (mtd->oobsize / n >> 1) << 1;
488 for (i = 0; i < n - 1; i++)
489 memcpy(d + i * j, s + i * t, j);
491 /* the last section */
492 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
494 for (i = 0; i < n - 1; i++)
495 memcpy(&s[i * t], &d[i * j], j);
497 /* the last section */
498 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
502 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
504 struct nand_chip *nand_chip = mtd->priv;
505 struct mxc_nand_host *host = nand_chip->priv;
507 /* Write out column address, if necessary */
510 * MXC NANDFC can only perform full page+spare or
511 * spare-only read/write. When the upper layers
512 * layers perform a read/write buf operation,
513 * we will used the saved column adress to index into
516 send_addr(host, 0, page_addr == -1);
517 if (mtd->writesize > 512)
518 /* another col addr cycle for 2k page */
519 send_addr(host, 0, false);
522 /* Write out page address, if necessary */
523 if (page_addr != -1) {
524 /* paddr_0 - p_addr_7 */
525 send_addr(host, (page_addr & 0xff), false);
527 if (mtd->writesize > 512) {
528 if (mtd->size >= 0x10000000) {
529 /* paddr_8 - paddr_15 */
530 send_addr(host, (page_addr >> 8) & 0xff, false);
531 send_addr(host, (page_addr >> 16) & 0xff, true);
533 /* paddr_8 - paddr_15 */
534 send_addr(host, (page_addr >> 8) & 0xff, true);
536 /* One more address cycle for higher density devices */
537 if (mtd->size >= 0x4000000) {
538 /* paddr_8 - paddr_15 */
539 send_addr(host, (page_addr >> 8) & 0xff, false);
540 send_addr(host, (page_addr >> 16) & 0xff, true);
542 /* paddr_8 - paddr_15 */
543 send_addr(host, (page_addr >> 8) & 0xff, true);
548 /* Used by the upper layer to write command to NAND Flash for
549 * different operations to be carried out on NAND Flash */
550 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
551 int column, int page_addr)
553 struct nand_chip *nand_chip = mtd->priv;
554 struct mxc_nand_host *host = nand_chip->priv;
556 DEBUG(MTD_DEBUG_LEVEL3,
557 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
558 command, column, page_addr);
560 /* Reset command state information */
561 host->status_request = false;
563 /* Command pre-processing step */
566 case NAND_CMD_STATUS:
568 host->status_request = true;
570 send_cmd(host, command, true);
571 mxc_do_addr_cycle(mtd, column, page_addr);
575 case NAND_CMD_READOOB:
576 if (command == NAND_CMD_READ0)
577 host->buf_start = column;
579 host->buf_start = column + mtd->writesize;
581 if (mtd->writesize > 512)
582 command = NAND_CMD_READ0; /* only READ0 is valid */
584 send_cmd(host, command, false);
585 mxc_do_addr_cycle(mtd, column, page_addr);
587 if (mtd->writesize > 512)
588 send_cmd(host, NAND_CMD_READSTART, true);
590 send_page(mtd, NFC_OUTPUT);
592 memcpy(host->data_buf, host->main_area0, mtd->writesize);
593 copy_spare(mtd, true);
597 if (column >= mtd->writesize) {
599 * FIXME: before send SEQIN command for write OOB,
600 * We must read one page out.
601 * For K9F1GXX has no READ1 command to set current HW
602 * pointer to spare area, we must write the whole page
603 * including OOB together.
605 if (mtd->writesize > 512)
606 /* call ourself to read a page */
607 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
610 host->buf_start = column;
612 /* Set program pointer to spare region */
613 if (mtd->writesize == 512)
614 send_cmd(host, NAND_CMD_READOOB, false);
616 host->buf_start = column;
618 /* Set program pointer to page start */
619 if (mtd->writesize == 512)
620 send_cmd(host, NAND_CMD_READ0, false);
623 send_cmd(host, command, false);
624 mxc_do_addr_cycle(mtd, column, page_addr);
627 case NAND_CMD_PAGEPROG:
628 memcpy(host->main_area0, host->data_buf, mtd->writesize);
629 copy_spare(mtd, false);
630 send_page(mtd, NFC_INPUT);
631 send_cmd(host, command, true);
632 mxc_do_addr_cycle(mtd, column, page_addr);
635 case NAND_CMD_READID:
636 send_cmd(host, command, true);
637 mxc_do_addr_cycle(mtd, column, page_addr);
639 host->buf_start = column;
642 case NAND_CMD_ERASE1:
643 case NAND_CMD_ERASE2:
644 send_cmd(host, command, false);
645 mxc_do_addr_cycle(mtd, column, page_addr);
652 * The generic flash bbt decriptors overlap with our ecc
653 * hardware, so define some i.MX specific ones.
655 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
656 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
658 static struct nand_bbt_descr bbt_main_descr = {
659 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
660 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
665 .pattern = bbt_pattern,
668 static struct nand_bbt_descr bbt_mirror_descr = {
669 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
670 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
675 .pattern = mirror_pattern,
678 static int __init mxcnd_probe(struct platform_device *pdev)
680 struct nand_chip *this;
681 struct mtd_info *mtd;
682 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
683 struct mxc_nand_host *host;
684 struct resource *res;
686 int err = 0, nr_parts = 0;
687 struct nand_ecclayout *oob_smallpage, *oob_largepage;
689 /* Allocate memory for MTD device structure and private data */
690 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
691 NAND_MAX_OOBSIZE, GFP_KERNEL);
695 host->data_buf = (uint8_t *)(host + 1);
697 host->dev = &pdev->dev;
698 /* structures must be linked */
702 mtd->owner = THIS_MODULE;
703 mtd->dev.parent = &pdev->dev;
704 mtd->name = "mxc_nand";
706 /* 50 us command delay time */
707 this->chip_delay = 5;
710 this->dev_ready = mxc_nand_dev_ready;
711 this->cmdfunc = mxc_nand_command;
712 this->select_chip = mxc_nand_select_chip;
713 this->read_byte = mxc_nand_read_byte;
714 this->read_word = mxc_nand_read_word;
715 this->write_buf = mxc_nand_write_buf;
716 this->read_buf = mxc_nand_read_buf;
717 this->verify_buf = mxc_nand_verify_buf;
719 host->clk = clk_get(&pdev->dev, "nfc");
720 if (IS_ERR(host->clk)) {
721 err = PTR_ERR(host->clk);
725 clk_enable(host->clk);
728 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
734 host->base = ioremap(res->start, resource_size(res));
740 host->main_area0 = host->base;
741 host->main_area1 = host->base + 0x200;
744 host->regs = host->base + 0x1000;
745 host->spare0 = host->base + 0x1000;
746 host->spare_len = 64;
747 oob_smallpage = &nandv2_hw_eccoob_smallpage;
748 oob_largepage = &nandv2_hw_eccoob_largepage;
749 } else if (nfc_is_v1()) {
750 host->regs = host->base;
751 host->spare0 = host->base + 0x800;
752 host->spare_len = 16;
753 oob_smallpage = &nandv1_hw_eccoob_smallpage;
754 oob_largepage = &nandv1_hw_eccoob_largepage;
758 /* disable interrupt and spare enable */
759 tmp = readw(host->regs + NFC_CONFIG1);
762 writew(tmp, host->regs + NFC_CONFIG1);
764 init_waitqueue_head(&host->irq_waitq);
766 host->irq = platform_get_irq(pdev, 0);
768 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
773 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
775 /* preset operation */
776 /* Unlock the internal RAM Buffer */
777 writew(0x2, host->regs + NFC_CONFIG);
779 /* Blocks to be unlocked */
781 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
782 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
784 } else if (nfc_is_v1()) {
785 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
786 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
791 /* Unlock Block Command for given address range */
792 writew(0x4, host->regs + NFC_WRPROT);
794 this->ecc.size = 512;
795 this->ecc.layout = oob_smallpage;
798 this->ecc.calculate = mxc_nand_calculate_ecc;
799 this->ecc.hwctl = mxc_nand_enable_hwecc;
800 this->ecc.correct = mxc_nand_correct_data;
801 this->ecc.mode = NAND_ECC_HW;
802 tmp = readw(host->regs + NFC_CONFIG1);
804 writew(tmp, host->regs + NFC_CONFIG1);
806 this->ecc.mode = NAND_ECC_SOFT;
807 tmp = readw(host->regs + NFC_CONFIG1);
809 writew(tmp, host->regs + NFC_CONFIG1);
812 /* NAND bus width determines access funtions used by upper layer */
813 if (pdata->width == 2)
814 this->options |= NAND_BUSWIDTH_16;
816 if (pdata->flash_bbt) {
817 this->bbt_td = &bbt_main_descr;
818 this->bbt_md = &bbt_mirror_descr;
819 /* update flash based bbt */
820 this->options |= NAND_USE_FLASH_BBT;
823 /* first scan to find the device and get the page size */
824 if (nand_scan_ident(mtd, 1)) {
829 if (mtd->writesize == 2048)
830 this->ecc.layout = oob_largepage;
832 /* second phase scan */
833 if (nand_scan_tail(mtd)) {
838 /* Register the partitions */
839 #ifdef CONFIG_MTD_PARTITIONS
841 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
843 add_mtd_partitions(mtd, host->parts, nr_parts);
847 pr_info("Registering %s as whole device\n", mtd->name);
851 platform_set_drvdata(pdev, host);
856 free_irq(host->irq, host);
867 static int __exit mxcnd_remove(struct platform_device *pdev)
869 struct mxc_nand_host *host = platform_get_drvdata(pdev);
873 platform_set_drvdata(pdev, NULL);
875 nand_release(&host->mtd);
876 free_irq(host->irq, host);
884 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
886 struct mtd_info *mtd = platform_get_drvdata(pdev);
887 struct nand_chip *nand_chip = mtd->priv;
888 struct mxc_nand_host *host = nand_chip->priv;
891 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
893 ret = mtd->suspend(mtd);
894 /* Disable the NFC clock */
895 clk_disable(host->clk);
901 static int mxcnd_resume(struct platform_device *pdev)
903 struct mtd_info *mtd = platform_get_drvdata(pdev);
904 struct nand_chip *nand_chip = mtd->priv;
905 struct mxc_nand_host *host = nand_chip->priv;
908 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
911 /* Enable the NFC clock */
912 clk_enable(host->clk);
920 # define mxcnd_suspend NULL
921 # define mxcnd_resume NULL
922 #endif /* CONFIG_PM */
924 static struct platform_driver mxcnd_driver = {
928 .remove = __exit_p(mxcnd_remove),
929 .suspend = mxcnd_suspend,
930 .resume = mxcnd_resume,
933 static int __init mxc_nd_init(void)
935 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
938 static void __exit mxc_nd_cleanup(void)
940 /* Unregister the device structure */
941 platform_driver_unregister(&mxcnd_driver);
944 module_init(mxc_nd_init);
945 module_exit(mxc_nd_cleanup);
947 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
948 MODULE_DESCRIPTION("MXC NAND MTD driver");
949 MODULE_LICENSE("GPL");