drivers/mtd/devices/ps3vram.c

   1 /**
   2  * ps3vram - Use extra PS3 video ram as MTD block device.
   3  *
   4  * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com>
   5  * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr>
   6  */
   7
   8 #include <linux/io.h>
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/list.h>
  12 #include <linux/module.h>
  13 #include <linux/moduleparam.h>
  14 #include <linux/slab.h>
  15 #include <linux/version.h>
  16 #include <linux/gfp.h>
  17 #include <linux/delay.h>
  18 #include <linux/mtd/mtd.h>
  19
  20 #include <asm/lv1call.h>
  21 #include <asm/ps3.h>
  22
  23 #define DEVICE_NAME             "ps3vram"
  24
  25 #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */
  26 #define XDR_IOIF 0x0c000000
  27
  28 #define FIFO_BASE XDR_IOIF
  29 #define FIFO_SIZE (64 * 1024)
  30
  31 #define DMA_PAGE_SIZE (4 * 1024)
  32
  33 #define CACHE_PAGE_SIZE (256 * 1024)
  34 #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE)
  35
  36 #define CACHE_OFFSET CACHE_PAGE_SIZE
  37 #define FIFO_OFFSET 0
  38
  39 #define CTRL_PUT 0x10
  40 #define CTRL_GET 0x11
  41 #define CTRL_TOP 0x15
  42
  43 #define UPLOAD_SUBCH    1
  44 #define DOWNLOAD_SUBCH  2
  45
  46 #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN    0x0000030c
  47 #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY       0x00000104
  48
  49 #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601
  50
  51 struct mtd_info ps3vram_mtd;
  52
  53 #define CACHE_PAGE_PRESENT 1
  54 #define CACHE_PAGE_DIRTY   2
  55
  56 #define dbg(fmt, args...)       \
  57         pr_debug("%s:%d " fmt "\n", __func__, __LINE__, ## args)
  58
  59 struct ps3vram_tag {
  60         unsigned int address;
  61         unsigned int flags;
  62 };
  63
  64 struct ps3vram_cache {
  65         unsigned int page_count;
  66         unsigned int page_size;
  67         struct ps3vram_tag *tags;
  68 };
  69
  70 struct ps3vram_priv {
  71         uint64_t memory_handle;
  72         uint64_t context_handle;
  73         uint8_t *base;
  74         uint32_t *ctrl;
  75         uint32_t *reports;
  76         uint8_t *xdr_buf;
  77
  78         uint32_t *fifo_base;
  79         uint32_t *fifo_ptr;
  80
  81         struct ps3vram_cache cache;
  82
  83         /* Used to serialize cache/DMA operations */
  84         struct mutex lock;
  85 };
  86
  87 #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */
  88 #define DMA_NOTIFIER_OFFSET_BASE 0x1000     /* first DMA notifier offset */
  89 #define DMA_NOTIFIER_SIZE        0x40
  90 #define NOTIFIER 7      /* notifier used for completion report */
  91
  92 /* A trailing '-' means to subtract off ps3fb_videomemory.size */
  93 char *size = "256M-";
  94 module_param(size, charp, 0);
  95 MODULE_PARM_DESC(size, "memory size");
  96
  97 static inline uint32_t *ps3vram_get_notifier(uint32_t *reports, int notifier)
  98 {
  99         return (void *) reports +
 100                 DMA_NOTIFIER_OFFSET_BASE +
 101                 DMA_NOTIFIER_SIZE * notifier;
 102 }
 103
 104 static void ps3vram_notifier_reset(struct mtd_info *mtd)
 105 {
 106         int i;
 107         struct ps3vram_priv *priv = mtd->priv;
 108         uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
 109         for (i = 0; i < 4; i++)
 110                 notify[i] = 0xffffffff;
 111 }
 112
 113 static int ps3vram_notifier_wait(struct mtd_info *mtd, int timeout_ms)
 114 {
 115         struct ps3vram_priv *priv = mtd->priv;
 116         uint32_t *notify = ps3vram_get_notifier(priv->reports, NOTIFIER);
 117
 118         timeout_ms *= 1000;
 119
 120         do {
 121                 if (notify[3] == 0)
 122                         return 0;
 123
 124                 if (timeout_ms)
 125                         udelay(1);
 126         } while (timeout_ms--);
 127
 128         return -1;
 129 }
 130
 131 static void ps3vram_init_ring(struct mtd_info *mtd)
 132 {
 133         struct ps3vram_priv *priv = mtd->priv;
 134
 135         priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
 136         priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET;
 137 }
 138
 139 static int ps3vram_wait_ring(struct mtd_info *mtd, int timeout)
 140 {
 141         struct ps3vram_priv *priv = mtd->priv;
 142
 143         /* wait until setup commands are processed */
 144         timeout *= 1000;
 145         while (--timeout) {
 146                 if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET])
 147                         break;
 148                 udelay(1);
 149         }
 150         if (timeout == 0) {
 151                 pr_err("FIFO timeout (%08x/%08x/%08x)\n", priv->ctrl[CTRL_PUT],
 152                        priv->ctrl[CTRL_GET], priv->ctrl[CTRL_TOP]);
 153                 return -ETIMEDOUT;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static inline void ps3vram_out_ring(struct ps3vram_priv *priv, uint32_t data)
 160 {
 161         *(priv->fifo_ptr)++ = data;
 162 }
 163
 164 static inline void ps3vram_begin_ring(struct ps3vram_priv *priv, uint32_t chan,
 165                                       uint32_t tag, uint32_t size)
 166 {
 167         ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag);
 168 }
 169
 170 static void ps3vram_rewind_ring(struct mtd_info *mtd)
 171 {
 172         struct ps3vram_priv *priv = mtd->priv;
 173         u64 status;
 174
 175         ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET));
 176
 177         priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET;
 178
 179         /* asking the HV for a blit will kick the fifo */
 180         status = lv1_gpu_context_attribute(priv->context_handle,
 181                                            L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
 182                                            0, 0, 0, 0);
 183         if (status)
 184                 pr_err("ps3vram: lv1_gpu_context_attribute FB_BLIT failed\n");
 185
 186         priv->fifo_ptr = priv->fifo_base;
 187 }
 188
 189 static void ps3vram_fire_ring(struct mtd_info *mtd)
 190 {
 191         struct ps3vram_priv *priv = mtd->priv;
 192         u64 status;
 193
 194         mutex_lock(&ps3_gpu_mutex);
 195
 196         priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET +
 197                 (priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t);
 198
 199         /* asking the HV for a blit will kick the fifo */
 200         status = lv1_gpu_context_attribute(priv->context_handle,
 201                                            L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT,
 202                                            0, 0, 0, 0);
 203         if (status)
 204                 pr_err("ps3vram: lv1_gpu_context_attribute FB_BLIT failed\n");
 205
 206         if ((priv->fifo_ptr - priv->fifo_base) * sizeof(uint32_t) >
 207             FIFO_SIZE - 1024) {
 208                 dbg("fifo full, rewinding");
 209                 ps3vram_wait_ring(mtd, 200);
 210                 ps3vram_rewind_ring(mtd);
 211         }
 212
 213         mutex_unlock(&ps3_gpu_mutex);
 214 }
 215
 216 static void ps3vram_bind(struct mtd_info *mtd)
 217 {
 218         struct ps3vram_priv *priv = mtd->priv;
 219
 220         ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1);
 221         ps3vram_out_ring(priv, 0x31337303);
 222         ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3);
 223         ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
 224         ps3vram_out_ring(priv, 0xfeed0001);     /* DMA system RAM instance */
 225         ps3vram_out_ring(priv, 0xfeed0000);     /* DMA video RAM instance */
 226
 227         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1);
 228         ps3vram_out_ring(priv, 0x3137c0de);
 229         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3);
 230         ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER);
 231         ps3vram_out_ring(priv, 0xfeed0000);     /* DMA video RAM instance */
 232         ps3vram_out_ring(priv, 0xfeed0001);     /* DMA system RAM instance */
 233
 234         ps3vram_fire_ring(mtd);
 235 }
 236
 237 static int ps3vram_upload(struct mtd_info *mtd, unsigned int src_offset,
 238                           unsigned int dst_offset, int len, int count)
 239 {
 240         struct ps3vram_priv *priv = mtd->priv;
 241
 242         ps3vram_begin_ring(priv, UPLOAD_SUBCH,
 243                            NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 244         ps3vram_out_ring(priv, XDR_IOIF + src_offset);
 245         ps3vram_out_ring(priv, dst_offset);
 246         ps3vram_out_ring(priv, len);
 247         ps3vram_out_ring(priv, len);
 248         ps3vram_out_ring(priv, len);
 249         ps3vram_out_ring(priv, count);
 250         ps3vram_out_ring(priv, (1 << 8) | 1);
 251         ps3vram_out_ring(priv, 0);
 252
 253         ps3vram_notifier_reset(mtd);
 254         ps3vram_begin_ring(priv, UPLOAD_SUBCH,
 255                            NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
 256         ps3vram_out_ring(priv, 0);
 257         ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1);
 258         ps3vram_out_ring(priv, 0);
 259         ps3vram_fire_ring(mtd);
 260         if (ps3vram_notifier_wait(mtd, 200) < 0) {
 261                 pr_err("notifier timeout\n");
 262                 return -1;
 263         }
 264
 265         return 0;
 266 }
 267
 268 static int ps3vram_download(struct mtd_info *mtd, unsigned int src_offset,
 269                             unsigned int dst_offset, int len, int count)
 270 {
 271         struct ps3vram_priv *priv = mtd->priv;
 272
 273         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
 274                            NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 275         ps3vram_out_ring(priv, src_offset);
 276         ps3vram_out_ring(priv, XDR_IOIF + dst_offset);
 277         ps3vram_out_ring(priv, len);
 278         ps3vram_out_ring(priv, len);
 279         ps3vram_out_ring(priv, len);
 280         ps3vram_out_ring(priv, count);
 281         ps3vram_out_ring(priv, (1 << 8) | 1);
 282         ps3vram_out_ring(priv, 0);
 283
 284         ps3vram_notifier_reset(mtd);
 285         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH,
 286                            NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1);
 287         ps3vram_out_ring(priv, 0);
 288         ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1);
 289         ps3vram_out_ring(priv, 0);
 290         ps3vram_fire_ring(mtd);
 291         if (ps3vram_notifier_wait(mtd, 200) < 0) {
 292                 pr_err("notifier timeout\n");
 293                 return -1;
 294         }
 295
 296         return 0;
 297 }
 298
 299 static void ps3vram_cache_evict(struct mtd_info *mtd, int entry)
 300 {
 301         struct ps3vram_priv *priv = mtd->priv;
 302         struct ps3vram_cache *cache = &priv->cache;
 303
 304         if (cache->tags[entry].flags & CACHE_PAGE_DIRTY) {
 305                 dbg("flushing %d : 0x%08x", entry, cache->tags[entry].address);
 306                 if (ps3vram_upload(mtd,
 307                                    CACHE_OFFSET + entry * cache->page_size,
 308                                    cache->tags[entry].address,
 309                                    DMA_PAGE_SIZE,
 310                                    cache->page_size / DMA_PAGE_SIZE) < 0) {
 311                         pr_err("failed to upload from 0x%x to 0x%x size 0x%x\n",
 312                                entry * cache->page_size,
 313                                cache->tags[entry].address,
 314                                cache->page_size);
 315                 }
 316                 cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY;
 317         }
 318 }
 319
 320 static void ps3vram_cache_load(struct mtd_info *mtd, int entry,
 321                                unsigned int address)
 322 {
 323         struct ps3vram_priv *priv = mtd->priv;
 324         struct ps3vram_cache *cache = &priv->cache;
 325
 326         dbg("fetching %d : 0x%08x", entry, address);
 327         if (ps3vram_download(mtd,
 328                              address,
 329                              CACHE_OFFSET + entry * cache->page_size,
 330                              DMA_PAGE_SIZE,
 331                              cache->page_size / DMA_PAGE_SIZE) < 0) {
 332                 pr_err("failed to download from 0x%x to 0x%x size 0x%x\n",
 333                        address,
 334                        entry * cache->page_size,
 335                        cache->page_size);
 336         }
 337
 338         cache->tags[entry].address = address;
 339         cache->tags[entry].flags |= CACHE_PAGE_PRESENT;
 340 }
 341
 342
 343 static void ps3vram_cache_flush(struct mtd_info *mtd)
 344 {
 345         struct ps3vram_priv *priv = mtd->priv;
 346         struct ps3vram_cache *cache = &priv->cache;
 347         int i;
 348
 349         dbg("FLUSH");
 350         for (i = 0; i < cache->page_count; i++) {
 351                 ps3vram_cache_evict(mtd, i);
 352                 cache->tags[i].flags = 0;
 353         }
 354 }
 355
 356 static unsigned int ps3vram_cache_match(struct mtd_info *mtd, loff_t address)
 357 {
 358         struct ps3vram_priv *priv = mtd->priv;
 359         struct ps3vram_cache *cache = &priv->cache;
 360         unsigned int base;
 361         unsigned int offset;
 362         int i;
 363         static int counter;
 364
 365         offset = (unsigned int) (address & (cache->page_size - 1));
 366         base = (unsigned int) (address - offset);
 367
 368         /* fully associative check */
 369         for (i = 0; i < cache->page_count; i++) {
 370                 if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) &&
 371                     cache->tags[i].address == base) {
 372                         dbg("found entry %d : 0x%08x",
 373                             i, cache->tags[i].address);
 374                         return i;
 375                 }
 376         }
 377
 378         /* choose a random entry */
 379         i = (jiffies + (counter++)) % cache->page_count;
 380         dbg("using cache entry %d", i);
 381
 382         ps3vram_cache_evict(mtd, i);
 383         ps3vram_cache_load(mtd, i, base);
 384
 385         return i;
 386 }
 387
 388 static int ps3vram_cache_init(struct mtd_info *mtd)
 389 {
 390         struct ps3vram_priv *priv = mtd->priv;
 391
 392         pr_info("creating cache: %d entries, %d bytes pages\n",
 393                CACHE_PAGE_COUNT, CACHE_PAGE_SIZE);
 394
 395         priv->cache.page_count = CACHE_PAGE_COUNT;
 396         priv->cache.page_size = CACHE_PAGE_SIZE;
 397         priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) *
 398                                    CACHE_PAGE_COUNT, GFP_KERNEL);
 399         if (priv->cache.tags == NULL) {
 400                 pr_err("could not allocate cache tags\n");
 401                 return -ENOMEM;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static void ps3vram_cache_cleanup(struct mtd_info *mtd)
 408 {
 409         struct ps3vram_priv *priv = mtd->priv;
 410
 411         ps3vram_cache_flush(mtd);
 412         kfree(priv->cache.tags);
 413 }
 414
 415 static int ps3vram_erase(struct mtd_info *mtd, struct erase_info *instr)
 416 {
 417         struct ps3vram_priv *priv = mtd->priv;
 418
 419         if (instr->addr + instr->len > mtd->size)
 420                 return -EINVAL;
 421
 422         mutex_lock(&priv->lock);
 423
 424         ps3vram_cache_flush(mtd);
 425
 426         /* Set bytes to 0xFF */
 427         memset(priv->base + instr->addr, 0xFF, instr->len);
 428
 429         mutex_unlock(&priv->lock);
 430
 431         instr->state = MTD_ERASE_DONE;
 432         mtd_erase_callback(instr);
 433
 434         return 0;
 435 }
 436
 437
 438 static int ps3vram_read(struct mtd_info *mtd, loff_t from, size_t len,
 439                         size_t *retlen, u_char *buf)
 440 {
 441         struct ps3vram_priv *priv = mtd->priv;
 442         unsigned int cached, count;
 443
 444         dbg("from = 0x%08x len = 0x%zx", (unsigned int) from, len);
 445
 446         if (from >= mtd->size)
 447                 return -EINVAL;
 448
 449         if (len > mtd->size - from)
 450                 len = mtd->size - from;
 451
 452         /* Copy from vram to buf */
 453         count = len;
 454         while (count) {
 455                 unsigned int offset, avail;
 456                 unsigned int entry;
 457
 458                 offset = (unsigned int) (from & (priv->cache.page_size - 1));
 459                 avail  = priv->cache.page_size - offset;
 460
 461                 mutex_lock(&priv->lock);
 462
 463                 entry = ps3vram_cache_match(mtd, from);
 464                 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
 465
 466                 dbg("from=%08x cached=%08x offset=%08x avail=%08x count=%08x",
 467                     (unsigned)from, cached, offset, avail, count);
 468
 469                 if (avail > count)
 470                         avail = count;
 471                 memcpy(buf, priv->xdr_buf + cached, avail);
 472
 473                 mutex_unlock(&priv->lock);
 474
 475                 buf += avail;
 476                 count -= avail;
 477                 from += avail;
 478         }
 479
 480         *retlen = len;
 481         return 0;
 482 }
 483
 484 static int ps3vram_write(struct mtd_info *mtd, loff_t to, size_t len,
 485                          size_t *retlen, const u_char *buf)
 486 {
 487         struct ps3vram_priv *priv = mtd->priv;
 488         unsigned int cached, count;
 489
 490         if (to >= mtd->size)
 491                 return -EINVAL;
 492
 493         if (len > mtd->size - to)
 494                 len = mtd->size - to;
 495
 496         /* Copy from buf to vram */
 497         count = len;
 498         while (count) {
 499                 unsigned int offset, avail;
 500                 unsigned int entry;
 501
 502                 offset = (unsigned int) (to & (priv->cache.page_size - 1));
 503                 avail  = priv->cache.page_size - offset;
 504
 505                 mutex_lock(&priv->lock);
 506
 507                 entry = ps3vram_cache_match(mtd, to);
 508                 cached = CACHE_OFFSET + entry * priv->cache.page_size + offset;
 509
 510                 dbg("to=%08x cached=%08x offset=%08x avail=%08x count=%08x",
 511                     (unsigned) to, cached, offset, avail, count);
 512
 513                 if (avail > count)
 514                         avail = count;
 515                 memcpy(priv->xdr_buf + cached, buf, avail);
 516
 517                 priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY;
 518
 519                 mutex_unlock(&priv->lock);
 520
 521                 buf += avail;
 522                 count -= avail;
 523                 to += avail;
 524         }
 525
 526         *retlen = len;
 527         return 0;
 528 }
 529
 530 static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev)
 531 {
 532         struct ps3vram_priv *priv;
 533         uint64_t status;
 534         uint64_t ddr_lpar, ctrl_lpar, info_lpar, reports_lpar;
 535         int64_t ddr_size;
 536         uint64_t reports_size;
 537         int ret = -ENOMEM;
 538         char *rest;
 539
 540         ret = -EIO;
 541         ps3vram_mtd.priv = kzalloc(sizeof(struct ps3vram_priv), GFP_KERNEL);
 542         if (!ps3vram_mtd.priv)
 543                 goto out;
 544         priv = ps3vram_mtd.priv;
 545
 546         mutex_init(&priv->lock);
 547
 548         /* Allocate XDR buffer (1MiB aligned) */
 549         priv->xdr_buf = (uint8_t *) __get_free_pages(GFP_KERNEL,
 550                                                      get_order(XDR_BUF_SIZE));
 551         if (priv->xdr_buf == NULL) {
 552                 pr_err("ps3vram: could not allocate XDR buffer\n");
 553                 ret = -ENOMEM;
 554                 goto out_free_priv;
 555         }
 556
 557         /* Put FIFO at begginning of XDR buffer */
 558         priv->fifo_base = (uint32_t *) (priv->xdr_buf + FIFO_OFFSET);
 559         priv->fifo_ptr = priv->fifo_base;
 560
 561         /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */
 562         if (ps3_open_hv_device(dev)) {
 563                 pr_err("ps3vram: ps3_open_hv_device failed\n");
 564                 ret = -EAGAIN;
 565                 goto out_close_gpu;
 566         }
 567
 568         /* Request memory */
 569         status = -1;
 570         ddr_size = memparse(size, &rest);
 571         if (*rest == '-')
 572                 ddr_size -= ps3fb_videomemory.size;
 573         ddr_size = ALIGN(ddr_size, 1024*1024);
 574         if (ddr_size <= 0) {
 575                 printk(KERN_ERR "ps3vram: specified size is too small\n");
 576                 ret = -EINVAL;
 577                 goto out_close_gpu;
 578         }
 579
 580         while (ddr_size > 0) {
 581                 status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0,
 582                                                  &priv->memory_handle,
 583                                                  &ddr_lpar);
 584                 if (status == 0)
 585                         break;
 586                 ddr_size -= 1024*1024;
 587         }
 588         if (status != 0 || ddr_size <= 0) {
 589                 pr_err("ps3vram: lv1_gpu_memory_allocate failed\n");
 590                 ret = -ENOMEM;
 591                 goto out_free_xdr_buf;
 592         }
 593         pr_info("ps3vram: allocated %u MiB of DDR memory\n",
 594                 (unsigned int) (ddr_size / 1024 / 1024));
 595
 596         /* Request context */
 597         status = lv1_gpu_context_allocate(priv->memory_handle,
 598                                           0,
 599                                           &priv->context_handle,
 600                                           &ctrl_lpar,
 601                                           &info_lpar,
 602                                           &reports_lpar,
 603                                           &reports_size);
 604         if (status) {
 605                 pr_err("ps3vram: lv1_gpu_context_allocate failed\n");
 606                 ret = -ENOMEM;
 607                 goto out_free_memory;
 608         }
 609
 610         /* Map XDR buffer to RSX */
 611         status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF,
 612                                        ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)),
 613                                        XDR_BUF_SIZE, 0);
 614         if (status) {
 615                 pr_err("ps3vram: lv1_gpu_context_iomap failed\n");
 616                 ret = -ENOMEM;
 617                 goto out_free_context;
 618         }
 619
 620         priv->base = ioremap(ddr_lpar, ddr_size);
 621         if (!priv->base) {
 622                 pr_err("ps3vram: ioremap failed\n");
 623                 ret = -ENOMEM;
 624                 goto out_free_context;
 625         }
 626
 627         priv->ctrl = ioremap(ctrl_lpar, 64 * 1024);
 628         if (!priv->ctrl) {
 629                 pr_err("ps3vram: ioremap failed\n");
 630                 ret = -ENOMEM;
 631                 goto out_unmap_vram;
 632         }
 633
 634         priv->reports = ioremap(reports_lpar, reports_size);
 635         if (!priv->reports) {
 636                 pr_err("ps3vram: ioremap failed\n");
 637                 ret = -ENOMEM;
 638                 goto out_unmap_ctrl;
 639         }
 640
 641         mutex_lock(&ps3_gpu_mutex);
 642         ps3vram_init_ring(&ps3vram_mtd);
 643         mutex_unlock(&ps3_gpu_mutex);
 644
 645         ps3vram_mtd.name = "ps3vram";
 646         ps3vram_mtd.size = ddr_size;
 647         ps3vram_mtd.flags = MTD_CAP_RAM;
 648         ps3vram_mtd.erase = ps3vram_erase;
 649         ps3vram_mtd.point = NULL;
 650         ps3vram_mtd.unpoint = NULL;
 651         ps3vram_mtd.read = ps3vram_read;
 652         ps3vram_mtd.write = ps3vram_write;
 653         ps3vram_mtd.owner = THIS_MODULE;
 654         ps3vram_mtd.type = MTD_RAM;
 655         ps3vram_mtd.erasesize = CACHE_PAGE_SIZE;
 656         ps3vram_mtd.writesize = 1;
 657
 658         ps3vram_bind(&ps3vram_mtd);
 659
 660         mutex_lock(&ps3_gpu_mutex);
 661         ret = ps3vram_wait_ring(&ps3vram_mtd, 100);
 662         mutex_unlock(&ps3_gpu_mutex);
 663         if (ret < 0) {
 664                 pr_err("failed to initialize channels\n");
 665                 ret = -ETIMEDOUT;
 666                 goto out_unmap_reports;
 667         }
 668
 669         ps3vram_cache_init(&ps3vram_mtd);
 670
 671         if (add_mtd_device(&ps3vram_mtd)) {
 672                 pr_err("ps3vram: failed to register device\n");
 673                 ret = -EAGAIN;
 674                 goto out_cache_cleanup;
 675         }
 676
 677         pr_info("ps3vram mtd device registered, %lu bytes\n", ddr_size);
 678         return 0;
 679
 680 out_cache_cleanup:
 681         ps3vram_cache_cleanup(&ps3vram_mtd);
 682 out_unmap_reports:
 683         iounmap(priv->reports);
 684 out_unmap_ctrl:
 685         iounmap(priv->ctrl);
 686 out_unmap_vram:
 687         iounmap(priv->base);
 688 out_free_context:
 689         lv1_gpu_context_free(priv->context_handle);
 690 out_free_memory:
 691         lv1_gpu_memory_free(priv->memory_handle);
 692 out_close_gpu:
 693         ps3_close_hv_device(dev);
 694 out_free_xdr_buf:
 695         free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
 696 out_free_priv:
 697         kfree(ps3vram_mtd.priv);
 698         ps3vram_mtd.priv = NULL;
 699 out:
 700         return ret;
 701 }
 702
 703 static int ps3vram_shutdown(struct ps3_system_bus_device *dev)
 704 {
 705         struct ps3vram_priv *priv;
 706
 707         priv = ps3vram_mtd.priv;
 708
 709         del_mtd_device(&ps3vram_mtd);
 710         ps3vram_cache_cleanup(&ps3vram_mtd);
 711         iounmap(priv->reports);
 712         iounmap(priv->ctrl);
 713         iounmap(priv->base);
 714         lv1_gpu_context_free(priv->context_handle);
 715         lv1_gpu_memory_free(priv->memory_handle);
 716         ps3_close_hv_device(dev);
 717         free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE));
 718         kfree(priv);
 719         return 0;
 720 }
 721
 722 static struct ps3_system_bus_driver ps3vram_driver = {
 723         .match_id       = PS3_MATCH_ID_GPU,
 724         .match_sub_id   = PS3_MATCH_SUB_ID_GPU_RAMDISK,
 725         .core.name      = DEVICE_NAME,
 726         .core.owner     = THIS_MODULE,
 727         .probe          = ps3vram_probe,
 728         .remove         = ps3vram_shutdown,
 729         .shutdown       = ps3vram_shutdown,
 730 };
 731
 732 static int __init ps3vram_init(void)
 733 {
 734         return ps3_system_bus_driver_register(&ps3vram_driver);
 735 }
 736
 737 static void __exit ps3vram_exit(void)
 738 {
 739         ps3_system_bus_driver_unregister(&ps3vram_driver);
 740 }
 741
 742 module_init(ps3vram_init);
 743 module_exit(ps3vram_exit);
 744
 745 MODULE_LICENSE("GPL");
 746 MODULE_AUTHOR("Jim Paris <jim@jtan.com>");
 747 MODULE_DESCRIPTION("MTD driver for PS3 video RAM");
 748 MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK);