1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2011
4 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
5 * Aaron <leafy.myeh@allwinnertech.com>
7 * MMC driver for allwinner sunxi platform.
19 #include <asm/arch/clock.h>
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/mmc.h>
23 #include <asm-generic/gpio.h>
26 struct sunxi_mmc_variant {
31 struct sunxi_mmc_plat {
32 struct mmc_config cfg;
36 struct sunxi_mmc_priv {
40 struct gpio_desc cd_gpio; /* Change Detect GPIO */
41 int cd_inverted; /* Inverted Card Detect */
42 struct sunxi_mmc *reg;
43 struct mmc_config cfg;
45 const struct sunxi_mmc_variant *variant;
49 #if !CONFIG_IS_ENABLED(DM_MMC)
50 /* support 4 mmc hosts */
51 struct sunxi_mmc_priv mmc_host[4];
53 static int sunxi_mmc_getcd_gpio(int sdc_no)
56 case 0: return sunxi_name_to_gpio(CONFIG_MMC0_CD_PIN);
57 case 1: return sunxi_name_to_gpio(CONFIG_MMC1_CD_PIN);
58 case 2: return sunxi_name_to_gpio(CONFIG_MMC2_CD_PIN);
59 case 3: return sunxi_name_to_gpio(CONFIG_MMC3_CD_PIN);
64 static int mmc_resource_init(int sdc_no)
66 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
67 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
70 debug("init mmc %d resource\n", sdc_no);
74 priv->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
75 priv->mclkreg = &ccm->sd0_clk_cfg;
78 priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
79 priv->mclkreg = &ccm->sd1_clk_cfg;
82 priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
83 priv->mclkreg = &ccm->sd2_clk_cfg;
85 #ifdef SUNXI_MMC3_BASE
87 priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
88 priv->mclkreg = &ccm->sd3_clk_cfg;
92 printf("Wrong mmc number %d\n", sdc_no);
95 priv->mmc_no = sdc_no;
97 cd_pin = sunxi_mmc_getcd_gpio(sdc_no);
99 ret = gpio_request(cd_pin, "mmc_cd");
101 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
102 ret = gpio_direction_input(cd_pin);
110 static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
112 unsigned int pll, pll_hz, div, n, oclk_dly, sclk_dly;
113 bool new_mode = true;
114 bool calibrate = false;
117 if (!IS_ENABLED(CONFIG_MMC_SUNXI_HAS_NEW_MODE))
120 /* A83T support new mode only on eMMC */
121 if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T) && priv->mmc_no != 2)
124 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
128 if (hz <= 24000000) {
129 pll = CCM_MMC_CTRL_OSCM24;
132 #ifdef CONFIG_MACH_SUN9I
133 pll = CCM_MMC_CTRL_PLL_PERIPH0;
134 pll_hz = clock_get_pll4_periph0();
135 #elif defined(CONFIG_MACH_SUN50I_H6)
136 pll = CCM_MMC_CTRL_PLL6X2;
137 pll_hz = clock_get_pll6() * 2;
139 pll = CCM_MMC_CTRL_PLL6;
140 pll_hz = clock_get_pll6();
155 printf("mmc %u error cannot set clock to %u\n", priv->mmc_no,
160 /* determine delays */
164 } else if (hz <= 25000000) {
167 #ifdef CONFIG_MACH_SUN9I
168 } else if (hz <= 52000000) {
176 } else if (hz <= 52000000) {
187 #ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
188 #ifdef CONFIG_MMC_SUNXI_HAS_MODE_SWITCH
189 val = CCM_MMC_CTRL_MODE_SEL_NEW;
191 setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
193 } else if (!calibrate) {
195 * Use hardcoded delay values if controller doesn't support
198 val = CCM_MMC_CTRL_OCLK_DLY(oclk_dly) |
199 CCM_MMC_CTRL_SCLK_DLY(sclk_dly);
202 writel(CCM_MMC_CTRL_ENABLE| pll | CCM_MMC_CTRL_N(n) |
203 CCM_MMC_CTRL_M(div) | val, priv->mclkreg);
205 debug("mmc %u set mod-clk req %u parent %u n %u m %u rate %u\n",
206 priv->mmc_no, hz, pll_hz, 1u << n, div, pll_hz / (1u << n) / div);
211 static int mmc_update_clk(struct sunxi_mmc_priv *priv)
214 unsigned timeout_msecs = 2000;
215 unsigned long start = get_timer(0);
217 cmd = SUNXI_MMC_CMD_START |
218 SUNXI_MMC_CMD_UPCLK_ONLY |
219 SUNXI_MMC_CMD_WAIT_PRE_OVER;
221 writel(cmd, &priv->reg->cmd);
222 while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
223 if (get_timer(start) > timeout_msecs)
227 /* clock update sets various irq status bits, clear these */
228 writel(readl(&priv->reg->rint), &priv->reg->rint);
233 static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc)
235 unsigned rval = readl(&priv->reg->clkcr);
238 rval &= ~SUNXI_MMC_CLK_ENABLE;
239 writel(rval, &priv->reg->clkcr);
240 if (mmc_update_clk(priv))
243 /* Set mod_clk to new rate */
244 if (mmc_set_mod_clk(priv, mmc->clock))
247 /* Clear internal divider */
248 rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK;
249 writel(rval, &priv->reg->clkcr);
251 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN50I_H6)
252 /* A64 supports calibration of delays on MMC controller and we
253 * have to set delay of zero before starting calibration.
254 * Allwinner BSP driver sets a delay only in the case of
255 * using HS400 which is not supported by mainline U-Boot or
256 * Linux at the moment
258 writel(SUNXI_MMC_CAL_DL_SW_EN, &priv->reg->samp_dl);
261 /* Re-enable Clock */
262 rval |= SUNXI_MMC_CLK_ENABLE;
263 writel(rval, &priv->reg->clkcr);
264 if (mmc_update_clk(priv))
270 static int sunxi_mmc_set_ios_common(struct sunxi_mmc_priv *priv,
273 debug("set ios: bus_width: %x, clock: %d\n",
274 mmc->bus_width, mmc->clock);
276 /* Change clock first */
277 if (mmc->clock && mmc_config_clock(priv, mmc) != 0) {
282 /* Change bus width */
283 if (mmc->bus_width == 8)
284 writel(0x2, &priv->reg->width);
285 else if (mmc->bus_width == 4)
286 writel(0x1, &priv->reg->width);
288 writel(0x0, &priv->reg->width);
293 #if !CONFIG_IS_ENABLED(DM_MMC)
294 static int sunxi_mmc_core_init(struct mmc *mmc)
296 struct sunxi_mmc_priv *priv = mmc->priv;
298 /* Reset controller */
299 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
306 static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
307 struct mmc_data *data)
309 const int reading = !!(data->flags & MMC_DATA_READ);
310 const uint32_t status_bit = reading ? SUNXI_MMC_STATUS_FIFO_EMPTY :
311 SUNXI_MMC_STATUS_FIFO_FULL;
313 unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
314 unsigned byte_cnt = data->blocksize * data->blocks;
315 unsigned timeout_msecs = byte_cnt >> 8;
318 if (timeout_msecs < 2000)
319 timeout_msecs = 2000;
321 /* Always read / write data through the CPU */
322 setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
324 start = get_timer(0);
326 for (i = 0; i < (byte_cnt >> 2); i++) {
327 while (readl(&priv->reg->status) & status_bit) {
328 if (get_timer(start) > timeout_msecs)
333 buff[i] = readl(&priv->reg->fifo);
335 writel(buff[i], &priv->reg->fifo);
341 static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
342 uint timeout_msecs, uint done_bit, const char *what)
345 unsigned long start = get_timer(0);
348 status = readl(&priv->reg->rint);
349 if ((get_timer(start) > timeout_msecs) ||
350 (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
351 debug("%s timeout %x\n", what,
352 status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
355 } while (!(status & done_bit));
360 static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
361 struct mmc *mmc, struct mmc_cmd *cmd,
362 struct mmc_data *data)
364 unsigned int cmdval = SUNXI_MMC_CMD_START;
365 unsigned int timeout_msecs;
367 unsigned int status = 0;
368 unsigned int bytecnt = 0;
372 if (cmd->resp_type & MMC_RSP_BUSY)
373 debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
374 if (cmd->cmdidx == 12)
378 cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ;
379 if (cmd->resp_type & MMC_RSP_PRESENT)
380 cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE;
381 if (cmd->resp_type & MMC_RSP_136)
382 cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE;
383 if (cmd->resp_type & MMC_RSP_CRC)
384 cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC;
387 if ((u32)(long)data->dest & 0x3) {
392 cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER;
393 if (data->flags & MMC_DATA_WRITE)
394 cmdval |= SUNXI_MMC_CMD_WRITE;
395 if (data->blocks > 1)
396 cmdval |= SUNXI_MMC_CMD_AUTO_STOP;
397 writel(data->blocksize, &priv->reg->blksz);
398 writel(data->blocks * data->blocksize, &priv->reg->bytecnt);
401 debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", priv->mmc_no,
402 cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
403 writel(cmd->cmdarg, &priv->reg->arg);
406 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
409 * transfer data and check status
410 * STATREG[2] : FIFO empty
411 * STATREG[3] : FIFO full
416 bytecnt = data->blocksize * data->blocks;
417 debug("trans data %d bytes\n", bytecnt);
418 writel(cmdval | cmd->cmdidx, &priv->reg->cmd);
419 ret = mmc_trans_data_by_cpu(priv, mmc, data);
421 error = readl(&priv->reg->rint) &
422 SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT;
428 error = mmc_rint_wait(priv, mmc, 1000, SUNXI_MMC_RINT_COMMAND_DONE,
435 debug("cacl timeout %x msec\n", timeout_msecs);
436 error = mmc_rint_wait(priv, mmc, timeout_msecs,
438 SUNXI_MMC_RINT_AUTO_COMMAND_DONE :
439 SUNXI_MMC_RINT_DATA_OVER,
445 if (cmd->resp_type & MMC_RSP_BUSY) {
446 unsigned long start = get_timer(0);
447 timeout_msecs = 2000;
450 status = readl(&priv->reg->status);
451 if (get_timer(start) > timeout_msecs) {
452 debug("busy timeout\n");
456 } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
459 if (cmd->resp_type & MMC_RSP_136) {
460 cmd->response[0] = readl(&priv->reg->resp3);
461 cmd->response[1] = readl(&priv->reg->resp2);
462 cmd->response[2] = readl(&priv->reg->resp1);
463 cmd->response[3] = readl(&priv->reg->resp0);
464 debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
465 cmd->response[3], cmd->response[2],
466 cmd->response[1], cmd->response[0]);
468 cmd->response[0] = readl(&priv->reg->resp0);
469 debug("mmc resp 0x%08x\n", cmd->response[0]);
473 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
474 mmc_update_clk(priv);
476 writel(0xffffffff, &priv->reg->rint);
477 writel(readl(&priv->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET,
483 #if !CONFIG_IS_ENABLED(DM_MMC)
484 static int sunxi_mmc_set_ios_legacy(struct mmc *mmc)
486 struct sunxi_mmc_priv *priv = mmc->priv;
488 return sunxi_mmc_set_ios_common(priv, mmc);
491 static int sunxi_mmc_send_cmd_legacy(struct mmc *mmc, struct mmc_cmd *cmd,
492 struct mmc_data *data)
494 struct sunxi_mmc_priv *priv = mmc->priv;
496 return sunxi_mmc_send_cmd_common(priv, mmc, cmd, data);
499 static int sunxi_mmc_getcd_legacy(struct mmc *mmc)
501 struct sunxi_mmc_priv *priv = mmc->priv;
504 cd_pin = sunxi_mmc_getcd_gpio(priv->mmc_no);
508 return !gpio_get_value(cd_pin);
511 static const struct mmc_ops sunxi_mmc_ops = {
512 .send_cmd = sunxi_mmc_send_cmd_legacy,
513 .set_ios = sunxi_mmc_set_ios_legacy,
514 .init = sunxi_mmc_core_init,
515 .getcd = sunxi_mmc_getcd_legacy,
518 struct mmc *sunxi_mmc_init(int sdc_no)
520 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
521 struct sunxi_mmc_priv *priv = &mmc_host[sdc_no];
522 struct mmc_config *cfg = &priv->cfg;
525 memset(priv, '\0', sizeof(struct sunxi_mmc_priv));
527 cfg->name = "SUNXI SD/MMC";
528 cfg->ops = &sunxi_mmc_ops;
530 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
531 cfg->host_caps = MMC_MODE_4BIT;
532 #if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I_H6)
534 cfg->host_caps = MMC_MODE_8BIT;
536 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
537 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
540 cfg->f_max = 52000000;
542 if (mmc_resource_init(sdc_no) != 0)
545 /* config ahb clock */
546 debug("init mmc %d clock and io\n", sdc_no);
547 #if !defined(CONFIG_MACH_SUN50I_H6)
548 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
550 #ifdef CONFIG_SUNXI_GEN_SUN6I
552 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
554 #if defined(CONFIG_MACH_SUN9I)
555 /* sun9i has a mmc-common module, also set the gate and reset there */
556 writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
557 SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
559 #else /* CONFIG_MACH_SUN50I_H6 */
560 setbits_le32(&ccm->sd_gate_reset, 1 << sdc_no);
562 setbits_le32(&ccm->sd_gate_reset, 1 << (RESET_SHIFT + sdc_no));
564 ret = mmc_set_mod_clk(priv, 24000000);
568 return mmc_create(cfg, priv);
572 static int sunxi_mmc_set_ios(struct udevice *dev)
574 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
575 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
577 return sunxi_mmc_set_ios_common(priv, &plat->mmc);
580 static int sunxi_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
581 struct mmc_data *data)
583 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
584 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
586 return sunxi_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
589 static int sunxi_mmc_getcd(struct udevice *dev)
591 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
593 if (dm_gpio_is_valid(&priv->cd_gpio)) {
594 int cd_state = dm_gpio_get_value(&priv->cd_gpio);
596 return cd_state ^ priv->cd_inverted;
601 static const struct dm_mmc_ops sunxi_mmc_ops = {
602 .send_cmd = sunxi_mmc_send_cmd,
603 .set_ios = sunxi_mmc_set_ios,
604 .get_cd = sunxi_mmc_getcd,
607 static int sunxi_mmc_probe(struct udevice *dev)
609 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
610 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
611 struct sunxi_mmc_priv *priv = dev_get_priv(dev);
612 struct reset_ctl_bulk reset_bulk;
614 struct mmc_config *cfg = &plat->cfg;
615 struct ofnode_phandle_args args;
619 cfg->name = dev->name;
620 bus_width = dev_read_u32_default(dev, "bus-width", 1);
622 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
625 cfg->host_caps |= MMC_MODE_8BIT;
627 cfg->host_caps |= MMC_MODE_4BIT;
628 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
629 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
632 cfg->f_max = 52000000;
634 priv->reg = (void *)dev_read_addr(dev);
636 (const struct sunxi_mmc_variant *)dev_get_driver_data(dev);
638 /* We don't have a sunxi clock driver so find the clock address here */
639 ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
643 ccu_reg = (u32 *)ofnode_get_addr(args.node);
645 priv->mmc_no = ((uintptr_t)priv->reg - SUNXI_MMC0_BASE) / 0x1000;
646 priv->mclkreg = (void *)ccu_reg +
647 (priv->variant->mclk_offset + (priv->mmc_no * 4));
649 ret = clk_get_by_name(dev, "ahb", &gate_clk);
651 clk_enable(&gate_clk);
653 ret = reset_get_bulk(dev, &reset_bulk);
655 reset_deassert_bulk(&reset_bulk);
657 ret = mmc_set_mod_clk(priv, 24000000);
661 /* This GPIO is optional */
662 if (!dev_read_bool(dev, "non-removable") &&
663 !gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
665 int cd_pin = gpio_get_number(&priv->cd_gpio);
667 sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP);
670 /* Check if card detect is inverted */
671 priv->cd_inverted = dev_read_bool(dev, "cd-inverted");
673 upriv->mmc = &plat->mmc;
675 /* Reset controller */
676 writel(SUNXI_MMC_GCTRL_RESET, &priv->reg->gctrl);
682 static int sunxi_mmc_bind(struct udevice *dev)
684 struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
686 return mmc_bind(dev, &plat->mmc, &plat->cfg);
689 static const struct sunxi_mmc_variant sun4i_a10_variant = {
693 static const struct sunxi_mmc_variant sun9i_a80_variant = {
694 .mclk_offset = 0x410,
697 static const struct sunxi_mmc_variant sun50i_h6_variant = {
698 .mclk_offset = 0x830,
701 static const struct udevice_id sunxi_mmc_ids[] = {
703 .compatible = "allwinner,sun4i-a10-mmc",
704 .data = (ulong)&sun4i_a10_variant,
707 .compatible = "allwinner,sun5i-a13-mmc",
708 .data = (ulong)&sun4i_a10_variant,
711 .compatible = "allwinner,sun7i-a20-mmc",
712 .data = (ulong)&sun4i_a10_variant,
715 .compatible = "allwinner,sun8i-a83t-emmc",
716 .data = (ulong)&sun4i_a10_variant,
719 .compatible = "allwinner,sun9i-a80-mmc",
720 .data = (ulong)&sun9i_a80_variant,
723 .compatible = "allwinner,sun50i-a64-mmc",
724 .data = (ulong)&sun4i_a10_variant,
727 .compatible = "allwinner,sun50i-a64-emmc",
728 .data = (ulong)&sun4i_a10_variant,
731 .compatible = "allwinner,sun50i-h6-mmc",
732 .data = (ulong)&sun50i_h6_variant,
735 .compatible = "allwinner,sun50i-h6-emmc",
736 .data = (ulong)&sun50i_h6_variant,
741 U_BOOT_DRIVER(sunxi_mmc_drv) = {
744 .of_match = sunxi_mmc_ids,
745 .bind = sunxi_mmc_bind,
746 .probe = sunxi_mmc_probe,
747 .ops = &sunxi_mmc_ops,
748 .platdata_auto_alloc_size = sizeof(struct sunxi_mmc_plat),
749 .priv_auto_alloc_size = sizeof(struct sunxi_mmc_priv),