1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2011, Marvell Semiconductor Inc.
4 * Lei Wen <leiwen@marvell.com>
6 * Back ported to the 8xx platform (from the 8260 platform) by
7 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
19 #include <asm/cache.h>
20 #include <linux/dma-mapping.h>
23 static void sdhci_reset(struct sdhci_host *host, u8 mask)
25 unsigned long timeout;
29 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
30 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
32 printf("%s: Reset 0x%x never completed.\n",
41 static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
44 if (cmd->resp_type & MMC_RSP_136) {
45 /* CRC is stripped so we need to do some shifting. */
46 for (i = 0; i < 4; i++) {
47 cmd->response[i] = sdhci_readl(host,
48 SDHCI_RESPONSE + (3-i)*4) << 8;
50 cmd->response[i] |= sdhci_readb(host,
51 SDHCI_RESPONSE + (3-i)*4-1);
54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
58 static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
62 for (i = 0; i < data->blocksize; i += 4) {
63 offs = data->dest + i;
64 if (data->flags == MMC_DATA_READ)
65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
67 sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
71 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
72 static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
75 struct sdhci_adma_desc *desc;
78 desc = &host->adma_desc_table[host->desc_slot];
80 attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
84 attr |= ADMA_DESC_ATTR_END;
89 desc->addr_lo = lower_32_bits(dma_addr);
90 #ifdef CONFIG_DMA_ADDR_T_64BIT
91 desc->addr_hi = upper_32_bits(dma_addr);
95 static void sdhci_prepare_adma_table(struct sdhci_host *host,
96 struct mmc_data *data)
98 uint trans_bytes = data->blocksize * data->blocks;
99 uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
101 dma_addr_t dma_addr = host->start_addr;
106 sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
107 dma_addr += ADMA_MAX_LEN;
108 trans_bytes -= ADMA_MAX_LEN;
111 sdhci_adma_desc(host, dma_addr, trans_bytes, true);
113 flush_cache((dma_addr_t)host->adma_desc_table,
114 ROUND(desc_count * sizeof(struct sdhci_adma_desc),
117 #elif defined(CONFIG_MMC_SDHCI_SDMA)
118 static void sdhci_prepare_adma_table(struct sdhci_host *host,
119 struct mmc_data *data)
122 #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
123 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
124 int *is_aligned, int trans_bytes)
129 if (data->flags == MMC_DATA_READ)
132 buf = (void *)data->src;
134 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
135 ctrl &= ~SDHCI_CTRL_DMA_MASK;
136 if (host->flags & USE_ADMA64)
137 ctrl |= SDHCI_CTRL_ADMA64;
138 else if (host->flags & USE_ADMA)
139 ctrl |= SDHCI_CTRL_ADMA32;
140 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
142 if (host->flags & USE_SDMA &&
143 (host->force_align_buffer ||
144 (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
145 ((unsigned long)buf & 0x7) != 0x0))) {
147 if (data->flags != MMC_DATA_READ)
148 memcpy(host->align_buffer, buf, trans_bytes);
149 buf = host->align_buffer;
152 host->start_addr = dma_map_single(buf, trans_bytes,
153 mmc_get_dma_dir(data));
155 if (host->flags & USE_SDMA) {
156 sdhci_writel(host, phys_to_bus((ulong)host->start_addr),
158 } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
159 sdhci_prepare_adma_table(host, data);
161 sdhci_writel(host, lower_32_bits(host->adma_addr),
163 if (host->flags & USE_ADMA64)
164 sdhci_writel(host, upper_32_bits(host->adma_addr),
165 SDHCI_ADMA_ADDRESS_HI);
169 static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
170 int *is_aligned, int trans_bytes)
173 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
175 dma_addr_t start_addr = host->start_addr;
176 unsigned int stat, rdy, mask, timeout, block = 0;
177 bool transfer_done = false;
180 rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
181 mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
183 stat = sdhci_readl(host, SDHCI_INT_STATUS);
184 if (stat & SDHCI_INT_ERROR) {
185 pr_debug("%s: Error detected in status(0x%X)!\n",
189 if (!transfer_done && (stat & rdy)) {
190 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
192 sdhci_writel(host, rdy, SDHCI_INT_STATUS);
193 sdhci_transfer_pio(host, data);
194 data->dest += data->blocksize;
195 if (++block >= data->blocks) {
196 /* Keep looping until the SDHCI_INT_DATA_END is
197 * cleared, even if we finished sending all the
200 transfer_done = true;
204 if ((host->flags & USE_DMA) && !transfer_done &&
205 (stat & SDHCI_INT_DMA_END)) {
206 sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
207 if (host->flags & USE_SDMA) {
209 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
210 start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
211 sdhci_writel(host, phys_to_bus((ulong)start_addr),
218 printf("%s: Transfer data timeout\n", __func__);
221 } while (!(stat & SDHCI_INT_DATA_END));
223 dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
224 mmc_get_dma_dir(data));
230 * No command will be sent by driver if card is busy, so driver must wait
231 * for card ready state.
232 * Every time when card is busy after timeout then (last) timeout value will be
233 * increased twice but only if it doesn't exceed global defined maximum.
234 * Each function call will use last timeout value.
236 #define SDHCI_CMD_MAX_TIMEOUT 3200
237 #define SDHCI_CMD_DEFAULT_TIMEOUT 100
238 #define SDHCI_READ_STATUS_TIMEOUT 1000
241 static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
242 struct mmc_data *data)
244 struct mmc *mmc = mmc_get_mmc_dev(dev);
247 static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
248 struct mmc_data *data)
251 struct sdhci_host *host = mmc->priv;
252 unsigned int stat = 0;
254 int trans_bytes = 0, is_aligned = 1;
255 u32 mask, flags, mode;
256 unsigned int time = 0;
257 int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
258 ulong start = get_timer(0);
260 host->start_addr = 0;
261 /* Timeout unit - ms */
262 static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
264 mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
266 /* We shouldn't wait for data inihibit for stop commands, even
267 though they might use busy signaling */
268 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
269 ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
270 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
271 mask &= ~SDHCI_DATA_INHIBIT;
273 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
274 if (time >= cmd_timeout) {
275 printf("%s: MMC: %d busy ", __func__, mmc_dev);
276 if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
277 cmd_timeout += cmd_timeout;
278 printf("timeout increasing to: %u ms.\n",
289 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
291 mask = SDHCI_INT_RESPONSE;
292 if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
293 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
294 mask = SDHCI_INT_DATA_AVAIL;
296 if (!(cmd->resp_type & MMC_RSP_PRESENT))
297 flags = SDHCI_CMD_RESP_NONE;
298 else if (cmd->resp_type & MMC_RSP_136)
299 flags = SDHCI_CMD_RESP_LONG;
300 else if (cmd->resp_type & MMC_RSP_BUSY) {
301 flags = SDHCI_CMD_RESP_SHORT_BUSY;
303 mask |= SDHCI_INT_DATA_END;
305 flags = SDHCI_CMD_RESP_SHORT;
307 if (cmd->resp_type & MMC_RSP_CRC)
308 flags |= SDHCI_CMD_CRC;
309 if (cmd->resp_type & MMC_RSP_OPCODE)
310 flags |= SDHCI_CMD_INDEX;
311 if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
312 cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
313 flags |= SDHCI_CMD_DATA;
315 /* Set Transfer mode regarding to data flag */
317 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
318 mode = SDHCI_TRNS_BLK_CNT_EN;
319 trans_bytes = data->blocks * data->blocksize;
320 if (data->blocks > 1)
321 mode |= SDHCI_TRNS_MULTI;
323 if (data->flags == MMC_DATA_READ)
324 mode |= SDHCI_TRNS_READ;
326 if (host->flags & USE_DMA) {
327 mode |= SDHCI_TRNS_DMA;
328 sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
331 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
334 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
335 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
336 } else if (cmd->resp_type & MMC_RSP_BUSY) {
337 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
340 sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
341 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
342 start = get_timer(0);
344 stat = sdhci_readl(host, SDHCI_INT_STATUS);
345 if (stat & SDHCI_INT_ERROR)
348 if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
349 if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
352 printf("%s: Timeout for status update!\n",
357 } while ((stat & mask) != mask);
359 if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
360 sdhci_cmd_done(host, cmd);
361 sdhci_writel(host, mask, SDHCI_INT_STATUS);
366 ret = sdhci_transfer_data(host, data);
368 if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
371 stat = sdhci_readl(host, SDHCI_INT_STATUS);
372 sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
374 if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
375 !is_aligned && (data->flags == MMC_DATA_READ))
376 memcpy(data->dest, host->align_buffer, trans_bytes);
380 sdhci_reset(host, SDHCI_RESET_CMD);
381 sdhci_reset(host, SDHCI_RESET_DATA);
382 if (stat & SDHCI_INT_TIMEOUT)
388 #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
389 static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
392 struct mmc *mmc = mmc_get_mmc_dev(dev);
393 struct sdhci_host *host = mmc->priv;
395 debug("%s\n", __func__);
397 if (host->ops && host->ops->platform_execute_tuning) {
398 err = host->ops->platform_execute_tuning(mmc, opcode);
406 int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
408 struct sdhci_host *host = mmc->priv;
409 unsigned int div, clk = 0, timeout;
413 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
414 (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
416 printf("%s: Timeout to wait cmd & data inhibit\n",
425 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
430 if (host->ops && host->ops->set_delay)
431 host->ops->set_delay(host);
433 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
435 * Check if the Host Controller supports Programmable Clock
439 for (div = 1; div <= 1024; div++) {
440 if ((host->max_clk / div) <= clock)
445 * Set Programmable Clock Mode in the Clock
448 clk = SDHCI_PROG_CLOCK_MODE;
451 /* Version 3.00 divisors must be a multiple of 2. */
452 if (host->max_clk <= clock) {
456 div < SDHCI_MAX_DIV_SPEC_300;
458 if ((host->max_clk / div) <= clock)
465 /* Version 2.00 divisors must be a power of 2. */
466 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
467 if ((host->max_clk / div) <= clock)
473 if (host->ops && host->ops->set_clock)
474 host->ops->set_clock(host, div);
476 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
477 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
478 << SDHCI_DIVIDER_HI_SHIFT;
479 clk |= SDHCI_CLOCK_INT_EN;
480 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
484 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
485 & SDHCI_CLOCK_INT_STABLE)) {
487 printf("%s: Internal clock never stabilised.\n",
495 clk |= SDHCI_CLOCK_CARD_EN;
496 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
500 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
504 if (power != (unsigned short)-1) {
505 switch (1 << power) {
506 case MMC_VDD_165_195:
507 pwr = SDHCI_POWER_180;
511 pwr = SDHCI_POWER_300;
515 pwr = SDHCI_POWER_330;
521 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
525 pwr |= SDHCI_POWER_ON;
527 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
530 void sdhci_set_uhs_timing(struct sdhci_host *host)
532 struct mmc *mmc = host->mmc;
535 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
536 reg &= ~SDHCI_CTRL_UHS_MASK;
538 switch (mmc->selected_mode) {
541 reg |= SDHCI_CTRL_UHS_SDR50;
545 reg |= SDHCI_CTRL_UHS_DDR50;
549 reg |= SDHCI_CTRL_UHS_SDR104;
552 reg |= SDHCI_CTRL_UHS_SDR12;
555 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
559 static int sdhci_set_ios(struct udevice *dev)
561 struct mmc *mmc = mmc_get_mmc_dev(dev);
563 static int sdhci_set_ios(struct mmc *mmc)
567 struct sdhci_host *host = mmc->priv;
569 if (host->ops && host->ops->set_control_reg)
570 host->ops->set_control_reg(host);
572 if (mmc->clock != host->clock)
573 sdhci_set_clock(mmc, mmc->clock);
575 if (mmc->clk_disable)
576 sdhci_set_clock(mmc, 0);
579 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
580 if (mmc->bus_width == 8) {
581 ctrl &= ~SDHCI_CTRL_4BITBUS;
582 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
583 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
584 ctrl |= SDHCI_CTRL_8BITBUS;
586 if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
587 (host->quirks & SDHCI_QUIRK_USE_WIDE8))
588 ctrl &= ~SDHCI_CTRL_8BITBUS;
589 if (mmc->bus_width == 4)
590 ctrl |= SDHCI_CTRL_4BITBUS;
592 ctrl &= ~SDHCI_CTRL_4BITBUS;
595 if (mmc->clock > 26000000)
596 ctrl |= SDHCI_CTRL_HISPD;
598 ctrl &= ~SDHCI_CTRL_HISPD;
600 if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
601 (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
602 ctrl &= ~SDHCI_CTRL_HISPD;
604 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
606 /* If available, call the driver specific "post" set_ios() function */
607 if (host->ops && host->ops->set_ios_post)
608 return host->ops->set_ios_post(host);
613 static int sdhci_init(struct mmc *mmc)
615 struct sdhci_host *host = mmc->priv;
616 #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
617 struct udevice *dev = mmc->dev;
619 gpio_request_by_name(dev, "cd-gpios", 0,
620 &host->cd_gpio, GPIOD_IS_IN);
623 sdhci_reset(host, SDHCI_RESET_ALL);
625 #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
626 host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
628 * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
631 host->force_align_buffer = true;
633 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
634 host->align_buffer = memalign(8, 512 * 1024);
635 if (!host->align_buffer) {
636 printf("%s: Aligned buffer alloc failed!!!\n",
643 sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
645 if (host->ops && host->ops->get_cd)
646 host->ops->get_cd(host);
648 /* Enable only interrupts served by the SD controller */
649 sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
651 /* Mask all sdhci interrupt sources */
652 sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
658 int sdhci_probe(struct udevice *dev)
660 struct mmc *mmc = mmc_get_mmc_dev(dev);
662 return sdhci_init(mmc);
665 static int sdhci_deferred_probe(struct udevice *dev)
668 struct mmc *mmc = mmc_get_mmc_dev(dev);
669 struct sdhci_host *host = mmc->priv;
671 if (host->ops && host->ops->deferred_probe) {
672 err = host->ops->deferred_probe(host);
679 static int sdhci_get_cd(struct udevice *dev)
681 struct mmc *mmc = mmc_get_mmc_dev(dev);
682 struct sdhci_host *host = mmc->priv;
685 /* If nonremovable, assume that the card is always present. */
686 if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
688 /* If polling, assume that the card is always present. */
689 if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
692 #if CONFIG_IS_ENABLED(DM_GPIO)
693 value = dm_gpio_get_value(&host->cd_gpio);
695 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
701 value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
703 if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
709 const struct dm_mmc_ops sdhci_ops = {
710 .send_cmd = sdhci_send_command,
711 .set_ios = sdhci_set_ios,
712 .get_cd = sdhci_get_cd,
713 .deferred_probe = sdhci_deferred_probe,
714 #ifdef MMC_SUPPORTS_TUNING
715 .execute_tuning = sdhci_execute_tuning,
719 static const struct mmc_ops sdhci_ops = {
720 .send_cmd = sdhci_send_command,
721 .set_ios = sdhci_set_ios,
726 int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
727 u32 f_max, u32 f_min)
729 u32 caps, caps_1 = 0;
730 #if CONFIG_IS_ENABLED(DM_MMC)
731 u64 dt_caps, dt_caps_mask;
733 dt_caps_mask = dev_read_u64_default(host->mmc->dev,
734 "sdhci-caps-mask", 0);
735 dt_caps = dev_read_u64_default(host->mmc->dev,
737 caps = ~(u32)dt_caps_mask &
738 sdhci_readl(host, SDHCI_CAPABILITIES);
739 caps |= (u32)dt_caps;
741 caps = sdhci_readl(host, SDHCI_CAPABILITIES);
743 debug("%s, caps: 0x%x\n", __func__, caps);
745 #ifdef CONFIG_MMC_SDHCI_SDMA
746 if ((caps & SDHCI_CAN_DO_SDMA)) {
747 host->flags |= USE_SDMA;
749 debug("%s: Your controller doesn't support SDMA!!\n",
753 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
754 if (!(caps & SDHCI_CAN_DO_ADMA2)) {
755 printf("%s: Your controller doesn't support SDMA!!\n",
759 host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
761 host->adma_addr = (dma_addr_t)host->adma_desc_table;
762 #ifdef CONFIG_DMA_ADDR_T_64BIT
763 host->flags |= USE_ADMA64;
765 host->flags |= USE_ADMA;
768 if (host->quirks & SDHCI_QUIRK_REG32_RW)
770 sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
772 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
774 cfg->name = host->name;
775 #ifndef CONFIG_DM_MMC
776 cfg->ops = &sdhci_ops;
779 /* Check whether the clock multiplier is supported or not */
780 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
781 #if CONFIG_IS_ENABLED(DM_MMC)
782 caps_1 = ~(u32)(dt_caps_mask >> 32) &
783 sdhci_readl(host, SDHCI_CAPABILITIES_1);
784 caps_1 |= (u32)(dt_caps >> 32);
786 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
788 debug("%s, caps_1: 0x%x\n", __func__, caps_1);
789 host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
790 SDHCI_CLOCK_MUL_SHIFT;
793 if (host->max_clk == 0) {
794 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
795 host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
796 SDHCI_CLOCK_BASE_SHIFT;
798 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
799 SDHCI_CLOCK_BASE_SHIFT;
800 host->max_clk *= 1000000;
802 host->max_clk *= host->clk_mul;
804 if (host->max_clk == 0) {
805 printf("%s: Hardware doesn't specify base clock frequency\n",
809 if (f_max && (f_max < host->max_clk))
812 cfg->f_max = host->max_clk;
816 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
817 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
819 cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
822 if (caps & SDHCI_CAN_VDD_330)
823 cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
824 if (caps & SDHCI_CAN_VDD_300)
825 cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
826 if (caps & SDHCI_CAN_VDD_180)
827 cfg->voltages |= MMC_VDD_165_195;
829 if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
830 cfg->voltages |= host->voltages;
832 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
834 /* Since Host Controller Version3.0 */
835 if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
836 if (!(caps & SDHCI_CAN_DO_8BIT))
837 cfg->host_caps &= ~MMC_MODE_8BIT;
840 if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
841 cfg->host_caps &= ~MMC_MODE_HS;
842 cfg->host_caps &= ~MMC_MODE_HS_52MHz;
845 if (!(cfg->voltages & MMC_VDD_165_195))
846 caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
847 SDHCI_SUPPORT_DDR50);
849 if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
850 SDHCI_SUPPORT_DDR50))
851 cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
853 if (caps_1 & SDHCI_SUPPORT_SDR104) {
854 cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
856 * SD3.0: SDR104 is supported so (for eMMC) the caps2
857 * field can be promoted to support HS200.
859 cfg->host_caps |= MMC_CAP(MMC_HS_200);
860 } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
861 cfg->host_caps |= MMC_CAP(UHS_SDR50);
864 if (caps_1 & SDHCI_SUPPORT_DDR50)
865 cfg->host_caps |= MMC_CAP(UHS_DDR50);
868 cfg->host_caps |= host->host_caps;
870 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
876 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
878 return mmc_bind(dev, mmc, cfg);
881 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
885 ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
889 host->mmc = mmc_create(&host->cfg, host);
890 if (host->mmc == NULL) {
891 printf("%s: mmc create fail!\n", __func__);