2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
31 #include <linux/mmc/mmc.h>
33 #include <linux/semaphore.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
38 #include <mach/hardware.h>
39 #include <plat/board.h>
43 /* OMAP HSMMC Host Controller Registers */
44 #define OMAP_HSMMC_SYSCONFIG 0x0010
45 #define OMAP_HSMMC_SYSSTATUS 0x0014
46 #define OMAP_HSMMC_CON 0x002C
47 #define OMAP_HSMMC_BLK 0x0104
48 #define OMAP_HSMMC_ARG 0x0108
49 #define OMAP_HSMMC_CMD 0x010C
50 #define OMAP_HSMMC_RSP10 0x0110
51 #define OMAP_HSMMC_RSP32 0x0114
52 #define OMAP_HSMMC_RSP54 0x0118
53 #define OMAP_HSMMC_RSP76 0x011C
54 #define OMAP_HSMMC_DATA 0x0120
55 #define OMAP_HSMMC_HCTL 0x0128
56 #define OMAP_HSMMC_SYSCTL 0x012C
57 #define OMAP_HSMMC_STAT 0x0130
58 #define OMAP_HSMMC_IE 0x0134
59 #define OMAP_HSMMC_ISE 0x0138
60 #define OMAP_HSMMC_CAPA 0x0140
62 #define VS18 (1 << 26)
63 #define VS30 (1 << 25)
64 #define SDVS18 (0x5 << 9)
65 #define SDVS30 (0x6 << 9)
66 #define SDVS33 (0x7 << 9)
67 #define SDVS_MASK 0x00000E00
68 #define SDVSCLR 0xFFFFF1FF
69 #define SDVSDET 0x00000400
76 #define CLKD_MASK 0x0000FFC0
78 #define DTO_MASK 0x000F0000
80 #define INT_EN_MASK 0x307F0033
81 #define BWR_ENABLE (1 << 4)
82 #define BRR_ENABLE (1 << 5)
83 #define DTO_ENABLE (1 << 20)
84 #define INIT_STREAM (1 << 1)
85 #define DP_SELECT (1 << 21)
90 #define FOUR_BIT (1 << 1)
96 #define CMD_TIMEOUT (1 << 16)
97 #define DATA_TIMEOUT (1 << 20)
98 #define CMD_CRC (1 << 17)
99 #define DATA_CRC (1 << 21)
100 #define CARD_ERR (1 << 28)
101 #define STAT_CLEAR 0xFFFFFFFF
102 #define INIT_STREAM_CMD 0x00000000
103 #define DUAL_VOLT_OCR_BIT 7
104 #define SRC (1 << 25)
105 #define SRD (1 << 26)
106 #define SOFTRESET (1 << 1)
107 #define RESETDONE (1 << 0)
110 * FIXME: Most likely all the data using these _DEVID defines should come
111 * from the platform_data, or implemented in controller and slot specific
114 #define OMAP_MMC1_DEVID 0
115 #define OMAP_MMC2_DEVID 1
116 #define OMAP_MMC3_DEVID 2
117 #define OMAP_MMC4_DEVID 3
118 #define OMAP_MMC5_DEVID 4
120 #define MMC_AUTOSUSPEND_DELAY 100
121 #define MMC_TIMEOUT_MS 20
122 #define OMAP_MMC_MASTER_CLOCK 96000000
123 #define OMAP_MMC_MIN_CLOCK 400000
124 #define OMAP_MMC_MAX_CLOCK 52000000
125 #define DRIVER_NAME "omap_hsmmc"
128 * One controller can have multiple slots, like on some omap boards using
129 * omap.c controller driver. Luckily this is not currently done on any known
130 * omap_hsmmc.c device.
132 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
135 * MMC Host controller read/write API's
137 #define OMAP_HSMMC_READ(base, reg) \
138 __raw_readl((base) + OMAP_HSMMC_##reg)
140 #define OMAP_HSMMC_WRITE(base, reg, val) \
141 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143 struct omap_hsmmc_next {
144 unsigned int dma_len;
148 struct omap_hsmmc_host {
150 struct mmc_host *mmc;
151 struct mmc_request *mrq;
152 struct mmc_command *cmd;
153 struct mmc_data *data;
157 * vcc == configured supply
158 * vcc_aux == optional
159 * - MMC1, supply for DAT4..DAT7
160 * - MMC2/MMC2, external level shifter voltage supply, for
161 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 struct regulator *vcc;
164 struct regulator *vcc_aux;
166 resource_size_t mapbase;
167 spinlock_t irq_lock; /* Prevent races with irq handler */
169 unsigned int dma_len;
170 unsigned int dma_sg_idx;
171 unsigned char bus_mode;
172 unsigned char power_mode;
178 int dma_line_tx, dma_line_rx;
189 struct omap_hsmmc_next next_data;
191 struct omap_mmc_platform_data *pdata;
194 static int omap_hsmmc_card_detect(struct device *dev, int slot)
196 struct omap_mmc_platform_data *mmc = dev->platform_data;
198 /* NOTE: assumes card detect signal is active-low */
199 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
202 static int omap_hsmmc_get_wp(struct device *dev, int slot)
204 struct omap_mmc_platform_data *mmc = dev->platform_data;
206 /* NOTE: assumes write protect signal is active-high */
207 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
210 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
212 struct omap_mmc_platform_data *mmc = dev->platform_data;
214 /* NOTE: assumes card detect signal is active-low */
215 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
220 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
222 struct omap_mmc_platform_data *mmc = dev->platform_data;
224 disable_irq(mmc->slots[0].card_detect_irq);
228 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
230 struct omap_mmc_platform_data *mmc = dev->platform_data;
232 enable_irq(mmc->slots[0].card_detect_irq);
238 #define omap_hsmmc_suspend_cdirq NULL
239 #define omap_hsmmc_resume_cdirq NULL
243 #ifdef CONFIG_REGULATOR
245 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
248 struct omap_hsmmc_host *host =
249 platform_get_drvdata(to_platform_device(dev));
252 if (mmc_slot(host).before_set_reg)
253 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
256 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
258 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
260 if (mmc_slot(host).after_set_reg)
261 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
266 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
269 struct omap_hsmmc_host *host =
270 platform_get_drvdata(to_platform_device(dev));
274 * If we don't see a Vcc regulator, assume it's a fixed
275 * voltage always-on regulator.
280 if (mmc_slot(host).before_set_reg)
281 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
284 * Assume Vcc regulator is used only to power the card ... OMAP
285 * VDDS is used to power the pins, optionally with a transceiver to
286 * support cards using voltages other than VDDS (1.8V nominal). When a
287 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
289 * In some cases this regulator won't support enable/disable;
290 * e.g. it's a fixed rail for a WLAN chip.
292 * In other cases vcc_aux switches interface power. Example, for
293 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
294 * chips/cards need an interface voltage rail too.
297 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
298 /* Enable interface voltage rail, if needed */
299 if (ret == 0 && host->vcc_aux) {
300 ret = regulator_enable(host->vcc_aux);
302 ret = mmc_regulator_set_ocr(host->mmc,
306 /* Shut down the rail */
308 ret = regulator_disable(host->vcc_aux);
310 /* Then proceed to shut down the local regulator */
311 ret = mmc_regulator_set_ocr(host->mmc,
316 if (mmc_slot(host).after_set_reg)
317 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
322 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
328 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
329 int vdd, int cardsleep)
331 struct omap_hsmmc_host *host =
332 platform_get_drvdata(to_platform_device(dev));
333 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
335 return regulator_set_mode(host->vcc, mode);
338 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
339 int vdd, int cardsleep)
341 struct omap_hsmmc_host *host =
342 platform_get_drvdata(to_platform_device(dev));
346 * If we don't see a Vcc regulator, assume it's a fixed
347 * voltage always-on regulator.
352 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
355 return regulator_set_mode(host->vcc, mode);
358 /* VCC can be turned off if card is asleep */
360 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
362 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
364 err = regulator_set_mode(host->vcc, mode);
368 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
369 return regulator_set_mode(host->vcc_aux, mode);
372 return regulator_disable(host->vcc_aux);
374 return regulator_enable(host->vcc_aux);
377 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
378 int vdd, int cardsleep)
383 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
385 struct regulator *reg;
390 case OMAP_MMC1_DEVID:
391 /* On-chip level shifting via PBIAS0/PBIAS1 */
392 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
393 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
395 case OMAP_MMC2_DEVID:
396 case OMAP_MMC3_DEVID:
397 case OMAP_MMC5_DEVID:
398 /* Off-chip level shifting, or none */
399 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
400 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
402 case OMAP_MMC4_DEVID:
403 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
404 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
406 pr_err("MMC%d configuration not supported!\n", host->id);
410 reg = regulator_get(host->dev, "vmmc");
412 dev_dbg(host->dev, "vmmc regulator missing\n");
414 * HACK: until fixed.c regulator is usable,
415 * we don't require a main regulator
418 if (host->id == OMAP_MMC1_DEVID) {
424 ocr_value = mmc_regulator_get_ocrmask(reg);
425 if (!mmc_slot(host).ocr_mask) {
426 mmc_slot(host).ocr_mask = ocr_value;
428 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
429 pr_err("MMC%d ocrmask %x is not supported\n",
430 host->id, mmc_slot(host).ocr_mask);
431 mmc_slot(host).ocr_mask = 0;
436 /* Allow an aux regulator */
437 reg = regulator_get(host->dev, "vmmc_aux");
438 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
440 /* For eMMC do not power off when not in sleep state */
441 if (mmc_slot(host).no_regulator_off_init)
444 * UGLY HACK: workaround regulator framework bugs.
445 * When the bootloader leaves a supply active, it's
446 * initialized with zero usecount ... and we can't
447 * disable it without first enabling it. Until the
448 * framework is fixed, we need a workaround like this
449 * (which is safe for MMC, but not in general).
451 if (regulator_is_enabled(host->vcc) > 0 ||
452 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
453 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
455 mmc_slot(host).set_power(host->dev, host->slot_id,
457 mmc_slot(host).set_power(host->dev, host->slot_id,
465 mmc_slot(host).set_power = NULL;
466 mmc_slot(host).set_sleep = NULL;
470 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
472 regulator_put(host->vcc);
473 regulator_put(host->vcc_aux);
474 mmc_slot(host).set_power = NULL;
475 mmc_slot(host).set_sleep = NULL;
478 static inline int omap_hsmmc_have_reg(void)
485 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
490 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
494 static inline int omap_hsmmc_have_reg(void)
501 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
505 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
506 if (pdata->slots[0].cover)
507 pdata->slots[0].get_cover_state =
508 omap_hsmmc_get_cover_state;
510 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
511 pdata->slots[0].card_detect_irq =
512 gpio_to_irq(pdata->slots[0].switch_pin);
513 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
516 ret = gpio_direction_input(pdata->slots[0].switch_pin);
520 pdata->slots[0].switch_pin = -EINVAL;
522 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
523 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
524 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
527 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
531 pdata->slots[0].gpio_wp = -EINVAL;
536 gpio_free(pdata->slots[0].gpio_wp);
538 if (gpio_is_valid(pdata->slots[0].switch_pin))
540 gpio_free(pdata->slots[0].switch_pin);
544 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
546 if (gpio_is_valid(pdata->slots[0].gpio_wp))
547 gpio_free(pdata->slots[0].gpio_wp);
548 if (gpio_is_valid(pdata->slots[0].switch_pin))
549 gpio_free(pdata->slots[0].switch_pin);
553 * Start clock to the card
555 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
557 OMAP_HSMMC_WRITE(host->base, SYSCTL,
558 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
562 * Stop clock to the card
564 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
566 OMAP_HSMMC_WRITE(host->base, SYSCTL,
567 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
568 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
569 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
572 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
573 struct mmc_command *cmd)
575 unsigned int irq_mask;
578 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
580 irq_mask = INT_EN_MASK;
582 /* Disable timeout for erases */
583 if (cmd->opcode == MMC_ERASE)
584 irq_mask &= ~DTO_ENABLE;
586 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
587 OMAP_HSMMC_WRITE(host->base, ISE, host->use_dma ? irq_mask : 0);
588 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
591 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
593 OMAP_HSMMC_WRITE(host->base, ISE, 0);
594 OMAP_HSMMC_WRITE(host->base, IE, 0);
595 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
598 /* Calculate divisor for the given clock frequency */
599 static u16 calc_divisor(struct mmc_ios *ios)
604 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
612 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
614 struct mmc_ios *ios = &host->mmc->ios;
615 unsigned long regval;
616 unsigned long timeout;
618 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
620 omap_hsmmc_stop_clock(host);
622 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
623 regval = regval & ~(CLKD_MASK | DTO_MASK);
624 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
625 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
626 OMAP_HSMMC_WRITE(host->base, SYSCTL,
627 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
629 /* Wait till the ICS bit is set */
630 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
631 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
632 && time_before(jiffies, timeout))
635 omap_hsmmc_start_clock(host);
638 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
640 struct mmc_ios *ios = &host->mmc->ios;
643 con = OMAP_HSMMC_READ(host->base, CON);
644 switch (ios->bus_width) {
645 case MMC_BUS_WIDTH_8:
646 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
648 case MMC_BUS_WIDTH_4:
649 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
650 OMAP_HSMMC_WRITE(host->base, HCTL,
651 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
653 case MMC_BUS_WIDTH_1:
654 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
655 OMAP_HSMMC_WRITE(host->base, HCTL,
656 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
661 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
663 struct mmc_ios *ios = &host->mmc->ios;
666 con = OMAP_HSMMC_READ(host->base, CON);
667 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
668 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
670 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
676 * Restore the MMC host context, if it was lost as result of a
677 * power state change.
679 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
681 struct mmc_ios *ios = &host->mmc->ios;
682 struct omap_mmc_platform_data *pdata = host->pdata;
683 int context_loss = 0;
685 unsigned long timeout;
687 if (pdata->get_context_loss_count) {
688 context_loss = pdata->get_context_loss_count(host->dev);
689 if (context_loss < 0)
693 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
694 context_loss == host->context_loss ? "not " : "");
695 if (host->context_loss == context_loss)
698 /* Wait for hardware reset */
699 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
700 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
701 && time_before(jiffies, timeout))
704 /* Do software reset */
705 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
706 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
707 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
708 && time_before(jiffies, timeout))
711 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
712 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
714 if (host->id == OMAP_MMC1_DEVID) {
715 if (host->power_mode != MMC_POWER_OFF &&
716 (1 << ios->vdd) <= MMC_VDD_23_24)
726 OMAP_HSMMC_WRITE(host->base, HCTL,
727 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
729 OMAP_HSMMC_WRITE(host->base, CAPA,
730 OMAP_HSMMC_READ(host->base, CAPA) | capa);
732 OMAP_HSMMC_WRITE(host->base, HCTL,
733 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
735 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
736 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
737 && time_before(jiffies, timeout))
740 omap_hsmmc_disable_irq(host);
742 /* Do not initialize card-specific things if the power is off */
743 if (host->power_mode == MMC_POWER_OFF)
746 omap_hsmmc_set_bus_width(host);
748 omap_hsmmc_set_clock(host);
750 omap_hsmmc_set_bus_mode(host);
753 host->context_loss = context_loss;
755 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
760 * Save the MMC host context (store the number of power state changes so far).
762 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
764 struct omap_mmc_platform_data *pdata = host->pdata;
767 if (pdata->get_context_loss_count) {
768 context_loss = pdata->get_context_loss_count(host->dev);
769 if (context_loss < 0)
771 host->context_loss = context_loss;
777 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
782 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
789 * Send init stream sequence to card
790 * before sending IDLE command
792 static void send_init_stream(struct omap_hsmmc_host *host)
795 unsigned long timeout;
797 if (host->protect_card)
800 disable_irq(host->irq);
802 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
803 OMAP_HSMMC_WRITE(host->base, CON,
804 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
805 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
807 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
808 while ((reg != CC) && time_before(jiffies, timeout))
809 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
811 OMAP_HSMMC_WRITE(host->base, CON,
812 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
814 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
815 OMAP_HSMMC_READ(host->base, STAT);
817 enable_irq(host->irq);
821 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
825 if (mmc_slot(host).get_cover_state)
826 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
831 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
834 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
835 struct omap_hsmmc_host *host = mmc_priv(mmc);
837 return sprintf(buf, "%s\n",
838 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
841 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
844 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
847 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
848 struct omap_hsmmc_host *host = mmc_priv(mmc);
850 return sprintf(buf, "%s\n", mmc_slot(host).name);
853 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
855 /* for hosts with 35xx erratum 2.1.1.128 */
857 omap_hsmmc_show_unsafe_read(struct device *dev, struct device_attribute *attr,
860 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
863 if (!(mmc->caps2 & MMC_CAP2_NO_MULTI_READ)) {
865 if (mmc->f_max == OMAP_MMC_MAX_CLOCK)
869 return sprintf(buf, "%d\n", val);
873 omap_hsmmc_set_unsafe_read(struct device *dev, struct device_attribute *attr,
874 const char *buf, size_t count)
876 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
880 ret = strict_strtoul(buf, 0, &val);
886 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
887 mmc->f_max = OMAP_MMC_MAX_CLOCK;
890 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
891 mmc->f_max = 32000000;
894 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
895 mmc->f_max = OMAP_MMC_MAX_CLOCK;
901 static DEVICE_ATTR(unsafe_read, S_IWUSR | S_IRUGO,
902 omap_hsmmc_show_unsafe_read, omap_hsmmc_set_unsafe_read);
905 * Configure the response type and send the cmd.
908 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
909 struct mmc_data *data)
911 int cmdreg = 0, resptype = 0, cmdtype = 0;
913 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
914 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
917 omap_hsmmc_enable_irq(host, cmd);
919 host->response_busy = 0;
920 if (cmd->flags & MMC_RSP_PRESENT) {
921 if (cmd->flags & MMC_RSP_136)
923 else if (cmd->flags & MMC_RSP_BUSY) {
925 host->response_busy = 1;
931 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
932 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
933 * a val of 0x3, rest 0x0.
935 if (cmd == host->mrq->stop)
938 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
941 cmdreg |= DP_SELECT | MSBS | BCE;
942 if (data->flags & MMC_DATA_READ)
951 host->req_in_progress = 1;
953 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
954 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
958 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
960 if (data->flags & MMC_DATA_WRITE)
961 return DMA_TO_DEVICE;
963 return DMA_FROM_DEVICE;
966 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
970 spin_lock(&host->irq_lock);
971 host->req_in_progress = 0;
972 dma_ch = host->dma_ch;
973 spin_unlock(&host->irq_lock);
975 omap_hsmmc_disable_irq(host);
976 /* Do not complete the request if DMA is still in progress */
977 if (mrq->data && host->use_dma && dma_ch != -1)
980 mmc_request_done(host->mmc, mrq);
984 * Notify the transfer complete to MMC core
987 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
990 struct mmc_request *mrq = host->mrq;
992 /* TC before CC from CMD6 - don't know why, but it happens */
993 if (host->cmd && host->cmd->opcode == 6 &&
994 host->response_busy) {
995 host->response_busy = 0;
999 omap_hsmmc_request_done(host, mrq);
1006 data->bytes_xfered += data->blocks * (data->blksz);
1008 data->bytes_xfered = 0;
1011 omap_hsmmc_request_done(host, data->mrq);
1014 omap_hsmmc_start_command(host, data->stop, NULL);
1018 * Notify the core about command completion
1021 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
1025 if (cmd->flags & MMC_RSP_PRESENT) {
1026 if (cmd->flags & MMC_RSP_136) {
1027 /* response type 2 */
1028 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1029 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1030 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1031 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1033 /* response types 1, 1b, 3, 4, 5, 6 */
1034 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1037 if ((host->data == NULL && !host->response_busy) || cmd->error)
1038 omap_hsmmc_request_done(host, cmd->mrq);
1042 * DMA clean up for command errors
1044 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
1048 host->data->error = errno;
1050 spin_lock(&host->irq_lock);
1051 dma_ch = host->dma_ch;
1053 spin_unlock(&host->irq_lock);
1055 if (host->use_dma && dma_ch != -1) {
1056 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
1058 omap_hsmmc_get_dma_dir(host, host->data));
1059 omap_free_dma(dma_ch);
1060 host->data->host_cookie = 0;
1066 * Readable error output
1068 #ifdef CONFIG_MMC_DEBUG
1069 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
1071 /* --- means reserved bit without definition at documentation */
1072 static const char *omap_hsmmc_status_bits[] = {
1073 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1074 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1075 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1076 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
1082 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1085 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1086 if (status & (1 << i)) {
1087 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1091 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1094 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1098 #endif /* CONFIG_MMC_DEBUG */
1101 * MMC controller internal state machines reset
1103 * Used to reset command or data internal state machines, using respectively
1104 * SRC or SRD bit of SYSCTL register
1105 * Can be called from interrupt context
1107 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1110 unsigned long i = 0;
1111 unsigned long limit = (loops_per_jiffy *
1112 msecs_to_jiffies(MMC_TIMEOUT_MS));
1114 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1115 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1118 * OMAP4 ES2 and greater has an updated reset logic.
1119 * Monitor a 0->1 transition first
1121 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1122 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1128 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1132 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1133 dev_err(mmc_dev(host->mmc),
1134 "Timeout waiting on controller reset in %s\n",
1138 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1140 struct mmc_data *data;
1141 int end_cmd = 0, end_trans = 0;
1143 if (!host->req_in_progress) {
1145 OMAP_HSMMC_WRITE(host->base, STAT, status);
1146 /* Flush posted write */
1147 status = OMAP_HSMMC_READ(host->base, STAT);
1148 } while (status & INT_EN_MASK);
1153 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1156 omap_hsmmc_dbg_report_irq(host, status);
1157 if ((status & CMD_TIMEOUT) ||
1158 (status & CMD_CRC)) {
1160 if (status & CMD_TIMEOUT) {
1161 omap_hsmmc_reset_controller_fsm(host,
1163 host->cmd->error = -ETIMEDOUT;
1165 host->cmd->error = -EILSEQ;
1169 if (host->data || host->response_busy) {
1171 omap_hsmmc_dma_cleanup(host,
1173 host->response_busy = 0;
1174 omap_hsmmc_reset_controller_fsm(host, SRD);
1177 if ((status & DATA_TIMEOUT) ||
1178 (status & DATA_CRC)) {
1179 if (host->data || host->response_busy) {
1180 int err = (status & DATA_TIMEOUT) ?
1181 -ETIMEDOUT : -EILSEQ;
1184 omap_hsmmc_dma_cleanup(host, err);
1186 host->mrq->cmd->error = err;
1187 host->response_busy = 0;
1188 omap_hsmmc_reset_controller_fsm(host, SRD);
1192 if (status & CARD_ERR) {
1193 dev_dbg(mmc_dev(host->mmc),
1194 "Ignoring card err CMD%d\n", host->cmd->opcode);
1202 OMAP_HSMMC_WRITE(host->base, STAT, status);
1204 if (end_cmd || ((status & CC) && host->cmd))
1205 omap_hsmmc_cmd_done(host, host->cmd);
1206 if ((end_trans || (status & TC)) && host->mrq)
1207 omap_hsmmc_xfer_done(host, data);
1211 * MMC controller IRQ handler
1213 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1215 struct omap_hsmmc_host *host = dev_id;
1218 status = OMAP_HSMMC_READ(host->base, STAT);
1220 omap_hsmmc_do_irq(host, status);
1221 /* Flush posted write */
1222 status = OMAP_HSMMC_READ(host->base, STAT);
1223 } while (status & INT_EN_MASK);
1228 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1232 OMAP_HSMMC_WRITE(host->base, HCTL,
1233 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1234 for (i = 0; i < loops_per_jiffy; i++) {
1235 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1242 * Switch MMC interface voltage ... only relevant for MMC1.
1244 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1245 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1246 * Some chips, like eMMC ones, use internal transceivers.
1248 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1253 /* Disable the clocks */
1254 pm_runtime_put_sync(host->dev);
1255 if (host->got_dbclk)
1256 clk_disable(host->dbclk);
1258 /* Turn the power off */
1259 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1261 /* Turn the power ON with given VDD 1.8 or 3.0v */
1263 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1265 pm_runtime_get_sync(host->dev);
1266 if (host->got_dbclk)
1267 clk_enable(host->dbclk);
1272 OMAP_HSMMC_WRITE(host->base, HCTL,
1273 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1274 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1277 * If a MMC dual voltage card is detected, the set_ios fn calls
1278 * this fn with VDD bit set for 1.8V. Upon card removal from the
1279 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1281 * Cope with a bit of slop in the range ... per data sheets:
1282 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1283 * but recommended values are 1.71V to 1.89V
1284 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1285 * but recommended values are 2.7V to 3.3V
1287 * Board setup code shouldn't permit anything very out-of-range.
1288 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1289 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1291 if ((1 << vdd) <= MMC_VDD_23_24)
1296 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1297 set_sd_bus_power(host);
1301 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1305 /* Protect the card while the cover is open */
1306 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1308 if (!mmc_slot(host).get_cover_state)
1311 host->reqs_blocked = 0;
1312 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1313 if (host->protect_card) {
1314 pr_info("%s: cover is closed, "
1315 "card is now accessible\n",
1316 mmc_hostname(host->mmc));
1317 host->protect_card = 0;
1320 if (!host->protect_card) {
1321 pr_info("%s: cover is open, "
1322 "card is now inaccessible\n",
1323 mmc_hostname(host->mmc));
1324 host->protect_card = 1;
1330 * irq handler to notify the core about card insertion/removal
1332 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1334 struct omap_hsmmc_host *host = dev_id;
1335 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1338 if (host->suspended)
1341 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1343 if (slot->card_detect)
1344 carddetect = slot->card_detect(host->dev, host->slot_id);
1346 omap_hsmmc_protect_card(host);
1347 carddetect = -ENOSYS;
1351 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1353 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1357 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1358 struct mmc_data *data)
1362 if (data->flags & MMC_DATA_WRITE)
1363 sync_dev = host->dma_line_tx;
1365 sync_dev = host->dma_line_rx;
1369 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1370 struct mmc_data *data,
1371 struct scatterlist *sgl)
1373 int blksz, nblk, dma_ch;
1375 dma_ch = host->dma_ch;
1376 if (data->flags & MMC_DATA_WRITE) {
1377 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1378 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1379 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1380 sg_dma_address(sgl), 0, 0);
1382 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1383 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1384 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1385 sg_dma_address(sgl), 0, 0);
1388 blksz = host->data->blksz;
1389 nblk = sg_dma_len(sgl) / blksz;
1391 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1392 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1393 omap_hsmmc_get_dma_sync_dev(host, data),
1394 !(data->flags & MMC_DATA_WRITE));
1396 omap_start_dma(dma_ch);
1400 * DMA call back function
1402 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1404 struct omap_hsmmc_host *host = cb_data;
1405 struct mmc_data *data;
1406 int dma_ch, req_in_progress;
1408 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1409 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1414 spin_lock(&host->irq_lock);
1415 if (host->dma_ch < 0) {
1416 spin_unlock(&host->irq_lock);
1420 data = host->mrq->data;
1422 if (host->dma_sg_idx < host->dma_len) {
1423 /* Fire up the next transfer. */
1424 omap_hsmmc_config_dma_params(host, data,
1425 data->sg + host->dma_sg_idx);
1426 spin_unlock(&host->irq_lock);
1430 if (!data->host_cookie)
1431 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1432 omap_hsmmc_get_dma_dir(host, data));
1434 req_in_progress = host->req_in_progress;
1435 dma_ch = host->dma_ch;
1437 spin_unlock(&host->irq_lock);
1439 omap_free_dma(dma_ch);
1441 /* If DMA has finished after TC, complete the request */
1442 if (!req_in_progress) {
1443 struct mmc_request *mrq = host->mrq;
1446 mmc_request_done(host->mmc, mrq);
1450 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1451 struct mmc_data *data,
1452 struct omap_hsmmc_next *next)
1456 if (!next && data->host_cookie &&
1457 data->host_cookie != host->next_data.cookie) {
1458 pr_warning("[%s] invalid cookie: data->host_cookie %d"
1459 " host->next_data.cookie %d\n",
1460 __func__, data->host_cookie, host->next_data.cookie);
1461 data->host_cookie = 0;
1464 /* Check if next job is already prepared */
1466 (!next && data->host_cookie != host->next_data.cookie)) {
1467 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1469 omap_hsmmc_get_dma_dir(host, data));
1472 dma_len = host->next_data.dma_len;
1473 host->next_data.dma_len = 0;
1481 next->dma_len = dma_len;
1482 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1484 host->dma_len = dma_len;
1490 * Routine to configure and start DMA for the MMC card
1492 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1493 struct mmc_request *req)
1495 int dma_ch = 0, ret = 0, i;
1496 struct mmc_data *data = req->data;
1498 /* Sanity check: all the SG entries must be aligned by block size. */
1499 for (i = 0; i < data->sg_len; i++) {
1500 struct scatterlist *sgl;
1503 if (sgl->length % data->blksz)
1506 if ((data->blksz % 4) != 0)
1507 /* REVISIT: The MMC buffer increments only when MSB is written.
1508 * Return error for blksz which is non multiple of four.
1512 BUG_ON(host->dma_ch != -1);
1514 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1515 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1517 dev_err(mmc_dev(host->mmc),
1518 "%s: omap_request_dma() failed with %d\n",
1519 mmc_hostname(host->mmc), ret);
1522 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1526 host->dma_ch = dma_ch;
1527 host->dma_sg_idx = 0;
1529 omap_hsmmc_config_dma_params(host, data, data->sg);
1534 static void set_data_timeout(struct omap_hsmmc_host *host)
1536 uint32_t reg, clkd, dto = 0;
1538 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1539 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1543 /* Use the maximum timeout value allowed in the standard of 14 or 0xE */
1547 reg |= dto << DTO_SHIFT;
1548 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1552 * Configure block length for MMC/SD cards and initiate the transfer.
1555 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1558 host->data = req->data;
1560 if (req->data == NULL) {
1561 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1563 * Set an arbitrary 100ms data timeout for commands with
1566 if (req->cmd->flags & MMC_RSP_BUSY)
1567 set_data_timeout(host);
1571 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1572 | (req->data->blocks << 16));
1573 set_data_timeout(host);
1575 if (host->use_dma) {
1576 ret = omap_hsmmc_start_dma_transfer(host, req);
1578 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1585 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1588 struct omap_hsmmc_host *host = mmc_priv(mmc);
1589 struct mmc_data *data = mrq->data;
1591 if (host->use_dma) {
1592 if (data->host_cookie)
1593 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1595 omap_hsmmc_get_dma_dir(host, data));
1596 data->host_cookie = 0;
1600 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1603 struct omap_hsmmc_host *host = mmc_priv(mmc);
1605 if (mrq->data->host_cookie) {
1606 mrq->data->host_cookie = 0;
1611 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1613 mrq->data->host_cookie = 0;
1616 #define BWR (1 << 4)
1617 #define BRR (1 << 5)
1619 static void omap_hsmmc_request_do_pio(struct mmc_host *mmc,
1620 struct mmc_request *req)
1622 struct omap_hsmmc_host *host = mmc_priv(mmc);
1623 u32 *data = sg_virt(req->data->sg);
1624 u32 len = req->data->sg->length;
1628 for (i = 0; i < 10000000; i++) {
1629 stat = OMAP_HSMMC_READ(host->base, STAT);
1633 //dev_err(mmc_dev(host->mmc), "stat %x, l %d\n", stat, i);
1635 if (stat & (DATA_TIMEOUT | DATA_CRC))
1636 omap_hsmmc_reset_controller_fsm(host, SRD);
1640 req->data->error = -EINVAL; // ?
1641 omap_hsmmc_xfer_done(host, host->data);
1645 if (req->data->flags & MMC_DATA_WRITE) {
1646 while (len > 0 && (stat & BWR)) {
1647 OMAP_HSMMC_WRITE(host->base, DATA, *data++);
1651 while (len > 0 && (stat & BRR)) {
1652 *data++ = OMAP_HSMMC_READ(host->base, DATA);
1657 if ((stat & CC) && host->cmd)
1658 omap_hsmmc_cmd_done(host, host->cmd);
1659 if ((stat & TC) && host->mrq) {
1660 omap_hsmmc_xfer_done(host, host->data);
1667 req->data->error = -ETIMEDOUT;
1668 omap_hsmmc_xfer_done(host, req->data);
1673 * Request function. for read/write operation
1675 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1677 struct omap_hsmmc_host *host = mmc_priv(mmc);
1680 BUG_ON(host->req_in_progress);
1681 BUG_ON(host->dma_ch != -1);
1682 if (host->protect_card) {
1683 if (host->reqs_blocked < 3) {
1685 * Ensure the controller is left in a consistent
1686 * state by resetting the command and data state
1689 omap_hsmmc_reset_controller_fsm(host, SRD);
1690 omap_hsmmc_reset_controller_fsm(host, SRC);
1691 host->reqs_blocked += 1;
1693 req->cmd->error = -EBADF;
1695 req->data->error = -EBADF;
1696 req->cmd->retries = 0;
1697 mmc_request_done(mmc, req);
1699 } else if (host->reqs_blocked)
1700 host->reqs_blocked = 0;
1702 /* pandora wifi hack.. */
1703 if (host->id == OMAP_MMC3_DEVID && req->data != NULL
1704 && req->data->sg_len == 1 && req->data->sg->length <= 16) {
1710 WARN_ON(host->mrq != NULL);
1712 err = omap_hsmmc_prepare_data(host, req);
1714 req->cmd->error = err;
1716 req->data->error = err;
1718 mmc_request_done(mmc, req);
1722 omap_hsmmc_start_command(host, req->cmd, req->data);
1724 if (host->use_dma == 0)
1725 omap_hsmmc_request_do_pio(mmc, req);
1728 /* Routine to configure clock values. Exposed API to core */
1729 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1731 struct omap_hsmmc_host *host = mmc_priv(mmc);
1732 int do_send_init_stream = 0;
1734 pm_runtime_get_sync(host->dev);
1736 if (ios->power_mode != host->power_mode) {
1737 switch (ios->power_mode) {
1739 mmc_slot(host).set_power(host->dev, host->slot_id,
1744 mmc_slot(host).set_power(host->dev, host->slot_id,
1746 host->vdd = ios->vdd;
1749 do_send_init_stream = 1;
1752 host->power_mode = ios->power_mode;
1755 /* FIXME: set registers based only on changes to ios */
1757 omap_hsmmc_set_bus_width(host);
1759 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1760 /* Only MMC1 can interface at 3V without some flavor
1761 * of external transceiver; but they all handle 1.8V.
1763 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1764 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1766 * The mmc_select_voltage fn of the core does
1767 * not seem to set the power_mode to
1768 * MMC_POWER_UP upon recalculating the voltage.
1771 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1772 dev_dbg(mmc_dev(host->mmc),
1773 "Switch operation failed\n");
1777 omap_hsmmc_set_clock(host);
1779 if (do_send_init_stream)
1780 send_init_stream(host);
1782 omap_hsmmc_set_bus_mode(host);
1784 pm_runtime_put_autosuspend(host->dev);
1787 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1789 struct omap_hsmmc_host *host = mmc_priv(mmc);
1791 if (!mmc_slot(host).card_detect)
1793 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1796 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1798 struct omap_hsmmc_host *host = mmc_priv(mmc);
1800 if (!mmc_slot(host).get_ro)
1802 return mmc_slot(host).get_ro(host->dev, 0);
1805 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1807 struct omap_hsmmc_host *host = mmc_priv(mmc);
1809 if (mmc_slot(host).init_card)
1810 mmc_slot(host).init_card(card);
1813 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1815 u32 hctl, capa, value;
1817 /* Only MMC1 supports 3.0V */
1818 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1826 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1827 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1829 value = OMAP_HSMMC_READ(host->base, CAPA);
1830 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1832 /* Set the controller to AUTO IDLE mode */
1833 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1834 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1836 /* Set SD bus power bit */
1837 set_sd_bus_power(host);
1840 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1842 struct omap_hsmmc_host *host = mmc_priv(mmc);
1844 pm_runtime_get_sync(host->dev);
1849 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1851 struct omap_hsmmc_host *host = mmc_priv(mmc);
1853 pm_runtime_mark_last_busy(host->dev);
1854 pm_runtime_put_autosuspend(host->dev);
1859 static const struct mmc_host_ops omap_hsmmc_ops = {
1860 .enable = omap_hsmmc_enable_fclk,
1861 .disable = omap_hsmmc_disable_fclk,
1862 .post_req = omap_hsmmc_post_req,
1863 .pre_req = omap_hsmmc_pre_req,
1864 .request = omap_hsmmc_request,
1865 .set_ios = omap_hsmmc_set_ios,
1866 .get_cd = omap_hsmmc_get_cd,
1867 .get_ro = omap_hsmmc_get_ro,
1868 .init_card = omap_hsmmc_init_card,
1869 /* NYET -- enable_sdio_irq */
1872 #ifdef CONFIG_DEBUG_FS
1874 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1876 struct mmc_host *mmc = s->private;
1877 struct omap_hsmmc_host *host = mmc_priv(mmc);
1878 int context_loss = 0;
1880 if (host->pdata->get_context_loss_count)
1881 context_loss = host->pdata->get_context_loss_count(host->dev);
1883 seq_printf(s, "mmc%d:\n"
1886 " nesting_cnt:\t%d\n"
1887 " ctx_loss:\t%d:%d\n"
1889 mmc->index, mmc->enabled ? 1 : 0,
1890 host->dpm_state, mmc->nesting_cnt,
1891 host->context_loss, context_loss);
1893 if (host->suspended) {
1894 seq_printf(s, "host suspended, can't read registers\n");
1898 pm_runtime_get_sync(host->dev);
1900 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1901 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1902 seq_printf(s, "CON:\t\t0x%08x\n",
1903 OMAP_HSMMC_READ(host->base, CON));
1904 seq_printf(s, "HCTL:\t\t0x%08x\n",
1905 OMAP_HSMMC_READ(host->base, HCTL));
1906 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1907 OMAP_HSMMC_READ(host->base, SYSCTL));
1908 seq_printf(s, "IE:\t\t0x%08x\n",
1909 OMAP_HSMMC_READ(host->base, IE));
1910 seq_printf(s, "ISE:\t\t0x%08x\n",
1911 OMAP_HSMMC_READ(host->base, ISE));
1912 seq_printf(s, "CAPA:\t\t0x%08x\n",
1913 OMAP_HSMMC_READ(host->base, CAPA));
1915 pm_runtime_mark_last_busy(host->dev);
1916 pm_runtime_put_autosuspend(host->dev);
1921 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1923 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1926 static const struct file_operations mmc_regs_fops = {
1927 .open = omap_hsmmc_regs_open,
1929 .llseek = seq_lseek,
1930 .release = single_release,
1933 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1935 if (mmc->debugfs_root)
1936 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1937 mmc, &mmc_regs_fops);
1942 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1948 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1950 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1951 struct mmc_host *mmc;
1952 struct omap_hsmmc_host *host = NULL;
1953 struct resource *res;
1956 if (pdata == NULL) {
1957 dev_err(&pdev->dev, "Platform Data is missing\n");
1961 if (pdata->nr_slots == 0) {
1962 dev_err(&pdev->dev, "No Slots\n");
1966 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1967 irq = platform_get_irq(pdev, 0);
1968 if (res == NULL || irq < 0)
1971 res->start += pdata->reg_offset;
1972 res->end += pdata->reg_offset;
1973 res = request_mem_region(res->start, resource_size(res), pdev->name);
1977 ret = omap_hsmmc_gpio_init(pdata);
1981 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1987 host = mmc_priv(mmc);
1989 host->pdata = pdata;
1990 host->dev = &pdev->dev;
1992 host->dev->dma_mask = &pdata->dma_mask;
1995 host->id = pdev->id;
1997 host->mapbase = res->start;
1998 host->base = ioremap(host->mapbase, SZ_4K);
1999 host->power_mode = MMC_POWER_OFF;
2000 host->next_data.cookie = 1;
2002 platform_set_drvdata(pdev, host);
2004 mmc->ops = &omap_hsmmc_ops;
2007 * If regulator_disable can only put vcc_aux to sleep then there is
2010 if (mmc_slot(host).vcc_aux_disable_is_sleep)
2011 mmc_slot(host).no_off = 1;
2013 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2014 mmc->f_max = OMAP_MMC_MAX_CLOCK;
2016 spin_lock_init(&host->irq_lock);
2018 host->fclk = clk_get(&pdev->dev, "fck");
2019 if (IS_ERR(host->fclk)) {
2020 ret = PTR_ERR(host->fclk);
2025 omap_hsmmc_context_save(host);
2027 mmc->caps |= MMC_CAP_DISABLE;
2029 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2030 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
2031 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
2034 pm_runtime_enable(host->dev);
2035 pm_runtime_get_sync(host->dev);
2036 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2037 pm_runtime_use_autosuspend(host->dev);
2039 if (cpu_is_omap2430()) {
2040 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2042 * MMC can still work without debounce clock.
2044 if (IS_ERR(host->dbclk))
2045 dev_warn(mmc_dev(host->mmc),
2046 "Failed to get debounce clock\n");
2048 host->got_dbclk = 1;
2050 if (host->got_dbclk)
2051 if (clk_enable(host->dbclk) != 0)
2052 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2056 /* Since we do only SG emulation, we can have as many segs
2058 mmc->max_segs = 1024;
2060 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2061 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2062 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2063 mmc->max_seg_size = mmc->max_req_size;
2065 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2066 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
2068 mmc->caps |= mmc_slot(host).caps;
2069 if (mmc->caps & MMC_CAP_8_BIT_DATA)
2070 mmc->caps |= MMC_CAP_4_BIT_DATA;
2072 if (mmc_slot(host).nonremovable)
2073 mmc->caps |= MMC_CAP_NONREMOVABLE;
2075 omap_hsmmc_conf_bus_power(host);
2077 /* Select DMA lines */
2079 case OMAP_MMC1_DEVID:
2080 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2081 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2083 case OMAP_MMC2_DEVID:
2084 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2085 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2087 case OMAP_MMC3_DEVID:
2088 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2089 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2091 case OMAP_MMC4_DEVID:
2092 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2093 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2095 case OMAP_MMC5_DEVID:
2096 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2097 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2100 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2104 /* Request IRQ for MMC operations */
2105 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
2106 mmc_hostname(mmc), host);
2108 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2112 if (pdata->init != NULL) {
2113 if (pdata->init(&pdev->dev) != 0) {
2114 dev_dbg(mmc_dev(host->mmc),
2115 "Unable to configure MMC IRQs\n");
2116 goto err_irq_cd_init;
2120 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2121 ret = omap_hsmmc_reg_get(host);
2127 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2129 /* Request IRQ for card detect */
2130 if ((mmc_slot(host).card_detect_irq)) {
2131 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
2134 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2135 mmc_hostname(mmc), host);
2137 dev_dbg(mmc_dev(host->mmc),
2138 "Unable to grab MMC CD IRQ\n");
2141 pdata->suspend = omap_hsmmc_suspend_cdirq;
2142 pdata->resume = omap_hsmmc_resume_cdirq;
2145 omap_hsmmc_disable_irq(host);
2147 omap_hsmmc_protect_card(host);
2151 if (mmc_slot(host).name != NULL) {
2152 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2156 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2157 ret = device_create_file(&mmc->class_dev,
2158 &dev_attr_cover_switch);
2163 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2164 ret = device_create_file(&mmc->class_dev, &dev_attr_unsafe_read);
2166 /* MMC_CAP2_NO_MULTI_READ makes it crawl, try a different workaround */
2167 mmc->caps2 &= ~MMC_CAP2_NO_MULTI_READ;
2169 mmc->f_max = 32000000;
2172 omap_hsmmc_debugfs(mmc);
2173 pm_runtime_mark_last_busy(host->dev);
2174 pm_runtime_put_autosuspend(host->dev);
2179 mmc_remove_host(mmc);
2180 free_irq(mmc_slot(host).card_detect_irq, host);
2183 omap_hsmmc_reg_put(host);
2185 if (host->pdata->cleanup)
2186 host->pdata->cleanup(&pdev->dev);
2188 free_irq(host->irq, host);
2190 pm_runtime_mark_last_busy(host->dev);
2191 pm_runtime_put_autosuspend(host->dev);
2192 clk_put(host->fclk);
2193 if (host->got_dbclk) {
2194 clk_disable(host->dbclk);
2195 clk_put(host->dbclk);
2198 iounmap(host->base);
2199 platform_set_drvdata(pdev, NULL);
2202 omap_hsmmc_gpio_free(pdata);
2204 release_mem_region(res->start, resource_size(res));
2208 static int omap_hsmmc_remove(struct platform_device *pdev)
2210 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2211 struct resource *res;
2214 pm_runtime_get_sync(host->dev);
2215 mmc_remove_host(host->mmc);
2217 omap_hsmmc_reg_put(host);
2218 if (host->pdata->cleanup)
2219 host->pdata->cleanup(&pdev->dev);
2220 free_irq(host->irq, host);
2221 if (mmc_slot(host).card_detect_irq)
2222 free_irq(mmc_slot(host).card_detect_irq, host);
2224 pm_runtime_put_sync(host->dev);
2225 pm_runtime_disable(host->dev);
2226 clk_put(host->fclk);
2227 if (host->got_dbclk) {
2228 clk_disable(host->dbclk);
2229 clk_put(host->dbclk);
2232 mmc_free_host(host->mmc);
2233 iounmap(host->base);
2234 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2237 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2239 release_mem_region(res->start, resource_size(res));
2240 platform_set_drvdata(pdev, NULL);
2246 static int omap_hsmmc_suspend(struct device *dev)
2249 struct platform_device *pdev = to_platform_device(dev);
2250 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2252 if (host && host->suspended)
2256 pm_runtime_get_sync(host->dev);
2257 host->suspended = 1;
2258 if (host->pdata->suspend) {
2259 ret = host->pdata->suspend(&pdev->dev,
2262 dev_dbg(mmc_dev(host->mmc),
2263 "Unable to handle MMC board"
2264 " level suspend\n");
2265 host->suspended = 0;
2269 ret = mmc_suspend_host(host->mmc);
2272 omap_hsmmc_disable_irq(host);
2273 OMAP_HSMMC_WRITE(host->base, HCTL,
2274 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2275 if (host->got_dbclk)
2276 clk_disable(host->dbclk);
2278 host->suspended = 0;
2279 if (host->pdata->resume) {
2280 if (host->pdata->resume(&pdev->dev, host->slot_id))
2281 dev_dbg(mmc_dev(host->mmc),
2282 "Unmask interrupt failed\n");
2285 pm_runtime_put_sync(host->dev);
2290 /* Routine to resume the MMC device */
2291 static int omap_hsmmc_resume(struct device *dev)
2294 struct platform_device *pdev = to_platform_device(dev);
2295 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2297 if (host && !host->suspended)
2301 pm_runtime_get_sync(host->dev);
2303 if (host->got_dbclk)
2304 clk_enable(host->dbclk);
2306 omap_hsmmc_conf_bus_power(host);
2308 if (host->pdata->resume) {
2309 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2311 dev_dbg(mmc_dev(host->mmc),
2312 "Unmask interrupt failed\n");
2315 omap_hsmmc_protect_card(host);
2317 /* Notify the core to resume the host */
2318 ret = mmc_resume_host(host->mmc);
2320 host->suspended = 0;
2322 pm_runtime_mark_last_busy(host->dev);
2323 pm_runtime_put_autosuspend(host->dev);
2331 #define omap_hsmmc_suspend NULL
2332 #define omap_hsmmc_resume NULL
2335 static int omap_hsmmc_runtime_suspend(struct device *dev)
2337 struct omap_hsmmc_host *host;
2339 host = platform_get_drvdata(to_platform_device(dev));
2340 omap_hsmmc_context_save(host);
2341 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2346 static int omap_hsmmc_runtime_resume(struct device *dev)
2348 struct omap_hsmmc_host *host;
2350 host = platform_get_drvdata(to_platform_device(dev));
2351 omap_hsmmc_context_restore(host);
2352 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2357 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2358 .suspend = omap_hsmmc_suspend,
2359 .resume = omap_hsmmc_resume,
2360 .runtime_suspend = omap_hsmmc_runtime_suspend,
2361 .runtime_resume = omap_hsmmc_runtime_resume,
2364 static struct platform_driver omap_hsmmc_driver = {
2365 .remove = omap_hsmmc_remove,
2367 .name = DRIVER_NAME,
2368 .owner = THIS_MODULE,
2369 .pm = &omap_hsmmc_dev_pm_ops,
2373 static int __init omap_hsmmc_init(void)
2375 /* Register the MMC driver */
2376 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2379 static void __exit omap_hsmmc_cleanup(void)
2381 /* Unregister MMC driver */
2382 platform_driver_unregister(&omap_hsmmc_driver);
2385 module_init(omap_hsmmc_init);
2386 module_exit(omap_hsmmc_cleanup);
2388 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2389 MODULE_LICENSE("GPL");
2390 MODULE_ALIAS("platform:" DRIVER_NAME);
2391 MODULE_AUTHOR("Texas Instruments Inc");