drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/dmaengine.h>
  23 #include <linux/seq_file.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/timer.h>
  29 #include <linux/clk.h>
  30 #include <linux/of.h>
  31 #include <linux/of_gpio.h>
  32 #include <linux/of_device.h>
  33 #include <linux/omap-dma.h>
  34 #include <linux/mmc/host.h>
  35 #include <linux/mmc/core.h>
  36 #include <linux/mmc/mmc.h>
  37 #include <linux/io.h>
  38 #include <linux/semaphore.h>
  39 #include <linux/gpio.h>
  40 #include <linux/regulator/consumer.h>
  41 #include <linux/pm_runtime.h>
  42 #include <mach/hardware.h>
  43 #include <plat/mmc.h>
  44 #include <plat/cpu.h>
  45
  46 /* OMAP HSMMC Host Controller Registers */
  47 #define OMAP_HSMMC_SYSCONFIG    0x0010
  48 #define OMAP_HSMMC_SYSSTATUS    0x0014
  49 #define OMAP_HSMMC_CON          0x002C
  50 #define OMAP_HSMMC_BLK          0x0104
  51 #define OMAP_HSMMC_ARG          0x0108
  52 #define OMAP_HSMMC_CMD          0x010C
  53 #define OMAP_HSMMC_RSP10        0x0110
  54 #define OMAP_HSMMC_RSP32        0x0114
  55 #define OMAP_HSMMC_RSP54        0x0118
  56 #define OMAP_HSMMC_RSP76        0x011C
  57 #define OMAP_HSMMC_DATA         0x0120
  58 #define OMAP_HSMMC_HCTL         0x0128
  59 #define OMAP_HSMMC_SYSCTL       0x012C
  60 #define OMAP_HSMMC_STAT         0x0130
  61 #define OMAP_HSMMC_IE           0x0134
  62 #define OMAP_HSMMC_ISE          0x0138
  63 #define OMAP_HSMMC_CAPA         0x0140
  64
  65 #define VS18                    (1 << 26)
  66 #define VS30                    (1 << 25)
  67 #define SDVS18                  (0x5 << 9)
  68 #define SDVS30                  (0x6 << 9)
  69 #define SDVS33                  (0x7 << 9)
  70 #define SDVS_MASK               0x00000E00
  71 #define SDVSCLR                 0xFFFFF1FF
  72 #define SDVSDET                 0x00000400
  73 #define AUTOIDLE                0x1
  74 #define SDBP                    (1 << 8)
  75 #define DTO                     0xe
  76 #define ICE                     0x1
  77 #define ICS                     0x2
  78 #define CEN                     (1 << 2)
  79 #define CLKD_MASK               0x0000FFC0
  80 #define CLKD_SHIFT              6
  81 #define DTO_MASK                0x000F0000
  82 #define DTO_SHIFT               16
  83 #define INT_EN_MASK             0x307F0033
  84 #define BWR_ENABLE              (1 << 4)
  85 #define BRR_ENABLE              (1 << 5)
  86 #define DTO_ENABLE              (1 << 20)
  87 #define INIT_STREAM             (1 << 1)
  88 #define DP_SELECT               (1 << 21)
  89 #define DDIR                    (1 << 4)
  90 #define DMA_EN                  0x1
  91 #define MSBS                    (1 << 5)
  92 #define BCE                     (1 << 1)
  93 #define FOUR_BIT                (1 << 1)
  94 #define DDR                     (1 << 19)
  95 #define DW8                     (1 << 5)
  96 #define CC                      0x1
  97 #define TC                      0x02
  98 #define OD                      0x1
  99 #define ERR                     (1 << 15)
 100 #define CMD_TIMEOUT             (1 << 16)
 101 #define DATA_TIMEOUT            (1 << 20)
 102 #define CMD_CRC                 (1 << 17)
 103 #define DATA_CRC                (1 << 21)
 104 #define CARD_ERR                (1 << 28)
 105 #define STAT_CLEAR              0xFFFFFFFF
 106 #define INIT_STREAM_CMD         0x00000000
 107 #define DUAL_VOLT_OCR_BIT       7
 108 #define SRC                     (1 << 25)
 109 #define SRD                     (1 << 26)
 110 #define SOFTRESET               (1 << 1)
 111 #define RESETDONE               (1 << 0)
 112
 113 #define MMC_AUTOSUSPEND_DELAY   100
 114 #define MMC_TIMEOUT_MS          20
 115 #define OMAP_MMC_MIN_CLOCK      400000
 116 #define OMAP_MMC_MAX_CLOCK      52000000
 117 #define DRIVER_NAME             "omap_hsmmc"
 118
 119 /*
 120  * One controller can have multiple slots, like on some omap boards using
 121  * omap.c controller driver. Luckily this is not currently done on any known
 122  * omap_hsmmc.c device.
 123  */
 124 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 125
 126 /*
 127  * MMC Host controller read/write API's
 128  */
 129 #define OMAP_HSMMC_READ(base, reg)      \
 130         __raw_readl((base) + OMAP_HSMMC_##reg)
 131
 132 #define OMAP_HSMMC_WRITE(base, reg, val) \
 133         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 134
 135 struct omap_hsmmc_next {
 136         unsigned int    dma_len;
 137         s32             cookie;
 138 };
 139
 140 struct omap_hsmmc_host {
 141         struct  device          *dev;
 142         struct  mmc_host        *mmc;
 143         struct  mmc_request     *mrq;
 144         struct  mmc_command     *cmd;
 145         struct  mmc_data        *data;
 146         struct  clk             *fclk;
 147         struct  clk             *dbclk;
 148         /*
 149          * vcc == configured supply
 150          * vcc_aux == optional
 151          *   -  MMC1, supply for DAT4..DAT7
 152          *   -  MMC2/MMC2, external level shifter voltage supply, for
 153          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 154          */
 155         struct  regulator       *vcc;
 156         struct  regulator       *vcc_aux;
 157         void    __iomem         *base;
 158         resource_size_t         mapbase;
 159         spinlock_t              irq_lock; /* Prevent races with irq handler */
 160         unsigned int            dma_len;
 161         unsigned int            dma_sg_idx;
 162         unsigned char           bus_mode;
 163         unsigned char           power_mode;
 164         u32                     *buffer;
 165         u32                     bytesleft;
 166         int                     suspended;
 167         int                     irq;
 168         int                     use_dma, dma_ch;
 169         struct dma_chan         *tx_chan;
 170         struct dma_chan         *rx_chan;
 171         int                     slot_id;
 172         int                     response_busy;
 173         int                     context_loss;
 174         int                     vdd;
 175         int                     protect_card;
 176         int                     reqs_blocked;
 177         int                     use_reg;
 178         int                     req_in_progress;
 179         struct omap_hsmmc_next  next_data;
 180
 181         struct  omap_mmc_platform_data  *pdata;
 182 };
 183
 184 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 185 {
 186         struct omap_mmc_platform_data *mmc = dev->platform_data;
 187
 188         /* NOTE: assumes card detect signal is active-low */
 189         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 190 }
 191
 192 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 193 {
 194         struct omap_mmc_platform_data *mmc = dev->platform_data;
 195
 196         /* NOTE: assumes write protect signal is active-high */
 197         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 198 }
 199
 200 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 201 {
 202         struct omap_mmc_platform_data *mmc = dev->platform_data;
 203
 204         /* NOTE: assumes card detect signal is active-low */
 205         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 206 }
 207
 208 #ifdef CONFIG_PM
 209
 210 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 211 {
 212         struct omap_mmc_platform_data *mmc = dev->platform_data;
 213
 214         disable_irq(mmc->slots[0].card_detect_irq);
 215         return 0;
 216 }
 217
 218 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 219 {
 220         struct omap_mmc_platform_data *mmc = dev->platform_data;
 221
 222         enable_irq(mmc->slots[0].card_detect_irq);
 223         return 0;
 224 }
 225
 226 #else
 227
 228 #define omap_hsmmc_suspend_cdirq        NULL
 229 #define omap_hsmmc_resume_cdirq         NULL
 230
 231 #endif
 232
 233 #ifdef CONFIG_REGULATOR
 234
 235 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 236                                    int vdd)
 237 {
 238         struct omap_hsmmc_host *host =
 239                 platform_get_drvdata(to_platform_device(dev));
 240         int ret = 0;
 241
 242         /*
 243          * If we don't see a Vcc regulator, assume it's a fixed
 244          * voltage always-on regulator.
 245          */
 246         if (!host->vcc)
 247                 return 0;
 248         /*
 249          * With DT, never turn OFF the regulator. This is because
 250          * the pbias cell programming support is still missing when
 251          * booting with Device tree
 252          */
 253         if (dev->of_node && !vdd)
 254                 return 0;
 255
 256         if (mmc_slot(host).before_set_reg)
 257                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 258
 259         /*
 260          * Assume Vcc regulator is used only to power the card ... OMAP
 261          * VDDS is used to power the pins, optionally with a transceiver to
 262          * support cards using voltages other than VDDS (1.8V nominal).  When a
 263          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 264          *
 265          * In some cases this regulator won't support enable/disable;
 266          * e.g. it's a fixed rail for a WLAN chip.
 267          *
 268          * In other cases vcc_aux switches interface power.  Example, for
 269          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 270          * chips/cards need an interface voltage rail too.
 271          */
 272         if (power_on) {
 273                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 274                 /* Enable interface voltage rail, if needed */
 275                 if (ret == 0 && host->vcc_aux) {
 276                         ret = regulator_enable(host->vcc_aux);
 277                         if (ret < 0)
 278                                 ret = mmc_regulator_set_ocr(host->mmc,
 279                                                         host->vcc, 0);
 280                 }
 281         } else {
 282                 /* Shut down the rail */
 283                 if (host->vcc_aux)
 284                         ret = regulator_disable(host->vcc_aux);
 285                 if (!ret) {
 286                         /* Then proceed to shut down the local regulator */
 287                         ret = mmc_regulator_set_ocr(host->mmc,
 288                                                 host->vcc, 0);
 289                 }
 290         }
 291
 292         if (mmc_slot(host).after_set_reg)
 293                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 294
 295         return ret;
 296 }
 297
 298 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 299 {
 300         struct regulator *reg;
 301         int ocr_value = 0;
 302
 303         mmc_slot(host).set_power = omap_hsmmc_set_power;
 304
 305         reg = regulator_get(host->dev, "vmmc");
 306         if (IS_ERR(reg)) {
 307                 dev_dbg(host->dev, "vmmc regulator missing\n");
 308         } else {
 309                 host->vcc = reg;
 310                 ocr_value = mmc_regulator_get_ocrmask(reg);
 311                 if (!mmc_slot(host).ocr_mask) {
 312                         mmc_slot(host).ocr_mask = ocr_value;
 313                 } else {
 314                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 315                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 316                                         mmc_slot(host).ocr_mask);
 317                                 mmc_slot(host).ocr_mask = 0;
 318                                 return -EINVAL;
 319                         }
 320                 }
 321
 322                 /* Allow an aux regulator */
 323                 reg = regulator_get(host->dev, "vmmc_aux");
 324                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 325
 326                 /* For eMMC do not power off when not in sleep state */
 327                 if (mmc_slot(host).no_regulator_off_init)
 328                         return 0;
 329                 /*
 330                 * UGLY HACK:  workaround regulator framework bugs.
 331                 * When the bootloader leaves a supply active, it's
 332                 * initialized with zero usecount ... and we can't
 333                 * disable it without first enabling it.  Until the
 334                 * framework is fixed, we need a workaround like this
 335                 * (which is safe for MMC, but not in general).
 336                 */
 337                 if (regulator_is_enabled(host->vcc) > 0 ||
 338                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 339                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 340
 341                         mmc_slot(host).set_power(host->dev, host->slot_id,
 342                                                  1, vdd);
 343                         mmc_slot(host).set_power(host->dev, host->slot_id,
 344                                                  0, 0);
 345                 }
 346         }
 347
 348         return 0;
 349 }
 350
 351 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 352 {
 353         regulator_put(host->vcc);
 354         regulator_put(host->vcc_aux);
 355         mmc_slot(host).set_power = NULL;
 356 }
 357
 358 static inline int omap_hsmmc_have_reg(void)
 359 {
 360         return 1;
 361 }
 362
 363 #else
 364
 365 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 366 {
 367         return -EINVAL;
 368 }
 369
 370 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 371 {
 372 }
 373
 374 static inline int omap_hsmmc_have_reg(void)
 375 {
 376         return 0;
 377 }
 378
 379 #endif
 380
 381 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 382 {
 383         int ret;
 384
 385         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 386                 if (pdata->slots[0].cover)
 387                         pdata->slots[0].get_cover_state =
 388                                         omap_hsmmc_get_cover_state;
 389                 else
 390                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 391                 pdata->slots[0].card_detect_irq =
 392                                 gpio_to_irq(pdata->slots[0].switch_pin);
 393                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 394                 if (ret)
 395                         return ret;
 396                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 397                 if (ret)
 398                         goto err_free_sp;
 399         } else
 400                 pdata->slots[0].switch_pin = -EINVAL;
 401
 402         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 403                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 404                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 405                 if (ret)
 406                         goto err_free_cd;
 407                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 408                 if (ret)
 409                         goto err_free_wp;
 410         } else
 411                 pdata->slots[0].gpio_wp = -EINVAL;
 412
 413         return 0;
 414
 415 err_free_wp:
 416         gpio_free(pdata->slots[0].gpio_wp);
 417 err_free_cd:
 418         if (gpio_is_valid(pdata->slots[0].switch_pin))
 419 err_free_sp:
 420                 gpio_free(pdata->slots[0].switch_pin);
 421         return ret;
 422 }
 423
 424 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 425 {
 426         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 427                 gpio_free(pdata->slots[0].gpio_wp);
 428         if (gpio_is_valid(pdata->slots[0].switch_pin))
 429                 gpio_free(pdata->slots[0].switch_pin);
 430 }
 431
 432 /*
 433  * Start clock to the card
 434  */
 435 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 436 {
 437         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 438                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 439 }
 440
 441 /*
 442  * Stop clock to the card
 443  */
 444 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 445 {
 446         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 447                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 448         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 449                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 450 }
 451
 452 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 453                                   struct mmc_command *cmd)
 454 {
 455         unsigned int irq_mask;
 456
 457         if (host->use_dma)
 458                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 459         else
 460                 irq_mask = INT_EN_MASK;
 461
 462         /* Disable timeout for erases */
 463         if (cmd->opcode == MMC_ERASE)
 464                 irq_mask &= ~DTO_ENABLE;
 465
 466         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 467         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 468         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 469 }
 470
 471 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 472 {
 473         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 474         OMAP_HSMMC_WRITE(host->base, IE, 0);
 475         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 476 }
 477
 478 /* Calculate divisor for the given clock frequency */
 479 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 480 {
 481         u16 dsor = 0;
 482
 483         if (ios->clock) {
 484                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 485                 if (dsor > 250)
 486                         dsor = 250;
 487         }
 488
 489         return dsor;
 490 }
 491
 492 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 493 {
 494         struct mmc_ios *ios = &host->mmc->ios;
 495         unsigned long regval;
 496         unsigned long timeout;
 497
 498         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 499
 500         omap_hsmmc_stop_clock(host);
 501
 502         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 503         regval = regval & ~(CLKD_MASK | DTO_MASK);
 504         regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
 505         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 506         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 507                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 508
 509         /* Wait till the ICS bit is set */
 510         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 511         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 512                 && time_before(jiffies, timeout))
 513                 cpu_relax();
 514
 515         omap_hsmmc_start_clock(host);
 516 }
 517
 518 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 519 {
 520         struct mmc_ios *ios = &host->mmc->ios;
 521         u32 con;
 522
 523         con = OMAP_HSMMC_READ(host->base, CON);
 524         if (ios->timing == MMC_TIMING_UHS_DDR50)
 525                 con |= DDR;     /* configure in DDR mode */
 526         else
 527                 con &= ~DDR;
 528         switch (ios->bus_width) {
 529         case MMC_BUS_WIDTH_8:
 530                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 531                 break;
 532         case MMC_BUS_WIDTH_4:
 533                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 534                 OMAP_HSMMC_WRITE(host->base, HCTL,
 535                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 536                 break;
 537         case MMC_BUS_WIDTH_1:
 538                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 539                 OMAP_HSMMC_WRITE(host->base, HCTL,
 540                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 541                 break;
 542         }
 543 }
 544
 545 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 546 {
 547         struct mmc_ios *ios = &host->mmc->ios;
 548         u32 con;
 549
 550         con = OMAP_HSMMC_READ(host->base, CON);
 551         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 552                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 553         else
 554                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 555 }
 556
 557 #ifdef CONFIG_PM
 558
 559 /*
 560  * Restore the MMC host context, if it was lost as result of a
 561  * power state change.
 562  */
 563 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 564 {
 565         struct mmc_ios *ios = &host->mmc->ios;
 566         struct omap_mmc_platform_data *pdata = host->pdata;
 567         int context_loss = 0;
 568         u32 hctl, capa;
 569         unsigned long timeout;
 570
 571         if (pdata->get_context_loss_count) {
 572                 context_loss = pdata->get_context_loss_count(host->dev);
 573                 if (context_loss < 0)
 574                         return 1;
 575         }
 576
 577         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 578                 context_loss == host->context_loss ? "not " : "");
 579         if (host->context_loss == context_loss)
 580                 return 1;
 581
 582         /* Wait for hardware reset */
 583         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 584         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 585                 && time_before(jiffies, timeout))
 586                 ;
 587
 588         /* Do software reset */
 589         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 590         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 591         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 592                 && time_before(jiffies, timeout))
 593                 ;
 594
 595         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 596                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 597
 598         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 599                 if (host->power_mode != MMC_POWER_OFF &&
 600                     (1 << ios->vdd) <= MMC_VDD_23_24)
 601                         hctl = SDVS18;
 602                 else
 603                         hctl = SDVS30;
 604                 capa = VS30 | VS18;
 605         } else {
 606                 hctl = SDVS18;
 607                 capa = VS18;
 608         }
 609
 610         OMAP_HSMMC_WRITE(host->base, HCTL,
 611                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 612
 613         OMAP_HSMMC_WRITE(host->base, CAPA,
 614                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 615
 616         OMAP_HSMMC_WRITE(host->base, HCTL,
 617                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 618
 619         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 620         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 621                 && time_before(jiffies, timeout))
 622                 ;
 623
 624         omap_hsmmc_disable_irq(host);
 625
 626         /* Do not initialize card-specific things if the power is off */
 627         if (host->power_mode == MMC_POWER_OFF)
 628                 goto out;
 629
 630         omap_hsmmc_set_bus_width(host);
 631
 632         omap_hsmmc_set_clock(host);
 633
 634         omap_hsmmc_set_bus_mode(host);
 635
 636 out:
 637         host->context_loss = context_loss;
 638
 639         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 640         return 0;
 641 }
 642
 643 /*
 644  * Save the MMC host context (store the number of power state changes so far).
 645  */
 646 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 647 {
 648         struct omap_mmc_platform_data *pdata = host->pdata;
 649         int context_loss;
 650
 651         if (pdata->get_context_loss_count) {
 652                 context_loss = pdata->get_context_loss_count(host->dev);
 653                 if (context_loss < 0)
 654                         return;
 655                 host->context_loss = context_loss;
 656         }
 657 }
 658
 659 #else
 660
 661 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 662 {
 663         return 0;
 664 }
 665
 666 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 667 {
 668 }
 669
 670 #endif
 671
 672 /*
 673  * Send init stream sequence to card
 674  * before sending IDLE command
 675  */
 676 static void send_init_stream(struct omap_hsmmc_host *host)
 677 {
 678         int reg = 0;
 679         unsigned long timeout;
 680
 681         if (host->protect_card)
 682                 return;
 683
 684         disable_irq(host->irq);
 685
 686         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 687         OMAP_HSMMC_WRITE(host->base, CON,
 688                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 689         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 690
 691         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 692         while ((reg != CC) && time_before(jiffies, timeout))
 693                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 694
 695         OMAP_HSMMC_WRITE(host->base, CON,
 696                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 697
 698         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 699         OMAP_HSMMC_READ(host->base, STAT);
 700
 701         enable_irq(host->irq);
 702 }
 703
 704 static inline
 705 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 706 {
 707         int r = 1;
 708
 709         if (mmc_slot(host).get_cover_state)
 710                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 711         return r;
 712 }
 713
 714 static ssize_t
 715 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 716                            char *buf)
 717 {
 718         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 719         struct omap_hsmmc_host *host = mmc_priv(mmc);
 720
 721         return sprintf(buf, "%s\n",
 722                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 723 }
 724
 725 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 726
 727 static ssize_t
 728 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 729                         char *buf)
 730 {
 731         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 732         struct omap_hsmmc_host *host = mmc_priv(mmc);
 733
 734         return sprintf(buf, "%s\n", mmc_slot(host).name);
 735 }
 736
 737 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 738
 739 /*
 740  * Configure the response type and send the cmd.
 741  */
 742 static void
 743 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 744         struct mmc_data *data)
 745 {
 746         int cmdreg = 0, resptype = 0, cmdtype = 0;
 747
 748         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 749                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 750         host->cmd = cmd;
 751
 752         omap_hsmmc_enable_irq(host, cmd);
 753
 754         host->response_busy = 0;
 755         if (cmd->flags & MMC_RSP_PRESENT) {
 756                 if (cmd->flags & MMC_RSP_136)
 757                         resptype = 1;
 758                 else if (cmd->flags & MMC_RSP_BUSY) {
 759                         resptype = 3;
 760                         host->response_busy = 1;
 761                 } else
 762                         resptype = 2;
 763         }
 764
 765         /*
 766          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 767          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 768          * a val of 0x3, rest 0x0.
 769          */
 770         if (cmd == host->mrq->stop)
 771                 cmdtype = 0x3;
 772
 773         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 774
 775         if (data) {
 776                 cmdreg |= DP_SELECT | MSBS | BCE;
 777                 if (data->flags & MMC_DATA_READ)
 778                         cmdreg |= DDIR;
 779                 else
 780                         cmdreg &= ~(DDIR);
 781         }
 782
 783         if (host->use_dma)
 784                 cmdreg |= DMA_EN;
 785
 786         host->req_in_progress = 1;
 787
 788         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 789         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 790 }
 791
 792 static int
 793 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 794 {
 795         if (data->flags & MMC_DATA_WRITE)
 796                 return DMA_TO_DEVICE;
 797         else
 798                 return DMA_FROM_DEVICE;
 799 }
 800
 801 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
 802         struct mmc_data *data)
 803 {
 804         return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
 805 }
 806
 807 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 808 {
 809         int dma_ch;
 810         unsigned long flags;
 811
 812         spin_lock_irqsave(&host->irq_lock, flags);
 813         host->req_in_progress = 0;
 814         dma_ch = host->dma_ch;
 815         spin_unlock_irqrestore(&host->irq_lock, flags);
 816
 817         omap_hsmmc_disable_irq(host);
 818         /* Do not complete the request if DMA is still in progress */
 819         if (mrq->data && host->use_dma && dma_ch != -1)
 820                 return;
 821         host->mrq = NULL;
 822         mmc_request_done(host->mmc, mrq);
 823 }
 824
 825 /*
 826  * Notify the transfer complete to MMC core
 827  */
 828 static void
 829 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 830 {
 831         if (!data) {
 832                 struct mmc_request *mrq = host->mrq;
 833
 834                 /* TC before CC from CMD6 - don't know why, but it happens */
 835                 if (host->cmd && host->cmd->opcode == 6 &&
 836                     host->response_busy) {
 837                         host->response_busy = 0;
 838                         return;
 839                 }
 840
 841                 omap_hsmmc_request_done(host, mrq);
 842                 return;
 843         }
 844
 845         host->data = NULL;
 846
 847         if (!data->error)
 848                 data->bytes_xfered += data->blocks * (data->blksz);
 849         else
 850                 data->bytes_xfered = 0;
 851
 852         if (!data->stop) {
 853                 omap_hsmmc_request_done(host, data->mrq);
 854                 return;
 855         }
 856         omap_hsmmc_start_command(host, data->stop, NULL);
 857 }
 858
 859 /*
 860  * Notify the core about command completion
 861  */
 862 static void
 863 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 864 {
 865         host->cmd = NULL;
 866
 867         if (cmd->flags & MMC_RSP_PRESENT) {
 868                 if (cmd->flags & MMC_RSP_136) {
 869                         /* response type 2 */
 870                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 871                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 872                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 873                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 874                 } else {
 875                         /* response types 1, 1b, 3, 4, 5, 6 */
 876                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 877                 }
 878         }
 879         if ((host->data == NULL && !host->response_busy) || cmd->error)
 880                 omap_hsmmc_request_done(host, cmd->mrq);
 881 }
 882
 883 /*
 884  * DMA clean up for command errors
 885  */
 886 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 887 {
 888         int dma_ch;
 889         unsigned long flags;
 890
 891         host->data->error = errno;
 892
 893         spin_lock_irqsave(&host->irq_lock, flags);
 894         dma_ch = host->dma_ch;
 895         host->dma_ch = -1;
 896         spin_unlock_irqrestore(&host->irq_lock, flags);
 897
 898         if (host->use_dma && dma_ch != -1) {
 899                 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
 900
 901                 dmaengine_terminate_all(chan);
 902                 dma_unmap_sg(chan->device->dev,
 903                         host->data->sg, host->data->sg_len,
 904                         omap_hsmmc_get_dma_dir(host, host->data));
 905
 906                 host->data->host_cookie = 0;
 907         }
 908         host->data = NULL;
 909 }
 910
 911 /*
 912  * Readable error output
 913  */
 914 #ifdef CONFIG_MMC_DEBUG
 915 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 916 {
 917         /* --- means reserved bit without definition at documentation */
 918         static const char *omap_hsmmc_status_bits[] = {
 919                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 920                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 921                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 922                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 923         };
 924         char res[256];
 925         char *buf = res;
 926         int len, i;
 927
 928         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 929         buf += len;
 930
 931         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 932                 if (status & (1 << i)) {
 933                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 934                         buf += len;
 935                 }
 936
 937         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 938 }
 939 #else
 940 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 941                                              u32 status)
 942 {
 943 }
 944 #endif  /* CONFIG_MMC_DEBUG */
 945
 946 /*
 947  * MMC controller internal state machines reset
 948  *
 949  * Used to reset command or data internal state machines, using respectively
 950  *  SRC or SRD bit of SYSCTL register
 951  * Can be called from interrupt context
 952  */
 953 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 954                                                    unsigned long bit)
 955 {
 956         unsigned long i = 0;
 957         unsigned long limit = (loops_per_jiffy *
 958                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 959
 960         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 961                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 962
 963         /*
 964          * OMAP4 ES2 and greater has an updated reset logic.
 965          * Monitor a 0->1 transition first
 966          */
 967         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 968                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 969                                         && (i++ < limit))
 970                         cpu_relax();
 971         }
 972         i = 0;
 973
 974         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 975                 (i++ < limit))
 976                 cpu_relax();
 977
 978         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 979                 dev_err(mmc_dev(host->mmc),
 980                         "Timeout waiting on controller reset in %s\n",
 981                         __func__);
 982 }
 983
 984 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 985 {
 986         struct mmc_data *data;
 987         int end_cmd = 0, end_trans = 0;
 988
 989         if (!host->req_in_progress) {
 990                 do {
 991                         OMAP_HSMMC_WRITE(host->base, STAT, status);
 992                         /* Flush posted write */
 993                         status = OMAP_HSMMC_READ(host->base, STAT);
 994                 } while (status & INT_EN_MASK);
 995                 return;
 996         }
 997
 998         data = host->data;
 999         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1000
1001         if (status & ERR) {
1002                 omap_hsmmc_dbg_report_irq(host, status);
1003                 if ((status & CMD_TIMEOUT) ||
1004                         (status & CMD_CRC)) {
1005                         if (host->cmd) {
1006                                 if (status & CMD_TIMEOUT) {
1007                                         omap_hsmmc_reset_controller_fsm(host,
1008                                                                         SRC);
1009                                         host->cmd->error = -ETIMEDOUT;
1010                                 } else {
1011                                         host->cmd->error = -EILSEQ;
1012                                 }
1013                                 end_cmd = 1;
1014                         }
1015                         if (host->data || host->response_busy) {
1016                                 if (host->data)
1017                                         omap_hsmmc_dma_cleanup(host,
1018                                                                 -ETIMEDOUT);
1019                                 host->response_busy = 0;
1020                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1021                         }
1022                 }
1023                 if ((status & DATA_TIMEOUT) ||
1024                         (status & DATA_CRC)) {
1025                         if (host->data || host->response_busy) {
1026                                 int err = (status & DATA_TIMEOUT) ?
1027                                                 -ETIMEDOUT : -EILSEQ;
1028
1029                                 if (host->data)
1030                                         omap_hsmmc_dma_cleanup(host, err);
1031                                 else
1032                                         host->mrq->cmd->error = err;
1033                                 host->response_busy = 0;
1034                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1035                                 end_trans = 1;
1036                         }
1037                 }
1038                 if (status & CARD_ERR) {
1039                         dev_dbg(mmc_dev(host->mmc),
1040                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1041                         if (host->cmd)
1042                                 end_cmd = 1;
1043                         if (host->data)
1044                                 end_trans = 1;
1045                 }
1046         }
1047
1048         OMAP_HSMMC_WRITE(host->base, STAT, status);
1049
1050         if (end_cmd || ((status & CC) && host->cmd))
1051                 omap_hsmmc_cmd_done(host, host->cmd);
1052         if ((end_trans || (status & TC)) && host->mrq)
1053                 omap_hsmmc_xfer_done(host, data);
1054 }
1055
1056 /*
1057  * MMC controller IRQ handler
1058  */
1059 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1060 {
1061         struct omap_hsmmc_host *host = dev_id;
1062         int status;
1063
1064         status = OMAP_HSMMC_READ(host->base, STAT);
1065         do {
1066                 omap_hsmmc_do_irq(host, status);
1067                 /* Flush posted write */
1068                 status = OMAP_HSMMC_READ(host->base, STAT);
1069         } while (status & INT_EN_MASK);
1070
1071         return IRQ_HANDLED;
1072 }
1073
1074 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1075 {
1076         unsigned long i;
1077
1078         OMAP_HSMMC_WRITE(host->base, HCTL,
1079                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1080         for (i = 0; i < loops_per_jiffy; i++) {
1081                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1082                         break;
1083                 cpu_relax();
1084         }
1085 }
1086
1087 /*
1088  * Switch MMC interface voltage ... only relevant for MMC1.
1089  *
1090  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1091  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1092  * Some chips, like eMMC ones, use internal transceivers.
1093  */
1094 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1095 {
1096         u32 reg_val = 0;
1097         int ret;
1098
1099         /* Disable the clocks */
1100         pm_runtime_put_sync(host->dev);
1101         if (host->dbclk)
1102                 clk_disable_unprepare(host->dbclk);
1103
1104         /* Turn the power off */
1105         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1106
1107         /* Turn the power ON with given VDD 1.8 or 3.0v */
1108         if (!ret)
1109                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1110                                                vdd);
1111         pm_runtime_get_sync(host->dev);
1112         if (host->dbclk)
1113                 clk_prepare_enable(host->dbclk);
1114
1115         if (ret != 0)
1116                 goto err;
1117
1118         OMAP_HSMMC_WRITE(host->base, HCTL,
1119                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1120         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1121
1122         /*
1123          * If a MMC dual voltage card is detected, the set_ios fn calls
1124          * this fn with VDD bit set for 1.8V. Upon card removal from the
1125          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1126          *
1127          * Cope with a bit of slop in the range ... per data sheets:
1128          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1129          *    but recommended values are 1.71V to 1.89V
1130          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1131          *    but recommended values are 2.7V to 3.3V
1132          *
1133          * Board setup code shouldn't permit anything very out-of-range.
1134          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1135          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1136          */
1137         if ((1 << vdd) <= MMC_VDD_23_24)
1138                 reg_val |= SDVS18;
1139         else
1140                 reg_val |= SDVS30;
1141
1142         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1143         set_sd_bus_power(host);
1144
1145         return 0;
1146 err:
1147         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1148         return ret;
1149 }
1150
1151 /* Protect the card while the cover is open */
1152 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1153 {
1154         if (!mmc_slot(host).get_cover_state)
1155                 return;
1156
1157         host->reqs_blocked = 0;
1158         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1159                 if (host->protect_card) {
1160                         dev_info(host->dev, "%s: cover is closed, "
1161                                          "card is now accessible\n",
1162                                          mmc_hostname(host->mmc));
1163                         host->protect_card = 0;
1164                 }
1165         } else {
1166                 if (!host->protect_card) {
1167                         dev_info(host->dev, "%s: cover is open, "
1168                                          "card is now inaccessible\n",
1169                                          mmc_hostname(host->mmc));
1170                         host->protect_card = 1;
1171                 }
1172         }
1173 }
1174
1175 /*
1176  * irq handler to notify the core about card insertion/removal
1177  */
1178 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1179 {
1180         struct omap_hsmmc_host *host = dev_id;
1181         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1182         int carddetect;
1183
1184         if (host->suspended)
1185                 return IRQ_HANDLED;
1186
1187         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1188
1189         if (slot->card_detect)
1190                 carddetect = slot->card_detect(host->dev, host->slot_id);
1191         else {
1192                 omap_hsmmc_protect_card(host);
1193                 carddetect = -ENOSYS;
1194         }
1195
1196         if (carddetect)
1197                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1198         else
1199                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1200         return IRQ_HANDLED;
1201 }
1202
1203 static void omap_hsmmc_dma_callback(void *param)
1204 {
1205         struct omap_hsmmc_host *host = param;
1206         struct dma_chan *chan;
1207         struct mmc_data *data;
1208         int req_in_progress;
1209
1210         spin_lock_irq(&host->irq_lock);
1211         if (host->dma_ch < 0) {
1212                 spin_unlock_irq(&host->irq_lock);
1213                 return;
1214         }
1215
1216         data = host->mrq->data;
1217         chan = omap_hsmmc_get_dma_chan(host, data);
1218         if (!data->host_cookie)
1219                 dma_unmap_sg(chan->device->dev,
1220                              data->sg, data->sg_len,
1221                              omap_hsmmc_get_dma_dir(host, data));
1222
1223         req_in_progress = host->req_in_progress;
1224         host->dma_ch = -1;
1225         spin_unlock_irq(&host->irq_lock);
1226
1227         /* If DMA has finished after TC, complete the request */
1228         if (!req_in_progress) {
1229                 struct mmc_request *mrq = host->mrq;
1230
1231                 host->mrq = NULL;
1232                 mmc_request_done(host->mmc, mrq);
1233         }
1234 }
1235
1236 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1237                                        struct mmc_data *data,
1238                                        struct omap_hsmmc_next *next,
1239                                        struct dma_chan *chan)
1240 {
1241         int dma_len;
1242
1243         if (!next && data->host_cookie &&
1244             data->host_cookie != host->next_data.cookie) {
1245                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1246                        " host->next_data.cookie %d\n",
1247                        __func__, data->host_cookie, host->next_data.cookie);
1248                 data->host_cookie = 0;
1249         }
1250
1251         /* Check if next job is already prepared */
1252         if (next ||
1253             (!next && data->host_cookie != host->next_data.cookie)) {
1254                 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1255                                      omap_hsmmc_get_dma_dir(host, data));
1256
1257         } else {
1258                 dma_len = host->next_data.dma_len;
1259                 host->next_data.dma_len = 0;
1260         }
1261
1262
1263         if (dma_len == 0)
1264                 return -EINVAL;
1265
1266         if (next) {
1267                 next->dma_len = dma_len;
1268                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1269         } else
1270                 host->dma_len = dma_len;
1271
1272         return 0;
1273 }
1274
1275 /*
1276  * Routine to configure and start DMA for the MMC card
1277  */
1278 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1279                                         struct mmc_request *req)
1280 {
1281         struct dma_slave_config cfg;
1282         struct dma_async_tx_descriptor *tx;
1283         int ret = 0, i;
1284         struct mmc_data *data = req->data;
1285         struct dma_chan *chan;
1286
1287         /* Sanity check: all the SG entries must be aligned by block size. */
1288         for (i = 0; i < data->sg_len; i++) {
1289                 struct scatterlist *sgl;
1290
1291                 sgl = data->sg + i;
1292                 if (sgl->length % data->blksz)
1293                         return -EINVAL;
1294         }
1295         if ((data->blksz % 4) != 0)
1296                 /* REVISIT: The MMC buffer increments only when MSB is written.
1297                  * Return error for blksz which is non multiple of four.
1298                  */
1299                 return -EINVAL;
1300
1301         BUG_ON(host->dma_ch != -1);
1302
1303         chan = omap_hsmmc_get_dma_chan(host, data);
1304
1305         cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1306         cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1307         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1308         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1309         cfg.src_maxburst = data->blksz / 4;
1310         cfg.dst_maxburst = data->blksz / 4;
1311
1312         ret = dmaengine_slave_config(chan, &cfg);
1313         if (ret)
1314                 return ret;
1315
1316         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1317         if (ret)
1318                 return ret;
1319
1320         tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1321                 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1322                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1323         if (!tx) {
1324                 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1325                 /* FIXME: cleanup */
1326                 return -1;
1327         }
1328
1329         tx->callback = omap_hsmmc_dma_callback;
1330         tx->callback_param = host;
1331
1332         /* Does not fail */
1333         dmaengine_submit(tx);
1334
1335         host->dma_ch = 1;
1336
1337         dma_async_issue_pending(chan);
1338
1339         return 0;
1340 }
1341
1342 static void set_data_timeout(struct omap_hsmmc_host *host,
1343                              unsigned int timeout_ns,
1344                              unsigned int timeout_clks)
1345 {
1346         unsigned int timeout, cycle_ns;
1347         uint32_t reg, clkd, dto = 0;
1348
1349         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1350         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1351         if (clkd == 0)
1352                 clkd = 1;
1353
1354         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1355         timeout = timeout_ns / cycle_ns;
1356         timeout += timeout_clks;
1357         if (timeout) {
1358                 while ((timeout & 0x80000000) == 0) {
1359                         dto += 1;
1360                         timeout <<= 1;
1361                 }
1362                 dto = 31 - dto;
1363                 timeout <<= 1;
1364                 if (timeout && dto)
1365                         dto += 1;
1366                 if (dto >= 13)
1367                         dto -= 13;
1368                 else
1369                         dto = 0;
1370                 if (dto > 14)
1371                         dto = 14;
1372         }
1373
1374         reg &= ~DTO_MASK;
1375         reg |= dto << DTO_SHIFT;
1376         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1377 }
1378
1379 /*
1380  * Configure block length for MMC/SD cards and initiate the transfer.
1381  */
1382 static int
1383 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1384 {
1385         int ret;
1386         host->data = req->data;
1387
1388         if (req->data == NULL) {
1389                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1390                 /*
1391                  * Set an arbitrary 100ms data timeout for commands with
1392                  * busy signal.
1393                  */
1394                 if (req->cmd->flags & MMC_RSP_BUSY)
1395                         set_data_timeout(host, 100000000U, 0);
1396                 return 0;
1397         }
1398
1399         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1400                                         | (req->data->blocks << 16));
1401         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1402
1403         if (host->use_dma) {
1404                 ret = omap_hsmmc_start_dma_transfer(host, req);
1405                 if (ret != 0) {
1406                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1407                         return ret;
1408                 }
1409         }
1410         return 0;
1411 }
1412
1413 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1414                                 int err)
1415 {
1416         struct omap_hsmmc_host *host = mmc_priv(mmc);
1417         struct mmc_data *data = mrq->data;
1418
1419         if (host->use_dma && data->host_cookie) {
1420                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1421
1422                 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1423                              omap_hsmmc_get_dma_dir(host, data));
1424                 data->host_cookie = 0;
1425         }
1426 }
1427
1428 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1429                                bool is_first_req)
1430 {
1431         struct omap_hsmmc_host *host = mmc_priv(mmc);
1432
1433         if (mrq->data->host_cookie) {
1434                 mrq->data->host_cookie = 0;
1435                 return ;
1436         }
1437
1438         if (host->use_dma) {
1439                 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1440
1441                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1442                                                 &host->next_data, c))
1443                         mrq->data->host_cookie = 0;
1444         }
1445 }
1446
1447 /*
1448  * Request function. for read/write operation
1449  */
1450 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1451 {
1452         struct omap_hsmmc_host *host = mmc_priv(mmc);
1453         int err;
1454
1455         BUG_ON(host->req_in_progress);
1456         BUG_ON(host->dma_ch != -1);
1457         if (host->protect_card) {
1458                 if (host->reqs_blocked < 3) {
1459                         /*
1460                          * Ensure the controller is left in a consistent
1461                          * state by resetting the command and data state
1462                          * machines.
1463                          */
1464                         omap_hsmmc_reset_controller_fsm(host, SRD);
1465                         omap_hsmmc_reset_controller_fsm(host, SRC);
1466                         host->reqs_blocked += 1;
1467                 }
1468                 req->cmd->error = -EBADF;
1469                 if (req->data)
1470                         req->data->error = -EBADF;
1471                 req->cmd->retries = 0;
1472                 mmc_request_done(mmc, req);
1473                 return;
1474         } else if (host->reqs_blocked)
1475                 host->reqs_blocked = 0;
1476         WARN_ON(host->mrq != NULL);
1477         host->mrq = req;
1478         err = omap_hsmmc_prepare_data(host, req);
1479         if (err) {
1480                 req->cmd->error = err;
1481                 if (req->data)
1482                         req->data->error = err;
1483                 host->mrq = NULL;
1484                 mmc_request_done(mmc, req);
1485                 return;
1486         }
1487
1488         omap_hsmmc_start_command(host, req->cmd, req->data);
1489 }
1490
1491 /* Routine to configure clock values. Exposed API to core */
1492 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1493 {
1494         struct omap_hsmmc_host *host = mmc_priv(mmc);
1495         int do_send_init_stream = 0;
1496
1497         pm_runtime_get_sync(host->dev);
1498
1499         if (ios->power_mode != host->power_mode) {
1500                 switch (ios->power_mode) {
1501                 case MMC_POWER_OFF:
1502                         mmc_slot(host).set_power(host->dev, host->slot_id,
1503                                                  0, 0);
1504                         host->vdd = 0;
1505                         break;
1506                 case MMC_POWER_UP:
1507                         mmc_slot(host).set_power(host->dev, host->slot_id,
1508                                                  1, ios->vdd);
1509                         host->vdd = ios->vdd;
1510                         break;
1511                 case MMC_POWER_ON:
1512                         do_send_init_stream = 1;
1513                         break;
1514                 }
1515                 host->power_mode = ios->power_mode;
1516         }
1517
1518         /* FIXME: set registers based only on changes to ios */
1519
1520         omap_hsmmc_set_bus_width(host);
1521
1522         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1523                 /* Only MMC1 can interface at 3V without some flavor
1524                  * of external transceiver; but they all handle 1.8V.
1525                  */
1526                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1527                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1528                         /*
1529                          * With pbias cell programming missing, this
1530                          * can't be allowed when booting with device
1531                          * tree.
1532                          */
1533                         !host->dev->of_node) {
1534                                 /*
1535                                  * The mmc_select_voltage fn of the core does
1536                                  * not seem to set the power_mode to
1537                                  * MMC_POWER_UP upon recalculating the voltage.
1538                                  * vdd 1.8v.
1539                                  */
1540                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1541                                 dev_dbg(mmc_dev(host->mmc),
1542                                                 "Switch operation failed\n");
1543                 }
1544         }
1545
1546         omap_hsmmc_set_clock(host);
1547
1548         if (do_send_init_stream)
1549                 send_init_stream(host);
1550
1551         omap_hsmmc_set_bus_mode(host);
1552
1553         pm_runtime_put_autosuspend(host->dev);
1554 }
1555
1556 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1557 {
1558         struct omap_hsmmc_host *host = mmc_priv(mmc);
1559
1560         if (!mmc_slot(host).card_detect)
1561                 return -ENOSYS;
1562         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1563 }
1564
1565 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1566 {
1567         struct omap_hsmmc_host *host = mmc_priv(mmc);
1568
1569         if (!mmc_slot(host).get_ro)
1570                 return -ENOSYS;
1571         return mmc_slot(host).get_ro(host->dev, 0);
1572 }
1573
1574 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1575 {
1576         struct omap_hsmmc_host *host = mmc_priv(mmc);
1577
1578         if (mmc_slot(host).init_card)
1579                 mmc_slot(host).init_card(card);
1580 }
1581
1582 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1583 {
1584         u32 hctl, capa, value;
1585
1586         /* Only MMC1 supports 3.0V */
1587         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1588                 hctl = SDVS30;
1589                 capa = VS30 | VS18;
1590         } else {
1591                 hctl = SDVS18;
1592                 capa = VS18;
1593         }
1594
1595         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1596         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1597
1598         value = OMAP_HSMMC_READ(host->base, CAPA);
1599         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1600
1601         /* Set the controller to AUTO IDLE mode */
1602         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1603         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1604
1605         /* Set SD bus power bit */
1606         set_sd_bus_power(host);
1607 }
1608
1609 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1610 {
1611         struct omap_hsmmc_host *host = mmc_priv(mmc);
1612
1613         pm_runtime_get_sync(host->dev);
1614
1615         return 0;
1616 }
1617
1618 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1619 {
1620         struct omap_hsmmc_host *host = mmc_priv(mmc);
1621
1622         pm_runtime_mark_last_busy(host->dev);
1623         pm_runtime_put_autosuspend(host->dev);
1624
1625         return 0;
1626 }
1627
1628 static const struct mmc_host_ops omap_hsmmc_ops = {
1629         .enable = omap_hsmmc_enable_fclk,
1630         .disable = omap_hsmmc_disable_fclk,
1631         .post_req = omap_hsmmc_post_req,
1632         .pre_req = omap_hsmmc_pre_req,
1633         .request = omap_hsmmc_request,
1634         .set_ios = omap_hsmmc_set_ios,
1635         .get_cd = omap_hsmmc_get_cd,
1636         .get_ro = omap_hsmmc_get_ro,
1637         .init_card = omap_hsmmc_init_card,
1638         /* NYET -- enable_sdio_irq */
1639 };
1640
1641 #ifdef CONFIG_DEBUG_FS
1642
1643 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1644 {
1645         struct mmc_host *mmc = s->private;
1646         struct omap_hsmmc_host *host = mmc_priv(mmc);
1647         int context_loss = 0;
1648
1649         if (host->pdata->get_context_loss_count)
1650                 context_loss = host->pdata->get_context_loss_count(host->dev);
1651
1652         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1653                         mmc->index, host->context_loss, context_loss);
1654
1655         if (host->suspended) {
1656                 seq_printf(s, "host suspended, can't read registers\n");
1657                 return 0;
1658         }
1659
1660         pm_runtime_get_sync(host->dev);
1661
1662         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1663                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1664         seq_printf(s, "CON:\t\t0x%08x\n",
1665                         OMAP_HSMMC_READ(host->base, CON));
1666         seq_printf(s, "HCTL:\t\t0x%08x\n",
1667                         OMAP_HSMMC_READ(host->base, HCTL));
1668         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1669                         OMAP_HSMMC_READ(host->base, SYSCTL));
1670         seq_printf(s, "IE:\t\t0x%08x\n",
1671                         OMAP_HSMMC_READ(host->base, IE));
1672         seq_printf(s, "ISE:\t\t0x%08x\n",
1673                         OMAP_HSMMC_READ(host->base, ISE));
1674         seq_printf(s, "CAPA:\t\t0x%08x\n",
1675                         OMAP_HSMMC_READ(host->base, CAPA));
1676
1677         pm_runtime_mark_last_busy(host->dev);
1678         pm_runtime_put_autosuspend(host->dev);
1679
1680         return 0;
1681 }
1682
1683 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1684 {
1685         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1686 }
1687
1688 static const struct file_operations mmc_regs_fops = {
1689         .open           = omap_hsmmc_regs_open,
1690         .read           = seq_read,
1691         .llseek         = seq_lseek,
1692         .release        = single_release,
1693 };
1694
1695 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1696 {
1697         if (mmc->debugfs_root)
1698                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1699                         mmc, &mmc_regs_fops);
1700 }
1701
1702 #else
1703
1704 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1705 {
1706 }
1707
1708 #endif
1709
1710 #ifdef CONFIG_OF
1711 static u16 omap4_reg_offset = 0x100;
1712
1713 static const struct of_device_id omap_mmc_of_match[] = {
1714         {
1715                 .compatible = "ti,omap2-hsmmc",
1716         },
1717         {
1718                 .compatible = "ti,omap3-hsmmc",
1719         },
1720         {
1721                 .compatible = "ti,omap4-hsmmc",
1722                 .data = &omap4_reg_offset,
1723         },
1724         {},
1725 };
1726 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1727
1728 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1729 {
1730         struct omap_mmc_platform_data *pdata;
1731         struct device_node *np = dev->of_node;
1732         u32 bus_width;
1733
1734         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1735         if (!pdata)
1736                 return NULL; /* out of memory */
1737
1738         if (of_find_property(np, "ti,dual-volt", NULL))
1739                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1740
1741         /* This driver only supports 1 slot */
1742         pdata->nr_slots = 1;
1743         pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1744         pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1745
1746         if (of_find_property(np, "ti,non-removable", NULL)) {
1747                 pdata->slots[0].nonremovable = true;
1748                 pdata->slots[0].no_regulator_off_init = true;
1749         }
1750         of_property_read_u32(np, "bus-width", &bus_width);
1751         if (bus_width == 4)
1752                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1753         else if (bus_width == 8)
1754                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1755
1756         if (of_find_property(np, "ti,needs-special-reset", NULL))
1757                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1758
1759         return pdata;
1760 }
1761 #else
1762 static inline struct omap_mmc_platform_data
1763                         *of_get_hsmmc_pdata(struct device *dev)
1764 {
1765         return NULL;
1766 }
1767 #endif
1768
1769 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1770 {
1771         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1772         struct mmc_host *mmc;
1773         struct omap_hsmmc_host *host = NULL;
1774         struct resource *res;
1775         int ret, irq;
1776         const struct of_device_id *match;
1777         dma_cap_mask_t mask;
1778         unsigned tx_req, rx_req;
1779
1780         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1781         if (match) {
1782                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1783                 if (match->data) {
1784                         u16 *offsetp = match->data;
1785                         pdata->reg_offset = *offsetp;
1786                 }
1787         }
1788
1789         if (pdata == NULL) {
1790                 dev_err(&pdev->dev, "Platform Data is missing\n");
1791                 return -ENXIO;
1792         }
1793
1794         if (pdata->nr_slots == 0) {
1795                 dev_err(&pdev->dev, "No Slots\n");
1796                 return -ENXIO;
1797         }
1798
1799         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1800         irq = platform_get_irq(pdev, 0);
1801         if (res == NULL || irq < 0)
1802                 return -ENXIO;
1803
1804         res = request_mem_region(res->start, resource_size(res), pdev->name);
1805         if (res == NULL)
1806                 return -EBUSY;
1807
1808         ret = omap_hsmmc_gpio_init(pdata);
1809         if (ret)
1810                 goto err;
1811
1812         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1813         if (!mmc) {
1814                 ret = -ENOMEM;
1815                 goto err_alloc;
1816         }
1817
1818         host            = mmc_priv(mmc);
1819         host->mmc       = mmc;
1820         host->pdata     = pdata;
1821         host->dev       = &pdev->dev;
1822         host->use_dma   = 1;
1823         host->dma_ch    = -1;
1824         host->irq       = irq;
1825         host->slot_id   = 0;
1826         host->mapbase   = res->start + pdata->reg_offset;
1827         host->base      = ioremap(host->mapbase, SZ_4K);
1828         host->power_mode = MMC_POWER_OFF;
1829         host->next_data.cookie = 1;
1830
1831         platform_set_drvdata(pdev, host);
1832
1833         mmc->ops        = &omap_hsmmc_ops;
1834
1835         /*
1836          * If regulator_disable can only put vcc_aux to sleep then there is
1837          * no off state.
1838          */
1839         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1840                 mmc_slot(host).no_off = 1;
1841
1842         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1843
1844         if (pdata->max_freq > 0)
1845                 mmc->f_max = pdata->max_freq;
1846         else
1847                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1848
1849         spin_lock_init(&host->irq_lock);
1850
1851         host->fclk = clk_get(&pdev->dev, "fck");
1852         if (IS_ERR(host->fclk)) {
1853                 ret = PTR_ERR(host->fclk);
1854                 host->fclk = NULL;
1855                 goto err1;
1856         }
1857
1858         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1859                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1860                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1861         }
1862
1863         pm_runtime_enable(host->dev);
1864         pm_runtime_get_sync(host->dev);
1865         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1866         pm_runtime_use_autosuspend(host->dev);
1867
1868         omap_hsmmc_context_save(host);
1869
1870         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1871         /*
1872          * MMC can still work without debounce clock.
1873          */
1874         if (IS_ERR(host->dbclk)) {
1875                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1876                 host->dbclk = NULL;
1877         } else if (clk_prepare_enable(host->dbclk) != 0) {
1878                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1879                 clk_put(host->dbclk);
1880                 host->dbclk = NULL;
1881         }
1882
1883         /* Since we do only SG emulation, we can have as many segs
1884          * as we want. */
1885         mmc->max_segs = 1024;
1886
1887         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1888         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1889         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1890         mmc->max_seg_size = mmc->max_req_size;
1891
1892         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1893                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1894
1895         mmc->caps |= mmc_slot(host).caps;
1896         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1897                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1898
1899         if (mmc_slot(host).nonremovable)
1900                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1901
1902         mmc->pm_caps = mmc_slot(host).pm_caps;
1903
1904         omap_hsmmc_conf_bus_power(host);
1905
1906         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1907         if (!res) {
1908                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1909                 ret = -ENXIO;
1910                 goto err_irq;
1911         }
1912         tx_req = res->start;
1913
1914         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1915         if (!res) {
1916                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1917                 ret = -ENXIO;
1918                 goto err_irq;
1919         }
1920         rx_req = res->start;
1921
1922         dma_cap_zero(mask);
1923         dma_cap_set(DMA_SLAVE, mask);
1924
1925         host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1926         if (!host->rx_chan) {
1927                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1928                 ret = -ENXIO;
1929                 goto err_irq;
1930         }
1931
1932         host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1933         if (!host->tx_chan) {
1934                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1935                 ret = -ENXIO;
1936                 goto err_irq;
1937         }
1938
1939         /* Request IRQ for MMC operations */
1940         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1941                         mmc_hostname(mmc), host);
1942         if (ret) {
1943                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1944                 goto err_irq;
1945         }
1946
1947         if (pdata->init != NULL) {
1948                 if (pdata->init(&pdev->dev) != 0) {
1949                         dev_dbg(mmc_dev(host->mmc),
1950                                 "Unable to configure MMC IRQs\n");
1951                         goto err_irq_cd_init;
1952                 }
1953         }
1954
1955         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1956                 ret = omap_hsmmc_reg_get(host);
1957                 if (ret)
1958                         goto err_reg;
1959                 host->use_reg = 1;
1960         }
1961
1962         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1963
1964         /* Request IRQ for card detect */
1965         if ((mmc_slot(host).card_detect_irq)) {
1966                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1967                                            NULL,
1968                                            omap_hsmmc_detect,
1969                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1970                                            mmc_hostname(mmc), host);
1971                 if (ret) {
1972                         dev_dbg(mmc_dev(host->mmc),
1973                                 "Unable to grab MMC CD IRQ\n");
1974                         goto err_irq_cd;
1975                 }
1976                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1977                 pdata->resume = omap_hsmmc_resume_cdirq;
1978         }
1979
1980         omap_hsmmc_disable_irq(host);
1981
1982         omap_hsmmc_protect_card(host);
1983
1984         mmc_add_host(mmc);
1985
1986         if (mmc_slot(host).name != NULL) {
1987                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1988                 if (ret < 0)
1989                         goto err_slot_name;
1990         }
1991         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1992                 ret = device_create_file(&mmc->class_dev,
1993                                         &dev_attr_cover_switch);
1994                 if (ret < 0)
1995                         goto err_slot_name;
1996         }
1997
1998         omap_hsmmc_debugfs(mmc);
1999         pm_runtime_mark_last_busy(host->dev);
2000         pm_runtime_put_autosuspend(host->dev);
2001
2002         return 0;
2003
2004 err_slot_name:
2005         mmc_remove_host(mmc);
2006         free_irq(mmc_slot(host).card_detect_irq, host);
2007 err_irq_cd:
2008         if (host->use_reg)
2009                 omap_hsmmc_reg_put(host);
2010 err_reg:
2011         if (host->pdata->cleanup)
2012                 host->pdata->cleanup(&pdev->dev);
2013 err_irq_cd_init:
2014         free_irq(host->irq, host);
2015 err_irq:
2016         if (host->tx_chan)
2017                 dma_release_channel(host->tx_chan);
2018         if (host->rx_chan)
2019                 dma_release_channel(host->rx_chan);
2020         pm_runtime_put_sync(host->dev);
2021         pm_runtime_disable(host->dev);
2022         clk_put(host->fclk);
2023         if (host->dbclk) {
2024                 clk_disable_unprepare(host->dbclk);
2025                 clk_put(host->dbclk);
2026         }
2027 err1:
2028         iounmap(host->base);
2029         platform_set_drvdata(pdev, NULL);
2030         mmc_free_host(mmc);
2031 err_alloc:
2032         omap_hsmmc_gpio_free(pdata);
2033 err:
2034         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2035         if (res)
2036                 release_mem_region(res->start, resource_size(res));
2037         return ret;
2038 }
2039
2040 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
2041 {
2042         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2043         struct resource *res;
2044
2045         pm_runtime_get_sync(host->dev);
2046         mmc_remove_host(host->mmc);
2047         if (host->use_reg)
2048                 omap_hsmmc_reg_put(host);
2049         if (host->pdata->cleanup)
2050                 host->pdata->cleanup(&pdev->dev);
2051         free_irq(host->irq, host);
2052         if (mmc_slot(host).card_detect_irq)
2053                 free_irq(mmc_slot(host).card_detect_irq, host);
2054
2055         if (host->tx_chan)
2056                 dma_release_channel(host->tx_chan);
2057         if (host->rx_chan)
2058                 dma_release_channel(host->rx_chan);
2059
2060         pm_runtime_put_sync(host->dev);
2061         pm_runtime_disable(host->dev);
2062         clk_put(host->fclk);
2063         if (host->dbclk) {
2064                 clk_disable_unprepare(host->dbclk);
2065                 clk_put(host->dbclk);
2066         }
2067
2068         mmc_free_host(host->mmc);
2069         iounmap(host->base);
2070         omap_hsmmc_gpio_free(pdev->dev.platform_data);
2071
2072         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2073         if (res)
2074                 release_mem_region(res->start, resource_size(res));
2075         platform_set_drvdata(pdev, NULL);
2076
2077         return 0;
2078 }
2079
2080 #ifdef CONFIG_PM
2081 static int omap_hsmmc_suspend(struct device *dev)
2082 {
2083         int ret = 0;
2084         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2085
2086         if (!host)
2087                 return 0;
2088
2089         if (host && host->suspended)
2090                 return 0;
2091
2092         pm_runtime_get_sync(host->dev);
2093         host->suspended = 1;
2094         if (host->pdata->suspend) {
2095                 ret = host->pdata->suspend(dev, host->slot_id);
2096                 if (ret) {
2097                         dev_dbg(dev, "Unable to handle MMC board"
2098                                         " level suspend\n");
2099                         host->suspended = 0;
2100                         return ret;
2101                 }
2102         }
2103         ret = mmc_suspend_host(host->mmc);
2104
2105         if (ret) {
2106                 host->suspended = 0;
2107                 if (host->pdata->resume) {
2108                         ret = host->pdata->resume(dev, host->slot_id);
2109                         if (ret)
2110                                 dev_dbg(dev, "Unmask interrupt failed\n");
2111                 }
2112                 goto err;
2113         }
2114
2115         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2116                 omap_hsmmc_disable_irq(host);
2117                 OMAP_HSMMC_WRITE(host->base, HCTL,
2118                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2119         }
2120
2121         if (host->dbclk)
2122                 clk_disable_unprepare(host->dbclk);
2123 err:
2124         pm_runtime_put_sync(host->dev);
2125         return ret;
2126 }
2127
2128 /* Routine to resume the MMC device */
2129 static int omap_hsmmc_resume(struct device *dev)
2130 {
2131         int ret = 0;
2132         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2133
2134         if (!host)
2135                 return 0;
2136
2137         if (host && !host->suspended)
2138                 return 0;
2139
2140         pm_runtime_get_sync(host->dev);
2141
2142         if (host->dbclk)
2143                 clk_prepare_enable(host->dbclk);
2144
2145         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2146                 omap_hsmmc_conf_bus_power(host);
2147
2148         if (host->pdata->resume) {
2149                 ret = host->pdata->resume(dev, host->slot_id);
2150                 if (ret)
2151                         dev_dbg(dev, "Unmask interrupt failed\n");
2152         }
2153
2154         omap_hsmmc_protect_card(host);
2155
2156         /* Notify the core to resume the host */
2157         ret = mmc_resume_host(host->mmc);
2158         if (ret == 0)
2159                 host->suspended = 0;
2160
2161         pm_runtime_mark_last_busy(host->dev);
2162         pm_runtime_put_autosuspend(host->dev);
2163
2164         return ret;
2165
2166 }
2167
2168 #else
2169 #define omap_hsmmc_suspend      NULL
2170 #define omap_hsmmc_resume               NULL
2171 #endif
2172
2173 static int omap_hsmmc_runtime_suspend(struct device *dev)
2174 {
2175         struct omap_hsmmc_host *host;
2176
2177         host = platform_get_drvdata(to_platform_device(dev));
2178         omap_hsmmc_context_save(host);
2179         dev_dbg(dev, "disabled\n");
2180
2181         return 0;
2182 }
2183
2184 static int omap_hsmmc_runtime_resume(struct device *dev)
2185 {
2186         struct omap_hsmmc_host *host;
2187
2188         host = platform_get_drvdata(to_platform_device(dev));
2189         omap_hsmmc_context_restore(host);
2190         dev_dbg(dev, "enabled\n");
2191
2192         return 0;
2193 }
2194
2195 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2196         .suspend        = omap_hsmmc_suspend,
2197         .resume         = omap_hsmmc_resume,
2198         .runtime_suspend = omap_hsmmc_runtime_suspend,
2199         .runtime_resume = omap_hsmmc_runtime_resume,
2200 };
2201
2202 static struct platform_driver omap_hsmmc_driver = {
2203         .probe          = omap_hsmmc_probe,
2204         .remove         = __devexit_p(omap_hsmmc_remove),
2205         .driver         = {
2206                 .name = DRIVER_NAME,
2207                 .owner = THIS_MODULE,
2208                 .pm = &omap_hsmmc_dev_pm_ops,
2209                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2210         },
2211 };
2212
2213 module_platform_driver(omap_hsmmc_driver);
2214 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2215 MODULE_LICENSE("GPL");
2216 MODULE_ALIAS("platform:" DRIVER_NAME);
2217 MODULE_AUTHOR("Texas Instruments Inc");