drivers/mmc/host/omap_hsmmc.c

   1 /*
   2  * drivers/mmc/host/omap_hsmmc.c
   3  *
   4  * Driver for OMAP2430/3430 MMC controller.
   5  *
   6  * Copyright (C) 2007 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Syed Mohammed Khasim    <x0khasim@ti.com>
  10  *      Madhusudhan             <madhu.cr@ti.com>
  11  *      Mohit Jalori            <mjalori@ti.com>
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/kernel.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/timer.h>
  28 #include <linux/clk.h>
  29 #include <linux/of.h>
  30 #include <linux/of_gpio.h>
  31 #include <linux/of_device.h>
  32 #include <linux/mmc/host.h>
  33 #include <linux/mmc/core.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/io.h>
  36 #include <linux/semaphore.h>
  37 #include <linux/gpio.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/pm_runtime.h>
  40 #include <plat/dma.h>
  41 #include <mach/hardware.h>
  42 #include <plat/board.h>
  43 #include <plat/mmc.h>
  44 #include <plat/cpu.h>
  45
  46 /* OMAP HSMMC Host Controller Registers */
  47 #define OMAP_HSMMC_SYSCONFIG    0x0010
  48 #define OMAP_HSMMC_SYSSTATUS    0x0014
  49 #define OMAP_HSMMC_CON          0x002C
  50 #define OMAP_HSMMC_BLK          0x0104
  51 #define OMAP_HSMMC_ARG          0x0108
  52 #define OMAP_HSMMC_CMD          0x010C
  53 #define OMAP_HSMMC_RSP10        0x0110
  54 #define OMAP_HSMMC_RSP32        0x0114
  55 #define OMAP_HSMMC_RSP54        0x0118
  56 #define OMAP_HSMMC_RSP76        0x011C
  57 #define OMAP_HSMMC_DATA         0x0120
  58 #define OMAP_HSMMC_HCTL         0x0128
  59 #define OMAP_HSMMC_SYSCTL       0x012C
  60 #define OMAP_HSMMC_STAT         0x0130
  61 #define OMAP_HSMMC_IE           0x0134
  62 #define OMAP_HSMMC_ISE          0x0138
  63 #define OMAP_HSMMC_CAPA         0x0140
  64
  65 #define VS18                    (1 << 26)
  66 #define VS30                    (1 << 25)
  67 #define SDVS18                  (0x5 << 9)
  68 #define SDVS30                  (0x6 << 9)
  69 #define SDVS33                  (0x7 << 9)
  70 #define SDVS_MASK               0x00000E00
  71 #define SDVSCLR                 0xFFFFF1FF
  72 #define SDVSDET                 0x00000400
  73 #define AUTOIDLE                0x1
  74 #define SDBP                    (1 << 8)
  75 #define DTO                     0xe
  76 #define ICE                     0x1
  77 #define ICS                     0x2
  78 #define CEN                     (1 << 2)
  79 #define CLKD_MASK               0x0000FFC0
  80 #define CLKD_SHIFT              6
  81 #define DTO_MASK                0x000F0000
  82 #define DTO_SHIFT               16
  83 #define INT_EN_MASK             0x307F0033
  84 #define BWR_ENABLE              (1 << 4)
  85 #define BRR_ENABLE              (1 << 5)
  86 #define DTO_ENABLE              (1 << 20)
  87 #define INIT_STREAM             (1 << 1)
  88 #define DP_SELECT               (1 << 21)
  89 #define DDIR                    (1 << 4)
  90 #define DMA_EN                  0x1
  91 #define MSBS                    (1 << 5)
  92 #define BCE                     (1 << 1)
  93 #define FOUR_BIT                (1 << 1)
  94 #define DDR                     (1 << 19)
  95 #define DW8                     (1 << 5)
  96 #define CC                      0x1
  97 #define TC                      0x02
  98 #define OD                      0x1
  99 #define ERR                     (1 << 15)
 100 #define CMD_TIMEOUT             (1 << 16)
 101 #define DATA_TIMEOUT            (1 << 20)
 102 #define CMD_CRC                 (1 << 17)
 103 #define DATA_CRC                (1 << 21)
 104 #define CARD_ERR                (1 << 28)
 105 #define STAT_CLEAR              0xFFFFFFFF
 106 #define INIT_STREAM_CMD         0x00000000
 107 #define DUAL_VOLT_OCR_BIT       7
 108 #define SRC                     (1 << 25)
 109 #define SRD                     (1 << 26)
 110 #define SOFTRESET               (1 << 1)
 111 #define RESETDONE               (1 << 0)
 112
 113 #define MMC_AUTOSUSPEND_DELAY   100
 114 #define MMC_TIMEOUT_MS          20
 115 #define OMAP_MMC_MIN_CLOCK      400000
 116 #define OMAP_MMC_MAX_CLOCK      52000000
 117 #define DRIVER_NAME             "omap_hsmmc"
 118
 119 /*
 120  * One controller can have multiple slots, like on some omap boards using
 121  * omap.c controller driver. Luckily this is not currently done on any known
 122  * omap_hsmmc.c device.
 123  */
 124 #define mmc_slot(host)          (host->pdata->slots[host->slot_id])
 125
 126 /*
 127  * MMC Host controller read/write API's
 128  */
 129 #define OMAP_HSMMC_READ(base, reg)      \
 130         __raw_readl((base) + OMAP_HSMMC_##reg)
 131
 132 #define OMAP_HSMMC_WRITE(base, reg, val) \
 133         __raw_writel((val), (base) + OMAP_HSMMC_##reg)
 134
 135 struct omap_hsmmc_next {
 136         unsigned int    dma_len;
 137         s32             cookie;
 138 };
 139
 140 struct omap_hsmmc_host {
 141         struct  device          *dev;
 142         struct  mmc_host        *mmc;
 143         struct  mmc_request     *mrq;
 144         struct  mmc_command     *cmd;
 145         struct  mmc_data        *data;
 146         struct  clk             *fclk;
 147         struct  clk             *dbclk;
 148         /*
 149          * vcc == configured supply
 150          * vcc_aux == optional
 151          *   -  MMC1, supply for DAT4..DAT7
 152          *   -  MMC2/MMC2, external level shifter voltage supply, for
 153          *      chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
 154          */
 155         struct  regulator       *vcc;
 156         struct  regulator       *vcc_aux;
 157         void    __iomem         *base;
 158         resource_size_t         mapbase;
 159         spinlock_t              irq_lock; /* Prevent races with irq handler */
 160         unsigned int            dma_len;
 161         unsigned int            dma_sg_idx;
 162         unsigned char           bus_mode;
 163         unsigned char           power_mode;
 164         u32                     *buffer;
 165         u32                     bytesleft;
 166         int                     suspended;
 167         int                     irq;
 168         int                     use_dma, dma_ch;
 169         int                     dma_line_tx, dma_line_rx;
 170         int                     slot_id;
 171         int                     response_busy;
 172         int                     context_loss;
 173         int                     vdd;
 174         int                     protect_card;
 175         int                     reqs_blocked;
 176         int                     use_reg;
 177         int                     req_in_progress;
 178         struct omap_hsmmc_next  next_data;
 179
 180         struct  omap_mmc_platform_data  *pdata;
 181 };
 182
 183 static int omap_hsmmc_card_detect(struct device *dev, int slot)
 184 {
 185         struct omap_mmc_platform_data *mmc = dev->platform_data;
 186
 187         /* NOTE: assumes card detect signal is active-low */
 188         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 189 }
 190
 191 static int omap_hsmmc_get_wp(struct device *dev, int slot)
 192 {
 193         struct omap_mmc_platform_data *mmc = dev->platform_data;
 194
 195         /* NOTE: assumes write protect signal is active-high */
 196         return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
 197 }
 198
 199 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 200 {
 201         struct omap_mmc_platform_data *mmc = dev->platform_data;
 202
 203         /* NOTE: assumes card detect signal is active-low */
 204         return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
 205 }
 206
 207 #ifdef CONFIG_PM
 208
 209 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
 210 {
 211         struct omap_mmc_platform_data *mmc = dev->platform_data;
 212
 213         disable_irq(mmc->slots[0].card_detect_irq);
 214         return 0;
 215 }
 216
 217 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
 218 {
 219         struct omap_mmc_platform_data *mmc = dev->platform_data;
 220
 221         enable_irq(mmc->slots[0].card_detect_irq);
 222         return 0;
 223 }
 224
 225 #else
 226
 227 #define omap_hsmmc_suspend_cdirq        NULL
 228 #define omap_hsmmc_resume_cdirq         NULL
 229
 230 #endif
 231
 232 #ifdef CONFIG_REGULATOR
 233
 234 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
 235                                    int vdd)
 236 {
 237         struct omap_hsmmc_host *host =
 238                 platform_get_drvdata(to_platform_device(dev));
 239         int ret = 0;
 240
 241         /*
 242          * If we don't see a Vcc regulator, assume it's a fixed
 243          * voltage always-on regulator.
 244          */
 245         if (!host->vcc)
 246                 return 0;
 247         /*
 248          * With DT, never turn OFF the regulator. This is because
 249          * the pbias cell programming support is still missing when
 250          * booting with Device tree
 251          */
 252         if (dev->of_node && !vdd)
 253                 return 0;
 254
 255         if (mmc_slot(host).before_set_reg)
 256                 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 257
 258         /*
 259          * Assume Vcc regulator is used only to power the card ... OMAP
 260          * VDDS is used to power the pins, optionally with a transceiver to
 261          * support cards using voltages other than VDDS (1.8V nominal).  When a
 262          * transceiver is used, DAT3..7 are muxed as transceiver control pins.
 263          *
 264          * In some cases this regulator won't support enable/disable;
 265          * e.g. it's a fixed rail for a WLAN chip.
 266          *
 267          * In other cases vcc_aux switches interface power.  Example, for
 268          * eMMC cards it represents VccQ.  Sometimes transceivers or SDIO
 269          * chips/cards need an interface voltage rail too.
 270          */
 271         if (power_on) {
 272                 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
 273                 /* Enable interface voltage rail, if needed */
 274                 if (ret == 0 && host->vcc_aux) {
 275                         ret = regulator_enable(host->vcc_aux);
 276                         if (ret < 0)
 277                                 ret = mmc_regulator_set_ocr(host->mmc,
 278                                                         host->vcc, 0);
 279                 }
 280         } else {
 281                 /* Shut down the rail */
 282                 if (host->vcc_aux)
 283                         ret = regulator_disable(host->vcc_aux);
 284                 if (!ret) {
 285                         /* Then proceed to shut down the local regulator */
 286                         ret = mmc_regulator_set_ocr(host->mmc,
 287                                                 host->vcc, 0);
 288                 }
 289         }
 290
 291         if (mmc_slot(host).after_set_reg)
 292                 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
 293
 294         return ret;
 295 }
 296
 297 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 298 {
 299         struct regulator *reg;
 300         int ocr_value = 0;
 301
 302         mmc_slot(host).set_power = omap_hsmmc_set_power;
 303
 304         reg = regulator_get(host->dev, "vmmc");
 305         if (IS_ERR(reg)) {
 306                 dev_dbg(host->dev, "vmmc regulator missing\n");
 307         } else {
 308                 host->vcc = reg;
 309                 ocr_value = mmc_regulator_get_ocrmask(reg);
 310                 if (!mmc_slot(host).ocr_mask) {
 311                         mmc_slot(host).ocr_mask = ocr_value;
 312                 } else {
 313                         if (!(mmc_slot(host).ocr_mask & ocr_value)) {
 314                                 dev_err(host->dev, "ocrmask %x is not supported\n",
 315                                         mmc_slot(host).ocr_mask);
 316                                 mmc_slot(host).ocr_mask = 0;
 317                                 return -EINVAL;
 318                         }
 319                 }
 320
 321                 /* Allow an aux regulator */
 322                 reg = regulator_get(host->dev, "vmmc_aux");
 323                 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
 324
 325                 /* For eMMC do not power off when not in sleep state */
 326                 if (mmc_slot(host).no_regulator_off_init)
 327                         return 0;
 328                 /*
 329                 * UGLY HACK:  workaround regulator framework bugs.
 330                 * When the bootloader leaves a supply active, it's
 331                 * initialized with zero usecount ... and we can't
 332                 * disable it without first enabling it.  Until the
 333                 * framework is fixed, we need a workaround like this
 334                 * (which is safe for MMC, but not in general).
 335                 */
 336                 if (regulator_is_enabled(host->vcc) > 0 ||
 337                     (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
 338                         int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
 339
 340                         mmc_slot(host).set_power(host->dev, host->slot_id,
 341                                                  1, vdd);
 342                         mmc_slot(host).set_power(host->dev, host->slot_id,
 343                                                  0, 0);
 344                 }
 345         }
 346
 347         return 0;
 348 }
 349
 350 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 351 {
 352         regulator_put(host->vcc);
 353         regulator_put(host->vcc_aux);
 354         mmc_slot(host).set_power = NULL;
 355 }
 356
 357 static inline int omap_hsmmc_have_reg(void)
 358 {
 359         return 1;
 360 }
 361
 362 #else
 363
 364 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
 365 {
 366         return -EINVAL;
 367 }
 368
 369 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
 370 {
 371 }
 372
 373 static inline int omap_hsmmc_have_reg(void)
 374 {
 375         return 0;
 376 }
 377
 378 #endif
 379
 380 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 381 {
 382         int ret;
 383
 384         if (gpio_is_valid(pdata->slots[0].switch_pin)) {
 385                 if (pdata->slots[0].cover)
 386                         pdata->slots[0].get_cover_state =
 387                                         omap_hsmmc_get_cover_state;
 388                 else
 389                         pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 390                 pdata->slots[0].card_detect_irq =
 391                                 gpio_to_irq(pdata->slots[0].switch_pin);
 392                 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
 393                 if (ret)
 394                         return ret;
 395                 ret = gpio_direction_input(pdata->slots[0].switch_pin);
 396                 if (ret)
 397                         goto err_free_sp;
 398         } else
 399                 pdata->slots[0].switch_pin = -EINVAL;
 400
 401         if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 402                 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
 403                 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
 404                 if (ret)
 405                         goto err_free_cd;
 406                 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
 407                 if (ret)
 408                         goto err_free_wp;
 409         } else
 410                 pdata->slots[0].gpio_wp = -EINVAL;
 411
 412         return 0;
 413
 414 err_free_wp:
 415         gpio_free(pdata->slots[0].gpio_wp);
 416 err_free_cd:
 417         if (gpio_is_valid(pdata->slots[0].switch_pin))
 418 err_free_sp:
 419                 gpio_free(pdata->slots[0].switch_pin);
 420         return ret;
 421 }
 422
 423 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
 424 {
 425         if (gpio_is_valid(pdata->slots[0].gpio_wp))
 426                 gpio_free(pdata->slots[0].gpio_wp);
 427         if (gpio_is_valid(pdata->slots[0].switch_pin))
 428                 gpio_free(pdata->slots[0].switch_pin);
 429 }
 430
 431 /*
 432  * Start clock to the card
 433  */
 434 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
 435 {
 436         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 437                 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
 438 }
 439
 440 /*
 441  * Stop clock to the card
 442  */
 443 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
 444 {
 445         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 446                 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
 447         if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
 448                 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
 449 }
 450
 451 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
 452                                   struct mmc_command *cmd)
 453 {
 454         unsigned int irq_mask;
 455
 456         if (host->use_dma)
 457                 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
 458         else
 459                 irq_mask = INT_EN_MASK;
 460
 461         /* Disable timeout for erases */
 462         if (cmd->opcode == MMC_ERASE)
 463                 irq_mask &= ~DTO_ENABLE;
 464
 465         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 466         OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
 467         OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
 468 }
 469
 470 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
 471 {
 472         OMAP_HSMMC_WRITE(host->base, ISE, 0);
 473         OMAP_HSMMC_WRITE(host->base, IE, 0);
 474         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 475 }
 476
 477 /* Calculate divisor for the given clock frequency */
 478 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
 479 {
 480         u16 dsor = 0;
 481
 482         if (ios->clock) {
 483                 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
 484                 if (dsor > 250)
 485                         dsor = 250;
 486         }
 487
 488         return dsor;
 489 }
 490
 491 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
 492 {
 493         struct mmc_ios *ios = &host->mmc->ios;
 494         unsigned long regval;
 495         unsigned long timeout;
 496
 497         dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
 498
 499         omap_hsmmc_stop_clock(host);
 500
 501         regval = OMAP_HSMMC_READ(host->base, SYSCTL);
 502         regval = regval & ~(CLKD_MASK | DTO_MASK);
 503         regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
 504         OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
 505         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 506                 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
 507
 508         /* Wait till the ICS bit is set */
 509         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 510         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
 511                 && time_before(jiffies, timeout))
 512                 cpu_relax();
 513
 514         omap_hsmmc_start_clock(host);
 515 }
 516
 517 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
 518 {
 519         struct mmc_ios *ios = &host->mmc->ios;
 520         u32 con;
 521
 522         con = OMAP_HSMMC_READ(host->base, CON);
 523         if (ios->timing == MMC_TIMING_UHS_DDR50)
 524                 con |= DDR;     /* configure in DDR mode */
 525         else
 526                 con &= ~DDR;
 527         switch (ios->bus_width) {
 528         case MMC_BUS_WIDTH_8:
 529                 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
 530                 break;
 531         case MMC_BUS_WIDTH_4:
 532                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 533                 OMAP_HSMMC_WRITE(host->base, HCTL,
 534                         OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
 535                 break;
 536         case MMC_BUS_WIDTH_1:
 537                 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
 538                 OMAP_HSMMC_WRITE(host->base, HCTL,
 539                         OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
 540                 break;
 541         }
 542 }
 543
 544 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
 545 {
 546         struct mmc_ios *ios = &host->mmc->ios;
 547         u32 con;
 548
 549         con = OMAP_HSMMC_READ(host->base, CON);
 550         if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
 551                 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
 552         else
 553                 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
 554 }
 555
 556 #ifdef CONFIG_PM
 557
 558 /*
 559  * Restore the MMC host context, if it was lost as result of a
 560  * power state change.
 561  */
 562 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 563 {
 564         struct mmc_ios *ios = &host->mmc->ios;
 565         struct omap_mmc_platform_data *pdata = host->pdata;
 566         int context_loss = 0;
 567         u32 hctl, capa;
 568         unsigned long timeout;
 569
 570         if (pdata->get_context_loss_count) {
 571                 context_loss = pdata->get_context_loss_count(host->dev);
 572                 if (context_loss < 0)
 573                         return 1;
 574         }
 575
 576         dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
 577                 context_loss == host->context_loss ? "not " : "");
 578         if (host->context_loss == context_loss)
 579                 return 1;
 580
 581         /* Wait for hardware reset */
 582         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 583         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 584                 && time_before(jiffies, timeout))
 585                 ;
 586
 587         /* Do software reset */
 588         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
 589         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 590         while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
 591                 && time_before(jiffies, timeout))
 592                 ;
 593
 594         OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
 595                         OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
 596
 597         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
 598                 if (host->power_mode != MMC_POWER_OFF &&
 599                     (1 << ios->vdd) <= MMC_VDD_23_24)
 600                         hctl = SDVS18;
 601                 else
 602                         hctl = SDVS30;
 603                 capa = VS30 | VS18;
 604         } else {
 605                 hctl = SDVS18;
 606                 capa = VS18;
 607         }
 608
 609         OMAP_HSMMC_WRITE(host->base, HCTL,
 610                         OMAP_HSMMC_READ(host->base, HCTL) | hctl);
 611
 612         OMAP_HSMMC_WRITE(host->base, CAPA,
 613                         OMAP_HSMMC_READ(host->base, CAPA) | capa);
 614
 615         OMAP_HSMMC_WRITE(host->base, HCTL,
 616                         OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
 617
 618         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 619         while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
 620                 && time_before(jiffies, timeout))
 621                 ;
 622
 623         omap_hsmmc_disable_irq(host);
 624
 625         /* Do not initialize card-specific things if the power is off */
 626         if (host->power_mode == MMC_POWER_OFF)
 627                 goto out;
 628
 629         omap_hsmmc_set_bus_width(host);
 630
 631         omap_hsmmc_set_clock(host);
 632
 633         omap_hsmmc_set_bus_mode(host);
 634
 635 out:
 636         host->context_loss = context_loss;
 637
 638         dev_dbg(mmc_dev(host->mmc), "context is restored\n");
 639         return 0;
 640 }
 641
 642 /*
 643  * Save the MMC host context (store the number of power state changes so far).
 644  */
 645 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 646 {
 647         struct omap_mmc_platform_data *pdata = host->pdata;
 648         int context_loss;
 649
 650         if (pdata->get_context_loss_count) {
 651                 context_loss = pdata->get_context_loss_count(host->dev);
 652                 if (context_loss < 0)
 653                         return;
 654                 host->context_loss = context_loss;
 655         }
 656 }
 657
 658 #else
 659
 660 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
 661 {
 662         return 0;
 663 }
 664
 665 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
 666 {
 667 }
 668
 669 #endif
 670
 671 /*
 672  * Send init stream sequence to card
 673  * before sending IDLE command
 674  */
 675 static void send_init_stream(struct omap_hsmmc_host *host)
 676 {
 677         int reg = 0;
 678         unsigned long timeout;
 679
 680         if (host->protect_card)
 681                 return;
 682
 683         disable_irq(host->irq);
 684
 685         OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
 686         OMAP_HSMMC_WRITE(host->base, CON,
 687                 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
 688         OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
 689
 690         timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
 691         while ((reg != CC) && time_before(jiffies, timeout))
 692                 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
 693
 694         OMAP_HSMMC_WRITE(host->base, CON,
 695                 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
 696
 697         OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
 698         OMAP_HSMMC_READ(host->base, STAT);
 699
 700         enable_irq(host->irq);
 701 }
 702
 703 static inline
 704 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
 705 {
 706         int r = 1;
 707
 708         if (mmc_slot(host).get_cover_state)
 709                 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
 710         return r;
 711 }
 712
 713 static ssize_t
 714 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
 715                            char *buf)
 716 {
 717         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 718         struct omap_hsmmc_host *host = mmc_priv(mmc);
 719
 720         return sprintf(buf, "%s\n",
 721                         omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
 722 }
 723
 724 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
 725
 726 static ssize_t
 727 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
 728                         char *buf)
 729 {
 730         struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
 731         struct omap_hsmmc_host *host = mmc_priv(mmc);
 732
 733         return sprintf(buf, "%s\n", mmc_slot(host).name);
 734 }
 735
 736 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
 737
 738 /*
 739  * Configure the response type and send the cmd.
 740  */
 741 static void
 742 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
 743         struct mmc_data *data)
 744 {
 745         int cmdreg = 0, resptype = 0, cmdtype = 0;
 746
 747         dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
 748                 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
 749         host->cmd = cmd;
 750
 751         omap_hsmmc_enable_irq(host, cmd);
 752
 753         host->response_busy = 0;
 754         if (cmd->flags & MMC_RSP_PRESENT) {
 755                 if (cmd->flags & MMC_RSP_136)
 756                         resptype = 1;
 757                 else if (cmd->flags & MMC_RSP_BUSY) {
 758                         resptype = 3;
 759                         host->response_busy = 1;
 760                 } else
 761                         resptype = 2;
 762         }
 763
 764         /*
 765          * Unlike OMAP1 controller, the cmdtype does not seem to be based on
 766          * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
 767          * a val of 0x3, rest 0x0.
 768          */
 769         if (cmd == host->mrq->stop)
 770                 cmdtype = 0x3;
 771
 772         cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
 773
 774         if (data) {
 775                 cmdreg |= DP_SELECT | MSBS | BCE;
 776                 if (data->flags & MMC_DATA_READ)
 777                         cmdreg |= DDIR;
 778                 else
 779                         cmdreg &= ~(DDIR);
 780         }
 781
 782         if (host->use_dma)
 783                 cmdreg |= DMA_EN;
 784
 785         host->req_in_progress = 1;
 786
 787         OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
 788         OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
 789 }
 790
 791 static int
 792 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
 793 {
 794         if (data->flags & MMC_DATA_WRITE)
 795                 return DMA_TO_DEVICE;
 796         else
 797                 return DMA_FROM_DEVICE;
 798 }
 799
 800 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
 801 {
 802         int dma_ch;
 803         unsigned long flags;
 804
 805         spin_lock_irqsave(&host->irq_lock, flags);
 806         host->req_in_progress = 0;
 807         dma_ch = host->dma_ch;
 808         spin_unlock_irqrestore(&host->irq_lock, flags);
 809
 810         omap_hsmmc_disable_irq(host);
 811         /* Do not complete the request if DMA is still in progress */
 812         if (mrq->data && host->use_dma && dma_ch != -1)
 813                 return;
 814         host->mrq = NULL;
 815         mmc_request_done(host->mmc, mrq);
 816 }
 817
 818 /*
 819  * Notify the transfer complete to MMC core
 820  */
 821 static void
 822 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
 823 {
 824         if (!data) {
 825                 struct mmc_request *mrq = host->mrq;
 826
 827                 /* TC before CC from CMD6 - don't know why, but it happens */
 828                 if (host->cmd && host->cmd->opcode == 6 &&
 829                     host->response_busy) {
 830                         host->response_busy = 0;
 831                         return;
 832                 }
 833
 834                 omap_hsmmc_request_done(host, mrq);
 835                 return;
 836         }
 837
 838         host->data = NULL;
 839
 840         if (!data->error)
 841                 data->bytes_xfered += data->blocks * (data->blksz);
 842         else
 843                 data->bytes_xfered = 0;
 844
 845         if (!data->stop) {
 846                 omap_hsmmc_request_done(host, data->mrq);
 847                 return;
 848         }
 849         omap_hsmmc_start_command(host, data->stop, NULL);
 850 }
 851
 852 /*
 853  * Notify the core about command completion
 854  */
 855 static void
 856 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
 857 {
 858         host->cmd = NULL;
 859
 860         if (cmd->flags & MMC_RSP_PRESENT) {
 861                 if (cmd->flags & MMC_RSP_136) {
 862                         /* response type 2 */
 863                         cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
 864                         cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
 865                         cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
 866                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
 867                 } else {
 868                         /* response types 1, 1b, 3, 4, 5, 6 */
 869                         cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
 870                 }
 871         }
 872         if ((host->data == NULL && !host->response_busy) || cmd->error)
 873                 omap_hsmmc_request_done(host, cmd->mrq);
 874 }
 875
 876 /*
 877  * DMA clean up for command errors
 878  */
 879 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
 880 {
 881         int dma_ch;
 882         unsigned long flags;
 883
 884         host->data->error = errno;
 885
 886         spin_lock_irqsave(&host->irq_lock, flags);
 887         dma_ch = host->dma_ch;
 888         host->dma_ch = -1;
 889         spin_unlock_irqrestore(&host->irq_lock, flags);
 890
 891         if (host->use_dma && dma_ch != -1) {
 892                 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
 893                         host->data->sg_len,
 894                         omap_hsmmc_get_dma_dir(host, host->data));
 895                 omap_free_dma(dma_ch);
 896                 host->data->host_cookie = 0;
 897         }
 898         host->data = NULL;
 899 }
 900
 901 /*
 902  * Readable error output
 903  */
 904 #ifdef CONFIG_MMC_DEBUG
 905 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
 906 {
 907         /* --- means reserved bit without definition at documentation */
 908         static const char *omap_hsmmc_status_bits[] = {
 909                 "CC"  , "TC"  , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
 910                 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
 911                 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
 912                 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
 913         };
 914         char res[256];
 915         char *buf = res;
 916         int len, i;
 917
 918         len = sprintf(buf, "MMC IRQ 0x%x :", status);
 919         buf += len;
 920
 921         for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
 922                 if (status & (1 << i)) {
 923                         len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
 924                         buf += len;
 925                 }
 926
 927         dev_dbg(mmc_dev(host->mmc), "%s\n", res);
 928 }
 929 #else
 930 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
 931                                              u32 status)
 932 {
 933 }
 934 #endif  /* CONFIG_MMC_DEBUG */
 935
 936 /*
 937  * MMC controller internal state machines reset
 938  *
 939  * Used to reset command or data internal state machines, using respectively
 940  *  SRC or SRD bit of SYSCTL register
 941  * Can be called from interrupt context
 942  */
 943 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
 944                                                    unsigned long bit)
 945 {
 946         unsigned long i = 0;
 947         unsigned long limit = (loops_per_jiffy *
 948                                 msecs_to_jiffies(MMC_TIMEOUT_MS));
 949
 950         OMAP_HSMMC_WRITE(host->base, SYSCTL,
 951                          OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
 952
 953         /*
 954          * OMAP4 ES2 and greater has an updated reset logic.
 955          * Monitor a 0->1 transition first
 956          */
 957         if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
 958                 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
 959                                         && (i++ < limit))
 960                         cpu_relax();
 961         }
 962         i = 0;
 963
 964         while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
 965                 (i++ < limit))
 966                 cpu_relax();
 967
 968         if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
 969                 dev_err(mmc_dev(host->mmc),
 970                         "Timeout waiting on controller reset in %s\n",
 971                         __func__);
 972 }
 973
 974 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
 975 {
 976         struct mmc_data *data;
 977         int end_cmd = 0, end_trans = 0;
 978
 979         if (!host->req_in_progress) {
 980                 do {
 981                         OMAP_HSMMC_WRITE(host->base, STAT, status);
 982                         /* Flush posted write */
 983                         status = OMAP_HSMMC_READ(host->base, STAT);
 984                 } while (status & INT_EN_MASK);
 985                 return;
 986         }
 987
 988         data = host->data;
 989         dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
 990
 991         if (status & ERR) {
 992                 omap_hsmmc_dbg_report_irq(host, status);
 993                 if ((status & CMD_TIMEOUT) ||
 994                         (status & CMD_CRC)) {
 995                         if (host->cmd) {
 996                                 if (status & CMD_TIMEOUT) {
 997                                         omap_hsmmc_reset_controller_fsm(host,
 998                                                                         SRC);
 999                                         host->cmd->error = -ETIMEDOUT;
1000                                 } else {
1001                                         host->cmd->error = -EILSEQ;
1002                                 }
1003                                 end_cmd = 1;
1004                         }
1005                         if (host->data || host->response_busy) {
1006                                 if (host->data)
1007                                         omap_hsmmc_dma_cleanup(host,
1008                                                                 -ETIMEDOUT);
1009                                 host->response_busy = 0;
1010                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1011                         }
1012                 }
1013                 if ((status & DATA_TIMEOUT) ||
1014                         (status & DATA_CRC)) {
1015                         if (host->data || host->response_busy) {
1016                                 int err = (status & DATA_TIMEOUT) ?
1017                                                 -ETIMEDOUT : -EILSEQ;
1018
1019                                 if (host->data)
1020                                         omap_hsmmc_dma_cleanup(host, err);
1021                                 else
1022                                         host->mrq->cmd->error = err;
1023                                 host->response_busy = 0;
1024                                 omap_hsmmc_reset_controller_fsm(host, SRD);
1025                                 end_trans = 1;
1026                         }
1027                 }
1028                 if (status & CARD_ERR) {
1029                         dev_dbg(mmc_dev(host->mmc),
1030                                 "Ignoring card err CMD%d\n", host->cmd->opcode);
1031                         if (host->cmd)
1032                                 end_cmd = 1;
1033                         if (host->data)
1034                                 end_trans = 1;
1035                 }
1036         }
1037
1038         OMAP_HSMMC_WRITE(host->base, STAT, status);
1039
1040         if (end_cmd || ((status & CC) && host->cmd))
1041                 omap_hsmmc_cmd_done(host, host->cmd);
1042         if ((end_trans || (status & TC)) && host->mrq)
1043                 omap_hsmmc_xfer_done(host, data);
1044 }
1045
1046 /*
1047  * MMC controller IRQ handler
1048  */
1049 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1050 {
1051         struct omap_hsmmc_host *host = dev_id;
1052         int status;
1053
1054         status = OMAP_HSMMC_READ(host->base, STAT);
1055         do {
1056                 omap_hsmmc_do_irq(host, status);
1057                 /* Flush posted write */
1058                 status = OMAP_HSMMC_READ(host->base, STAT);
1059         } while (status & INT_EN_MASK);
1060
1061         return IRQ_HANDLED;
1062 }
1063
1064 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1065 {
1066         unsigned long i;
1067
1068         OMAP_HSMMC_WRITE(host->base, HCTL,
1069                          OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1070         for (i = 0; i < loops_per_jiffy; i++) {
1071                 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1072                         break;
1073                 cpu_relax();
1074         }
1075 }
1076
1077 /*
1078  * Switch MMC interface voltage ... only relevant for MMC1.
1079  *
1080  * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1081  * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1082  * Some chips, like eMMC ones, use internal transceivers.
1083  */
1084 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1085 {
1086         u32 reg_val = 0;
1087         int ret;
1088
1089         /* Disable the clocks */
1090         pm_runtime_put_sync(host->dev);
1091         if (host->dbclk)
1092                 clk_disable_unprepare(host->dbclk);
1093
1094         /* Turn the power off */
1095         ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1096
1097         /* Turn the power ON with given VDD 1.8 or 3.0v */
1098         if (!ret)
1099                 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1100                                                vdd);
1101         pm_runtime_get_sync(host->dev);
1102         if (host->dbclk)
1103                 clk_prepare_enable(host->dbclk);
1104
1105         if (ret != 0)
1106                 goto err;
1107
1108         OMAP_HSMMC_WRITE(host->base, HCTL,
1109                 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1110         reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1111
1112         /*
1113          * If a MMC dual voltage card is detected, the set_ios fn calls
1114          * this fn with VDD bit set for 1.8V. Upon card removal from the
1115          * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1116          *
1117          * Cope with a bit of slop in the range ... per data sheets:
1118          *  - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1119          *    but recommended values are 1.71V to 1.89V
1120          *  - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1121          *    but recommended values are 2.7V to 3.3V
1122          *
1123          * Board setup code shouldn't permit anything very out-of-range.
1124          * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1125          * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1126          */
1127         if ((1 << vdd) <= MMC_VDD_23_24)
1128                 reg_val |= SDVS18;
1129         else
1130                 reg_val |= SDVS30;
1131
1132         OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1133         set_sd_bus_power(host);
1134
1135         return 0;
1136 err:
1137         dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1138         return ret;
1139 }
1140
1141 /* Protect the card while the cover is open */
1142 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1143 {
1144         if (!mmc_slot(host).get_cover_state)
1145                 return;
1146
1147         host->reqs_blocked = 0;
1148         if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1149                 if (host->protect_card) {
1150                         dev_info(host->dev, "%s: cover is closed, "
1151                                          "card is now accessible\n",
1152                                          mmc_hostname(host->mmc));
1153                         host->protect_card = 0;
1154                 }
1155         } else {
1156                 if (!host->protect_card) {
1157                         dev_info(host->dev, "%s: cover is open, "
1158                                          "card is now inaccessible\n",
1159                                          mmc_hostname(host->mmc));
1160                         host->protect_card = 1;
1161                 }
1162         }
1163 }
1164
1165 /*
1166  * irq handler to notify the core about card insertion/removal
1167  */
1168 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1169 {
1170         struct omap_hsmmc_host *host = dev_id;
1171         struct omap_mmc_slot_data *slot = &mmc_slot(host);
1172         int carddetect;
1173
1174         if (host->suspended)
1175                 return IRQ_HANDLED;
1176
1177         sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1178
1179         if (slot->card_detect)
1180                 carddetect = slot->card_detect(host->dev, host->slot_id);
1181         else {
1182                 omap_hsmmc_protect_card(host);
1183                 carddetect = -ENOSYS;
1184         }
1185
1186         if (carddetect)
1187                 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1188         else
1189                 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1190         return IRQ_HANDLED;
1191 }
1192
1193 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1194                                      struct mmc_data *data)
1195 {
1196         int sync_dev;
1197
1198         if (data->flags & MMC_DATA_WRITE)
1199                 sync_dev = host->dma_line_tx;
1200         else
1201                 sync_dev = host->dma_line_rx;
1202         return sync_dev;
1203 }
1204
1205 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1206                                        struct mmc_data *data,
1207                                        struct scatterlist *sgl)
1208 {
1209         int blksz, nblk, dma_ch;
1210
1211         dma_ch = host->dma_ch;
1212         if (data->flags & MMC_DATA_WRITE) {
1213                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1214                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1215                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1216                         sg_dma_address(sgl), 0, 0);
1217         } else {
1218                 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1219                         (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1220                 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1221                         sg_dma_address(sgl), 0, 0);
1222         }
1223
1224         blksz = host->data->blksz;
1225         nblk = sg_dma_len(sgl) / blksz;
1226
1227         omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1228                         blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1229                         omap_hsmmc_get_dma_sync_dev(host, data),
1230                         !(data->flags & MMC_DATA_WRITE));
1231
1232         omap_start_dma(dma_ch);
1233 }
1234
1235 /*
1236  * DMA call back function
1237  */
1238 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1239 {
1240         struct omap_hsmmc_host *host = cb_data;
1241         struct mmc_data *data;
1242         int dma_ch, req_in_progress;
1243         unsigned long flags;
1244
1245         if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1246                 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1247                         ch_status);
1248                 return;
1249         }
1250
1251         spin_lock_irqsave(&host->irq_lock, flags);
1252         if (host->dma_ch < 0) {
1253                 spin_unlock_irqrestore(&host->irq_lock, flags);
1254                 return;
1255         }
1256
1257         data = host->mrq->data;
1258         host->dma_sg_idx++;
1259         if (host->dma_sg_idx < host->dma_len) {
1260                 /* Fire up the next transfer. */
1261                 omap_hsmmc_config_dma_params(host, data,
1262                                            data->sg + host->dma_sg_idx);
1263                 spin_unlock_irqrestore(&host->irq_lock, flags);
1264                 return;
1265         }
1266
1267         if (!data->host_cookie)
1268                 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1269                              omap_hsmmc_get_dma_dir(host, data));
1270
1271         req_in_progress = host->req_in_progress;
1272         dma_ch = host->dma_ch;
1273         host->dma_ch = -1;
1274         spin_unlock_irqrestore(&host->irq_lock, flags);
1275
1276         omap_free_dma(dma_ch);
1277
1278         /* If DMA has finished after TC, complete the request */
1279         if (!req_in_progress) {
1280                 struct mmc_request *mrq = host->mrq;
1281
1282                 host->mrq = NULL;
1283                 mmc_request_done(host->mmc, mrq);
1284         }
1285 }
1286
1287 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1288                                        struct mmc_data *data,
1289                                        struct omap_hsmmc_next *next)
1290 {
1291         int dma_len;
1292
1293         if (!next && data->host_cookie &&
1294             data->host_cookie != host->next_data.cookie) {
1295                 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1296                        " host->next_data.cookie %d\n",
1297                        __func__, data->host_cookie, host->next_data.cookie);
1298                 data->host_cookie = 0;
1299         }
1300
1301         /* Check if next job is already prepared */
1302         if (next ||
1303             (!next && data->host_cookie != host->next_data.cookie)) {
1304                 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1305                                      data->sg_len,
1306                                      omap_hsmmc_get_dma_dir(host, data));
1307
1308         } else {
1309                 dma_len = host->next_data.dma_len;
1310                 host->next_data.dma_len = 0;
1311         }
1312
1313
1314         if (dma_len == 0)
1315                 return -EINVAL;
1316
1317         if (next) {
1318                 next->dma_len = dma_len;
1319                 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1320         } else
1321                 host->dma_len = dma_len;
1322
1323         return 0;
1324 }
1325
1326 /*
1327  * Routine to configure and start DMA for the MMC card
1328  */
1329 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1330                                         struct mmc_request *req)
1331 {
1332         int dma_ch = 0, ret = 0, i;
1333         struct mmc_data *data = req->data;
1334
1335         /* Sanity check: all the SG entries must be aligned by block size. */
1336         for (i = 0; i < data->sg_len; i++) {
1337                 struct scatterlist *sgl;
1338
1339                 sgl = data->sg + i;
1340                 if (sgl->length % data->blksz)
1341                         return -EINVAL;
1342         }
1343         if ((data->blksz % 4) != 0)
1344                 /* REVISIT: The MMC buffer increments only when MSB is written.
1345                  * Return error for blksz which is non multiple of four.
1346                  */
1347                 return -EINVAL;
1348
1349         BUG_ON(host->dma_ch != -1);
1350
1351         ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1352                                "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1353         if (ret != 0) {
1354                 dev_err(mmc_dev(host->mmc),
1355                         "%s: omap_request_dma() failed with %d\n",
1356                         mmc_hostname(host->mmc), ret);
1357                 return ret;
1358         }
1359         ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1360         if (ret)
1361                 return ret;
1362
1363         host->dma_ch = dma_ch;
1364         host->dma_sg_idx = 0;
1365
1366         omap_hsmmc_config_dma_params(host, data, data->sg);
1367
1368         return 0;
1369 }
1370
1371 static void set_data_timeout(struct omap_hsmmc_host *host,
1372                              unsigned int timeout_ns,
1373                              unsigned int timeout_clks)
1374 {
1375         unsigned int timeout, cycle_ns;
1376         uint32_t reg, clkd, dto = 0;
1377
1378         reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1379         clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1380         if (clkd == 0)
1381                 clkd = 1;
1382
1383         cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1384         timeout = timeout_ns / cycle_ns;
1385         timeout += timeout_clks;
1386         if (timeout) {
1387                 while ((timeout & 0x80000000) == 0) {
1388                         dto += 1;
1389                         timeout <<= 1;
1390                 }
1391                 dto = 31 - dto;
1392                 timeout <<= 1;
1393                 if (timeout && dto)
1394                         dto += 1;
1395                 if (dto >= 13)
1396                         dto -= 13;
1397                 else
1398                         dto = 0;
1399                 if (dto > 14)
1400                         dto = 14;
1401         }
1402
1403         reg &= ~DTO_MASK;
1404         reg |= dto << DTO_SHIFT;
1405         OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1406 }
1407
1408 /*
1409  * Configure block length for MMC/SD cards and initiate the transfer.
1410  */
1411 static int
1412 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1413 {
1414         int ret;
1415         host->data = req->data;
1416
1417         if (req->data == NULL) {
1418                 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1419                 /*
1420                  * Set an arbitrary 100ms data timeout for commands with
1421                  * busy signal.
1422                  */
1423                 if (req->cmd->flags & MMC_RSP_BUSY)
1424                         set_data_timeout(host, 100000000U, 0);
1425                 return 0;
1426         }
1427
1428         OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1429                                         | (req->data->blocks << 16));
1430         set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1431
1432         if (host->use_dma) {
1433                 ret = omap_hsmmc_start_dma_transfer(host, req);
1434                 if (ret != 0) {
1435                         dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1436                         return ret;
1437                 }
1438         }
1439         return 0;
1440 }
1441
1442 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1443                                 int err)
1444 {
1445         struct omap_hsmmc_host *host = mmc_priv(mmc);
1446         struct mmc_data *data = mrq->data;
1447
1448         if (host->use_dma) {
1449                 if (data->host_cookie)
1450                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1451                                      data->sg_len,
1452                                      omap_hsmmc_get_dma_dir(host, data));
1453                 data->host_cookie = 0;
1454         }
1455 }
1456
1457 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1458                                bool is_first_req)
1459 {
1460         struct omap_hsmmc_host *host = mmc_priv(mmc);
1461
1462         if (mrq->data->host_cookie) {
1463                 mrq->data->host_cookie = 0;
1464                 return ;
1465         }
1466
1467         if (host->use_dma)
1468                 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1469                                                 &host->next_data))
1470                         mrq->data->host_cookie = 0;
1471 }
1472
1473 /*
1474  * Request function. for read/write operation
1475  */
1476 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1477 {
1478         struct omap_hsmmc_host *host = mmc_priv(mmc);
1479         int err;
1480
1481         BUG_ON(host->req_in_progress);
1482         BUG_ON(host->dma_ch != -1);
1483         if (host->protect_card) {
1484                 if (host->reqs_blocked < 3) {
1485                         /*
1486                          * Ensure the controller is left in a consistent
1487                          * state by resetting the command and data state
1488                          * machines.
1489                          */
1490                         omap_hsmmc_reset_controller_fsm(host, SRD);
1491                         omap_hsmmc_reset_controller_fsm(host, SRC);
1492                         host->reqs_blocked += 1;
1493                 }
1494                 req->cmd->error = -EBADF;
1495                 if (req->data)
1496                         req->data->error = -EBADF;
1497                 req->cmd->retries = 0;
1498                 mmc_request_done(mmc, req);
1499                 return;
1500         } else if (host->reqs_blocked)
1501                 host->reqs_blocked = 0;
1502         WARN_ON(host->mrq != NULL);
1503         host->mrq = req;
1504         err = omap_hsmmc_prepare_data(host, req);
1505         if (err) {
1506                 req->cmd->error = err;
1507                 if (req->data)
1508                         req->data->error = err;
1509                 host->mrq = NULL;
1510                 mmc_request_done(mmc, req);
1511                 return;
1512         }
1513
1514         omap_hsmmc_start_command(host, req->cmd, req->data);
1515 }
1516
1517 /* Routine to configure clock values. Exposed API to core */
1518 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1519 {
1520         struct omap_hsmmc_host *host = mmc_priv(mmc);
1521         int do_send_init_stream = 0;
1522
1523         pm_runtime_get_sync(host->dev);
1524
1525         if (ios->power_mode != host->power_mode) {
1526                 switch (ios->power_mode) {
1527                 case MMC_POWER_OFF:
1528                         mmc_slot(host).set_power(host->dev, host->slot_id,
1529                                                  0, 0);
1530                         host->vdd = 0;
1531                         break;
1532                 case MMC_POWER_UP:
1533                         mmc_slot(host).set_power(host->dev, host->slot_id,
1534                                                  1, ios->vdd);
1535                         host->vdd = ios->vdd;
1536                         break;
1537                 case MMC_POWER_ON:
1538                         do_send_init_stream = 1;
1539                         break;
1540                 }
1541                 host->power_mode = ios->power_mode;
1542         }
1543
1544         /* FIXME: set registers based only on changes to ios */
1545
1546         omap_hsmmc_set_bus_width(host);
1547
1548         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1549                 /* Only MMC1 can interface at 3V without some flavor
1550                  * of external transceiver; but they all handle 1.8V.
1551                  */
1552                 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1553                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1554                         /*
1555                          * With pbias cell programming missing, this
1556                          * can't be allowed when booting with device
1557                          * tree.
1558                          */
1559                         !host->dev->of_node) {
1560                                 /*
1561                                  * The mmc_select_voltage fn of the core does
1562                                  * not seem to set the power_mode to
1563                                  * MMC_POWER_UP upon recalculating the voltage.
1564                                  * vdd 1.8v.
1565                                  */
1566                         if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1567                                 dev_dbg(mmc_dev(host->mmc),
1568                                                 "Switch operation failed\n");
1569                 }
1570         }
1571
1572         omap_hsmmc_set_clock(host);
1573
1574         if (do_send_init_stream)
1575                 send_init_stream(host);
1576
1577         omap_hsmmc_set_bus_mode(host);
1578
1579         pm_runtime_put_autosuspend(host->dev);
1580 }
1581
1582 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1583 {
1584         struct omap_hsmmc_host *host = mmc_priv(mmc);
1585
1586         if (!mmc_slot(host).card_detect)
1587                 return -ENOSYS;
1588         return mmc_slot(host).card_detect(host->dev, host->slot_id);
1589 }
1590
1591 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1592 {
1593         struct omap_hsmmc_host *host = mmc_priv(mmc);
1594
1595         if (!mmc_slot(host).get_ro)
1596                 return -ENOSYS;
1597         return mmc_slot(host).get_ro(host->dev, 0);
1598 }
1599
1600 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1601 {
1602         struct omap_hsmmc_host *host = mmc_priv(mmc);
1603
1604         if (mmc_slot(host).init_card)
1605                 mmc_slot(host).init_card(card);
1606 }
1607
1608 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1609 {
1610         u32 hctl, capa, value;
1611
1612         /* Only MMC1 supports 3.0V */
1613         if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1614                 hctl = SDVS30;
1615                 capa = VS30 | VS18;
1616         } else {
1617                 hctl = SDVS18;
1618                 capa = VS18;
1619         }
1620
1621         value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1622         OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1623
1624         value = OMAP_HSMMC_READ(host->base, CAPA);
1625         OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1626
1627         /* Set the controller to AUTO IDLE mode */
1628         value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1629         OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1630
1631         /* Set SD bus power bit */
1632         set_sd_bus_power(host);
1633 }
1634
1635 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1636 {
1637         struct omap_hsmmc_host *host = mmc_priv(mmc);
1638
1639         pm_runtime_get_sync(host->dev);
1640
1641         return 0;
1642 }
1643
1644 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1645 {
1646         struct omap_hsmmc_host *host = mmc_priv(mmc);
1647
1648         pm_runtime_mark_last_busy(host->dev);
1649         pm_runtime_put_autosuspend(host->dev);
1650
1651         return 0;
1652 }
1653
1654 static const struct mmc_host_ops omap_hsmmc_ops = {
1655         .enable = omap_hsmmc_enable_fclk,
1656         .disable = omap_hsmmc_disable_fclk,
1657         .post_req = omap_hsmmc_post_req,
1658         .pre_req = omap_hsmmc_pre_req,
1659         .request = omap_hsmmc_request,
1660         .set_ios = omap_hsmmc_set_ios,
1661         .get_cd = omap_hsmmc_get_cd,
1662         .get_ro = omap_hsmmc_get_ro,
1663         .init_card = omap_hsmmc_init_card,
1664         /* NYET -- enable_sdio_irq */
1665 };
1666
1667 #ifdef CONFIG_DEBUG_FS
1668
1669 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1670 {
1671         struct mmc_host *mmc = s->private;
1672         struct omap_hsmmc_host *host = mmc_priv(mmc);
1673         int context_loss = 0;
1674
1675         if (host->pdata->get_context_loss_count)
1676                 context_loss = host->pdata->get_context_loss_count(host->dev);
1677
1678         seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1679                         mmc->index, host->context_loss, context_loss);
1680
1681         if (host->suspended) {
1682                 seq_printf(s, "host suspended, can't read registers\n");
1683                 return 0;
1684         }
1685
1686         pm_runtime_get_sync(host->dev);
1687
1688         seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1689                         OMAP_HSMMC_READ(host->base, SYSCONFIG));
1690         seq_printf(s, "CON:\t\t0x%08x\n",
1691                         OMAP_HSMMC_READ(host->base, CON));
1692         seq_printf(s, "HCTL:\t\t0x%08x\n",
1693                         OMAP_HSMMC_READ(host->base, HCTL));
1694         seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1695                         OMAP_HSMMC_READ(host->base, SYSCTL));
1696         seq_printf(s, "IE:\t\t0x%08x\n",
1697                         OMAP_HSMMC_READ(host->base, IE));
1698         seq_printf(s, "ISE:\t\t0x%08x\n",
1699                         OMAP_HSMMC_READ(host->base, ISE));
1700         seq_printf(s, "CAPA:\t\t0x%08x\n",
1701                         OMAP_HSMMC_READ(host->base, CAPA));
1702
1703         pm_runtime_mark_last_busy(host->dev);
1704         pm_runtime_put_autosuspend(host->dev);
1705
1706         return 0;
1707 }
1708
1709 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1710 {
1711         return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1712 }
1713
1714 static const struct file_operations mmc_regs_fops = {
1715         .open           = omap_hsmmc_regs_open,
1716         .read           = seq_read,
1717         .llseek         = seq_lseek,
1718         .release        = single_release,
1719 };
1720
1721 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1722 {
1723         if (mmc->debugfs_root)
1724                 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1725                         mmc, &mmc_regs_fops);
1726 }
1727
1728 #else
1729
1730 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1731 {
1732 }
1733
1734 #endif
1735
1736 #ifdef CONFIG_OF
1737 static u16 omap4_reg_offset = 0x100;
1738
1739 static const struct of_device_id omap_mmc_of_match[] = {
1740         {
1741                 .compatible = "ti,omap2-hsmmc",
1742         },
1743         {
1744                 .compatible = "ti,omap3-hsmmc",
1745         },
1746         {
1747                 .compatible = "ti,omap4-hsmmc",
1748                 .data = &omap4_reg_offset,
1749         },
1750         {},
1751 };
1752 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1753
1754 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1755 {
1756         struct omap_mmc_platform_data *pdata;
1757         struct device_node *np = dev->of_node;
1758         u32 bus_width;
1759
1760         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1761         if (!pdata)
1762                 return NULL; /* out of memory */
1763
1764         if (of_find_property(np, "ti,dual-volt", NULL))
1765                 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1766
1767         /* This driver only supports 1 slot */
1768         pdata->nr_slots = 1;
1769         pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1770         pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1771
1772         if (of_find_property(np, "ti,non-removable", NULL)) {
1773                 pdata->slots[0].nonremovable = true;
1774                 pdata->slots[0].no_regulator_off_init = true;
1775         }
1776         of_property_read_u32(np, "bus-width", &bus_width);
1777         if (bus_width == 4)
1778                 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1779         else if (bus_width == 8)
1780                 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1781
1782         if (of_find_property(np, "ti,needs-special-reset", NULL))
1783                 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1784
1785         return pdata;
1786 }
1787 #else
1788 static inline struct omap_mmc_platform_data
1789                         *of_get_hsmmc_pdata(struct device *dev)
1790 {
1791         return NULL;
1792 }
1793 #endif
1794
1795 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1796 {
1797         struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1798         struct mmc_host *mmc;
1799         struct omap_hsmmc_host *host = NULL;
1800         struct resource *res;
1801         int ret, irq;
1802         const struct of_device_id *match;
1803
1804         match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1805         if (match) {
1806                 pdata = of_get_hsmmc_pdata(&pdev->dev);
1807                 if (match->data) {
1808                         u16 *offsetp = match->data;
1809                         pdata->reg_offset = *offsetp;
1810                 }
1811         }
1812
1813         if (pdata == NULL) {
1814                 dev_err(&pdev->dev, "Platform Data is missing\n");
1815                 return -ENXIO;
1816         }
1817
1818         if (pdata->nr_slots == 0) {
1819                 dev_err(&pdev->dev, "No Slots\n");
1820                 return -ENXIO;
1821         }
1822
1823         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1824         irq = platform_get_irq(pdev, 0);
1825         if (res == NULL || irq < 0)
1826                 return -ENXIO;
1827
1828         res = request_mem_region(res->start, resource_size(res), pdev->name);
1829         if (res == NULL)
1830                 return -EBUSY;
1831
1832         ret = omap_hsmmc_gpio_init(pdata);
1833         if (ret)
1834                 goto err;
1835
1836         mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1837         if (!mmc) {
1838                 ret = -ENOMEM;
1839                 goto err_alloc;
1840         }
1841
1842         host            = mmc_priv(mmc);
1843         host->mmc       = mmc;
1844         host->pdata     = pdata;
1845         host->dev       = &pdev->dev;
1846         host->use_dma   = 1;
1847         host->dev->dma_mask = &pdata->dma_mask;
1848         host->dma_ch    = -1;
1849         host->irq       = irq;
1850         host->slot_id   = 0;
1851         host->mapbase   = res->start + pdata->reg_offset;
1852         host->base      = ioremap(host->mapbase, SZ_4K);
1853         host->power_mode = MMC_POWER_OFF;
1854         host->next_data.cookie = 1;
1855
1856         platform_set_drvdata(pdev, host);
1857
1858         mmc->ops        = &omap_hsmmc_ops;
1859
1860         /*
1861          * If regulator_disable can only put vcc_aux to sleep then there is
1862          * no off state.
1863          */
1864         if (mmc_slot(host).vcc_aux_disable_is_sleep)
1865                 mmc_slot(host).no_off = 1;
1866
1867         mmc->f_min = OMAP_MMC_MIN_CLOCK;
1868
1869         if (pdata->max_freq > 0)
1870                 mmc->f_max = pdata->max_freq;
1871         else
1872                 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1873
1874         spin_lock_init(&host->irq_lock);
1875
1876         host->fclk = clk_get(&pdev->dev, "fck");
1877         if (IS_ERR(host->fclk)) {
1878                 ret = PTR_ERR(host->fclk);
1879                 host->fclk = NULL;
1880                 goto err1;
1881         }
1882
1883         if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1884                 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1885                 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1886         }
1887
1888         pm_runtime_enable(host->dev);
1889         pm_runtime_get_sync(host->dev);
1890         pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1891         pm_runtime_use_autosuspend(host->dev);
1892
1893         omap_hsmmc_context_save(host);
1894
1895         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1896         /*
1897          * MMC can still work without debounce clock.
1898          */
1899         if (IS_ERR(host->dbclk)) {
1900                 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1901                 host->dbclk = NULL;
1902         } else if (clk_prepare_enable(host->dbclk) != 0) {
1903                 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1904                 clk_put(host->dbclk);
1905                 host->dbclk = NULL;
1906         }
1907
1908         /* Since we do only SG emulation, we can have as many segs
1909          * as we want. */
1910         mmc->max_segs = 1024;
1911
1912         mmc->max_blk_size = 512;       /* Block Length at max can be 1024 */
1913         mmc->max_blk_count = 0xFFFF;    /* No. of Blocks is 16 bits */
1914         mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1915         mmc->max_seg_size = mmc->max_req_size;
1916
1917         mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1918                      MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1919
1920         mmc->caps |= mmc_slot(host).caps;
1921         if (mmc->caps & MMC_CAP_8_BIT_DATA)
1922                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1923
1924         if (mmc_slot(host).nonremovable)
1925                 mmc->caps |= MMC_CAP_NONREMOVABLE;
1926
1927         mmc->pm_caps = mmc_slot(host).pm_caps;
1928
1929         omap_hsmmc_conf_bus_power(host);
1930
1931         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1932         if (!res) {
1933                 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1934                 ret = -ENXIO;
1935                 goto err_irq;
1936         }
1937         host->dma_line_tx = res->start;
1938
1939         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1940         if (!res) {
1941                 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1942                 ret = -ENXIO;
1943                 goto err_irq;
1944         }
1945         host->dma_line_rx = res->start;
1946
1947         /* Request IRQ for MMC operations */
1948         ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1949                         mmc_hostname(mmc), host);
1950         if (ret) {
1951                 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1952                 goto err_irq;
1953         }
1954
1955         if (pdata->init != NULL) {
1956                 if (pdata->init(&pdev->dev) != 0) {
1957                         dev_dbg(mmc_dev(host->mmc),
1958                                 "Unable to configure MMC IRQs\n");
1959                         goto err_irq_cd_init;
1960                 }
1961         }
1962
1963         if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1964                 ret = omap_hsmmc_reg_get(host);
1965                 if (ret)
1966                         goto err_reg;
1967                 host->use_reg = 1;
1968         }
1969
1970         mmc->ocr_avail = mmc_slot(host).ocr_mask;
1971
1972         /* Request IRQ for card detect */
1973         if ((mmc_slot(host).card_detect_irq)) {
1974                 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1975                                            NULL,
1976                                            omap_hsmmc_detect,
1977                                            IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1978                                            mmc_hostname(mmc), host);
1979                 if (ret) {
1980                         dev_dbg(mmc_dev(host->mmc),
1981                                 "Unable to grab MMC CD IRQ\n");
1982                         goto err_irq_cd;
1983                 }
1984                 pdata->suspend = omap_hsmmc_suspend_cdirq;
1985                 pdata->resume = omap_hsmmc_resume_cdirq;
1986         }
1987
1988         omap_hsmmc_disable_irq(host);
1989
1990         omap_hsmmc_protect_card(host);
1991
1992         mmc_add_host(mmc);
1993
1994         if (mmc_slot(host).name != NULL) {
1995                 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1996                 if (ret < 0)
1997                         goto err_slot_name;
1998         }
1999         if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2000                 ret = device_create_file(&mmc->class_dev,
2001                                         &dev_attr_cover_switch);
2002                 if (ret < 0)
2003                         goto err_slot_name;
2004         }
2005
2006         omap_hsmmc_debugfs(mmc);
2007         pm_runtime_mark_last_busy(host->dev);
2008         pm_runtime_put_autosuspend(host->dev);
2009
2010         return 0;
2011
2012 err_slot_name:
2013         mmc_remove_host(mmc);
2014         free_irq(mmc_slot(host).card_detect_irq, host);
2015 err_irq_cd:
2016         if (host->use_reg)
2017                 omap_hsmmc_reg_put(host);
2018 err_reg:
2019         if (host->pdata->cleanup)
2020                 host->pdata->cleanup(&pdev->dev);
2021 err_irq_cd_init:
2022         free_irq(host->irq, host);
2023 err_irq:
2024         pm_runtime_put_sync(host->dev);
2025         pm_runtime_disable(host->dev);
2026         clk_put(host->fclk);
2027         if (host->dbclk) {
2028                 clk_disable_unprepare(host->dbclk);
2029                 clk_put(host->dbclk);
2030         }
2031 err1:
2032         iounmap(host->base);
2033         platform_set_drvdata(pdev, NULL);
2034         mmc_free_host(mmc);
2035 err_alloc:
2036         omap_hsmmc_gpio_free(pdata);
2037 err:
2038         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2039         if (res)
2040                 release_mem_region(res->start, resource_size(res));
2041         return ret;
2042 }
2043
2044 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
2045 {
2046         struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2047         struct resource *res;
2048
2049         pm_runtime_get_sync(host->dev);
2050         mmc_remove_host(host->mmc);
2051         if (host->use_reg)
2052                 omap_hsmmc_reg_put(host);
2053         if (host->pdata->cleanup)
2054                 host->pdata->cleanup(&pdev->dev);
2055         free_irq(host->irq, host);
2056         if (mmc_slot(host).card_detect_irq)
2057                 free_irq(mmc_slot(host).card_detect_irq, host);
2058
2059         pm_runtime_put_sync(host->dev);
2060         pm_runtime_disable(host->dev);
2061         clk_put(host->fclk);
2062         if (host->dbclk) {
2063                 clk_disable_unprepare(host->dbclk);
2064                 clk_put(host->dbclk);
2065         }
2066
2067         mmc_free_host(host->mmc);
2068         iounmap(host->base);
2069         omap_hsmmc_gpio_free(pdev->dev.platform_data);
2070
2071         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2072         if (res)
2073                 release_mem_region(res->start, resource_size(res));
2074         platform_set_drvdata(pdev, NULL);
2075
2076         return 0;
2077 }
2078
2079 #ifdef CONFIG_PM
2080 static int omap_hsmmc_suspend(struct device *dev)
2081 {
2082         int ret = 0;
2083         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2084
2085         if (!host)
2086                 return 0;
2087
2088         if (host && host->suspended)
2089                 return 0;
2090
2091         pm_runtime_get_sync(host->dev);
2092         host->suspended = 1;
2093         if (host->pdata->suspend) {
2094                 ret = host->pdata->suspend(dev, host->slot_id);
2095                 if (ret) {
2096                         dev_dbg(dev, "Unable to handle MMC board"
2097                                         " level suspend\n");
2098                         host->suspended = 0;
2099                         return ret;
2100                 }
2101         }
2102         ret = mmc_suspend_host(host->mmc);
2103
2104         if (ret) {
2105                 host->suspended = 0;
2106                 if (host->pdata->resume) {
2107                         ret = host->pdata->resume(dev, host->slot_id);
2108                         if (ret)
2109                                 dev_dbg(dev, "Unmask interrupt failed\n");
2110                 }
2111                 goto err;
2112         }
2113
2114         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2115                 omap_hsmmc_disable_irq(host);
2116                 OMAP_HSMMC_WRITE(host->base, HCTL,
2117                                 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2118         }
2119
2120         if (host->dbclk)
2121                 clk_disable_unprepare(host->dbclk);
2122 err:
2123         pm_runtime_put_sync(host->dev);
2124         return ret;
2125 }
2126
2127 /* Routine to resume the MMC device */
2128 static int omap_hsmmc_resume(struct device *dev)
2129 {
2130         int ret = 0;
2131         struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2132
2133         if (!host)
2134                 return 0;
2135
2136         if (host && !host->suspended)
2137                 return 0;
2138
2139         pm_runtime_get_sync(host->dev);
2140
2141         if (host->dbclk)
2142                 clk_prepare_enable(host->dbclk);
2143
2144         if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2145                 omap_hsmmc_conf_bus_power(host);
2146
2147         if (host->pdata->resume) {
2148                 ret = host->pdata->resume(dev, host->slot_id);
2149                 if (ret)
2150                         dev_dbg(dev, "Unmask interrupt failed\n");
2151         }
2152
2153         omap_hsmmc_protect_card(host);
2154
2155         /* Notify the core to resume the host */
2156         ret = mmc_resume_host(host->mmc);
2157         if (ret == 0)
2158                 host->suspended = 0;
2159
2160         pm_runtime_mark_last_busy(host->dev);
2161         pm_runtime_put_autosuspend(host->dev);
2162
2163         return ret;
2164
2165 }
2166
2167 #else
2168 #define omap_hsmmc_suspend      NULL
2169 #define omap_hsmmc_resume               NULL
2170 #endif
2171
2172 static int omap_hsmmc_runtime_suspend(struct device *dev)
2173 {
2174         struct omap_hsmmc_host *host;
2175
2176         host = platform_get_drvdata(to_platform_device(dev));
2177         omap_hsmmc_context_save(host);
2178         dev_dbg(dev, "disabled\n");
2179
2180         return 0;
2181 }
2182
2183 static int omap_hsmmc_runtime_resume(struct device *dev)
2184 {
2185         struct omap_hsmmc_host *host;
2186
2187         host = platform_get_drvdata(to_platform_device(dev));
2188         omap_hsmmc_context_restore(host);
2189         dev_dbg(dev, "enabled\n");
2190
2191         return 0;
2192 }
2193
2194 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2195         .suspend        = omap_hsmmc_suspend,
2196         .resume         = omap_hsmmc_resume,
2197         .runtime_suspend = omap_hsmmc_runtime_suspend,
2198         .runtime_resume = omap_hsmmc_runtime_resume,
2199 };
2200
2201 static struct platform_driver omap_hsmmc_driver = {
2202         .probe          = omap_hsmmc_probe,
2203         .remove         = __devexit_p(omap_hsmmc_remove),
2204         .driver         = {
2205                 .name = DRIVER_NAME,
2206                 .owner = THIS_MODULE,
2207                 .pm = &omap_hsmmc_dev_pm_ops,
2208                 .of_match_table = of_match_ptr(omap_mmc_of_match),
2209         },
2210 };
2211
2212 module_platform_driver(omap_hsmmc_driver);
2213 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2214 MODULE_LICENSE("GPL");
2215 MODULE_ALIAS("platform:" DRIVER_NAME);
2216 MODULE_AUTHOR("Texas Instruments Inc");