2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/seq_file.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/workqueue.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/core.h>
32 #include <linux/mmc/mmc.h>
34 #include <linux/semaphore.h>
35 #include <linux/gpio.h>
36 #include <linux/regulator/consumer.h>
37 #include <linux/pm_runtime.h>
39 #include <mach/hardware.h>
40 #include <plat/board.h>
44 /* OMAP HSMMC Host Controller Registers */
45 #define OMAP_HSMMC_SYSCONFIG 0x0010
46 #define OMAP_HSMMC_SYSSTATUS 0x0014
47 #define OMAP_HSMMC_CON 0x002C
48 #define OMAP_HSMMC_BLK 0x0104
49 #define OMAP_HSMMC_ARG 0x0108
50 #define OMAP_HSMMC_CMD 0x010C
51 #define OMAP_HSMMC_RSP10 0x0110
52 #define OMAP_HSMMC_RSP32 0x0114
53 #define OMAP_HSMMC_RSP54 0x0118
54 #define OMAP_HSMMC_RSP76 0x011C
55 #define OMAP_HSMMC_DATA 0x0120
56 #define OMAP_HSMMC_HCTL 0x0128
57 #define OMAP_HSMMC_SYSCTL 0x012C
58 #define OMAP_HSMMC_STAT 0x0130
59 #define OMAP_HSMMC_IE 0x0134
60 #define OMAP_HSMMC_ISE 0x0138
61 #define OMAP_HSMMC_CAPA 0x0140
63 #define VS18 (1 << 26)
64 #define VS30 (1 << 25)
65 #define SDVS18 (0x5 << 9)
66 #define SDVS30 (0x6 << 9)
67 #define SDVS33 (0x7 << 9)
68 #define SDVS_MASK 0x00000E00
69 #define SDVSCLR 0xFFFFF1FF
70 #define SDVSDET 0x00000400
77 #define CLKD_MASK 0x0000FFC0
79 #define DTO_MASK 0x000F0000
81 #define INT_EN_MASK 0x307F0033
82 #define BWR_ENABLE (1 << 4)
83 #define BRR_ENABLE (1 << 5)
84 #define DTO_ENABLE (1 << 20)
85 #define INIT_STREAM (1 << 1)
86 #define DP_SELECT (1 << 21)
91 #define FOUR_BIT (1 << 1)
97 #define CMD_TIMEOUT (1 << 16)
98 #define DATA_TIMEOUT (1 << 20)
99 #define CMD_CRC (1 << 17)
100 #define DATA_CRC (1 << 21)
101 #define CARD_ERR (1 << 28)
102 #define STAT_CLEAR 0xFFFFFFFF
103 #define INIT_STREAM_CMD 0x00000000
104 #define DUAL_VOLT_OCR_BIT 7
105 #define SRC (1 << 25)
106 #define SRD (1 << 26)
107 #define SOFTRESET (1 << 1)
108 #define RESETDONE (1 << 0)
111 * FIXME: Most likely all the data using these _DEVID defines should come
112 * from the platform_data, or implemented in controller and slot specific
115 #define OMAP_MMC1_DEVID 0
116 #define OMAP_MMC2_DEVID 1
117 #define OMAP_MMC3_DEVID 2
118 #define OMAP_MMC4_DEVID 3
119 #define OMAP_MMC5_DEVID 4
121 #define MMC_AUTOSUSPEND_DELAY 100
122 #define MMC_TIMEOUT_MS 20
123 #define OMAP_MMC_MASTER_CLOCK 96000000
124 #define OMAP_MMC_MIN_CLOCK 400000
125 #define OMAP_MMC_MAX_CLOCK 52000000
126 #define DRIVER_NAME "omap_hsmmc"
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
133 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
136 * MMC Host controller read/write API's
138 #define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
141 #define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
144 struct omap_hsmmc_next {
145 unsigned int dma_len;
149 struct omap_hsmmc_host {
151 struct mmc_host *mmc;
152 struct mmc_request *mrq;
153 struct mmc_command *cmd;
154 struct mmc_data *data;
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
166 struct work_struct mmc_carddetect_work;
168 resource_size_t mapbase;
169 spinlock_t irq_lock; /* Prevent races with irq handler */
171 unsigned int dma_len;
172 unsigned int dma_sg_idx;
173 unsigned char bus_mode;
174 unsigned char power_mode;
180 int dma_line_tx, dma_line_rx;
191 struct omap_hsmmc_next next_data;
193 struct omap_mmc_platform_data *pdata;
196 static int omap_hsmmc_card_detect(struct device *dev, int slot)
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
204 static int omap_hsmmc_get_wp(struct device *dev, int slot)
206 struct omap_mmc_platform_data *mmc = dev->platform_data;
208 /* NOTE: assumes write protect signal is active-high */
209 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
212 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
216 /* NOTE: assumes card detect signal is active-low */
217 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
222 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
224 struct omap_mmc_platform_data *mmc = dev->platform_data;
226 disable_irq(mmc->slots[0].card_detect_irq);
230 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
232 struct omap_mmc_platform_data *mmc = dev->platform_data;
234 enable_irq(mmc->slots[0].card_detect_irq);
240 #define omap_hsmmc_suspend_cdirq NULL
241 #define omap_hsmmc_resume_cdirq NULL
245 #ifdef CONFIG_REGULATOR
247 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
250 struct omap_hsmmc_host *host =
251 platform_get_drvdata(to_platform_device(dev));
254 if (mmc_slot(host).before_set_reg)
255 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
258 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
260 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
262 if (mmc_slot(host).after_set_reg)
263 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
268 static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
271 struct omap_hsmmc_host *host =
272 platform_get_drvdata(to_platform_device(dev));
276 * If we don't see a Vcc regulator, assume it's a fixed
277 * voltage always-on regulator.
282 if (mmc_slot(host).before_set_reg)
283 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
286 * Assume Vcc regulator is used only to power the card ... OMAP
287 * VDDS is used to power the pins, optionally with a transceiver to
288 * support cards using voltages other than VDDS (1.8V nominal). When a
289 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
291 * In some cases this regulator won't support enable/disable;
292 * e.g. it's a fixed rail for a WLAN chip.
294 * In other cases vcc_aux switches interface power. Example, for
295 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
296 * chips/cards need an interface voltage rail too.
299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
304 ret = mmc_regulator_set_ocr(host->mmc,
308 /* Shut down the rail */
310 ret = regulator_disable(host->vcc_aux);
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
318 if (mmc_slot(host).after_set_reg)
319 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
324 static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
330 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
331 int vdd, int cardsleep)
333 struct omap_hsmmc_host *host =
334 platform_get_drvdata(to_platform_device(dev));
335 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
337 return regulator_set_mode(host->vcc, mode);
340 static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
341 int vdd, int cardsleep)
343 struct omap_hsmmc_host *host =
344 platform_get_drvdata(to_platform_device(dev));
348 * If we don't see a Vcc regulator, assume it's a fixed
349 * voltage always-on regulator.
354 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
357 return regulator_set_mode(host->vcc, mode);
360 /* VCC can be turned off if card is asleep */
362 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
364 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
366 err = regulator_set_mode(host->vcc, mode);
370 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
371 return regulator_set_mode(host->vcc_aux, mode);
374 return regulator_disable(host->vcc_aux);
376 return regulator_enable(host->vcc_aux);
379 static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
380 int vdd, int cardsleep)
385 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
387 struct regulator *reg;
392 case OMAP_MMC1_DEVID:
393 /* On-chip level shifting via PBIAS0/PBIAS1 */
394 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
395 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
397 case OMAP_MMC2_DEVID:
398 case OMAP_MMC3_DEVID:
399 case OMAP_MMC5_DEVID:
400 /* Off-chip level shifting, or none */
401 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
402 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
404 case OMAP_MMC4_DEVID:
405 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
406 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
408 pr_err("MMC%d configuration not supported!\n", host->id);
412 reg = regulator_get(host->dev, "vmmc");
414 dev_dbg(host->dev, "vmmc regulator missing\n");
416 * HACK: until fixed.c regulator is usable,
417 * we don't require a main regulator
420 if (host->id == OMAP_MMC1_DEVID) {
426 ocr_value = mmc_regulator_get_ocrmask(reg);
427 if (!mmc_slot(host).ocr_mask) {
428 mmc_slot(host).ocr_mask = ocr_value;
430 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
431 pr_err("MMC%d ocrmask %x is not supported\n",
432 host->id, mmc_slot(host).ocr_mask);
433 mmc_slot(host).ocr_mask = 0;
438 /* Allow an aux regulator */
439 reg = regulator_get(host->dev, "vmmc_aux");
440 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
442 /* For eMMC do not power off when not in sleep state */
443 if (mmc_slot(host).no_regulator_off_init)
446 * UGLY HACK: workaround regulator framework bugs.
447 * When the bootloader leaves a supply active, it's
448 * initialized with zero usecount ... and we can't
449 * disable it without first enabling it. Until the
450 * framework is fixed, we need a workaround like this
451 * (which is safe for MMC, but not in general).
453 if (regulator_is_enabled(host->vcc) > 0) {
454 regulator_enable(host->vcc);
455 regulator_disable(host->vcc);
458 if (regulator_is_enabled(reg) > 0) {
459 regulator_enable(reg);
460 regulator_disable(reg);
468 mmc_slot(host).set_power = NULL;
469 mmc_slot(host).set_sleep = NULL;
473 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
475 regulator_put(host->vcc);
476 regulator_put(host->vcc_aux);
477 mmc_slot(host).set_power = NULL;
478 mmc_slot(host).set_sleep = NULL;
481 static inline int omap_hsmmc_have_reg(void)
488 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
493 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
497 static inline int omap_hsmmc_have_reg(void)
504 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
508 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
509 if (pdata->slots[0].cover)
510 pdata->slots[0].get_cover_state =
511 omap_hsmmc_get_cover_state;
513 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
514 pdata->slots[0].card_detect_irq =
515 gpio_to_irq(pdata->slots[0].switch_pin);
516 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
519 ret = gpio_direction_input(pdata->slots[0].switch_pin);
523 pdata->slots[0].switch_pin = -EINVAL;
525 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
526 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
527 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
530 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
534 pdata->slots[0].gpio_wp = -EINVAL;
539 gpio_free(pdata->slots[0].gpio_wp);
541 if (gpio_is_valid(pdata->slots[0].switch_pin))
543 gpio_free(pdata->slots[0].switch_pin);
547 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
549 if (gpio_is_valid(pdata->slots[0].gpio_wp))
550 gpio_free(pdata->slots[0].gpio_wp);
551 if (gpio_is_valid(pdata->slots[0].switch_pin))
552 gpio_free(pdata->slots[0].switch_pin);
556 * Stop clock to the card
558 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
560 OMAP_HSMMC_WRITE(host->base, SYSCTL,
561 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
562 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
563 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
566 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
567 struct mmc_command *cmd)
569 unsigned int irq_mask;
572 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
574 irq_mask = INT_EN_MASK;
576 /* Disable timeout for erases */
577 if (cmd->opcode == MMC_ERASE)
578 irq_mask &= ~DTO_ENABLE;
580 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
581 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
582 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
585 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
587 OMAP_HSMMC_WRITE(host->base, ISE, 0);
588 OMAP_HSMMC_WRITE(host->base, IE, 0);
589 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
592 /* Calculate divisor for the given clock frequency */
593 static u16 calc_divisor(struct mmc_ios *ios)
598 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
609 * Restore the MMC host context, if it was lost as result of a
610 * power state change.
612 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
614 struct mmc_ios *ios = &host->mmc->ios;
615 struct omap_mmc_platform_data *pdata = host->pdata;
616 int context_loss = 0;
618 unsigned long timeout;
620 if (pdata->get_context_loss_count) {
621 context_loss = pdata->get_context_loss_count(host->dev);
622 if (context_loss < 0)
626 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
627 context_loss == host->context_loss ? "not " : "");
628 if (host->context_loss == context_loss)
631 /* Wait for hardware reset */
632 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
633 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
634 && time_before(jiffies, timeout))
637 /* Do software reset */
638 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
639 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
640 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
641 && time_before(jiffies, timeout))
644 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
645 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
647 if (host->id == OMAP_MMC1_DEVID) {
648 if (host->power_mode != MMC_POWER_OFF &&
649 (1 << ios->vdd) <= MMC_VDD_23_24)
659 OMAP_HSMMC_WRITE(host->base, HCTL,
660 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
662 OMAP_HSMMC_WRITE(host->base, CAPA,
663 OMAP_HSMMC_READ(host->base, CAPA) | capa);
665 OMAP_HSMMC_WRITE(host->base, HCTL,
666 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
668 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
669 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
670 && time_before(jiffies, timeout))
673 omap_hsmmc_disable_irq(host);
675 /* Do not initialize card-specific things if the power is off */
676 if (host->power_mode == MMC_POWER_OFF)
679 con = OMAP_HSMMC_READ(host->base, CON);
680 switch (ios->bus_width) {
681 case MMC_BUS_WIDTH_8:
682 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
684 case MMC_BUS_WIDTH_4:
685 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
686 OMAP_HSMMC_WRITE(host->base, HCTL,
687 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
689 case MMC_BUS_WIDTH_1:
690 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
691 OMAP_HSMMC_WRITE(host->base, HCTL,
692 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
696 OMAP_HSMMC_WRITE(host->base, SYSCTL,
697 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
698 OMAP_HSMMC_WRITE(host->base, SYSCTL,
699 (calc_divisor(ios) << 6) | (DTO << 16));
700 OMAP_HSMMC_WRITE(host->base, SYSCTL,
701 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
703 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
704 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
705 && time_before(jiffies, timeout))
708 OMAP_HSMMC_WRITE(host->base, SYSCTL,
709 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
711 con = OMAP_HSMMC_READ(host->base, CON);
712 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
713 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
715 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
717 host->context_loss = context_loss;
719 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
724 * Save the MMC host context (store the number of power state changes so far).
726 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
728 struct omap_mmc_platform_data *pdata = host->pdata;
731 if (pdata->get_context_loss_count) {
732 context_loss = pdata->get_context_loss_count(host->dev);
733 if (context_loss < 0)
735 host->context_loss = context_loss;
741 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
746 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
753 * Send init stream sequence to card
754 * before sending IDLE command
756 static void send_init_stream(struct omap_hsmmc_host *host)
759 unsigned long timeout;
761 if (host->protect_card)
764 disable_irq(host->irq);
766 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
767 OMAP_HSMMC_WRITE(host->base, CON,
768 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
769 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
771 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
772 while ((reg != CC) && time_before(jiffies, timeout))
773 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
775 OMAP_HSMMC_WRITE(host->base, CON,
776 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
778 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
779 OMAP_HSMMC_READ(host->base, STAT);
781 enable_irq(host->irq);
785 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
789 if (mmc_slot(host).get_cover_state)
790 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
795 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
798 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
799 struct omap_hsmmc_host *host = mmc_priv(mmc);
801 return sprintf(buf, "%s\n",
802 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
805 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
808 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
811 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
812 struct omap_hsmmc_host *host = mmc_priv(mmc);
814 return sprintf(buf, "%s\n", mmc_slot(host).name);
817 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
820 * Configure the response type and send the cmd.
823 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
824 struct mmc_data *data)
826 int cmdreg = 0, resptype = 0, cmdtype = 0;
828 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
829 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
832 omap_hsmmc_enable_irq(host, cmd);
834 host->response_busy = 0;
835 if (cmd->flags & MMC_RSP_PRESENT) {
836 if (cmd->flags & MMC_RSP_136)
838 else if (cmd->flags & MMC_RSP_BUSY) {
840 host->response_busy = 1;
846 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
847 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
848 * a val of 0x3, rest 0x0.
850 if (cmd == host->mrq->stop)
853 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
856 cmdreg |= DP_SELECT | MSBS | BCE;
857 if (data->flags & MMC_DATA_READ)
866 host->req_in_progress = 1;
868 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
869 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
873 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
875 if (data->flags & MMC_DATA_WRITE)
876 return DMA_TO_DEVICE;
878 return DMA_FROM_DEVICE;
881 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
885 spin_lock(&host->irq_lock);
886 host->req_in_progress = 0;
887 dma_ch = host->dma_ch;
888 spin_unlock(&host->irq_lock);
890 omap_hsmmc_disable_irq(host);
891 /* Do not complete the request if DMA is still in progress */
892 if (mrq->data && host->use_dma && dma_ch != -1)
895 mmc_request_done(host->mmc, mrq);
899 * Notify the transfer complete to MMC core
902 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
905 struct mmc_request *mrq = host->mrq;
907 /* TC before CC from CMD6 - don't know why, but it happens */
908 if (host->cmd && host->cmd->opcode == 6 &&
909 host->response_busy) {
910 host->response_busy = 0;
914 omap_hsmmc_request_done(host, mrq);
921 data->bytes_xfered += data->blocks * (data->blksz);
923 data->bytes_xfered = 0;
926 omap_hsmmc_request_done(host, data->mrq);
929 omap_hsmmc_start_command(host, data->stop, NULL);
933 * Notify the core about command completion
936 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
940 if (cmd->flags & MMC_RSP_PRESENT) {
941 if (cmd->flags & MMC_RSP_136) {
942 /* response type 2 */
943 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
944 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
945 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
946 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
948 /* response types 1, 1b, 3, 4, 5, 6 */
949 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
952 if ((host->data == NULL && !host->response_busy) || cmd->error)
953 omap_hsmmc_request_done(host, cmd->mrq);
957 * DMA clean up for command errors
959 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
963 host->data->error = errno;
965 spin_lock(&host->irq_lock);
966 dma_ch = host->dma_ch;
968 spin_unlock(&host->irq_lock);
970 if (host->use_dma && dma_ch != -1) {
971 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
973 omap_hsmmc_get_dma_dir(host, host->data));
974 omap_free_dma(dma_ch);
980 * Readable error output
982 #ifdef CONFIG_MMC_DEBUG
983 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
985 /* --- means reserved bit without definition at documentation */
986 static const char *omap_hsmmc_status_bits[] = {
987 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
988 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
989 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
990 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
996 len = sprintf(buf, "MMC IRQ 0x%x :", status);
999 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
1000 if (status & (1 << i)) {
1001 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
1005 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1008 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1012 #endif /* CONFIG_MMC_DEBUG */
1015 * MMC controller internal state machines reset
1017 * Used to reset command or data internal state machines, using respectively
1018 * SRC or SRD bit of SYSCTL register
1019 * Can be called from interrupt context
1021 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1024 unsigned long i = 0;
1025 unsigned long limit = (loops_per_jiffy *
1026 msecs_to_jiffies(MMC_TIMEOUT_MS));
1028 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1029 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1032 * OMAP4 ES2 and greater has an updated reset logic.
1033 * Monitor a 0->1 transition first
1035 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
1036 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
1042 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1046 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1047 dev_err(mmc_dev(host->mmc),
1048 "Timeout waiting on controller reset in %s\n",
1052 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
1054 struct mmc_data *data;
1055 int end_cmd = 0, end_trans = 0;
1057 if (!host->req_in_progress) {
1059 OMAP_HSMMC_WRITE(host->base, STAT, status);
1060 /* Flush posted write */
1061 status = OMAP_HSMMC_READ(host->base, STAT);
1062 } while (status & INT_EN_MASK);
1067 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1070 omap_hsmmc_dbg_report_irq(host, status);
1071 if ((status & CMD_TIMEOUT) ||
1072 (status & CMD_CRC)) {
1074 if (status & CMD_TIMEOUT) {
1075 omap_hsmmc_reset_controller_fsm(host,
1077 host->cmd->error = -ETIMEDOUT;
1079 host->cmd->error = -EILSEQ;
1083 if (host->data || host->response_busy) {
1085 omap_hsmmc_dma_cleanup(host,
1087 host->response_busy = 0;
1088 omap_hsmmc_reset_controller_fsm(host, SRD);
1091 if ((status & DATA_TIMEOUT) ||
1092 (status & DATA_CRC)) {
1093 if (host->data || host->response_busy) {
1094 int err = (status & DATA_TIMEOUT) ?
1095 -ETIMEDOUT : -EILSEQ;
1098 omap_hsmmc_dma_cleanup(host, err);
1100 host->mrq->cmd->error = err;
1101 host->response_busy = 0;
1102 omap_hsmmc_reset_controller_fsm(host, SRD);
1106 if (status & CARD_ERR) {
1107 dev_dbg(mmc_dev(host->mmc),
1108 "Ignoring card err CMD%d\n", host->cmd->opcode);
1116 OMAP_HSMMC_WRITE(host->base, STAT, status);
1118 if (end_cmd || ((status & CC) && host->cmd))
1119 omap_hsmmc_cmd_done(host, host->cmd);
1120 if ((end_trans || (status & TC)) && host->mrq)
1121 omap_hsmmc_xfer_done(host, data);
1125 * MMC controller IRQ handler
1127 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1129 struct omap_hsmmc_host *host = dev_id;
1132 status = OMAP_HSMMC_READ(host->base, STAT);
1134 omap_hsmmc_do_irq(host, status);
1135 /* Flush posted write */
1136 status = OMAP_HSMMC_READ(host->base, STAT);
1137 } while (status & INT_EN_MASK);
1142 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1146 OMAP_HSMMC_WRITE(host->base, HCTL,
1147 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1148 for (i = 0; i < loops_per_jiffy; i++) {
1149 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1156 * Switch MMC interface voltage ... only relevant for MMC1.
1158 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1159 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1160 * Some chips, like eMMC ones, use internal transceivers.
1162 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1167 /* Disable the clocks */
1168 pm_runtime_put_sync(host->dev);
1169 if (host->got_dbclk)
1170 clk_disable(host->dbclk);
1172 /* Turn the power off */
1173 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1175 /* Turn the power ON with given VDD 1.8 or 3.0v */
1177 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1179 pm_runtime_get_sync(host->dev);
1180 if (host->got_dbclk)
1181 clk_enable(host->dbclk);
1186 OMAP_HSMMC_WRITE(host->base, HCTL,
1187 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1188 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1191 * If a MMC dual voltage card is detected, the set_ios fn calls
1192 * this fn with VDD bit set for 1.8V. Upon card removal from the
1193 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1195 * Cope with a bit of slop in the range ... per data sheets:
1196 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1197 * but recommended values are 1.71V to 1.89V
1198 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1199 * but recommended values are 2.7V to 3.3V
1201 * Board setup code shouldn't permit anything very out-of-range.
1202 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1203 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1205 if ((1 << vdd) <= MMC_VDD_23_24)
1210 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1211 set_sd_bus_power(host);
1215 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1219 /* Protect the card while the cover is open */
1220 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1222 if (!mmc_slot(host).get_cover_state)
1225 host->reqs_blocked = 0;
1226 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1227 if (host->protect_card) {
1228 printk(KERN_INFO "%s: cover is closed, "
1229 "card is now accessible\n",
1230 mmc_hostname(host->mmc));
1231 host->protect_card = 0;
1234 if (!host->protect_card) {
1235 printk(KERN_INFO "%s: cover is open, "
1236 "card is now inaccessible\n",
1237 mmc_hostname(host->mmc));
1238 host->protect_card = 1;
1244 * Work Item to notify the core about card insertion/removal
1246 static void omap_hsmmc_detect(struct work_struct *work)
1248 struct omap_hsmmc_host *host =
1249 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
1250 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1253 if (host->suspended)
1256 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1258 if (slot->card_detect)
1259 carddetect = slot->card_detect(host->dev, host->slot_id);
1261 omap_hsmmc_protect_card(host);
1262 carddetect = -ENOSYS;
1266 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1268 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1272 * ISR for handling card insertion and removal
1274 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
1276 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
1278 if (host->suspended)
1280 schedule_work(&host->mmc_carddetect_work);
1285 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
1286 struct mmc_data *data)
1290 if (data->flags & MMC_DATA_WRITE)
1291 sync_dev = host->dma_line_tx;
1293 sync_dev = host->dma_line_rx;
1297 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
1298 struct mmc_data *data,
1299 struct scatterlist *sgl)
1301 int blksz, nblk, dma_ch;
1303 dma_ch = host->dma_ch;
1304 if (data->flags & MMC_DATA_WRITE) {
1305 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1306 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1307 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1308 sg_dma_address(sgl), 0, 0);
1310 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1311 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1312 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1313 sg_dma_address(sgl), 0, 0);
1316 blksz = host->data->blksz;
1317 nblk = sg_dma_len(sgl) / blksz;
1319 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1320 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
1321 omap_hsmmc_get_dma_sync_dev(host, data),
1322 !(data->flags & MMC_DATA_WRITE));
1324 omap_start_dma(dma_ch);
1328 * DMA call back function
1330 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
1332 struct omap_hsmmc_host *host = cb_data;
1333 struct mmc_data *data = host->mrq->data;
1334 int dma_ch, req_in_progress;
1336 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1337 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1342 spin_lock(&host->irq_lock);
1343 if (host->dma_ch < 0) {
1344 spin_unlock(&host->irq_lock);
1349 if (host->dma_sg_idx < host->dma_len) {
1350 /* Fire up the next transfer. */
1351 omap_hsmmc_config_dma_params(host, data,
1352 data->sg + host->dma_sg_idx);
1353 spin_unlock(&host->irq_lock);
1357 if (!data->host_cookie)
1358 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1359 omap_hsmmc_get_dma_dir(host, data));
1361 req_in_progress = host->req_in_progress;
1362 dma_ch = host->dma_ch;
1364 spin_unlock(&host->irq_lock);
1366 omap_free_dma(dma_ch);
1368 /* If DMA has finished after TC, complete the request */
1369 if (!req_in_progress) {
1370 struct mmc_request *mrq = host->mrq;
1373 mmc_request_done(host->mmc, mrq);
1377 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1378 struct mmc_data *data,
1379 struct omap_hsmmc_next *next)
1383 if (!next && data->host_cookie &&
1384 data->host_cookie != host->next_data.cookie) {
1385 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1386 " host->next_data.cookie %d\n",
1387 __func__, data->host_cookie, host->next_data.cookie);
1388 data->host_cookie = 0;
1391 /* Check if next job is already prepared */
1393 (!next && data->host_cookie != host->next_data.cookie)) {
1394 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1396 omap_hsmmc_get_dma_dir(host, data));
1399 dma_len = host->next_data.dma_len;
1400 host->next_data.dma_len = 0;
1408 next->dma_len = dma_len;
1409 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1411 host->dma_len = dma_len;
1417 * Routine to configure and start DMA for the MMC card
1419 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1420 struct mmc_request *req)
1422 int dma_ch = 0, ret = 0, i;
1423 struct mmc_data *data = req->data;
1425 /* Sanity check: all the SG entries must be aligned by block size. */
1426 for (i = 0; i < data->sg_len; i++) {
1427 struct scatterlist *sgl;
1430 if (sgl->length % data->blksz)
1433 if ((data->blksz % 4) != 0)
1434 /* REVISIT: The MMC buffer increments only when MSB is written.
1435 * Return error for blksz which is non multiple of four.
1439 BUG_ON(host->dma_ch != -1);
1441 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1442 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
1444 dev_err(mmc_dev(host->mmc),
1445 "%s: omap_request_dma() failed with %d\n",
1446 mmc_hostname(host->mmc), ret);
1449 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1453 host->dma_ch = dma_ch;
1454 host->dma_sg_idx = 0;
1456 omap_hsmmc_config_dma_params(host, data, data->sg);
1461 static void set_data_timeout(struct omap_hsmmc_host *host,
1462 unsigned int timeout_ns,
1463 unsigned int timeout_clks)
1465 unsigned int timeout, cycle_ns;
1466 uint32_t reg, clkd, dto = 0;
1468 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1469 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1473 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1474 timeout = timeout_ns / cycle_ns;
1475 timeout += timeout_clks;
1477 while ((timeout & 0x80000000) == 0) {
1494 reg |= dto << DTO_SHIFT;
1495 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1499 * Configure block length for MMC/SD cards and initiate the transfer.
1502 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1505 host->data = req->data;
1507 if (req->data == NULL) {
1508 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1510 * Set an arbitrary 100ms data timeout for commands with
1513 if (req->cmd->flags & MMC_RSP_BUSY)
1514 set_data_timeout(host, 100000000U, 0);
1518 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1519 | (req->data->blocks << 16));
1520 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1522 if (host->use_dma) {
1523 ret = omap_hsmmc_start_dma_transfer(host, req);
1525 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1532 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1535 struct omap_hsmmc_host *host = mmc_priv(mmc);
1536 struct mmc_data *data = mrq->data;
1538 if (host->use_dma) {
1539 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1540 omap_hsmmc_get_dma_dir(host, data));
1541 data->host_cookie = 0;
1545 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1548 struct omap_hsmmc_host *host = mmc_priv(mmc);
1550 if (mrq->data->host_cookie) {
1551 mrq->data->host_cookie = 0;
1556 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1558 mrq->data->host_cookie = 0;
1562 * Request function. for read/write operation
1564 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1566 struct omap_hsmmc_host *host = mmc_priv(mmc);
1569 BUG_ON(host->req_in_progress);
1570 BUG_ON(host->dma_ch != -1);
1571 if (host->protect_card) {
1572 if (host->reqs_blocked < 3) {
1574 * Ensure the controller is left in a consistent
1575 * state by resetting the command and data state
1578 omap_hsmmc_reset_controller_fsm(host, SRD);
1579 omap_hsmmc_reset_controller_fsm(host, SRC);
1580 host->reqs_blocked += 1;
1582 req->cmd->error = -EBADF;
1584 req->data->error = -EBADF;
1585 req->cmd->retries = 0;
1586 mmc_request_done(mmc, req);
1588 } else if (host->reqs_blocked)
1589 host->reqs_blocked = 0;
1590 WARN_ON(host->mrq != NULL);
1592 err = omap_hsmmc_prepare_data(host, req);
1594 req->cmd->error = err;
1596 req->data->error = err;
1598 mmc_request_done(mmc, req);
1602 omap_hsmmc_start_command(host, req->cmd, req->data);
1605 /* Routine to configure clock values. Exposed API to core */
1606 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1608 struct omap_hsmmc_host *host = mmc_priv(mmc);
1609 unsigned long regval;
1610 unsigned long timeout;
1612 int do_send_init_stream = 0;
1614 pm_runtime_get_sync(host->dev);
1616 if (ios->power_mode != host->power_mode) {
1617 switch (ios->power_mode) {
1619 mmc_slot(host).set_power(host->dev, host->slot_id,
1624 mmc_slot(host).set_power(host->dev, host->slot_id,
1626 host->vdd = ios->vdd;
1629 do_send_init_stream = 1;
1632 host->power_mode = ios->power_mode;
1635 /* FIXME: set registers based only on changes to ios */
1637 con = OMAP_HSMMC_READ(host->base, CON);
1638 switch (mmc->ios.bus_width) {
1639 case MMC_BUS_WIDTH_8:
1640 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1642 case MMC_BUS_WIDTH_4:
1643 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1644 OMAP_HSMMC_WRITE(host->base, HCTL,
1645 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1647 case MMC_BUS_WIDTH_1:
1648 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
1649 OMAP_HSMMC_WRITE(host->base, HCTL,
1650 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1654 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1655 /* Only MMC1 can interface at 3V without some flavor
1656 * of external transceiver; but they all handle 1.8V.
1658 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1659 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1661 * The mmc_select_voltage fn of the core does
1662 * not seem to set the power_mode to
1663 * MMC_POWER_UP upon recalculating the voltage.
1666 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1667 dev_dbg(mmc_dev(host->mmc),
1668 "Switch operation failed\n");
1672 omap_hsmmc_stop_clock(host);
1674 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1675 regval = regval & ~(CLKD_MASK);
1676 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
1677 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1678 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1679 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1681 /* Wait till the ICS bit is set */
1682 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
1683 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
1684 && time_before(jiffies, timeout))
1687 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1688 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1690 if (do_send_init_stream)
1691 send_init_stream(host);
1693 con = OMAP_HSMMC_READ(host->base, CON);
1694 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1695 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1697 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
1699 pm_runtime_put_autosuspend(host->dev);
1702 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1704 struct omap_hsmmc_host *host = mmc_priv(mmc);
1706 if (!mmc_slot(host).card_detect)
1708 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1711 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1713 struct omap_hsmmc_host *host = mmc_priv(mmc);
1715 if (!mmc_slot(host).get_ro)
1717 return mmc_slot(host).get_ro(host->dev, 0);
1720 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1722 struct omap_hsmmc_host *host = mmc_priv(mmc);
1724 if (mmc_slot(host).init_card)
1725 mmc_slot(host).init_card(card);
1728 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1730 u32 hctl, capa, value;
1732 /* Only MMC1 supports 3.0V */
1733 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1741 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1742 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1744 value = OMAP_HSMMC_READ(host->base, CAPA);
1745 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1747 /* Set the controller to AUTO IDLE mode */
1748 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1749 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1751 /* Set SD bus power bit */
1752 set_sd_bus_power(host);
1755 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1757 struct omap_hsmmc_host *host = mmc_priv(mmc);
1759 pm_runtime_get_sync(host->dev);
1764 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
1766 struct omap_hsmmc_host *host = mmc_priv(mmc);
1768 pm_runtime_mark_last_busy(host->dev);
1769 pm_runtime_put_autosuspend(host->dev);
1774 static const struct mmc_host_ops omap_hsmmc_ops = {
1775 .enable = omap_hsmmc_enable_fclk,
1776 .disable = omap_hsmmc_disable_fclk,
1777 .post_req = omap_hsmmc_post_req,
1778 .pre_req = omap_hsmmc_pre_req,
1779 .request = omap_hsmmc_request,
1780 .set_ios = omap_hsmmc_set_ios,
1781 .get_cd = omap_hsmmc_get_cd,
1782 .get_ro = omap_hsmmc_get_ro,
1783 .init_card = omap_hsmmc_init_card,
1784 /* NYET -- enable_sdio_irq */
1787 #ifdef CONFIG_DEBUG_FS
1789 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1791 struct mmc_host *mmc = s->private;
1792 struct omap_hsmmc_host *host = mmc_priv(mmc);
1793 int context_loss = 0;
1795 if (host->pdata->get_context_loss_count)
1796 context_loss = host->pdata->get_context_loss_count(host->dev);
1798 seq_printf(s, "mmc%d:\n"
1801 " nesting_cnt:\t%d\n"
1802 " ctx_loss:\t%d:%d\n"
1804 mmc->index, mmc->enabled ? 1 : 0,
1805 host->dpm_state, mmc->nesting_cnt,
1806 host->context_loss, context_loss);
1808 if (host->suspended) {
1809 seq_printf(s, "host suspended, can't read registers\n");
1813 pm_runtime_get_sync(host->dev);
1815 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1816 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1817 seq_printf(s, "CON:\t\t0x%08x\n",
1818 OMAP_HSMMC_READ(host->base, CON));
1819 seq_printf(s, "HCTL:\t\t0x%08x\n",
1820 OMAP_HSMMC_READ(host->base, HCTL));
1821 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1822 OMAP_HSMMC_READ(host->base, SYSCTL));
1823 seq_printf(s, "IE:\t\t0x%08x\n",
1824 OMAP_HSMMC_READ(host->base, IE));
1825 seq_printf(s, "ISE:\t\t0x%08x\n",
1826 OMAP_HSMMC_READ(host->base, ISE));
1827 seq_printf(s, "CAPA:\t\t0x%08x\n",
1828 OMAP_HSMMC_READ(host->base, CAPA));
1830 pm_runtime_mark_last_busy(host->dev);
1831 pm_runtime_put_autosuspend(host->dev);
1836 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1838 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1841 static const struct file_operations mmc_regs_fops = {
1842 .open = omap_hsmmc_regs_open,
1844 .llseek = seq_lseek,
1845 .release = single_release,
1848 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1850 if (mmc->debugfs_root)
1851 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1852 mmc, &mmc_regs_fops);
1857 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1863 static int __init omap_hsmmc_probe(struct platform_device *pdev)
1865 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1866 struct mmc_host *mmc;
1867 struct omap_hsmmc_host *host = NULL;
1868 struct resource *res;
1871 if (pdata == NULL) {
1872 dev_err(&pdev->dev, "Platform Data is missing\n");
1876 if (pdata->nr_slots == 0) {
1877 dev_err(&pdev->dev, "No Slots\n");
1881 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1882 irq = platform_get_irq(pdev, 0);
1883 if (res == NULL || irq < 0)
1886 res->start += pdata->reg_offset;
1887 res->end += pdata->reg_offset;
1888 res = request_mem_region(res->start, resource_size(res), pdev->name);
1892 ret = omap_hsmmc_gpio_init(pdata);
1896 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1902 host = mmc_priv(mmc);
1904 host->pdata = pdata;
1905 host->dev = &pdev->dev;
1907 host->dev->dma_mask = &pdata->dma_mask;
1910 host->id = pdev->id;
1912 host->mapbase = res->start;
1913 host->base = ioremap(host->mapbase, SZ_4K);
1914 host->power_mode = MMC_POWER_OFF;
1915 host->next_data.cookie = 1;
1917 platform_set_drvdata(pdev, host);
1918 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
1920 mmc->ops = &omap_hsmmc_ops;
1923 * If regulator_disable can only put vcc_aux to sleep then there is
1926 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1927 mmc_slot(host).no_off = 1;
1929 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1930 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1932 spin_lock_init(&host->irq_lock);
1934 host->fclk = clk_get(&pdev->dev, "fck");
1935 if (IS_ERR(host->fclk)) {
1936 ret = PTR_ERR(host->fclk);
1941 omap_hsmmc_context_save(host);
1943 mmc->caps |= MMC_CAP_DISABLE;
1945 pm_runtime_enable(host->dev);
1946 pm_runtime_get_sync(host->dev);
1947 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1948 pm_runtime_use_autosuspend(host->dev);
1950 if (cpu_is_omap2430()) {
1951 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1953 * MMC can still work without debounce clock.
1955 if (IS_ERR(host->dbclk))
1956 dev_warn(mmc_dev(host->mmc),
1957 "Failed to get debounce clock\n");
1959 host->got_dbclk = 1;
1961 if (host->got_dbclk)
1962 if (clk_enable(host->dbclk) != 0)
1963 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1967 /* Since we do only SG emulation, we can have as many segs
1969 mmc->max_segs = 1024;
1971 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1972 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1973 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1974 mmc->max_seg_size = mmc->max_req_size;
1976 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1977 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1979 mmc->caps |= mmc_slot(host).caps;
1980 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1981 mmc->caps |= MMC_CAP_4_BIT_DATA;
1983 if (mmc_slot(host).nonremovable)
1984 mmc->caps |= MMC_CAP_NONREMOVABLE;
1986 omap_hsmmc_conf_bus_power(host);
1988 /* Select DMA lines */
1990 case OMAP_MMC1_DEVID:
1991 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1992 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1994 case OMAP_MMC2_DEVID:
1995 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1996 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1998 case OMAP_MMC3_DEVID:
1999 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2000 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2002 case OMAP_MMC4_DEVID:
2003 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2004 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2006 case OMAP_MMC5_DEVID:
2007 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2008 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2011 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2015 /* Request IRQ for MMC operations */
2016 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
2017 mmc_hostname(mmc), host);
2019 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2023 if (pdata->init != NULL) {
2024 if (pdata->init(&pdev->dev) != 0) {
2025 dev_dbg(mmc_dev(host->mmc),
2026 "Unable to configure MMC IRQs\n");
2027 goto err_irq_cd_init;
2031 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
2032 ret = omap_hsmmc_reg_get(host);
2038 mmc->ocr_avail = mmc_slot(host).ocr_mask;
2040 /* Request IRQ for card detect */
2041 if ((mmc_slot(host).card_detect_irq)) {
2042 ret = request_irq(mmc_slot(host).card_detect_irq,
2043 omap_hsmmc_cd_handler,
2044 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2046 mmc_hostname(mmc), host);
2048 dev_dbg(mmc_dev(host->mmc),
2049 "Unable to grab MMC CD IRQ\n");
2052 pdata->suspend = omap_hsmmc_suspend_cdirq;
2053 pdata->resume = omap_hsmmc_resume_cdirq;
2056 omap_hsmmc_disable_irq(host);
2058 omap_hsmmc_protect_card(host);
2062 if (mmc_slot(host).name != NULL) {
2063 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2067 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
2068 ret = device_create_file(&mmc->class_dev,
2069 &dev_attr_cover_switch);
2074 omap_hsmmc_debugfs(mmc);
2075 pm_runtime_mark_last_busy(host->dev);
2076 pm_runtime_put_autosuspend(host->dev);
2081 mmc_remove_host(mmc);
2082 free_irq(mmc_slot(host).card_detect_irq, host);
2085 omap_hsmmc_reg_put(host);
2087 if (host->pdata->cleanup)
2088 host->pdata->cleanup(&pdev->dev);
2090 free_irq(host->irq, host);
2092 pm_runtime_mark_last_busy(host->dev);
2093 pm_runtime_put_autosuspend(host->dev);
2094 clk_put(host->fclk);
2095 if (host->got_dbclk) {
2096 clk_disable(host->dbclk);
2097 clk_put(host->dbclk);
2100 iounmap(host->base);
2101 platform_set_drvdata(pdev, NULL);
2104 omap_hsmmc_gpio_free(pdata);
2106 release_mem_region(res->start, resource_size(res));
2110 static int omap_hsmmc_remove(struct platform_device *pdev)
2112 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2113 struct resource *res;
2116 pm_runtime_get_sync(host->dev);
2117 mmc_remove_host(host->mmc);
2119 omap_hsmmc_reg_put(host);
2120 if (host->pdata->cleanup)
2121 host->pdata->cleanup(&pdev->dev);
2122 free_irq(host->irq, host);
2123 if (mmc_slot(host).card_detect_irq)
2124 free_irq(mmc_slot(host).card_detect_irq, host);
2125 flush_work_sync(&host->mmc_carddetect_work);
2127 pm_runtime_put_sync(host->dev);
2128 pm_runtime_disable(host->dev);
2129 clk_put(host->fclk);
2130 if (host->got_dbclk) {
2131 clk_disable(host->dbclk);
2132 clk_put(host->dbclk);
2135 mmc_free_host(host->mmc);
2136 iounmap(host->base);
2137 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2140 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2142 release_mem_region(res->start, resource_size(res));
2143 platform_set_drvdata(pdev, NULL);
2149 static int omap_hsmmc_suspend(struct device *dev)
2152 struct platform_device *pdev = to_platform_device(dev);
2153 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2155 if (host && host->suspended)
2159 pm_runtime_get_sync(host->dev);
2160 host->suspended = 1;
2161 if (host->pdata->suspend) {
2162 ret = host->pdata->suspend(&pdev->dev,
2165 dev_dbg(mmc_dev(host->mmc),
2166 "Unable to handle MMC board"
2167 " level suspend\n");
2168 host->suspended = 0;
2172 cancel_work_sync(&host->mmc_carddetect_work);
2173 ret = mmc_suspend_host(host->mmc);
2176 omap_hsmmc_disable_irq(host);
2177 OMAP_HSMMC_WRITE(host->base, HCTL,
2178 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2179 if (host->got_dbclk)
2180 clk_disable(host->dbclk);
2182 host->suspended = 0;
2183 if (host->pdata->resume) {
2184 ret = host->pdata->resume(&pdev->dev,
2187 dev_dbg(mmc_dev(host->mmc),
2188 "Unmask interrupt failed\n");
2191 pm_runtime_put_sync(host->dev);
2196 /* Routine to resume the MMC device */
2197 static int omap_hsmmc_resume(struct device *dev)
2200 struct platform_device *pdev = to_platform_device(dev);
2201 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
2203 if (host && !host->suspended)
2207 pm_runtime_get_sync(host->dev);
2209 if (host->got_dbclk)
2210 clk_enable(host->dbclk);
2212 omap_hsmmc_conf_bus_power(host);
2214 if (host->pdata->resume) {
2215 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2217 dev_dbg(mmc_dev(host->mmc),
2218 "Unmask interrupt failed\n");
2221 omap_hsmmc_protect_card(host);
2223 /* Notify the core to resume the host */
2224 ret = mmc_resume_host(host->mmc);
2226 host->suspended = 0;
2228 pm_runtime_mark_last_busy(host->dev);
2229 pm_runtime_put_autosuspend(host->dev);
2237 #define omap_hsmmc_suspend NULL
2238 #define omap_hsmmc_resume NULL
2241 static int omap_hsmmc_runtime_suspend(struct device *dev)
2243 struct omap_hsmmc_host *host;
2245 host = platform_get_drvdata(to_platform_device(dev));
2246 omap_hsmmc_context_save(host);
2247 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2252 static int omap_hsmmc_runtime_resume(struct device *dev)
2254 struct omap_hsmmc_host *host;
2256 host = platform_get_drvdata(to_platform_device(dev));
2257 omap_hsmmc_context_restore(host);
2258 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2263 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2264 .suspend = omap_hsmmc_suspend,
2265 .resume = omap_hsmmc_resume,
2266 .runtime_suspend = omap_hsmmc_runtime_suspend,
2267 .runtime_resume = omap_hsmmc_runtime_resume,
2270 static struct platform_driver omap_hsmmc_driver = {
2271 .remove = omap_hsmmc_remove,
2273 .name = DRIVER_NAME,
2274 .owner = THIS_MODULE,
2275 .pm = &omap_hsmmc_dev_pm_ops,
2279 static int __init omap_hsmmc_init(void)
2281 /* Register the MMC driver */
2282 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
2285 static void __exit omap_hsmmc_cleanup(void)
2287 /* Unregister MMC driver */
2288 platform_driver_unregister(&omap_hsmmc_driver);
2291 module_init(omap_hsmmc_init);
2292 module_exit(omap_hsmmc_cleanup);
2294 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2295 MODULE_LICENSE("GPL");
2296 MODULE_ALIAS("platform:" DRIVER_NAME);
2297 MODULE_AUTHOR("Texas Instruments Inc");