2 * linux/drivers/mmc/host/omap.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com>
6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com>
7 * Other hacks (DMA, SD, etc) by David Brownell
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/delay.h>
22 #include <linux/spinlock.h>
23 #include <linux/timer.h>
24 #include <linux/mmc/host.h>
25 #include <linux/mmc/card.h>
26 #include <linux/clk.h>
27 #include <linux/scatterlist.h>
28 #include <linux/i2c/tps65010.h>
32 #include <asm/mach-types.h>
34 #include <asm/arch/board.h>
35 #include <asm/arch/mmc.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/dma.h>
38 #include <asm/arch/mux.h>
39 #include <asm/arch/fpga.h>
41 #define OMAP_MMC_REG_CMD 0x00
42 #define OMAP_MMC_REG_ARGL 0x04
43 #define OMAP_MMC_REG_ARGH 0x08
44 #define OMAP_MMC_REG_CON 0x0c
45 #define OMAP_MMC_REG_STAT 0x10
46 #define OMAP_MMC_REG_IE 0x14
47 #define OMAP_MMC_REG_CTO 0x18
48 #define OMAP_MMC_REG_DTO 0x1c
49 #define OMAP_MMC_REG_DATA 0x20
50 #define OMAP_MMC_REG_BLEN 0x24
51 #define OMAP_MMC_REG_NBLK 0x28
52 #define OMAP_MMC_REG_BUF 0x2c
53 #define OMAP_MMC_REG_SDIO 0x34
54 #define OMAP_MMC_REG_REV 0x3c
55 #define OMAP_MMC_REG_RSP0 0x40
56 #define OMAP_MMC_REG_RSP1 0x44
57 #define OMAP_MMC_REG_RSP2 0x48
58 #define OMAP_MMC_REG_RSP3 0x4c
59 #define OMAP_MMC_REG_RSP4 0x50
60 #define OMAP_MMC_REG_RSP5 0x54
61 #define OMAP_MMC_REG_RSP6 0x58
62 #define OMAP_MMC_REG_RSP7 0x5c
63 #define OMAP_MMC_REG_IOSR 0x60
64 #define OMAP_MMC_REG_SYSC 0x64
65 #define OMAP_MMC_REG_SYSS 0x68
67 #define OMAP_MMC_STAT_CARD_ERR (1 << 14)
68 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13)
69 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12)
70 #define OMAP_MMC_STAT_A_EMPTY (1 << 11)
71 #define OMAP_MMC_STAT_A_FULL (1 << 10)
72 #define OMAP_MMC_STAT_CMD_CRC (1 << 8)
73 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7)
74 #define OMAP_MMC_STAT_DATA_CRC (1 << 6)
75 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5)
76 #define OMAP_MMC_STAT_END_BUSY (1 << 4)
77 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3)
78 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2)
79 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0)
81 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG_##reg)
82 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG_##reg)
87 #define OMAP_MMC_CMDTYPE_BC 0
88 #define OMAP_MMC_CMDTYPE_BCR 1
89 #define OMAP_MMC_CMDTYPE_AC 2
90 #define OMAP_MMC_CMDTYPE_ADTC 3
93 #define DRIVER_NAME "mmci-omap"
95 /* Specifies how often in millisecs to poll for card status changes
96 * when the cover switch is open */
97 #define OMAP_MMC_SWITCH_POLL_DELAY 500
101 struct mmc_omap_slot {
106 unsigned int fclk_freq;
109 struct work_struct switch_work;
110 struct timer_list switch_timer;
113 struct mmc_request *mrq;
114 struct mmc_omap_host *host;
115 struct mmc_host *mmc;
116 struct omap_mmc_slot_data *pdata;
119 struct mmc_omap_host {
122 struct mmc_request * mrq;
123 struct mmc_command * cmd;
124 struct mmc_data * data;
125 struct mmc_host * mmc;
127 unsigned char id; /* 16xx chips have 2 MMC blocks */
130 struct resource *mem_res;
131 void __iomem *virt_base;
132 unsigned int phys_base;
134 unsigned char bus_mode;
135 unsigned char hw_bus_mode;
137 struct work_struct cmd_abort;
138 struct timer_list cmd_timer;
143 u32 buffer_bytes_left;
144 u32 total_bytes_left;
147 unsigned brs_received:1, dma_done:1;
148 unsigned dma_is_read:1;
149 unsigned dma_in_use:1;
152 struct timer_list dma_timer;
157 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS];
158 struct mmc_omap_slot *current_slot;
159 spinlock_t slot_lock;
160 wait_queue_head_t slot_wq;
163 struct omap_mmc_platform_data *pdata;
166 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed)
168 struct mmc_omap_host *host = slot->host;
173 spin_lock_irqsave(&host->slot_lock, flags);
174 while (host->mmc != NULL) {
175 spin_unlock_irqrestore(&host->slot_lock, flags);
176 wait_event(host->slot_wq, host->mmc == NULL);
177 spin_lock_irqsave(&host->slot_lock, flags);
179 host->mmc = slot->mmc;
180 spin_unlock_irqrestore(&host->slot_lock, flags);
182 clk_enable(host->fclk);
183 if (host->current_slot != slot) {
184 if (host->pdata->switch_slot != NULL)
185 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id);
186 host->current_slot = slot;
189 /* Doing the dummy read here seems to work around some bug
190 * at least in OMAP24xx silicon where the command would not
191 * start after writing the CMD register. Sigh. */
192 OMAP_MMC_READ(host, CON);
194 OMAP_MMC_WRITE(host, CON, slot->saved_con);
197 static void mmc_omap_start_request(struct mmc_omap_host *host,
198 struct mmc_request *req);
200 static void mmc_omap_release_slot(struct mmc_omap_slot *slot)
202 struct mmc_omap_host *host = slot->host;
206 BUG_ON(slot == NULL || host->mmc == NULL);
207 clk_disable(host->fclk);
209 spin_lock_irqsave(&host->slot_lock, flags);
210 /* Check for any pending requests */
211 for (i = 0; i < host->nr_slots; i++) {
212 struct mmc_omap_slot *new_slot;
213 struct mmc_request *rq;
215 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL)
218 new_slot = host->slots[i];
219 /* The current slot should not have a request in queue */
220 BUG_ON(new_slot == host->current_slot);
222 host->mmc = new_slot->mmc;
223 spin_unlock_irqrestore(&host->slot_lock, flags);
224 mmc_omap_select_slot(new_slot, 1);
226 new_slot->mrq = NULL;
227 mmc_omap_start_request(host, rq);
232 wake_up(&host->slot_wq);
233 spin_unlock_irqrestore(&host->slot_lock, flags);
237 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot)
239 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), slot->id);
243 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
246 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
247 struct mmc_omap_slot *slot = mmc_priv(mmc);
249 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" :
253 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
256 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
259 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
260 struct mmc_omap_slot *slot = mmc_priv(mmc);
262 return sprintf(buf, "%s\n", slot->pdata->name);
265 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
268 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd)
279 /* Our hardware needs to know exact type */
280 switch (mmc_resp_type(cmd)) {
285 /* resp 1, 1b, 6, 7 */
295 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd));
299 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) {
300 cmdtype = OMAP_MMC_CMDTYPE_ADTC;
301 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) {
302 cmdtype = OMAP_MMC_CMDTYPE_BC;
303 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) {
304 cmdtype = OMAP_MMC_CMDTYPE_BCR;
306 cmdtype = OMAP_MMC_CMDTYPE_AC;
309 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12);
311 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN)
314 if (cmd->flags & MMC_RSP_BUSY)
317 if (host->data && !(host->data->flags & MMC_DATA_WRITE))
320 mod_timer(&host->cmd_timer, jiffies + HZ/2);
322 OMAP_MMC_WRITE(host, CTO, 200);
323 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff);
324 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16);
325 OMAP_MMC_WRITE(host, IE,
326 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL |
327 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT |
328 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT |
329 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR |
330 OMAP_MMC_STAT_END_OF_DATA);
331 OMAP_MMC_WRITE(host, CMD, cmdreg);
335 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data,
338 enum dma_data_direction dma_data_dir;
340 BUG_ON(host->dma_ch < 0);
342 omap_stop_dma(host->dma_ch);
343 /* Release DMA channel lazily */
344 mod_timer(&host->dma_timer, jiffies + HZ);
345 if (data->flags & MMC_DATA_WRITE)
346 dma_data_dir = DMA_TO_DEVICE;
348 dma_data_dir = DMA_FROM_DEVICE;
349 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_len,
354 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
356 if (host->dma_in_use)
357 mmc_omap_release_dma(host, data, data->error);
362 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing
363 * dozens of requests until the card finishes writing data.
364 * It'd be cheaper to just wait till an EOFB interrupt arrives...
368 struct mmc_host *mmc;
372 mmc_omap_release_slot(host->current_slot);
373 mmc_request_done(mmc, data->mrq);
377 mmc_omap_start_command(host, data->stop);
381 mmc_omap_send_abort(struct mmc_omap_host *host)
383 struct mmc_omap_slot *slot = host->current_slot;
384 unsigned int restarts, passes, timeout;
387 /* Sending abort takes 80 clocks. Have some extra and round up */
388 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq;
390 while (restarts < 10000) {
391 OMAP_MMC_WRITE(host, STAT, 0xFFFF);
392 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7));
395 while (passes < timeout) {
396 stat = OMAP_MMC_READ(host, STAT);
397 if (stat & OMAP_MMC_STAT_END_OF_CMD)
406 OMAP_MMC_WRITE(host, STAT, stat);
410 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data)
414 if (host->dma_in_use)
415 mmc_omap_release_dma(host, data, 1);
420 ie = OMAP_MMC_READ(host, IE);
421 OMAP_MMC_WRITE(host, IE, 0);
422 OMAP_MMC_WRITE(host, IE, ie);
423 mmc_omap_send_abort(host);
427 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data)
432 if (!host->dma_in_use) {
433 mmc_omap_xfer_done(host, data);
437 spin_lock_irqsave(&host->dma_lock, flags);
441 host->brs_received = 1;
442 spin_unlock_irqrestore(&host->dma_lock, flags);
444 mmc_omap_xfer_done(host, data);
448 mmc_omap_dma_timer(unsigned long data)
450 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
452 BUG_ON(host->dma_ch < 0);
453 omap_free_dma(host->dma_ch);
458 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data)
464 spin_lock_irqsave(&host->dma_lock, flags);
465 if (host->brs_received)
469 spin_unlock_irqrestore(&host->dma_lock, flags);
471 mmc_omap_xfer_done(host, data);
475 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
479 del_timer(&host->cmd_timer);
481 if (cmd->flags & MMC_RSP_PRESENT) {
482 if (cmd->flags & MMC_RSP_136) {
483 /* response type 2 */
485 OMAP_MMC_READ(host, RSP0) |
486 (OMAP_MMC_READ(host, RSP1) << 16);
488 OMAP_MMC_READ(host, RSP2) |
489 (OMAP_MMC_READ(host, RSP3) << 16);
491 OMAP_MMC_READ(host, RSP4) |
492 (OMAP_MMC_READ(host, RSP5) << 16);
494 OMAP_MMC_READ(host, RSP6) |
495 (OMAP_MMC_READ(host, RSP7) << 16);
497 /* response types 1, 1b, 3, 4, 5, 6 */
499 OMAP_MMC_READ(host, RSP6) |
500 (OMAP_MMC_READ(host, RSP7) << 16);
504 if (host->data == NULL || cmd->error) {
505 struct mmc_host *mmc;
507 if (host->data != NULL)
508 mmc_omap_abort_xfer(host, host->data);
511 mmc_omap_release_slot(host->current_slot);
512 mmc_request_done(mmc, cmd->mrq);
517 * Abort stuck command. Can occur when card is removed while it is being
520 static void mmc_omap_abort_command(struct work_struct *work)
522 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
526 ie = OMAP_MMC_READ(host, IE);
527 OMAP_MMC_WRITE(host, IE, 0);
530 OMAP_MMC_WRITE(host, IE, ie);
534 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n",
537 if (host->data && host->dma_in_use)
538 mmc_omap_release_dma(host, host->data, 1);
543 mmc_omap_send_abort(host);
544 host->cmd->error = -ETIMEDOUT;
545 mmc_omap_cmd_done(host, host->cmd);
546 OMAP_MMC_WRITE(host, IE, ie);
550 mmc_omap_cmd_timer(unsigned long data)
552 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
554 schedule_work(&host->cmd_abort);
559 mmc_omap_sg_to_buf(struct mmc_omap_host *host)
561 struct scatterlist *sg;
563 sg = host->data->sg + host->sg_idx;
564 host->buffer_bytes_left = sg->length;
565 host->buffer = sg_virt(sg);
566 if (host->buffer_bytes_left > host->total_bytes_left)
567 host->buffer_bytes_left = host->total_bytes_left;
572 mmc_omap_xfer_data(struct mmc_omap_host *host, int write)
576 if (host->buffer_bytes_left == 0) {
578 BUG_ON(host->sg_idx == host->sg_len);
579 mmc_omap_sg_to_buf(host);
582 if (n > host->buffer_bytes_left)
583 n = host->buffer_bytes_left;
584 host->buffer_bytes_left -= n;
585 host->total_bytes_left -= n;
586 host->data->bytes_xfered += n;
589 __raw_writesw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
591 __raw_readsw(host->virt_base + OMAP_MMC_REG_DATA, host->buffer, n);
595 static inline void mmc_omap_report_irq(u16 status)
597 static const char *mmc_omap_status_bits[] = {
598 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO",
599 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR"
603 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
604 if (status & (1 << i)) {
607 printk("%s", mmc_omap_status_bits[i]);
612 static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
614 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id;
618 int transfer_error, cmd_error;
620 if (host->cmd == NULL && host->data == NULL) {
621 status = OMAP_MMC_READ(host, STAT);
622 dev_info(mmc_dev(host->slots[0]->mmc),
623 "Spurious IRQ 0x%04x\n", status);
625 OMAP_MMC_WRITE(host, STAT, status);
626 OMAP_MMC_WRITE(host, IE, 0);
636 while ((status = OMAP_MMC_READ(host, STAT)) != 0) {
639 OMAP_MMC_WRITE(host, STAT, status);
640 if (host->cmd != NULL)
641 cmd = host->cmd->opcode;
644 #ifdef CONFIG_MMC_DEBUG
645 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ",
647 mmc_omap_report_irq(status);
650 if (host->total_bytes_left) {
651 if ((status & OMAP_MMC_STAT_A_FULL) ||
652 (status & OMAP_MMC_STAT_END_OF_DATA))
653 mmc_omap_xfer_data(host, 0);
654 if (status & OMAP_MMC_STAT_A_EMPTY)
655 mmc_omap_xfer_data(host, 1);
658 if (status & OMAP_MMC_STAT_END_OF_DATA)
661 if (status & OMAP_MMC_STAT_DATA_TOUT) {
662 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n",
665 host->data->error = -ETIMEDOUT;
670 if (status & OMAP_MMC_STAT_DATA_CRC) {
672 host->data->error = -EILSEQ;
673 dev_dbg(mmc_dev(host->mmc),
674 "data CRC error, bytes left %d\n",
675 host->total_bytes_left);
678 dev_dbg(mmc_dev(host->mmc), "data CRC error\n");
682 if (status & OMAP_MMC_STAT_CMD_TOUT) {
683 /* Timeouts are routine with some commands */
685 struct mmc_omap_slot *slot =
688 !mmc_omap_cover_is_open(slot))
689 dev_err(mmc_dev(host->mmc),
690 "command timeout (CMD%d)\n",
692 host->cmd->error = -ETIMEDOUT;
698 if (status & OMAP_MMC_STAT_CMD_CRC) {
700 dev_err(mmc_dev(host->mmc),
701 "command CRC error (CMD%d, arg 0x%08x)\n",
702 cmd, host->cmd->arg);
703 host->cmd->error = -EILSEQ;
707 dev_err(mmc_dev(host->mmc),
708 "command CRC error without cmd?\n");
711 if (status & OMAP_MMC_STAT_CARD_ERR) {
712 dev_dbg(mmc_dev(host->mmc),
713 "ignoring card status error (CMD%d)\n",
719 * NOTE: On 1610 the END_OF_CMD may come too early when
722 if ((status & OMAP_MMC_STAT_END_OF_CMD) &&
723 (!(status & OMAP_MMC_STAT_A_EMPTY))) {
729 mmc_omap_cmd_done(host, host->cmd);
730 if (host->data != NULL) {
732 mmc_omap_xfer_done(host, host->data);
733 else if (end_transfer)
734 mmc_omap_end_of_data(host, host->data);
740 void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed)
742 struct mmc_omap_host *host = dev_get_drvdata(dev);
744 BUG_ON(slot >= host->nr_slots);
746 /* Other subsystems can call in here before we're initialised. */
747 if (host->nr_slots == 0 || !host->slots[slot])
750 schedule_work(&host->slots[slot]->switch_work);
753 static void mmc_omap_switch_timer(unsigned long arg)
755 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg;
757 schedule_work(&slot->switch_work);
760 static void mmc_omap_cover_handler(struct work_struct *work)
762 struct mmc_omap_slot *slot = container_of(work, struct mmc_omap_slot,
766 cover_open = mmc_omap_cover_is_open(slot);
767 if (cover_open != slot->cover_open) {
768 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch");
769 slot->cover_open = cover_open;
770 dev_info(mmc_dev(slot->mmc), "cover is now %s\n",
771 cover_open ? "open" : "closed");
773 mmc_detect_change(slot->mmc, slot->id);
776 /* Prepare to transfer the next segment of a scatterlist */
778 mmc_omap_prepare_dma(struct mmc_omap_host *host, struct mmc_data *data)
780 int dma_ch = host->dma_ch;
781 unsigned long data_addr;
784 struct scatterlist *sg = &data->sg[host->sg_idx];
789 data_addr = host->phys_base + OMAP_MMC_REG_DATA;
791 count = sg_dma_len(sg);
793 if ((data->blocks == 1) && (count > data->blksz))
796 host->dma_len = count;
798 /* FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx and 24xx.
799 * Use 16 or 32 word frames when the blocksize is at least that large.
800 * Blocksize is usually 512 bytes; but not for some SD reads.
802 if (cpu_is_omap15xx() && frame > 32)
809 if (!(data->flags & MMC_DATA_WRITE)) {
810 buf = 0x800f | ((frame - 1) << 8);
812 if (cpu_class_is_omap1()) {
813 src_port = OMAP_DMA_PORT_TIPB;
814 dst_port = OMAP_DMA_PORT_EMIFF;
816 if (cpu_is_omap24xx())
817 sync_dev = OMAP24XX_DMA_MMC1_RX;
819 omap_set_dma_src_params(dma_ch, src_port,
820 OMAP_DMA_AMODE_CONSTANT,
822 omap_set_dma_dest_params(dma_ch, dst_port,
823 OMAP_DMA_AMODE_POST_INC,
824 sg_dma_address(sg), 0, 0);
825 omap_set_dma_dest_data_pack(dma_ch, 1);
826 omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
828 buf = 0x0f80 | ((frame - 1) << 0);
830 if (cpu_class_is_omap1()) {
831 src_port = OMAP_DMA_PORT_EMIFF;
832 dst_port = OMAP_DMA_PORT_TIPB;
834 if (cpu_is_omap24xx())
835 sync_dev = OMAP24XX_DMA_MMC1_TX;
837 omap_set_dma_dest_params(dma_ch, dst_port,
838 OMAP_DMA_AMODE_CONSTANT,
840 omap_set_dma_src_params(dma_ch, src_port,
841 OMAP_DMA_AMODE_POST_INC,
842 sg_dma_address(sg), 0, 0);
843 omap_set_dma_src_data_pack(dma_ch, 1);
844 omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
847 /* Max limit for DMA frame count is 0xffff */
848 BUG_ON(count > 0xffff);
850 OMAP_MMC_WRITE(host, BUF, buf);
851 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
852 frame, count, OMAP_DMA_SYNC_FRAME,
856 /* A scatterlist segment completed */
857 static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
859 struct mmc_omap_host *host = (struct mmc_omap_host *) data;
860 struct mmc_data *mmcdat = host->data;
862 if (unlikely(host->dma_ch < 0)) {
863 dev_err(mmc_dev(host->mmc),
864 "DMA callback while DMA not enabled\n");
867 /* FIXME: We really should do something to _handle_ the errors */
868 if (ch_status & OMAP1_DMA_TOUT_IRQ) {
869 dev_err(mmc_dev(host->mmc),"DMA timeout\n");
872 if (ch_status & OMAP_DMA_DROP_IRQ) {
873 dev_err(mmc_dev(host->mmc), "DMA sync error\n");
876 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
879 mmcdat->bytes_xfered += host->dma_len;
881 if (host->sg_idx < host->sg_len) {
882 mmc_omap_prepare_dma(host, host->data);
883 omap_start_dma(host->dma_ch);
885 mmc_omap_dma_done(host, host->data);
888 static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
890 const char *dev_name;
891 int sync_dev, dma_ch, is_read, r;
893 is_read = !(data->flags & MMC_DATA_WRITE);
894 del_timer_sync(&host->dma_timer);
895 if (host->dma_ch >= 0) {
896 if (is_read == host->dma_is_read)
898 omap_free_dma(host->dma_ch);
904 sync_dev = OMAP_DMA_MMC_RX;
905 dev_name = "MMC1 read";
907 sync_dev = OMAP_DMA_MMC2_RX;
908 dev_name = "MMC2 read";
912 sync_dev = OMAP_DMA_MMC_TX;
913 dev_name = "MMC1 write";
915 sync_dev = OMAP_DMA_MMC2_TX;
916 dev_name = "MMC2 write";
919 r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
922 dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
925 host->dma_ch = dma_ch;
926 host->dma_is_read = is_read;
931 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req)
935 reg = OMAP_MMC_READ(host, SDIO);
937 OMAP_MMC_WRITE(host, SDIO, reg);
938 /* Set maximum timeout */
939 OMAP_MMC_WRITE(host, CTO, 0xff);
942 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req)
944 unsigned int timeout, cycle_ns;
947 cycle_ns = 1000000000 / host->current_slot->fclk_freq;
948 timeout = req->data->timeout_ns / cycle_ns;
949 timeout += req->data->timeout_clks;
951 /* Check if we need to use timeout multiplier register */
952 reg = OMAP_MMC_READ(host, SDIO);
953 if (timeout > 0xffff) {
958 OMAP_MMC_WRITE(host, SDIO, reg);
959 OMAP_MMC_WRITE(host, DTO, timeout);
963 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
965 struct mmc_data *data = req->data;
966 int i, use_dma, block_size;
971 OMAP_MMC_WRITE(host, BLEN, 0);
972 OMAP_MMC_WRITE(host, NBLK, 0);
973 OMAP_MMC_WRITE(host, BUF, 0);
974 host->dma_in_use = 0;
975 set_cmd_timeout(host, req);
979 block_size = data->blksz;
981 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1);
982 OMAP_MMC_WRITE(host, BLEN, block_size - 1);
983 set_data_timeout(host, req);
985 /* cope with calling layer confusion; it issues "single
986 * block" writes using multi-block scatterlists.
988 sg_len = (data->blocks == 1) ? 1 : data->sg_len;
990 /* Only do DMA for entire blocks */
991 use_dma = host->use_dma;
993 for (i = 0; i < sg_len; i++) {
994 if ((data->sg[i].length % block_size) != 0) {
1003 if (mmc_omap_get_dma_channel(host, data) == 0) {
1004 enum dma_data_direction dma_data_dir;
1006 if (data->flags & MMC_DATA_WRITE)
1007 dma_data_dir = DMA_TO_DEVICE;
1009 dma_data_dir = DMA_FROM_DEVICE;
1011 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1012 sg_len, dma_data_dir);
1013 host->total_bytes_left = 0;
1014 mmc_omap_prepare_dma(host, req->data);
1015 host->brs_received = 0;
1017 host->dma_in_use = 1;
1022 /* Revert to PIO? */
1024 OMAP_MMC_WRITE(host, BUF, 0x1f1f);
1025 host->total_bytes_left = data->blocks * block_size;
1026 host->sg_len = sg_len;
1027 mmc_omap_sg_to_buf(host);
1028 host->dma_in_use = 0;
1032 static void mmc_omap_start_request(struct mmc_omap_host *host,
1033 struct mmc_request *req)
1035 BUG_ON(host->mrq != NULL);
1039 /* only touch fifo AFTER the controller readies it */
1040 mmc_omap_prepare_data(host, req);
1041 mmc_omap_start_command(host, req->cmd);
1042 if (host->dma_in_use)
1043 omap_start_dma(host->dma_ch);
1044 BUG_ON(irqs_disabled());
1047 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req)
1049 struct mmc_omap_slot *slot = mmc_priv(mmc);
1050 struct mmc_omap_host *host = slot->host;
1051 unsigned long flags;
1053 spin_lock_irqsave(&host->slot_lock, flags);
1054 if (host->mmc != NULL) {
1055 BUG_ON(slot->mrq != NULL);
1057 spin_unlock_irqrestore(&host->slot_lock, flags);
1061 spin_unlock_irqrestore(&host->slot_lock, flags);
1062 mmc_omap_select_slot(slot, 1);
1063 mmc_omap_start_request(host, req);
1066 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on,
1069 struct mmc_omap_host *host;
1073 if (slot->pdata->set_power != NULL)
1074 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on,
1077 if (cpu_is_omap24xx()) {
1081 w = OMAP_MMC_READ(host, CON);
1082 OMAP_MMC_WRITE(host, CON, w | (1 << 11));
1084 w = OMAP_MMC_READ(host, CON);
1085 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11));
1090 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios)
1092 struct mmc_omap_slot *slot = mmc_priv(mmc);
1093 struct mmc_omap_host *host = slot->host;
1094 int func_clk_rate = clk_get_rate(host->fclk);
1097 if (ios->clock == 0)
1100 dsor = func_clk_rate / ios->clock;
1104 if (func_clk_rate / dsor > ios->clock)
1110 slot->fclk_freq = func_clk_rate / dsor;
1112 if (ios->bus_width == MMC_BUS_WIDTH_4)
1118 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1120 struct mmc_omap_slot *slot = mmc_priv(mmc);
1121 struct mmc_omap_host *host = slot->host;
1124 dsor = mmc_omap_calc_divisor(mmc, ios);
1126 mmc_omap_select_slot(slot, 0);
1128 if (ios->vdd != slot->vdd)
1129 slot->vdd = ios->vdd;
1131 switch (ios->power_mode) {
1133 mmc_omap_set_power(slot, 0, ios->vdd);
1136 /* Cannot touch dsor yet, just power up MMC */
1137 mmc_omap_set_power(slot, 1, ios->vdd);
1144 if (slot->bus_mode != ios->bus_mode) {
1145 if (slot->pdata->set_bus_mode != NULL)
1146 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id,
1148 slot->bus_mode = ios->bus_mode;
1151 /* On insanely high arm_per frequencies something sometimes
1152 * goes somehow out of sync, and the POW bit is not being set,
1153 * which results in the while loop below getting stuck.
1154 * Writing to the CON register twice seems to do the trick. */
1155 for (i = 0; i < 2; i++)
1156 OMAP_MMC_WRITE(host, CON, dsor);
1157 slot->saved_con = dsor;
1158 if (ios->power_mode == MMC_POWER_ON) {
1159 /* Send clock cycles, poll completion */
1160 OMAP_MMC_WRITE(host, IE, 0);
1161 OMAP_MMC_WRITE(host, STAT, 0xffff);
1162 OMAP_MMC_WRITE(host, CMD, 1 << 7);
1163 while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
1164 OMAP_MMC_WRITE(host, STAT, 1);
1168 mmc_omap_release_slot(slot);
1171 static const struct mmc_host_ops mmc_omap_ops = {
1172 .request = mmc_omap_request,
1173 .set_ios = mmc_omap_set_ios,
1176 static int __init mmc_omap_new_slot(struct mmc_omap_host *host, int id)
1178 struct mmc_omap_slot *slot = NULL;
1179 struct mmc_host *mmc;
1182 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev);
1186 slot = mmc_priv(mmc);
1190 slot->pdata = &host->pdata->slots[id];
1192 host->slots[id] = slot;
1194 mmc->caps = MMC_CAP_MULTIWRITE;
1195 if (host->pdata->conf.wire4)
1196 mmc->caps |= MMC_CAP_4_BIT_DATA;
1198 mmc->ops = &mmc_omap_ops;
1199 mmc->f_min = 400000;
1201 if (cpu_class_is_omap2())
1202 mmc->f_max = 48000000;
1204 mmc->f_max = 24000000;
1205 if (host->pdata->max_freq)
1206 mmc->f_max = min(host->pdata->max_freq, mmc->f_max);
1207 mmc->ocr_avail = slot->pdata->ocr_mask;
1209 /* Use scatterlist DMA to reduce per-transfer costs.
1210 * NOTE max_seg_size assumption that small blocks aren't
1211 * normally used (except e.g. for reading SD registers).
1213 mmc->max_phys_segs = 32;
1214 mmc->max_hw_segs = 32;
1215 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */
1216 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */
1217 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1218 mmc->max_seg_size = mmc->max_req_size;
1220 r = mmc_add_host(mmc);
1222 goto err_remove_host;
1224 if (slot->pdata->name != NULL) {
1225 r = device_create_file(&mmc->class_dev,
1226 &dev_attr_slot_name);
1228 goto err_remove_host;
1231 if (slot->pdata->get_cover_state != NULL) {
1232 r = device_create_file(&mmc->class_dev,
1233 &dev_attr_cover_switch);
1235 goto err_remove_slot_name;
1237 INIT_WORK(&slot->switch_work, mmc_omap_cover_handler);
1238 setup_timer(&slot->switch_timer, mmc_omap_switch_timer,
1239 (unsigned long) slot);
1240 schedule_work(&slot->switch_work);
1245 err_remove_slot_name:
1246 if (slot->pdata->name != NULL)
1247 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1249 mmc_remove_host(mmc);
1254 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot)
1256 struct mmc_host *mmc = slot->mmc;
1258 if (slot->pdata->name != NULL)
1259 device_remove_file(&mmc->class_dev, &dev_attr_slot_name);
1260 if (slot->pdata->get_cover_state != NULL)
1261 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1263 del_timer_sync(&slot->switch_timer);
1264 flush_scheduled_work();
1266 mmc_remove_host(mmc);
1270 static int __init mmc_omap_probe(struct platform_device *pdev)
1272 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1273 struct mmc_omap_host *host = NULL;
1274 struct resource *res;
1278 if (pdata == NULL) {
1279 dev_err(&pdev->dev, "platform data missing\n");
1282 if (pdata->nr_slots == 0) {
1283 dev_err(&pdev->dev, "no slots\n");
1287 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1288 irq = platform_get_irq(pdev, 0);
1289 if (res == NULL || irq < 0)
1292 res = request_mem_region(res->start, res->end - res->start + 1,
1297 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL);
1300 goto err_free_mem_region;
1303 INIT_WORK(&host->cmd_abort, mmc_omap_abort_command);
1304 setup_timer(&host->cmd_timer, mmc_omap_cmd_timer, (unsigned long) host);
1306 spin_lock_init(&host->dma_lock);
1307 setup_timer(&host->dma_timer, mmc_omap_dma_timer, (unsigned long) host);
1308 spin_lock_init(&host->slot_lock);
1309 init_waitqueue_head(&host->slot_wq);
1311 host->pdata = pdata;
1312 host->dev = &pdev->dev;
1313 platform_set_drvdata(pdev, host);
1315 host->id = pdev->id;
1316 host->mem_res = res;
1323 host->phys_base = host->mem_res->start;
1324 host->virt_base = (void __iomem *) IO_ADDRESS(host->phys_base);
1326 if (cpu_is_omap24xx()) {
1327 host->iclk = clk_get(&pdev->dev, "mmc_ick");
1328 if (IS_ERR(host->iclk))
1329 goto err_free_mmc_host;
1330 clk_enable(host->iclk);
1333 if (!cpu_is_omap24xx())
1334 host->fclk = clk_get(&pdev->dev, "mmc_ck");
1336 host->fclk = clk_get(&pdev->dev, "mmc_fck");
1338 if (IS_ERR(host->fclk)) {
1339 ret = PTR_ERR(host->fclk);
1343 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host);
1347 if (pdata->init != NULL) {
1348 ret = pdata->init(&pdev->dev);
1353 host->nr_slots = pdata->nr_slots;
1354 for (i = 0; i < pdata->nr_slots; i++) {
1355 ret = mmc_omap_new_slot(host, i);
1358 mmc_omap_remove_slot(host->slots[i]);
1360 goto err_plat_cleanup;
1368 pdata->cleanup(&pdev->dev);
1370 free_irq(host->irq, host);
1372 clk_put(host->fclk);
1374 if (host->iclk != NULL) {
1375 clk_disable(host->iclk);
1376 clk_put(host->iclk);
1380 err_free_mem_region:
1381 release_mem_region(res->start, res->end - res->start + 1);
1385 static int mmc_omap_remove(struct platform_device *pdev)
1387 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1390 platform_set_drvdata(pdev, NULL);
1392 BUG_ON(host == NULL);
1394 for (i = 0; i < host->nr_slots; i++)
1395 mmc_omap_remove_slot(host->slots[i]);
1397 if (host->pdata->cleanup)
1398 host->pdata->cleanup(&pdev->dev);
1400 if (host->iclk && !IS_ERR(host->iclk))
1401 clk_put(host->iclk);
1402 if (host->fclk && !IS_ERR(host->fclk))
1403 clk_put(host->fclk);
1405 release_mem_region(pdev->resource[0].start,
1406 pdev->resource[0].end - pdev->resource[0].start + 1);
1414 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg)
1417 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1419 if (host == NULL || host->suspended)
1422 for (i = 0; i < host->nr_slots; i++) {
1423 struct mmc_omap_slot *slot;
1425 slot = host->slots[i];
1426 ret = mmc_suspend_host(slot->mmc, mesg);
1429 slot = host->slots[i];
1430 mmc_resume_host(slot->mmc);
1435 host->suspended = 1;
1439 static int mmc_omap_resume(struct platform_device *pdev)
1442 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1444 if (host == NULL || !host->suspended)
1447 for (i = 0; i < host->nr_slots; i++) {
1448 struct mmc_omap_slot *slot;
1449 slot = host->slots[i];
1450 ret = mmc_resume_host(slot->mmc);
1454 host->suspended = 0;
1459 #define mmc_omap_suspend NULL
1460 #define mmc_omap_resume NULL
1463 static struct platform_driver mmc_omap_driver = {
1464 .probe = mmc_omap_probe,
1465 .remove = mmc_omap_remove,
1466 .suspend = mmc_omap_suspend,
1467 .resume = mmc_omap_resume,
1469 .name = DRIVER_NAME,
1470 .owner = THIS_MODULE,
1474 static int __init mmc_omap_init(void)
1476 return platform_driver_register(&mmc_omap_driver);
1479 static void __exit mmc_omap_exit(void)
1481 platform_driver_unregister(&mmc_omap_driver);
1484 module_init(mmc_omap_init);
1485 module_exit(mmc_omap_exit);
1487 MODULE_DESCRIPTION("OMAP Multimedia Card driver");
1488 MODULE_LICENSE("GPL");
1489 MODULE_ALIAS("platform:" DRIVER_NAME);
1490 MODULE_AUTHOR("Juha Yrjölä");