2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/platform_device.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/dmaengine.h>
31 #include <linux/highmem.h>
32 #include <linux/clk.h>
33 #include <linux/err.h>
34 #include <linux/completion.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/mmc/sdio.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/module.h>
43 #include <mach/common.h>
47 #define DRIVER_NAME "mxs-mmc"
49 /* card detect polling timeout */
50 #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
52 #define SSP_VERSION_LATEST 4
53 #define ssp_is_old() (host->version < SSP_VERSION_LATEST)
56 #define HW_SSP_CTRL0 0x000
57 #define BM_SSP_CTRL0_RUN (1 << 29)
58 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
59 #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
60 #define BM_SSP_CTRL0_READ (1 << 25)
61 #define BM_SSP_CTRL0_DATA_XFER (1 << 24)
62 #define BP_SSP_CTRL0_BUS_WIDTH (22)
63 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
64 #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
65 #define BM_SSP_CTRL0_LONG_RESP (1 << 19)
66 #define BM_SSP_CTRL0_GET_RESP (1 << 17)
67 #define BM_SSP_CTRL0_ENABLE (1 << 16)
68 #define BP_SSP_CTRL0_XFER_COUNT (0)
69 #define BM_SSP_CTRL0_XFER_COUNT (0xffff)
70 #define HW_SSP_CMD0 0x010
71 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
72 #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
73 #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
74 #define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
75 #define BP_SSP_CMD0_BLOCK_SIZE (16)
76 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
77 #define BP_SSP_CMD0_BLOCK_COUNT (8)
78 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
79 #define BP_SSP_CMD0_CMD (0)
80 #define BM_SSP_CMD0_CMD (0xff)
81 #define HW_SSP_CMD1 0x020
82 #define HW_SSP_XFER_SIZE 0x030
83 #define HW_SSP_BLOCK_SIZE 0x040
84 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
85 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
86 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
87 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
88 #define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070)
89 #define BP_SSP_TIMING_TIMEOUT (16)
90 #define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
91 #define BP_SSP_TIMING_CLOCK_DIVIDE (8)
92 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
93 #define BP_SSP_TIMING_CLOCK_RATE (0)
94 #define BM_SSP_TIMING_CLOCK_RATE (0xff)
95 #define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080)
96 #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
97 #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
98 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
99 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
100 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
101 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
102 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
103 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
104 #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
105 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
106 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
107 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
108 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
109 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
110 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
111 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
112 #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
113 #define BM_SSP_CTRL1_POLARITY (1 << 9)
114 #define BP_SSP_CTRL1_WORD_LENGTH (4)
115 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
116 #define BP_SSP_CTRL1_SSP_MODE (0)
117 #define BM_SSP_CTRL1_SSP_MODE (0xf)
118 #define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0)
119 #define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0)
120 #define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0)
121 #define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0)
122 #define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100)
123 #define BM_SSP_STATUS_CARD_DETECT (1 << 28)
124 #define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
125 #define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130)
126 #define BP_SSP_VERSION_MAJOR (24)
128 #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
130 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
131 BM_SSP_CTRL1_RESP_ERR_IRQ | \
132 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
134 BM_SSP_CTRL1_DATA_CRC_IRQ | \
135 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
136 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
137 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
139 #define SSP_PIO_NUM 3
141 struct mxs_mmc_host {
142 struct mmc_host *mmc;
143 struct mmc_request *mrq;
144 struct mmc_command *cmd;
145 struct mmc_data *data;
149 struct resource *res;
150 struct resource *dma_res;
152 unsigned int clk_rate;
154 struct dma_chan *dmach;
155 struct mxs_dma_data dma_data;
156 unsigned int dma_dir;
157 u32 ssp_pio_words[SSP_PIO_NUM];
159 unsigned int version;
160 unsigned char bus_width;
165 static int mxs_mmc_get_ro(struct mmc_host *mmc)
167 struct mxs_mmc_host *host = mmc_priv(mmc);
168 struct mxs_mmc_platform_data *pdata =
169 mmc_dev(host->mmc)->platform_data;
174 if (!gpio_is_valid(pdata->wp_gpio))
177 return gpio_get_value(pdata->wp_gpio);
180 static int mxs_mmc_get_cd(struct mmc_host *mmc)
182 struct mxs_mmc_host *host = mmc_priv(mmc);
184 return !(readl(host->base + HW_SSP_STATUS) &
185 BM_SSP_STATUS_CARD_DETECT);
188 static void mxs_mmc_reset(struct mxs_mmc_host *host)
192 mxs_reset_block(host->base);
194 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
195 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
196 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
197 BM_SSP_CTRL1_DMA_ENABLE |
198 BM_SSP_CTRL1_POLARITY |
199 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
200 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
201 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
202 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
203 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
205 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
206 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
207 BF_SSP(0, TIMING_CLOCK_RATE),
208 host->base + HW_SSP_TIMING);
210 if (host->sdio_irq_en) {
211 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
212 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
215 writel(ctrl0, host->base + HW_SSP_CTRL0);
216 writel(ctrl1, host->base + HW_SSP_CTRL1);
219 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
220 struct mmc_command *cmd);
222 static void mxs_mmc_request_done(struct mxs_mmc_host *host)
224 struct mmc_command *cmd = host->cmd;
225 struct mmc_data *data = host->data;
226 struct mmc_request *mrq = host->mrq;
228 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
229 if (mmc_resp_type(cmd) & MMC_RSP_136) {
230 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0);
231 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1);
232 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2);
233 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3);
235 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0);
240 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
241 data->sg_len, host->dma_dir);
243 * If there was an error on any block, we mark all
244 * data blocks as being in error.
247 data->bytes_xfered = data->blocks * data->blksz;
249 data->bytes_xfered = 0;
253 mxs_mmc_start_cmd(host, mrq->stop);
259 mmc_request_done(host->mmc, mrq);
262 static void mxs_mmc_dma_irq_callback(void *param)
264 struct mxs_mmc_host *host = param;
266 mxs_mmc_request_done(host);
269 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
271 struct mxs_mmc_host *host = dev_id;
272 struct mmc_command *cmd = host->cmd;
273 struct mmc_data *data = host->data;
276 spin_lock(&host->lock);
278 stat = readl(host->base + HW_SSP_CTRL1);
279 writel(stat & MXS_MMC_IRQ_BITS,
280 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
282 spin_unlock(&host->lock);
284 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
285 mmc_signal_sdio_irq(host->mmc);
287 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
288 cmd->error = -ETIMEDOUT;
289 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
293 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
294 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
295 data->error = -ETIMEDOUT;
296 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
297 data->error = -EILSEQ;
298 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
299 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
306 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
307 struct mxs_mmc_host *host, unsigned int append)
309 struct dma_async_tx_descriptor *desc;
310 struct mmc_data *data = host->data;
311 struct scatterlist * sgl;
316 dma_map_sg(mmc_dev(host->mmc), data->sg,
317 data->sg_len, host->dma_dir);
319 sg_len = data->sg_len;
322 sgl = (struct scatterlist *) host->ssp_pio_words;
323 sg_len = SSP_PIO_NUM;
326 desc = host->dmach->device->device_prep_slave_sg(host->dmach,
327 sgl, sg_len, host->dma_dir, append);
329 desc->callback = mxs_mmc_dma_irq_callback;
330 desc->callback_param = host;
333 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
334 data->sg_len, host->dma_dir);
340 static void mxs_mmc_bc(struct mxs_mmc_host *host)
342 struct mmc_command *cmd = host->cmd;
343 struct dma_async_tx_descriptor *desc;
344 u32 ctrl0, cmd0, cmd1;
346 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
347 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
350 if (host->sdio_irq_en) {
351 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
352 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
355 host->ssp_pio_words[0] = ctrl0;
356 host->ssp_pio_words[1] = cmd0;
357 host->ssp_pio_words[2] = cmd1;
358 host->dma_dir = DMA_NONE;
359 desc = mxs_mmc_prep_dma(host, 0);
363 dmaengine_submit(desc);
367 dev_warn(mmc_dev(host->mmc),
368 "%s: failed to prep dma\n", __func__);
371 static void mxs_mmc_ac(struct mxs_mmc_host *host)
373 struct mmc_command *cmd = host->cmd;
374 struct dma_async_tx_descriptor *desc;
375 u32 ignore_crc, get_resp, long_resp;
376 u32 ctrl0, cmd0, cmd1;
378 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
379 0 : BM_SSP_CTRL0_IGNORE_CRC;
380 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
381 BM_SSP_CTRL0_GET_RESP : 0;
382 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
383 BM_SSP_CTRL0_LONG_RESP : 0;
385 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
386 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
389 if (cmd->opcode == MMC_STOP_TRANSMISSION)
390 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
392 if (host->sdio_irq_en) {
393 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
394 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
397 host->ssp_pio_words[0] = ctrl0;
398 host->ssp_pio_words[1] = cmd0;
399 host->ssp_pio_words[2] = cmd1;
400 host->dma_dir = DMA_NONE;
401 desc = mxs_mmc_prep_dma(host, 0);
405 dmaengine_submit(desc);
409 dev_warn(mmc_dev(host->mmc),
410 "%s: failed to prep dma\n", __func__);
413 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
415 const unsigned int ssp_timeout_mul = 4096;
417 * Calculate ticks in ms since ns are large numbers
420 const unsigned int clock_per_ms = clock_rate / 1000;
421 const unsigned int ms = ns / 1000;
422 const unsigned int ticks = ms * clock_per_ms;
423 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
425 WARN_ON(ssp_ticks == 0);
429 static void mxs_mmc_adtc(struct mxs_mmc_host *host)
431 struct mmc_command *cmd = host->cmd;
432 struct mmc_data *data = cmd->data;
433 struct dma_async_tx_descriptor *desc;
434 struct scatterlist *sgl = data->sg, *sg;
435 unsigned int sg_len = data->sg_len;
438 unsigned short dma_data_dir, timeout;
439 unsigned int data_size = 0, log2_blksz;
440 unsigned int blocks = data->blocks;
442 u32 ignore_crc, get_resp, long_resp, read;
443 u32 ctrl0, cmd0, cmd1, val;
445 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
446 0 : BM_SSP_CTRL0_IGNORE_CRC;
447 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
448 BM_SSP_CTRL0_GET_RESP : 0;
449 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
450 BM_SSP_CTRL0_LONG_RESP : 0;
452 if (data->flags & MMC_DATA_WRITE) {
453 dma_data_dir = DMA_TO_DEVICE;
456 dma_data_dir = DMA_FROM_DEVICE;
457 read = BM_SSP_CTRL0_READ;
460 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
461 ignore_crc | get_resp | long_resp |
462 BM_SSP_CTRL0_DATA_XFER | read |
463 BM_SSP_CTRL0_WAIT_FOR_IRQ |
466 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
468 /* get logarithm to base 2 of block size for setting register */
469 log2_blksz = ilog2(data->blksz);
472 * take special care of the case that data size from data->sg
473 * is not equal to blocks x blksz
475 for_each_sg(sgl, sg, sg_len, i)
476 data_size += sg->length;
478 if (data_size != data->blocks * data->blksz)
481 /* xfer count, block size and count need to be set differently */
483 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
484 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
485 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
487 writel(data_size, host->base + HW_SSP_XFER_SIZE);
488 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
489 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
490 host->base + HW_SSP_BLOCK_SIZE);
493 if (cmd->opcode == SD_IO_RW_EXTENDED)
494 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
498 if (host->sdio_irq_en) {
499 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
500 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
503 /* set the timeout count */
504 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
505 val = readl(host->base + HW_SSP_TIMING);
506 val &= ~(BM_SSP_TIMING_TIMEOUT);
507 val |= BF_SSP(timeout, TIMING_TIMEOUT);
508 writel(val, host->base + HW_SSP_TIMING);
511 host->ssp_pio_words[0] = ctrl0;
512 host->ssp_pio_words[1] = cmd0;
513 host->ssp_pio_words[2] = cmd1;
514 host->dma_dir = DMA_NONE;
515 desc = mxs_mmc_prep_dma(host, 0);
520 WARN_ON(host->data != NULL);
522 host->dma_dir = dma_data_dir;
523 desc = mxs_mmc_prep_dma(host, 1);
527 dmaengine_submit(desc);
530 dev_warn(mmc_dev(host->mmc),
531 "%s: failed to prep dma\n", __func__);
534 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
535 struct mmc_command *cmd)
539 switch (mmc_cmd_type(cmd)) {
553 dev_warn(mmc_dev(host->mmc),
554 "%s: unknown MMC command\n", __func__);
559 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
561 struct mxs_mmc_host *host = mmc_priv(mmc);
563 WARN_ON(host->mrq != NULL);
565 mxs_mmc_start_cmd(host, mrq->cmd);
568 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
570 unsigned int ssp_clk, ssp_sck;
571 u32 clock_divide, clock_rate;
574 ssp_clk = clk_get_rate(host->clk);
576 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
577 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
578 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
579 if (clock_rate <= 255)
583 if (clock_divide > 254) {
584 dev_err(mmc_dev(host->mmc),
585 "%s: cannot set clock to %d\n", __func__, rate);
589 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
591 val = readl(host->base + HW_SSP_TIMING);
592 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
593 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
594 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
595 writel(val, host->base + HW_SSP_TIMING);
597 host->clk_rate = ssp_sck;
599 dev_dbg(mmc_dev(host->mmc),
600 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
601 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
604 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
606 struct mxs_mmc_host *host = mmc_priv(mmc);
608 if (ios->bus_width == MMC_BUS_WIDTH_8)
610 else if (ios->bus_width == MMC_BUS_WIDTH_4)
616 mxs_mmc_set_clk_rate(host, ios->clock);
619 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
621 struct mxs_mmc_host *host = mmc_priv(mmc);
624 spin_lock_irqsave(&host->lock, flags);
626 host->sdio_irq_en = enable;
629 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
630 host->base + HW_SSP_CTRL0 + MXS_SET_ADDR);
631 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
632 host->base + HW_SSP_CTRL1 + MXS_SET_ADDR);
634 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
635 host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR);
636 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
637 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
640 spin_unlock_irqrestore(&host->lock, flags);
642 if (enable && readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ)
643 mmc_signal_sdio_irq(host->mmc);
647 static const struct mmc_host_ops mxs_mmc_ops = {
648 .request = mxs_mmc_request,
649 .get_ro = mxs_mmc_get_ro,
650 .get_cd = mxs_mmc_get_cd,
651 .set_ios = mxs_mmc_set_ios,
652 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
655 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
657 struct mxs_mmc_host *host = param;
659 if (!mxs_dma_is_apbh(chan))
662 if (chan->chan_id != host->dma_res->start)
665 chan->private = &host->dma_data;
670 static int mxs_mmc_probe(struct platform_device *pdev)
672 struct mxs_mmc_host *host;
673 struct mmc_host *mmc;
674 struct resource *iores, *dmares, *r;
675 struct mxs_mmc_platform_data *pdata;
676 int ret = 0, irq_err, irq_dma;
679 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
680 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
681 irq_err = platform_get_irq(pdev, 0);
682 irq_dma = platform_get_irq(pdev, 1);
683 if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
686 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
690 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
693 goto out_release_mem;
696 host = mmc_priv(mmc);
697 host->base = ioremap(r->start, resource_size(r));
703 /* only major verion does matter */
704 host->version = readl(host->base + HW_SSP_VERSION) >>
705 BP_SSP_VERSION_MAJOR;
709 host->dma_res = dmares;
711 host->sdio_irq_en = 0;
713 host->clk = clk_get(&pdev->dev, NULL);
714 if (IS_ERR(host->clk)) {
715 ret = PTR_ERR(host->clk);
718 clk_enable(host->clk);
723 dma_cap_set(DMA_SLAVE, mask);
724 host->dma_data.chan_irq = irq_dma;
725 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
727 dev_err(mmc_dev(host->mmc),
728 "%s: failed to request dma\n", __func__);
732 /* set mmc core parameters */
733 mmc->ops = &mxs_mmc_ops;
734 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
735 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
737 pdata = mmc_dev(host->mmc)->platform_data;
739 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
740 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
741 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
742 mmc->caps |= MMC_CAP_4_BIT_DATA;
746 mmc->f_max = 288000000;
747 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
750 mmc->max_blk_size = 1 << 0xf;
751 mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff;
752 mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff;
753 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
755 platform_set_drvdata(pdev, mmc);
757 spin_lock_init(&host->lock);
759 ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host);
763 ret = mmc_add_host(mmc);
767 dev_info(mmc_dev(host->mmc), "initialized\n");
772 free_irq(host->irq, host);
775 dma_release_channel(host->dmach);
777 clk_disable(host->clk);
784 release_mem_region(iores->start, resource_size(iores));
788 static int mxs_mmc_remove(struct platform_device *pdev)
790 struct mmc_host *mmc = platform_get_drvdata(pdev);
791 struct mxs_mmc_host *host = mmc_priv(mmc);
792 struct resource *res = host->res;
794 mmc_remove_host(mmc);
796 free_irq(host->irq, host);
798 platform_set_drvdata(pdev, NULL);
801 dma_release_channel(host->dmach);
803 clk_disable(host->clk);
810 release_mem_region(res->start, resource_size(res));
816 static int mxs_mmc_suspend(struct device *dev)
818 struct mmc_host *mmc = dev_get_drvdata(dev);
819 struct mxs_mmc_host *host = mmc_priv(mmc);
822 ret = mmc_suspend_host(mmc);
824 clk_disable(host->clk);
829 static int mxs_mmc_resume(struct device *dev)
831 struct mmc_host *mmc = dev_get_drvdata(dev);
832 struct mxs_mmc_host *host = mmc_priv(mmc);
835 clk_enable(host->clk);
837 ret = mmc_resume_host(mmc);
842 static const struct dev_pm_ops mxs_mmc_pm_ops = {
843 .suspend = mxs_mmc_suspend,
844 .resume = mxs_mmc_resume,
848 static struct platform_driver mxs_mmc_driver = {
849 .probe = mxs_mmc_probe,
850 .remove = mxs_mmc_remove,
853 .owner = THIS_MODULE,
855 .pm = &mxs_mmc_pm_ops,
860 static int __init mxs_mmc_init(void)
862 return platform_driver_register(&mxs_mmc_driver);
865 static void __exit mxs_mmc_exit(void)
867 platform_driver_unregister(&mxs_mmc_driver);
870 module_init(mxs_mmc_init);
871 module_exit(mxs_mmc_exit);
873 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
874 MODULE_AUTHOR("Freescale Semiconductor");
875 MODULE_LICENSE("GPL");