2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/highmem.h>
21 #include <linux/log2.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/card.h>
24 #include <linux/amba/bus.h>
25 #include <linux/clk.h>
26 #include <linux/scatterlist.h>
27 #include <linux/gpio.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/amba/mmci.h>
33 #include <asm/div64.h>
35 #include <asm/sizes.h>
39 #define DRIVER_NAME "mmci-pl18x"
41 static unsigned int fmax = 515633;
44 * struct variant_data - MMCI variant-specific quirks
45 * @clkreg: default value for MCICLOCK register
46 * @clkreg_enable: enable value for MMCICLOCK register
47 * @datalength_bits: number of bits in the MMCIDATALENGTH register
48 * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
49 * is asserted (likewise for RX)
50 * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
51 * is asserted (likewise for RX)
52 * @sdio: variant supports SDIO
53 * @st_clkdiv: true if using a ST-specific clock divider algorithm
57 unsigned int clkreg_enable;
58 unsigned int datalength_bits;
59 unsigned int fifosize;
60 unsigned int fifohalfsize;
65 static struct variant_data variant_arm = {
67 .fifohalfsize = 8 * 4,
68 .datalength_bits = 16,
71 static struct variant_data variant_arm_extended_fifo = {
73 .fifohalfsize = 64 * 4,
74 .datalength_bits = 16,
77 static struct variant_data variant_u300 = {
79 .fifohalfsize = 8 * 4,
80 .clkreg_enable = MCI_ST_U300_HWFCEN,
81 .datalength_bits = 16,
85 static struct variant_data variant_ux500 = {
87 .fifohalfsize = 8 * 4,
88 .clkreg = MCI_CLK_ENABLE,
89 .clkreg_enable = MCI_ST_UX500_HWFCEN,
90 .datalength_bits = 24,
96 * This must be called with host->lock held
98 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
100 struct variant_data *variant = host->variant;
101 u32 clk = variant->clkreg;
104 if (desired >= host->mclk) {
105 clk = MCI_CLK_BYPASS;
106 if (variant->st_clkdiv)
107 clk |= MCI_ST_UX500_NEG_EDGE;
108 host->cclk = host->mclk;
109 } else if (variant->st_clkdiv) {
111 * DB8500 TRM says f = mclk / (clkdiv + 2)
112 * => clkdiv = (mclk / f) - 2
113 * Round the divider up so we don't exceed the max
116 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
119 host->cclk = host->mclk / (clk + 2);
122 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
123 * => clkdiv = mclk / (2 * f) - 1
125 clk = host->mclk / (2 * desired) - 1;
128 host->cclk = host->mclk / (2 * (clk + 1));
131 clk |= variant->clkreg_enable;
132 clk |= MCI_CLK_ENABLE;
133 /* This hasn't proven to be worthwhile */
134 /* clk |= MCI_CLK_PWRSAVE; */
137 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
139 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
140 clk |= MCI_ST_8BIT_BUS;
142 writel(clk, host->base + MMCICLOCK);
146 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
148 writel(0, host->base + MMCICOMMAND);
156 * Need to drop the host lock here; mmc_request_done may call
157 * back into the driver...
159 spin_unlock(&host->lock);
160 mmc_request_done(host->mmc, mrq);
161 spin_lock(&host->lock);
164 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
166 void __iomem *base = host->base;
168 if (host->singleirq) {
169 unsigned int mask0 = readl(base + MMCIMASK0);
171 mask0 &= ~MCI_IRQ1MASK;
174 writel(mask0, base + MMCIMASK0);
177 writel(mask, base + MMCIMASK1);
180 static void mmci_stop_data(struct mmci_host *host)
182 writel(0, host->base + MMCIDATACTRL);
183 mmci_set_mask1(host, 0);
187 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
189 unsigned int flags = SG_MITER_ATOMIC;
191 if (data->flags & MMC_DATA_READ)
192 flags |= SG_MITER_TO_SG;
194 flags |= SG_MITER_FROM_SG;
196 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
200 * All the DMA operation mode stuff goes inside this ifdef.
201 * This assumes that you have a generic DMA device interface,
202 * no custom DMA interfaces are supported.
204 #ifdef CONFIG_DMA_ENGINE
205 static void __devinit mmci_dma_setup(struct mmci_host *host)
207 struct mmci_platform_data *plat = host->plat;
208 const char *rxname, *txname;
211 if (!plat || !plat->dma_filter) {
212 dev_info(mmc_dev(host->mmc), "no DMA platform data\n");
216 /* Try to acquire a generic DMA engine slave channel */
218 dma_cap_set(DMA_SLAVE, mask);
221 * If only an RX channel is specified, the driver will
222 * attempt to use it bidirectionally, however if it is
223 * is specified but cannot be located, DMA will be disabled.
225 if (plat->dma_rx_param) {
226 host->dma_rx_channel = dma_request_channel(mask,
229 /* E.g if no DMA hardware is present */
230 if (!host->dma_rx_channel)
231 dev_err(mmc_dev(host->mmc), "no RX DMA channel\n");
234 if (plat->dma_tx_param) {
235 host->dma_tx_channel = dma_request_channel(mask,
238 if (!host->dma_tx_channel)
239 dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n");
241 host->dma_tx_channel = host->dma_rx_channel;
244 if (host->dma_rx_channel)
245 rxname = dma_chan_name(host->dma_rx_channel);
249 if (host->dma_tx_channel)
250 txname = dma_chan_name(host->dma_tx_channel);
254 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
258 * Limit the maximum segment size in any SG entry according to
259 * the parameters of the DMA engine device.
261 if (host->dma_tx_channel) {
262 struct device *dev = host->dma_tx_channel->device->dev;
263 unsigned int max_seg_size = dma_get_max_seg_size(dev);
265 if (max_seg_size < host->mmc->max_seg_size)
266 host->mmc->max_seg_size = max_seg_size;
268 if (host->dma_rx_channel) {
269 struct device *dev = host->dma_rx_channel->device->dev;
270 unsigned int max_seg_size = dma_get_max_seg_size(dev);
272 if (max_seg_size < host->mmc->max_seg_size)
273 host->mmc->max_seg_size = max_seg_size;
278 * This is used in __devinit or __devexit so inline it
279 * so it can be discarded.
281 static inline void mmci_dma_release(struct mmci_host *host)
283 struct mmci_platform_data *plat = host->plat;
285 if (host->dma_rx_channel)
286 dma_release_channel(host->dma_rx_channel);
287 if (host->dma_tx_channel && plat->dma_tx_param)
288 dma_release_channel(host->dma_tx_channel);
289 host->dma_rx_channel = host->dma_tx_channel = NULL;
292 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
294 struct dma_chan *chan = host->dma_current;
295 enum dma_data_direction dir;
299 /* Wait up to 1ms for the DMA to complete */
301 status = readl(host->base + MMCISTATUS);
302 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
308 * Check to see whether we still have some data left in the FIFO -
309 * this catches DMA controllers which are unable to monitor the
310 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
311 * contiguous buffers. On TX, we'll get a FIFO underrun error.
313 if (status & MCI_RXDATAAVLBLMASK) {
314 dmaengine_terminate_all(chan);
319 if (data->flags & MMC_DATA_WRITE) {
322 dir = DMA_FROM_DEVICE;
325 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
328 * Use of DMA with scatter-gather is impossible.
329 * Give up with DMA and switch back to PIO mode.
331 if (status & MCI_RXDATAAVLBLMASK) {
332 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
333 mmci_dma_release(host);
337 static void mmci_dma_data_error(struct mmci_host *host)
339 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
340 dmaengine_terminate_all(host->dma_current);
343 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
345 struct variant_data *variant = host->variant;
346 struct dma_slave_config conf = {
347 .src_addr = host->phybase + MMCIFIFO,
348 .dst_addr = host->phybase + MMCIFIFO,
349 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
350 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
351 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
352 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
354 struct mmc_data *data = host->data;
355 struct dma_chan *chan;
356 struct dma_device *device;
357 struct dma_async_tx_descriptor *desc;
360 host->dma_current = NULL;
362 if (data->flags & MMC_DATA_READ) {
363 conf.direction = DMA_FROM_DEVICE;
364 chan = host->dma_rx_channel;
366 conf.direction = DMA_TO_DEVICE;
367 chan = host->dma_tx_channel;
370 /* If there's no DMA channel, fall back to PIO */
374 /* If less than or equal to the fifo size, don't bother with DMA */
375 if (host->size <= variant->fifosize)
378 device = chan->device;
379 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, conf.direction);
383 dmaengine_slave_config(chan, &conf);
384 desc = device->device_prep_slave_sg(chan, data->sg, nr_sg,
385 conf.direction, DMA_CTRL_ACK);
389 /* Okay, go for it. */
390 host->dma_current = chan;
392 dev_vdbg(mmc_dev(host->mmc),
393 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
394 data->sg_len, data->blksz, data->blocks, data->flags);
395 dmaengine_submit(desc);
396 dma_async_issue_pending(chan);
398 datactrl |= MCI_DPSM_DMAENABLE;
400 /* Trigger the DMA transfer */
401 writel(datactrl, host->base + MMCIDATACTRL);
404 * Let the MMCI say when the data is ended and it's time
405 * to fire next DMA request. When that happens, MMCI will
406 * call mmci_data_end()
408 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
409 host->base + MMCIMASK0);
413 dmaengine_terminate_all(chan);
414 dma_unmap_sg(device->dev, data->sg, data->sg_len, conf.direction);
418 /* Blank functions if the DMA engine is not available */
419 static inline void mmci_dma_setup(struct mmci_host *host)
423 static inline void mmci_dma_release(struct mmci_host *host)
427 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
431 static inline void mmci_dma_data_error(struct mmci_host *host)
435 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
441 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
443 struct variant_data *variant = host->variant;
444 unsigned int datactrl, timeout, irqmask;
445 unsigned long long clks;
449 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
450 data->blksz, data->blocks, data->flags);
453 host->size = data->blksz * data->blocks;
454 data->bytes_xfered = 0;
456 clks = (unsigned long long)data->timeout_ns * host->cclk;
457 do_div(clks, 1000000000UL);
459 timeout = data->timeout_clks + (unsigned int)clks;
462 writel(timeout, base + MMCIDATATIMER);
463 writel(host->size, base + MMCIDATALENGTH);
465 blksz_bits = ffs(data->blksz) - 1;
466 BUG_ON(1 << blksz_bits != data->blksz);
468 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
470 if (data->flags & MMC_DATA_READ)
471 datactrl |= MCI_DPSM_DIRECTION;
474 * Attempt to use DMA operation mode, if this
475 * should fail, fall back to PIO mode
477 if (!mmci_dma_start_data(host, datactrl))
480 /* IRQ mode, map the SG list for CPU reading/writing */
481 mmci_init_sg(host, data);
483 if (data->flags & MMC_DATA_READ) {
484 irqmask = MCI_RXFIFOHALFFULLMASK;
487 * If we have less than the fifo 'half-full' threshold to
488 * transfer, trigger a PIO interrupt as soon as any data
491 if (host->size < variant->fifohalfsize)
492 irqmask |= MCI_RXDATAAVLBLMASK;
495 * We don't actually need to include "FIFO empty" here
496 * since its implicit in "FIFO half empty".
498 irqmask = MCI_TXFIFOHALFEMPTYMASK;
501 /* The ST Micro variants has a special bit to enable SDIO */
502 if (variant->sdio && host->mmc->card)
503 if (mmc_card_sdio(host->mmc->card))
504 datactrl |= MCI_ST_DPSM_SDIOEN;
506 writel(datactrl, base + MMCIDATACTRL);
507 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
508 mmci_set_mask1(host, irqmask);
512 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
514 void __iomem *base = host->base;
516 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
517 cmd->opcode, cmd->arg, cmd->flags);
519 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
520 writel(0, base + MMCICOMMAND);
524 c |= cmd->opcode | MCI_CPSM_ENABLE;
525 if (cmd->flags & MMC_RSP_PRESENT) {
526 if (cmd->flags & MMC_RSP_136)
527 c |= MCI_CPSM_LONGRSP;
528 c |= MCI_CPSM_RESPONSE;
531 c |= MCI_CPSM_INTERRUPT;
535 writel(cmd->arg, base + MMCIARGUMENT);
536 writel(c, base + MMCICOMMAND);
540 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
543 /* First check for errors */
544 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
547 /* Terminate the DMA transfer */
548 if (dma_inprogress(host))
549 mmci_dma_data_error(host);
552 * Calculate how far we are into the transfer. Note that
553 * the data counter gives the number of bytes transferred
554 * on the MMC bus, not on the host side. On reads, this
555 * can be as much as a FIFO-worth of data ahead. This
556 * matters for FIFO overruns only.
558 remain = readl(host->base + MMCIDATACNT);
559 success = data->blksz * data->blocks - remain;
561 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
563 if (status & MCI_DATACRCFAIL) {
564 /* Last block was not successful */
566 data->error = -EILSEQ;
567 } else if (status & MCI_DATATIMEOUT) {
568 data->error = -ETIMEDOUT;
569 } else if (status & MCI_TXUNDERRUN) {
571 } else if (status & MCI_RXOVERRUN) {
572 if (success > host->variant->fifosize)
573 success -= host->variant->fifosize;
578 data->bytes_xfered = round_down(success, data->blksz);
581 if (status & MCI_DATABLOCKEND)
582 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
584 if (status & MCI_DATAEND || data->error) {
585 if (dma_inprogress(host))
586 mmci_dma_unmap(host, data);
587 mmci_stop_data(host);
590 /* The error clause is handled above, success! */
591 data->bytes_xfered = data->blksz * data->blocks;
594 mmci_request_end(host, data->mrq);
596 mmci_start_command(host, data->stop, 0);
602 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
605 void __iomem *base = host->base;
609 if (status & MCI_CMDTIMEOUT) {
610 cmd->error = -ETIMEDOUT;
611 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
612 cmd->error = -EILSEQ;
614 cmd->resp[0] = readl(base + MMCIRESPONSE0);
615 cmd->resp[1] = readl(base + MMCIRESPONSE1);
616 cmd->resp[2] = readl(base + MMCIRESPONSE2);
617 cmd->resp[3] = readl(base + MMCIRESPONSE3);
620 if (!cmd->data || cmd->error) {
622 mmci_stop_data(host);
623 mmci_request_end(host, cmd->mrq);
624 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
625 mmci_start_data(host, cmd->data);
629 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
631 void __iomem *base = host->base;
634 int host_remain = host->size;
637 int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
645 readsl(base + MMCIFIFO, ptr, count >> 2);
649 host_remain -= count;
654 status = readl(base + MMCISTATUS);
655 } while (status & MCI_RXDATAAVLBL);
660 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
662 struct variant_data *variant = host->variant;
663 void __iomem *base = host->base;
667 unsigned int count, maxcnt;
669 maxcnt = status & MCI_TXFIFOEMPTY ?
670 variant->fifosize : variant->fifohalfsize;
671 count = min(remain, maxcnt);
674 * The ST Micro variant for SDIO transfer sizes
675 * less then 8 bytes should have clock H/W flow
679 mmc_card_sdio(host->mmc->card)) {
681 writel(readl(host->base + MMCICLOCK) &
682 ~variant->clkreg_enable,
683 host->base + MMCICLOCK);
685 writel(readl(host->base + MMCICLOCK) |
686 variant->clkreg_enable,
687 host->base + MMCICLOCK);
691 * SDIO especially may want to send something that is
692 * not divisible by 4 (as opposed to card sectors
693 * etc), and the FIFO only accept full 32-bit writes.
694 * So compensate by adding +3 on the count, a single
695 * byte become a 32bit write, 7 bytes will be two
698 writesl(base + MMCIFIFO, ptr, (count + 3) >> 2);
706 status = readl(base + MMCISTATUS);
707 } while (status & MCI_TXFIFOHALFEMPTY);
713 * PIO data transfer IRQ handler.
715 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
717 struct mmci_host *host = dev_id;
718 struct sg_mapping_iter *sg_miter = &host->sg_miter;
719 struct variant_data *variant = host->variant;
720 void __iomem *base = host->base;
724 status = readl(base + MMCISTATUS);
726 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
728 local_irq_save(flags);
731 unsigned int remain, len;
735 * For write, we only need to test the half-empty flag
736 * here - if the FIFO is completely empty, then by
737 * definition it is more than half empty.
739 * For read, check for data available.
741 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
744 if (!sg_miter_next(sg_miter))
747 buffer = sg_miter->addr;
748 remain = sg_miter->length;
751 if (status & MCI_RXACTIVE)
752 len = mmci_pio_read(host, buffer, remain);
753 if (status & MCI_TXACTIVE)
754 len = mmci_pio_write(host, buffer, remain, status);
756 sg_miter->consumed = len;
764 status = readl(base + MMCISTATUS);
767 sg_miter_stop(sg_miter);
769 local_irq_restore(flags);
772 * If we have less than the fifo 'half-full' threshold to transfer,
773 * trigger a PIO interrupt as soon as any data is available.
775 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
776 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
779 * If we run out of data, disable the data IRQs; this
780 * prevents a race where the FIFO becomes empty before
781 * the chip itself has disabled the data path, and
782 * stops us racing with our data end IRQ.
784 if (host->size == 0) {
785 mmci_set_mask1(host, 0);
786 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
793 * Handle completion of command and data transfers.
795 static irqreturn_t mmci_irq(int irq, void *dev_id)
797 struct mmci_host *host = dev_id;
801 spin_lock(&host->lock);
804 struct mmc_command *cmd;
805 struct mmc_data *data;
807 status = readl(host->base + MMCISTATUS);
809 if (host->singleirq) {
810 if (status & readl(host->base + MMCIMASK1))
811 mmci_pio_irq(irq, dev_id);
813 status &= ~MCI_IRQ1MASK;
816 status &= readl(host->base + MMCIMASK0);
817 writel(status, host->base + MMCICLEAR);
819 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
822 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
823 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
824 mmci_data_irq(host, data, status);
827 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
828 mmci_cmd_irq(host, cmd, status);
833 spin_unlock(&host->lock);
835 return IRQ_RETVAL(ret);
838 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
840 struct mmci_host *host = mmc_priv(mmc);
843 WARN_ON(host->mrq != NULL);
845 if (mrq->data && !is_power_of_2(mrq->data->blksz)) {
846 dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n",
848 mrq->cmd->error = -EINVAL;
849 mmc_request_done(mmc, mrq);
853 spin_lock_irqsave(&host->lock, flags);
857 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
858 mmci_start_data(host, mrq->data);
860 mmci_start_command(host, mrq->cmd, 0);
862 spin_unlock_irqrestore(&host->lock, flags);
865 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
867 struct mmci_host *host = mmc_priv(mmc);
872 switch (ios->power_mode) {
875 ret = mmc_regulator_set_ocr(mmc, host->vcc, 0);
879 ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd);
881 dev_err(mmc_dev(mmc), "unable to set OCR\n");
883 * The .set_ios() function in the mmc_host_ops
884 * struct return void, and failing to set the
885 * power should be rare so we print an error
891 if (host->plat->vdd_handler)
892 pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd,
894 /* The ST version does not have this, fall through to POWER_ON */
895 if (host->hw_designer != AMBA_VENDOR_ST) {
904 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
905 if (host->hw_designer != AMBA_VENDOR_ST)
909 * The ST Micro variant use the ROD bit for something
910 * else and only has OD (Open Drain).
916 spin_lock_irqsave(&host->lock, flags);
918 mmci_set_clkreg(host, ios->clock);
920 if (host->pwr != pwr) {
922 writel(pwr, host->base + MMCIPOWER);
925 spin_unlock_irqrestore(&host->lock, flags);
928 static int mmci_get_ro(struct mmc_host *mmc)
930 struct mmci_host *host = mmc_priv(mmc);
932 if (host->gpio_wp == -ENOSYS)
935 return gpio_get_value_cansleep(host->gpio_wp);
938 static int mmci_get_cd(struct mmc_host *mmc)
940 struct mmci_host *host = mmc_priv(mmc);
941 struct mmci_platform_data *plat = host->plat;
944 if (host->gpio_cd == -ENOSYS) {
946 return 1; /* Assume always present */
948 status = plat->status(mmc_dev(host->mmc));
950 status = !!gpio_get_value_cansleep(host->gpio_cd)
954 * Use positive logic throughout - status is zero for no card,
955 * non-zero for card inserted.
960 static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
962 struct mmci_host *host = dev_id;
964 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
969 static const struct mmc_host_ops mmci_ops = {
970 .request = mmci_request,
971 .set_ios = mmci_set_ios,
972 .get_ro = mmci_get_ro,
973 .get_cd = mmci_get_cd,
976 static int __devinit mmci_probe(struct amba_device *dev,
977 const struct amba_id *id)
979 struct mmci_platform_data *plat = dev->dev.platform_data;
980 struct variant_data *variant = id->data;
981 struct mmci_host *host;
982 struct mmc_host *mmc;
985 /* must have platform data */
991 ret = amba_request_regions(dev, DRIVER_NAME);
995 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1001 host = mmc_priv(mmc);
1004 host->gpio_wp = -ENOSYS;
1005 host->gpio_cd = -ENOSYS;
1006 host->gpio_cd_irq = -1;
1008 host->hw_designer = amba_manf(dev);
1009 host->hw_revision = amba_rev(dev);
1010 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1011 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1013 host->clk = clk_get(&dev->dev, NULL);
1014 if (IS_ERR(host->clk)) {
1015 ret = PTR_ERR(host->clk);
1020 ret = clk_enable(host->clk);
1025 host->variant = variant;
1026 host->mclk = clk_get_rate(host->clk);
1028 * According to the spec, mclk is max 100 MHz,
1029 * so we try to adjust the clock down to this,
1032 if (host->mclk > 100000000) {
1033 ret = clk_set_rate(host->clk, 100000000);
1036 host->mclk = clk_get_rate(host->clk);
1037 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1040 host->phybase = dev->res.start;
1041 host->base = ioremap(dev->res.start, resource_size(&dev->res));
1047 mmc->ops = &mmci_ops;
1048 mmc->f_min = (host->mclk + 511) / 512;
1050 * If the platform data supplies a maximum operating
1051 * frequency, this takes precedence. Else, we fall back
1052 * to using the module parameter, which has a (low)
1053 * default value in case it is not specified. Either
1054 * value must not exceed the clock rate into the block,
1058 mmc->f_max = min(host->mclk, plat->f_max);
1060 mmc->f_max = min(host->mclk, fmax);
1061 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1063 #ifdef CONFIG_REGULATOR
1064 /* If we're using the regulator framework, try to fetch a regulator */
1065 host->vcc = regulator_get(&dev->dev, "vmmc");
1066 if (IS_ERR(host->vcc))
1069 int mask = mmc_regulator_get_ocrmask(host->vcc);
1072 dev_err(&dev->dev, "error getting OCR mask (%d)\n",
1075 host->mmc->ocr_avail = (u32) mask;
1078 "Provided ocr_mask/setpower will not be used "
1079 "(using regulator instead)\n");
1083 /* Fall back to platform data if no regulator is found */
1084 if (host->vcc == NULL)
1085 mmc->ocr_avail = plat->ocr_mask;
1086 mmc->caps = plat->capabilities;
1091 mmc->max_segs = NR_SG;
1094 * Since only a certain number of bits are valid in the data length
1095 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1098 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1101 * Set the maximum segment size. Since we aren't doing DMA
1102 * (yet) we are only limited by the data length register.
1104 mmc->max_seg_size = mmc->max_req_size;
1107 * Block size can be up to 2048 bytes, but must be a power of two.
1109 mmc->max_blk_size = 2048;
1112 * No limit on the number of blocks transferred.
1114 mmc->max_blk_count = mmc->max_req_size;
1116 spin_lock_init(&host->lock);
1118 writel(0, host->base + MMCIMASK0);
1119 writel(0, host->base + MMCIMASK1);
1120 writel(0xfff, host->base + MMCICLEAR);
1122 if (gpio_is_valid(plat->gpio_cd)) {
1123 ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)");
1125 ret = gpio_direction_input(plat->gpio_cd);
1127 host->gpio_cd = plat->gpio_cd;
1128 else if (ret != -ENOSYS)
1131 ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
1133 DRIVER_NAME " (cd)", host);
1135 host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
1137 if (gpio_is_valid(plat->gpio_wp)) {
1138 ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
1140 ret = gpio_direction_input(plat->gpio_wp);
1142 host->gpio_wp = plat->gpio_wp;
1143 else if (ret != -ENOSYS)
1147 if ((host->plat->status || host->gpio_cd != -ENOSYS)
1148 && host->gpio_cd_irq < 0)
1149 mmc->caps |= MMC_CAP_NEEDS_POLL;
1151 ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
1155 if (dev->irq[1] == NO_IRQ)
1156 host->singleirq = true;
1158 ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
1159 DRIVER_NAME " (pio)", host);
1164 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1166 amba_set_drvdata(dev, mmc);
1168 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1169 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1170 amba_rev(dev), (unsigned long long)dev->res.start,
1171 dev->irq[0], dev->irq[1]);
1173 mmci_dma_setup(host);
1180 free_irq(dev->irq[0], host);
1182 if (host->gpio_wp != -ENOSYS)
1183 gpio_free(host->gpio_wp);
1185 if (host->gpio_cd_irq >= 0)
1186 free_irq(host->gpio_cd_irq, host);
1187 if (host->gpio_cd != -ENOSYS)
1188 gpio_free(host->gpio_cd);
1190 iounmap(host->base);
1192 clk_disable(host->clk);
1198 amba_release_regions(dev);
1203 static int __devexit mmci_remove(struct amba_device *dev)
1205 struct mmc_host *mmc = amba_get_drvdata(dev);
1207 amba_set_drvdata(dev, NULL);
1210 struct mmci_host *host = mmc_priv(mmc);
1212 mmc_remove_host(mmc);
1214 writel(0, host->base + MMCIMASK0);
1215 writel(0, host->base + MMCIMASK1);
1217 writel(0, host->base + MMCICOMMAND);
1218 writel(0, host->base + MMCIDATACTRL);
1220 mmci_dma_release(host);
1221 free_irq(dev->irq[0], host);
1222 if (!host->singleirq)
1223 free_irq(dev->irq[1], host);
1225 if (host->gpio_wp != -ENOSYS)
1226 gpio_free(host->gpio_wp);
1227 if (host->gpio_cd_irq >= 0)
1228 free_irq(host->gpio_cd_irq, host);
1229 if (host->gpio_cd != -ENOSYS)
1230 gpio_free(host->gpio_cd);
1232 iounmap(host->base);
1233 clk_disable(host->clk);
1237 mmc_regulator_set_ocr(mmc, host->vcc, 0);
1238 regulator_put(host->vcc);
1242 amba_release_regions(dev);
1249 static int mmci_suspend(struct amba_device *dev, pm_message_t state)
1251 struct mmc_host *mmc = amba_get_drvdata(dev);
1255 struct mmci_host *host = mmc_priv(mmc);
1257 ret = mmc_suspend_host(mmc);
1259 writel(0, host->base + MMCIMASK0);
1265 static int mmci_resume(struct amba_device *dev)
1267 struct mmc_host *mmc = amba_get_drvdata(dev);
1271 struct mmci_host *host = mmc_priv(mmc);
1273 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1275 ret = mmc_resume_host(mmc);
1281 #define mmci_suspend NULL
1282 #define mmci_resume NULL
1285 static struct amba_id mmci_ids[] = {
1289 .data = &variant_arm,
1294 .data = &variant_arm_extended_fifo,
1299 .data = &variant_arm,
1301 /* ST Micro variants */
1305 .data = &variant_u300,
1310 .data = &variant_u300,
1315 .data = &variant_ux500,
1320 static struct amba_driver mmci_driver = {
1322 .name = DRIVER_NAME,
1324 .probe = mmci_probe,
1325 .remove = __devexit_p(mmci_remove),
1326 .suspend = mmci_suspend,
1327 .resume = mmci_resume,
1328 .id_table = mmci_ids,
1331 static int __init mmci_init(void)
1333 return amba_driver_register(&mmci_driver);
1336 static void __exit mmci_exit(void)
1338 amba_driver_unregister(&mmci_driver);
1341 module_init(mmci_init);
1342 module_exit(mmci_exit);
1343 module_param(fmax, uint, 0444);
1345 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
1346 MODULE_LICENSE("GPL");