2 * linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
4 * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
7 * derived from pxamci.c by Russell King
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/ioport.h>
18 #include <linux/platform_device.h>
19 #include <linux/interrupt.h>
20 #include <linux/blkdev.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/card.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
30 #include <asm/sizes.h>
32 #include <mach/imx-dma.h>
36 #define DRIVER_NAME "imx-mmc"
38 #define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
39 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
40 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
48 volatile unsigned int imask;
49 unsigned int power_mode;
51 struct imxmmc_platform_data *pdata;
53 struct mmc_request *req;
54 struct mmc_command *cmd;
55 struct mmc_data *data;
57 struct timer_list timer;
58 struct tasklet_struct tasklet;
59 unsigned int status_reg;
60 unsigned long pending_events;
61 /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
63 unsigned int data_cnt;
64 atomic_t stuck_timeout;
66 unsigned int dma_nents;
67 unsigned int dma_size;
71 unsigned char actual_bus_width;
78 #define IMXMCI_PEND_IRQ_b 0
79 #define IMXMCI_PEND_DMA_END_b 1
80 #define IMXMCI_PEND_DMA_ERR_b 2
81 #define IMXMCI_PEND_WAIT_RESP_b 3
82 #define IMXMCI_PEND_DMA_DATA_b 4
83 #define IMXMCI_PEND_CPU_DATA_b 5
84 #define IMXMCI_PEND_CARD_XCHG_b 6
85 #define IMXMCI_PEND_SET_INIT_b 7
86 #define IMXMCI_PEND_STARTED_b 8
88 #define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b)
89 #define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b)
90 #define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b)
91 #define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
92 #define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b)
93 #define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b)
94 #define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
95 #define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b)
96 #define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b)
98 static void imxmci_stop_clock(struct imxmci_host *host)
101 MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
104 MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
106 if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
107 /* Check twice before cut */
108 if (!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
114 dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
117 static int imxmci_start_clock(struct imxmci_host *host)
119 unsigned int trials = 0;
120 unsigned int delay_limit = 128;
123 MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
125 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
128 * Command start of the clock, this usually succeeds in less
129 * then 6 delay loops, but during card detection (low clockrate)
130 * it takes up to 5000 delay loops and sometimes fails for the first time
132 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
135 unsigned int delay = delay_limit;
138 if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
139 /* Check twice before cut */
140 if (MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
143 if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
147 local_irq_save(flags);
149 * Ensure, that request is not doubled under all possible circumstances.
150 * It is possible, that cock running state is missed, because some other
151 * IRQ or schedule delays this function execution and the clocks has
152 * been already stopped by other means (response processing, SDHC HW)
154 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
155 MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
156 local_irq_restore(flags);
158 } while (++trials < 256);
160 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
165 static void imxmci_softreset(void)
168 MMC_STR_STP_CLK = 0x8;
169 MMC_STR_STP_CLK = 0xD;
170 MMC_STR_STP_CLK = 0x5;
171 MMC_STR_STP_CLK = 0x5;
172 MMC_STR_STP_CLK = 0x5;
173 MMC_STR_STP_CLK = 0x5;
174 MMC_STR_STP_CLK = 0x5;
175 MMC_STR_STP_CLK = 0x5;
176 MMC_STR_STP_CLK = 0x5;
177 MMC_STR_STP_CLK = 0x5;
184 static int imxmci_busy_wait_for_status(struct imxmci_host *host,
185 unsigned int *pstat, unsigned int stat_mask,
186 int timeout, const char *where)
190 while (!(*pstat & stat_mask)) {
192 if (loops >= timeout) {
193 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
194 where, *pstat, stat_mask);
198 *pstat |= MMC_STATUS;
203 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
204 if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
205 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
206 loops, where, *pstat, stat_mask);
210 static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
212 unsigned int nob = data->blocks;
213 unsigned int blksz = data->blksz;
214 unsigned int datasz = nob * blksz;
217 if (data->flags & MMC_DATA_STREAM)
221 data->bytes_xfered = 0;
227 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
228 * We are in big troubles for non-512 byte transfers according to note in the paragraph
229 * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
230 * The situation is even more complex in reality. The SDHC in not able to handle wll
231 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
232 * This is required for SCR read at least.
235 host->dma_size = datasz;
236 if (data->flags & MMC_DATA_READ) {
237 host->dma_dir = DMA_FROM_DEVICE;
239 /* Hack to enable read SCR */
243 host->dma_dir = DMA_TO_DEVICE;
246 /* Convert back to virtual address */
247 host->data_ptr = (u16 *)sg_virt(data->sg);
250 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
251 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
256 if (data->flags & MMC_DATA_READ) {
257 host->dma_dir = DMA_FROM_DEVICE;
258 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
259 data->sg_len, host->dma_dir);
261 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
262 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
264 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
265 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
267 host->dma_dir = DMA_TO_DEVICE;
269 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
270 data->sg_len, host->dma_dir);
272 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
273 host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
275 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
276 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
279 #if 1 /* This code is there only for consistency checking and can be disabled in future */
281 for (i = 0; i < host->dma_nents; i++)
282 host->dma_size += data->sg[i].length;
284 if (datasz > host->dma_size) {
285 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
286 datasz, host->dma_size);
290 host->dma_size = datasz;
294 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
295 BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
297 BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
299 RSSR(host->dma) = DMA_REQ_SDHC;
301 set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
302 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
304 /* start DMA engine for read, write is delayed after initial response */
305 if (host->dma_dir == DMA_FROM_DEVICE)
306 imx_dma_enable(host->dma);
309 static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
314 WARN_ON(host->cmd != NULL);
317 /* Ensure, that clock are stopped else command programming and start fails */
318 imxmci_stop_clock(host);
320 if (cmd->flags & MMC_RSP_BUSY)
321 cmdat |= CMD_DAT_CONT_BUSY;
323 switch (mmc_resp_type(cmd)) {
324 case MMC_RSP_R1: /* short CRC, OPCODE */
325 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
326 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
328 case MMC_RSP_R2: /* long 136 bit + CRC */
329 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
331 case MMC_RSP_R3: /* short */
332 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
338 if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
339 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
341 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
342 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
344 MMC_CMD = cmd->opcode;
345 MMC_ARGH = cmd->arg >> 16;
346 MMC_ARGL = cmd->arg & 0xffff;
347 MMC_CMD_DAT_CONT = cmdat;
349 atomic_set(&host->stuck_timeout, 0);
350 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
353 imask = IMXMCI_INT_MASK_DEFAULT;
354 imask &= ~INT_MASK_END_CMD_RES;
355 if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
356 /* imask &= ~INT_MASK_BUF_READY; */
357 imask &= ~INT_MASK_DATA_TRAN;
358 if (cmdat & CMD_DAT_CONT_WRITE)
359 imask &= ~INT_MASK_WRITE_OP_DONE;
360 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
361 imask &= ~INT_MASK_BUF_READY;
364 spin_lock_irqsave(&host->lock, flags);
366 MMC_INT_MASK = host->imask;
367 spin_unlock_irqrestore(&host->lock, flags);
369 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
370 cmd->opcode, cmd->opcode, imask);
372 imxmci_start_clock(host);
375 static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
379 spin_lock_irqsave(&host->lock, flags);
381 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
382 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
384 host->imask = IMXMCI_INT_MASK_DEFAULT;
385 MMC_INT_MASK = host->imask;
387 spin_unlock_irqrestore(&host->lock, flags);
390 host->prev_cmd_code = req->cmd->opcode;
395 mmc_request_done(host->mmc, req);
398 static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
400 struct mmc_data *data = host->data;
403 if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
404 imx_dma_disable(host->dma);
405 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
409 if (stat & STATUS_ERR_MASK) {
410 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
411 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
412 data->error = -EILSEQ;
413 else if (stat & STATUS_TIME_OUT_READ)
414 data->error = -ETIMEDOUT;
418 data->bytes_xfered = host->dma_size;
421 data_error = data->error;
428 static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
430 struct mmc_command *cmd = host->cmd;
433 struct mmc_data *data = host->data;
440 if (stat & STATUS_TIME_OUT_RESP) {
441 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
442 cmd->error = -ETIMEDOUT;
443 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
444 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
445 cmd->error = -EILSEQ;
448 if (cmd->flags & MMC_RSP_PRESENT) {
449 if (cmd->flags & MMC_RSP_136) {
450 for (i = 0; i < 4; i++) {
451 u32 d = MMC_RES_FIFO & 0xffff;
452 u32 e = MMC_RES_FIFO & 0xffff;
453 cmd->resp[i] = d << 16 | e;
456 a = MMC_RES_FIFO & 0xffff;
457 b = MMC_RES_FIFO & 0xffff;
458 c = MMC_RES_FIFO & 0xffff;
459 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
463 dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
464 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
466 if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
467 if (host->req->data->flags & MMC_DATA_WRITE) {
469 /* Wait for FIFO to be empty before starting DMA write */
472 if (imxmci_busy_wait_for_status(host, &stat,
474 40, "imxmci_cmd_done DMA WR") < 0) {
476 imxmci_finish_data(host, stat);
478 imxmci_finish_request(host, host->req);
479 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
484 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
485 imx_dma_enable(host->dma);
488 struct mmc_request *req;
489 imxmci_stop_clock(host);
493 imxmci_finish_data(host, stat);
496 imxmci_finish_request(host, req);
498 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
504 static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
506 struct mmc_data *data = host->data;
512 data_error = imxmci_finish_data(host, stat);
514 if (host->req->stop) {
515 imxmci_stop_clock(host);
516 imxmci_start_cmd(host, host->req->stop, 0);
518 struct mmc_request *req;
521 imxmci_finish_request(host, req);
523 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
529 static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
534 unsigned int stat = *pstat;
536 if (host->actual_bus_width != MMC_BUS_WIDTH_4)
541 /* This is unfortunately required */
542 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
545 udelay(20); /* required for clocks < 8MHz*/
547 if (host->dma_dir == DMA_FROM_DEVICE) {
548 imxmci_busy_wait_for_status(host, &stat,
549 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
550 STATUS_TIME_OUT_READ,
551 50, "imxmci_cpu_driven_data read");
553 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
554 !(stat & STATUS_TIME_OUT_READ) &&
555 (host->data_cnt < 512)) {
557 udelay(20); /* required for clocks < 8MHz*/
559 for (i = burst_len; i >= 2 ; i -= 2) {
561 data = MMC_BUFFER_ACCESS;
562 udelay(10); /* required for clocks < 8MHz*/
563 if (host->data_cnt+2 <= host->dma_size) {
564 *(host->data_ptr++) = data;
566 if (host->data_cnt < host->dma_size)
567 *(u8 *)(host->data_ptr) = data;
574 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
575 host->data_cnt, burst_len, stat);
578 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
581 if (host->dma_size & 0x1ff)
582 stat &= ~STATUS_CRC_READ_ERR;
584 if (stat & STATUS_TIME_OUT_READ) {
585 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
591 imxmci_busy_wait_for_status(host, &stat,
593 20, "imxmci_cpu_driven_data write");
595 while ((stat & STATUS_APPL_BUFF_FE) &&
596 (host->data_cnt < host->dma_size)) {
597 if (burst_len >= host->dma_size - host->data_cnt) {
598 burst_len = host->dma_size - host->data_cnt;
599 host->data_cnt = host->dma_size;
602 host->data_cnt += burst_len;
605 for (i = burst_len; i > 0 ; i -= 2)
606 MMC_BUFFER_ACCESS = *(host->data_ptr++);
610 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
620 static void imxmci_dma_irq(int dma, void *devid)
622 struct imxmci_host *host = devid;
623 uint32_t stat = MMC_STATUS;
625 atomic_set(&host->stuck_timeout, 0);
626 host->status_reg = stat;
627 set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
628 tasklet_schedule(&host->tasklet);
631 static irqreturn_t imxmci_irq(int irq, void *devid)
633 struct imxmci_host *host = devid;
634 uint32_t stat = MMC_STATUS;
637 MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
639 atomic_set(&host->stuck_timeout, 0);
640 host->status_reg = stat;
641 set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
642 set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
643 tasklet_schedule(&host->tasklet);
645 return IRQ_RETVAL(handled);;
648 static void imxmci_tasklet_fnc(unsigned long data)
650 struct imxmci_host *host = (struct imxmci_host *)data;
652 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
655 if (atomic_read(&host->stuck_timeout) > 4) {
659 host->status_reg = stat;
660 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
661 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
666 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
667 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
674 dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
675 what, stat, MMC_INT_MASK);
676 dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
677 MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
678 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
679 host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1 << host->actual_bus_width, host->dma_size);
682 if (!host->present || timeout)
683 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
684 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
686 if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
687 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
691 * This is not required in theory, but there is chance to miss some flag
692 * which clears automatically by mask write, FreeScale original code keeps
693 * stat from IRQ time so do I
695 stat |= host->status_reg;
697 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
698 stat &= ~STATUS_CRC_READ_ERR;
700 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
701 imxmci_busy_wait_for_status(host, &stat,
702 STATUS_END_CMD_RESP | STATUS_ERR_MASK,
703 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
706 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
707 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
708 imxmci_cmd_done(host, stat);
709 if (host->data && (stat & STATUS_ERR_MASK))
710 imxmci_data_done(host, stat);
713 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
715 if (imxmci_cpu_driven_data(host, &stat)) {
716 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
717 imxmci_cmd_done(host, stat);
718 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
719 &host->pending_events);
720 imxmci_data_done(host, stat);
725 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
726 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
730 stat |= host->status_reg;
732 if (host->dma_dir == DMA_TO_DEVICE)
733 data_dir_mask = STATUS_WRITE_OP_DONE;
735 data_dir_mask = STATUS_DATA_TRANS_DONE;
737 if (stat & data_dir_mask) {
738 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
739 imxmci_data_done(host, stat);
743 if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
746 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
749 imxmci_data_done(host, STATUS_TIME_OUT_READ |
750 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
753 imxmci_finish_request(host, host->req);
755 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
760 static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
762 struct imxmci_host *host = mmc_priv(mmc);
765 WARN_ON(host->req != NULL);
772 imxmci_setup_data(host, req->data);
774 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
776 if (req->data->flags & MMC_DATA_WRITE)
777 cmdat |= CMD_DAT_CONT_WRITE;
779 if (req->data->flags & MMC_DATA_STREAM)
780 cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
783 imxmci_start_cmd(host, req->cmd, cmdat);
786 #define CLK_RATE 19200000
788 static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
790 struct imxmci_host *host = mmc_priv(mmc);
793 if (ios->bus_width == MMC_BUS_WIDTH_4) {
794 host->actual_bus_width = MMC_BUS_WIDTH_4;
795 imx_gpio_mode(PB11_PF_SD_DAT3);
797 host->actual_bus_width = MMC_BUS_WIDTH_1;
798 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
801 if (host->power_mode != ios->power_mode) {
802 switch (ios->power_mode) {
806 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
811 host->power_mode = ios->power_mode;
817 /* The prescaler is 5 for PERCLK2 equal to 96MHz
818 * then 96MHz / 5 = 19.2 MHz
820 clk = clk_get_rate(host->clk);
821 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
824 case 1: prescaler = 0;
826 case 2: prescaler = 1;
828 case 3: prescaler = 2;
830 case 4: prescaler = 4;
833 case 5: prescaler = 5;
837 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
840 for (clk = 0; clk < 8; clk++) {
842 x = CLK_RATE / (1 << clk);
847 MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
849 imxmci_stop_clock(host);
850 MMC_CLK_RATE = (prescaler << 3) | clk;
852 * Under my understanding, clock should not be started there, because it would
853 * initiate SDHC sequencer and send last or random command into card
855 /* imxmci_start_clock(host); */
857 dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
859 imxmci_stop_clock(host);
863 static int imxmci_get_ro(struct mmc_host *mmc)
865 struct imxmci_host *host = mmc_priv(mmc);
867 if (host->pdata && host->pdata->get_ro)
868 return !!host->pdata->get_ro(mmc_dev(mmc));
870 * Board doesn't support read only detection; let the mmc core
877 static const struct mmc_host_ops imxmci_ops = {
878 .request = imxmci_request,
879 .set_ios = imxmci_set_ios,
880 .get_ro = imxmci_get_ro,
883 static void imxmci_check_status(unsigned long data)
885 struct imxmci_host *host = (struct imxmci_host *)data;
887 if (host->pdata && host->pdata->card_present &&
888 host->pdata->card_present(mmc_dev(host->mmc)) != host->present) {
890 dev_info(mmc_dev(host->mmc), "card %s\n",
891 host->present ? "inserted" : "removed");
893 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
894 tasklet_schedule(&host->tasklet);
897 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
898 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
899 atomic_inc(&host->stuck_timeout);
900 if (atomic_read(&host->stuck_timeout) > 4)
901 tasklet_schedule(&host->tasklet);
903 atomic_set(&host->stuck_timeout, 0);
907 mod_timer(&host->timer, jiffies + (HZ>>1));
910 static int imxmci_probe(struct platform_device *pdev)
912 struct mmc_host *mmc;
913 struct imxmci_host *host = NULL;
917 printk(KERN_INFO "i.MX mmc driver\n");
919 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
920 irq = platform_get_irq(pdev, 0);
924 if (!request_mem_region(r->start, 0x100, pdev->name))
927 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
933 mmc->ops = &imxmci_ops;
935 mmc->f_max = CLK_RATE/2;
936 mmc->ocr_avail = MMC_VDD_32_33;
937 mmc->caps = MMC_CAP_4_BIT_DATA;
939 /* MMC core transfer sizes tunable parameters */
940 mmc->max_hw_segs = 64;
941 mmc->max_phys_segs = 64;
942 mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */
943 mmc->max_req_size = 64*512; /* default PAGE_CACHE_SIZE */
944 mmc->max_blk_size = 2048;
945 mmc->max_blk_count = 65535;
947 host = mmc_priv(mmc);
949 host->dma_allocated = 0;
950 host->pdata = pdev->dev.platform_data;
952 dev_warn(&pdev->dev, "No platform data provided!\n");
954 spin_lock_init(&host->lock);
958 host->clk = clk_get(&pdev->dev, "perclk2");
959 if (IS_ERR(host->clk)) {
960 ret = PTR_ERR(host->clk);
963 clk_enable(host->clk);
965 imx_gpio_mode(PB8_PF_SD_DAT0);
966 imx_gpio_mode(PB9_PF_SD_DAT1);
967 imx_gpio_mode(PB10_PF_SD_DAT2);
968 /* Configured as GPIO with pull-up to ensure right MCC card mode */
969 /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
970 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
971 /* imx_gpio_mode(PB11_PF_SD_DAT3); */
972 imx_gpio_mode(PB12_PF_SD_CLK);
973 imx_gpio_mode(PB13_PF_SD_CMD);
977 if (MMC_REV_NO != 0x390) {
978 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
983 MMC_READ_TO = 0x2db4; /* recommended in data sheet */
985 host->imask = IMXMCI_INT_MASK_DEFAULT;
986 MMC_INT_MASK = host->imask;
988 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
990 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
994 host->dma_allocated = 1;
995 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
997 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
999 host->pending_events=0;
1001 ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1005 if (host->pdata && host->pdata->card_present)
1006 host->present = host->pdata->card_present(mmc_dev(mmc));
1007 else /* if there is no way to detect assume that card is present */
1010 init_timer(&host->timer);
1011 host->timer.data = (unsigned long)host;
1012 host->timer.function = imxmci_check_status;
1013 add_timer(&host->timer);
1014 mod_timer(&host->timer, jiffies + (HZ >> 1));
1016 platform_set_drvdata(pdev, mmc);
1024 if (host->dma_allocated) {
1025 imx_dma_free(host->dma);
1026 host->dma_allocated = 0;
1029 clk_disable(host->clk);
1035 release_mem_region(r->start, 0x100);
1039 static int imxmci_remove(struct platform_device *pdev)
1041 struct mmc_host *mmc = platform_get_drvdata(pdev);
1043 platform_set_drvdata(pdev, NULL);
1046 struct imxmci_host *host = mmc_priv(mmc);
1048 tasklet_disable(&host->tasklet);
1050 del_timer_sync(&host->timer);
1051 mmc_remove_host(mmc);
1053 free_irq(host->irq, host);
1054 if (host->dma_allocated) {
1055 imx_dma_free(host->dma);
1056 host->dma_allocated = 0;
1059 tasklet_kill(&host->tasklet);
1061 clk_disable(host->clk);
1064 release_mem_region(host->res->start, 0x100);
1072 static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1074 struct mmc_host *mmc = platform_get_drvdata(dev);
1078 ret = mmc_suspend_host(mmc, state);
1083 static int imxmci_resume(struct platform_device *dev)
1085 struct mmc_host *mmc = platform_get_drvdata(dev);
1086 struct imxmci_host *host;
1090 host = mmc_priv(mmc);
1092 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1093 ret = mmc_resume_host(mmc);
1099 #define imxmci_suspend NULL
1100 #define imxmci_resume NULL
1101 #endif /* CONFIG_PM */
1103 static struct platform_driver imxmci_driver = {
1104 .probe = imxmci_probe,
1105 .remove = imxmci_remove,
1106 .suspend = imxmci_suspend,
1107 .resume = imxmci_resume,
1109 .name = DRIVER_NAME,
1110 .owner = THIS_MODULE,
1114 static int __init imxmci_init(void)
1116 return platform_driver_register(&imxmci_driver);
1119 static void __exit imxmci_exit(void)
1121 platform_driver_unregister(&imxmci_driver);
1124 module_init(imxmci_init);
1125 module_exit(imxmci_exit);
1127 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1128 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1129 MODULE_LICENSE("GPL");
1130 MODULE_ALIAS("platform:imx-mmc");