drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/scatterlist.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/slab.h>
  28 #include <linux/stat.h>
  29 #include <linux/delay.h>
  30 #include <linux/irq.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/dw_mmc.h>
  34 #include <linux/bitops.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/workqueue.h>
  37
  38 #include "dw_mmc.h"
  39
  40 /* Common flag combinations */
  41 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  42                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  43                                  SDMMC_INT_EBE)
  44 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  45                                  SDMMC_INT_RESP_ERR)
  46 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  47                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  48 #define DW_MCI_SEND_STATUS      1
  49 #define DW_MCI_RECV_STATUS      2
  50 #define DW_MCI_DMA_THRESHOLD    16
  51
  52 #ifdef CONFIG_MMC_DW_IDMAC
  53 struct idmac_desc {
  54         u32             des0;   /* Control Descriptor */
  55 #define IDMAC_DES0_DIC  BIT(1)
  56 #define IDMAC_DES0_LD   BIT(2)
  57 #define IDMAC_DES0_FD   BIT(3)
  58 #define IDMAC_DES0_CH   BIT(4)
  59 #define IDMAC_DES0_ER   BIT(5)
  60 #define IDMAC_DES0_CES  BIT(30)
  61 #define IDMAC_DES0_OWN  BIT(31)
  62
  63         u32             des1;   /* Buffer sizes */
  64 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  65         ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
  66
  67         u32             des2;   /* buffer 1 physical address */
  68
  69         u32             des3;   /* buffer 2 physical address */
  70 };
  71 #endif /* CONFIG_MMC_DW_IDMAC */
  72
  73 /**
  74  * struct dw_mci_slot - MMC slot state
  75  * @mmc: The mmc_host representing this slot.
  76  * @host: The MMC controller this slot is using.
  77  * @ctype: Card type for this slot.
  78  * @mrq: mmc_request currently being processed or waiting to be
  79  *      processed, or NULL when the slot is idle.
  80  * @queue_node: List node for placing this node in the @queue list of
  81  *      &struct dw_mci.
  82  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  83  * @flags: Random state bits associated with the slot.
  84  * @id: Number of this slot.
  85  * @last_detect_state: Most recently observed card detect state.
  86  */
  87 struct dw_mci_slot {
  88         struct mmc_host         *mmc;
  89         struct dw_mci           *host;
  90
  91         u32                     ctype;
  92
  93         struct mmc_request      *mrq;
  94         struct list_head        queue_node;
  95
  96         unsigned int            clock;
  97         unsigned long           flags;
  98 #define DW_MMC_CARD_PRESENT     0
  99 #define DW_MMC_CARD_NEED_INIT   1
 100         int                     id;
 101         int                     last_detect_state;
 102 };
 103
 104 static struct workqueue_struct *dw_mci_card_workqueue;
 105
 106 #if defined(CONFIG_DEBUG_FS)
 107 static int dw_mci_req_show(struct seq_file *s, void *v)
 108 {
 109         struct dw_mci_slot *slot = s->private;
 110         struct mmc_request *mrq;
 111         struct mmc_command *cmd;
 112         struct mmc_command *stop;
 113         struct mmc_data *data;
 114
 115         /* Make sure we get a consistent snapshot */
 116         spin_lock_bh(&slot->host->lock);
 117         mrq = slot->mrq;
 118
 119         if (mrq) {
 120                 cmd = mrq->cmd;
 121                 data = mrq->data;
 122                 stop = mrq->stop;
 123
 124                 if (cmd)
 125                         seq_printf(s,
 126                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 127                                    cmd->opcode, cmd->arg, cmd->flags,
 128                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 129                                    cmd->resp[2], cmd->error);
 130                 if (data)
 131                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 132                                    data->bytes_xfered, data->blocks,
 133                                    data->blksz, data->flags, data->error);
 134                 if (stop)
 135                         seq_printf(s,
 136                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 137                                    stop->opcode, stop->arg, stop->flags,
 138                                    stop->resp[0], stop->resp[1], stop->resp[2],
 139                                    stop->resp[2], stop->error);
 140         }
 141
 142         spin_unlock_bh(&slot->host->lock);
 143
 144         return 0;
 145 }
 146
 147 static int dw_mci_req_open(struct inode *inode, struct file *file)
 148 {
 149         return single_open(file, dw_mci_req_show, inode->i_private);
 150 }
 151
 152 static const struct file_operations dw_mci_req_fops = {
 153         .owner          = THIS_MODULE,
 154         .open           = dw_mci_req_open,
 155         .read           = seq_read,
 156         .llseek         = seq_lseek,
 157         .release        = single_release,
 158 };
 159
 160 static int dw_mci_regs_show(struct seq_file *s, void *v)
 161 {
 162         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 163         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 164         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 165         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 166         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 167         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 168
 169         return 0;
 170 }
 171
 172 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 173 {
 174         return single_open(file, dw_mci_regs_show, inode->i_private);
 175 }
 176
 177 static const struct file_operations dw_mci_regs_fops = {
 178         .owner          = THIS_MODULE,
 179         .open           = dw_mci_regs_open,
 180         .read           = seq_read,
 181         .llseek         = seq_lseek,
 182         .release        = single_release,
 183 };
 184
 185 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 186 {
 187         struct mmc_host *mmc = slot->mmc;
 188         struct dw_mci *host = slot->host;
 189         struct dentry *root;
 190         struct dentry *node;
 191
 192         root = mmc->debugfs_root;
 193         if (!root)
 194                 return;
 195
 196         node = debugfs_create_file("regs", S_IRUSR, root, host,
 197                                    &dw_mci_regs_fops);
 198         if (!node)
 199                 goto err;
 200
 201         node = debugfs_create_file("req", S_IRUSR, root, slot,
 202                                    &dw_mci_req_fops);
 203         if (!node)
 204                 goto err;
 205
 206         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 207         if (!node)
 208                 goto err;
 209
 210         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 211                                   (u32 *)&host->pending_events);
 212         if (!node)
 213                 goto err;
 214
 215         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 216                                   (u32 *)&host->completed_events);
 217         if (!node)
 218                 goto err;
 219
 220         return;
 221
 222 err:
 223         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 224 }
 225 #endif /* defined(CONFIG_DEBUG_FS) */
 226
 227 static void dw_mci_set_timeout(struct dw_mci *host)
 228 {
 229         /* timeout (maximum) */
 230         mci_writel(host, TMOUT, 0xffffffff);
 231 }
 232
 233 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 234 {
 235         struct mmc_data *data;
 236         u32 cmdr;
 237         cmd->error = -EINPROGRESS;
 238
 239         cmdr = cmd->opcode;
 240
 241         if (cmdr == MMC_STOP_TRANSMISSION)
 242                 cmdr |= SDMMC_CMD_STOP;
 243         else
 244                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 245
 246         if (cmd->flags & MMC_RSP_PRESENT) {
 247                 /* We expect a response, so set this bit */
 248                 cmdr |= SDMMC_CMD_RESP_EXP;
 249                 if (cmd->flags & MMC_RSP_136)
 250                         cmdr |= SDMMC_CMD_RESP_LONG;
 251         }
 252
 253         if (cmd->flags & MMC_RSP_CRC)
 254                 cmdr |= SDMMC_CMD_RESP_CRC;
 255
 256         data = cmd->data;
 257         if (data) {
 258                 cmdr |= SDMMC_CMD_DAT_EXP;
 259                 if (data->flags & MMC_DATA_STREAM)
 260                         cmdr |= SDMMC_CMD_STRM_MODE;
 261                 if (data->flags & MMC_DATA_WRITE)
 262                         cmdr |= SDMMC_CMD_DAT_WR;
 263         }
 264
 265         return cmdr;
 266 }
 267
 268 static void dw_mci_start_command(struct dw_mci *host,
 269                                  struct mmc_command *cmd, u32 cmd_flags)
 270 {
 271         host->cmd = cmd;
 272         dev_vdbg(&host->pdev->dev,
 273                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 274                  cmd->arg, cmd_flags);
 275
 276         mci_writel(host, CMDARG, cmd->arg);
 277         wmb();
 278
 279         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 280 }
 281
 282 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 283 {
 284         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 285 }
 286
 287 /* DMA interface functions */
 288 static void dw_mci_stop_dma(struct dw_mci *host)
 289 {
 290         if (host->use_dma) {
 291                 host->dma_ops->stop(host);
 292                 host->dma_ops->cleanup(host);
 293         } else {
 294                 /* Data transfer was stopped by the interrupt handler */
 295                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 296         }
 297 }
 298
 299 #ifdef CONFIG_MMC_DW_IDMAC
 300 static void dw_mci_dma_cleanup(struct dw_mci *host)
 301 {
 302         struct mmc_data *data = host->data;
 303
 304         if (data)
 305                 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
 306                              ((data->flags & MMC_DATA_WRITE)
 307                               ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
 308 }
 309
 310 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 311 {
 312         u32 temp;
 313
 314         /* Disable and reset the IDMAC interface */
 315         temp = mci_readl(host, CTRL);
 316         temp &= ~SDMMC_CTRL_USE_IDMAC;
 317         temp |= SDMMC_CTRL_DMA_RESET;
 318         mci_writel(host, CTRL, temp);
 319
 320         /* Stop the IDMAC running */
 321         temp = mci_readl(host, BMOD);
 322         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 323         mci_writel(host, BMOD, temp);
 324 }
 325
 326 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 327 {
 328         struct mmc_data *data = host->data;
 329
 330         dev_vdbg(&host->pdev->dev, "DMA complete\n");
 331
 332         host->dma_ops->cleanup(host);
 333
 334         /*
 335          * If the card was removed, data will be NULL. No point in trying to
 336          * send the stop command or waiting for NBUSY in this case.
 337          */
 338         if (data) {
 339                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 340                 tasklet_schedule(&host->tasklet);
 341         }
 342 }
 343
 344 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 345                                     unsigned int sg_len)
 346 {
 347         int i;
 348         struct idmac_desc *desc = host->sg_cpu;
 349
 350         for (i = 0; i < sg_len; i++, desc++) {
 351                 unsigned int length = sg_dma_len(&data->sg[i]);
 352                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 353
 354                 /* Set the OWN bit and disable interrupts for this descriptor */
 355                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 356
 357                 /* Buffer length */
 358                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 359
 360                 /* Physical address to DMA to/from */
 361                 desc->des2 = mem_addr;
 362         }
 363
 364         /* Set first descriptor */
 365         desc = host->sg_cpu;
 366         desc->des0 |= IDMAC_DES0_FD;
 367
 368         /* Set last descriptor */
 369         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 370         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 371         desc->des0 |= IDMAC_DES0_LD;
 372
 373         wmb();
 374 }
 375
 376 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 377 {
 378         u32 temp;
 379
 380         dw_mci_translate_sglist(host, host->data, sg_len);
 381
 382         /* Select IDMAC interface */
 383         temp = mci_readl(host, CTRL);
 384         temp |= SDMMC_CTRL_USE_IDMAC;
 385         mci_writel(host, CTRL, temp);
 386
 387         wmb();
 388
 389         /* Enable the IDMAC */
 390         temp = mci_readl(host, BMOD);
 391         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 392         mci_writel(host, BMOD, temp);
 393
 394         /* Start it running */
 395         mci_writel(host, PLDMND, 1);
 396 }
 397
 398 static int dw_mci_idmac_init(struct dw_mci *host)
 399 {
 400         struct idmac_desc *p;
 401         int i;
 402
 403         /* Number of descriptors in the ring buffer */
 404         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 405
 406         /* Forward link the descriptor list */
 407         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 408                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 409
 410         /* Set the last descriptor as the end-of-ring descriptor */
 411         p->des3 = host->sg_dma;
 412         p->des0 = IDMAC_DES0_ER;
 413
 414         /* Mask out interrupts - get Tx & Rx complete only */
 415         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 416                    SDMMC_IDMAC_INT_TI);
 417
 418         /* Set the descriptor base address */
 419         mci_writel(host, DBADDR, host->sg_dma);
 420         return 0;
 421 }
 422
 423 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
 424         .init = dw_mci_idmac_init,
 425         .start = dw_mci_idmac_start_dma,
 426         .stop = dw_mci_idmac_stop_dma,
 427         .complete = dw_mci_idmac_complete_dma,
 428         .cleanup = dw_mci_dma_cleanup,
 429 };
 430 #endif /* CONFIG_MMC_DW_IDMAC */
 431
 432 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 433 {
 434         struct scatterlist *sg;
 435         unsigned int i, direction, sg_len;
 436         u32 temp;
 437
 438         /* If we don't have a channel, we can't do DMA */
 439         if (!host->use_dma)
 440                 return -ENODEV;
 441
 442         /*
 443          * We don't do DMA on "complex" transfers, i.e. with
 444          * non-word-aligned buffers or lengths. Also, we don't bother
 445          * with all the DMA setup overhead for short transfers.
 446          */
 447         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 448                 return -EINVAL;
 449         if (data->blksz & 3)
 450                 return -EINVAL;
 451
 452         for_each_sg(data->sg, sg, data->sg_len, i) {
 453                 if (sg->offset & 3 || sg->length & 3)
 454                         return -EINVAL;
 455         }
 456
 457         if (data->flags & MMC_DATA_READ)
 458                 direction = DMA_FROM_DEVICE;
 459         else
 460                 direction = DMA_TO_DEVICE;
 461
 462         sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
 463                             direction);
 464
 465         dev_vdbg(&host->pdev->dev,
 466                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 467                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 468                  sg_len);
 469
 470         /* Enable the DMA interface */
 471         temp = mci_readl(host, CTRL);
 472         temp |= SDMMC_CTRL_DMA_ENABLE;
 473         mci_writel(host, CTRL, temp);
 474
 475         /* Disable RX/TX IRQs, let DMA handle it */
 476         temp = mci_readl(host, INTMASK);
 477         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 478         mci_writel(host, INTMASK, temp);
 479
 480         host->dma_ops->start(host, sg_len);
 481
 482         return 0;
 483 }
 484
 485 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 486 {
 487         u32 temp;
 488
 489         data->error = -EINPROGRESS;
 490
 491         WARN_ON(host->data);
 492         host->sg = NULL;
 493         host->data = data;
 494
 495         if (dw_mci_submit_data_dma(host, data)) {
 496                 host->sg = data->sg;
 497                 host->pio_offset = 0;
 498                 if (data->flags & MMC_DATA_READ)
 499                         host->dir_status = DW_MCI_RECV_STATUS;
 500                 else
 501                         host->dir_status = DW_MCI_SEND_STATUS;
 502
 503                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 504                 temp = mci_readl(host, INTMASK);
 505                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 506                 mci_writel(host, INTMASK, temp);
 507
 508                 temp = mci_readl(host, CTRL);
 509                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 510                 mci_writel(host, CTRL, temp);
 511         }
 512 }
 513
 514 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 515 {
 516         struct dw_mci *host = slot->host;
 517         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 518         unsigned int cmd_status = 0;
 519
 520         mci_writel(host, CMDARG, arg);
 521         wmb();
 522         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 523
 524         while (time_before(jiffies, timeout)) {
 525                 cmd_status = mci_readl(host, CMD);
 526                 if (!(cmd_status & SDMMC_CMD_START))
 527                         return;
 528         }
 529         dev_err(&slot->mmc->class_dev,
 530                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 531                 cmd, arg, cmd_status);
 532 }
 533
 534 static void dw_mci_setup_bus(struct dw_mci_slot *slot)
 535 {
 536         struct dw_mci *host = slot->host;
 537         u32 div;
 538
 539         if (slot->clock != host->current_speed) {
 540                 if (host->bus_hz % slot->clock)
 541                         /*
 542                          * move the + 1 after the divide to prevent
 543                          * over-clocking the card.
 544                          */
 545                         div = ((host->bus_hz / slot->clock) >> 1) + 1;
 546                 else
 547                         div = (host->bus_hz  / slot->clock) >> 1;
 548
 549                 dev_info(&slot->mmc->class_dev,
 550                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 551                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 552                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 553
 554                 /* disable clock */
 555                 mci_writel(host, CLKENA, 0);
 556                 mci_writel(host, CLKSRC, 0);
 557
 558                 /* inform CIU */
 559                 mci_send_cmd(slot,
 560                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 561
 562                 /* set clock to desired speed */
 563                 mci_writel(host, CLKDIV, div);
 564
 565                 /* inform CIU */
 566                 mci_send_cmd(slot,
 567                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 568
 569                 /* enable clock */
 570                 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
 571                            SDMMC_CLKEN_LOW_PWR);
 572
 573                 /* inform CIU */
 574                 mci_send_cmd(slot,
 575                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 576
 577                 host->current_speed = slot->clock;
 578         }
 579
 580         /* Set the current slot bus width */
 581         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 582 }
 583
 584 static void dw_mci_start_request(struct dw_mci *host,
 585                                  struct dw_mci_slot *slot)
 586 {
 587         struct mmc_request *mrq;
 588         struct mmc_command *cmd;
 589         struct mmc_data *data;
 590         u32 cmdflags;
 591
 592         mrq = slot->mrq;
 593         if (host->pdata->select_slot)
 594                 host->pdata->select_slot(slot->id);
 595
 596         /* Slot specific timing and width adjustment */
 597         dw_mci_setup_bus(slot);
 598
 599         host->cur_slot = slot;
 600         host->mrq = mrq;
 601
 602         host->pending_events = 0;
 603         host->completed_events = 0;
 604         host->data_status = 0;
 605
 606         data = mrq->data;
 607         if (data) {
 608                 dw_mci_set_timeout(host);
 609                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 610                 mci_writel(host, BLKSIZ, data->blksz);
 611         }
 612
 613         cmd = mrq->cmd;
 614         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 615
 616         /* this is the first command, send the initialization clock */
 617         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 618                 cmdflags |= SDMMC_CMD_INIT;
 619
 620         if (data) {
 621                 dw_mci_submit_data(host, data);
 622                 wmb();
 623         }
 624
 625         dw_mci_start_command(host, cmd, cmdflags);
 626
 627         if (mrq->stop)
 628                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 629 }
 630
 631 /* must be called with host->lock held */
 632 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 633                                  struct mmc_request *mrq)
 634 {
 635         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 636                  host->state);
 637
 638         slot->mrq = mrq;
 639
 640         if (host->state == STATE_IDLE) {
 641                 host->state = STATE_SENDING_CMD;
 642                 dw_mci_start_request(host, slot);
 643         } else {
 644                 list_add_tail(&slot->queue_node, &host->queue);
 645         }
 646 }
 647
 648 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 649 {
 650         struct dw_mci_slot *slot = mmc_priv(mmc);
 651         struct dw_mci *host = slot->host;
 652
 653         WARN_ON(slot->mrq);
 654
 655         /*
 656          * The check for card presence and queueing of the request must be
 657          * atomic, otherwise the card could be removed in between and the
 658          * request wouldn't fail until another card was inserted.
 659          */
 660         spin_lock_bh(&host->lock);
 661
 662         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 663                 spin_unlock_bh(&host->lock);
 664                 mrq->cmd->error = -ENOMEDIUM;
 665                 mmc_request_done(mmc, mrq);
 666                 return;
 667         }
 668
 669         dw_mci_queue_request(host, slot, mrq);
 670
 671         spin_unlock_bh(&host->lock);
 672 }
 673
 674 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 675 {
 676         struct dw_mci_slot *slot = mmc_priv(mmc);
 677         u32 regs;
 678
 679         /* set default 1 bit mode */
 680         slot->ctype = SDMMC_CTYPE_1BIT;
 681
 682         switch (ios->bus_width) {
 683         case MMC_BUS_WIDTH_1:
 684                 slot->ctype = SDMMC_CTYPE_1BIT;
 685                 break;
 686         case MMC_BUS_WIDTH_4:
 687                 slot->ctype = SDMMC_CTYPE_4BIT;
 688                 break;
 689         case MMC_BUS_WIDTH_8:
 690                 slot->ctype = SDMMC_CTYPE_8BIT;
 691                 break;
 692         }
 693
 694         /* DDR mode set */
 695         if (ios->ddr) {
 696                 regs = mci_readl(slot->host, UHS_REG);
 697                 regs |= (0x1 << slot->id) << 16;
 698                 mci_writel(slot->host, UHS_REG, regs);
 699         }
 700
 701         if (ios->clock) {
 702                 /*
 703                  * Use mirror of ios->clock to prevent race with mmc
 704                  * core ios update when finding the minimum.
 705                  */
 706                 slot->clock = ios->clock;
 707         }
 708
 709         switch (ios->power_mode) {
 710         case MMC_POWER_UP:
 711                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 712                 break;
 713         default:
 714                 break;
 715         }
 716 }
 717
 718 static int dw_mci_get_ro(struct mmc_host *mmc)
 719 {
 720         int read_only;
 721         struct dw_mci_slot *slot = mmc_priv(mmc);
 722         struct dw_mci_board *brd = slot->host->pdata;
 723
 724         /* Use platform get_ro function, else try on board write protect */
 725         if (brd->get_ro)
 726                 read_only = brd->get_ro(slot->id);
 727         else
 728                 read_only =
 729                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 730
 731         dev_dbg(&mmc->class_dev, "card is %s\n",
 732                 read_only ? "read-only" : "read-write");
 733
 734         return read_only;
 735 }
 736
 737 static int dw_mci_get_cd(struct mmc_host *mmc)
 738 {
 739         int present;
 740         struct dw_mci_slot *slot = mmc_priv(mmc);
 741         struct dw_mci_board *brd = slot->host->pdata;
 742
 743         /* Use platform get_cd function, else try onboard card detect */
 744         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
 745                 present = 1;
 746         else if (brd->get_cd)
 747                 present = !brd->get_cd(slot->id);
 748         else
 749                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 750                         == 0 ? 1 : 0;
 751
 752         if (present)
 753                 dev_dbg(&mmc->class_dev, "card is present\n");
 754         else
 755                 dev_dbg(&mmc->class_dev, "card is not present\n");
 756
 757         return present;
 758 }
 759
 760 static const struct mmc_host_ops dw_mci_ops = {
 761         .request        = dw_mci_request,
 762         .set_ios        = dw_mci_set_ios,
 763         .get_ro         = dw_mci_get_ro,
 764         .get_cd         = dw_mci_get_cd,
 765 };
 766
 767 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 768         __releases(&host->lock)
 769         __acquires(&host->lock)
 770 {
 771         struct dw_mci_slot *slot;
 772         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 773
 774         WARN_ON(host->cmd || host->data);
 775
 776         host->cur_slot->mrq = NULL;
 777         host->mrq = NULL;
 778         if (!list_empty(&host->queue)) {
 779                 slot = list_entry(host->queue.next,
 780                                   struct dw_mci_slot, queue_node);
 781                 list_del(&slot->queue_node);
 782                 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
 783                          mmc_hostname(slot->mmc));
 784                 host->state = STATE_SENDING_CMD;
 785                 dw_mci_start_request(host, slot);
 786         } else {
 787                 dev_vdbg(&host->pdev->dev, "list empty\n");
 788                 host->state = STATE_IDLE;
 789         }
 790
 791         spin_unlock(&host->lock);
 792         mmc_request_done(prev_mmc, mrq);
 793         spin_lock(&host->lock);
 794 }
 795
 796 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 797 {
 798         u32 status = host->cmd_status;
 799
 800         host->cmd_status = 0;
 801
 802         /* Read the response from the card (up to 16 bytes) */
 803         if (cmd->flags & MMC_RSP_PRESENT) {
 804                 if (cmd->flags & MMC_RSP_136) {
 805                         cmd->resp[3] = mci_readl(host, RESP0);
 806                         cmd->resp[2] = mci_readl(host, RESP1);
 807                         cmd->resp[1] = mci_readl(host, RESP2);
 808                         cmd->resp[0] = mci_readl(host, RESP3);
 809                 } else {
 810                         cmd->resp[0] = mci_readl(host, RESP0);
 811                         cmd->resp[1] = 0;
 812                         cmd->resp[2] = 0;
 813                         cmd->resp[3] = 0;
 814                 }
 815         }
 816
 817         if (status & SDMMC_INT_RTO)
 818                 cmd->error = -ETIMEDOUT;
 819         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 820                 cmd->error = -EILSEQ;
 821         else if (status & SDMMC_INT_RESP_ERR)
 822                 cmd->error = -EIO;
 823         else
 824                 cmd->error = 0;
 825
 826         if (cmd->error) {
 827                 /* newer ip versions need a delay between retries */
 828                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
 829                         mdelay(20);
 830
 831                 if (cmd->data) {
 832                         host->data = NULL;
 833                         dw_mci_stop_dma(host);
 834                 }
 835         }
 836 }
 837
 838 static void dw_mci_tasklet_func(unsigned long priv)
 839 {
 840         struct dw_mci *host = (struct dw_mci *)priv;
 841         struct mmc_data *data;
 842         struct mmc_command *cmd;
 843         enum dw_mci_state state;
 844         enum dw_mci_state prev_state;
 845         u32 status;
 846
 847         spin_lock(&host->lock);
 848
 849         state = host->state;
 850         data = host->data;
 851
 852         do {
 853                 prev_state = state;
 854
 855                 switch (state) {
 856                 case STATE_IDLE:
 857                         break;
 858
 859                 case STATE_SENDING_CMD:
 860                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 861                                                 &host->pending_events))
 862                                 break;
 863
 864                         cmd = host->cmd;
 865                         host->cmd = NULL;
 866                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
 867                         dw_mci_command_complete(host, host->mrq->cmd);
 868                         if (!host->mrq->data || cmd->error) {
 869                                 dw_mci_request_end(host, host->mrq);
 870                                 goto unlock;
 871                         }
 872
 873                         prev_state = state = STATE_SENDING_DATA;
 874                         /* fall through */
 875
 876                 case STATE_SENDING_DATA:
 877                         if (test_and_clear_bit(EVENT_DATA_ERROR,
 878                                                &host->pending_events)) {
 879                                 dw_mci_stop_dma(host);
 880                                 if (data->stop)
 881                                         send_stop_cmd(host, data);
 882                                 state = STATE_DATA_ERROR;
 883                                 break;
 884                         }
 885
 886                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
 887                                                 &host->pending_events))
 888                                 break;
 889
 890                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
 891                         prev_state = state = STATE_DATA_BUSY;
 892                         /* fall through */
 893
 894                 case STATE_DATA_BUSY:
 895                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
 896                                                 &host->pending_events))
 897                                 break;
 898
 899                         host->data = NULL;
 900                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
 901                         status = host->data_status;
 902
 903                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
 904                                 if (status & SDMMC_INT_DTO) {
 905                                         dev_err(&host->pdev->dev,
 906                                                 "data timeout error\n");
 907                                         data->error = -ETIMEDOUT;
 908                                 } else if (status & SDMMC_INT_DCRC) {
 909                                         dev_err(&host->pdev->dev,
 910                                                 "data CRC error\n");
 911                                         data->error = -EILSEQ;
 912                                 } else {
 913                                         dev_err(&host->pdev->dev,
 914                                                 "data FIFO error "
 915                                                 "(status=%08x)\n",
 916                                                 status);
 917                                         data->error = -EIO;
 918                                 }
 919                         } else {
 920                                 data->bytes_xfered = data->blocks * data->blksz;
 921                                 data->error = 0;
 922                         }
 923
 924                         if (!data->stop) {
 925                                 dw_mci_request_end(host, host->mrq);
 926                                 goto unlock;
 927                         }
 928
 929                         prev_state = state = STATE_SENDING_STOP;
 930                         if (!data->error)
 931                                 send_stop_cmd(host, data);
 932                         /* fall through */
 933
 934                 case STATE_SENDING_STOP:
 935                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
 936                                                 &host->pending_events))
 937                                 break;
 938
 939                         host->cmd = NULL;
 940                         dw_mci_command_complete(host, host->mrq->stop);
 941                         dw_mci_request_end(host, host->mrq);
 942                         goto unlock;
 943
 944                 case STATE_DATA_ERROR:
 945                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
 946                                                 &host->pending_events))
 947                                 break;
 948
 949                         state = STATE_DATA_BUSY;
 950                         break;
 951                 }
 952         } while (state != prev_state);
 953
 954         host->state = state;
 955 unlock:
 956         spin_unlock(&host->lock);
 957
 958 }
 959
 960 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
 961 {
 962         u16 *pdata = (u16 *)buf;
 963
 964         WARN_ON(cnt % 2 != 0);
 965
 966         cnt = cnt >> 1;
 967         while (cnt > 0) {
 968                 mci_writew(host, DATA, *pdata++);
 969                 cnt--;
 970         }
 971 }
 972
 973 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
 974 {
 975         u16 *pdata = (u16 *)buf;
 976
 977         WARN_ON(cnt % 2 != 0);
 978
 979         cnt = cnt >> 1;
 980         while (cnt > 0) {
 981                 *pdata++ = mci_readw(host, DATA);
 982                 cnt--;
 983         }
 984 }
 985
 986 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
 987 {
 988         u32 *pdata = (u32 *)buf;
 989
 990         WARN_ON(cnt % 4 != 0);
 991         WARN_ON((unsigned long)pdata & 0x3);
 992
 993         cnt = cnt >> 2;
 994         while (cnt > 0) {
 995                 mci_writel(host, DATA, *pdata++);
 996                 cnt--;
 997         }
 998 }
 999
1000 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1001 {
1002         u32 *pdata = (u32 *)buf;
1003
1004         WARN_ON(cnt % 4 != 0);
1005         WARN_ON((unsigned long)pdata & 0x3);
1006
1007         cnt = cnt >> 2;
1008         while (cnt > 0) {
1009                 *pdata++ = mci_readl(host, DATA);
1010                 cnt--;
1011         }
1012 }
1013
1014 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1015 {
1016         u64 *pdata = (u64 *)buf;
1017
1018         WARN_ON(cnt % 8 != 0);
1019
1020         cnt = cnt >> 3;
1021         while (cnt > 0) {
1022                 mci_writeq(host, DATA, *pdata++);
1023                 cnt--;
1024         }
1025 }
1026
1027 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1028 {
1029         u64 *pdata = (u64 *)buf;
1030
1031         WARN_ON(cnt % 8 != 0);
1032
1033         cnt = cnt >> 3;
1034         while (cnt > 0) {
1035                 *pdata++ = mci_readq(host, DATA);
1036                 cnt--;
1037         }
1038 }
1039
1040 static void dw_mci_read_data_pio(struct dw_mci *host)
1041 {
1042         struct scatterlist *sg = host->sg;
1043         void *buf = sg_virt(sg);
1044         unsigned int offset = host->pio_offset;
1045         struct mmc_data *data = host->data;
1046         int shift = host->data_shift;
1047         u32 status;
1048         unsigned int nbytes = 0, len;
1049
1050         do {
1051                 len = SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift;
1052                 if (offset + len <= sg->length) {
1053                         host->pull_data(host, (void *)(buf + offset), len);
1054
1055                         offset += len;
1056                         nbytes += len;
1057
1058                         if (offset == sg->length) {
1059                                 flush_dcache_page(sg_page(sg));
1060                                 host->sg = sg = sg_next(sg);
1061                                 if (!sg)
1062                                         goto done;
1063
1064                                 offset = 0;
1065                                 buf = sg_virt(sg);
1066                         }
1067                 } else {
1068                         unsigned int remaining = sg->length - offset;
1069                         host->pull_data(host, (void *)(buf + offset),
1070                                         remaining);
1071                         nbytes += remaining;
1072
1073                         flush_dcache_page(sg_page(sg));
1074                         host->sg = sg = sg_next(sg);
1075                         if (!sg)
1076                                 goto done;
1077
1078                         offset = len - remaining;
1079                         buf = sg_virt(sg);
1080                         host->pull_data(host, buf, offset);
1081                         nbytes += offset;
1082                 }
1083
1084                 status = mci_readl(host, MINTSTS);
1085                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1086                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1087                         host->data_status = status;
1088                         data->bytes_xfered += nbytes;
1089                         smp_wmb();
1090
1091                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1092
1093                         tasklet_schedule(&host->tasklet);
1094                         return;
1095                 }
1096         } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1097         len = SDMMC_GET_FCNT(mci_readl(host, STATUS));
1098         host->pio_offset = offset;
1099         data->bytes_xfered += nbytes;
1100         return;
1101
1102 done:
1103         data->bytes_xfered += nbytes;
1104         smp_wmb();
1105         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1106 }
1107
1108 static void dw_mci_write_data_pio(struct dw_mci *host)
1109 {
1110         struct scatterlist *sg = host->sg;
1111         void *buf = sg_virt(sg);
1112         unsigned int offset = host->pio_offset;
1113         struct mmc_data *data = host->data;
1114         int shift = host->data_shift;
1115         u32 status;
1116         unsigned int nbytes = 0, len;
1117
1118         do {
1119                 len = SDMMC_FIFO_SZ -
1120                         (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1121                 if (offset + len <= sg->length) {
1122                         host->push_data(host, (void *)(buf + offset), len);
1123
1124                         offset += len;
1125                         nbytes += len;
1126                         if (offset == sg->length) {
1127                                 host->sg = sg = sg_next(sg);
1128                                 if (!sg)
1129                                         goto done;
1130
1131                                 offset = 0;
1132                                 buf = sg_virt(sg);
1133                         }
1134                 } else {
1135                         unsigned int remaining = sg->length - offset;
1136
1137                         host->push_data(host, (void *)(buf + offset),
1138                                         remaining);
1139                         nbytes += remaining;
1140
1141                         host->sg = sg = sg_next(sg);
1142                         if (!sg)
1143                                 goto done;
1144
1145                         offset = len - remaining;
1146                         buf = sg_virt(sg);
1147                         host->push_data(host, (void *)buf, offset);
1148                         nbytes += offset;
1149                 }
1150
1151                 status = mci_readl(host, MINTSTS);
1152                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1153                 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1154                         host->data_status = status;
1155                         data->bytes_xfered += nbytes;
1156
1157                         smp_wmb();
1158
1159                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1160
1161                         tasklet_schedule(&host->tasklet);
1162                         return;
1163                 }
1164         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1165
1166         host->pio_offset = offset;
1167         data->bytes_xfered += nbytes;
1168
1169         return;
1170
1171 done:
1172         data->bytes_xfered += nbytes;
1173         smp_wmb();
1174         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1175 }
1176
1177 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1178 {
1179         if (!host->cmd_status)
1180                 host->cmd_status = status;
1181
1182         smp_wmb();
1183
1184         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1185         tasklet_schedule(&host->tasklet);
1186 }
1187
1188 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1189 {
1190         struct dw_mci *host = dev_id;
1191         u32 status, pending;
1192         unsigned int pass_count = 0;
1193
1194         do {
1195                 status = mci_readl(host, RINTSTS);
1196                 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1197
1198                 /*
1199                  * DTO fix - version 2.10a and below, and only if internal DMA
1200                  * is configured.
1201                  */
1202                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1203                         if (!pending &&
1204                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1205                                 pending |= SDMMC_INT_DATA_OVER;
1206                 }
1207
1208                 if (!pending)
1209                         break;
1210
1211                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1212                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1213                         host->cmd_status = status;
1214                         smp_wmb();
1215                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1216                 }
1217
1218                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1219                         /* if there is an error report DATA_ERROR */
1220                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1221                         host->data_status = status;
1222                         smp_wmb();
1223                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1224                         if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1225                                          SDMMC_INT_SBE | SDMMC_INT_EBE)))
1226                                 tasklet_schedule(&host->tasklet);
1227                 }
1228
1229                 if (pending & SDMMC_INT_DATA_OVER) {
1230                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1231                         if (!host->data_status)
1232                                 host->data_status = status;
1233                         smp_wmb();
1234                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1235                                 if (host->sg != NULL)
1236                                         dw_mci_read_data_pio(host);
1237                         }
1238                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1239                         tasklet_schedule(&host->tasklet);
1240                 }
1241
1242                 if (pending & SDMMC_INT_RXDR) {
1243                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1244                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1245                                 dw_mci_read_data_pio(host);
1246                 }
1247
1248                 if (pending & SDMMC_INT_TXDR) {
1249                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1250                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1251                                 dw_mci_write_data_pio(host);
1252                 }
1253
1254                 if (pending & SDMMC_INT_CMD_DONE) {
1255                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1256                         dw_mci_cmd_interrupt(host, status);
1257                 }
1258
1259                 if (pending & SDMMC_INT_CD) {
1260                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1261                         queue_work(dw_mci_card_workqueue, &host->card_work);
1262                 }
1263
1264         } while (pass_count++ < 5);
1265
1266 #ifdef CONFIG_MMC_DW_IDMAC
1267         /* Handle DMA interrupts */
1268         pending = mci_readl(host, IDSTS);
1269         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1270                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1271                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1272                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1273                 host->dma_ops->complete(host);
1274         }
1275 #endif
1276
1277         return IRQ_HANDLED;
1278 }
1279
1280 static void dw_mci_work_routine_card(struct work_struct *work)
1281 {
1282         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1283         int i;
1284
1285         for (i = 0; i < host->num_slots; i++) {
1286                 struct dw_mci_slot *slot = host->slot[i];
1287                 struct mmc_host *mmc = slot->mmc;
1288                 struct mmc_request *mrq;
1289                 int present;
1290                 u32 ctrl;
1291
1292                 present = dw_mci_get_cd(mmc);
1293                 while (present != slot->last_detect_state) {
1294                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1295                                 present ? "inserted" : "removed");
1296
1297                         /* Power up slot (before spin_lock, may sleep) */
1298                         if (present != 0 && host->pdata->setpower)
1299                                 host->pdata->setpower(slot->id, mmc->ocr_avail);
1300
1301                         spin_lock_bh(&host->lock);
1302
1303                         /* Card change detected */
1304                         slot->last_detect_state = present;
1305
1306                         /* Mark card as present if applicable */
1307                         if (present != 0)
1308                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1309
1310                         /* Clean up queue if present */
1311                         mrq = slot->mrq;
1312                         if (mrq) {
1313                                 if (mrq == host->mrq) {
1314                                         host->data = NULL;
1315                                         host->cmd = NULL;
1316
1317                                         switch (host->state) {
1318                                         case STATE_IDLE:
1319                                                 break;
1320                                         case STATE_SENDING_CMD:
1321                                                 mrq->cmd->error = -ENOMEDIUM;
1322                                                 if (!mrq->data)
1323                                                         break;
1324                                                 /* fall through */
1325                                         case STATE_SENDING_DATA:
1326                                                 mrq->data->error = -ENOMEDIUM;
1327                                                 dw_mci_stop_dma(host);
1328                                                 break;
1329                                         case STATE_DATA_BUSY:
1330                                         case STATE_DATA_ERROR:
1331                                                 if (mrq->data->error == -EINPROGRESS)
1332                                                         mrq->data->error = -ENOMEDIUM;
1333                                                 if (!mrq->stop)
1334                                                         break;
1335                                                 /* fall through */
1336                                         case STATE_SENDING_STOP:
1337                                                 mrq->stop->error = -ENOMEDIUM;
1338                                                 break;
1339                                         }
1340
1341                                         dw_mci_request_end(host, mrq);
1342                                 } else {
1343                                         list_del(&slot->queue_node);
1344                                         mrq->cmd->error = -ENOMEDIUM;
1345                                         if (mrq->data)
1346                                                 mrq->data->error = -ENOMEDIUM;
1347                                         if (mrq->stop)
1348                                                 mrq->stop->error = -ENOMEDIUM;
1349
1350                                         spin_unlock(&host->lock);
1351                                         mmc_request_done(slot->mmc, mrq);
1352                                         spin_lock(&host->lock);
1353                                 }
1354                         }
1355
1356                         /* Power down slot */
1357                         if (present == 0) {
1358                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1359
1360                                 /*
1361                                  * Clear down the FIFO - doing so generates a
1362                                  * block interrupt, hence setting the
1363                                  * scatter-gather pointer to NULL.
1364                                  */
1365                                 host->sg = NULL;
1366
1367                                 ctrl = mci_readl(host, CTRL);
1368                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1369                                 mci_writel(host, CTRL, ctrl);
1370
1371 #ifdef CONFIG_MMC_DW_IDMAC
1372                                 ctrl = mci_readl(host, BMOD);
1373                                 ctrl |= 0x01; /* Software reset of DMA */
1374                                 mci_writel(host, BMOD, ctrl);
1375 #endif
1376
1377                         }
1378
1379                         spin_unlock_bh(&host->lock);
1380
1381                         /* Power down slot (after spin_unlock, may sleep) */
1382                         if (present == 0 && host->pdata->setpower)
1383                                 host->pdata->setpower(slot->id, 0);
1384
1385                         present = dw_mci_get_cd(mmc);
1386                 }
1387
1388                 mmc_detect_change(slot->mmc,
1389                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1390         }
1391 }
1392
1393 static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1394 {
1395         struct mmc_host *mmc;
1396         struct dw_mci_slot *slot;
1397
1398         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1399         if (!mmc)
1400                 return -ENOMEM;
1401
1402         slot = mmc_priv(mmc);
1403         slot->id = id;
1404         slot->mmc = mmc;
1405         slot->host = host;
1406
1407         mmc->ops = &dw_mci_ops;
1408         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1409         mmc->f_max = host->bus_hz;
1410
1411         if (host->pdata->get_ocr)
1412                 mmc->ocr_avail = host->pdata->get_ocr(id);
1413         else
1414                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1415
1416         /*
1417          * Start with slot power disabled, it will be enabled when a card
1418          * is detected.
1419          */
1420         if (host->pdata->setpower)
1421                 host->pdata->setpower(id, 0);
1422
1423         if (host->pdata->caps)
1424                 mmc->caps = host->pdata->caps;
1425         else
1426                 mmc->caps = 0;
1427
1428         if (host->pdata->get_bus_wd)
1429                 if (host->pdata->get_bus_wd(slot->id) >= 4)
1430                         mmc->caps |= MMC_CAP_4_BIT_DATA;
1431
1432         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1433                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1434
1435 #ifdef CONFIG_MMC_DW_IDMAC
1436         mmc->max_segs = host->ring_size;
1437         mmc->max_blk_size = 65536;
1438         mmc->max_blk_count = host->ring_size;
1439         mmc->max_seg_size = 0x1000;
1440         mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1441 #else
1442         if (host->pdata->blk_settings) {
1443                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1444                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1445                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1446                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1447                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1448         } else {
1449                 /* Useful defaults if platform data is unset. */
1450                 mmc->max_segs = 64;
1451                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1452                 mmc->max_blk_count = 512;
1453                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1454                 mmc->max_seg_size = mmc->max_req_size;
1455         }
1456 #endif /* CONFIG_MMC_DW_IDMAC */
1457
1458         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1459         if (IS_ERR(host->vmmc)) {
1460                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1461                 host->vmmc = NULL;
1462         } else
1463                 regulator_enable(host->vmmc);
1464
1465         if (dw_mci_get_cd(mmc))
1466                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1467         else
1468                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1469
1470         host->slot[id] = slot;
1471         mmc_add_host(mmc);
1472
1473 #if defined(CONFIG_DEBUG_FS)
1474         dw_mci_init_debugfs(slot);
1475 #endif
1476
1477         /* Card initially undetected */
1478         slot->last_detect_state = 0;
1479
1480         /*
1481          * Card may have been plugged in prior to boot so we
1482          * need to run the detect tasklet
1483          */
1484         queue_work(dw_mci_card_workqueue, &host->card_work);
1485
1486         return 0;
1487 }
1488
1489 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1490 {
1491         /* Shutdown detect IRQ */
1492         if (slot->host->pdata->exit)
1493                 slot->host->pdata->exit(id);
1494
1495         /* Debugfs stuff is cleaned up by mmc core */
1496         mmc_remove_host(slot->mmc);
1497         slot->host->slot[id] = NULL;
1498         mmc_free_host(slot->mmc);
1499 }
1500
1501 static void dw_mci_init_dma(struct dw_mci *host)
1502 {
1503         /* Alloc memory for sg translation */
1504         host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1505                                           &host->sg_dma, GFP_KERNEL);
1506         if (!host->sg_cpu) {
1507                 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1508                         __func__);
1509                 goto no_dma;
1510         }
1511
1512         /* Determine which DMA interface to use */
1513 #ifdef CONFIG_MMC_DW_IDMAC
1514         host->dma_ops = &dw_mci_idmac_ops;
1515         dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1516 #endif
1517
1518         if (!host->dma_ops)
1519                 goto no_dma;
1520
1521         if (host->dma_ops->init) {
1522                 if (host->dma_ops->init(host)) {
1523                         dev_err(&host->pdev->dev, "%s: Unable to initialize "
1524                                 "DMA Controller.\n", __func__);
1525                         goto no_dma;
1526                 }
1527         } else {
1528                 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1529                 goto no_dma;
1530         }
1531
1532         host->use_dma = 1;
1533         return;
1534
1535 no_dma:
1536         dev_info(&host->pdev->dev, "Using PIO mode.\n");
1537         host->use_dma = 0;
1538         return;
1539 }
1540
1541 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1542 {
1543         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1544         unsigned int ctrl;
1545
1546         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1547                                 SDMMC_CTRL_DMA_RESET));
1548
1549         /* wait till resets clear */
1550         do {
1551                 ctrl = mci_readl(host, CTRL);
1552                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1553                               SDMMC_CTRL_DMA_RESET)))
1554                         return true;
1555         } while (time_before(jiffies, timeout));
1556
1557         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1558
1559         return false;
1560 }
1561
1562 static int dw_mci_probe(struct platform_device *pdev)
1563 {
1564         struct dw_mci *host;
1565         struct resource *regs;
1566         struct dw_mci_board *pdata;
1567         int irq, ret, i, width;
1568         u32 fifo_size;
1569
1570         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1571         if (!regs)
1572                 return -ENXIO;
1573
1574         irq = platform_get_irq(pdev, 0);
1575         if (irq < 0)
1576                 return irq;
1577
1578         host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1579         if (!host)
1580                 return -ENOMEM;
1581
1582         host->pdev = pdev;
1583         host->pdata = pdata = pdev->dev.platform_data;
1584         if (!pdata || !pdata->init) {
1585                 dev_err(&pdev->dev,
1586                         "Platform data must supply init function\n");
1587                 ret = -ENODEV;
1588                 goto err_freehost;
1589         }
1590
1591         if (!pdata->select_slot && pdata->num_slots > 1) {
1592                 dev_err(&pdev->dev,
1593                         "Platform data must supply select_slot function\n");
1594                 ret = -ENODEV;
1595                 goto err_freehost;
1596         }
1597
1598         if (!pdata->bus_hz) {
1599                 dev_err(&pdev->dev,
1600                         "Platform data must supply bus speed\n");
1601                 ret = -ENODEV;
1602                 goto err_freehost;
1603         }
1604
1605         host->bus_hz = pdata->bus_hz;
1606         host->quirks = pdata->quirks;
1607
1608         spin_lock_init(&host->lock);
1609         INIT_LIST_HEAD(&host->queue);
1610
1611         ret = -ENOMEM;
1612         host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1613         if (!host->regs)
1614                 goto err_freehost;
1615
1616         host->dma_ops = pdata->dma_ops;
1617         dw_mci_init_dma(host);
1618
1619         /*
1620          * Get the host data width - this assumes that HCON has been set with
1621          * the correct values.
1622          */
1623         i = (mci_readl(host, HCON) >> 7) & 0x7;
1624         if (!i) {
1625                 host->push_data = dw_mci_push_data16;
1626                 host->pull_data = dw_mci_pull_data16;
1627                 width = 16;
1628                 host->data_shift = 1;
1629         } else if (i == 2) {
1630                 host->push_data = dw_mci_push_data64;
1631                 host->pull_data = dw_mci_pull_data64;
1632                 width = 64;
1633                 host->data_shift = 3;
1634         } else {
1635                 /* Check for a reserved value, and warn if it is */
1636                 WARN((i != 1),
1637                      "HCON reports a reserved host data width!\n"
1638                      "Defaulting to 32-bit access.\n");
1639                 host->push_data = dw_mci_push_data32;
1640                 host->pull_data = dw_mci_pull_data32;
1641                 width = 32;
1642                 host->data_shift = 2;
1643         }
1644
1645         /* Reset all blocks */
1646         if (!mci_wait_reset(&pdev->dev, host)) {
1647                 ret = -ENODEV;
1648                 goto err_dmaunmap;
1649         }
1650
1651         /* Clear the interrupts for the host controller */
1652         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1653         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1654
1655         /* Put in max timeout */
1656         mci_writel(host, TMOUT, 0xFFFFFFFF);
1657
1658         /*
1659          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
1660          *                          Tx Mark = fifo_size / 2 DMA Size = 8
1661          */
1662         fifo_size = mci_readl(host, FIFOTH);
1663         fifo_size = (fifo_size >> 16) & 0x7ff;
1664         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1665                         ((fifo_size/2) << 0));
1666         mci_writel(host, FIFOTH, host->fifoth_val);
1667
1668         /* disable clock to CIU */
1669         mci_writel(host, CLKENA, 0);
1670         mci_writel(host, CLKSRC, 0);
1671
1672         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1673         dw_mci_card_workqueue = alloc_workqueue("dw-mci-card",
1674                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
1675         if (!dw_mci_card_workqueue)
1676                 goto err_dmaunmap;
1677         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
1678
1679         ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1680         if (ret)
1681                 goto err_workqueue;
1682
1683         platform_set_drvdata(pdev, host);
1684
1685         if (host->pdata->num_slots)
1686                 host->num_slots = host->pdata->num_slots;
1687         else
1688                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1689
1690         /* We need at least one slot to succeed */
1691         for (i = 0; i < host->num_slots; i++) {
1692                 ret = dw_mci_init_slot(host, i);
1693                 if (ret) {
1694                         ret = -ENODEV;
1695                         goto err_init_slot;
1696                 }
1697         }
1698
1699         /*
1700          * Enable interrupts for command done, data over, data empty, card det,
1701          * receive ready and error such as transmit, receive timeout, crc error
1702          */
1703         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1704         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1705                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1706                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1707         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1708
1709         dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1710                  "%d bit host data width\n", irq, width);
1711         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1712                 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1713
1714         return 0;
1715
1716 err_init_slot:
1717         /* De-init any initialized slots */
1718         while (i > 0) {
1719                 if (host->slot[i])
1720                         dw_mci_cleanup_slot(host->slot[i], i);
1721                 i--;
1722         }
1723         free_irq(irq, host);
1724
1725 err_workqueue:
1726         destroy_workqueue(dw_mci_card_workqueue);
1727
1728 err_dmaunmap:
1729         if (host->use_dma && host->dma_ops->exit)
1730                 host->dma_ops->exit(host);
1731         dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1732                           host->sg_cpu, host->sg_dma);
1733         iounmap(host->regs);
1734
1735         if (host->vmmc) {
1736                 regulator_disable(host->vmmc);
1737                 regulator_put(host->vmmc);
1738         }
1739
1740
1741 err_freehost:
1742         kfree(host);
1743         return ret;
1744 }
1745
1746 static int __exit dw_mci_remove(struct platform_device *pdev)
1747 {
1748         struct dw_mci *host = platform_get_drvdata(pdev);
1749         int i;
1750
1751         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1752         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1753
1754         platform_set_drvdata(pdev, NULL);
1755
1756         for (i = 0; i < host->num_slots; i++) {
1757                 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1758                 if (host->slot[i])
1759                         dw_mci_cleanup_slot(host->slot[i], i);
1760         }
1761
1762         /* disable clock to CIU */
1763         mci_writel(host, CLKENA, 0);
1764         mci_writel(host, CLKSRC, 0);
1765
1766         free_irq(platform_get_irq(pdev, 0), host);
1767         destroy_workqueue(dw_mci_card_workqueue);
1768         dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1769
1770         if (host->use_dma && host->dma_ops->exit)
1771                 host->dma_ops->exit(host);
1772
1773         if (host->vmmc) {
1774                 regulator_disable(host->vmmc);
1775                 regulator_put(host->vmmc);
1776         }
1777
1778         iounmap(host->regs);
1779
1780         kfree(host);
1781         return 0;
1782 }
1783
1784 #ifdef CONFIG_PM
1785 /*
1786  * TODO: we should probably disable the clock to the card in the suspend path.
1787  */
1788 static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
1789 {
1790         int i, ret;
1791         struct dw_mci *host = platform_get_drvdata(pdev);
1792
1793         for (i = 0; i < host->num_slots; i++) {
1794                 struct dw_mci_slot *slot = host->slot[i];
1795                 if (!slot)
1796                         continue;
1797                 ret = mmc_suspend_host(slot->mmc);
1798                 if (ret < 0) {
1799                         while (--i >= 0) {
1800                                 slot = host->slot[i];
1801                                 if (slot)
1802                                         mmc_resume_host(host->slot[i]->mmc);
1803                         }
1804                         return ret;
1805                 }
1806         }
1807
1808         if (host->vmmc)
1809                 regulator_disable(host->vmmc);
1810
1811         return 0;
1812 }
1813
1814 static int dw_mci_resume(struct platform_device *pdev)
1815 {
1816         int i, ret;
1817         struct dw_mci *host = platform_get_drvdata(pdev);
1818
1819         if (host->vmmc)
1820                 regulator_enable(host->vmmc);
1821
1822         if (host->dma_ops->init)
1823                 host->dma_ops->init(host);
1824
1825         if (!mci_wait_reset(&pdev->dev, host)) {
1826                 ret = -ENODEV;
1827                 return ret;
1828         }
1829
1830         /* Restore the old value at FIFOTH register */
1831         mci_writel(host, FIFOTH, host->fifoth_val);
1832
1833         mci_writel(host, RINTSTS, 0xFFFFFFFF);
1834         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1835                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1836                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1837         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
1838
1839         for (i = 0; i < host->num_slots; i++) {
1840                 struct dw_mci_slot *slot = host->slot[i];
1841                 if (!slot)
1842                         continue;
1843                 ret = mmc_resume_host(host->slot[i]->mmc);
1844                 if (ret < 0)
1845                         return ret;
1846         }
1847
1848         return 0;
1849 }
1850 #else
1851 #define dw_mci_suspend  NULL
1852 #define dw_mci_resume   NULL
1853 #endif /* CONFIG_PM */
1854
1855 static struct platform_driver dw_mci_driver = {
1856         .remove         = __exit_p(dw_mci_remove),
1857         .suspend        = dw_mci_suspend,
1858         .resume         = dw_mci_resume,
1859         .driver         = {
1860                 .name           = "dw_mmc",
1861         },
1862 };
1863
1864 static int __init dw_mci_init(void)
1865 {
1866         return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
1867 }
1868
1869 static void __exit dw_mci_exit(void)
1870 {
1871         platform_driver_unregister(&dw_mci_driver);
1872 }
1873
1874 module_init(dw_mci_init);
1875 module_exit(dw_mci_exit);
1876
1877 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
1878 MODULE_AUTHOR("NXP Semiconductor VietNam");
1879 MODULE_AUTHOR("Imagination Technologies Ltd");
1880 MODULE_LICENSE("GPL v2");