drivers/mmc/host/au1xmmc.c

   1 /*
   2  * linux/drivers/mmc/host/au1xmmc.c - AU1XX0 MMC driver
   3  *
   4  *  Copyright (c) 2005, Advanced Micro Devices, Inc.
   5  *
   6  *  Developed with help from the 2.4.30 MMC AU1XXX controller including
   7  *  the following copyright notices:
   8  *     Copyright (c) 2003-2004 Embedded Edge, LLC.
   9  *     Portions Copyright (C) 2002 Embedix, Inc
  10  *     Copyright 2002 Hewlett-Packard Company
  11
  12  *  2.6 version of this driver inspired by:
  13  *     (drivers/mmc/wbsd.c) Copyright (C) 2004-2005 Pierre Ossman,
  14  *     All Rights Reserved.
  15  *     (drivers/mmc/pxa.c) Copyright (C) 2003 Russell King,
  16  *     All Rights Reserved.
  17  *
  18
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License version 2 as
  21  * published by the Free Software Foundation.
  22  */
  23
  24 /* Why is a timer used to detect insert events?
  25  *
  26  * From the AU1100 MMC application guide:
  27  * If the Au1100-based design is intended to support both MultiMediaCards
  28  * and 1- or 4-data bit SecureDigital cards, then the solution is to
  29  * connect a weak (560KOhm) pull-up resistor to connector pin 1.
  30  * In doing so, a MMC card never enters SPI-mode communications,
  31  * but now the SecureDigital card-detect feature of CD/DAT3 is ineffective
  32  * (the low to high transition will not occur).
  33  *
  34  * So we use the timer to check the status manually.
  35  */
  36
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/platform_device.h>
  40 #include <linux/mm.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/scatterlist.h>
  44 #include <linux/leds.h>
  45 #include <linux/mmc/host.h>
  46
  47 #include <asm/io.h>
  48 #include <asm/mach-au1x00/au1000.h>
  49 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  50 #include <asm/mach-au1x00/au1100_mmc.h>
  51
  52 #include <au1xxx.h>
  53 #include "au1xmmc.h"
  54
  55 #define DRIVER_NAME "au1xxx-mmc"
  56
  57 /* Set this to enable special debugging macros */
  58 /* #define DEBUG */
  59
  60 #ifdef DEBUG
  61 #define DBG(fmt, idx, args...) printk("au1xx(%d): DEBUG: " fmt, idx, ##args)
  62 #else
  63 #define DBG(fmt, idx, args...)
  64 #endif
  65
  66 static inline void IRQ_ON(struct au1xmmc_host *host, u32 mask)
  67 {
  68         u32 val = au_readl(HOST_CONFIG(host));
  69         val |= mask;
  70         au_writel(val, HOST_CONFIG(host));
  71         au_sync();
  72 }
  73
  74 static inline void FLUSH_FIFO(struct au1xmmc_host *host)
  75 {
  76         u32 val = au_readl(HOST_CONFIG2(host));
  77
  78         au_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host));
  79         au_sync_delay(1);
  80
  81         /* SEND_STOP will turn off clock control - this re-enables it */
  82         val &= ~SD_CONFIG2_DF;
  83
  84         au_writel(val, HOST_CONFIG2(host));
  85         au_sync();
  86 }
  87
  88 static inline void IRQ_OFF(struct au1xmmc_host *host, u32 mask)
  89 {
  90         u32 val = au_readl(HOST_CONFIG(host));
  91         val &= ~mask;
  92         au_writel(val, HOST_CONFIG(host));
  93         au_sync();
  94 }
  95
  96 static inline void SEND_STOP(struct au1xmmc_host *host)
  97 {
  98
  99         /* We know the value of CONFIG2, so avoid a read we don't need */
 100         u32 mask = SD_CONFIG2_EN;
 101
 102         WARN_ON(host->status != HOST_S_DATA);
 103         host->status = HOST_S_STOP;
 104
 105         au_writel(mask | SD_CONFIG2_DF, HOST_CONFIG2(host));
 106         au_sync();
 107
 108         /* Send the stop commmand */
 109         au_writel(STOP_CMD, HOST_CMD(host));
 110 }
 111
 112 static void au1xmmc_set_power(struct au1xmmc_host *host, int state)
 113 {
 114         if (host->platdata && host->platdata->set_power)
 115                 host->platdata->set_power(host->mmc, state);
 116 }
 117
 118 static int au1xmmc_card_inserted(struct au1xmmc_host *host)
 119 {
 120         int ret;
 121
 122         if (host->platdata && host->platdata->card_inserted)
 123                 ret = host->platdata->card_inserted(host->mmc);
 124         else
 125                 ret = 1;        /* assume there is a card */
 126
 127         return ret;
 128 }
 129
 130 static int au1xmmc_card_readonly(struct mmc_host *mmc)
 131 {
 132         struct au1xmmc_host *host = mmc_priv(mmc);
 133         int ret;
 134
 135         if (host->platdata && host->platdata->card_readonly)
 136                 ret = host->platdata->card_readonly(mmc);
 137         else
 138                 ret = 0;        /* assume card is read-write */
 139
 140         return ret;
 141 }
 142
 143 static void au1xmmc_finish_request(struct au1xmmc_host *host)
 144 {
 145
 146         struct mmc_request *mrq = host->mrq;
 147
 148         host->mrq = NULL;
 149         host->flags &= HOST_F_ACTIVE | HOST_F_DMA;
 150
 151         host->dma.len = 0;
 152         host->dma.dir = 0;
 153
 154         host->pio.index  = 0;
 155         host->pio.offset = 0;
 156         host->pio.len = 0;
 157
 158         host->status = HOST_S_IDLE;
 159
 160         mmc_request_done(host->mmc, mrq);
 161 }
 162
 163 static void au1xmmc_tasklet_finish(unsigned long param)
 164 {
 165         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 166         au1xmmc_finish_request(host);
 167 }
 168
 169 static int au1xmmc_send_command(struct au1xmmc_host *host, int wait,
 170                                 struct mmc_command *cmd, struct mmc_data *data)
 171 {
 172         u32 mmccmd = (cmd->opcode << SD_CMD_CI_SHIFT);
 173
 174         switch (mmc_resp_type(cmd)) {
 175         case MMC_RSP_NONE:
 176                 break;
 177         case MMC_RSP_R1:
 178                 mmccmd |= SD_CMD_RT_1;
 179                 break;
 180         case MMC_RSP_R1B:
 181                 mmccmd |= SD_CMD_RT_1B;
 182                 break;
 183         case MMC_RSP_R2:
 184                 mmccmd |= SD_CMD_RT_2;
 185                 break;
 186         case MMC_RSP_R3:
 187                 mmccmd |= SD_CMD_RT_3;
 188                 break;
 189         default:
 190                 printk(KERN_INFO "au1xmmc: unhandled response type %02x\n",
 191                         mmc_resp_type(cmd));
 192                 return -EINVAL;
 193         }
 194
 195         if (data) {
 196                 if (data->flags & MMC_DATA_READ) {
 197                         if (data->blocks > 1)
 198                                 mmccmd |= SD_CMD_CT_4;
 199                         else
 200                                 mmccmd |= SD_CMD_CT_2;
 201                 } else if (data->flags & MMC_DATA_WRITE) {
 202                         if (data->blocks > 1)
 203                                 mmccmd |= SD_CMD_CT_3;
 204                         else
 205                                 mmccmd |= SD_CMD_CT_1;
 206                 }
 207         }
 208
 209         au_writel(cmd->arg, HOST_CMDARG(host));
 210         au_sync();
 211
 212         if (wait)
 213                 IRQ_OFF(host, SD_CONFIG_CR);
 214
 215         au_writel((mmccmd | SD_CMD_GO), HOST_CMD(host));
 216         au_sync();
 217
 218         /* Wait for the command to go on the line */
 219
 220         while(1) {
 221                 if (!(au_readl(HOST_CMD(host)) & SD_CMD_GO))
 222                         break;
 223         }
 224
 225         /* Wait for the command to come back */
 226
 227         if (wait) {
 228                 u32 status = au_readl(HOST_STATUS(host));
 229
 230                 while(!(status & SD_STATUS_CR))
 231                         status = au_readl(HOST_STATUS(host));
 232
 233                 /* Clear the CR status */
 234                 au_writel(SD_STATUS_CR, HOST_STATUS(host));
 235
 236                 IRQ_ON(host, SD_CONFIG_CR);
 237         }
 238
 239         return 0;
 240 }
 241
 242 static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status)
 243 {
 244
 245         struct mmc_request *mrq = host->mrq;
 246         struct mmc_data *data;
 247         u32 crc;
 248
 249         WARN_ON(host->status != HOST_S_DATA && host->status != HOST_S_STOP);
 250
 251         if (host->mrq == NULL)
 252                 return;
 253
 254         data = mrq->cmd->data;
 255
 256         if (status == 0)
 257                 status = au_readl(HOST_STATUS(host));
 258
 259         /* The transaction is really over when the SD_STATUS_DB bit is clear */
 260
 261         while((host->flags & HOST_F_XMIT) && (status & SD_STATUS_DB))
 262                 status = au_readl(HOST_STATUS(host));
 263
 264         data->error = 0;
 265         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, host->dma.dir);
 266
 267         /* Process any errors */
 268
 269         crc = (status & (SD_STATUS_WC | SD_STATUS_RC));
 270         if (host->flags & HOST_F_XMIT)
 271                 crc |= ((status & 0x07) == 0x02) ? 0 : 1;
 272
 273         if (crc)
 274                 data->error = -EILSEQ;
 275
 276         /* Clear the CRC bits */
 277         au_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host));
 278
 279         data->bytes_xfered = 0;
 280
 281         if (!data->error) {
 282                 if (host->flags & HOST_F_DMA) {
 283 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 284                         u32 chan = DMA_CHANNEL(host);
 285
 286                         chan_tab_t *c = *((chan_tab_t **) chan);
 287                         au1x_dma_chan_t *cp = c->chan_ptr;
 288                         data->bytes_xfered = cp->ddma_bytecnt;
 289 #endif
 290                 }
 291                 else
 292                         data->bytes_xfered =
 293                                 (data->blocks * data->blksz) -
 294                                 host->pio.len;
 295         }
 296
 297         au1xmmc_finish_request(host);
 298 }
 299
 300 static void au1xmmc_tasklet_data(unsigned long param)
 301 {
 302         struct au1xmmc_host *host = (struct au1xmmc_host *) param;
 303
 304         u32 status = au_readl(HOST_STATUS(host));
 305         au1xmmc_data_complete(host, status);
 306 }
 307
 308 #define AU1XMMC_MAX_TRANSFER 8
 309
 310 static void au1xmmc_send_pio(struct au1xmmc_host *host)
 311 {
 312
 313         struct mmc_data *data = 0;
 314         int sg_len, max, count = 0;
 315         unsigned char *sg_ptr;
 316         u32 status = 0;
 317         struct scatterlist *sg;
 318
 319         data = host->mrq->data;
 320
 321         if (!(host->flags & HOST_F_XMIT))
 322                 return;
 323
 324         /* This is the pointer to the data buffer */
 325         sg = &data->sg[host->pio.index];
 326         sg_ptr = sg_virt(sg) + host->pio.offset;
 327
 328         /* This is the space left inside the buffer */
 329         sg_len = data->sg[host->pio.index].length - host->pio.offset;
 330
 331         /* Check to if we need less then the size of the sg_buffer */
 332
 333         max = (sg_len > host->pio.len) ? host->pio.len : sg_len;
 334         if (max > AU1XMMC_MAX_TRANSFER) max = AU1XMMC_MAX_TRANSFER;
 335
 336         for(count = 0; count < max; count++ ) {
 337                 unsigned char val;
 338
 339                 status = au_readl(HOST_STATUS(host));
 340
 341                 if (!(status & SD_STATUS_TH))
 342                         break;
 343
 344                 val = *sg_ptr++;
 345
 346                 au_writel((unsigned long) val, HOST_TXPORT(host));
 347                 au_sync();
 348         }
 349
 350         host->pio.len -= count;
 351         host->pio.offset += count;
 352
 353         if (count == sg_len) {
 354                 host->pio.index++;
 355                 host->pio.offset = 0;
 356         }
 357
 358         if (host->pio.len == 0) {
 359                 IRQ_OFF(host, SD_CONFIG_TH);
 360
 361                 if (host->flags & HOST_F_STOP)
 362                         SEND_STOP(host);
 363
 364                 tasklet_schedule(&host->data_task);
 365         }
 366 }
 367
 368 static void au1xmmc_receive_pio(struct au1xmmc_host *host)
 369 {
 370
 371         struct mmc_data *data = 0;
 372         int sg_len = 0, max = 0, count = 0;
 373         unsigned char *sg_ptr = 0;
 374         u32 status = 0;
 375         struct scatterlist *sg;
 376
 377         data = host->mrq->data;
 378
 379         if (!(host->flags & HOST_F_RECV))
 380                 return;
 381
 382         max = host->pio.len;
 383
 384         if (host->pio.index < host->dma.len) {
 385                 sg = &data->sg[host->pio.index];
 386                 sg_ptr = sg_virt(sg) + host->pio.offset;
 387
 388                 /* This is the space left inside the buffer */
 389                 sg_len = sg_dma_len(&data->sg[host->pio.index]) - host->pio.offset;
 390
 391                 /* Check to if we need less then the size of the sg_buffer */
 392                 if (sg_len < max) max = sg_len;
 393         }
 394
 395         if (max > AU1XMMC_MAX_TRANSFER)
 396                 max = AU1XMMC_MAX_TRANSFER;
 397
 398         for(count = 0; count < max; count++ ) {
 399                 u32 val;
 400                 status = au_readl(HOST_STATUS(host));
 401
 402                 if (!(status & SD_STATUS_NE))
 403                         break;
 404
 405                 if (status & SD_STATUS_RC) {
 406                         DBG("RX CRC Error [%d + %d].\n", host->pdev->id,
 407                                         host->pio.len, count);
 408                         break;
 409                 }
 410
 411                 if (status & SD_STATUS_RO) {
 412                         DBG("RX Overrun [%d + %d]\n", host->pdev->id,
 413                                         host->pio.len, count);
 414                         break;
 415                 }
 416                 else if (status & SD_STATUS_RU) {
 417                         DBG("RX Underrun [%d + %d]\n", host->pdev->id,
 418                                         host->pio.len,  count);
 419                         break;
 420                 }
 421
 422                 val = au_readl(HOST_RXPORT(host));
 423
 424                 if (sg_ptr)
 425                         *sg_ptr++ = (unsigned char) (val & 0xFF);
 426         }
 427
 428         host->pio.len -= count;
 429         host->pio.offset += count;
 430
 431         if (sg_len && count == sg_len) {
 432                 host->pio.index++;
 433                 host->pio.offset = 0;
 434         }
 435
 436         if (host->pio.len == 0) {
 437                 //IRQ_OFF(host, SD_CONFIG_RA | SD_CONFIG_RF);
 438                 IRQ_OFF(host, SD_CONFIG_NE);
 439
 440                 if (host->flags & HOST_F_STOP)
 441                         SEND_STOP(host);
 442
 443                 tasklet_schedule(&host->data_task);
 444         }
 445 }
 446
 447 /* static void au1xmmc_cmd_complete
 448    This is called when a command has been completed - grab the response
 449    and check for errors.  Then start the data transfer if it is indicated.
 450 */
 451
 452 static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status)
 453 {
 454
 455         struct mmc_request *mrq = host->mrq;
 456         struct mmc_command *cmd;
 457         int trans;
 458
 459         if (!host->mrq)
 460                 return;
 461
 462         cmd = mrq->cmd;
 463         cmd->error = 0;
 464
 465         if (cmd->flags & MMC_RSP_PRESENT) {
 466                 if (cmd->flags & MMC_RSP_136) {
 467                         u32 r[4];
 468                         int i;
 469
 470                         r[0] = au_readl(host->iobase + SD_RESP3);
 471                         r[1] = au_readl(host->iobase + SD_RESP2);
 472                         r[2] = au_readl(host->iobase + SD_RESP1);
 473                         r[3] = au_readl(host->iobase + SD_RESP0);
 474
 475                         /* The CRC is omitted from the response, so really
 476                          * we only got 120 bytes, but the engine expects
 477                          * 128 bits, so we have to shift things up
 478                          */
 479
 480                         for(i = 0; i < 4; i++) {
 481                                 cmd->resp[i] = (r[i] & 0x00FFFFFF) << 8;
 482                                 if (i != 3)
 483                                         cmd->resp[i] |= (r[i + 1] & 0xFF000000) >> 24;
 484                         }
 485                 } else {
 486                         /* Techincally, we should be getting all 48 bits of
 487                          * the response (SD_RESP1 + SD_RESP2), but because
 488                          * our response omits the CRC, our data ends up
 489                          * being shifted 8 bits to the right.  In this case,
 490                          * that means that the OSR data starts at bit 31,
 491                          * so we can just read RESP0 and return that
 492                          */
 493                         cmd->resp[0] = au_readl(host->iobase + SD_RESP0);
 494                 }
 495         }
 496
 497         /* Figure out errors */
 498
 499         if (status & (SD_STATUS_SC | SD_STATUS_WC | SD_STATUS_RC))
 500                 cmd->error = -EILSEQ;
 501
 502         trans = host->flags & (HOST_F_XMIT | HOST_F_RECV);
 503
 504         if (!trans || cmd->error) {
 505
 506                 IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA|SD_CONFIG_RF);
 507                 tasklet_schedule(&host->finish_task);
 508                 return;
 509         }
 510
 511         host->status = HOST_S_DATA;
 512
 513         if (host->flags & HOST_F_DMA) {
 514 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 515                 u32 channel = DMA_CHANNEL(host);
 516
 517                 /* Start the DMA as soon as the buffer gets something in it */
 518
 519                 if (host->flags & HOST_F_RECV) {
 520                         u32 mask = SD_STATUS_DB | SD_STATUS_NE;
 521
 522                         while((status & mask) != mask)
 523                                 status = au_readl(HOST_STATUS(host));
 524                 }
 525
 526                 au1xxx_dbdma_start(channel);
 527 #endif
 528         }
 529 }
 530
 531 static void au1xmmc_set_clock(struct au1xmmc_host *host, int rate)
 532 {
 533
 534         unsigned int pbus = get_au1x00_speed();
 535         unsigned int divisor;
 536         u32 config;
 537
 538         /* From databook:
 539            divisor = ((((cpuclock / sbus_divisor) / 2) / mmcclock) / 2) - 1
 540         */
 541
 542         pbus /= ((au_readl(SYS_POWERCTRL) & 0x3) + 2);
 543         pbus /= 2;
 544
 545         divisor = ((pbus / rate) / 2) - 1;
 546
 547         config = au_readl(HOST_CONFIG(host));
 548
 549         config &= ~(SD_CONFIG_DIV);
 550         config |= (divisor & SD_CONFIG_DIV) | SD_CONFIG_DE;
 551
 552         au_writel(config, HOST_CONFIG(host));
 553         au_sync();
 554 }
 555
 556 static int
 557 au1xmmc_prepare_data(struct au1xmmc_host *host, struct mmc_data *data)
 558 {
 559         int datalen = data->blocks * data->blksz;
 560
 561         if (data->flags & MMC_DATA_READ)
 562                 host->flags |= HOST_F_RECV;
 563         else
 564                 host->flags |= HOST_F_XMIT;
 565
 566         if (host->mrq->stop)
 567                 host->flags |= HOST_F_STOP;
 568
 569         host->dma.dir = DMA_BIDIRECTIONAL;
 570
 571         host->dma.len = dma_map_sg(mmc_dev(host->mmc), data->sg,
 572                                    data->sg_len, host->dma.dir);
 573
 574         if (host->dma.len == 0)
 575                 return -ETIMEDOUT;
 576
 577         au_writel(data->blksz - 1, HOST_BLKSIZE(host));
 578
 579         if (host->flags & HOST_F_DMA) {
 580 #ifdef CONFIG_SOC_AU1200        /* DBDMA */
 581                 int i;
 582                 u32 channel = DMA_CHANNEL(host);
 583
 584                 au1xxx_dbdma_stop(channel);
 585
 586                 for(i = 0; i < host->dma.len; i++) {
 587                         u32 ret = 0, flags = DDMA_FLAGS_NOIE;
 588                         struct scatterlist *sg = &data->sg[i];
 589                         int sg_len = sg->length;
 590
 591                         int len = (datalen > sg_len) ? sg_len : datalen;
 592
 593                         if (i == host->dma.len - 1)
 594                                 flags = DDMA_FLAGS_IE;
 595
 596                         if (host->flags & HOST_F_XMIT){
 597                                 ret = au1xxx_dbdma_put_source_flags(channel,
 598                                         (void *) sg_virt(sg), len, flags);
 599                         }
 600                         else {
 601                                 ret = au1xxx_dbdma_put_dest_flags(channel,
 602                                         (void *) sg_virt(sg),
 603                                         len, flags);
 604                         }
 605
 606                         if (!ret)
 607                                 goto dataerr;
 608
 609                         datalen -= len;
 610                 }
 611 #endif
 612         }
 613         else {
 614                 host->pio.index = 0;
 615                 host->pio.offset = 0;
 616                 host->pio.len = datalen;
 617
 618                 if (host->flags & HOST_F_XMIT)
 619                         IRQ_ON(host, SD_CONFIG_TH);
 620                 else
 621                         IRQ_ON(host, SD_CONFIG_NE);
 622                         //IRQ_ON(host, SD_CONFIG_RA|SD_CONFIG_RF);
 623         }
 624
 625         return 0;
 626
 627 dataerr:
 628         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
 629                         host->dma.dir);
 630         return -ETIMEDOUT;
 631 }
 632
 633 /* static void au1xmmc_request
 634    This actually starts a command or data transaction
 635 */
 636
 637 static void au1xmmc_request(struct mmc_host* mmc, struct mmc_request* mrq)
 638 {
 639
 640         struct au1xmmc_host *host = mmc_priv(mmc);
 641         unsigned int flags = 0;
 642         int ret = 0;
 643
 644         WARN_ON(irqs_disabled());
 645         WARN_ON(host->status != HOST_S_IDLE);
 646
 647         host->mrq = mrq;
 648         host->status = HOST_S_CMD;
 649
 650         if (mrq->data) {
 651                 FLUSH_FIFO(host);
 652                 flags = mrq->data->flags;
 653                 ret = au1xmmc_prepare_data(host, mrq->data);
 654         }
 655
 656         if (!ret)
 657                 ret = au1xmmc_send_command(host, 0, mrq->cmd, mrq->data);
 658
 659         if (ret) {
 660                 mrq->cmd->error = ret;
 661                 au1xmmc_finish_request(host);
 662         }
 663 }
 664
 665 static void au1xmmc_reset_controller(struct au1xmmc_host *host)
 666 {
 667
 668         /* Apply the clock */
 669         au_writel(SD_ENABLE_CE, HOST_ENABLE(host));
 670         au_sync_delay(1);
 671
 672         au_writel(SD_ENABLE_R | SD_ENABLE_CE, HOST_ENABLE(host));
 673         au_sync_delay(5);
 674
 675         au_writel(~0, HOST_STATUS(host));
 676         au_sync();
 677
 678         au_writel(0, HOST_BLKSIZE(host));
 679         au_writel(0x001fffff, HOST_TIMEOUT(host));
 680         au_sync();
 681
 682         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 683         au_sync();
 684
 685         au_writel(SD_CONFIG2_EN | SD_CONFIG2_FF, HOST_CONFIG2(host));
 686         au_sync_delay(1);
 687
 688         au_writel(SD_CONFIG2_EN, HOST_CONFIG2(host));
 689         au_sync();
 690
 691         /* Configure interrupts */
 692         au_writel(AU1XMMC_INTERRUPTS, HOST_CONFIG(host));
 693         au_sync();
 694 }
 695
 696
 697 static void au1xmmc_set_ios(struct mmc_host* mmc, struct mmc_ios* ios)
 698 {
 699         struct au1xmmc_host *host = mmc_priv(mmc);
 700
 701         if (ios->power_mode == MMC_POWER_OFF)
 702                 au1xmmc_set_power(host, 0);
 703         else if (ios->power_mode == MMC_POWER_ON) {
 704                 au1xmmc_set_power(host, 1);
 705         }
 706
 707         if (ios->clock && ios->clock != host->clock) {
 708                 au1xmmc_set_clock(host, ios->clock);
 709                 host->clock = ios->clock;
 710         }
 711 }
 712
 713 #define STATUS_TIMEOUT (SD_STATUS_RAT | SD_STATUS_DT)
 714 #define STATUS_DATA_IN  (SD_STATUS_NE)
 715 #define STATUS_DATA_OUT (SD_STATUS_TH)
 716
 717 static irqreturn_t au1xmmc_irq(int irq, void *dev_id)
 718 {
 719         struct au1xmmc_host *host = dev_id;
 720         u32 status;
 721
 722         status = au_readl(HOST_STATUS(host));
 723
 724         if (!(status & SD_STATUS_I))
 725                 return IRQ_NONE;        /* not ours */
 726
 727         if (host->mrq && (status & STATUS_TIMEOUT)) {
 728                 if (status & SD_STATUS_RAT)
 729                         host->mrq->cmd->error = -ETIMEDOUT;
 730                 else if (status & SD_STATUS_DT)
 731                         host->mrq->data->error = -ETIMEDOUT;
 732
 733                 /* In PIO mode, interrupts might still be enabled */
 734                 IRQ_OFF(host, SD_CONFIG_NE | SD_CONFIG_TH);
 735
 736                 /* IRQ_OFF(host, SD_CONFIG_TH | SD_CONFIG_RA | SD_CONFIG_RF); */
 737                 tasklet_schedule(&host->finish_task);
 738         }
 739 #if 0
 740         else if (status & SD_STATUS_DD) {
 741                 /* Sometimes we get a DD before a NE in PIO mode */
 742                 if (!(host->flags & HOST_F_DMA) && (status & SD_STATUS_NE))
 743                         au1xmmc_receive_pio(host);
 744                 else {
 745                         au1xmmc_data_complete(host, status);
 746                         /* tasklet_schedule(&host->data_task); */
 747                 }
 748         }
 749 #endif
 750         else if (status & SD_STATUS_CR) {
 751                 if (host->status == HOST_S_CMD)
 752                         au1xmmc_cmd_complete(host, status);
 753
 754         } else if (!(host->flags & HOST_F_DMA)) {
 755                 if ((host->flags & HOST_F_XMIT) && (status & STATUS_DATA_OUT))
 756                         au1xmmc_send_pio(host);
 757                 else if ((host->flags & HOST_F_RECV) && (status & STATUS_DATA_IN))
 758                         au1xmmc_receive_pio(host);
 759
 760         } else if (status & 0x203F3C70) {
 761                         DBG("Unhandled status %8.8x\n", host->pdev->id,
 762                                 status);
 763         }
 764
 765         au_writel(status, HOST_STATUS(host));
 766         au_sync();
 767
 768         return IRQ_HANDLED;
 769 }
 770
 771 #ifdef CONFIG_SOC_AU1200
 772 /* 8bit memory DMA device */
 773 static dbdev_tab_t au1xmmc_mem_dbdev = {
 774         .dev_id         = DSCR_CMD0_ALWAYS,
 775         .dev_flags      = DEV_FLAGS_ANYUSE,
 776         .dev_tsize      = 0,
 777         .dev_devwidth   = 8,
 778         .dev_physaddr   = 0x00000000,
 779         .dev_intlevel   = 0,
 780         .dev_intpolarity = 0,
 781 };
 782 static int memid;
 783
 784 static void au1xmmc_dbdma_callback(int irq, void *dev_id)
 785 {
 786         struct au1xmmc_host *host = (struct au1xmmc_host *)dev_id;
 787
 788         /* Avoid spurious interrupts */
 789         if (!host->mrq)
 790                 return;
 791
 792         if (host->flags & HOST_F_STOP)
 793                 SEND_STOP(host);
 794
 795         tasklet_schedule(&host->data_task);
 796 }
 797
 798 static int au1xmmc_dbdma_init(struct au1xmmc_host *host)
 799 {
 800         struct resource *res;
 801         int txid, rxid;
 802
 803         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 0);
 804         if (!res)
 805                 return -ENODEV;
 806         txid = res->start;
 807
 808         res = platform_get_resource(host->pdev, IORESOURCE_DMA, 1);
 809         if (!res)
 810                 return -ENODEV;
 811         rxid = res->start;
 812
 813         if (!memid)
 814                 return -ENODEV;
 815
 816         host->tx_chan = au1xxx_dbdma_chan_alloc(memid, txid,
 817                                 au1xmmc_dbdma_callback, (void *)host);
 818         if (!host->tx_chan) {
 819                 dev_err(&host->pdev->dev, "cannot allocate TX DMA\n");
 820                 return -ENODEV;
 821         }
 822
 823         host->rx_chan = au1xxx_dbdma_chan_alloc(rxid, memid,
 824                                 au1xmmc_dbdma_callback, (void *)host);
 825         if (!host->rx_chan) {
 826                 dev_err(&host->pdev->dev, "cannot allocate RX DMA\n");
 827                 au1xxx_dbdma_chan_free(host->tx_chan);
 828                 return -ENODEV;
 829         }
 830
 831         au1xxx_dbdma_set_devwidth(host->tx_chan, 8);
 832         au1xxx_dbdma_set_devwidth(host->rx_chan, 8);
 833
 834         au1xxx_dbdma_ring_alloc(host->tx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 835         au1xxx_dbdma_ring_alloc(host->rx_chan, AU1XMMC_DESCRIPTOR_COUNT);
 836
 837         /* DBDMA is good to go */
 838         host->flags |= HOST_F_DMA;
 839
 840         return 0;
 841 }
 842
 843 static void au1xmmc_dbdma_shutdown(struct au1xmmc_host *host)
 844 {
 845         if (host->flags & HOST_F_DMA) {
 846                 host->flags &= ~HOST_F_DMA;
 847                 au1xxx_dbdma_chan_free(host->tx_chan);
 848                 au1xxx_dbdma_chan_free(host->rx_chan);
 849         }
 850 }
 851 #endif
 852
 853 static const struct mmc_host_ops au1xmmc_ops = {
 854         .request        = au1xmmc_request,
 855         .set_ios        = au1xmmc_set_ios,
 856         .get_ro         = au1xmmc_card_readonly,
 857 };
 858
 859 static void au1xmmc_poll_event(unsigned long arg)
 860 {
 861         struct au1xmmc_host *host = (struct au1xmmc_host *)arg;
 862         int card = au1xmmc_card_inserted(host);
 863         int controller = (host->flags & HOST_F_ACTIVE) ? 1 : 0;
 864
 865         if (card != controller) {
 866                 host->flags &= ~HOST_F_ACTIVE;
 867                 if (card)
 868                         host->flags |= HOST_F_ACTIVE;
 869                 mmc_detect_change(host->mmc, 0);
 870         }
 871
 872 #ifdef DEBUG
 873         if (host->mrq != NULL) {
 874                 u32 status = au_readl(HOST_STATUS(host));
 875                 DBG("PENDING - %8.8x\n", host->pdev->id, status);
 876         }
 877 #endif
 878         mod_timer(&host->timer, jiffies + AU1XMMC_DETECT_TIMEOUT);
 879 }
 880
 881 static void au1xmmc_init_cd_poll_timer(struct au1xmmc_host *host)
 882 {
 883         init_timer(&host->timer);
 884         host->timer.function = au1xmmc_poll_event;
 885         host->timer.data = (unsigned long)host;
 886         host->timer.expires = jiffies + AU1XMMC_DETECT_TIMEOUT;
 887 }
 888
 889 static int __devinit au1xmmc_probe(struct platform_device *pdev)
 890 {
 891         struct mmc_host *mmc;
 892         struct au1xmmc_host *host;
 893         struct resource *r;
 894         int ret;
 895
 896         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
 897         if (!mmc) {
 898                 dev_err(&pdev->dev, "no memory for mmc_host\n");
 899                 ret = -ENOMEM;
 900                 goto out0;
 901         }
 902
 903         host = mmc_priv(mmc);
 904         host->mmc = mmc;
 905         host->platdata = pdev->dev.platform_data;
 906         host->pdev = pdev;
 907
 908         ret = -ENODEV;
 909         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 910         if (!r) {
 911                 dev_err(&pdev->dev, "no mmio defined\n");
 912                 goto out1;
 913         }
 914
 915         host->ioarea = request_mem_region(r->start, r->end - r->start + 1,
 916                                            pdev->name);
 917         if (!host->ioarea) {
 918                 dev_err(&pdev->dev, "mmio already in use\n");
 919                 goto out1;
 920         }
 921
 922         host->iobase = (unsigned long)ioremap(r->start, 0x3c);
 923         if (!host->iobase) {
 924                 dev_err(&pdev->dev, "cannot remap mmio\n");
 925                 goto out2;
 926         }
 927
 928         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 929         if (!r) {
 930                 dev_err(&pdev->dev, "no IRQ defined\n");
 931                 goto out3;
 932         }
 933
 934         host->irq = r->start;
 935         /* IRQ is shared among both SD controllers */
 936         ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
 937                           DRIVER_NAME, host);
 938         if (ret) {
 939                 dev_err(&pdev->dev, "cannot grab IRQ\n");
 940                 goto out3;
 941         }
 942
 943         mmc->ops = &au1xmmc_ops;
 944
 945         mmc->f_min =   450000;
 946         mmc->f_max = 24000000;
 947
 948         mmc->max_seg_size = AU1XMMC_DESCRIPTOR_SIZE;
 949         mmc->max_phys_segs = AU1XMMC_DESCRIPTOR_COUNT;
 950
 951         mmc->max_blk_size = 2048;
 952         mmc->max_blk_count = 512;
 953
 954         mmc->ocr_avail = AU1XMMC_OCR;
 955         mmc->caps = 0;
 956
 957         host->status = HOST_S_IDLE;
 958
 959         /* board-specific carddetect setup, if any */
 960         if (host->platdata && host->platdata->cd_setup) {
 961                 ret = host->platdata->cd_setup(mmc, 1);
 962                 if (ret) {
 963                         dev_err(&pdev->dev, "board CD setup failed\n");
 964                         goto out4;
 965                 }
 966         } else {
 967                 /* poll the board-specific is-card-in-socket-? method */
 968                 au1xmmc_init_cd_poll_timer(host);
 969         }
 970
 971         tasklet_init(&host->data_task, au1xmmc_tasklet_data,
 972                         (unsigned long)host);
 973
 974         tasklet_init(&host->finish_task, au1xmmc_tasklet_finish,
 975                         (unsigned long)host);
 976
 977 #ifdef CONFIG_SOC_AU1200
 978         ret = au1xmmc_dbdma_init(host);
 979         if (ret)
 980                 printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n");
 981 #endif
 982
 983 #ifdef CONFIG_LEDS_CLASS
 984         if (host->platdata && host->platdata->led) {
 985                 struct led_classdev *led = host->platdata->led;
 986                 led->name = mmc_hostname(mmc);
 987                 led->brightness = LED_OFF;
 988                 led->default_trigger = mmc_hostname(mmc);
 989                 ret = led_classdev_register(mmc_dev(mmc), led);
 990                 if (ret)
 991                         goto out5;
 992         }
 993 #endif
 994
 995         au1xmmc_reset_controller(host);
 996
 997         ret = mmc_add_host(mmc);
 998         if (ret) {
 999                 dev_err(&pdev->dev, "cannot add mmc host\n");
1000                 goto out6;
1001         }
1002
1003         platform_set_drvdata(pdev, mmc);
1004
1005         /* start the carddetect poll timer if necessary */
1006         if (!(host->platdata && host->platdata->cd_setup))
1007                 add_timer(&host->timer);
1008
1009         printk(KERN_INFO DRIVER_NAME ": MMC Controller %d set up at %8.8X"
1010                 " (mode=%s)\n", pdev->id, host->iobase,
1011                 host->flags & HOST_F_DMA ? "dma" : "pio");
1012
1013         return 0;       /* all ok */
1014
1015 out6:
1016 #ifdef CONFIG_LEDS_CLASS
1017         if (host->platdata && host->platdata->led)
1018                 led_classdev_unregister(host->platdata->led);
1019 out5:
1020 #endif
1021         au_writel(0, HOST_ENABLE(host));
1022         au_writel(0, HOST_CONFIG(host));
1023         au_writel(0, HOST_CONFIG2(host));
1024         au_sync();
1025
1026 #ifdef CONFIG_SOC_AU1200
1027         au1xmmc_dbdma_shutdown(host);
1028 #endif
1029
1030         tasklet_kill(&host->data_task);
1031         tasklet_kill(&host->finish_task);
1032
1033         if (host->platdata && host->platdata->cd_setup)
1034                 host->platdata->cd_setup(mmc, 0);
1035 out4:
1036         free_irq(host->irq, host);
1037 out3:
1038         iounmap((void *)host->iobase);
1039 out2:
1040         release_resource(host->ioarea);
1041         kfree(host->ioarea);
1042 out1:
1043         mmc_free_host(mmc);
1044 out0:
1045         return ret;
1046 }
1047
1048 static int __devexit au1xmmc_remove(struct platform_device *pdev)
1049 {
1050         struct mmc_host *mmc = platform_get_drvdata(pdev);
1051         struct au1xmmc_host *host;
1052
1053         if (mmc) {
1054                 host  = mmc_priv(mmc);
1055
1056                 mmc_remove_host(mmc);
1057
1058 #ifdef CONFIG_LEDS_CLASS
1059                 if (host->platdata && host->platdata->led)
1060                         led_classdev_unregister(host->platdata->led);
1061 #endif
1062
1063                 if (host->platdata && host->platdata->cd_setup)
1064                         host->platdata->cd_setup(mmc, 0);
1065                 else
1066                         del_timer_sync(&host->timer);
1067
1068                 au_writel(0, HOST_ENABLE(host));
1069                 au_writel(0, HOST_CONFIG(host));
1070                 au_writel(0, HOST_CONFIG2(host));
1071                 au_sync();
1072
1073                 tasklet_kill(&host->data_task);
1074                 tasklet_kill(&host->finish_task);
1075
1076 #ifdef CONFIG_SOC_AU1200
1077                 au1xmmc_dbdma_shutdown(host);
1078 #endif
1079                 au1xmmc_set_power(host, 0);
1080
1081                 free_irq(host->irq, host);
1082                 iounmap((void *)host->iobase);
1083                 release_resource(host->ioarea);
1084                 kfree(host->ioarea);
1085
1086                 mmc_free_host(mmc);
1087         }
1088         return 0;
1089 }
1090
1091 static struct platform_driver au1xmmc_driver = {
1092         .probe         = au1xmmc_probe,
1093         .remove        = au1xmmc_remove,
1094         .suspend       = NULL,
1095         .resume        = NULL,
1096         .driver        = {
1097                 .name  = DRIVER_NAME,
1098                 .owner = THIS_MODULE,
1099         },
1100 };
1101
1102 static int __init au1xmmc_init(void)
1103 {
1104 #ifdef CONFIG_SOC_AU1200
1105         /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride
1106          * of 8 bits.  And since devices are shared, we need to create
1107          * our own to avoid freaking out other devices.
1108          */
1109         memid = au1xxx_ddma_add_device(&au1xmmc_mem_dbdev);
1110         if (!memid)
1111                 printk(KERN_ERR "au1xmmc: cannot add memory dbdma dev\n");
1112 #endif
1113         return platform_driver_register(&au1xmmc_driver);
1114 }
1115
1116 static void __exit au1xmmc_exit(void)
1117 {
1118 #ifdef CONFIG_SOC_AU1200
1119         if (memid)
1120                 au1xxx_ddma_del_device(memid);
1121 #endif
1122         platform_driver_unregister(&au1xmmc_driver);
1123 }
1124
1125 module_init(au1xmmc_init);
1126 module_exit(au1xmmc_exit);
1127
1128 MODULE_AUTHOR("Advanced Micro Devices, Inc");
1129 MODULE_DESCRIPTION("MMC/SD driver for the Alchemy Au1XXX");
1130 MODULE_LICENSE("GPL");
1131 MODULE_ALIAS("platform:au1xxx-mmc");