drivers/mfd/db8500-prcmu.c

   1 /*
   2  * Copyright (C) STMicroelectronics 2009
   3  * Copyright (C) ST-Ericsson SA 2010
   4  *
   5  * License Terms: GNU General Public License v2
   6  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   7  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
   8  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
   9  *
  10  * U8500 PRCM Unit interface driver
  11  *
  12  */
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/io.h>
  20 #include <linux/slab.h>
  21 #include <linux/mutex.h>
  22 #include <linux/completion.h>
  23 #include <linux/irq.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/bitops.h>
  26 #include <linux/fs.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/irqchip/arm-gic.h>
  30 #include <linux/mfd/core.h>
  31 #include <linux/mfd/dbx500-prcmu.h>
  32 #include <linux/mfd/abx500/ab8500.h>
  33 #include <linux/regulator/db8500-prcmu.h>
  34 #include <linux/regulator/machine.h>
  35 #include <linux/cpufreq.h>
  36 #include <mach/hardware.h>
  37 #include <mach/irqs.h>
  38 #include <mach/db8500-regs.h>
  39 #include "dbx500-prcmu-regs.h"
  40
  41 /* Offset for the firmware version within the TCPM */
  42 #define PRCMU_FW_VERSION_OFFSET 0xA4
  43
  44 /* Index of different voltages to be used when accessing AVSData */
  45 #define PRCM_AVS_BASE           0x2FC
  46 #define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
  47 #define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
  48 #define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
  49 #define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
  50 #define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
  51 #define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
  52 #define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
  53 #define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
  54 #define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
  55 #define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
  56 #define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
  57 #define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
  58 #define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
  59
  60 #define PRCM_AVS_VOLTAGE                0
  61 #define PRCM_AVS_VOLTAGE_MASK           0x3f
  62 #define PRCM_AVS_ISSLOWSTARTUP          6
  63 #define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
  64 #define PRCM_AVS_ISMODEENABLE           7
  65 #define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
  66
  67 #define PRCM_BOOT_STATUS        0xFFF
  68 #define PRCM_ROMCODE_A2P        0xFFE
  69 #define PRCM_ROMCODE_P2A        0xFFD
  70 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
  71
  72 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  73
  74 #define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
  75 #define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
  76 #define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
  77 #define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
  78 #define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
  79 #define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
  80 #define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
  81 #define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
  82
  83 /* Req Mailboxes */
  84 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
  85 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
  86 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
  87 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
  88 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
  89 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
  90
  91 /* Ack Mailboxes */
  92 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
  93 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  94 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  95 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  96 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
  97 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
  98
  99 /* Mailbox 0 headers */
 100 #define MB0H_POWER_STATE_TRANS          0
 101 #define MB0H_CONFIG_WAKEUPS_EXE         1
 102 #define MB0H_READ_WAKEUP_ACK            3
 103 #define MB0H_CONFIG_WAKEUPS_SLEEP       4
 104
 105 #define MB0H_WAKEUP_EXE 2
 106 #define MB0H_WAKEUP_SLEEP 5
 107
 108 /* Mailbox 0 REQs */
 109 #define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
 110 #define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
 111 #define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
 112 #define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
 113 #define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
 114 #define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
 115
 116 /* Mailbox 0 ACKs */
 117 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
 118 #define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
 119 #define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
 120 #define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
 121 #define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
 122 #define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
 123 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
 124
 125 /* Mailbox 1 headers */
 126 #define MB1H_ARM_APE_OPP 0x0
 127 #define MB1H_RESET_MODEM 0x2
 128 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
 129 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
 130 #define MB1H_RELEASE_USB_WAKEUP 0x5
 131 #define MB1H_PLL_ON_OFF 0x6
 132
 133 /* Mailbox 1 Requests */
 134 #define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
 135 #define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
 136 #define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
 137 #define PLL_SOC0_OFF    0x1
 138 #define PLL_SOC0_ON     0x2
 139 #define PLL_SOC1_OFF    0x4
 140 #define PLL_SOC1_ON     0x8
 141
 142 /* Mailbox 1 ACKs */
 143 #define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
 144 #define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
 145 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
 146 #define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
 147
 148 /* Mailbox 2 headers */
 149 #define MB2H_DPS        0x0
 150 #define MB2H_AUTO_PWR   0x1
 151
 152 /* Mailbox 2 REQs */
 153 #define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
 154 #define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
 155 #define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
 156 #define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
 157 #define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
 158 #define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
 159 #define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
 160 #define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
 161 #define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
 162 #define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
 163
 164 /* Mailbox 2 ACKs */
 165 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
 166 #define HWACC_PWR_ST_OK 0xFE
 167
 168 /* Mailbox 3 headers */
 169 #define MB3H_ANC        0x0
 170 #define MB3H_SIDETONE   0x1
 171 #define MB3H_SYSCLK     0xE
 172
 173 /* Mailbox 3 Requests */
 174 #define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
 175 #define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
 176 #define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
 177 #define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
 178 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
 179 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
 180 #define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
 181
 182 /* Mailbox 4 headers */
 183 #define MB4H_DDR_INIT   0x0
 184 #define MB4H_MEM_ST     0x1
 185 #define MB4H_HOTDOG     0x12
 186 #define MB4H_HOTMON     0x13
 187 #define MB4H_HOT_PERIOD 0x14
 188 #define MB4H_A9WDOG_CONF 0x16
 189 #define MB4H_A9WDOG_EN   0x17
 190 #define MB4H_A9WDOG_DIS  0x18
 191 #define MB4H_A9WDOG_LOAD 0x19
 192 #define MB4H_A9WDOG_KICK 0x20
 193
 194 /* Mailbox 4 Requests */
 195 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
 196 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
 197 #define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
 198 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
 199 #define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
 200 #define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
 201 #define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
 202 #define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
 203 #define HOTMON_CONFIG_LOW                       BIT(0)
 204 #define HOTMON_CONFIG_HIGH                      BIT(1)
 205 #define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
 206 #define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
 207 #define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
 208 #define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
 209 #define A9WDOG_AUTO_OFF_EN                      BIT(7)
 210 #define A9WDOG_AUTO_OFF_DIS                     0
 211 #define A9WDOG_ID_MASK                          0xf
 212
 213 /* Mailbox 5 Requests */
 214 #define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
 215 #define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
 216 #define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
 217 #define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
 218 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
 219 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
 220 #define PRCMU_I2C_STOP_EN               BIT(3)
 221
 222 /* Mailbox 5 ACKs */
 223 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
 224 #define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
 225 #define I2C_WR_OK 0x1
 226 #define I2C_RD_OK 0x2
 227
 228 #define NUM_MB 8
 229 #define MBOX_BIT BIT
 230 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
 231
 232 /*
 233  * Wakeups/IRQs
 234  */
 235
 236 #define WAKEUP_BIT_RTC BIT(0)
 237 #define WAKEUP_BIT_RTT0 BIT(1)
 238 #define WAKEUP_BIT_RTT1 BIT(2)
 239 #define WAKEUP_BIT_HSI0 BIT(3)
 240 #define WAKEUP_BIT_HSI1 BIT(4)
 241 #define WAKEUP_BIT_CA_WAKE BIT(5)
 242 #define WAKEUP_BIT_USB BIT(6)
 243 #define WAKEUP_BIT_ABB BIT(7)
 244 #define WAKEUP_BIT_ABB_FIFO BIT(8)
 245 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
 246 #define WAKEUP_BIT_CA_SLEEP BIT(10)
 247 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
 248 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
 249 #define WAKEUP_BIT_ANC_OK BIT(13)
 250 #define WAKEUP_BIT_SW_ERROR BIT(14)
 251 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
 252 #define WAKEUP_BIT_ARM BIT(17)
 253 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
 254 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
 255 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
 256 #define WAKEUP_BIT_GPIO0 BIT(23)
 257 #define WAKEUP_BIT_GPIO1 BIT(24)
 258 #define WAKEUP_BIT_GPIO2 BIT(25)
 259 #define WAKEUP_BIT_GPIO3 BIT(26)
 260 #define WAKEUP_BIT_GPIO4 BIT(27)
 261 #define WAKEUP_BIT_GPIO5 BIT(28)
 262 #define WAKEUP_BIT_GPIO6 BIT(29)
 263 #define WAKEUP_BIT_GPIO7 BIT(30)
 264 #define WAKEUP_BIT_GPIO8 BIT(31)
 265
 266 static struct {
 267         bool valid;
 268         struct prcmu_fw_version version;
 269 } fw_info;
 270
 271 static struct irq_domain *db8500_irq_domain;
 272
 273 /*
 274  * This vector maps irq numbers to the bits in the bit field used in
 275  * communication with the PRCMU firmware.
 276  *
 277  * The reason for having this is to keep the irq numbers contiguous even though
 278  * the bits in the bit field are not. (The bits also have a tendency to move
 279  * around, to further complicate matters.)
 280  */
 281 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
 282 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
 283 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
 284         IRQ_ENTRY(RTC),
 285         IRQ_ENTRY(RTT0),
 286         IRQ_ENTRY(RTT1),
 287         IRQ_ENTRY(HSI0),
 288         IRQ_ENTRY(HSI1),
 289         IRQ_ENTRY(CA_WAKE),
 290         IRQ_ENTRY(USB),
 291         IRQ_ENTRY(ABB),
 292         IRQ_ENTRY(ABB_FIFO),
 293         IRQ_ENTRY(CA_SLEEP),
 294         IRQ_ENTRY(ARM),
 295         IRQ_ENTRY(HOTMON_LOW),
 296         IRQ_ENTRY(HOTMON_HIGH),
 297         IRQ_ENTRY(MODEM_SW_RESET_REQ),
 298         IRQ_ENTRY(GPIO0),
 299         IRQ_ENTRY(GPIO1),
 300         IRQ_ENTRY(GPIO2),
 301         IRQ_ENTRY(GPIO3),
 302         IRQ_ENTRY(GPIO4),
 303         IRQ_ENTRY(GPIO5),
 304         IRQ_ENTRY(GPIO6),
 305         IRQ_ENTRY(GPIO7),
 306         IRQ_ENTRY(GPIO8)
 307 };
 308
 309 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
 310 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
 311 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
 312         WAKEUP_ENTRY(RTC),
 313         WAKEUP_ENTRY(RTT0),
 314         WAKEUP_ENTRY(RTT1),
 315         WAKEUP_ENTRY(HSI0),
 316         WAKEUP_ENTRY(HSI1),
 317         WAKEUP_ENTRY(USB),
 318         WAKEUP_ENTRY(ABB),
 319         WAKEUP_ENTRY(ABB_FIFO),
 320         WAKEUP_ENTRY(ARM)
 321 };
 322
 323 /*
 324  * mb0_transfer - state needed for mailbox 0 communication.
 325  * @lock:               The transaction lock.
 326  * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
 327  *                      the request data.
 328  * @mask_work:          Work structure used for (un)masking wakeup interrupts.
 329  * @req:                Request data that need to persist between requests.
 330  */
 331 static struct {
 332         spinlock_t lock;
 333         spinlock_t dbb_irqs_lock;
 334         struct work_struct mask_work;
 335         struct mutex ac_wake_lock;
 336         struct completion ac_wake_work;
 337         struct {
 338                 u32 dbb_irqs;
 339                 u32 dbb_wakeups;
 340                 u32 abb_events;
 341         } req;
 342 } mb0_transfer;
 343
 344 /*
 345  * mb1_transfer - state needed for mailbox 1 communication.
 346  * @lock:       The transaction lock.
 347  * @work:       The transaction completion structure.
 348  * @ape_opp:    The current APE OPP.
 349  * @ack:        Reply ("acknowledge") data.
 350  */
 351 static struct {
 352         struct mutex lock;
 353         struct completion work;
 354         u8 ape_opp;
 355         struct {
 356                 u8 header;
 357                 u8 arm_opp;
 358                 u8 ape_opp;
 359                 u8 ape_voltage_status;
 360         } ack;
 361 } mb1_transfer;
 362
 363 /*
 364  * mb2_transfer - state needed for mailbox 2 communication.
 365  * @lock:            The transaction lock.
 366  * @work:            The transaction completion structure.
 367  * @auto_pm_lock:    The autonomous power management configuration lock.
 368  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
 369  * @req:             Request data that need to persist between requests.
 370  * @ack:             Reply ("acknowledge") data.
 371  */
 372 static struct {
 373         struct mutex lock;
 374         struct completion work;
 375         spinlock_t auto_pm_lock;
 376         bool auto_pm_enabled;
 377         struct {
 378                 u8 status;
 379         } ack;
 380 } mb2_transfer;
 381
 382 /*
 383  * mb3_transfer - state needed for mailbox 3 communication.
 384  * @lock:               The request lock.
 385  * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
 386  * @sysclk_work:        Work structure used for sysclk requests.
 387  */
 388 static struct {
 389         spinlock_t lock;
 390         struct mutex sysclk_lock;
 391         struct completion sysclk_work;
 392 } mb3_transfer;
 393
 394 /*
 395  * mb4_transfer - state needed for mailbox 4 communication.
 396  * @lock:       The transaction lock.
 397  * @work:       The transaction completion structure.
 398  */
 399 static struct {
 400         struct mutex lock;
 401         struct completion work;
 402 } mb4_transfer;
 403
 404 /*
 405  * mb5_transfer - state needed for mailbox 5 communication.
 406  * @lock:       The transaction lock.
 407  * @work:       The transaction completion structure.
 408  * @ack:        Reply ("acknowledge") data.
 409  */
 410 static struct {
 411         struct mutex lock;
 412         struct completion work;
 413         struct {
 414                 u8 status;
 415                 u8 value;
 416         } ack;
 417 } mb5_transfer;
 418
 419 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 420
 421 /* Spinlocks */
 422 static DEFINE_SPINLOCK(prcmu_lock);
 423 static DEFINE_SPINLOCK(clkout_lock);
 424
 425 /* Global var to runtime determine TCDM base for v2 or v1 */
 426 static __iomem void *tcdm_base;
 427
 428 struct clk_mgt {
 429         void __iomem *reg;
 430         u32 pllsw;
 431         int branch;
 432         bool clk38div;
 433 };
 434
 435 enum {
 436         PLL_RAW,
 437         PLL_FIX,
 438         PLL_DIV
 439 };
 440
 441 static DEFINE_SPINLOCK(clk_mgt_lock);
 442
 443 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
 444         { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
 445 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 446         CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
 447         CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
 448         CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
 449         CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
 450         CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
 451         CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
 452         CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
 453         CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
 454         CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
 455         CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
 456         CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
 457         CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
 458         CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
 459         CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
 460         CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
 461         CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
 462         CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
 463         CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
 464         CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
 465         CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
 466         CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
 467         CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
 468         CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
 469         CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
 470         CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
 471         CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
 472         CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
 473         CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
 474         CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
 475 };
 476
 477 struct dsiclk {
 478         u32 divsel_mask;
 479         u32 divsel_shift;
 480         u32 divsel;
 481 };
 482
 483 static struct dsiclk dsiclk[2] = {
 484         {
 485                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
 486                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
 487                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 488         },
 489         {
 490                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
 491                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
 492                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 493         }
 494 };
 495
 496 struct dsiescclk {
 497         u32 en;
 498         u32 div_mask;
 499         u32 div_shift;
 500 };
 501
 502 static struct dsiescclk dsiescclk[3] = {
 503         {
 504                 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
 505                 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
 506                 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
 507         },
 508         {
 509                 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
 510                 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
 511                 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
 512         },
 513         {
 514                 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
 515                 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
 516                 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
 517         }
 518 };
 519
 520
 521 /*
 522 * Used by MCDE to setup all necessary PRCMU registers
 523 */
 524 #define PRCMU_RESET_DSIPLL              0x00004000
 525 #define PRCMU_UNCLAMP_DSIPLL            0x00400800
 526
 527 #define PRCMU_CLK_PLL_DIV_SHIFT         0
 528 #define PRCMU_CLK_PLL_SW_SHIFT          5
 529 #define PRCMU_CLK_38                    (1 << 9)
 530 #define PRCMU_CLK_38_SRC                (1 << 10)
 531 #define PRCMU_CLK_38_DIV                (1 << 11)
 532
 533 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
 534 #define PRCMU_DSI_CLOCK_SETTING         0x0000008C
 535
 536 /* DPI 50000000 Hz */
 537 #define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 538                                           (16 << PRCMU_CLK_PLL_DIV_SHIFT))
 539 #define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
 540
 541 /* D=101, N=1, R=4, SELDIV2=0 */
 542 #define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
 543
 544 #define PRCMU_ENABLE_PLLDSI             0x00000001
 545 #define PRCMU_DISABLE_PLLDSI            0x00000000
 546 #define PRCMU_RELEASE_RESET_DSS         0x0000400C
 547 #define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
 548 /* ESC clk, div0=1, div1=1, div2=3 */
 549 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
 550 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
 551 #define PRCMU_DSI_RESET_SW              0x00000007
 552
 553 #define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
 554
 555 int db8500_prcmu_enable_dsipll(void)
 556 {
 557         int i;
 558
 559         /* Clear DSIPLL_RESETN */
 560         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
 561         /* Unclamp DSIPLL in/out */
 562         writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
 563
 564         /* Set DSI PLL FREQ */
 565         writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
 566         writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
 567         /* Enable Escape clocks */
 568         writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 569
 570         /* Start DSI PLL */
 571         writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 572         /* Reset DSI PLL */
 573         writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
 574         for (i = 0; i < 10; i++) {
 575                 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
 576                                         == PRCMU_PLLDSI_LOCKP_LOCKED)
 577                         break;
 578                 udelay(100);
 579         }
 580         /* Set DSIPLL_RESETN */
 581         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
 582         return 0;
 583 }
 584
 585 int db8500_prcmu_disable_dsipll(void)
 586 {
 587         /* Disable dsi pll */
 588         writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 589         /* Disable  escapeclock */
 590         writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 591         return 0;
 592 }
 593
 594 int db8500_prcmu_set_display_clocks(void)
 595 {
 596         unsigned long flags;
 597
 598         spin_lock_irqsave(&clk_mgt_lock, flags);
 599
 600         /* Grab the HW semaphore. */
 601         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 602                 cpu_relax();
 603
 604         writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
 605         writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
 606         writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
 607
 608         /* Release the HW semaphore. */
 609         writel(0, PRCM_SEM);
 610
 611         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 612
 613         return 0;
 614 }
 615
 616 u32 db8500_prcmu_read(unsigned int reg)
 617 {
 618         return readl(_PRCMU_BASE + reg);
 619 }
 620
 621 void db8500_prcmu_write(unsigned int reg, u32 value)
 622 {
 623         unsigned long flags;
 624
 625         spin_lock_irqsave(&prcmu_lock, flags);
 626         writel(value, (_PRCMU_BASE + reg));
 627         spin_unlock_irqrestore(&prcmu_lock, flags);
 628 }
 629
 630 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 631 {
 632         u32 val;
 633         unsigned long flags;
 634
 635         spin_lock_irqsave(&prcmu_lock, flags);
 636         val = readl(_PRCMU_BASE + reg);
 637         val = ((val & ~mask) | (value & mask));
 638         writel(val, (_PRCMU_BASE + reg));
 639         spin_unlock_irqrestore(&prcmu_lock, flags);
 640 }
 641
 642 struct prcmu_fw_version *prcmu_get_fw_version(void)
 643 {
 644         return fw_info.valid ? &fw_info.version : NULL;
 645 }
 646
 647 bool prcmu_has_arm_maxopp(void)
 648 {
 649         return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
 650                 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
 651 }
 652
 653 /**
 654  * prcmu_get_boot_status - PRCMU boot status checking
 655  * Returns: the current PRCMU boot status
 656  */
 657 int prcmu_get_boot_status(void)
 658 {
 659         return readb(tcdm_base + PRCM_BOOT_STATUS);
 660 }
 661
 662 /**
 663  * prcmu_set_rc_a2p - This function is used to run few power state sequences
 664  * @val: Value to be set, i.e. transition requested
 665  * Returns: 0 on success, -EINVAL on invalid argument
 666  *
 667  * This function is used to run the following power state sequences -
 668  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 669  */
 670 int prcmu_set_rc_a2p(enum romcode_write val)
 671 {
 672         if (val < RDY_2_DS || val > RDY_2_XP70_RST)
 673                 return -EINVAL;
 674         writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
 675         return 0;
 676 }
 677
 678 /**
 679  * prcmu_get_rc_p2a - This function is used to get power state sequences
 680  * Returns: the power transition that has last happened
 681  *
 682  * This function can return the following transitions-
 683  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 684  */
 685 enum romcode_read prcmu_get_rc_p2a(void)
 686 {
 687         return readb(tcdm_base + PRCM_ROMCODE_P2A);
 688 }
 689
 690 /**
 691  * prcmu_get_current_mode - Return the current XP70 power mode
 692  * Returns: Returns the current AP(ARM) power mode: init,
 693  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
 694  */
 695 enum ap_pwrst prcmu_get_xp70_current_state(void)
 696 {
 697         return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
 698 }
 699
 700 /**
 701  * prcmu_config_clkout - Configure one of the programmable clock outputs.
 702  * @clkout:     The CLKOUT number (0 or 1).
 703  * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
 704  * @div:        The divider to be applied.
 705  *
 706  * Configures one of the programmable clock outputs (CLKOUTs).
 707  * @div should be in the range [1,63] to request a configuration, or 0 to
 708  * inform that the configuration is no longer requested.
 709  */
 710 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 711 {
 712         static int requests[2];
 713         int r = 0;
 714         unsigned long flags;
 715         u32 val;
 716         u32 bits;
 717         u32 mask;
 718         u32 div_mask;
 719
 720         BUG_ON(clkout > 1);
 721         BUG_ON(div > 63);
 722         BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
 723
 724         if (!div && !requests[clkout])
 725                 return -EINVAL;
 726
 727         switch (clkout) {
 728         case 0:
 729                 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
 730                 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
 731                 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
 732                         (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
 733                 break;
 734         case 1:
 735                 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
 736                 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
 737                         PRCM_CLKOCR_CLK1TYPE);
 738                 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
 739                         (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
 740                 break;
 741         }
 742         bits &= mask;
 743
 744         spin_lock_irqsave(&clkout_lock, flags);
 745
 746         val = readl(PRCM_CLKOCR);
 747         if (val & div_mask) {
 748                 if (div) {
 749                         if ((val & mask) != bits) {
 750                                 r = -EBUSY;
 751                                 goto unlock_and_return;
 752                         }
 753                 } else {
 754                         if ((val & mask & ~div_mask) != bits) {
 755                                 r = -EINVAL;
 756                                 goto unlock_and_return;
 757                         }
 758                 }
 759         }
 760         writel((bits | (val & ~mask)), PRCM_CLKOCR);
 761         requests[clkout] += (div ? 1 : -1);
 762
 763 unlock_and_return:
 764         spin_unlock_irqrestore(&clkout_lock, flags);
 765
 766         return r;
 767 }
 768
 769 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 770 {
 771         unsigned long flags;
 772
 773         BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
 774
 775         spin_lock_irqsave(&mb0_transfer.lock, flags);
 776
 777         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 778                 cpu_relax();
 779
 780         writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 781         writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
 782         writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
 783         writeb((keep_ulp_clk ? 1 : 0),
 784                 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
 785         writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
 786         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 787
 788         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 789
 790         return 0;
 791 }
 792
 793 u8 db8500_prcmu_get_power_state_result(void)
 794 {
 795         return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
 796 }
 797
 798 /* This function decouple the gic from the prcmu */
 799 int db8500_prcmu_gic_decouple(void)
 800 {
 801         u32 val = readl(PRCM_A9_MASK_REQ);
 802
 803         /* Set bit 0 register value to 1 */
 804         writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
 805                PRCM_A9_MASK_REQ);
 806
 807         /* Make sure the register is updated */
 808         readl(PRCM_A9_MASK_REQ);
 809
 810         /* Wait a few cycles for the gic mask completion */
 811         udelay(1);
 812
 813         return 0;
 814 }
 815
 816 /* This function recouple the gic with the prcmu */
 817 int db8500_prcmu_gic_recouple(void)
 818 {
 819         u32 val = readl(PRCM_A9_MASK_REQ);
 820
 821         /* Set bit 0 register value to 0 */
 822         writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
 823
 824         return 0;
 825 }
 826
 827 #define PRCMU_GIC_NUMBER_REGS 5
 828
 829 /*
 830  * This function checks if there are pending irq on the gic. It only
 831  * makes sense if the gic has been decoupled before with the
 832  * db8500_prcmu_gic_decouple function. Disabling an interrupt only
 833  * disables the forwarding of the interrupt to any CPU interface. It
 834  * does not prevent the interrupt from changing state, for example
 835  * becoming pending, or active and pending if it is already
 836  * active. Hence, we have to check the interrupt is pending *and* is
 837  * active.
 838  */
 839 bool db8500_prcmu_gic_pending_irq(void)
 840 {
 841         u32 pr; /* Pending register */
 842         u32 er; /* Enable register */
 843         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 844         int i;
 845
 846         /* 5 registers. STI & PPI not skipped */
 847         for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
 848
 849                 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
 850                 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 851
 852                 if (pr & er)
 853                         return true; /* There is a pending interrupt */
 854         }
 855
 856         return false;
 857 }
 858
 859 /*
 860  * This function checks if there are pending interrupt on the
 861  * prcmu which has been delegated to monitor the irqs with the
 862  * db8500_prcmu_copy_gic_settings function.
 863  */
 864 bool db8500_prcmu_pending_irq(void)
 865 {
 866         u32 it, im;
 867         int i;
 868
 869         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 870                 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
 871                 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
 872                 if (it & im)
 873                         return true; /* There is a pending interrupt */
 874         }
 875
 876         return false;
 877 }
 878
 879 /*
 880  * This function checks if the specified cpu is in in WFI. It's usage
 881  * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
 882  * function. Of course passing smp_processor_id() to this function will
 883  * always return false...
 884  */
 885 bool db8500_prcmu_is_cpu_in_wfi(int cpu)
 886 {
 887         return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
 888                      PRCM_ARM_WFI_STANDBY_WFI0;
 889 }
 890
 891 /*
 892  * This function copies the gic SPI settings to the prcmu in order to
 893  * monitor them and abort/finish the retention/off sequence or state.
 894  */
 895 int db8500_prcmu_copy_gic_settings(void)
 896 {
 897         u32 er; /* Enable register */
 898         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 899         int i;
 900
 901         /* We skip the STI and PPI */
 902         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 903                 er = readl_relaxed(dist_base +
 904                                    GIC_DIST_ENABLE_SET + (i + 1) * 4);
 905                 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
 906         }
 907
 908         return 0;
 909 }
 910
 911 /* This function should only be called while mb0_transfer.lock is held. */
 912 static void config_wakeups(void)
 913 {
 914         const u8 header[2] = {
 915                 MB0H_CONFIG_WAKEUPS_EXE,
 916                 MB0H_CONFIG_WAKEUPS_SLEEP
 917         };
 918         static u32 last_dbb_events;
 919         static u32 last_abb_events;
 920         u32 dbb_events;
 921         u32 abb_events;
 922         unsigned int i;
 923
 924         dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
 925         dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
 926
 927         abb_events = mb0_transfer.req.abb_events;
 928
 929         if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
 930                 return;
 931
 932         for (i = 0; i < 2; i++) {
 933                 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 934                         cpu_relax();
 935                 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
 936                 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
 937                 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 938                 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 939         }
 940         last_dbb_events = dbb_events;
 941         last_abb_events = abb_events;
 942 }
 943
 944 void db8500_prcmu_enable_wakeups(u32 wakeups)
 945 {
 946         unsigned long flags;
 947         u32 bits;
 948         int i;
 949
 950         BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
 951
 952         for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
 953                 if (wakeups & BIT(i))
 954                         bits |= prcmu_wakeup_bit[i];
 955         }
 956
 957         spin_lock_irqsave(&mb0_transfer.lock, flags);
 958
 959         mb0_transfer.req.dbb_wakeups = bits;
 960         config_wakeups();
 961
 962         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 963 }
 964
 965 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
 966 {
 967         unsigned long flags;
 968
 969         spin_lock_irqsave(&mb0_transfer.lock, flags);
 970
 971         mb0_transfer.req.abb_events = abb_events;
 972         config_wakeups();
 973
 974         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 975 }
 976
 977 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
 978 {
 979         if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
 980                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
 981         else
 982                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
 983 }
 984
 985 /**
 986  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
 987  * @opp: The new ARM operating point to which transition is to be made
 988  * Returns: 0 on success, non-zero on failure
 989  *
 990  * This function sets the the operating point of the ARM.
 991  */
 992 int db8500_prcmu_set_arm_opp(u8 opp)
 993 {
 994         int r;
 995
 996         if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
 997                 return -EINVAL;
 998
 999         r = 0;
1000
1001         mutex_lock(&mb1_transfer.lock);
1002
1003         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1004                 cpu_relax();
1005
1006         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1007         writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1008         writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1009
1010         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1011         wait_for_completion(&mb1_transfer.work);
1012
1013         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1014                 (mb1_transfer.ack.arm_opp != opp))
1015                 r = -EIO;
1016
1017         mutex_unlock(&mb1_transfer.lock);
1018
1019         return r;
1020 }
1021
1022 /**
1023  * db8500_prcmu_get_arm_opp - get the current ARM OPP
1024  *
1025  * Returns: the current ARM OPP
1026  */
1027 int db8500_prcmu_get_arm_opp(void)
1028 {
1029         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
1030 }
1031
1032 /**
1033  * db8500_prcmu_get_ddr_opp - get the current DDR OPP
1034  *
1035  * Returns: the current DDR OPP
1036  */
1037 int db8500_prcmu_get_ddr_opp(void)
1038 {
1039         return readb(PRCM_DDR_SUBSYS_APE_MINBW);
1040 }
1041
1042 /**
1043  * db8500_set_ddr_opp - set the appropriate DDR OPP
1044  * @opp: The new DDR operating point to which transition is to be made
1045  * Returns: 0 on success, non-zero on failure
1046  *
1047  * This function sets the operating point of the DDR.
1048  */
1049 static bool enable_set_ddr_opp;
1050 int db8500_prcmu_set_ddr_opp(u8 opp)
1051 {
1052         if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1053                 return -EINVAL;
1054         /* Changing the DDR OPP can hang the hardware pre-v21 */
1055         if (enable_set_ddr_opp)
1056                 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
1057
1058         return 0;
1059 }
1060
1061 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1062 static void request_even_slower_clocks(bool enable)
1063 {
1064         void __iomem *clock_reg[] = {
1065                 PRCM_ACLK_MGT,
1066                 PRCM_DMACLK_MGT
1067         };
1068         unsigned long flags;
1069         unsigned int i;
1070
1071         spin_lock_irqsave(&clk_mgt_lock, flags);
1072
1073         /* Grab the HW semaphore. */
1074         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1075                 cpu_relax();
1076
1077         for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
1078                 u32 val;
1079                 u32 div;
1080
1081                 val = readl(clock_reg[i]);
1082                 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1083                 if (enable) {
1084                         if ((div <= 1) || (div > 15)) {
1085                                 pr_err("prcmu: Bad clock divider %d in %s\n",
1086                                         div, __func__);
1087                                 goto unlock_and_return;
1088                         }
1089                         div <<= 1;
1090                 } else {
1091                         if (div <= 2)
1092                                 goto unlock_and_return;
1093                         div >>= 1;
1094                 }
1095                 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1096                         (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1097                 writel(val, clock_reg[i]);
1098         }
1099
1100 unlock_and_return:
1101         /* Release the HW semaphore. */
1102         writel(0, PRCM_SEM);
1103
1104         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1105 }
1106
1107 /**
1108  * db8500_set_ape_opp - set the appropriate APE OPP
1109  * @opp: The new APE operating point to which transition is to be made
1110  * Returns: 0 on success, non-zero on failure
1111  *
1112  * This function sets the operating point of the APE.
1113  */
1114 int db8500_prcmu_set_ape_opp(u8 opp)
1115 {
1116         int r = 0;
1117
1118         if (opp == mb1_transfer.ape_opp)
1119                 return 0;
1120
1121         mutex_lock(&mb1_transfer.lock);
1122
1123         if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1124                 request_even_slower_clocks(false);
1125
1126         if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1127                 goto skip_message;
1128
1129         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1130                 cpu_relax();
1131
1132         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1133         writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1134         writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1135                 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1136
1137         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1138         wait_for_completion(&mb1_transfer.work);
1139
1140         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1141                 (mb1_transfer.ack.ape_opp != opp))
1142                 r = -EIO;
1143
1144 skip_message:
1145         if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1146                 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1147                 request_even_slower_clocks(true);
1148         if (!r)
1149                 mb1_transfer.ape_opp = opp;
1150
1151         mutex_unlock(&mb1_transfer.lock);
1152
1153         return r;
1154 }
1155
1156 /**
1157  * db8500_prcmu_get_ape_opp - get the current APE OPP
1158  *
1159  * Returns: the current APE OPP
1160  */
1161 int db8500_prcmu_get_ape_opp(void)
1162 {
1163         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1164 }
1165
1166 /**
1167  * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1168  * @enable: true to request the higher voltage, false to drop a request.
1169  *
1170  * Calls to this function to enable and disable requests must be balanced.
1171  */
1172 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1173 {
1174         int r = 0;
1175         u8 header;
1176         static unsigned int requests;
1177
1178         mutex_lock(&mb1_transfer.lock);
1179
1180         if (enable) {
1181                 if (0 != requests++)
1182                         goto unlock_and_return;
1183                 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1184         } else {
1185                 if (requests == 0) {
1186                         r = -EIO;
1187                         goto unlock_and_return;
1188                 } else if (1 != requests--) {
1189                         goto unlock_and_return;
1190                 }
1191                 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1192         }
1193
1194         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1195                 cpu_relax();
1196
1197         writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1198
1199         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1200         wait_for_completion(&mb1_transfer.work);
1201
1202         if ((mb1_transfer.ack.header != header) ||
1203                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1204                 r = -EIO;
1205
1206 unlock_and_return:
1207         mutex_unlock(&mb1_transfer.lock);
1208
1209         return r;
1210 }
1211
1212 /**
1213  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1214  *
1215  * This function releases the power state requirements of a USB wakeup.
1216  */
1217 int prcmu_release_usb_wakeup_state(void)
1218 {
1219         int r = 0;
1220
1221         mutex_lock(&mb1_transfer.lock);
1222
1223         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1224                 cpu_relax();
1225
1226         writeb(MB1H_RELEASE_USB_WAKEUP,
1227                 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1228
1229         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1230         wait_for_completion(&mb1_transfer.work);
1231
1232         if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1233                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1234                 r = -EIO;
1235
1236         mutex_unlock(&mb1_transfer.lock);
1237
1238         return r;
1239 }
1240
1241 static int request_pll(u8 clock, bool enable)
1242 {
1243         int r = 0;
1244
1245         if (clock == PRCMU_PLLSOC0)
1246                 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1247         else if (clock == PRCMU_PLLSOC1)
1248                 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1249         else
1250                 return -EINVAL;
1251
1252         mutex_lock(&mb1_transfer.lock);
1253
1254         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1255                 cpu_relax();
1256
1257         writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1258         writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1259
1260         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1261         wait_for_completion(&mb1_transfer.work);
1262
1263         if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1264                 r = -EIO;
1265
1266         mutex_unlock(&mb1_transfer.lock);
1267
1268         return r;
1269 }
1270
1271 /**
1272  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1273  * @epod_id: The EPOD to set
1274  * @epod_state: The new EPOD state
1275  *
1276  * This function sets the state of a EPOD (power domain). It may not be called
1277  * from interrupt context.
1278  */
1279 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1280 {
1281         int r = 0;
1282         bool ram_retention = false;
1283         int i;
1284
1285         /* check argument */
1286         BUG_ON(epod_id >= NUM_EPOD_ID);
1287
1288         /* set flag if retention is possible */
1289         switch (epod_id) {
1290         case EPOD_ID_SVAMMDSP:
1291         case EPOD_ID_SIAMMDSP:
1292         case EPOD_ID_ESRAM12:
1293         case EPOD_ID_ESRAM34:
1294                 ram_retention = true;
1295                 break;
1296         }
1297
1298         /* check argument */
1299         BUG_ON(epod_state > EPOD_STATE_ON);
1300         BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1301
1302         /* get lock */
1303         mutex_lock(&mb2_transfer.lock);
1304
1305         /* wait for mailbox */
1306         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1307                 cpu_relax();
1308
1309         /* fill in mailbox */
1310         for (i = 0; i < NUM_EPOD_ID; i++)
1311                 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1312         writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1313
1314         writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1315
1316         writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1317
1318         /*
1319          * The current firmware version does not handle errors correctly,
1320          * and we cannot recover if there is an error.
1321          * This is expected to change when the firmware is updated.
1322          */
1323         if (!wait_for_completion_timeout(&mb2_transfer.work,
1324                         msecs_to_jiffies(20000))) {
1325                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1326                         __func__);
1327                 r = -EIO;
1328                 goto unlock_and_return;
1329         }
1330
1331         if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1332                 r = -EIO;
1333
1334 unlock_and_return:
1335         mutex_unlock(&mb2_transfer.lock);
1336         return r;
1337 }
1338
1339 /**
1340  * prcmu_configure_auto_pm - Configure autonomous power management.
1341  * @sleep: Configuration for ApSleep.
1342  * @idle:  Configuration for ApIdle.
1343  */
1344 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1345         struct prcmu_auto_pm_config *idle)
1346 {
1347         u32 sleep_cfg;
1348         u32 idle_cfg;
1349         unsigned long flags;
1350
1351         BUG_ON((sleep == NULL) || (idle == NULL));
1352
1353         sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1354         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1355         sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1356         sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1357         sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1358         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1359
1360         idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1361         idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1362         idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1363         idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1364         idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1365         idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1366
1367         spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1368
1369         /*
1370          * The autonomous power management configuration is done through
1371          * fields in mailbox 2, but these fields are only used as shared
1372          * variables - i.e. there is no need to send a message.
1373          */
1374         writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1375         writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1376
1377         mb2_transfer.auto_pm_enabled =
1378                 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1379                  (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1380                  (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1381                  (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1382
1383         spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1384 }
1385 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1386
1387 bool prcmu_is_auto_pm_enabled(void)
1388 {
1389         return mb2_transfer.auto_pm_enabled;
1390 }
1391
1392 static int request_sysclk(bool enable)
1393 {
1394         int r;
1395         unsigned long flags;
1396
1397         r = 0;
1398
1399         mutex_lock(&mb3_transfer.sysclk_lock);
1400
1401         spin_lock_irqsave(&mb3_transfer.lock, flags);
1402
1403         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1404                 cpu_relax();
1405
1406         writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1407
1408         writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1409         writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1410
1411         spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1412
1413         /*
1414          * The firmware only sends an ACK if we want to enable the
1415          * SysClk, and it succeeds.
1416          */
1417         if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1418                         msecs_to_jiffies(20000))) {
1419                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1420                         __func__);
1421                 r = -EIO;
1422         }
1423
1424         mutex_unlock(&mb3_transfer.sysclk_lock);
1425
1426         return r;
1427 }
1428
1429 static int request_timclk(bool enable)
1430 {
1431         u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1432
1433         if (!enable)
1434                 val |= PRCM_TCR_STOP_TIMERS;
1435         writel(val, PRCM_TCR);
1436
1437         return 0;
1438 }
1439
1440 static int request_clock(u8 clock, bool enable)
1441 {
1442         u32 val;
1443         unsigned long flags;
1444
1445         spin_lock_irqsave(&clk_mgt_lock, flags);
1446
1447         /* Grab the HW semaphore. */
1448         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1449                 cpu_relax();
1450
1451         val = readl(clk_mgt[clock].reg);
1452         if (enable) {
1453                 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1454         } else {
1455                 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1456                 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1457         }
1458         writel(val, clk_mgt[clock].reg);
1459
1460         /* Release the HW semaphore. */
1461         writel(0, PRCM_SEM);
1462
1463         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1464
1465         return 0;
1466 }
1467
1468 static int request_sga_clock(u8 clock, bool enable)
1469 {
1470         u32 val;
1471         int ret;
1472
1473         if (enable) {
1474                 val = readl(PRCM_CGATING_BYPASS);
1475                 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1476         }
1477
1478         ret = request_clock(clock, enable);
1479
1480         if (!ret && !enable) {
1481                 val = readl(PRCM_CGATING_BYPASS);
1482                 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1483         }
1484
1485         return ret;
1486 }
1487
1488 static inline bool plldsi_locked(void)
1489 {
1490         return (readl(PRCM_PLLDSI_LOCKP) &
1491                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1492                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1493                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1494                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1495 }
1496
1497 static int request_plldsi(bool enable)
1498 {
1499         int r = 0;
1500         u32 val;
1501
1502         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1503                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1504                 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1505
1506         val = readl(PRCM_PLLDSI_ENABLE);
1507         if (enable)
1508                 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1509         else
1510                 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1511         writel(val, PRCM_PLLDSI_ENABLE);
1512
1513         if (enable) {
1514                 unsigned int i;
1515                 bool locked = plldsi_locked();
1516
1517                 for (i = 10; !locked && (i > 0); --i) {
1518                         udelay(100);
1519                         locked = plldsi_locked();
1520                 }
1521                 if (locked) {
1522                         writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1523                                 PRCM_APE_RESETN_SET);
1524                 } else {
1525                         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1526                                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1527                                 PRCM_MMIP_LS_CLAMP_SET);
1528                         val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1529                         writel(val, PRCM_PLLDSI_ENABLE);
1530                         r = -EAGAIN;
1531                 }
1532         } else {
1533                 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1534         }
1535         return r;
1536 }
1537
1538 static int request_dsiclk(u8 n, bool enable)
1539 {
1540         u32 val;
1541
1542         val = readl(PRCM_DSI_PLLOUT_SEL);
1543         val &= ~dsiclk[n].divsel_mask;
1544         val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1545                 dsiclk[n].divsel_shift);
1546         writel(val, PRCM_DSI_PLLOUT_SEL);
1547         return 0;
1548 }
1549
1550 static int request_dsiescclk(u8 n, bool enable)
1551 {
1552         u32 val;
1553
1554         val = readl(PRCM_DSITVCLK_DIV);
1555         enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1556         writel(val, PRCM_DSITVCLK_DIV);
1557         return 0;
1558 }
1559
1560 /**
1561  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1562  * @clock:      The clock for which the request is made.
1563  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1564  *
1565  * This function should only be used by the clock implementation.
1566  * Do not use it from any other place!
1567  */
1568 int db8500_prcmu_request_clock(u8 clock, bool enable)
1569 {
1570         if (clock == PRCMU_SGACLK)
1571                 return request_sga_clock(clock, enable);
1572         else if (clock < PRCMU_NUM_REG_CLOCKS)
1573                 return request_clock(clock, enable);
1574         else if (clock == PRCMU_TIMCLK)
1575                 return request_timclk(enable);
1576         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1577                 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1578         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1579                 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1580         else if (clock == PRCMU_PLLDSI)
1581                 return request_plldsi(enable);
1582         else if (clock == PRCMU_SYSCLK)
1583                 return request_sysclk(enable);
1584         else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1585                 return request_pll(clock, enable);
1586         else
1587                 return -EINVAL;
1588 }
1589
1590 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1591         int branch)
1592 {
1593         u64 rate;
1594         u32 val;
1595         u32 d;
1596         u32 div = 1;
1597
1598         val = readl(reg);
1599
1600         rate = src_rate;
1601         rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1602
1603         d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1604         if (d > 1)
1605                 div *= d;
1606
1607         d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1608         if (d > 1)
1609                 div *= d;
1610
1611         if (val & PRCM_PLL_FREQ_SELDIV2)
1612                 div *= 2;
1613
1614         if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1615                 (val & PRCM_PLL_FREQ_DIV2EN) &&
1616                 ((reg == PRCM_PLLSOC0_FREQ) ||
1617                  (reg == PRCM_PLLARM_FREQ) ||
1618                  (reg == PRCM_PLLDDR_FREQ))))
1619                 div *= 2;
1620
1621         (void)do_div(rate, div);
1622
1623         return (unsigned long)rate;
1624 }
1625
1626 #define ROOT_CLOCK_RATE 38400000
1627
1628 static unsigned long clock_rate(u8 clock)
1629 {
1630         u32 val;
1631         u32 pllsw;
1632         unsigned long rate = ROOT_CLOCK_RATE;
1633
1634         val = readl(clk_mgt[clock].reg);
1635
1636         if (val & PRCM_CLK_MGT_CLK38) {
1637                 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1638                         rate /= 2;
1639                 return rate;
1640         }
1641
1642         val |= clk_mgt[clock].pllsw;
1643         pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1644
1645         if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1646                 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1647         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1648                 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1649         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1650                 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1651         else
1652                 return 0;
1653
1654         if ((clock == PRCMU_SGACLK) &&
1655                 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1656                 u64 r = (rate * 10);
1657
1658                 (void)do_div(r, 25);
1659                 return (unsigned long)r;
1660         }
1661         val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1662         if (val)
1663                 return rate / val;
1664         else
1665                 return 0;
1666 }
1667
1668 static unsigned long armss_rate(void)
1669 {
1670         u32 r;
1671         unsigned long rate;
1672
1673         r = readl(PRCM_ARM_CHGCLKREQ);
1674
1675         if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1676                 /* External ARMCLKFIX clock */
1677
1678                 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1679
1680                 /* Check PRCM_ARM_CHGCLKREQ divider */
1681                 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1682                         rate /= 2;
1683
1684                 /* Check PRCM_ARMCLKFIX_MGT divider */
1685                 r = readl(PRCM_ARMCLKFIX_MGT);
1686                 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1687                 rate /= r;
1688
1689         } else {/* ARM PLL */
1690                 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1691         }
1692
1693         return rate;
1694 }
1695
1696 static unsigned long dsiclk_rate(u8 n)
1697 {
1698         u32 divsel;
1699         u32 div = 1;
1700
1701         divsel = readl(PRCM_DSI_PLLOUT_SEL);
1702         divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1703
1704         if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1705                 divsel = dsiclk[n].divsel;
1706
1707         switch (divsel) {
1708         case PRCM_DSI_PLLOUT_SEL_PHI_4:
1709                 div *= 2;
1710         case PRCM_DSI_PLLOUT_SEL_PHI_2:
1711                 div *= 2;
1712         case PRCM_DSI_PLLOUT_SEL_PHI:
1713                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1714                         PLL_RAW) / div;
1715         default:
1716                 return 0;
1717         }
1718 }
1719
1720 static unsigned long dsiescclk_rate(u8 n)
1721 {
1722         u32 div;
1723
1724         div = readl(PRCM_DSITVCLK_DIV);
1725         div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1726         return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1727 }
1728
1729 unsigned long prcmu_clock_rate(u8 clock)
1730 {
1731         if (clock < PRCMU_NUM_REG_CLOCKS)
1732                 return clock_rate(clock);
1733         else if (clock == PRCMU_TIMCLK)
1734                 return ROOT_CLOCK_RATE / 16;
1735         else if (clock == PRCMU_SYSCLK)
1736                 return ROOT_CLOCK_RATE;
1737         else if (clock == PRCMU_PLLSOC0)
1738                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1739         else if (clock == PRCMU_PLLSOC1)
1740                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1741         else if (clock == PRCMU_ARMSS)
1742                 return armss_rate();
1743         else if (clock == PRCMU_PLLDDR)
1744                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1745         else if (clock == PRCMU_PLLDSI)
1746                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1747                         PLL_RAW);
1748         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1749                 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1750         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1751                 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1752         else
1753                 return 0;
1754 }
1755
1756 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1757 {
1758         if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1759                 return ROOT_CLOCK_RATE;
1760         clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1761         if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1762                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1763         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1764                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1765         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1766                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1767         else
1768                 return 0;
1769 }
1770
1771 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1772 {
1773         u32 div;
1774
1775         div = (src_rate / rate);
1776         if (div == 0)
1777                 return 1;
1778         if (rate < (src_rate / div))
1779                 div++;
1780         return div;
1781 }
1782
1783 static long round_clock_rate(u8 clock, unsigned long rate)
1784 {
1785         u32 val;
1786         u32 div;
1787         unsigned long src_rate;
1788         long rounded_rate;
1789
1790         val = readl(clk_mgt[clock].reg);
1791         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1792                 clk_mgt[clock].branch);
1793         div = clock_divider(src_rate, rate);
1794         if (val & PRCM_CLK_MGT_CLK38) {
1795                 if (clk_mgt[clock].clk38div) {
1796                         if (div > 2)
1797                                 div = 2;
1798                 } else {
1799                         div = 1;
1800                 }
1801         } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1802                 u64 r = (src_rate * 10);
1803
1804                 (void)do_div(r, 25);
1805                 if (r <= rate)
1806                         return (unsigned long)r;
1807         }
1808         rounded_rate = (src_rate / min(div, (u32)31));
1809
1810         return rounded_rate;
1811 }
1812
1813 /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1814 static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
1815         { .frequency = 200000, .index = ARM_EXTCLK,},
1816         { .frequency = 400000, .index = ARM_50_OPP,},
1817         { .frequency = 800000, .index = ARM_100_OPP,},
1818         { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
1819         { .frequency = CPUFREQ_TABLE_END,},
1820 };
1821
1822 static long round_armss_rate(unsigned long rate)
1823 {
1824         long freq = 0;
1825         int i = 0;
1826
1827         /* cpufreq table frequencies is in KHz. */
1828         rate = rate / 1000;
1829
1830         /* Find the corresponding arm opp from the cpufreq table. */
1831         while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1832                 freq = db8500_cpufreq_table[i].frequency;
1833                 if (freq == rate)
1834                         break;
1835                 i++;
1836         }
1837
1838         /* Return the last valid value, even if a match was not found. */
1839         return freq * 1000;
1840 }
1841
1842 #define MIN_PLL_VCO_RATE 600000000ULL
1843 #define MAX_PLL_VCO_RATE 1680640000ULL
1844
1845 static long round_plldsi_rate(unsigned long rate)
1846 {
1847         long rounded_rate = 0;
1848         unsigned long src_rate;
1849         unsigned long rem;
1850         u32 r;
1851
1852         src_rate = clock_rate(PRCMU_HDMICLK);
1853         rem = rate;
1854
1855         for (r = 7; (rem > 0) && (r > 0); r--) {
1856                 u64 d;
1857
1858                 d = (r * rate);
1859                 (void)do_div(d, src_rate);
1860                 if (d < 6)
1861                         d = 6;
1862                 else if (d > 255)
1863                         d = 255;
1864                 d *= src_rate;
1865                 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1866                         ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1867                         continue;
1868                 (void)do_div(d, r);
1869                 if (rate < d) {
1870                         if (rounded_rate == 0)
1871                                 rounded_rate = (long)d;
1872                         break;
1873                 }
1874                 if ((rate - d) < rem) {
1875                         rem = (rate - d);
1876                         rounded_rate = (long)d;
1877                 }
1878         }
1879         return rounded_rate;
1880 }
1881
1882 static long round_dsiclk_rate(unsigned long rate)
1883 {
1884         u32 div;
1885         unsigned long src_rate;
1886         long rounded_rate;
1887
1888         src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1889                 PLL_RAW);
1890         div = clock_divider(src_rate, rate);
1891         rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1892
1893         return rounded_rate;
1894 }
1895
1896 static long round_dsiescclk_rate(unsigned long rate)
1897 {
1898         u32 div;
1899         unsigned long src_rate;
1900         long rounded_rate;
1901
1902         src_rate = clock_rate(PRCMU_TVCLK);
1903         div = clock_divider(src_rate, rate);
1904         rounded_rate = (src_rate / min(div, (u32)255));
1905
1906         return rounded_rate;
1907 }
1908
1909 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1910 {
1911         if (clock < PRCMU_NUM_REG_CLOCKS)
1912                 return round_clock_rate(clock, rate);
1913         else if (clock == PRCMU_ARMSS)
1914                 return round_armss_rate(rate);
1915         else if (clock == PRCMU_PLLDSI)
1916                 return round_plldsi_rate(rate);
1917         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1918                 return round_dsiclk_rate(rate);
1919         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1920                 return round_dsiescclk_rate(rate);
1921         else
1922                 return (long)prcmu_clock_rate(clock);
1923 }
1924
1925 static void set_clock_rate(u8 clock, unsigned long rate)
1926 {
1927         u32 val;
1928         u32 div;
1929         unsigned long src_rate;
1930         unsigned long flags;
1931
1932         spin_lock_irqsave(&clk_mgt_lock, flags);
1933
1934         /* Grab the HW semaphore. */
1935         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1936                 cpu_relax();
1937
1938         val = readl(clk_mgt[clock].reg);
1939         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1940                 clk_mgt[clock].branch);
1941         div = clock_divider(src_rate, rate);
1942         if (val & PRCM_CLK_MGT_CLK38) {
1943                 if (clk_mgt[clock].clk38div) {
1944                         if (div > 1)
1945                                 val |= PRCM_CLK_MGT_CLK38DIV;
1946                         else
1947                                 val &= ~PRCM_CLK_MGT_CLK38DIV;
1948                 }
1949         } else if (clock == PRCMU_SGACLK) {
1950                 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1951                         PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1952                 if (div == 3) {
1953                         u64 r = (src_rate * 10);
1954
1955                         (void)do_div(r, 25);
1956                         if (r <= rate) {
1957                                 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1958                                 div = 0;
1959                         }
1960                 }
1961                 val |= min(div, (u32)31);
1962         } else {
1963                 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1964                 val |= min(div, (u32)31);
1965         }
1966         writel(val, clk_mgt[clock].reg);
1967
1968         /* Release the HW semaphore. */
1969         writel(0, PRCM_SEM);
1970
1971         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1972 }
1973
1974 static int set_armss_rate(unsigned long rate)
1975 {
1976         int i = 0;
1977
1978         /* cpufreq table frequencies is in KHz. */
1979         rate = rate / 1000;
1980
1981         /* Find the corresponding arm opp from the cpufreq table. */
1982         while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1983                 if (db8500_cpufreq_table[i].frequency == rate)
1984                         break;
1985                 i++;
1986         }
1987
1988         if (db8500_cpufreq_table[i].frequency != rate)
1989                 return -EINVAL;
1990
1991         /* Set the new arm opp. */
1992         return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index);
1993 }
1994
1995 static int set_plldsi_rate(unsigned long rate)
1996 {
1997         unsigned long src_rate;
1998         unsigned long rem;
1999         u32 pll_freq = 0;
2000         u32 r;
2001
2002         src_rate = clock_rate(PRCMU_HDMICLK);
2003         rem = rate;
2004
2005         for (r = 7; (rem > 0) && (r > 0); r--) {
2006                 u64 d;
2007                 u64 hwrate;
2008
2009                 d = (r * rate);
2010                 (void)do_div(d, src_rate);
2011                 if (d < 6)
2012                         d = 6;
2013                 else if (d > 255)
2014                         d = 255;
2015                 hwrate = (d * src_rate);
2016                 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
2017                         ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
2018                         continue;
2019                 (void)do_div(hwrate, r);
2020                 if (rate < hwrate) {
2021                         if (pll_freq == 0)
2022                                 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
2023                                         (r << PRCM_PLL_FREQ_R_SHIFT));
2024                         break;
2025                 }
2026                 if ((rate - hwrate) < rem) {
2027                         rem = (rate - hwrate);
2028                         pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
2029                                 (r << PRCM_PLL_FREQ_R_SHIFT));
2030                 }
2031         }
2032         if (pll_freq == 0)
2033                 return -EINVAL;
2034
2035         pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
2036         writel(pll_freq, PRCM_PLLDSI_FREQ);
2037
2038         return 0;
2039 }
2040
2041 static void set_dsiclk_rate(u8 n, unsigned long rate)
2042 {
2043         u32 val;
2044         u32 div;
2045
2046         div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
2047                         clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
2048
2049         dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
2050                            (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
2051                            /* else */   PRCM_DSI_PLLOUT_SEL_PHI_4;
2052
2053         val = readl(PRCM_DSI_PLLOUT_SEL);
2054         val &= ~dsiclk[n].divsel_mask;
2055         val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
2056         writel(val, PRCM_DSI_PLLOUT_SEL);
2057 }
2058
2059 static void set_dsiescclk_rate(u8 n, unsigned long rate)
2060 {
2061         u32 val;
2062         u32 div;
2063
2064         div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
2065         val = readl(PRCM_DSITVCLK_DIV);
2066         val &= ~dsiescclk[n].div_mask;
2067         val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
2068         writel(val, PRCM_DSITVCLK_DIV);
2069 }
2070
2071 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
2072 {
2073         if (clock < PRCMU_NUM_REG_CLOCKS)
2074                 set_clock_rate(clock, rate);
2075         else if (clock == PRCMU_ARMSS)
2076                 return set_armss_rate(rate);
2077         else if (clock == PRCMU_PLLDSI)
2078                 return set_plldsi_rate(rate);
2079         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
2080                 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
2081         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
2082                 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
2083         return 0;
2084 }
2085
2086 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
2087 {
2088         if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2089             (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2090                 return -EINVAL;
2091
2092         mutex_lock(&mb4_transfer.lock);
2093
2094         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2095                 cpu_relax();
2096
2097         writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2098         writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2099                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2100         writeb(DDR_PWR_STATE_ON,
2101                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2102         writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2103
2104         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2105         wait_for_completion(&mb4_transfer.work);
2106
2107         mutex_unlock(&mb4_transfer.lock);
2108
2109         return 0;
2110 }
2111
2112 int db8500_prcmu_config_hotdog(u8 threshold)
2113 {
2114         mutex_lock(&mb4_transfer.lock);
2115
2116         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2117                 cpu_relax();
2118
2119         writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2120         writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2121
2122         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2123         wait_for_completion(&mb4_transfer.work);
2124
2125         mutex_unlock(&mb4_transfer.lock);
2126
2127         return 0;
2128 }
2129
2130 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2131 {
2132         mutex_lock(&mb4_transfer.lock);
2133
2134         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2135                 cpu_relax();
2136
2137         writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2138         writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2139         writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2140                 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2141         writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2142
2143         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2144         wait_for_completion(&mb4_transfer.work);
2145
2146         mutex_unlock(&mb4_transfer.lock);
2147
2148         return 0;
2149 }
2150
2151 static int config_hot_period(u16 val)
2152 {
2153         mutex_lock(&mb4_transfer.lock);
2154
2155         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2156                 cpu_relax();
2157
2158         writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2159         writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2160
2161         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2162         wait_for_completion(&mb4_transfer.work);
2163
2164         mutex_unlock(&mb4_transfer.lock);
2165
2166         return 0;
2167 }
2168
2169 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2170 {
2171         if (cycles32k == 0xFFFF)
2172                 return -EINVAL;
2173
2174         return config_hot_period(cycles32k);
2175 }
2176
2177 int db8500_prcmu_stop_temp_sense(void)
2178 {
2179         return config_hot_period(0xFFFF);
2180 }
2181
2182 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2183 {
2184
2185         mutex_lock(&mb4_transfer.lock);
2186
2187         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2188                 cpu_relax();
2189
2190         writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2191         writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2192         writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2193         writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2194
2195         writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2196
2197         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2198         wait_for_completion(&mb4_transfer.work);
2199
2200         mutex_unlock(&mb4_transfer.lock);
2201
2202         return 0;
2203
2204 }
2205
2206 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2207 {
2208         BUG_ON(num == 0 || num > 0xf);
2209         return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2210                             sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2211                             A9WDOG_AUTO_OFF_DIS);
2212 }
2213
2214 int db8500_prcmu_enable_a9wdog(u8 id)
2215 {
2216         return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2217 }
2218
2219 int db8500_prcmu_disable_a9wdog(u8 id)
2220 {
2221         return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2222 }
2223
2224 int db8500_prcmu_kick_a9wdog(u8 id)
2225 {
2226         return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2227 }
2228
2229 /*
2230  * timeout is 28 bit, in ms.
2231  */
2232 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2233 {
2234         return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2235                             (id & A9WDOG_ID_MASK) |
2236                             /*
2237                              * Put the lowest 28 bits of timeout at
2238                              * offset 4. Four first bits are used for id.
2239                              */
2240                             (u8)((timeout << 4) & 0xf0),
2241                             (u8)((timeout >> 4) & 0xff),
2242                             (u8)((timeout >> 12) & 0xff),
2243                             (u8)((timeout >> 20) & 0xff));
2244 }
2245
2246 /**
2247  * prcmu_abb_read() - Read register value(s) from the ABB.
2248  * @slave:      The I2C slave address.
2249  * @reg:        The (start) register address.
2250  * @value:      The read out value(s).
2251  * @size:       The number of registers to read.
2252  *
2253  * Reads register value(s) from the ABB.
2254  * @size has to be 1 for the current firmware version.
2255  */
2256 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2257 {
2258         int r;
2259
2260         if (size != 1)
2261                 return -EINVAL;
2262
2263         mutex_lock(&mb5_transfer.lock);
2264
2265         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2266                 cpu_relax();
2267
2268         writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2269         writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2270         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2271         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2272         writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2273
2274         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2275
2276         if (!wait_for_completion_timeout(&mb5_transfer.work,
2277                                 msecs_to_jiffies(20000))) {
2278                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2279                         __func__);
2280                 r = -EIO;
2281         } else {
2282                 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2283         }
2284
2285         if (!r)
2286                 *value = mb5_transfer.ack.value;
2287
2288         mutex_unlock(&mb5_transfer.lock);
2289
2290         return r;
2291 }
2292
2293 /**
2294  * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2295  * @slave:      The I2C slave address.
2296  * @reg:        The (start) register address.
2297  * @value:      The value(s) to write.
2298  * @mask:       The mask(s) to use.
2299  * @size:       The number of registers to write.
2300  *
2301  * Writes masked register value(s) to the ABB.
2302  * For each @value, only the bits set to 1 in the corresponding @mask
2303  * will be written. The other bits are not changed.
2304  * @size has to be 1 for the current firmware version.
2305  */
2306 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2307 {
2308         int r;
2309
2310         if (size != 1)
2311                 return -EINVAL;
2312
2313         mutex_lock(&mb5_transfer.lock);
2314
2315         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2316                 cpu_relax();
2317
2318         writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2319         writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2320         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2321         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2322         writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2323
2324         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2325
2326         if (!wait_for_completion_timeout(&mb5_transfer.work,
2327                                 msecs_to_jiffies(20000))) {
2328                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2329                         __func__);
2330                 r = -EIO;
2331         } else {
2332                 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2333         }
2334
2335         mutex_unlock(&mb5_transfer.lock);
2336
2337         return r;
2338 }
2339
2340 /**
2341  * prcmu_abb_write() - Write register value(s) to the ABB.
2342  * @slave:      The I2C slave address.
2343  * @reg:        The (start) register address.
2344  * @value:      The value(s) to write.
2345  * @size:       The number of registers to write.
2346  *
2347  * Writes register value(s) to the ABB.
2348  * @size has to be 1 for the current firmware version.
2349  */
2350 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2351 {
2352         u8 mask = ~0;
2353
2354         return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2355 }
2356
2357 /**
2358  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2359  */
2360 int prcmu_ac_wake_req(void)
2361 {
2362         u32 val;
2363         int ret = 0;
2364
2365         mutex_lock(&mb0_transfer.ac_wake_lock);
2366
2367         val = readl(PRCM_HOSTACCESS_REQ);
2368         if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2369                 goto unlock_and_return;
2370
2371         atomic_set(&ac_wake_req_state, 1);
2372
2373         /*
2374          * Force Modem Wake-up before hostaccess_req ping-pong.
2375          * It prevents Modem to enter in Sleep while acking the hostaccess
2376          * request. The 31us delay has been calculated by HWI.
2377          */
2378         val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2379         writel(val, PRCM_HOSTACCESS_REQ);
2380
2381         udelay(31);
2382
2383         val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2384         writel(val, PRCM_HOSTACCESS_REQ);
2385
2386         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2387                         msecs_to_jiffies(5000))) {
2388 #if defined(CONFIG_DBX500_PRCMU_DEBUG)
2389                 db8500_prcmu_debug_dump(__func__, true, true);
2390 #endif
2391                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2392                         __func__);
2393                 ret = -EFAULT;
2394         }
2395
2396 unlock_and_return:
2397         mutex_unlock(&mb0_transfer.ac_wake_lock);
2398         return ret;
2399 }
2400
2401 /**
2402  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2403  */
2404 void prcmu_ac_sleep_req()
2405 {
2406         u32 val;
2407
2408         mutex_lock(&mb0_transfer.ac_wake_lock);
2409
2410         val = readl(PRCM_HOSTACCESS_REQ);
2411         if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2412                 goto unlock_and_return;
2413
2414         writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2415                 PRCM_HOSTACCESS_REQ);
2416
2417         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2418                         msecs_to_jiffies(5000))) {
2419                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2420                         __func__);
2421         }
2422
2423         atomic_set(&ac_wake_req_state, 0);
2424
2425 unlock_and_return:
2426         mutex_unlock(&mb0_transfer.ac_wake_lock);
2427 }
2428
2429 bool db8500_prcmu_is_ac_wake_requested(void)
2430 {
2431         return (atomic_read(&ac_wake_req_state) != 0);
2432 }
2433
2434 /**
2435  * db8500_prcmu_system_reset - System reset
2436  *
2437  * Saves the reset reason code and then sets the APE_SOFTRST register which
2438  * fires interrupt to fw
2439  */
2440 void db8500_prcmu_system_reset(u16 reset_code)
2441 {
2442         writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2443         writel(1, PRCM_APE_SOFTRST);
2444 }
2445
2446 /**
2447  * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2448  *
2449  * Retrieves the reset reason code stored by prcmu_system_reset() before
2450  * last restart.
2451  */
2452 u16 db8500_prcmu_get_reset_code(void)
2453 {
2454         return readw(tcdm_base + PRCM_SW_RST_REASON);
2455 }
2456
2457 /**
2458  * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2459  */
2460 void db8500_prcmu_modem_reset(void)
2461 {
2462         mutex_lock(&mb1_transfer.lock);
2463
2464         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2465                 cpu_relax();
2466
2467         writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2468         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2469         wait_for_completion(&mb1_transfer.work);
2470
2471         /*
2472          * No need to check return from PRCMU as modem should go in reset state
2473          * This state is already managed by upper layer
2474          */
2475
2476         mutex_unlock(&mb1_transfer.lock);
2477 }
2478
2479 static void ack_dbb_wakeup(void)
2480 {
2481         unsigned long flags;
2482
2483         spin_lock_irqsave(&mb0_transfer.lock, flags);
2484
2485         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2486                 cpu_relax();
2487
2488         writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2489         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2490
2491         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2492 }
2493
2494 static inline void print_unknown_header_warning(u8 n, u8 header)
2495 {
2496         pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2497                 header, n);
2498 }
2499
2500 static bool read_mailbox_0(void)
2501 {
2502         bool r;
2503         u32 ev;
2504         unsigned int n;
2505         u8 header;
2506
2507         header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2508         switch (header) {
2509         case MB0H_WAKEUP_EXE:
2510         case MB0H_WAKEUP_SLEEP:
2511                 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2512                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2513                 else
2514                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2515
2516                 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2517                         complete(&mb0_transfer.ac_wake_work);
2518                 if (ev & WAKEUP_BIT_SYSCLK_OK)
2519                         complete(&mb3_transfer.sysclk_work);
2520
2521                 ev &= mb0_transfer.req.dbb_irqs;
2522
2523                 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2524                         if (ev & prcmu_irq_bit[n])
2525                                 generic_handle_irq(IRQ_PRCMU_BASE + n);
2526                 }
2527                 r = true;
2528                 break;
2529         default:
2530                 print_unknown_header_warning(0, header);
2531                 r = false;
2532                 break;
2533         }
2534         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2535         return r;
2536 }
2537
2538 static bool read_mailbox_1(void)
2539 {
2540         mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2541         mb1_transfer.ack.arm_opp = readb(tcdm_base +
2542                 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2543         mb1_transfer.ack.ape_opp = readb(tcdm_base +
2544                 PRCM_ACK_MB1_CURRENT_APE_OPP);
2545         mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2546                 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2547         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2548         complete(&mb1_transfer.work);
2549         return false;
2550 }
2551
2552 static bool read_mailbox_2(void)
2553 {
2554         mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2555         writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2556         complete(&mb2_transfer.work);
2557         return false;
2558 }
2559
2560 static bool read_mailbox_3(void)
2561 {
2562         writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2563         return false;
2564 }
2565
2566 static bool read_mailbox_4(void)
2567 {
2568         u8 header;
2569         bool do_complete = true;
2570
2571         header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2572         switch (header) {
2573         case MB4H_MEM_ST:
2574         case MB4H_HOTDOG:
2575         case MB4H_HOTMON:
2576         case MB4H_HOT_PERIOD:
2577         case MB4H_A9WDOG_CONF:
2578         case MB4H_A9WDOG_EN:
2579         case MB4H_A9WDOG_DIS:
2580         case MB4H_A9WDOG_LOAD:
2581         case MB4H_A9WDOG_KICK:
2582                 break;
2583         default:
2584                 print_unknown_header_warning(4, header);
2585                 do_complete = false;
2586                 break;
2587         }
2588
2589         writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2590
2591         if (do_complete)
2592                 complete(&mb4_transfer.work);
2593
2594         return false;
2595 }
2596
2597 static bool read_mailbox_5(void)
2598 {
2599         mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2600         mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2601         writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2602         complete(&mb5_transfer.work);
2603         return false;
2604 }
2605
2606 static bool read_mailbox_6(void)
2607 {
2608         writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2609         return false;
2610 }
2611
2612 static bool read_mailbox_7(void)
2613 {
2614         writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2615         return false;
2616 }
2617
2618 static bool (* const read_mailbox[NUM_MB])(void) = {
2619         read_mailbox_0,
2620         read_mailbox_1,
2621         read_mailbox_2,
2622         read_mailbox_3,
2623         read_mailbox_4,
2624         read_mailbox_5,
2625         read_mailbox_6,
2626         read_mailbox_7
2627 };
2628
2629 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2630 {
2631         u32 bits;
2632         u8 n;
2633         irqreturn_t r;
2634
2635         bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2636         if (unlikely(!bits))
2637                 return IRQ_NONE;
2638
2639         r = IRQ_HANDLED;
2640         for (n = 0; bits; n++) {
2641                 if (bits & MBOX_BIT(n)) {
2642                         bits -= MBOX_BIT(n);
2643                         if (read_mailbox[n]())
2644                                 r = IRQ_WAKE_THREAD;
2645                 }
2646         }
2647         return r;
2648 }
2649
2650 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2651 {
2652         ack_dbb_wakeup();
2653         return IRQ_HANDLED;
2654 }
2655
2656 static void prcmu_mask_work(struct work_struct *work)
2657 {
2658         unsigned long flags;
2659
2660         spin_lock_irqsave(&mb0_transfer.lock, flags);
2661
2662         config_wakeups();
2663
2664         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2665 }
2666
2667 static void prcmu_irq_mask(struct irq_data *d)
2668 {
2669         unsigned long flags;
2670
2671         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2672
2673         mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2674
2675         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2676
2677         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2678                 schedule_work(&mb0_transfer.mask_work);
2679 }
2680
2681 static void prcmu_irq_unmask(struct irq_data *d)
2682 {
2683         unsigned long flags;
2684
2685         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2686
2687         mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2688
2689         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2690
2691         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2692                 schedule_work(&mb0_transfer.mask_work);
2693 }
2694
2695 static void noop(struct irq_data *d)
2696 {
2697 }
2698
2699 static struct irq_chip prcmu_irq_chip = {
2700         .name           = "prcmu",
2701         .irq_disable    = prcmu_irq_mask,
2702         .irq_ack        = noop,
2703         .irq_mask       = prcmu_irq_mask,
2704         .irq_unmask     = prcmu_irq_unmask,
2705 };
2706
2707 static char *fw_project_name(u8 project)
2708 {
2709         switch (project) {
2710         case PRCMU_FW_PROJECT_U8500:
2711                 return "U8500";
2712         case PRCMU_FW_PROJECT_U8500_C2:
2713                 return "U8500 C2";
2714         case PRCMU_FW_PROJECT_U9500:
2715                 return "U9500";
2716         case PRCMU_FW_PROJECT_U9500_C2:
2717                 return "U9500 C2";
2718         case PRCMU_FW_PROJECT_U8520:
2719                 return "U8520";
2720         case PRCMU_FW_PROJECT_U8420:
2721                 return "U8420";
2722         default:
2723                 return "Unknown";
2724         }
2725 }
2726
2727 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2728                                 irq_hw_number_t hwirq)
2729 {
2730         irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2731                                 handle_simple_irq);
2732         set_irq_flags(virq, IRQF_VALID);
2733
2734         return 0;
2735 }
2736
2737 static struct irq_domain_ops db8500_irq_ops = {
2738         .map    = db8500_irq_map,
2739         .xlate  = irq_domain_xlate_twocell,
2740 };
2741
2742 static int db8500_irq_init(struct device_node *np)
2743 {
2744         int irq_base = -1;
2745
2746         /* In the device tree case, just take some IRQs */
2747         if (!np)
2748                 irq_base = IRQ_PRCMU_BASE;
2749
2750         db8500_irq_domain = irq_domain_add_simple(
2751                 np, NUM_PRCMU_WAKEUPS, irq_base,
2752                 &db8500_irq_ops, NULL);
2753
2754         if (!db8500_irq_domain) {
2755                 pr_err("Failed to create irqdomain\n");
2756                 return -ENOSYS;
2757         }
2758
2759         return 0;
2760 }
2761
2762 void __init db8500_prcmu_early_init(void)
2763 {
2764         if (cpu_is_u8500v2() || cpu_is_u9540()) {
2765                 void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
2766
2767                 if (tcpm_base != NULL) {
2768                         u32 version;
2769                         version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
2770                         fw_info.version.project = version & 0xFF;
2771                         fw_info.version.api_version = (version >> 8) & 0xFF;
2772                         fw_info.version.func_version = (version >> 16) & 0xFF;
2773                         fw_info.version.errata = (version >> 24) & 0xFF;
2774                         fw_info.valid = true;
2775                         pr_info("PRCMU firmware: %s, version %d.%d.%d\n",
2776                                 fw_project_name(fw_info.version.project),
2777                                 (version >> 8) & 0xFF, (version >> 16) & 0xFF,
2778                                 (version >> 24) & 0xFF);
2779                         iounmap(tcpm_base);
2780                 }
2781
2782                 if (cpu_is_u9540())
2783                         tcdm_base = ioremap_nocache(U8500_PRCMU_TCDM_BASE,
2784                                                 SZ_4K + SZ_8K) + SZ_8K;
2785                 else
2786                         tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2787         } else {
2788                 pr_err("prcmu: Unsupported chip version\n");
2789                 BUG();
2790         }
2791         tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
2792
2793         spin_lock_init(&mb0_transfer.lock);
2794         spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2795         mutex_init(&mb0_transfer.ac_wake_lock);
2796         init_completion(&mb0_transfer.ac_wake_work);
2797         mutex_init(&mb1_transfer.lock);
2798         init_completion(&mb1_transfer.work);
2799         mb1_transfer.ape_opp = APE_NO_CHANGE;
2800         mutex_init(&mb2_transfer.lock);
2801         init_completion(&mb2_transfer.work);
2802         spin_lock_init(&mb2_transfer.auto_pm_lock);
2803         spin_lock_init(&mb3_transfer.lock);
2804         mutex_init(&mb3_transfer.sysclk_lock);
2805         init_completion(&mb3_transfer.sysclk_work);
2806         mutex_init(&mb4_transfer.lock);
2807         init_completion(&mb4_transfer.work);
2808         mutex_init(&mb5_transfer.lock);
2809         init_completion(&mb5_transfer.work);
2810
2811         INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2812 }
2813
2814 static void __init init_prcm_registers(void)
2815 {
2816         u32 val;
2817
2818         val = readl(PRCM_A9PL_FORCE_CLKEN);
2819         val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2820                 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2821         writel(val, (PRCM_A9PL_FORCE_CLKEN));
2822 }
2823
2824 /*
2825  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2826  */
2827 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2828         REGULATOR_SUPPLY("v-ape", NULL),
2829         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2830         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2831         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2832         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2833         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2834         /* "v-mmc" changed to "vcore" in the mainline kernel */
2835         REGULATOR_SUPPLY("vcore", "sdi0"),
2836         REGULATOR_SUPPLY("vcore", "sdi1"),
2837         REGULATOR_SUPPLY("vcore", "sdi2"),
2838         REGULATOR_SUPPLY("vcore", "sdi3"),
2839         REGULATOR_SUPPLY("vcore", "sdi4"),
2840         REGULATOR_SUPPLY("v-dma", "dma40.0"),
2841         REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2842         /* "v-uart" changed to "vcore" in the mainline kernel */
2843         REGULATOR_SUPPLY("vcore", "uart0"),
2844         REGULATOR_SUPPLY("vcore", "uart1"),
2845         REGULATOR_SUPPLY("vcore", "uart2"),
2846         REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2847         REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2848         REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2849 };
2850
2851 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2852         REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2853         /* AV8100 regulator */
2854         REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2855 };
2856
2857 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2858         REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2859         REGULATOR_SUPPLY("vsupply", "mcde"),
2860 };
2861
2862 /* SVA MMDSP regulator switch */
2863 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2864         REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2865 };
2866
2867 /* SVA pipe regulator switch */
2868 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2869         REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2870 };
2871
2872 /* SIA MMDSP regulator switch */
2873 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2874         REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2875 };
2876
2877 /* SIA pipe regulator switch */
2878 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2879         REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2880 };
2881
2882 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2883         REGULATOR_SUPPLY("v-mali", NULL),
2884 };
2885
2886 /* ESRAM1 and 2 regulator switch */
2887 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2888         REGULATOR_SUPPLY("esram12", "cm_control"),
2889 };
2890
2891 /* ESRAM3 and 4 regulator switch */
2892 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2893         REGULATOR_SUPPLY("v-esram34", "mcde"),
2894         REGULATOR_SUPPLY("esram34", "cm_control"),
2895         REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2896 };
2897
2898 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2899         [DB8500_REGULATOR_VAPE] = {
2900                 .constraints = {
2901                         .name = "db8500-vape",
2902                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2903                         .always_on = true,
2904                 },
2905                 .consumer_supplies = db8500_vape_consumers,
2906                 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2907         },
2908         [DB8500_REGULATOR_VARM] = {
2909                 .constraints = {
2910                         .name = "db8500-varm",
2911                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2912                 },
2913         },
2914         [DB8500_REGULATOR_VMODEM] = {
2915                 .constraints = {
2916                         .name = "db8500-vmodem",
2917                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2918                 },
2919         },
2920         [DB8500_REGULATOR_VPLL] = {
2921                 .constraints = {
2922                         .name = "db8500-vpll",
2923                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2924                 },
2925         },
2926         [DB8500_REGULATOR_VSMPS1] = {
2927                 .constraints = {
2928                         .name = "db8500-vsmps1",
2929                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2930                 },
2931         },
2932         [DB8500_REGULATOR_VSMPS2] = {
2933                 .constraints = {
2934                         .name = "db8500-vsmps2",
2935                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2936                 },
2937                 .consumer_supplies = db8500_vsmps2_consumers,
2938                 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2939         },
2940         [DB8500_REGULATOR_VSMPS3] = {
2941                 .constraints = {
2942                         .name = "db8500-vsmps3",
2943                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2944                 },
2945         },
2946         [DB8500_REGULATOR_VRF1] = {
2947                 .constraints = {
2948                         .name = "db8500-vrf1",
2949                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2950                 },
2951         },
2952         [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2953                 /* dependency to u8500-vape is handled outside regulator framework */
2954                 .constraints = {
2955                         .name = "db8500-sva-mmdsp",
2956                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2957                 },
2958                 .consumer_supplies = db8500_svammdsp_consumers,
2959                 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2960         },
2961         [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2962                 .constraints = {
2963                         /* "ret" means "retention" */
2964                         .name = "db8500-sva-mmdsp-ret",
2965                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2966                 },
2967         },
2968         [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
2969                 /* dependency to u8500-vape is handled outside regulator framework */
2970                 .constraints = {
2971                         .name = "db8500-sva-pipe",
2972                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2973                 },
2974                 .consumer_supplies = db8500_svapipe_consumers,
2975                 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
2976         },
2977         [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
2978                 /* dependency to u8500-vape is handled outside regulator framework */
2979                 .constraints = {
2980                         .name = "db8500-sia-mmdsp",
2981                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2982                 },
2983                 .consumer_supplies = db8500_siammdsp_consumers,
2984                 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
2985         },
2986         [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
2987                 .constraints = {
2988                         .name = "db8500-sia-mmdsp-ret",
2989                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2990                 },
2991         },
2992         [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
2993                 /* dependency to u8500-vape is handled outside regulator framework */
2994                 .constraints = {
2995                         .name = "db8500-sia-pipe",
2996                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2997                 },
2998                 .consumer_supplies = db8500_siapipe_consumers,
2999                 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
3000         },
3001         [DB8500_REGULATOR_SWITCH_SGA] = {
3002                 .supply_regulator = "db8500-vape",
3003                 .constraints = {
3004                         .name = "db8500-sga",
3005                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3006                 },
3007                 .consumer_supplies = db8500_sga_consumers,
3008                 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
3009
3010         },
3011         [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
3012                 .supply_regulator = "db8500-vape",
3013                 .constraints = {
3014                         .name = "db8500-b2r2-mcde",
3015                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3016                 },
3017                 .consumer_supplies = db8500_b2r2_mcde_consumers,
3018                 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
3019         },
3020         [DB8500_REGULATOR_SWITCH_ESRAM12] = {
3021                 /*
3022                  * esram12 is set in retention and supplied by Vsafe when Vape is off,
3023                  * no need to hold Vape
3024                  */
3025                 .constraints = {
3026                         .name = "db8500-esram12",
3027                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3028                 },
3029                 .consumer_supplies = db8500_esram12_consumers,
3030                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
3031         },
3032         [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
3033                 .constraints = {
3034                         .name = "db8500-esram12-ret",
3035                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3036                 },
3037         },
3038         [DB8500_REGULATOR_SWITCH_ESRAM34] = {
3039                 /*
3040                  * esram34 is set in retention and supplied by Vsafe when Vape is off,
3041                  * no need to hold Vape
3042                  */
3043                 .constraints = {
3044                         .name = "db8500-esram34",
3045                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3046                 },
3047                 .consumer_supplies = db8500_esram34_consumers,
3048                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3049         },
3050         [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3051                 .constraints = {
3052                         .name = "db8500-esram34-ret",
3053                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3054                 },
3055         },
3056 };
3057
3058 static struct resource ab8500_resources[] = {
3059         [0] = {
3060                 .start  = IRQ_DB8500_AB8500,
3061                 .end    = IRQ_DB8500_AB8500,
3062                 .flags  = IORESOURCE_IRQ
3063         }
3064 };
3065
3066 static struct mfd_cell db8500_prcmu_devs[] = {
3067         {
3068                 .name = "db8500-prcmu-regulators",
3069                 .of_compatible = "stericsson,db8500-prcmu-regulator",
3070                 .platform_data = &db8500_regulators,
3071                 .pdata_size = sizeof(db8500_regulators),
3072         },
3073         {
3074                 .name = "cpufreq-u8500",
3075                 .of_compatible = "stericsson,cpufreq-u8500",
3076                 .platform_data = &db8500_cpufreq_table,
3077                 .pdata_size = sizeof(db8500_cpufreq_table),
3078         },
3079         {
3080                 .name = "ab8500-core",
3081                 .of_compatible = "stericsson,ab8500",
3082                 .num_resources = ARRAY_SIZE(ab8500_resources),
3083                 .resources = ab8500_resources,
3084                 .id = AB8500_VERSION_AB8500,
3085         },
3086 };
3087
3088 static void db8500_prcmu_update_cpufreq(void)
3089 {
3090         if (prcmu_has_arm_maxopp()) {
3091                 db8500_cpufreq_table[3].frequency = 1000000;
3092                 db8500_cpufreq_table[3].index = ARM_MAX_OPP;
3093         }
3094 }
3095
3096 /**
3097  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3098  *
3099  */
3100 static int db8500_prcmu_probe(struct platform_device *pdev)
3101 {
3102         struct ab8500_platform_data *ab8500_platdata = pdev->dev.platform_data;
3103         struct device_node *np = pdev->dev.of_node;
3104         int irq = 0, err = 0, i;
3105
3106         init_prcm_registers();
3107
3108         /* Clean up the mailbox interrupts after pre-kernel code. */
3109         writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3110
3111         if (np)
3112                 irq = platform_get_irq(pdev, 0);
3113
3114         if (!np || irq <= 0)
3115                 irq = IRQ_DB8500_PRCMU1;
3116
3117         err = request_threaded_irq(irq, prcmu_irq_handler,
3118                 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3119         if (err < 0) {
3120                 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3121                 err = -EBUSY;
3122                 goto no_irq_return;
3123         }
3124
3125         db8500_irq_init(np);
3126
3127         for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
3128                 if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
3129                         db8500_prcmu_devs[i].platform_data = ab8500_platdata;
3130                         db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data);
3131                 }
3132         }
3133
3134         prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3135
3136         db8500_prcmu_update_cpufreq();
3137
3138         err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3139                               ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL);
3140         if (err) {
3141                 pr_err("prcmu: Failed to add subdevices\n");
3142                 return err;
3143         }
3144
3145         pr_info("DB8500 PRCMU initialized\n");
3146
3147 no_irq_return:
3148         return err;
3149 }
3150 static const struct of_device_id db8500_prcmu_match[] = {
3151         { .compatible = "stericsson,db8500-prcmu"},
3152         { },
3153 };
3154
3155 static struct platform_driver db8500_prcmu_driver = {
3156         .driver = {
3157                 .name = "db8500-prcmu",
3158                 .owner = THIS_MODULE,
3159                 .of_match_table = db8500_prcmu_match,
3160         },
3161         .probe = db8500_prcmu_probe,
3162 };
3163
3164 static int __init db8500_prcmu_init(void)
3165 {
3166         return platform_driver_register(&db8500_prcmu_driver);
3167 }
3168
3169 core_initcall(db8500_prcmu_init);
3170
3171 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3172 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3173 MODULE_LICENSE("GPL v2");