drivers/memory/emif.c

   1 /*
   2  * EMIF driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments, Inc.
   5  *
   6  * Aneesh V <aneesh@ti.com>
   7  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #include <linux/err.h>
  14 #include <linux/kernel.h>
  15 #include <linux/reboot.h>
  16 #include <linux/platform_data/emif_plat.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/slab.h>
  22 #include <linux/of.h>
  23 #include <linux/debugfs.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/module.h>
  26 #include <linux/list.h>
  27 #include <linux/spinlock.h>
  28 #include <memory/jedec_ddr.h>
  29 #include "emif.h"
  30 #include "of_memory.h"
  31
  32 /**
  33  * struct emif_data - Per device static data for driver's use
  34  * @duplicate:                  Whether the DDR devices attached to this EMIF
  35  *                              instance are exactly same as that on EMIF1. In
  36  *                              this case we can save some memory and processing
  37  * @temperature_level:          Maximum temperature of LPDDR2 devices attached
  38  *                              to this EMIF - read from MR4 register. If there
  39  *                              are two devices attached to this EMIF, this
  40  *                              value is the maximum of the two temperature
  41  *                              levels.
  42  * @node:                       node in the device list
  43  * @base:                       base address of memory-mapped IO registers.
  44  * @dev:                        device pointer.
  45  * @addressing                  table with addressing information from the spec
  46  * @regs_cache:                 An array of 'struct emif_regs' that stores
  47  *                              calculated register values for different
  48  *                              frequencies, to avoid re-calculating them on
  49  *                              each DVFS transition.
  50  * @curr_regs:                  The set of register values used in the last
  51  *                              frequency change (i.e. corresponding to the
  52  *                              frequency in effect at the moment)
  53  * @plat_data:                  Pointer to saved platform data.
  54  * @debugfs_root:               dentry to the root folder for EMIF in debugfs
  55  * @np_ddr:                     Pointer to ddr device tree node
  56  */
  57 struct emif_data {
  58         u8                              duplicate;
  59         u8                              temperature_level;
  60         u8                              lpmode;
  61         struct list_head                node;
  62         unsigned long                   irq_state;
  63         void __iomem                    *base;
  64         struct device                   *dev;
  65         const struct lpddr2_addressing  *addressing;
  66         struct emif_regs                *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
  67         struct emif_regs                *curr_regs;
  68         struct emif_platform_data       *plat_data;
  69         struct dentry                   *debugfs_root;
  70         struct device_node              *np_ddr;
  71 };
  72
  73 static struct emif_data *emif1;
  74 static spinlock_t       emif_lock;
  75 static unsigned long    irq_state;
  76 static u32              t_ck; /* DDR clock period in ps */
  77 static LIST_HEAD(device_list);
  78
  79 #ifdef CONFIG_DEBUG_FS
  80 static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
  81         struct emif_regs *regs)
  82 {
  83         u32 type = emif->plat_data->device_info->type;
  84         u32 ip_rev = emif->plat_data->ip_rev;
  85
  86         seq_printf(s, "EMIF register cache dump for %dMHz\n",
  87                 regs->freq/1000000);
  88
  89         seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
  90         seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
  91         seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
  92         seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
  93
  94         if (ip_rev == EMIF_4D) {
  95                 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
  96                         regs->read_idle_ctrl_shdw_normal);
  97                 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
  98                         regs->read_idle_ctrl_shdw_volt_ramp);
  99         } else if (ip_rev == EMIF_4D5) {
 100                 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
 101                         regs->dll_calib_ctrl_shdw_normal);
 102                 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
 103                         regs->dll_calib_ctrl_shdw_volt_ramp);
 104         }
 105
 106         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
 107                 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
 108                         regs->ref_ctrl_shdw_derated);
 109                 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
 110                         regs->sdram_tim1_shdw_derated);
 111                 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
 112                         regs->sdram_tim3_shdw_derated);
 113         }
 114 }
 115
 116 static int emif_regdump_show(struct seq_file *s, void *unused)
 117 {
 118         struct emif_data        *emif   = s->private;
 119         struct emif_regs        **regs_cache;
 120         int                     i;
 121
 122         if (emif->duplicate)
 123                 regs_cache = emif1->regs_cache;
 124         else
 125                 regs_cache = emif->regs_cache;
 126
 127         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
 128                 do_emif_regdump_show(s, emif, regs_cache[i]);
 129                 seq_printf(s, "\n");
 130         }
 131
 132         return 0;
 133 }
 134
 135 static int emif_regdump_open(struct inode *inode, struct file *file)
 136 {
 137         return single_open(file, emif_regdump_show, inode->i_private);
 138 }
 139
 140 static const struct file_operations emif_regdump_fops = {
 141         .open                   = emif_regdump_open,
 142         .read                   = seq_read,
 143         .release                = single_release,
 144 };
 145
 146 static int emif_mr4_show(struct seq_file *s, void *unused)
 147 {
 148         struct emif_data *emif = s->private;
 149
 150         seq_printf(s, "MR4=%d\n", emif->temperature_level);
 151         return 0;
 152 }
 153
 154 static int emif_mr4_open(struct inode *inode, struct file *file)
 155 {
 156         return single_open(file, emif_mr4_show, inode->i_private);
 157 }
 158
 159 static const struct file_operations emif_mr4_fops = {
 160         .open                   = emif_mr4_open,
 161         .read                   = seq_read,
 162         .release                = single_release,
 163 };
 164
 165 static int __init_or_module emif_debugfs_init(struct emif_data *emif)
 166 {
 167         struct dentry   *dentry;
 168         int             ret;
 169
 170         dentry = debugfs_create_dir(dev_name(emif->dev), NULL);
 171         if (!dentry) {
 172                 ret = -ENOMEM;
 173                 goto err0;
 174         }
 175         emif->debugfs_root = dentry;
 176
 177         dentry = debugfs_create_file("regcache_dump", S_IRUGO,
 178                         emif->debugfs_root, emif, &emif_regdump_fops);
 179         if (!dentry) {
 180                 ret = -ENOMEM;
 181                 goto err1;
 182         }
 183
 184         dentry = debugfs_create_file("mr4", S_IRUGO,
 185                         emif->debugfs_root, emif, &emif_mr4_fops);
 186         if (!dentry) {
 187                 ret = -ENOMEM;
 188                 goto err1;
 189         }
 190
 191         return 0;
 192 err1:
 193         debugfs_remove_recursive(emif->debugfs_root);
 194 err0:
 195         return ret;
 196 }
 197
 198 static void __exit emif_debugfs_exit(struct emif_data *emif)
 199 {
 200         debugfs_remove_recursive(emif->debugfs_root);
 201         emif->debugfs_root = NULL;
 202 }
 203 #else
 204 static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
 205 {
 206         return 0;
 207 }
 208
 209 static inline void __exit emif_debugfs_exit(struct emif_data *emif)
 210 {
 211 }
 212 #endif
 213
 214 /*
 215  * Calculate the period of DDR clock from frequency value
 216  */
 217 static void set_ddr_clk_period(u32 freq)
 218 {
 219         /* Divide 10^12 by frequency to get period in ps */
 220         t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
 221 }
 222
 223 /*
 224  * Get bus width used by EMIF. Note that this may be different from the
 225  * bus width of the DDR devices used. For instance two 16-bit DDR devices
 226  * may be connected to a given CS of EMIF. In this case bus width as far
 227  * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
 228  */
 229 static u32 get_emif_bus_width(struct emif_data *emif)
 230 {
 231         u32             width;
 232         void __iomem    *base = emif->base;
 233
 234         width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
 235                         >> NARROW_MODE_SHIFT;
 236         width = width == 0 ? 32 : 16;
 237
 238         return width;
 239 }
 240
 241 /*
 242  * Get the CL from SDRAM_CONFIG register
 243  */
 244 static u32 get_cl(struct emif_data *emif)
 245 {
 246         u32             cl;
 247         void __iomem    *base = emif->base;
 248
 249         cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
 250
 251         return cl;
 252 }
 253
 254 static void set_lpmode(struct emif_data *emif, u8 lpmode)
 255 {
 256         u32 temp;
 257         void __iomem *base = emif->base;
 258
 259         temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
 260         temp &= ~LP_MODE_MASK;
 261         temp |= (lpmode << LP_MODE_SHIFT);
 262         writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
 263 }
 264
 265 static void do_freq_update(void)
 266 {
 267         struct emif_data *emif;
 268
 269         /*
 270          * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
 271          *
 272          * i728 DESCRIPTION:
 273          * The EMIF automatically puts the SDRAM into self-refresh mode
 274          * after the EMIF has not performed accesses during
 275          * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
 276          * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
 277          * to 0x2. If during a small window the following three events
 278          * occur:
 279          * - The SR_TIMING counter expires
 280          * - And frequency change is requested
 281          * - And OCP access is requested
 282          * Then it causes instable clock on the DDR interface.
 283          *
 284          * WORKAROUND
 285          * To avoid the occurrence of the three events, the workaround
 286          * is to disable the self-refresh when requesting a frequency
 287          * change. Before requesting a frequency change the software must
 288          * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
 289          * frequency change has been done, the software can reprogram
 290          * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
 291          */
 292         list_for_each_entry(emif, &device_list, node) {
 293                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 294                         set_lpmode(emif, EMIF_LP_MODE_DISABLE);
 295         }
 296
 297         /*
 298          * TODO: Do FREQ_UPDATE here when an API
 299          * is available for this as part of the new
 300          * clock framework
 301          */
 302
 303         list_for_each_entry(emif, &device_list, node) {
 304                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 305                         set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
 306         }
 307 }
 308
 309 /* Find addressing table entry based on the device's type and density */
 310 static const struct lpddr2_addressing *get_addressing_table(
 311         const struct ddr_device_info *device_info)
 312 {
 313         u32             index, type, density;
 314
 315         type = device_info->type;
 316         density = device_info->density;
 317
 318         switch (type) {
 319         case DDR_TYPE_LPDDR2_S4:
 320                 index = density - 1;
 321                 break;
 322         case DDR_TYPE_LPDDR2_S2:
 323                 switch (density) {
 324                 case DDR_DENSITY_1Gb:
 325                 case DDR_DENSITY_2Gb:
 326                         index = density + 3;
 327                         break;
 328                 default:
 329                         index = density - 1;
 330                 }
 331                 break;
 332         default:
 333                 return NULL;
 334         }
 335
 336         return &lpddr2_jedec_addressing_table[index];
 337 }
 338
 339 /*
 340  * Find the the right timing table from the array of timing
 341  * tables of the device using DDR clock frequency
 342  */
 343 static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
 344                 u32 freq)
 345 {
 346         u32                             i, min, max, freq_nearest;
 347         const struct lpddr2_timings     *timings = NULL;
 348         const struct lpddr2_timings     *timings_arr = emif->plat_data->timings;
 349         struct                          device *dev = emif->dev;
 350
 351         /* Start with a very high frequency - 1GHz */
 352         freq_nearest = 1000000000;
 353
 354         /*
 355          * Find the timings table such that:
 356          *  1. the frequency range covers the required frequency(safe) AND
 357          *  2. the max_freq is closest to the required frequency(optimal)
 358          */
 359         for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
 360                 max = timings_arr[i].max_freq;
 361                 min = timings_arr[i].min_freq;
 362                 if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
 363                         freq_nearest = max;
 364                         timings = &timings_arr[i];
 365                 }
 366         }
 367
 368         if (!timings)
 369                 dev_err(dev, "%s: couldn't find timings for - %dHz\n",
 370                         __func__, freq);
 371
 372         dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
 373                 __func__, freq, freq_nearest);
 374
 375         return timings;
 376 }
 377
 378 static u32 get_sdram_ref_ctrl_shdw(u32 freq,
 379                 const struct lpddr2_addressing *addressing)
 380 {
 381         u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
 382
 383         /* Scale down frequency and t_refi to avoid overflow */
 384         freq_khz = freq / 1000;
 385         t_refi = addressing->tREFI_ns / 100;
 386
 387         /*
 388          * refresh rate to be set is 'tREFI(in us) * freq in MHz
 389          * division by 10000 to account for change in units
 390          */
 391         val = t_refi * freq_khz / 10000;
 392         ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
 393
 394         return ref_ctrl_shdw;
 395 }
 396
 397 static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
 398                 const struct lpddr2_min_tck *min_tck,
 399                 const struct lpddr2_addressing *addressing)
 400 {
 401         u32 tim1 = 0, val = 0;
 402
 403         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 404         tim1 |= val << T_WTR_SHIFT;
 405
 406         if (addressing->num_banks == B8)
 407                 val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
 408         else
 409                 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
 410         tim1 |= (val - 1) << T_RRD_SHIFT;
 411
 412         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
 413         tim1 |= val << T_RC_SHIFT;
 414
 415         val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
 416         tim1 |= (val - 1) << T_RAS_SHIFT;
 417
 418         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 419         tim1 |= val << T_WR_SHIFT;
 420
 421         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
 422         tim1 |= val << T_RCD_SHIFT;
 423
 424         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
 425         tim1 |= val << T_RP_SHIFT;
 426
 427         return tim1;
 428 }
 429
 430 static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
 431                 const struct lpddr2_min_tck *min_tck,
 432                 const struct lpddr2_addressing *addressing)
 433 {
 434         u32 tim1 = 0, val = 0;
 435
 436         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 437         tim1 = val << T_WTR_SHIFT;
 438
 439         /*
 440          * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
 441          * to tFAW for de-rating
 442          */
 443         if (addressing->num_banks == B8) {
 444                 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
 445         } else {
 446                 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
 447                 val = max(min_tck->tRRD, val) - 1;
 448         }
 449         tim1 |= val << T_RRD_SHIFT;
 450
 451         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
 452         tim1 |= (val - 1) << T_RC_SHIFT;
 453
 454         val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
 455         val = max(min_tck->tRASmin, val) - 1;
 456         tim1 |= val << T_RAS_SHIFT;
 457
 458         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 459         tim1 |= val << T_WR_SHIFT;
 460
 461         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
 462         tim1 |= (val - 1) << T_RCD_SHIFT;
 463
 464         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
 465         tim1 |= (val - 1) << T_RP_SHIFT;
 466
 467         return tim1;
 468 }
 469
 470 static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
 471                 const struct lpddr2_min_tck *min_tck,
 472                 const struct lpddr2_addressing *addressing,
 473                 u32 type)
 474 {
 475         u32 tim2 = 0, val = 0;
 476
 477         val = min_tck->tCKE - 1;
 478         tim2 |= val << T_CKE_SHIFT;
 479
 480         val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
 481         tim2 |= val << T_RTP_SHIFT;
 482
 483         /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
 484         val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
 485         tim2 |= val << T_XSNR_SHIFT;
 486
 487         /* XSRD same as XSNR for LPDDR2 */
 488         tim2 |= val << T_XSRD_SHIFT;
 489
 490         val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
 491         tim2 |= val << T_XP_SHIFT;
 492
 493         return tim2;
 494 }
 495
 496 static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
 497                 const struct lpddr2_min_tck *min_tck,
 498                 const struct lpddr2_addressing *addressing,
 499                 u32 type, u32 ip_rev, u32 derated)
 500 {
 501         u32 tim3 = 0, val = 0, t_dqsck;
 502
 503         val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
 504         val = val > 0xF ? 0xF : val;
 505         tim3 |= val << T_RAS_MAX_SHIFT;
 506
 507         val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
 508         tim3 |= val << T_RFC_SHIFT;
 509
 510         t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
 511                 timings->tDQSCK_max_derated : timings->tDQSCK_max;
 512         if (ip_rev == EMIF_4D5)
 513                 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
 514         else
 515                 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
 516
 517         tim3 |= val << T_TDQSCKMAX_SHIFT;
 518
 519         val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
 520         tim3 |= val << ZQ_ZQCS_SHIFT;
 521
 522         val = DIV_ROUND_UP(timings->tCKESR, t_ck);
 523         val = max(min_tck->tCKESR, val) - 1;
 524         tim3 |= val << T_CKESR_SHIFT;
 525
 526         if (ip_rev == EMIF_4D5) {
 527                 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
 528
 529                 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
 530                 tim3 |= val << T_PDLL_UL_SHIFT;
 531         }
 532
 533         return tim3;
 534 }
 535
 536 static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
 537                 bool cs1_used, bool cal_resistors_per_cs)
 538 {
 539         u32 zq = 0, val = 0;
 540
 541         val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
 542         zq |= val << ZQ_REFINTERVAL_SHIFT;
 543
 544         val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
 545         zq |= val << ZQ_ZQCL_MULT_SHIFT;
 546
 547         val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
 548         zq |= val << ZQ_ZQINIT_MULT_SHIFT;
 549
 550         zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
 551
 552         if (cal_resistors_per_cs)
 553                 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
 554         else
 555                 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
 556
 557         zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
 558
 559         val = cs1_used ? 1 : 0;
 560         zq |= val << ZQ_CS1EN_SHIFT;
 561
 562         return zq;
 563 }
 564
 565 static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
 566                 const struct emif_custom_configs *custom_configs, bool cs1_used,
 567                 u32 sdram_io_width, u32 emif_bus_width)
 568 {
 569         u32 alert = 0, interval, devcnt;
 570
 571         if (custom_configs && (custom_configs->mask &
 572                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
 573                 interval = custom_configs->temp_alert_poll_interval_ms;
 574         else
 575                 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
 576
 577         interval *= 1000000;                    /* Convert to ns */
 578         interval /= addressing->tREFI_ns;       /* Convert to refresh cycles */
 579         alert |= (interval << TA_REFINTERVAL_SHIFT);
 580
 581         /*
 582          * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
 583          * also to this form and subtract to get TA_DEVCNT, which is
 584          * in log2(x) form.
 585          */
 586         emif_bus_width = __fls(emif_bus_width) - 1;
 587         devcnt = emif_bus_width - sdram_io_width;
 588         alert |= devcnt << TA_DEVCNT_SHIFT;
 589
 590         /* DEVWDT is in 'log2(x) - 3' form */
 591         alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
 592
 593         alert |= 1 << TA_SFEXITEN_SHIFT;
 594         alert |= 1 << TA_CS0EN_SHIFT;
 595         alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
 596
 597         return alert;
 598 }
 599
 600 static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
 601 {
 602         u32 idle = 0, val = 0;
 603
 604         /*
 605          * Maximum value in normal conditions and increased frequency
 606          * when voltage is ramping
 607          */
 608         if (volt_ramp)
 609                 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
 610         else
 611                 val = 0x1FF;
 612
 613         /*
 614          * READ_IDLE_CTRL register in EMIF4D has same offset and fields
 615          * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
 616          */
 617         idle |= val << DLL_CALIB_INTERVAL_SHIFT;
 618         idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
 619
 620         return idle;
 621 }
 622
 623 static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
 624 {
 625         u32 calib = 0, val = 0;
 626
 627         if (volt_ramp == DDR_VOLTAGE_RAMPING)
 628                 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
 629         else
 630                 val = 0; /* Disabled when voltage is stable */
 631
 632         calib |= val << DLL_CALIB_INTERVAL_SHIFT;
 633         calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
 634
 635         return calib;
 636 }
 637
 638 static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
 639         u32 freq, u8 RL)
 640 {
 641         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
 642
 643         val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
 644         phy |= val << READ_LATENCY_SHIFT_4D;
 645
 646         if (freq <= 100000000)
 647                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
 648         else if (freq <= 200000000)
 649                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
 650         else
 651                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
 652
 653         phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
 654
 655         return phy;
 656 }
 657
 658 static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
 659 {
 660         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
 661
 662         /*
 663          * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
 664          * half-delay is not needed else set half-delay
 665          */
 666         if (freq >= 265000000 && freq < 267000000)
 667                 half_delay = 0;
 668         else
 669                 half_delay = 1;
 670
 671         phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
 672         phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
 673                         t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
 674
 675         return phy;
 676 }
 677
 678 static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
 679 {
 680         u32 fifo_we_slave_ratio;
 681
 682         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 683                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 684
 685         return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
 686                 fifo_we_slave_ratio << 22;
 687 }
 688
 689 static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
 690 {
 691         u32 fifo_we_slave_ratio;
 692
 693         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 694                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 695
 696         return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
 697                 fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
 698 }
 699
 700 static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
 701 {
 702         u32 fifo_we_slave_ratio;
 703
 704         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 705                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 706
 707         return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
 708                 fifo_we_slave_ratio << 13;
 709 }
 710
 711 static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
 712 {
 713         u32 pwr_mgmt_ctrl       = 0, timeout;
 714         u32 lpmode              = EMIF_LP_MODE_SELF_REFRESH;
 715         u32 timeout_perf        = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
 716         u32 timeout_pwr         = EMIF_LP_MODE_TIMEOUT_POWER;
 717         u32 freq_threshold      = EMIF_LP_MODE_FREQ_THRESHOLD;
 718
 719         struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
 720
 721         if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
 722                 lpmode          = cust_cfgs->lpmode;
 723                 timeout_perf    = cust_cfgs->lpmode_timeout_performance;
 724                 timeout_pwr     = cust_cfgs->lpmode_timeout_power;
 725                 freq_threshold  = cust_cfgs->lpmode_freq_threshold;
 726         }
 727
 728         /* Timeout based on DDR frequency */
 729         timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
 730
 731         /* The value to be set in register is "log2(timeout) - 3" */
 732         if (timeout < 16) {
 733                 timeout = 0;
 734         } else {
 735                 timeout = __fls(timeout) - 3;
 736                 if (timeout & (timeout - 1))
 737                         timeout++;
 738         }
 739
 740         switch (lpmode) {
 741         case EMIF_LP_MODE_CLOCK_STOP:
 742                 pwr_mgmt_ctrl = (timeout << CS_TIM_SHIFT) |
 743                                         SR_TIM_MASK | PD_TIM_MASK;
 744                 break;
 745         case EMIF_LP_MODE_SELF_REFRESH:
 746                 /* Workaround for errata i735 */
 747                 if (timeout < 6)
 748                         timeout = 6;
 749
 750                 pwr_mgmt_ctrl = (timeout << SR_TIM_SHIFT) |
 751                                         CS_TIM_MASK | PD_TIM_MASK;
 752                 break;
 753         case EMIF_LP_MODE_PWR_DN:
 754                 pwr_mgmt_ctrl = (timeout << PD_TIM_SHIFT) |
 755                                         CS_TIM_MASK | SR_TIM_MASK;
 756                 break;
 757         case EMIF_LP_MODE_DISABLE:
 758         default:
 759                 pwr_mgmt_ctrl = CS_TIM_MASK |
 760                                         PD_TIM_MASK | SR_TIM_MASK;
 761         }
 762
 763         /* No CS_TIM in EMIF_4D5 */
 764         if (ip_rev == EMIF_4D5)
 765                 pwr_mgmt_ctrl &= ~CS_TIM_MASK;
 766
 767         pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
 768
 769         return pwr_mgmt_ctrl;
 770 }
 771
 772 /*
 773  * Get the temperature level of the EMIF instance:
 774  * Reads the MR4 register of attached SDRAM parts to find out the temperature
 775  * level. If there are two parts attached(one on each CS), then the temperature
 776  * level for the EMIF instance is the higher of the two temperatures.
 777  */
 778 static void get_temperature_level(struct emif_data *emif)
 779 {
 780         u32             temp, temperature_level;
 781         void __iomem    *base;
 782
 783         base = emif->base;
 784
 785         /* Read mode register 4 */
 786         writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 787         temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 788         temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
 789                                 MR4_SDRAM_REF_RATE_SHIFT;
 790
 791         if (emif->plat_data->device_info->cs1_used) {
 792                 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 793                 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 794                 temp = (temp & MR4_SDRAM_REF_RATE_MASK)
 795                                 >> MR4_SDRAM_REF_RATE_SHIFT;
 796                 temperature_level = max(temp, temperature_level);
 797         }
 798
 799         /* treat everything less than nominal(3) in MR4 as nominal */
 800         if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
 801                 temperature_level = SDRAM_TEMP_NOMINAL;
 802
 803         /* if we get reserved value in MR4 persist with the existing value */
 804         if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
 805                 emif->temperature_level = temperature_level;
 806 }
 807
 808 /*
 809  * Program EMIF shadow registers that are not dependent on temperature
 810  * or voltage
 811  */
 812 static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
 813 {
 814         void __iomem    *base = emif->base;
 815
 816         writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
 817         writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
 818
 819         /* Settings specific for EMIF4D5 */
 820         if (emif->plat_data->ip_rev != EMIF_4D5)
 821                 return;
 822         writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
 823         writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
 824         writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
 825 }
 826
 827 /*
 828  * When voltage ramps dll calibration and forced read idle should
 829  * happen more often
 830  */
 831 static void setup_volt_sensitive_regs(struct emif_data *emif,
 832                 struct emif_regs *regs, u32 volt_state)
 833 {
 834         u32             calib_ctrl;
 835         void __iomem    *base = emif->base;
 836
 837         /*
 838          * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
 839          * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
 840          * is an alias of the respective read_idle_ctrl_shdw_* (members of
 841          * a union). So, the below code takes care of both cases
 842          */
 843         if (volt_state == DDR_VOLTAGE_RAMPING)
 844                 calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
 845         else
 846                 calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
 847
 848         writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
 849 }
 850
 851 /*
 852  * setup_temperature_sensitive_regs() - set the timings for temperature
 853  * sensitive registers. This happens once at initialisation time based
 854  * on the temperature at boot time and subsequently based on the temperature
 855  * alert interrupt. Temperature alert can happen when the temperature
 856  * increases or drops. So this function can have the effect of either
 857  * derating the timings or going back to nominal values.
 858  */
 859 static void setup_temperature_sensitive_regs(struct emif_data *emif,
 860                 struct emif_regs *regs)
 861 {
 862         u32             tim1, tim3, ref_ctrl, type;
 863         void __iomem    *base = emif->base;
 864         u32             temperature;
 865
 866         type = emif->plat_data->device_info->type;
 867
 868         tim1 = regs->sdram_tim1_shdw;
 869         tim3 = regs->sdram_tim3_shdw;
 870         ref_ctrl = regs->ref_ctrl_shdw;
 871
 872         /* No de-rating for non-lpddr2 devices */
 873         if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
 874                 goto out;
 875
 876         temperature = emif->temperature_level;
 877         if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
 878                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 879         } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
 880                 tim1 = regs->sdram_tim1_shdw_derated;
 881                 tim3 = regs->sdram_tim3_shdw_derated;
 882                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 883         }
 884
 885 out:
 886         writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
 887         writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
 888         writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
 889 }
 890
 891 static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
 892 {
 893         u32             old_temp_level;
 894         irqreturn_t     ret = IRQ_HANDLED;
 895
 896         spin_lock_irqsave(&emif_lock, irq_state);
 897         old_temp_level = emif->temperature_level;
 898         get_temperature_level(emif);
 899
 900         if (unlikely(emif->temperature_level == old_temp_level)) {
 901                 goto out;
 902         } else if (!emif->curr_regs) {
 903                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
 904                 goto out;
 905         }
 906
 907         if (emif->temperature_level < old_temp_level ||
 908                 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
 909                 /*
 910                  * Temperature coming down - defer handling to thread OR
 911                  * Temperature far too high - do kernel_power_off() from
 912                  * thread context
 913                  */
 914                 ret = IRQ_WAKE_THREAD;
 915         } else {
 916                 /* Temperature is going up - handle immediately */
 917                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
 918                 do_freq_update();
 919         }
 920
 921 out:
 922         spin_unlock_irqrestore(&emif_lock, irq_state);
 923         return ret;
 924 }
 925
 926 static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
 927 {
 928         u32                     interrupts;
 929         struct emif_data        *emif = dev_id;
 930         void __iomem            *base = emif->base;
 931         struct device           *dev = emif->dev;
 932         irqreturn_t             ret = IRQ_HANDLED;
 933
 934         /* Save the status and clear it */
 935         interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 936         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 937
 938         /*
 939          * Handle temperature alert
 940          * Temperature alert should be same for all ports
 941          * So, it's enough to process it only for one of the ports
 942          */
 943         if (interrupts & TA_SYS_MASK)
 944                 ret = handle_temp_alert(base, emif);
 945
 946         if (interrupts & ERR_SYS_MASK)
 947                 dev_err(dev, "Access error from SYS port - %x\n", interrupts);
 948
 949         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
 950                 /* Save the status and clear it */
 951                 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
 952                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
 953
 954                 if (interrupts & ERR_LL_MASK)
 955                         dev_err(dev, "Access error from LL port - %x\n",
 956                                 interrupts);
 957         }
 958
 959         return ret;
 960 }
 961
 962 static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
 963 {
 964         struct emif_data        *emif = dev_id;
 965
 966         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
 967                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
 968                 kernel_power_off();
 969                 return IRQ_HANDLED;
 970         }
 971
 972         spin_lock_irqsave(&emif_lock, irq_state);
 973
 974         if (emif->curr_regs) {
 975                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
 976                 do_freq_update();
 977         } else {
 978                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
 979         }
 980
 981         spin_unlock_irqrestore(&emif_lock, irq_state);
 982
 983         return IRQ_HANDLED;
 984 }
 985
 986 static void clear_all_interrupts(struct emif_data *emif)
 987 {
 988         void __iomem    *base = emif->base;
 989
 990         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
 991                 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
 992         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
 993                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
 994                         base + EMIF_LL_OCP_INTERRUPT_STATUS);
 995 }
 996
 997 static void disable_and_clear_all_interrupts(struct emif_data *emif)
 998 {
 999         void __iomem            *base = emif->base;
1000
1001         /* Disable all interrupts */
1002         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
1003                 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
1004         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1005                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
1006                         base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
1007
1008         /* Clear all interrupts */
1009         clear_all_interrupts(emif);
1010 }
1011
1012 static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
1013 {
1014         u32             interrupts, type;
1015         void __iomem    *base = emif->base;
1016
1017         type = emif->plat_data->device_info->type;
1018
1019         clear_all_interrupts(emif);
1020
1021         /* Enable interrupts for SYS interface */
1022         interrupts = EN_ERR_SYS_MASK;
1023         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
1024                 interrupts |= EN_TA_SYS_MASK;
1025         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
1026
1027         /* Enable interrupts for LL interface */
1028         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1029                 /* TA need not be enabled for LL */
1030                 interrupts = EN_ERR_LL_MASK;
1031                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
1032         }
1033
1034         /* setup IRQ handlers */
1035         return devm_request_threaded_irq(emif->dev, irq,
1036                                     emif_interrupt_handler,
1037                                     emif_threaded_isr,
1038                                     0, dev_name(emif->dev),
1039                                     emif);
1040
1041 }
1042
1043 static void __init_or_module emif_onetime_settings(struct emif_data *emif)
1044 {
1045         u32                             pwr_mgmt_ctrl, zq, temp_alert_cfg;
1046         void __iomem                    *base = emif->base;
1047         const struct lpddr2_addressing  *addressing;
1048         const struct ddr_device_info    *device_info;
1049
1050         device_info = emif->plat_data->device_info;
1051         addressing = get_addressing_table(device_info);
1052
1053         /*
1054          * Init power management settings
1055          * We don't know the frequency yet. Use a high frequency
1056          * value for a conservative timeout setting
1057          */
1058         pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
1059                         emif->plat_data->ip_rev);
1060         emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
1061         writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
1062
1063         /* Init ZQ calibration settings */
1064         zq = get_zq_config_reg(addressing, device_info->cs1_used,
1065                 device_info->cal_resistors_per_cs);
1066         writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
1067
1068         /* Check temperature level temperature level*/
1069         get_temperature_level(emif);
1070         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
1071                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1072
1073         /* Init temperature polling */
1074         temp_alert_cfg = get_temp_alert_config(addressing,
1075                 emif->plat_data->custom_configs, device_info->cs1_used,
1076                 device_info->io_width, get_emif_bus_width(emif));
1077         writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
1078
1079         /*
1080          * Program external PHY control registers that are not frequency
1081          * dependent
1082          */
1083         if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
1084                 return;
1085         writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
1086         writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
1087         writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
1088         writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
1089         writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
1090         writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
1091         writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
1092         writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
1093         writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
1094         writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
1095         writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
1096         writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
1097         writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
1098         writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
1099         writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
1100         writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
1101         writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
1102         writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
1103         writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
1104         writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
1105         writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
1106 }
1107
1108 static void get_default_timings(struct emif_data *emif)
1109 {
1110         struct emif_platform_data *pd = emif->plat_data;
1111
1112         pd->timings             = lpddr2_jedec_timings;
1113         pd->timings_arr_size    = ARRAY_SIZE(lpddr2_jedec_timings);
1114
1115         dev_warn(emif->dev, "%s: using default timings\n", __func__);
1116 }
1117
1118 static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
1119                 u32 ip_rev, struct device *dev)
1120 {
1121         int valid;
1122
1123         valid = (type == DDR_TYPE_LPDDR2_S4 ||
1124                         type == DDR_TYPE_LPDDR2_S2)
1125                 && (density >= DDR_DENSITY_64Mb
1126                         && density <= DDR_DENSITY_8Gb)
1127                 && (io_width >= DDR_IO_WIDTH_8
1128                         && io_width <= DDR_IO_WIDTH_32);
1129
1130         /* Combinations of EMIF and PHY revisions that we support today */
1131         switch (ip_rev) {
1132         case EMIF_4D:
1133                 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
1134                 break;
1135         case EMIF_4D5:
1136                 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
1137                 break;
1138         default:
1139                 valid = 0;
1140         }
1141
1142         if (!valid)
1143                 dev_err(dev, "%s: invalid DDR details\n", __func__);
1144         return valid;
1145 }
1146
1147 static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
1148                 struct device *dev)
1149 {
1150         int valid = 1;
1151
1152         if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
1153                 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
1154                 valid = cust_cfgs->lpmode_freq_threshold &&
1155                         cust_cfgs->lpmode_timeout_performance &&
1156                         cust_cfgs->lpmode_timeout_power;
1157
1158         if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
1159                 valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
1160
1161         if (!valid)
1162                 dev_warn(dev, "%s: invalid custom configs\n", __func__);
1163
1164         return valid;
1165 }
1166
1167 #if defined(CONFIG_OF)
1168 static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
1169                 struct emif_data *emif)
1170 {
1171         struct emif_custom_configs      *cust_cfgs = NULL;
1172         int                             len;
1173         const int                       *lpmode, *poll_intvl;
1174
1175         lpmode = of_get_property(np_emif, "low-power-mode", &len);
1176         poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
1177
1178         if (lpmode || poll_intvl)
1179                 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
1180                         GFP_KERNEL);
1181
1182         if (!cust_cfgs)
1183                 return;
1184
1185         if (lpmode) {
1186                 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
1187                 cust_cfgs->lpmode = *lpmode;
1188                 of_property_read_u32(np_emif,
1189                                 "low-power-mode-timeout-performance",
1190                                 &cust_cfgs->lpmode_timeout_performance);
1191                 of_property_read_u32(np_emif,
1192                                 "low-power-mode-timeout-power",
1193                                 &cust_cfgs->lpmode_timeout_power);
1194                 of_property_read_u32(np_emif,
1195                                 "low-power-mode-freq-threshold",
1196                                 &cust_cfgs->lpmode_freq_threshold);
1197         }
1198
1199         if (poll_intvl) {
1200                 cust_cfgs->mask |=
1201                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
1202                 cust_cfgs->temp_alert_poll_interval_ms = *poll_intvl;
1203         }
1204
1205         if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
1206                 devm_kfree(emif->dev, cust_cfgs);
1207                 return;
1208         }
1209
1210         emif->plat_data->custom_configs = cust_cfgs;
1211 }
1212
1213 static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
1214                 struct device_node *np_ddr,
1215                 struct ddr_device_info *dev_info)
1216 {
1217         u32 density = 0, io_width = 0;
1218         int len;
1219
1220         if (of_find_property(np_emif, "cs1-used", &len))
1221                 dev_info->cs1_used = true;
1222
1223         if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
1224                 dev_info->cal_resistors_per_cs = true;
1225
1226         if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4"))
1227                 dev_info->type = DDR_TYPE_LPDDR2_S4;
1228         else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2"))
1229                 dev_info->type = DDR_TYPE_LPDDR2_S2;
1230
1231         of_property_read_u32(np_ddr, "density", &density);
1232         of_property_read_u32(np_ddr, "io-width", &io_width);
1233
1234         /* Convert from density in Mb to the density encoding in jedc_ddr.h */
1235         if (density & (density - 1))
1236                 dev_info->density = 0;
1237         else
1238                 dev_info->density = __fls(density) - 5;
1239
1240         /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
1241         if (io_width & (io_width - 1))
1242                 dev_info->io_width = 0;
1243         else
1244                 dev_info->io_width = __fls(io_width) - 1;
1245 }
1246
1247 static struct emif_data * __init_or_module of_get_memory_device_details(
1248                 struct device_node *np_emif, struct device *dev)
1249 {
1250         struct emif_data                *emif = NULL;
1251         struct ddr_device_info          *dev_info = NULL;
1252         struct emif_platform_data       *pd = NULL;
1253         struct device_node              *np_ddr;
1254         int                             len;
1255
1256         np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
1257         if (!np_ddr)
1258                 goto error;
1259         emif    = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
1260         pd      = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1261         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1262
1263         if (!emif || !pd || !dev_info) {
1264                 dev_err(dev, "%s: Out of memory!!\n",
1265                         __func__);
1266                 goto error;
1267         }
1268
1269         emif->plat_data         = pd;
1270         pd->device_info         = dev_info;
1271         emif->dev               = dev;
1272         emif->np_ddr            = np_ddr;
1273         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1274
1275         if (of_device_is_compatible(np_emif, "ti,emif-4d"))
1276                 emif->plat_data->ip_rev = EMIF_4D;
1277         else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
1278                 emif->plat_data->ip_rev = EMIF_4D5;
1279
1280         of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
1281
1282         if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
1283                 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
1284
1285         of_get_ddr_info(np_emif, np_ddr, dev_info);
1286         if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
1287                         pd->device_info->io_width, pd->phy_type, pd->ip_rev,
1288                         emif->dev)) {
1289                 dev_err(dev, "%s: invalid device data!!\n", __func__);
1290                 goto error;
1291         }
1292         /*
1293          * For EMIF instances other than EMIF1 see if the devices connected
1294          * are exactly same as on EMIF1(which is typically the case). If so,
1295          * mark it as a duplicate of EMIF1. This will save some memory and
1296          * computation.
1297          */
1298         if (emif1 && emif1->np_ddr == np_ddr) {
1299                 emif->duplicate = true;
1300                 goto out;
1301         } else if (emif1) {
1302                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1303                         __func__);
1304         }
1305
1306         of_get_custom_configs(np_emif, emif);
1307         emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
1308                                         emif->plat_data->device_info->type,
1309                                         &emif->plat_data->timings_arr_size);
1310
1311         emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
1312         goto out;
1313
1314 error:
1315         return NULL;
1316 out:
1317         return emif;
1318 }
1319
1320 #else
1321
1322 static struct emif_data * __init_or_module of_get_memory_device_details(
1323                 struct device_node *np_emif, struct device *dev)
1324 {
1325         return NULL;
1326 }
1327 #endif
1328
1329 static struct emif_data *__init_or_module get_device_details(
1330                 struct platform_device *pdev)
1331 {
1332         u32                             size;
1333         struct emif_data                *emif = NULL;
1334         struct ddr_device_info          *dev_info;
1335         struct emif_custom_configs      *cust_cfgs;
1336         struct emif_platform_data       *pd;
1337         struct device                   *dev;
1338         void                            *temp;
1339
1340         pd = pdev->dev.platform_data;
1341         dev = &pdev->dev;
1342
1343         if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
1344                         pd->device_info->density, pd->device_info->io_width,
1345                         pd->phy_type, pd->ip_rev, dev))) {
1346                 dev_err(dev, "%s: invalid device data\n", __func__);
1347                 goto error;
1348         }
1349
1350         emif    = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
1351         temp    = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1352         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1353
1354         if (!emif || !pd || !dev_info) {
1355                 dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
1356                 goto error;
1357         }
1358
1359         memcpy(temp, pd, sizeof(*pd));
1360         pd = temp;
1361         memcpy(dev_info, pd->device_info, sizeof(*dev_info));
1362
1363         pd->device_info         = dev_info;
1364         emif->plat_data         = pd;
1365         emif->dev               = dev;
1366         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1367
1368         /*
1369          * For EMIF instances other than EMIF1 see if the devices connected
1370          * are exactly same as on EMIF1(which is typically the case). If so,
1371          * mark it as a duplicate of EMIF1 and skip copying timings data.
1372          * This will save some memory and some computation later.
1373          */
1374         emif->duplicate = emif1 && (memcmp(dev_info,
1375                 emif1->plat_data->device_info,
1376                 sizeof(struct ddr_device_info)) == 0);
1377
1378         if (emif->duplicate) {
1379                 pd->timings = NULL;
1380                 pd->min_tck = NULL;
1381                 goto out;
1382         } else if (emif1) {
1383                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1384                         __func__);
1385         }
1386
1387         /*
1388          * Copy custom configs - ignore allocation error, if any, as
1389          * custom_configs is not very critical
1390          */
1391         cust_cfgs = pd->custom_configs;
1392         if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
1393                 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
1394                 if (temp)
1395                         memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
1396                 else
1397                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1398                                 __LINE__);
1399                 pd->custom_configs = temp;
1400         }
1401
1402         /*
1403          * Copy timings and min-tck values from platform data. If it is not
1404          * available or if memory allocation fails, use JEDEC defaults
1405          */
1406         size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
1407         if (pd->timings) {
1408                 temp = devm_kzalloc(dev, size, GFP_KERNEL);
1409                 if (temp) {
1410                         memcpy(temp, pd->timings, sizeof(*pd->timings));
1411                         pd->timings = temp;
1412                 } else {
1413                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1414                                 __LINE__);
1415                         get_default_timings(emif);
1416                 }
1417         } else {
1418                 get_default_timings(emif);
1419         }
1420
1421         if (pd->min_tck) {
1422                 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
1423                 if (temp) {
1424                         memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
1425                         pd->min_tck = temp;
1426                 } else {
1427                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1428                                 __LINE__);
1429                         pd->min_tck = &lpddr2_jedec_min_tck;
1430                 }
1431         } else {
1432                 pd->min_tck = &lpddr2_jedec_min_tck;
1433         }
1434
1435 out:
1436         return emif;
1437
1438 error:
1439         return NULL;
1440 }
1441
1442 static int __init_or_module emif_probe(struct platform_device *pdev)
1443 {
1444         struct emif_data        *emif;
1445         struct resource         *res;
1446         int                     irq;
1447
1448         if (pdev->dev.of_node)
1449                 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
1450         else
1451                 emif = get_device_details(pdev);
1452
1453         if (!emif) {
1454                 pr_err("%s: error getting device data\n", __func__);
1455                 goto error;
1456         }
1457
1458         list_add(&emif->node, &device_list);
1459         emif->addressing = get_addressing_table(emif->plat_data->device_info);
1460
1461         /* Save pointers to each other in emif and device structures */
1462         emif->dev = &pdev->dev;
1463         platform_set_drvdata(pdev, emif);
1464
1465         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1466         if (!res) {
1467                 dev_err(emif->dev, "%s: error getting memory resource\n",
1468                         __func__);
1469                 goto error;
1470         }
1471
1472         emif->base = devm_ioremap_resource(emif->dev, res);
1473         if (IS_ERR(emif->base))
1474                 goto error;
1475
1476         irq = platform_get_irq(pdev, 0);
1477         if (irq < 0) {
1478                 dev_err(emif->dev, "%s: error getting IRQ resource - %d\n",
1479                         __func__, irq);
1480                 goto error;
1481         }
1482
1483         emif_onetime_settings(emif);
1484         emif_debugfs_init(emif);
1485         disable_and_clear_all_interrupts(emif);
1486         setup_interrupts(emif, irq);
1487
1488         /* One-time actions taken on probing the first device */
1489         if (!emif1) {
1490                 emif1 = emif;
1491                 spin_lock_init(&emif_lock);
1492
1493                 /*
1494                  * TODO: register notifiers for frequency and voltage
1495                  * change here once the respective frameworks are
1496                  * available
1497                  */
1498         }
1499
1500         dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
1501                 __func__, emif->base, irq);
1502
1503         return 0;
1504 error:
1505         return -ENODEV;
1506 }
1507
1508 static int __exit emif_remove(struct platform_device *pdev)
1509 {
1510         struct emif_data *emif = platform_get_drvdata(pdev);
1511
1512         emif_debugfs_exit(emif);
1513
1514         return 0;
1515 }
1516
1517 static void emif_shutdown(struct platform_device *pdev)
1518 {
1519         struct emif_data        *emif = platform_get_drvdata(pdev);
1520
1521         disable_and_clear_all_interrupts(emif);
1522 }
1523
1524 static int get_emif_reg_values(struct emif_data *emif, u32 freq,
1525                 struct emif_regs *regs)
1526 {
1527         u32                             cs1_used, ip_rev, phy_type;
1528         u32                             cl, type;
1529         const struct lpddr2_timings     *timings;
1530         const struct lpddr2_min_tck     *min_tck;
1531         const struct ddr_device_info    *device_info;
1532         const struct lpddr2_addressing  *addressing;
1533         struct emif_data                *emif_for_calc;
1534         struct device                   *dev;
1535         const struct emif_custom_configs *custom_configs;
1536
1537         dev = emif->dev;
1538         /*
1539          * If the devices on this EMIF instance is duplicate of EMIF1,
1540          * use EMIF1 details for the calculation
1541          */
1542         emif_for_calc   = emif->duplicate ? emif1 : emif;
1543         timings         = get_timings_table(emif_for_calc, freq);
1544         addressing      = emif_for_calc->addressing;
1545         if (!timings || !addressing) {
1546                 dev_err(dev, "%s: not enough data available for %dHz",
1547                         __func__, freq);
1548                 return -1;
1549         }
1550
1551         device_info     = emif_for_calc->plat_data->device_info;
1552         type            = device_info->type;
1553         cs1_used        = device_info->cs1_used;
1554         ip_rev          = emif_for_calc->plat_data->ip_rev;
1555         phy_type        = emif_for_calc->plat_data->phy_type;
1556
1557         min_tck         = emif_for_calc->plat_data->min_tck;
1558         custom_configs  = emif_for_calc->plat_data->custom_configs;
1559
1560         set_ddr_clk_period(freq);
1561
1562         regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
1563         regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
1564                         addressing);
1565         regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
1566                         addressing, type);
1567         regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
1568                 addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
1569
1570         cl = get_cl(emif);
1571
1572         if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
1573                 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
1574                         timings, freq, cl);
1575         } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
1576                 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
1577                 regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
1578                 regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
1579                 regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
1580         } else {
1581                 return -1;
1582         }
1583
1584         /* Only timeout values in pwr_mgmt_ctrl_shdw register */
1585         regs->pwr_mgmt_ctrl_shdw =
1586                 get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
1587                 (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
1588
1589         if (ip_rev & EMIF_4D) {
1590                 regs->read_idle_ctrl_shdw_normal =
1591                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
1592
1593                 regs->read_idle_ctrl_shdw_volt_ramp =
1594                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1595         } else if (ip_rev & EMIF_4D5) {
1596                 regs->dll_calib_ctrl_shdw_normal =
1597                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
1598
1599                 regs->dll_calib_ctrl_shdw_volt_ramp =
1600                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1601         }
1602
1603         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
1604                 regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
1605                         addressing);
1606
1607                 regs->sdram_tim1_shdw_derated =
1608                         get_sdram_tim_1_shdw_derated(timings, min_tck,
1609                                 addressing);
1610
1611                 regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
1612                         min_tck, addressing, type, ip_rev,
1613                         EMIF_DERATED_TIMINGS);
1614         }
1615
1616         regs->freq = freq;
1617
1618         return 0;
1619 }
1620
1621 /*
1622  * get_regs() - gets the cached emif_regs structure for a given EMIF instance
1623  * given frequency(freq):
1624  *
1625  * As an optimisation, every EMIF instance other than EMIF1 shares the
1626  * register cache with EMIF1 if the devices connected on this instance
1627  * are same as that on EMIF1(indicated by the duplicate flag)
1628  *
1629  * If we do not have an entry corresponding to the frequency given, we
1630  * allocate a new entry and calculate the values
1631  *
1632  * Upon finding the right reg dump, save it in curr_regs. It can be
1633  * directly used for thermal de-rating and voltage ramping changes.
1634  */
1635 static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
1636 {
1637         int                     i;
1638         struct emif_regs        **regs_cache;
1639         struct emif_regs        *regs = NULL;
1640         struct device           *dev;
1641
1642         dev = emif->dev;
1643         if (emif->curr_regs && emif->curr_regs->freq == freq) {
1644                 dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
1645                 return emif->curr_regs;
1646         }
1647
1648         if (emif->duplicate)
1649                 regs_cache = emif1->regs_cache;
1650         else
1651                 regs_cache = emif->regs_cache;
1652
1653         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
1654                 if (regs_cache[i]->freq == freq) {
1655                         regs = regs_cache[i];
1656                         dev_dbg(dev,
1657                                 "%s: reg dump found in reg cache for %u Hz\n",
1658                                 __func__, freq);
1659                         break;
1660                 }
1661         }
1662
1663         /*
1664          * If we don't have an entry for this frequency in the cache create one
1665          * and calculate the values
1666          */
1667         if (!regs) {
1668                 regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
1669                 if (!regs)
1670                         return NULL;
1671
1672                 if (get_emif_reg_values(emif, freq, regs)) {
1673                         devm_kfree(emif->dev, regs);
1674                         return NULL;
1675                 }
1676
1677                 /*
1678                  * Now look for an un-used entry in the cache and save the
1679                  * newly created struct. If there are no free entries
1680                  * over-write the last entry
1681                  */
1682                 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
1683                         ;
1684
1685                 if (i >= EMIF_MAX_NUM_FREQUENCIES) {
1686                         dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
1687                                 __func__);
1688                         i = EMIF_MAX_NUM_FREQUENCIES - 1;
1689                         devm_kfree(emif->dev, regs_cache[i]);
1690                 }
1691                 regs_cache[i] = regs;
1692         }
1693
1694         return regs;
1695 }
1696
1697 static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
1698 {
1699         dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
1700                 volt_state);
1701
1702         if (!emif->curr_regs) {
1703                 dev_err(emif->dev,
1704                         "%s: volt-notify before registers are ready: %d\n",
1705                         __func__, volt_state);
1706                 return;
1707         }
1708
1709         setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
1710 }
1711
1712 /*
1713  * TODO: voltage notify handling should be hooked up to
1714  * regulator framework as soon as the necessary support
1715  * is available in mainline kernel. This function is un-used
1716  * right now.
1717  */
1718 static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
1719 {
1720         struct emif_data *emif;
1721
1722         spin_lock_irqsave(&emif_lock, irq_state);
1723
1724         list_for_each_entry(emif, &device_list, node)
1725                 do_volt_notify_handling(emif, volt_state);
1726         do_freq_update();
1727
1728         spin_unlock_irqrestore(&emif_lock, irq_state);
1729 }
1730
1731 static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
1732 {
1733         struct emif_regs *regs;
1734
1735         regs = get_regs(emif, new_freq);
1736         if (!regs)
1737                 return;
1738
1739         emif->curr_regs = regs;
1740
1741         /*
1742          * Update the shadow registers:
1743          * Temperature and voltage-ramp sensitive settings are also configured
1744          * in terms of DDR cycles. So, we need to update them too when there
1745          * is a freq change
1746          */
1747         dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
1748                 __func__, new_freq);
1749         setup_registers(emif, regs);
1750         setup_temperature_sensitive_regs(emif, regs);
1751         setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
1752
1753         /*
1754          * Part of workaround for errata i728. See do_freq_update()
1755          * for more details
1756          */
1757         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1758                 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
1759 }
1760
1761 /*
1762  * TODO: frequency notify handling should be hooked up to
1763  * clock framework as soon as the necessary support is
1764  * available in mainline kernel. This function is un-used
1765  * right now.
1766  */
1767 static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
1768 {
1769         struct emif_data *emif;
1770
1771         /*
1772          * NOTE: we are taking the spin-lock here and releases it
1773          * only in post-notifier. This doesn't look good and
1774          * Sparse complains about it, but this seems to be
1775          * un-avoidable. We need to lock a sequence of events
1776          * that is split between EMIF and clock framework.
1777          *
1778          * 1. EMIF driver updates EMIF timings in shadow registers in the
1779          *    frequency pre-notify callback from clock framework
1780          * 2. clock framework sets up the registers for the new frequency
1781          * 3. clock framework initiates a hw-sequence that updates
1782          *    the frequency EMIF timings synchronously.
1783          *
1784          * All these 3 steps should be performed as an atomic operation
1785          * vis-a-vis similar sequence in the EMIF interrupt handler
1786          * for temperature events. Otherwise, there could be race
1787          * conditions that could result in incorrect EMIF timings for
1788          * a given frequency
1789          */
1790         spin_lock_irqsave(&emif_lock, irq_state);
1791
1792         list_for_each_entry(emif, &device_list, node)
1793                 do_freq_pre_notify_handling(emif, new_freq);
1794 }
1795
1796 static void do_freq_post_notify_handling(struct emif_data *emif)
1797 {
1798         /*
1799          * Part of workaround for errata i728. See do_freq_update()
1800          * for more details
1801          */
1802         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1803                 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
1804 }
1805
1806 /*
1807  * TODO: frequency notify handling should be hooked up to
1808  * clock framework as soon as the necessary support is
1809  * available in mainline kernel. This function is un-used
1810  * right now.
1811  */
1812 static void __attribute__((unused)) freq_post_notify_handling(void)
1813 {
1814         struct emif_data *emif;
1815
1816         list_for_each_entry(emif, &device_list, node)
1817                 do_freq_post_notify_handling(emif);
1818
1819         /*
1820          * Lock is done in pre-notify handler. See freq_pre_notify_handling()
1821          * for more details
1822          */
1823         spin_unlock_irqrestore(&emif_lock, irq_state);
1824 }
1825
1826 #if defined(CONFIG_OF)
1827 static const struct of_device_id emif_of_match[] = {
1828                 { .compatible = "ti,emif-4d" },
1829                 { .compatible = "ti,emif-4d5" },
1830                 {},
1831 };
1832 MODULE_DEVICE_TABLE(of, emif_of_match);
1833 #endif
1834
1835 static struct platform_driver emif_driver = {
1836         .remove         = __exit_p(emif_remove),
1837         .shutdown       = emif_shutdown,
1838         .driver = {
1839                 .name = "emif",
1840                 .of_match_table = of_match_ptr(emif_of_match),
1841         },
1842 };
1843
1844 static int __init_or_module emif_register(void)
1845 {
1846         return platform_driver_probe(&emif_driver, emif_probe);
1847 }
1848
1849 static void __exit emif_unregister(void)
1850 {
1851         platform_driver_unregister(&emif_driver);
1852 }
1853
1854 module_init(emif_register);
1855 module_exit(emif_unregister);
1856 MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1857 MODULE_LICENSE("GPL");
1858 MODULE_ALIAS("platform:emif");
1859 MODULE_AUTHOR("Texas Instruments Inc");